Using the Xilinx Platform Studio (XPS)
Contents
1. debug module mdm 1 00 b d RS232_ Tl xps uartlite 1 00 ta lt gt clock generator O0 clock generator 2 00 a proc sys reset O sys reset 2 00 a D SRAM_util_bus_split_0 util_bus_split 1 00 a System Assembly View Block Diagram1 Figure 8 Rename xps_gpio_O to LEDs include lt xparameters h gt include lt xgpio h gt define WAIT_VAL 0x1000000 int delay void int main int count int count masked XGpio led XGpio Initialize amp led XPAR LEDS DEVICE ID XGpio_SetDataDirection amp led 1 0 count 0 while 1 count_masked count amp Oxf XGpio_DiscreteWrite amp led 1 count_masked ECEN 449 9 10 Laboratory Exercise 2 oru mzr mb mb v10 1 00 a i mb pib plb v46 1 02 a 9 9 dimb cntir mb bram if cntlr 2 10 a ilmb entir mb bram if cntlr 2 10 a v D SRAM xps mch emc 1 00 a i Imb_bram bram_block 1 00 a debug module mdm 1 00 b 3 9 LEDs xps gpio 1 00 a 9 amp RS232 Uart 1 No Connection xps uartlite 1 00 a clock v generator O aa E generator 2 00 a r wproc sys reset O mb_plb proc sys reset 2 00 a LO SRAM util bus soir 0 RE NES Dus bus spit Um 4 J System Assembly View Block Diagram Diagram1 Figure 9 Connect to PLB xil printf LEDs OxVxXn Vr count masked delay count j return 0 int delay void volatile int delay_count 0 while delay_count W2. c What does the while 1 expression in our code do d ECEN 449 Compare and contrast this lab with the previous lab Which implementation do you feel is easier What are the advantages and disadvantages associated with a purely software implementation such as this when compared to a purely hardware implementation such as the previous lab 13
3. hardcoded communication configurations are acceptable Also note that we 4 ECEN 449 Laboratory Exercise 2 5 select a target development board Select board would like to create a system for the following development board Board vendor Board name XUPVb5 LX110T Evaluation Platform Board revision A Note Visit the vendor website for additional board support materials Vendor s Website Contact Info Download Third Party Board Definition Files C would like to create a system for a custom board Maned nn mna mas Figure 4 Base System Builder Select Board are not using interrupts in this design k After specifying the peripherals connected to the PLB the Software Setup window Figure 6 will come up Uncheck Memory test and Peripheral selftest These are test applications that XPS will autogenerate for us We have no intentions of using them so we will not clutter up our project with them Note the first two fields in Figure 6 These point to the RS232 peripheral we specified previous for STDIN and STDOUT Essentially STDIN and STDNOUT link printf and scanf to the serial port on the XUP board The third field specifies where the boot code should be placed on the finished system Upon reset the microprocessor must know where to start executing code and this is that area of memory In our simple system the BRAMs are the only memories we have recall from the system diagram
4. 3 After modifying the ucf we must build our hardware system and generate the appropriate software ECEN 449 7 Laboratory Exercise 2 File Edit View Project Hardware Software Device Configuration Debug Simulation Window Help IDO e E i MA AE MM cB m3 fae f xo RSE MESE MEE EA x P L E Bus interfaces Ports Add 5 E EDK Install opt Xilinx Analog 1 Bus and Bridge i tf Clock Reset and Interrupt Communication High Sp Le ilmb ba P mb_plb 6 2 dimb_cntir 4 9 SRAM II Imb_bram debug module i Communication Low Sp i i DMA and Timer i FPGA Reconfiguration General Purpose IO II AS232_Uart_1 i clock_generator_0 i proc sys reset O lt gt SRAM util bus split O l Memory and Memon i m PCI View IP Modifications Change Log i H Peripheral Controller View PDF Datasheet H Processor i oh Utility x Assigned Driver gpio 2 11 a for instance xps gpio 0 xps gpio 0 has been added to the project Figure 7 Add XPS General Purpose IO libraries a b c Select Hardware Generate Netlist from the top menu of the XPS window This will take a few moments to complete as XPS synthesizes the various IP blocks in your system including the MicroBlaze processor and the GPIO module Once complete you will see Done in the output console at the bottom of the XPS window Next selec
5. aliveness and perform a basic read write test to each memory in your system Peripheral selftest Perform a simple self test for each peripheral in your system Figure 6 Software Setup for the SPLB_Clk port Set the net connection to sys clk s g We are almost done adding a GPIO IP to our microprocessor system Now we must specify an address range on the bus for our LEDs module To do this select the Addresses tab under the system assembly window Set the size field of LEDs to 64K and hit the Generate Addresses button This will adjust the address ranges for other IP blocks in our system Ensure there are no overlapping address h While under the Addresses tab change the sizes of both the dlmb_cntlr and ilmb_cntrl to 128K and regenerate the hardware addresses It turns out that 64K is not enough memory for our system when using printf in your application code 1 The final step is to modify the ucf to specify the pin locations of LEDs_ext Click on the Project tab in the upper left corner of the XPS window Locate the data system ucf file and double click on it In the editor window that appears append the following code to the ucf NET LEDS ext lt 0 gt LOC HIS NET LEDs ext l1 LOC Lis NET LEDS exc lt 2 gt LOC G15 NET LEDs exc lt 3 gt LOC AD26 Does this code snippet look familiar Be sure to save the ucf when you are done editing it
6. that the 1LMB controller connects directly to the BRAM 1 Hit Next to continue The System Created screen will provide you with a summary of the system BSB will setup for you Press Generate to go forward with your design Finally click Finish on the last prompt 2 Once the BSB completes we will have a blank system without the GPIO peripherals The following steps will now guide you through the process of adding a GPIO IP block to our microprocessor based system and connecting that block to the LEDs on the XUP board a In the upper left hand corner of the XPS window select the IP Catalog tab A list of IP categories will be displayed Expand the General Purpose IO category and right click on XPS ECEN 449 5 b Ne c d e f Laboratory Exercise 2 The following external memory and IO devices were found on your board Xilinx XUPV5 LX110T Evaluation Platform Revision A Please select the IO devices which you would like to use IO devices Rs232 Uart 1 Beripheral APS UARTLITE Baudrate bits per seconds 9600 I Data bits s y Parity NONE Use interrupt Data Sheet Rs232 Uat 2 Data Sheet Figure 5 RS232 Configuration General Purpose IO Then select Add IP Figure 7 XPS responds by adding an IP block called xps gpio O to the project This can be seen now in the System Assembly View under t
7. AIT VAL delay_count return 0 j b Look through the code you just wrote and try to understand what exactly is going on Notice we include the xparameters h and xgpio h header files These files are located in the microb laze O include directory under you lab2 project directory Open up these files and understand what they provide At the end of lab you will find questions on these files c Once system implementation is complete select the Applications tab in the upper left corner of the XPS window Then click on Add Software Application Project Enter lab2a for the Project Name and hit OK You should now see a lab2a application project show up in the 10 ECEN 449 Laboratory Exercise 2 1 Applications window d Expand lab2a and right click on Sources and select Add Existing Files Figure 10 Add the source file we just created and click OK Project Applications IP Catalog Software Projects 1 Add Software Application Project Le v Default microblaze 0 bootloop f Default microblaze 0 xmdstub j k Project lab2a Processor microblaze 0 gt Executable home atarghe1 Desktop ecen443 lab2 lab2a executable elf Compiler Options Sources k Add Existing Files Figure 10 Add Source File to lab2a e Right click on the lab2a application project and select Generate Linker Script In the resulting window cha
8. ECEN 449 Microprocessor System Design Department of Electrical and Computer Engineering Texas A amp M University Prof Peng Li TA Andrew Targhetta Lab exercises created by A Targhetta P Gratz Laboratory Exercise 2 Using the Xilinx Platform Studio XPS Objective The purpose of lab this week is to familiarize you with XPS by developing a software based solution for controlling the LEDs in a manner similar to that which was done last week in pure FPGA hardware To accomplish this goal you will be guided through the process of creating a MicroBlaze processor system using the XPS Base System Builder BSB You will then add General Purpose Input Output GPIO capa bilities to the microprocessor via Intellectual Property IP hardware blocks from Xilinx Finally you will create software using the C programming language which will run on the MicroBlaze processor inorder to implement the appropriate LED functionality System Overview The microprocessor system you will build in this lab is depicted in Figure 1 At the center of the diagram is the MicroBlaze soft IP processor Connected to it are two Local Memory Buses LMBs 1LMB and dLMB for instruction fetch and data access respectively Each LMB has its own block RAM BRAM controller which provides the interconnect logic between the MicroBlaze and BRAM local memory The Processor Local Bus PLB connects the MicroBlaze bus master to peripherals bus slaves external to the mic
9. f the DIP switches should be displayed The count should reset when you push the center push button The serial console should display the current action and LEDs value Hints 12 ECEN 449 Laboratory Exercise 2 13 When configuring the additional GPIO if you set the Channel 1 is input only field to TRUE be sure you connect the input signals to the GPIO_in port Skim through the user manual for the XUPV5 board to determine the pin assignments for addi tional signals The user manual may be found on the course website Do not forget to add the DIP switches and push buttons to your UCF before generating the netlist Your source code must detect a change on the push buttons and DIP switches and react ac cordingly When a change is detected print the current action and LEDs value to the terminal window Also print to the terminal everytime the LEDs value changes 3 4 points Answer the following questions a In the first part of lab we created a delay function by implementing a counter The goal was to update the LEDs approximately every second as we did in the previous lab Compare the count value in this lab to the count value you used as a delay in the previous lab If they different explain why Can you determine approximately how many clock cycles are required to execute one iteration of the delay for loop If so how many b Why is the count variable in our software delay declared as volatile
10. he Bus Interfaces tab Click on this IP module and rename it LEDs See Figure 8 Now right click on the GPIO module and select Configure IP Change GPIO Data Channel Width to 4 This will allow us to control four LEDs Leave GPIO Supports Interrupts and Enable Channel 2 unchecked Hit OK to continue In the Bus Interfaces tab expand LEDs and set the SPLB bus connection to mb_plb Fig ure 9 This will connect the GPIO module to the PLB Next click on the Ports tab under the system assembly window and expand LEDs Find the GPIO IO port and select Make External from the Net drop box This will create a 4 bit external port called LEDs_GPIO_IO Rename it LEDs_ext so we do not have to type as much when we modify the ucf At the top of the system assembly window with the Ports tab selected you will find a button called Filters Select that button and click on All Then navigate back to LEDs and look 6 ECEN 449 Laboratory Exercise 2 7 Base System Builder Software Setup Devices to use as standard input standard output and boot memory STDIN RAs232 Uar_1 m STDOUT HS232 LUart 1 Boot Memory imb_ontir sample application selection select the sample C application that you would like to have generated Each application will include a linker script Memory test Ilustrate system
11. m the top menu c If everything is correct you should see the LEDs on the XUP board count as seen in the lab before Note that you do not have to hold the up or down buttons in for the LEDs to count d To see the output of the printf statements in our code we must use kermit a serial console application on the CentOS machines Open a terminal window and type the following gt source homes faculty shared ECEN449 settings csh gt kermit l dev ttySO You should see the kermit prompt In kermit type the following C Kermit gt set speed 9600 C Kermit gt connect If everything is correct you will see text being printed to the serial console Demostrate your progress to the TA Deliverables 1 4 points Demonstrate your work to the TA after downloading the bitstream for the design created using the steps provided in the manual Add comments to your C code and the modified portion of the ucf file and include them in your lab write up 2 12 points Add an 9 bit GPIO IP block to your system and connect the lower 4 bits to the DIP switchs and the upper 5 bits to the push buttons on the XUP board Then develop software to implement the following functionality When the North push button is pressed the LEDs should count up When the South push button is pressed the LEDs should count down When the West push button is pressed the current count should be displayed on the LEDs When the East push but ton is pressed the status o
12. nge the Heap and Stack fields to 0x4000 If we had other physical regions of memory other than the BRAM this is where we would specify where exactly to place our application code Click OK to generate the linker script f Right click on the lab2a application project again and select Build Project Correct any errors in the build process g Once again right click on the lab2a application project and select Mark to Initialize BRAMs This tells XPS to initialize the BRAM memory with the lab2a application Ensure the projects other than lab2a are not marked to initialize in BRAM 5 At this point both the hardware and software have been created We will now use XPS to create a bitstream and load it onto the FPGA You should have noticed that the code includes printf statements ECEN 449 11 12 Laboratory Exercise 2 The output of those statements are directed to the rs232 port and we will use a serial console on the CentOS machines to display them a In the top menu select Device Configuration Update Bitstream This will combine the hard ware bitstream created earlier with the BRAM initialization bitstream taken from the executable and linkable format elf file The result is an download bit file stored in the implementation directory under your lab2 directory b Ensure the XUP board is turned on To download the bitstream to the FPGA select Device Configuration Download Bitstream fro
13. on Platform Board revision A Leave I would like to create a system for a custom board unselected and press Next to go to the next screen Now you should get the Select Processor window Accept the defaults in which Use stepping is unselected and the MicroBlaze processor is selected Note that the PowerPC is not an option for this FPGA It is a hard IP processor included on some high end Virtex 5 FPGAs and many pre Virtex 5 FPGAs such as the Virtex II Before pressing Next please take a moment to read the Processor description for the MicroBlaze In the Configure MicroBlaze Processor window leave the Processor Bus clock at 125Mhz keep the Debug I F field on default and leave Local memory set to 8 KB We will end up changing this later on in the lab however the drop box here only goes up to 64K B and we need 128KB Try to understand what the rest of the options mean but leave them as default as well The next five BSB steps are for configuring the peripherals connected to our Processor Local Bus PLB Uncheck everything except the RS232 Uart 1 and leave its configuration as default Notice the RS232 peripheral is called XPS UARTLITE This name refers to the fact that it is light weight requiring very little FPGA logic Compared to the other option the XPS UART16550 the communication settings are hardcoded i e determined at hardware synthesis time For this lab
14. roprocessor Typically included in the list of peripherals are the debugger module and a Universal Asynchronous Receiver Transmitter UART The debugger allows XPS to interact with the MicroBlaze 2 Laboratory Exercise 2 processor after the FPGA has been programmed This is useful for initializing regions of memory outside of the FPGA and for general software debugging The UART is used for RS232 communication which will be our primary method of communicating with the microprocessor for the next few labs The GPIO blocks provide the microprocessor with a means of controlling the LEDs and reading user input from the DIP switches and push buttons PLB Debug JTAG Block RAM BRAM Cntir BRAM Cntir iLBM dLBM UART RS232 GPIO LEDs MicroBlaze Processor Switches GPIO Push Buttons Figure 1 MicroBlaze System Diagram Procedure 1 Launch Platform Studio and run Base System Builder BSB a Before beginning create a directory in your home folder for today s lab Try to avoid spaces and special characters in the directory name as they have the potential for causing problems during 2 ECEN 449 Laboratory Exercise 2 3 the system build process You may use the mkdir command in an open terminal to create a directory b Next type the following commands in the terminal window gt source homes faculty shared ECEN449 settings csh gt xps The former will setup the environment for XPS and kermit a serial con
15. sole required for lab this week c Once XPS comes up select Base System Builder wizard in first prompt Figure 2 Hit OK to continue Xilinx Platform Studio Create new or open existing project Y C Open a recent project Browse for More Projects Browse installed EDK examples projects here cora oe Figure 2 Begin Base System Builder d In the next window Figure 3 define the Project file as system xmp within your project directory created in step 1 a e In the same window check Set Project Peripheral Repositories and hit Browse to set homes faculty shared ECEN449 EDK XUPV5 LX110T Pack lib as the project peripheral repositories for this lab Hit OK to proceed f At this point the BSB welcome window appears Select I would like to create a new design and hit Next to start BSB with a blank design g The Select Board window Figure 4 will now come up Set the following fields before contin uing ECEN 449 3 h G Laboratory Exercise 2 Create New XPS Project Using BSB Wizard x New project Project file homes adt3508 ecen443 lab2 system xmp Browse Advanced options optional F1 for help M Set Project Peripheral Repositories 3508 ecen443 EDK XUP V5 LX110T Pack lib Browse Figure 3 Project file and Project Peripheral Repositories Board vendor Xilinx Board name XUPV5 LX110T Evaluati
16. t Software Generate Libraries and BSPs from the top menu This operation will complete much faster than the previous operation XPS will compile the necessary libraries based on the hardware configurations found in the system assembly window Just as before you will see Done in the output console when complete Before we start our software development we should start the implementation phase as this takes a considerable amount of time So far we have synthesized our hardware but now XPS must translate map and place and route our hardware From the top menu select Hard ware Generate Bitstream This will also attempt to compile any application code and ini tialize the BRAMs We have no application code at this point 4 To complete our simple microprocessor system we must develop the software to drive the LEDs The next few steps will guide you through the software development process using C programming and the XPS development tools a Using you favorite editor create a file called lab2a c Type the uncommented C code shown below in your file and save it in your lab2 directory ECEN 449 Laboratory Exercise 2 oro r nicroblaze 7 10 i lt gt dimb mb_v10 1 00 a 9 Imb nb v10 1 00 a gt mb pib plb v46 1 02 a O amp 9 dimb entir nb bram if cntlr 2 10 a 3 iimb cntir mb bram if cntlr 2 10 a L gt e SRAM xps_mch_emc 1 00 a li 4 lt 2 Imb_bram bram_block 1 00 a i
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