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uPD789014 Subseries 8-bit Single
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1. seseeee 140 9 8 Accepting Non Maskable Interrupt Request eem 140 9 9 Interrupt Request Acceptance Program Algorithm seen eee 142 9 10 Interrupt Request Acceptance Timing example of MOV A r sssssseeeeeemen 143 9 11 Interrupt Request Acceptance Timing When interrupt request flag generates at the last clock during instruction execution 143 9 12 Example of Multiplexed Interrupt 0 0 0 eeeseeeeeseeeeeneeeeeeneeeeeaeeeseneeeeseneeseseeeeseaeeeeeeeeensaeeeesaeeeeeneeeeees 144 10 1 Oscillation Stabilization Time Select Register Format ccceecceeeeeseeeeeeeeeeeseeeeeeeseaeeeeeeseaeesseeeeates 148 10 2 Releasing HALT Mode by Interrupt 000 0 eee eeeeseeeesneeeeeneeeeeeneeesnaeeeeeaeeeeseaeeeseaeeeeeeeeeeeeeeseeesensatenees 150 10 3 Releasing HALT Mode by RESET Input ceccecceeeeeeeeeeceeeeeeeeeeeeeaeeeeaeeseeseaeeseeseaeeseeeseaeeseaeeeeetes 151 10 4 Releasing STOP Mode by Interrupt esssssssneeeneeneneeene nennen neret nennen nennen nnne nnn 153 10 5 Releasing STOP Mode by RESET Input sssssseeeeeeeenneneeenenenneen nennen enne nnne 154 11 1 Block Diagram of Reset FUNCOM acude reete nex eet ee erc ERR LER e EXE ERE HC Y nien 155 11 2 Reset Timing by RESET Input er yeti tt Hg e v Led e ence i cen dant 156 11 3 Reset Timing by Overflow in Watchdog Timer esssssssseeeeneeneenenenneee nennen nene 156 11 4 Reset
2. Internal bus Output latch P10 to P17 b P10 to P17 PM10 to PM17 Remark PUO pull up resistor option register PM port mode register RD port 1 read signal WR port 1 write signal 60 i wA j ed CHAPTER 4 PORT FUNCTIONS 4 2 3 Port 2 This is a 3 bit I O port with output latch Port 2 can be specified in the input or output mode in 1 bit units by using the port mode register 2 PM2 When using P20 to P22 pins as input port pins internal pull up resistors can be connected in 1 bit units by using the pull up resistor option register PUO The pins of this port are also used as the data I O pin of the serial interface This port is set in the input mode when the RESET signal is input Figures 4 4 through 4 6 show the block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O or output latch must be set according to the functions to be used For the details of the setting refer to Table 8 2 Serial Interface 00 Operating Mode Settings Figure 4 4 Block Diagram of P20 Voo Mm P ch 7 3 a s t o 2 O P20 ASCK SCKO PUO pull up resistor option register PM port mode register RD port 2 read signal WR port 2 write signal 61 CHAPTER 4 PORT FUNCTIONS 62 Figure 4 5 Block Diagram of P21 WRreort Internal bus me
3. Caution When using port 2 as serial interface pins the I O or output latch must be set according to the functions to be used For the details of the setting refer to Table 8 2 Serial Interface 00 Operating Mode Settings Remark x don t care PMxx port mode register Pxx port output latch 66 CHAPTER 4 PORT FUNCTIONS Figure 4 9 Port Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address After Reset R W PMO PMO07 PMO6 PMO5 PM04 PMOS PM02 PMO1 PMOO FF20H FFH R W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H FFH R W PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R W PM3 1 1 1 1 1 PM32 PM31 PM30 FF23H FFH R W Pmn Pin Input Output Mode Selection m 0 to 3 n 0 to 7 Output mode output buffer ON Input mode output buffer OFF 2 Pull up resistor option register PUO The pull up resistor option register PUO sets whether an on chip pull up resistor on each port is used or not On the port which is specified to use the on chip pull up resistor in the PUO the pull up resistor can be internally used only for the bits set in the input mode No on chip pull up resistors can be used in the bits set in the output mode in spite of setting the PUO On chip pull up resistors cannot be used even when the pins are used as the alternate function output pins PUO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PUO to 00H Figure 4 10 Pu
4. 46 i wA j ed CHAPTER 3 CPU ARCHITECTURE 3 3 Instruction Address Addressing An instruction address is determined by program counter PC contents PC contents are normally incremented 1 for each byte automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed When a branch instruction is executed the branch destination information is set to the PC and branched by the following addressing For details of each instruction refer to 78K 0S Series User s Manual Instruction U11047E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words the range of branch in relative addressing is between 128 and 127 of the start address of the following instruction This function is carried out when the BR addr16 instruction or a conditional branch instruction is executed Illustration oa eo the next instruction of a BR instruction 15 8 7 6 0 uw qu y jdisp8 15 0 When S 0 a indicates all bits 0 When S 1 a indicates all bits 1 47 i rio g ie ed CHAPTER 3 CPU ARCHITECTURE 3
5. fx 2 39 1 kHz O oj o o ooo o fx 28 19 5 kHz 1 Input clock from external to ASCK pin Other than above Setting prohibited Cautions 1 When writing to BRGCOO is performed during a communication operation the output of baud rate generator is disrupted and communications cannot be performed normally Be sure not to write to BRGCOO during communication operation 2 Be sure not to select n 1 during an operation at fx 5 0 MHz because n 1 exceeds the baud rate limit Remarks 1 fx system clock oscillation frequency 114 2 Figure in parentheses applies to operation when fx 5 0 MHz CHAPTER 8 SERIAL INTERFACE 00 The baud rate transmit receive clock to be generated is either a signal scaled from the system clock or a signal scaled from the clock input from the ASCK pin i Generation of baud rate transmit receive clock by means of system clock The transmit receive clock is generated by scaling the system clock The baud rate generated from the system clock is found from the following expression f Baud rate a Hz ant x 8 fx system clock oscillation frequency n value set in TPS000 to TPS003 2 lt n lt 8 Table 8 5 Example of Relationship between System Clock and Baud Rate Baud Rate BRGCO00 Set Value Error 95 bps fx 5 0 MHz fx 4 9152 MHz 115 CHAPTER 8 SERIAL INTERFACE 00 116 ii Generation of baud r
6. pee HERR pater edhe t ERE sateen ODen 50 3 4 2 Short direct addressing un oa uenit ei MORIR E 51 3 4 8 Special function register SFR addressing sssssseeeenenenne 52 3 4 4 Register addressing sinine npe e pn edenda E eed UR c ia e eat 53 3 4 5 Register indirect addressing cseccceesseneseeceeesceeteesceeeneeeeseseeesessneneneeeeedeeeeeeeasenenseeeeseeeeees 54 3 4 6 Based addressing nee cerei dote Sra Ebo rete eee eerie 55 3 47 Stackcaddressilig 5 deside Ius 55 CHAPTER 4 PORT FUNCTIONS 1 e rerieeeren rtc enre nnne rh nocere ern Donna eroi Uma Eae eDaDR OK a ean Dm nnmnnn nenn 57 4 1 F nctioris of Ports uere eri didtur eer iu er Cose aa dat edu ge ni dtnmr ra aa Ene Reds 57 4 2 POrt COMMUTATION m o M 59 pus MED ROMO p EE 59 B22 do shee esd she dee satan UTLC RE EUST 60 4 2 3 SPOFt Secs silted ae E ee a aea diaeta ie ola 61 4 2 4 EROM 9 deci tht c tiet i geet ehe duced peated a a aide Ae ey 64 4 3 Port Function Control Registers c cccsseccsseeesseeeeeeeeeeseneeeeseeeeseesseseaeeeeeeeeeseneeeneneeeas 66 4 4 Operation of Port Functions cssecceesee seen eeeeeee sees eeeeeeesecaeseseeeeeeseesesseeeeneeeeesneaeeneenees 68 AAi Writing toO portei e ED staat ase beaten e etn rius itid 68 4 4 2 Heading from l O pott et erecto mb t ede ade Ra d ec need edt ee bx ELE 68 4 4 3 Arithmetic operation of I O port ssssssssee
7. A 2 PROM Writing Tools A 2 1 Hardware PG 1500 PROM programmer that can program PROM contained single chip microcontrollers PROM programmer in stand alone mode or through manipulation from host machine when connected to board supplied as accessory and optional PROM programmer adapter Can program representative PROMs from 256K bit to 4M bit models PA 78P9014GT PROM programmer adapter for uPD78P9014 and connected to PG 1500 PA 17K DZ PROM programmer adapter A 2 2 Software PG 1500 controller Connects PG 1500 and host machine with serial and parallel interfaces and controls PG 1500 on host machine The PG 1500 controller is a DOS based application Use this software in the DOS pane when running it on Windows Part number uSxxxxPG1500 Remark xxxx in the part number differs depending on the host machines and operating systems to be used uSxxxxPG1500 PC 9800 Series MS DOS 3 5 2HD FD Ver 3 30 to Ver 6 2Nete IBM PC AT compatibles IBM DOS J5 02 V ee 3 5 2HC FD Note Although the MS DOS or IBM DOS Ver 5 0 or later provides a task swap function the above software does not provide the task swap function 178 APPENDIX A DEVELOPMENT TOOLS A 3 Debugging Tools A 3 1 Hardware IE 78K0 NS In circuit emulator In circuit emulator for debugging hardware and software of application system using 78K 0S Series Supports integrated debugger ID 78K0S NS Used in combination with AC a
8. Bit manipulation set reset test etc I O ports CMOS input output 22 Serial interface 3 wire serial I O mode UART mode selectable 1 channel Timer 8 bit timer event counter 2 channels Watchdog timer 1 channel Timer outputs 2 Vectored interrupt Maskable Internal 5 External 3 Sources Non maskable Internal 1 Power supply voltage Voo 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C Packages 28 pin plastic shrink DIP 400 mil 28 pin plastic SOP 375 mil 25 MEMO 26 2 1 List of Pin Functions CHAPTER 2 PIN FUNCTIONS 2 1 1 Pins in normal operating mode 1 Port pins POO to P07 Input output Function Port 0 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly After Reset Alternate Function P10 to P17 Input output Port 1 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly Input output Port 2 3 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specifi
9. P21 TxD soo Alternate function PUO pull up resistor option register PM port mode register RD port 2 read signal WR port 2 write signal CHAPTER 4 PORT FUNCTIONS Figure 4 6 Block Diagram of P22 PUO2 p P ch Alternate 4 function ix Sal o 2 a Oo c o g ec T 1 P22 RxD SIO PM22 PUO pull up resistor option register PM port mode register RD port 2 read signal WR port 2 write signal 63 i PY SY o ed CHAPTER 4 PORT FUNCTIONS 4 2 4 Port 3 This is a 3 bit I O port with output latch Port 3 can be specified in the input or output mode in 1 bit units by using the port mode register 3 PM3 When using P30 to P32 pins as input port pins on chip pull up resistors can be connected in 3 bit units by using the pull up resistor option register PUO The pins of this port are also used as the timer I O and external interrupt pins This port is set in the input mode when the RESET signal is input Figures 4 7 and 4 8 show the block diagrams of port 3 Figure 4 7 Block Diagram of P30 and P31 Voo gt ey Alternate 4 RD function Internal bus Output latch P30 P31 PM30 PM31 Alternate function gt P30 INTPO TIO TOO P31 INTP1 TH TO1 PUO pull up resistor option register PM port mode register RD por
10. Table 4 1 Port Functions Function Port 0 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly After Reset Alternate Function P10 to P17 Input output Port 1 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly Input output Port 2 3 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly ASCK SCKO TxD SOO RxD SIO 58 Input output Port 3 3 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly INTPO TIO TOO INTP1 TIT TO1 i ri oY a ed CHAPTER 4 PORT FUNCTIONS 4 2 Port Configuration Ports have the following hardware configuration Table 4 2 Port Configuration Configuration Control register Port mode register PMm m 0 to 3 Pull up resistor option register PUO Port Total 22 Inp
11. 1 saddr16 PC PC 2 jdisp8 if CY 0 saddr16 PC PC 2 jdisp8 if Z 1 saddr16 0 0o 0o 0o o o o o o o m BR PM PC PC 2 jdisp8 if Z 0 saddr bit addr16 E eo PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 E eo PC c PC 4 jdisp8 if sfr bit 1 A bit addr16 PC lt PC 3 jdisp8 if A bit 1 PSW bit addr16 PC c PC 4 jdisp8 if PSW bit 1 saddr bit addr16 PC lt PC 4 jdisp8 if saddr bit 0 sfr bit addr16 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 PC amp PC 3 jdisp8 if A bit 0 PSW bit addr16 PC PC 4 jdisp8 if PSW bit 0 B addr16 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 C C 1 then PC PC 2 jdisp8 if C 0 saddr addr16 WINI N AJOJ AJAJAJ oO AJ BR M MM NM Dw saddr saddr 1 then PC lt PC 3 jdisp8 if saddr z 0 No Operation IE 1 Enable Interrupt IE 0 Disable Interrupt Set HALT Mode Set STOP Mode Remark One instruction clock cycle is one CPU clock cycle fceu selected by processor clock control register PCC 171 i YU NS aae PEMSEBEAT AHN Gye r MCL CHAPTER 13 INSTRUCTION SET 13 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC D
12. CY A byte CY saddr CY saddr byte CY saddr byte A r A saddr A CY A r CyY A CY A saddr CY A laddr16 A HL A HL byte A CY A addr16 CY A CY A HL CY A CY A HL byte CY A byte A CY A byte saddr CY lt saddr byte saddr byte A r A saddr A CY A r A CY A saddr laddr16 HL A HL byte A CY A addr16 A CY A HL 0 0o 0 A HR oO BR OD OD oO BR KR OO HR OD OD oO BR HR ODO HR oO HR HR oO WD oa A CY A HL byte Note Only when rp BC DE or HL Remark One instruction clock cycle is one CPU clock cycle fceu selected by processor clock control register PCC 168 CHAPTER 13 INSTRUCTION SET Mnemonic Operands Operation A byte A CY A byte CY saddr CY lt saddr byte CY A CY A r CY A CY A saddr A CY A addr16 CY A CY A HL A CY A HL byte CY saddr byte A r A saddr A laddr16 A HL A HL byte A byte A lt A byte saddr saddr byte A c A r saddr byte A r A saddr A lt A saddr A laddr16 A HL A A addr16 H L A amp A HL byte AC A A HL byte A byte
13. Figure 10 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal mode HALT mode aa al Operation Oscillation Clock Remarks 1 The broken line indicates the case where the interrupt request that has released the standby mode is accepted 2 The wait time is as follows When vectored interrupt processing is performed 9 to 10 clocks When vectored interrupt processing is not performed 1 to 2 clocks b Releasing by non maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled and vectored interrupt processing is performed 150 CHAPTER 10 STANDBY FUNCTION c Releasing by RESET input When the HALT mode is released by the RESET signal execution branches to the reset vector address in the same manner as the ordinary reset operation and program execution is started Figure 10 3 Releasing HALT Mode by RESET Input HALT Wait instruction p 2 5 fx 6 55 ms i RESET signal Oscillation Operation Reset stabilization Operation mode HALT mode period wait status mode lt 3 lt Oscillation Clock Oscillation uA stops E Oscillation Remarks 1 fx system clock oscillation frequency 2 at fx 5 0 MHz operation Table 10 2 Operation after Release of HALT Mode Releasing Source Operation Maskable interrupt request Executes next address instruction Executes interrup
14. IFO INTMO M MKO 0 OSTS P PO P1 P2 P3 PCC PMO PM1 PM2 PM3 PUO R RXBOO T TCL2 TMOO TMO1 TMCOO TMCO1 TXS00 W WDTM Asynchronous serial interface mode register 00 102 110 112 126 Asynchronous serial interface status register 00 105 113 Baud rate generator control register 00 106 114 127 8 bit compare register 00 80 8 bit compare register 01 80 Serial operating mode register 00 101 109 111 125 Interrupt request flag register O 135 External interrupt mode register O 137 Interrupt mask flag register O 136 Oscillation stabilization time select register 148 Port 0 59 Port 1 60 Port 2 61 Port 3 64 Processor clock control register 70 Port mode register 0 66 Port mode register 1 66 Port mode register 2 66 Port mode register 3 66 83 Pull up resistor option register 67 Receive buffer register 00 100 Timer clock select register 2 93 8 bit timer register 00 80 8 bit timer register 01 80 8 bit timer mode control register 00 81 8 bit timer mode control register 01 82 Transmit shift register 00 100 Watchdog timer mode register 94 185 MEMO 186 APPENDIX D REVISION HISTORY Major revisions by edition and revised chapters are shown below Edition Major Revisions from Previous Edition U
15. The clock generator generates the clock to be supplied to the CPU and peripheral hardware The system clock oscillator consists of the following type System clock oscillator This circuit oscillates at frequencies of 1 0 to 5 0 MHz Oscillation can be stopped by executing the STOP instruction 5 2 Configuration of Clock Generator The clock generator consists of the following hardware Table 5 1 Configuration of Clock Generator Configuration Control register Processor clock control register PCC Oscillator System clock oscillator Figure 5 1 Block Diagram of Clock Generator Peer Ex Clock to peripheral hardware Standby control dbi CPU clock fcru circuit x1 System clock x2 oscillator i STOP Prescaler fx 2 Selector Processor clock control register PCC Internal bus 69 i tinued CHAPTER 5 CLOCK GENERATOR 5 3 Clock Generator Control Register The clock generator is controlled by the following register Processor clock control register PCC 1 Processor clock control register PCC The PCC sets CPU clock selection and the ratio of division The PCC is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the PCC to 02H Figure 5 2 Processor Clock Control Register Format Symbol 7 Address After Reset R W Poc Lee Ts Fer FFFBH o2H RW CPU Clock fceu Selection 0 2 us fx 2 0 8 us Caution Bit 0 and bits 2 to 7 must be
16. 00 BRGCOO 1 Serial operating mode register 00 CSIMOO This register is set when using the serial interface 00 in the 3 wire serial I O mode CSIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMOO to 00H Figure 8 3 Serial Operating Mode Register 00 Format Symbol lt 7 gt Address After Reset R W 6 5 4 3 2 1 0 csimoo seo o o o o prosao o ref ooh Rw CSIEO0 Operation Control in 3 Wire Serial I O Mode 0 Operation stop 1 Operation enable DIROO Start Bit Specification 0 MSB 1 LSB cso Clock Selection in 3 Wire Serial I O Mode 0 Input clock to SCKO pin from external 1 Dedicated baud rate generator output Cautions 1 Be sure to set 0 to bit 0 and bits 3 to 6 2 Set 00H to the CSIMOO at the UART mode 3 In the 3 wire serial I O mode if the operation is interrupted CSIE00 0 during data transmission reception and if the operation control flag is cleared CSIEO0 0 when not performing data transmit receive P21 which is the alternate function I O port pin of SOO cannot be used as a general purpose output port 101 CHAPTER 8 SERIAL INTERFACE 00 2 Asynchronous serial interface mode register 00 ASIMOO This register is set when using the serial interface 00 in the asynchronous serial interface mode ASIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIMOO to 00H Figure 8 4 Asynchronous Serial Interface Mode Reg
17. 00H Transmit shift register TXSO00 Receive buffer register RXBOO Undefined Interrupt Request flag register IFO 00H Mask flag register MKO FFH External interrupt mode register INTMO 00H Notes 1 During reset input and oscillation stabilization time wait only the PC contents among the hardware statuses become undefined All other hardware remains unchanged after reset 2 The post reset values are retained in the standby mode 157 MEMO 158 CHAPTER 12 uPD78P9014 The uPD78P9014 is a version with an internal ROM of the uPD789011 and 789012 expanded and replaced with a one time PROM The differences between the uPD78P9014 and the mask ROM versions are shown in Table 12 1 Table 12 1 Differences between PD78P9014 and Mask ROM Versions Mask ROM Version Item One Time PROM Version uPD78P9014 Internal memory ROM 8 Kbytes uPD78901 1 2 Kbytes uPD789012 4 Kbytes High speed RAM 256 bytes 128 bytes IC pin Not provided Provided Ver pin Provided Not provided Electrical specifications Refer to each data sheet Caution There are differences in noise immunity and noise radiation between the PROM and mask ROM versions When pre producing an application set with the PROM version and then mass producing it with the mask ROM version be sure to conduct sufficient evaluations for the commercial samples not engineering samples
18. 2 atfx 5 0 MHz operation 3 n20 1 84 CHAPTER 6 8 BIT TIMER EVENT COUNTER Figure 6 5 Interval Timer Operation Timing l t I l E Bi I I I I l l 1 rwoncomtvaue 0 Jer X 2 Xov Jon oI GC UG TCEOn TOn i La mla mla I I Interval time Interval time Interval time l Remarks 1 Interval time N 1 x t N 00H to FFH 2 n20 1 85 CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 4 2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TIO P30 INTPO TOO and TI1 P31 INTP1 TO1 pins by using the timer register 00 and 01 TMOO and TMO1 To operate the 8 bit timer event counter as an external event counter the settings are required in the following order lt 1 gt Set P30 and P31 to input mode PM30 1 PM31 1 lt 2 gt Set the 8 bit timer register On TMOn to operation disable TCEOn bit 7 of 8 bit timer mode control register On TMCOn 0 3 Specify the rising and falling edges of Tin refer to Table 6 4 and set TOn to output disable TOEOn bit 0 of TMCOn 0 lt 4 gt Set count value to CROn lt 5 gt Set TMOn to operation enable TCEOn 1 Each time the valid edge specified by bit 1 TCL000 and TCL010 of TMC00 and TMC01 is input the value of the 8 bit timer register On TMOO and TMO1 is incremented When the count values of TM00 and TMO1 match the value set to C
19. 25 156 kHz fx 28 78 1 kHz fx 27 39 1 kHz fx 28 19 5 kHz Input clock from external to ASCK pin Other than above Setting prohibited Note Only used in UART mode Cautions 1 When writing to BRGCOO is performed during a communication operation the baud rate generator output is disrupted and communications cannot be performed normally Be sure not to write to BRGCOO during communication operation 2 Be sure not to select n 1 during an operation at fx 5 0 MHz because n 1 exceeds the baud rate limit Remarks 1 fx system clock oscillation frequency 2 Figure in parentheses applies to operation when fx 5 0 MHz CHAPTER 8 SERIAL INTERFACE 00 The baud rate transmit receive clock to be generated is either a signal scaled from the system clock or a signal scaled from the clock input from the ASCK pin a Generation of baud rate transmit receive clock by means of system clock The transmit receive clock is generated by scaling the system clock The baud rate generated from the system clock is found from the following expression f Baud rate PE M Hz ant x 8 fx system clock oscillation frequency Table 8 3 Example of Relationship between System Clock and Baud Rate Baud Rate BRGCOO Set Value Error 95 bps fx 5 0 MHz fx 4 9152 MHz 107 CHAPTER 8 SERIAL INTERFACE 00 b Generation of baud rate transmit receive clock by m
20. 3 2 Immediate addressing Function Immediate data in the instruction word is transferred to the program counter PC and branched This function is carried out when the CALL laddr16 and BR laddr16 instructions are executed CALL addr16 and BR addr16 instructions can branch to all the memory spaces Illustration In case of CALL addr16 BR addr16 instruction 7 0 CALL or BR Low Addr High Addr 15 87 0 PC 48 i i id we Le L CHAPTER 3 CPU ARCHITECTURE 3 3 3 Table indirect addressing Function Table contents branch destination address of the particular location to be addressed by the low order 5 bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces Illustration 7 6 5 1 0 renwsencase 0 1 w To 15 8 7 6 5 10 Ettecive Address o o o o o o o oloi 7 Memory Table 0 Low Addr Effective Address 1 High Adar 15 8 7 0 PC 3 3 4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX instruction is executed Illustration 4
21. 5 V to Vpop and 12 5 V to Vp 6 Verify mode Data are output as one address sequentially every fourth pulse cycles when clock pulse is fed to the X1 pin Program memory address 0 clear mode Change Vo and Vr pins voltage to 5 V Power off S Steps 2 to 7 of the above procedure are shown in the figure below MDO A MD1 f MD2 PUES mo MD3 C a AN 162 CHAPTER 12 uPD78P9014 12 1 4 One time PROM screening The one time PROM version due to its structure cannot be fully tested by NEC before shipping It is recommended to perform screening to verify PROM after writing necessary data and performing high temperature storage under the conditions indicated below Storage Temperature Storage Time NEC offers the services with charged to write through mark screen and verify a one time PROM version as we call the QTOP Microcontroller For details contact an NEC sales representative 163 MEMO 164 CHAPTER 13 INSTRUCTION SET This chapter lists the instruction set of the L PD789014 Subseries For the details of the operation and machine language instruction code of each instruction refer to 78K 0S Series User s Manual Instruction U11047E 13 1 Operation 13 1 1 Operand identifiers and description methods Operands are described in Operand column of each instruction in accordance with the description method of the instruction operand identifier refer to th
22. Acceptance WDTMA 1 watchdog timer mode is selected S Yes WDT overflows Yes WDTM3 0 non maskable interrupt is selected Yes Interrupt request is generated Interrupt processing is started Interval timer Reset processing WDTM watchdog timer mode register WDT watchdog timer Figure 9 7 Timing of Non Maskable Interrupt Request Acceptance 7 Saving PSW and PC and CPU processing Instruction Instruction jump to interrupt processing terrupt processing program Figure 9 8 Accepting Non Maskable Interrupt Request Main routine First interrupt processing NMI request second t NMI request first Second interrupt processing 140 al Mie CHAPTER 9 INTERRUPT FUNCTIONS 9 4 2 Maskable interrupt acceptance operation A maskable interrupt request can be accepted when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0 A vectored interrupt request is accepted in the interrupt enabled status when the IE flag is set to 1 The time required to start the interrupt processing after a maskable interrupt request has been generated is shown in Table 9 3 Refer to Figures 9 10 and 9 11 for the interrupt request acceptance timing Table 9 3 Time from Generation of Maskable Interrupt Request to Processing Minimum Time Maximum TimeNete Note The wait time is maximum when an interrupt
23. CSIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMOO to 00H Set 00H to CSIMOO when UART mode is selected Symbol 7 Address After Reset R W CSIMOO EES ean ERA FF72H 00H R W sion Operation Control in 3 Wire Serial O Mode Control in 3 Wire Serial I O Mode Operation stop Operation enable DIROO Start Bit Specification cso Clock Selection in 3 Wire Serial I O Mode 0 Input clock to SCKO pin from external Dedicated baud rate generator output Caution Be sure to set 0 to bit 0 and bits 3 to 6 111 i tinued CHAPTER 8 SERIAL INTERFACE 00 b Asynchronous serial interface mode register 00 ASIMOO ASIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIMOO to 00H Symbol 7 Address After Reset R W ASIMo0 E OE EEA FFT OOH RW Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity CLOO Character Length Specification O 7 bits 1 8bits SLOO Transmit Data Stop Bit Length Specification O 1 bit 1 2 bits Cautions 1 Be sure to set 0 to bits 0 and 1 2 Switching operation modes must be performed after the halt of serial transmit receive operation 112 CHAPTER 8 SERIAL INTERFACE 00
24. Clock IC Internally Connected SIO Serial Input POO to P07 Porto SO0 Serial Output P10 to P17 Port TIO Timer Input P20 to P22 Port2 TOO Timer Output P30 to P32 Port3 TxD Transmit Data RESET Reset Vpop Power Supply RxD Receive Data VpP Programming Power Supply Vss Ground 20 CHAPTER 1 GENERAL 2 PROM programming mode 28 pin plastic shrink DIP 400 mil LPD78P9014CT 28 pin plastic SOP 375 mil uPD78P9014GT DO O Cautions 1 L Independently connect to Vss via a pull down resistor 2 Vss Connect to the ground 3 RESET Set to low level 4 Open Leave open DO to D7 Data Bus VoD Power Supply MDO to MD3 Programming Power Supply VpP Programming Power Supply RESET Reset Vss Ground X1 Programming Clock Input 21 CHAPTER 1 GENERAL x 1 5 78K 0S Series Lineup The products in the 78K 0S Series are listed below The names enclosed in boxes are subseries names 78K 0S Series 22 44 pin 42 44 pin 28 pin 44 48 pin 44 48 pin 44 pin 44 pin 30 pin 30 pin 28 30 pin 28 30 pin 28 30 pin 28 30 pin I 44 pin 80 pin 80 pin 88 pin 44 pin 42 44 pin 5 pin g uPD789046 uPD789026 JPD789014 Jo y Products in mass production K Products under development fans Added a subsystem clock to the uPD789026 Enhanced timer of the uPD789014 On chip UART capable of operating at
25. High speed RAM E 128 x 8 bits 3 FE80H Y FE7FH Direct Addressing Register Indirect Addressing Reserved Based Addressing 0800H 07FFH Internal ROM 2048 x 8 bits 0000H 1 38 CHAPTER 3 CPU ARCHITECTURE Figure 3 5 Data Memory Addressing uPD789012 FFFFH Special Function Registers SFR SFR Addressing 256 x 8 bits EE2OEE lim Lor m eet meom secco entr salen e mt e t ER en e n FF1FH 4 FFOOH FEFFH Short Direct Internal High speed RAM 128 x 8 bits Addressing FE80H i FE7FH Direct Addressing Register Indirect Addressing Reserved Based Addressing 1000H OFFFH Internal ROM 4096 x 8 bits 0000H 39 CHAPTER 3 CPU ARCHITECTURE 40 Figure 3 6 Data Memory Addressing uPD78P9014 FFFFH Special Function Registers SFR SFR Addressing 256 x 8 bits FF20H FFIFH FFOOH FEFFH Short Direct Internal High speed RAM Addressing 256 x 8 bits FE20H FE1FH FEOOH FDFFH Reserved 2000H 1FFFH Internal PROM 8192 x 8 bits 0000H Direct Addressing Register Indirect Addressing Based Addressing i PI SY o ed CHAPTER 3 CPU ARCHITECTURE 3 2 Processor Registers The uPD789014 Subseries provide the following on chip processor registers 3 2 1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory A program counter a program status word and a
26. Receive Errors Cause Parity error Transmission time parity specification and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from receive buffer register Figure 8 10 Receive Error Timing a Parity error generated STOP RxD Input D1 D2 D7 START INTSR b Framing error or overrun error generated START INTSR Cautions 1 Thecontents of the ASISOO register are reset 0 by reading the receive buffer register 00 RXBOO or receiving the next data To ascertain the error contents read ASISOO before reading RXBOO 2 Be sure to read the receive buffer register 00 RXBOO even if a receive error occurs If RXBOO is not read an overrun error will be generated when the next data is received and the receive error state will continue indefinitely 121 CHAPTER 8 SERIAL INTERFACE 00 3 UART mode cautions 122 a When bit 7 TXEOO of the asynchronous serial interface mode register 00 ASIMOO is cleared during transmission be sure to set the transmit shift register 00 TXS00 to FFH then set TXEOO to 1 before executing the next transmission b When bit 6 RXEOO of the asynchronous serial interface mode register 00 ASIMOO is cleared during reception receive buffer register 00 RXBOO and receive completion interrupt INTSR are as follows INTSR When RXEOO is set to 0 at a time indicated by 1
27. Receive clock Selector Selector Clear CSCKOO CSIEO0 RXE00 CSIEO0 EP Start bit detection BRGCOO write RXEO0 gt 3 bit counter I Clear Baud rate generator control register 1 semet Internal bus 00 39VJH3INI 1VIH3S 8 HdldVHO CHAPTER 8 SERIAL INTERFACE 00 1 2 3 4 5 100 Transmit shift register 00 TXS00 This register is used to specify data to be transmitted Data written to TXSOO is transmitted as serial data If the data length is specified as 7 bits bits 0 to 6 of the data written to TXSOO are transferred as the transmit data The transmit operation is started by writing data to TXSOO TXSO0 is written to with an 8 bit memory manipulation instruction It cannot be read RESET input sets TXS00 to FFH Caution Do not write to TXSO00 during transmission TXS00 and the receive buffer register 00 RXBOO are allocated to the same address and when reading is performed RXBOO values are read Receive shift register 00 RXS00 This register is used to convert serial data input to the RxD pin into parallel data Each time one byte of data is received it is transferred to the receive buffer register 00 RXBOO The RXS00 cannot be manipulated directly by program Receive buffer register 00 RXBOO This register is used to hold received data Each time one byte of data is received a new receive data is transferred from the rece
28. Reset R W ASIS00 fe ee PEOO FEOO OVE0O FF71H 00H R PEO0 Parity Error Flag Parity error not generated Parity error generated when the parity of transmit data does not coincide FEOO Flaming Error Flag Flaming error not generated Flaming error generated when stop bit is not detected e e 1 Overrun error not generated Overrun error generatedete when the next receive operation is completed before the data is read from the receive buffer register Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SLOO of the asynchronous serial interface mode register 00 ASIMOO the stop bit detection in the case of reception is performed with 1 bit 2 When an overrun error occurs be sure to read out the receive buffer register 00 RXBO0O Unless RXBOO is read out overrun errors occur at each data reception 105 CHAPTER 8 SERIAL INTERFACE 00 4 Symbol 106 Baud rate generator control register 00 BRGCOO This register is used to set the serial clock of serial interface 00 BRGCOO is set with an 8 bit memory manipulation instruction RESET input sets BRGCOO to 00H Figure 8 6 Baud Rate Generator Control Register 00 Format 7 6 5 4 3 Address After Reset R W 2 1 0 BRGCOO TPS003 TPS002 TPS001 TPS000 ESNESESES FF73H 00H R W TPSO02 TPS001 TPS000 3 Bit Counter Source Clock Selection n fx 2 2 5 MHz fx 22 1 25 MHz fx 23 625 kHz fx 24 313 kHz fx
29. Reset stabilization Operation mode STOP mode period wait status mode Oscillation Clock Oscillation stops ue Oscillation Remarks 1 fx system clock oscillation frequency 2 at fx 5 0 MHz operation Table 10 4 Operation after Release of STOP Mode Releasing Source MKxx Operation Maskable interrupt request Executes next address instruction Executes interrupt processing Retains STOP mode RESET input Reset processing x don t care 154 i wA j ed CHAPTER 11 RESET FUNCTION The following two operations are available to generate reset signals 1 External reset input with RESET pin 2 Internal reset by program runaway time detected with watchdog timer External and internal reset have no functional differences In both cases program execution starts at the address at 0000H and 0001H by reset signal input When a low level is input to the RESET pin or the watchdog timer overflows a reset is applied and each hardware is set to the status shown in Table 11 1 Each pin has a high impedance during reset input or during oscillation stabilization time just after reset clear When ah high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabilization time 2 5 fx has elapsed The reset applied by the watchdog timer overflow is automatically cleared after reset and program execution is started after the oscillation stabilization t
30. Special Function Registers 256 x 8 bits FFOOH FEFFH Internal High speed RAM 256 x 8 bits FEOOH FDFFH Reserved Data memory space 1FFFH 2000H 1FFFH Program Area Program Internal PROM 0080H boda sd 8192 x 8 bits ME CALLT Table Area 0040H 003FH Program Area 0014H 0013H Vector Table Area 1 0000H 0000H 35 CHAPTER 3 CPU ARCHITECTURE 3 1 1 Internal program memory space The internal program memory space stores programs and table data This space is usually addressed by the program counter PC The uPD789014 Subseries provide the internal ROMs or PROM containing the following capacities on each product Table 3 1 Internal ROM Capacity Part Number Internal ROM Structure Capacity uPD78901 1 Mask ROM 2048 x 8 bits uPD789012 4096 x 8 bits uPD78P9014 8192 x 8 bits The following areas are allocated to the internal program memory space 1 Vector table area A 20 byte area of addresses 0000H to 0013H is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation Of a 16 bit program address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request RESET input INTSR INTCSIO INTWDT INTST INTPO INTT
31. Symbol 7 6 5 4 3 2 1 0 Address After Reset R W TMCOO TOO 0 o o o ToLo01 TCL00d TOEO0 FF53H 00H R W TCEO0 8 Bit Timer Register 00 Operation Control 0 Operation stop TMOO cleared to 0 1 Operation enable TCLO01 TCLOO0 8 Bit Timer Register 00 Count Clock Selection fx 5 0 MHz fx 25 156 kHz Rising edge of TIONete Falling edge of TION Output disable port mode ToE00 8 Bit Timer Event Counter 00 Output Control 0 1 Output enable Note When clock is externally input timer output cannot be used Caution Be sure to select the count clock after stopping timer operation TCEO0 0 For details refer to 6 4 Operation of 8 Bit Timer Event Counter Remarks 1 fx system clock oscillation frequency 2 at fx 5 0 MHz operation 81 CHAPTER 6 8 BIT TIMER EVENT COUNTER 82 2 8 bit timer mode control register 01 TMCO1 This register enables stops operation of 8 bit timer register 01 TMO1 sets the count clock of 8 bit timer event counter 01 and controls the operation of the output control circuit TMCO01 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMCO1 to 00H Figure 6 3 8 Bit Timer Mode Control Register 01 Format Symbol 7 6 0 Address After Reset R W 5 4 3 2 1 0 TMCO01 TOO o 0 o o raton TCLO010 TOEO1 FF57H 00H R W TCEO1 8 Bit Timer Register 01 Operation Control Operation stop TMO1 cleared to 0 Opera
32. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers offi
33. ee eeeeeeeeeeee enne n nenne nnmnnn nnmnnn nnmnnn nnn nn nnn 97 8 1 Serial Interface 00 Functions ueeeeesseeeeeeeeeeeeseseeene enne nnn nnne nn etna nnn nennen 97 8 2 Serial Interface 00 Configuration leseeeeeeeesese esee eeeeee senem nn nante nnn tn nana 97 8 3 Serial Interface 00 Control Registers esee nennen enne nnne 101 8 4 Serial Interface 00 Operation eeesseeeeeeeeeeeses seen en enne natnm nnne nnn anne nnns 109 84 1 Operation Stop mode tic ci ie ie eterne ie e D nde do e eS aee 109 8 4 2 Asynchronous serial interface UART mode seem 111 9 4 3 3 wire serial l Ocmode 5 oerte hem ttd ih de dile ae e us 125 CHAPTER 9 INTERRUPT FUNCTIONS 1 cree eccL Leer cere Lerner creen eee c cech aan r rera aa sr D ccce rar 131 9 1 Interrupt Function Types seeeeeeeenenen nennen nennen nennen nurses nnt nn nin nnn enin nnmnnn nnmnnn 131 9 2 Interrupt Sources and Configuration necesse esses eeen nennen nnne nnn 131 9 3 Interrupt Function Control Registers eeeeeseeee esee eene eeenee nennen nnne nnne 134 9 4 Interrupt Processing Operation eeseeessseeeeeeeeseseene nennen nennen nnne nnn snnt 139 9 4 1 Non maskable interrupt request acceptance operation ssm 139 9 4 2 Maskable interrupt acceptanc
34. erara raae eaa era es a e hea deena ihoa sain nnns nnns sss n anna 181 APPENDIX C REGISTER INDEX eeeeeessseeeeeeeeneeen nenne tnnn nnn tn snnt n n snis sans nnne sanas nnns nnn 183 C 1 Register Name Index Alphabetic Order cessent 183 C 2 Register Symbol Index Alphabetic Order eese 185 APPENDIX D REVISION HIS TO RY ertet aeea P eaae E Ea irana Ee Eene eoa dapat Teana 187 14 Figure No Title Page 2 1 Pin Input Output GIFIC lts ep Et idl E e te ee pee re RE Ee es 32 3 1 Memory Map uPD789011 atenn naaa e e n a a a 33 3 2 Memory Map UPD78901 2 ziii coder o ge mec ol dtes ne e oi 34 3 3 Memory Map j PD78P9014 ert gate ee Her ertet e n CO RE RO e ee EAD E RES REE Run 35 3 4 Data Memory Addressing uPD789011 ssssssseeneneeeeeneen meer nnne nnne 38 3 5 Data Memory Addressing uPD789012 ssssssssseeeeeeeeeen enm eee nre 39 3 6 Data Memory Addressing uPD78P901 4 eene nennen nennen 40 3 7 Program Counter Configuration snenie mina a a a enne nennen rennes nenne nnne enne 41 3 8 Program Status Word Configuration ssssssseseeeeeeneee nennen nennen nenne nnne enne 41 3 9 Stack Pointer Gonfig ratiort aea netter ete ao qe ct d ee e ee Do 43 3 10 Data to be Saved to Stack Memory sssssssssssssssseeseeeeeee tenerent nennen nennen nennen 43 3 11 Data to be Restored fr
35. includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above M8E 00 4 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S
36. nnns 101 8 4 Asynchronous Serial Interface Mode Register 00 Format ssssseeeeeeene 102 8 5 Asynchronous Serial Interface Status Register 00 Format 105 8 6 Baud Rate Generator Control Register 00 Format ceeceeseeeeeeeeeeeseeeeeeeeeeeeesaeeseaeeeeeseeeeeeeeeaeeed 106 8 7 Asynchronous Serial Interface Transmit Receive Data Format sesssssssssseeeeee 117 8 8 Asynchronous Serial Interface Transmission Completion Interrupt Timing essss 119 8 9 Asynchronous Serial Interface Reception Completion Interrupt Timing seseeeesss 120 8 10 Receive Error Tring ote Ee QR ei eii rente each aees 121 8 11 3 Wire Serial I O Mode Timing sesssssssssssssseseseeesteete ee tnetne entente tenir trni trennen 128 9 1 Basic Configuration of Interrupt Function sssssssseeseeeneeneneneeen nennen nennen 133 9 2 Interrupt Request Flag Register O Format sssseeeneeeen nennen nnne 135 9 3 Interrupt Mask Flag Register 0 Format ssssssseeeeenem eene nre 136 9 4 External Interrupt Mode Register 0 Format ssssseseeneeeeee meer 137 9 5 Program Status Word Configuration esesssessseseeeeeeneeneenenennee nnne nenne nnne nen 138 9 6 Flowchart from Non Maskable Interrupt Request Generation to Acceptance ssssss 140 9 7 Timing of Non Maskable Interrupt Request Acceptance
37. of 1 in the transmit data including parity bit may be odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a value of 1 is an even number in transmit data 1 At reception The number of bits with a value of 1 in the receive data including parity bit is counted and if the number is even a parity error is generated iii 0 Parity When transmitting the parity bit is set to 0 irrespective of the transmit data Atreception a parity bit check is not performed Therefore a parity error is not generated irrespective of whether the parity bit is set to 0 or 1 iv No parity A parity bit is not added to the transmit data At reception data is received assuming that there is no parity bit Since there is no parity bit a parity error is not generated 118 CHAPTER 8 SERIAL INTERFACE 00 c Transmission A transmit operation is started by writing transmit data to the transmit shift register 00 TXSO0 The start bit parity bit and stop bit s are added automatically When the transmit operation starts the data in TXSOO is shifted out and when TXSOO is empty a transmission completion interrupt INTST is generated Figure 8 8 Asynchronous Serial Interface Transmission Completion Interrupt Timing a Stop bit length 1 START INTST b Stop bit length 2 START INTST Cautio
38. of the mask ROM version 159 i wA j ed CHAPTER 12 uPD78P9014 12 1 PROM Programming An on chip program memory in the uPD78P9014 is an 8 Kbyte one time PROM that can be written electrically Write verify of this one time PROM uses the pins shown in Table 12 2 For the connection of unused pins refer to 1 4 Pin Configuration Top View 2 PROM programming mode Addresses are updated through clock input from the X1 pin instead of address input Table 12 2 Pins in PROM Programming Mode Function VPP PROM programming mode setting and high voltage applied during program write verify normally Voo potential MDO to MD3 Pin used for selecting operating mode during program write verify DO to D7 Data bus Address update clock input during program write verify PROM programming mode setting and power supply voltage application pin Normally 1 8 to 5 5 V and 5 5 V are applied in normal operating mode and PROM programming mode respectively 12 1 1 Operating modes When 5 5 V is applied to the Vop pin and 12 5 V is applied to the VPP pin the PROM programming mode is set This mode will become the operating mode as shown in Table 12 3 when the MDO to MD3 pins are set as shown Table 12 3 Operating Modes of PROM Programming VPP Operating Mode Program memory address 0 clear Write mode Verify mode Program inhibit mode x L or H 160 CHAPTER 12 u
39. reception the most significant bit bit 7 is always 0 The serial transfer rate is selected by means of ASIMOO and the baud rate generator control register 00 BRGCOO If a serial data receive error is generated the receive error contents can be determined by reading the status of the asynchronous serial interface status register 00 ASISOO 117 i rit id ty NG CHAPTER 8 SERIAL INTERFACE 00 b Parity types and operation The parity bit is used to detect a bit error in the communication data Normally the same kind of parity bit is used on the transmitting side and the receiving side With even parity and odd parity a one bit odd number error can be detected With 0 parity and no parity an error cannot be detected i Even parity At transmission The transmission operation is controlled so that the number of bits with a value of 1 in the transmit data including parity bit may be even The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 1 The number of bits with a value of 1 is an even number in transmit data 0 At reception The number of bits with a value of 1 in the receive data including parity bit is counted and if the number is odd a parity error is generated ii Odd parity At transmission Conversely to the even parity the transmission operation is controlled so that the number of bits with a value
40. register On TMOn to operation disable TCEOn bit 7 of 8 bit timer mode control register On TMCOn 0 3 Set count clock of 8 bit timer event counter refer to Table 6 5 and set TOn to output enable TOEOn bit 0 of TMCOn 1 4 Set count value to CROn 5 Set TMOn to operation enable TCEOn 1 When the count value of an 8 bit timer register On TMOO and TM01 matches the value set in CROO and CRO1 the TOO P30 INTPO TIO and TO1 P31 INTP1 TI1 pin output will be inverted respectively Through application of this mechanism square waves of any frequency can be output As soon as a match occurs the TMOO and TMO1 value will be cleared to 0 then resume to count generating an interrupt request signal INTTMO and INTTM1 Setting 0 to the bit 7 in TMCOO and TMCO1 that is TCEOO and TCEO1 clears the square wave output to 0 Table 6 5 shows square wave output range and Figure 6 7 shows timing of square wave output Caution When the count clock and TMOn operation enable are set simultaneously with TMCOn using the 8 bit memory manipulation instruction the error of a cycle from which a timer has been started may become one clock or more Therefore settings must be done in the above order to operate the 8 bit timer event counter for square wave output Remark n O 1 Table 6 5 Square Wave Output Range of 8 Bit Timer Event Counter TCLOn1 TCLOnO Minimum Pulse Width Maximum Pulse Width 1 fx 200 ns 28 fx 51 2 us 1 f
41. request signal INTCSIO 129 MEMO 130 al Mie CHAPTER 9 INTERRUPT FUNCTIONS 9 1 Interrupt Function Types The following two types of interrupt functions are used 1 Non maskable interrupt This interrupt is acknowledged unconditionally even in the interrupt disabled state It does no undergo interrupt priority control and is given top priority over all other interrupt requests A standby release signal is generated The non maskable interrupt has one source of interrupt from the watchdog timer 2 Maskable interrupt These interrupts undergo mask control If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority priority as shown in Table 9 1 A standby release signal is generated The maskable interrupt has three sources of external interrupts and five sources of internal interrupts 9 2 Interrupt Sources and Configuration There are total of 9 non maskable and maskable interrupts in the interrupt sources see Table 9 1 131 CHAPTER 9 INTERRUPT FUNCTIONS Table 9 1 Interrupt Source List Interrupt Type PriorityNete 1 Interrupt Source Internal Vector Basic External Table Configuration Trigger Address TypeNete2 Non maskable INTWDT Watchdog timer overflow with watchdog Internal timer mode 1 selected Maskable INTWDT Watchdog timer overflow with interval timer mode selected NTPO Pin input edge detection Ex
42. requestis generated immediately before BT and BF instruction Remark 1 clock zu fcPu CPU clock fcPu When two or more maskable interrupt requests are generated at the same time they are accepted starting from the interrupt request assigned the highest priority A pended interrupt is accepted when the status where it can be accepted is set Figure 9 9 shows the algorithm of accepting interrupt requests When a maskable interrupt request is accepted the contents of PSW and PC are saved to the stack in that order the IE flag is reset to 0 and the data in the vector table determined for each interrupt request is loaded to the PC and execution branches To return from interrupt processing use the RETI instruction 141 CHAPTER 9 INTERRUPT FUNCTIONS 142 Figure 9 9 Interrupt Request Acceptance Program Algorithm Yes Interrupt request generated No Interrupt request pending No Yes Interrupt request pending Vectored interrupt processing xxlF interrupt request flag xxMK interrupt mask flag IE flag to control maskable interrupt request acceptance 1 enable 0 disable i wA j ed CHAPTER 9 INTERRUPT FUNCTIONS Figure 9 10 Interrupt Request Acceptance Timing example of MOV A r 8 clocks eee Le gn ge ee Lg Saving PSW and PC jump CPU MOV A r to inteirupt precsssing Interrupt processing program Interrupt l D If an interrupt request flag xxIF is set befor
43. serial clock is input from off chip setting BRGCOO is not necessary fx Serial clock frequency oni Hz fx system clock oscillation frequency 127 CHAPTER 8 SERIAL INTERFACE 00 2 Communication operation In the 3 wire serial I O mode data transmission reception is performed in 8 bit units Data is transmitted received bit by bit in synchronization with the serial clock Transmit shift register 00 TXS00 SIOO00 and receive shift register 00 RXSOO shift operations are performed in synchronization with the fall of the serial clock SCKO Then transmit data is held in the SOO latch and output from the SOO pin Also receive data input to the SIO pin is latched in the receive buffer register 00 RXB00 SIOO0 on the rise of SCKO At the end of an 8 bit transfer the operation of TXS00 SIOO00 or RXSO00 stops automatically and the interrupt request signal INTCSIO is generated Figure 8 11 3 Wire Serial I O Mode Timing SCKO SIO SO0 INTCSIO End of transfer Transfer start at the falling edge of SCKO Caution In the 3 wire serial I O mode if the operation is interrupted CSIMOO 0 during data transmission reception and if the operation control flag is cleared CSIEO0 0 when not performing data transmit receive P21 which is the alternate function I O port pin of SOO cannot be used as a general purpose output port To use P21 as a general purpose output port do the following Do not clear th
44. set to 0 Remarks 1 fx system clock oscillation frequency 2 Value in parentheses is when operating at fx 5 0 MHz 3 Minimum instruction execution time 2fcPu When fcru 0 2 us 0 4 us When fcru 0 8 us 1 6 us 70 i PY SY o ed CHAPTER 5 CLOCK GENERATOR 5 4 System Clock Oscillator 5 4 1 System clock oscillator The system clock oscillator is oscillated by the crystal or ceramic resonator 5 0 MHz TYP connected across the X1 and X2 pins An external clock can also be input to the circuit In this case input the clock signal to the X1 pin and input the reversed signal to the X2 pin Figure 5 3 shows the external circuit of the system clock oscillator Figure 5 3 External Circuit of System Clock Oscillator a Crystal or ceramic oscillation b External clock External clock X1 X2 ceramic resonator Cautions 1 While an external clock is input to the circuit do not execute the STOP instruction Doing so stops the system clock operation and pulls up the X2 pin to Vpp 2 When using the system clock oscillator wire the area enclosed by the broken line in Figure 5 3 as follows to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Donotcross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always keep the ground point of the oscillator capacitor to the same po
45. that converts program written in C language into object codes that can be C compiler package executed by microcontroller Used in combination with optional assembler package and device file Caution when used under PC environment The C compiler package is a DOS based application but may be used under the Windows environment by using Project Manager of Windows included in the assembler package Part number wSxxxxCC78K0S DF78901 4Note File containing the information inherent to the device Device file Used in combination with other optional tools RA78KOS CC78K0S SM78KO0S The corresponding operating system and host machine depend on the tools they are combined with Part number uSxxxxDF789014 Note DF789014 is a common file that can be used with RA78KOS CC78KO0S and SM78KO0S Remark xxxx in the part number differs depending on the host machines and operating systems to be used LSxxxxRA78K0S LSxxxxCC78K0S uSxxxxDF789014 T Host Machine Supply Media PC 9800 Series Japanese WindowsNete 3 5 2HD FD IBM PC AT compatibles Japanese WindowsNete English WindowsNete 3 5 2HC FD HP9000 Series 700 HP UXTM Rel 10 10 DAT DDS SPARCstation SunOS Rel 4 1 4 Solaris Rel 2 5 1 3 5 2HC FD 1 4 CGMT NEWS RISC NEWS OS Rel 6 1 Note Also operates under the DOS environmment 3 5 2HC FD 177 APPENDIX A DEVELOPMENT TOOLS
46. 1 Refer to Illustration Operand format saddr Label or FE80H to FF1FH immediate data saddrp Label or FE80H to FF1FH immediate data even address only Description example MOV FE90H 50H When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 O O0 O 90H saddr offset Oo 1 Oo 1 0 0 0 0 50H immediate data Illustration OP code saddr offset 7 Short Direct Memory Effective Address When 8 bit immediate data is 20H to FFH a 0 When 8 bit immediate data is OOH to 1FH a 1 51 CHAPTER 3 CPU ARCHITECTURE 3 4 3 Special function register SFR addressing Function The memory mapped special function register SFR is addressed with 8 bit immediate data in an instruction word This addressing is applied to the 240 byte spaces FFOOH to FFCFH and FFEOH to FFFFH However the SFR mapped at FFOOH to FF1FH can be accessed with short direct addressing Operand format Special function register name Description example MOV PMO A When selecting PMO for sfr Instruction code 1 1 1 0 0 1 1 1 Illustration OP code sfr offset SFR Effective Address 52 i wA j ed CHAPTER 3 CPU ARCHITECTURE 3 4 4 Register addressing Function The general register is accessed as an operand The general register to be accessed is specified with register specify code and functiona
47. 4 822 3813 Contact an NEC distributor regarding the purchase of these products 179 APPENDIX A DEVELOPMENT TOOLS A 3 2 Software ID78KOS NS Integrated debugger Supports in circuit emulator IE78KOS NS Control program for debugging 78K 0S Series This program provides a graphical user interface It runs on Windows for personal computer users and on OSF Motif for engineering work station users and has visual designs and operationability that comply with these operating systems In addition it has a powerful debug function that supports C language Therefore trace results can be displayed at a C language level by the window integration function that links source program disassembled display and memory display to the trace result This software also allows users to add other function extension modules such as task debugger and system performance analyzer to improve the debug efficiency for programs using a real time operating system Used in combination with optional device file Part number uSxxxxlD78K0S NS Remark xxxx in the part number differs depending on the host machines and operating system to be used uSxxxxID78K0S NS o Host Machine Supply Media PC 9800 Series Japanese Windows 3 5 2HD FD BBi3 English Windows SM78K0S System simulator IBM PC AT compatibles Japanese Windows 3 5 2HC FD Debugs program at C source level or assembler level while simulating operation of tar
48. 6 Based addressing Function 8 bit immediate data is added to the contents of the base register that is the HL register pair and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Description example MOV A HL 10H When setting byte to 10H Instruction code 0 O 1 0 1 1 0 1 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon generation of an interrupt request Stack addressing enables to address the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 55 MEMO 56 CHAPTER 4 PORT FUNCTIONS 4 1 Functions of Ports The uPD789014 Subseries provides the ports shown in Figure 4 1 enabling various methods of control Numerous other functions are provided that can be used in addition to the digital I O port function For more information on these additional functions refer to CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types gt PortO gt Port 1 57 CHAPTER 4 PORT FUNCTIONS Pin Name POO to P07 Input Output Input output
49. 89842 LPD789417A 12 K to 24 K LPD789407A uPD789830 uPD789840 uPD789800 uPD789810 10 bit timer 1 channel 10 Bit A D Serial Interface 1 ch UART 1 ch 2 ch E 1 ch SMB 1 ch 1 ch UART 1 ch 1 ch UART 1 ch 1 ch MIN Value 2ch USB 1 ch RC oscillator version On chip EEPROM On chip EEPROM On chip EEPROM RC oscillator version On chip EEPROM 23 CHAPTER 1 GENERAL 1 6 Block Diagram TIO TOO 8 bit TIMER P30 INTPO EVENT COUNTEROO PORTO KY P00 to P07 ROM TH TO1 8 bit TIMER P31 INTP1 EVENT COUNTERO1 PORTI 5 gt P10 to P17 WATCHDOG TIMER PORT2 CZ gt P20 to P22 SCKO ASCK P20 SERIAL RAM PORT3 K P30 to P32 SOOT DIES INTERFACEOO SIO RxD P22 RESET INTPO P30 to INTERRUPT SYSTEM us INTP2 P32 CONTROL CONTROL qu Voo Vss IC VPP Remarks 1 The internal ROM and RAM capacities vary depending on the product 2 An item in parentheses applies to the uPD78P9014 only 24 CHAPTER 1 GENERAL 1 7 Overview of Functions oes Part Number Internal memory uPD78901 1 Mask ROM uPD789012 uPD78P9014 One time PROM 2 Kbytes 4 Kbytes 8 Kbytes High speed RAM 128 bytes 256 bytes Minimum instruction execution time 0 4 us 1 6 us 5 0 MHz operation with system clock Instruction set 16 bit operation
50. 9 CHAPTER 3 CPU ARCHITECTURE 3 4 Operand Address Addressing The following various methods are available to specify the register and memory addressing which undergo manipulation during instruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format addr16 Label or 16 bit immediate data Description example MOV A FEOOH When setting addr16 to FEO0H Instruction code 0 0 1 0 1 0 0 1 OP code Illustration OP code addr16 low addr16 high Memory 50 i wA j ed CHAPTER 3 CPU ARCHITECTURE 3 4 2 Short direct addressing Function The memory to be manipulated in the fixed space is directly addressed with 8 bit data in an instruction word The fixed space where this addressing is applied to is the 160 byte space FE80H to FF1FH An internal high speed RAM and a special function register SFR are mapped at FE80H to FEFFH and FFOOH to FF1FH respectively The SFR area FFOOH to FF1FH where short direct addressing is applied is a part of all SFR areas In this area ports which are frequently accessed in a program and a compare register of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at OOH to 1FH bit 8 is set to
51. A Velizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics France S A Madrid Office Madrid Spain Tel 91 504 2787 Fax 91 504 2860 NEC Electronics Germany GmbH Scandinavia Office Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Singapore Pte Ltd United Square Singapore Tel 65 253 8311 Fax 65 250 3583 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 55 11 6462 6810 Fax 55 11 6462 6829 J00 7 Major Revisions in This Edition Modification of recommended connection of unused pins in Table 2 1 Types of Pin Input Output Circuits Modification of part of name and symbol in Table 3 4 Special Function Register List Addition of Caution in 6 2 1 8 bit compare register On CROn Modification of symbol and flag name in Figure 6 2 8 Bit Timer Mode Control Register 00 Format Modification of symbol and flag name in Figure 6 3 8 Bit Timer Mode Control Register 01 Format Modification of operation explanation in 6 4 1 Operation as interval timer Modification of operation explanation in 6 4 2 Operation as external event counter Modification of operation explanation in 6 4 3 Operati
52. A amp A v byte saddr saddr v byte AcAvr saddr byte A r A saddr A laddr16 A HL A amp A v saddr A lt A v addr16 H L A amp A v HL byte Ac Av A HL byte A byte A amp A v byte saddr saddr v byte AcAvr saddr byte A r A saddr laddr16 A amp A v saddr A amp A v addr16 A HL A HL byte A A x HL oO MD oO BR RI OD AJ OD OD oO HR KR OD RL OD aj oO BR KR OO HR aJ aj wo BR KR OO A A amp A v HL byte Remark One instruction clock cycle is one CPU clock cycle fceu selected by processor clock control register PCC 169 CHAPTER 13 INSTRUCTION SET Mnemonic Operands A byte Operation A byte saddr byte saddr byte A r A r A saddr saddr A laddr16 A HL A A addr16 A HL A HL byte A HL byte AX word AX CY AX word AX word AX CY AX word AX word AX word r rer 1 saddr saddr 1 rer 1 MO NINI MH WI WI Ww N saddr saddr 1 rp rp 1 rp rp 1 CY A amp Ao Am 1 Am x 1 CY Ao amp Az Ama Am x 1 CY lt A7 Ao CY Amn Am x 1 saddr bit CY lt Ao A CY Am 1 Am x 1 sa
53. Control Register 00 Format sssssssseseeeeenneneeeneen eene 81 6 3 8 Bit Timer Mode Control Register 01 Format sesssssssseseeeeenneneenenn eene nennen 82 6 4 Port Mode Register 3 Format inte aoa ti E E ERE SERERE caves 83 6 5 Interval Timer Operation Timing eseessesseeeseee eene nennen nennen enne nennen enne nne 85 6 6 External Event Counter Operation Timing with rising edge specified sssesssss 86 6 7 Square Wave Output Timing s dee Gis ae cette cn esee ied e nde dotes e e dd en 88 6 8 Start Timing of 8 Bit Timer Register sessssssssseeeeeeeeeneeneren nennen nennen nennen enn 89 6 9 External Event Counter Operation Timing sessseseeneeeeeneennnee nennen rennen nene 89 7 1 Block Diagram of Watchdog Timer sesssssseeeeeneneen nennen nennen nnne nnne nere 92 15 LIST OF FIGURES 2 2 Figure No Title Page 7 2 Timer Clock Select Register 2 Format ssesssssssssesessseeeeeeennne nnne nnne nnne nennen 93 7 3 Watchdog Timer Mode Register Format ssssssseeeeeeeneenenen nennen nre eren 94 8 1 Block Diagram of Serial Interface 00 sssssssssssssseseeeeeeeeennnen eene nennen nnne nnn 98 8 2 Block Diagram of Baud Rate Generator sse nennen nnne 99 8 3 Serial Operating Mode Register 00 Format ssssssssssssseeeeeeeeenee nennen rennen
54. EC ROR ROL RORC ROLC PUSH POP DBNZ 2nd Operand laddr16 HL byte addr16 1st Operand MOVNete XCHNete ADD ADDC SUB SUBC AND OR XOR CMP laddr16 PSW DE HL HL byte Note Exceptr A 172 CHAPTER 13 INSTRUCTION SET 2 16 bit instructions MOVW XCHW ADDW SUBW CMPW PUSH POP INCW DECW 2nd Operand 1st Operand M OVWhNete Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF addr16 1st Operand sfr bit saddr bit PSW bit HL bit CY 173 CHAPTER 13 INSTRUCTION SET 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand laddr16 1st Operand Basic Instructions addr5 addr16 Compound Instructions 5 Other instructions RET RETI NOP El DI HALT STOP 174 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the uPD789014 Subseries Figure A 1 shows development tools Support to PC98 NX Series Unless specified otherwise the products supported by IBM PC AT compatibles can be used in PC98 NX Series When using the PC98 NX Series refer to the explanation of IBM PC AT compatibles Windows Unless specified otherwise Windows indicates the following op
55. K input clock CMOS output Internal clock External ASCK input clock Internal clock TxD CMOS output External ASCK input clock Internal clock Other than above Setting prohibited 103 CHAPTER 8 SERIAL INTERFACE 00 Table 8 2 Serial Interface 00 Operating Mode Settings 2 2 3 3 wire serial I O mode ASIMOO CSIMOO CSIE00 DIROO CSCK00 1 Nole2 P20 Start External P22 S10 RxD Pin Function S oNote 2 P21 SO0 TxD Pin Function SOO P20 SCKO ASCK Pin Function SCKO input clock CMOS output Internal SCKO output clock SCKO input External clock Internal SCKO output clock Other than above Setting prohibited Notes 1 Can be used as port function 2 If used only for transmission can be used as P22 CMOS input output Remark x don t care 104 CHAPTER 8 SERIAL INTERFACE 00 3 Asynchronous serial interface status register 00 ASISOO This register indicates types of error when a reception error is generated in the asynchronous interface mode ASISOO is read with a 1 bit or 8 bit memory manipulation instruction The contents of ASISOO become undefined in the 3 wire serial I O mode RESET input sets ASISOO to 00H Figure 8 5 Asynchronous Serial Interface Status Register 00 Format Symbol 7 Address After
56. KOS Integrated Debugger Windows Based Reference U12901E U12901J Document for Embedded Software User s Manual Document Name Document No English Japanese 78K 0S Series OS MX78K08S U12938E U12938J Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing Other Related Documents Document Name Document No English Japanese NEC IC Package Manual CD ROM C13388E Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E C11892J Guide to Quality Assurance for Semiconductor Devices MEI 1202 Microcomputer Product Series Guide U11416J Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing MEMO 10 al d nued inue CONTENTS CHAPTER 1 GENERAL EE 19 Wel FO AUIS setifis E 19 12 Applications onc E ME 19 1 3 Ordering Information eren eere retenir Aa Ta eeraa ae aAa aaa eae TENETS 19 1 4 Pin Configuration Top View sssssssssesuuensnnnnennnnnnnnnnnnnunne
57. M to 00H Figure 7 3 Watchdog Timer Mode Register Format Symbol lt gt 6 Address After Reset R W 5 4 3 2 1 0 WDTM RN 0 0 WDTM4 WDTMS3 ENEE FFF9H 00H R W Selects Operation of Watchdog Timer e e 1 Stops counting Clears counter and starts counting Operation stop Interval timer mode overflow occurs and maskable interrupt occurs Nete 3 Watchdog timer mode 1 overflow occurs and non maskable interrupt occurs Watchdog timer mode 2 overflow occurs and reset operation started Notes 1 Once RUN has been setto 1 it cannot be cleared to 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set to 1 they cannot be cleared to 0 by software 3 The watchdog timer starts operations as an interval timer when RUN is set to 1 Cautions 1 When the watchdog timer is cleared by setting 1 to RUN the actual overflow time is up to 0 8 shorter than the time set by the timer clock select register 2 TCL2 2 In watchdog timer mode 1 or 2 set WDTMA to 1 after confirming the TMIFA bit 0 of interrupt request flag 0 IF0 being set to 0 When watchdog timer mode 1 or2 is selected under the condition where TMIFA is 1 a non maskable interrupt occurs at the completion of rewriting 94 CHAPTER 7 WATCHDOG TIMER 7 4 Operation of Watchdog Timer 7 4 1 Operation as watchdog timer The watchdog timer detects a pr
58. MO INTP1 INTTM1 INTP2 2 CALLT instruction table area In a 64 byte area of addresses 0040H to 007FH the subroutine entry address of a 1 byte call instruction CALLT can be stored 36 i ri oY o ed CHAPTER 3 CPU ARCHITECTURE 3 1 2 Internal data memory internal high speed RAM space The uPD789014 Subseries provide internal high speed RAM containing the following capacities on each product The internal high speed RAM can also be used as a stack memory Table 3 3 Internal High Speed RAM Capacity Part Number Capacity uPD789011 128 x 8 bits uPD789012 uPD78P9014 256 x 8 bits 3 1 3 Special function register SFR area Special function registers SFRs of on chip peripheral hardware are allocated to an area of FFOOH to FFFFH refer to Table 3 4 37 CHAPTER 3 CPU ARCHITECTURE 3 1 4 Data memory addressing The uPD789014 Subseries provide a variety of addressing modes which take account of memory manipulability etc Especially at addresses corresponding to data memory area FE80H to FFFFH particular addressing modes are possible to meet the functions of the special function registers SFR and general registers Figures 3 4 through 3 6 show the data memory addressing modes Figure 3 4 Data Memory Addressing uPD789011 FFFFH Special Function Registers SFR SFR Addressing 256 x 8 bits FF20H oto nS ote L Rs FF1FH 4 FFOOH FEFFH Internal
59. MO1 count values Interrupt request flag 00H 00H 00H 00H 89 MEMO 90 CHAPTER 7 WATCHDOG TIMER 7 1 Functions of Watchdog Timer The watchdog timer has the following functions Watchdog timer nterval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register WDTM 1 Watchdog timer The watchdog timer is usedto detect program runaway When a runaway is detected a non maskable interrupt or the RESET signal can be generated Table 7 1 Runaway Detection Time of Watchdog Timer Runaway Detection Time At fx 5 0 MHz 2 x 1 fx 21 x 1 fx 275 x 1 fx 2 x 1 fx fx system clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at a given interval set in advance Table 7 2 Interval Time Interval Time At fx 5 0 MHz 2 x 1 fx 21 x 1 fx 215 x 1 fx 2 x 1 fx fx system clock oscillation frequency 91 CHAPTER 7 WATCHDOG TIMER 7 2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware Table 7 3 Configuration of Watchdog Timer Control register Timer clock select register 2 TCL2 Watchdog timer mode register WDTM Figure 7 1 Block Diagram of Watchdog Timer Internal bus fx 24 Prescaler INTWDT maskable interrupt request 7 bit counter Control RESET circuit INTWD
60. P30 INTPO TIO P31 INTP1 TI1 Input System reset input Input Connecting crystal resonator for system clock oscillation Positive power supply High voltage applied during program write verify Connect directly to Vss in normal operating mode Ground potential Note Internally connected Connect directly to Vss 2 1 2 Pins in PROM programming mode Pin Name Input Output Function Connect to Vss Pin input from Schmitt trigger refer to Type 5 D of Figure 2 1 Pin Input Output Circuits PROM programming mode setting and high voltage applied during program write verify When 45 5 V and 12 5 V are applied to Voo and Ve pins respectively PROM programming mode is set MDO to MD3 Input output Operating mode selected in PROM programming mode DO to D7 Input output Data bus Input Address update clock input in PROM programming mode PROM programming mode setting and positive power supply 28 Ground potential CHAPTER 2 PIN FUNCTIONS 2 2 Description of Pin Functions 2 2 1 POO to P07 Port 0 These pins constitute an 8 bit I O port and can be set in the input or output port mode in 1 bit units by using port mode register 0 PMO When these pins are used as an input port an on chip pull up resistor can be used in the pull up resistor option register PUO LEDs can be driven directly 2 2 2 P10 to P17 Port 1 Thes
61. PD78P9014 12 1 2 Program memory write procedure Program memory is written by the following procedure High speed writing is possible a Pull down unused pins to Vss via a resistor Fix the X1 pin at low level 1 2 Supply 5 V to the Voo and Vr pins 3 10 us wait 4 Program memory address 0 clear mode 5 Supply 5 5 V to Voo and 12 5 V to Vp 6 Write data with 1 ms write mode 7 Verify mode Proceed to step 8 if write was performed or repeat steps 6 7 if write was not performed 8 X Number of writes in steps 6 7 x 1 ms additional write 9 Program memory address incremented 1 through input of 4 pulses to X1 pin 10 Repeat steps 6 to 9 until last address 11 Program memory address 0 clear mode 12 Change Vp and VPP pins voltage to 5 V 13 Power off Steps 2 to 9 of the above procedure are shown in the figure below Repeat X times c s Address Write Verify Additional write increment e lt gt X1 UU DO to D7 ete Data Input EE i aon 9t x zw MD1 N m MD2 A N c0 m MD3 A o a 161 CHAPTER 12 uPD78P9014 12 1 3 Program memory read procedure Program memory is read by the following procedure Pull down unused pins to Vss via a resistor Fix the X1 pin at low level 1 2 Supply 5 V to the Von and Vr pins 3 10 us wait 4 Program memory address 0 clear mode 5 Supply 5
62. R is generated If an error is generated the receive data in which the error was generated is still transferred to RXBOO and INTSR is generated If the RXEOO bit is reset 0 during the receive operation the receive operation is stopped immediately In this case the contents of RXBOO and asynchronous serial interface status register 00 ASISOO are not changed and INTSR is not generated Figure 8 9 Asynchronous Serial Interface Reception Completion Interrupt Timing START INTSR Caution Be sure to read the receive buffer register 00 RXBOO even if a receive error occurs If RXBOO is not read an overrun error will be generated when the next data is received and the receive error state will continue indefinitely CHAPTER 8 SERIAL INTERFACE 00 e Receive errors The following three errors may occur during a receive operation a parity error framing error or overrun error The data reception result error flag is set in the asynchronous serial interface status register 00 ASISO0 Receive error causes are shown in Table 8 7 It is possible to determine what kind of error was generated during reception by reading the contents of ASISOO in the reception error interrupt servicing see Figures 8 9 and 8 10 The contents of ASISOO are reset 0 by reading the receive buffer register 00 RXBOO or receiving the next data if there is an error in the next data the corresponding error flag is set Table 8 7 Receive Error Causes
63. R EVENT COUNTER Modification of symbol and flag name of serial operating mode register 00 and addition of Caution regarding transmit receive operation Modification of symbol and flag name of asynchronous serial interface mode register 00 and addition of Caution regarding transmit operation Modification of description of 1 bit memory manipulation instruction enabled in asynchronous serial interface status register 00 Modification of symbol and flag name of asynchronous serial interface status register 00 Addition of description regarding transmit operation and description regarding read operation of RXBOO register in asynchronous serial interface UART mode Addition of description regarding transmit receive operation in 3 wire serial I O mode CHAPTER 8 SERIAL INTERFACE 00 Modification of flag name of interrupt request flag register 0 Modification of flag name of interrupt mask flag register 0 CHAPTER 9 INTERRUPT FUNCTIONS Addition of Caution for replacing PROM version with mask ROM version CHAPTER 12 uPD78P9014 Addition of Solaris to operating system of language processing software Addition of PA 17K DZ to PROM programmer adapter Modification of PC card interface name and addition of IE 70000 PCI IF to interface adapter APPENDIX A DEVELOPMENT TOOLS 187 MEMO 188 CAMI Message From Name Company Tel FAX Although NEC has tak
64. ROO and CRO1 the values of TM00 and TMO1 are cleared to 0 and TMOO and TMO1 continue counting At the same time an interrupt request signal INTTMO and INTTM1 is generated Figure 6 6 shows the timing of the external event counter operation with rising edge specified Caution When the count clock and TMOn operation enable are set simultaneously with TMCOn using the 8 bit memory manipulation instruction the error of a cycle from which a timer has been started may become one clock or more Therefore settings must be done in the above order to operate the 8 bit timer event counter as an external event counter Remark n Q 1 Figure 6 6 External Event Counter Operation Timing with rising edge specified tapes i ab SE PB E RESI ESTEE EE TMOncountvaue o0 X 01 X o2 X os X 04 X o5 X AN 1X N A00 X 0 X 02 X o3 X CROn ey ee i 5 TCEOn Ed INTTMn Remarks 1 N 00H to FFH 2 n 0 1 86 CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 4 3 Operation as square wave output The 8 bit timer event counter can generate output square waves of a given frequency at intervals specified by the count value set to the 8 bit compare registers 00 and 01 CROO and CRO01 in advance To operate the 8 bit timer event counter for square wave output the settings are required in the following order 1 Set P30 and P31 to output mode PM30 0 PM31 0 and set output latches of P30 and P31 to 0 2 Set the 8 bit timer
65. RXBOO holds the previous data and does not generate INTSR When RXEOO is set to 0 at a time indicated by 2 RXBOO renews the data and does not generate INTSR When RXEOO is set to 0 at a time indicated by 3 RXBOO renews the data and generates INTSR CHAPTER 8 SERIAL INTERFACE 00 i PI P Y o j ed c Ifthe operation is interrupted TXEOO 0 during data transmission P21 which is the alternate function I O port pin of TxD cannot be used as a general purpose output port Therefore do not clear the transmit operation enable flag TXE00 0 during data transmission in the transmit operation enabled state TXEOO 1 When switching to the general purpose output port clear the transmit operation enable flag TXEOO 0 upon completion of data transmission An example of a program switching to the general purpose output portfollowing UART transmit completion is shown below MOV MOV MOV WAIT BF CLR1 CSIMOO 00H BRGCOO 40H Baud rate 9600 bps ASIMOO 88H Character length 8 bits Stop bit length STIFOO WAIT TXEOO dbit no parity d Upon occurrence of INTSR if the RXBOO register has been read before the clock shown in Table 8 8 from the start of this interrupt routine an overrun error is generated To read the receive data do so after letting the number of clocks indicated in Table 8 8 elapse prior to reading RXBOO Table 8 8 Number of Clocks Required to Read RXBOO Re
66. S PC7 to PCO n Owen riali as PC7 to PCO SP 2 PC15 to PC8 Register Pairs i n SP 1 Hp UR SP 1 PC15 to PC8 SP 1 PSW i SP SP gt SP gt Figure 3 11 Data to be Restored from Stack Memory POP rp RET Instruction RETI Instruction Instruction gpa Wer EE SP PC7toPCO SP PC7 to PCO Register Pairs Upper Half SP Register Pairs SHE posto EGS SP1 PC15 to PC8 SP SP 2 SP SP 2 SP 2 PSW SP SP 3 43 CHAPTER 3 CPU ARCHITECTURE 3 2 2 General registers A general register consists of eight 8 bit registers X A C B E D L and H In addition that each register can be used as an 8 bit register two 8 bit registers in pairs can be used as a 16 bit register AX BC DE and HL They can be described in terms of functional names X A C B E D L H AX BC DE and HL and absolute names RO to R7 and RPO to RP3 Figure 3 12 General Register Configuration a Absolute Names 16 Bit Processing 8 Bit Processing RP3 RP2 RP1 b Functional Names 16 Bit Processing 8 Bit Processing HL AX 44 CHAPTER 3 CPU ARCHITECTURE 3 2 3 Special function register SFR Unlike a general register each special function register has a special function It is allocated in the 256 byte area FFOOH to FFFFH The special function register can be manipulated like the general register with t
67. T non maskable interrupt request Selector WDTM4 WDTM3 Pee TCL22 TCL20 Timer clock select register 2 Watchdog timer mode register WDTM TCL2 92 CHAPTER 7 WATCHDOG TIMER 7 3 Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with an 8 bit memory manipulation instruction RESET input sets TCL2 to 00H Figure 7 2 Timer Clock Select Register 2 Format Symbol 7 6 5 Address After Reset R W 4 3 2 1 0 TCL2 fo o o o o rcu TCL21 TCL20 FF42H 00H R W TCL21 TCL20 Watchdog Timer Count Clock Selection Interval Time fx 24 312 5 kHz 2 fx 410 us fx 2 78 1 kHz 213 fx 1 64 ms fx 28 19 5 kHz 215 fx 6 55 ms fx 210 4 88 kHz 217 fx 26 2 ms Other than above Setting prohibited Remarks 1 fx system clock oscillation frequency 2 Figures in parentheses apply to operation when fx 5 0 MHz 93 i ri oY a ed CHAPTER 7 WATCHDOG TIMER 2 Watchdog timer mode register WDTM This register sets an operation mode of the watchdog timer and enables disables counting of the watchdog timer WDTM is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets WDT
68. Timing by RESET Input in STOP Mode sssseete tette tete tenens 156 A 1 Development Tools 2 aaa Ee a e tete aa Da P ERE RE be ede 176 16 LIST OF TABLES 1 2 Table No Title Page 2 1 Types ot Pin Input Output Circuits 2 iot rt DR ERE IR E REGE GERE tal 32 3 1 Internal ROM Capacity 5 1 ono etit iere terit fedt dena uite ee coc 36 3 2 Vector Table eme 36 3 3 Internal High Speed RAM Capacity sessssssessssseeeeeeneee eene enne nnne nennt nennen nnns 37 3 4 Sp cial Function Register List 5 ea eedem etd ire Rte AER e 46 4 1 Port FURlctions 35 nono Net terme Deut osea vies 58 4 2 Port Config ratiori 2 2 5 wa ae Ae ig e LIC ee Ce e dee cepe det ER e LE Cae doe ed 59 4 3 Port Mode Register and Output Latch Settings When Using Alternate Functions 66 5 1 Configuration of Clock Generator sss eene nren nene tnne enne nnne tenens 69 5 2 Maximum Time Required for Switching CPU Clock eeeeeeeeeenene nennen 75 6 1 Interval Time of 8 Bit Timer Event Counter sssssssseseeeeeeeeenenennen nennen 78 6 2 Square Wave Output Range of 8 Bit Timer Event Counter sesssssssssseeeeeen 78 6 3 8 Bit Timer Event Counter Configuration esssssssssesseeeeeenen nennen nennen nnne 79 6 4 Interval Time of 8 Bit Timer Event Counter essssssseeeeeeeeen nennen 84 6 5 Square Wav
69. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is
70. VO port 22 lines Serial interface 1 channel 3 wire serial I O mode UART mode selection O Timer 3 channels 8 bit timer event counter 2 channels Watchdog timer 1 channel O Vectored interrupt source 9 Supply voltage Voo 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C 1 2 Applications Small home appliances remote controls video games etc 1 3 Ordering Information Part number Package Internal ROM uPD789011CT xxx 28 pin plastic shrink DIP 400 mil Mask ROM uPD789011GT xxx 28 pin plastic SOP 375 mil Mask ROM LPD789012CT xxx 28 pin plastic shrink DIP 400 mil Mask ROM uPD789012GT xxx 28 pin plastic SOP 375 mil Mask ROM LPD78P9014CT 28 pin plastic shrink DIP 400 mil One time PROM uPD78P9014GT 28 pin plastic SOP 375 mil One time PROM Remark xxx indicates ROM code suffix 19 CHAPTER 1 GENERAL 1 4 Pin Configuration Top View 1 Normal operating mode 28 pin plastic shrink DIP 400 mil LuPD789011CT xxx 789012CT xxx and 78P9014CT 28 pin plastic SOP 375 mil LuPD789011GT xxx 789012GT xxx and 78P9014GT P31 INTP1 TH TO1 O P3O0 INTPO TIO TOO P32 INTP2 O P22 RxD SIO IC VPP O P21 TxD SOO RESET P20 ASCK SCKO X20 Q P17 X10 O P16 Vss O O P15 Voo O O P14 P00 O O P13 P01 O P12 P02 P11 P03 P10 P04 O P07 P05 QO O P06 Caution Connect IC directly to Vss Remark uPD78P9014 ASCK Asynchronous Serial Clock SCKO Serial
71. W instructions RESET input sets PSW to 02H Figure 9 5 Program Status Word Configuration Symbol 7 6 5 4 3 2 1 0 After Reset 138 02H Used when normal instruction is executed Interrupt Acknowledge Enable Disable 0 Disable 1 Enable i PY SY o ed CHAPTER 9 INTERRUPT FUNCTIONS 9 4 Interrupt Processing Operation 9 4 1 Non maskable interrupt request acceptance operation The non maskable interrupt request is unconditionally accepted even when interrupts are disabled Itis not subject to interrupt priority control and takes precedence over all other interrupts When the non maskable interrupt request is acknowledged PSW and PC are saved to the stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 9 6 shows the flowchart from non maskable interrupt request generation to acceptance Figure 9 7 shows the timing of non maskable interrupt request acceptance Figure 9 8 shows the acceptance operation if multiple non maskable interrupts are generated Caution During a non maskable interrupt service program execution do not input another non maskable interrupt request if it is input the service program will be interrupted and the new non maskable interrupt request will be acknowledged 139 CHAPTER 9 INTERRUPT FUNCTIONS Figure 9 6 Flowchart from Non Maskable Interrupt Request Generation to
72. another interrupt is accepted while an interrupt is processed can be processed by priority When the priority is controlled by the default priority and two or more interrupts are generated at once interrupt processing is performed according to the priority assigned to each interrupt request in advance refer to Table 9 1 143 CHAPTER 9 INTERRUPT FUNCTIONS Figure 9 12 Example of Multiplexed Interrupt Example 1 Multiplexed interrupt is accepted Main processing INTxx processing INTyy processing During interrupt INTxx servicing interrupt request INTyy is accepted and a multiple interrupt is generated An El instruction is issued before each interrupt request acceptance and the interrupt request acceptance enable state is set Example 2 A multiple interrupt is not generated because interrupts are not enabled Main processing INTxx processing INTyy processing IE 0 INTyy INTyy is kept pending RETI INTxx IE 20 RETI Because interrupts are not enabled in interrupt INTxx servicing an El instruction is not issued interrupt request INTyy is not accepted and a multiple interrupt is not generated The INTyy request is reserved and accepted after the INTxx processing is performed IE 0 Interrupt request acceptance disabled 144 CHAPTER 9 INTERRUPT FUNCTIONS 9 4 4 Interrupt request reserve Some instructions may reserve the acceptance of an instruction request until the completion
73. ate transmit receive clock by means of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is found from the following expression fasck Baud rate Hz 16 Hz fasck frequency of clock input to ASCK pin Table 8 6 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGCOO is set to 80H Baud Rate bps ASCK Pin Input Frequency kHz al Mie CHAPTER 8 SERIAL INTERFACE 00 2 Communication operation a Data format The transmit receive data format is as shown in Figure 8 7 One data frame consists of a start bit character bits parity bit and stop bit s The specification of character bit length parity selection and specification of stop bit length for each data frame is carried out with asynchronous serial interface mode register 00 ASIMOO Figure 8 7 Asynchronous Serial Interface Transmit Receive Data Format P One Data Frame gt el o Fay Start bit 00 1 bit e Character bits 7 bits 8 bits e Parity bits Even parity odd parity O parity no parity Stop bit s 1 bit 2 bits When 7 bits are selected as the number of character bits only the lower 7 bits bits O to 6 are valid in transmission the most significant bit bit 7 is ignored and in
74. bit 1 2 bits Cautions 1 Be sure to set 0 to bits 0 and 1 2 Switching operation modes must be performed after serial transmit receive operation is halted 126 i ri oY o ed CHAPTER 8 SERIAL INTERFACE 00 c Baud rate generator control register 00 BRGCOO BRGCOO is set with an 8 bit memory manipulation instruction RESET input sets BRGCOO to 00H Symbol 7 6 5 4 Address After Reset R W 3 2 1 0 BRGC00 TPson3 TPS002 TPS001 ts 0 0 o o FF73H 00H RW PS000 3 Bit Counter Source Clock Selection n fx 2 2 5 MHz fx 22 1 25 MHz fx 23 625 kHz fx 24 313 kHz fx 25 156 kHz fx 28 78 1 kHz fx 27 39 1 kHz fx 28 19 5 kHz Other than above Setting prohibited Cautions 1 When writing to BRGCOO is performed during a communication operation the baud rate generator outputis disrupted and communications cannot be performed normally Be sure not to write to BRGCOO during communication operation 2 Be sure not to select n 1 during an operation at fx 5 0 MHz because n 1 exceeds the baud rate limit Remarks 1 fx system clock oscillation frequency 2 Figure in parentheses applies to operation when fx 5 0 MHz If the internal clock is used as the serial clock for the 3 wire serial I O mode set the TPS000 to TPS003 bits to set the frequency of the serial clock To obtain the frequency to be set use the following formula When the
75. c Asynchronous serial interface status register 00 ASISOO ASISOO is read with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASISOO to OOH Symbol 7 Address After Reset R W oe o o o o o enen e c on Parity error not generated Parity error generated when the parity of transmit data does not coincide FE00 Flaming Error Flag Framing error not generated Framing error generated when stop bit is not detected e e 1 Overrun error not generated Overrun error generatedN gt te2 when the next receive operation is completed before the data is read from the receive buffer register Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SLOO of the asynchronous serial interface mode register 00 ASIMOO the stop bit detection in the case of reception is performed with 1 bit 2 When an overrun error occurs be sure to read out the receive buffer register 00 RXBO00 Unless RXBOO is read out overrun errors occur at each data reception 113 CHAPTER 8 SERIAL INTERFACE 00 d Baud rate generator control register 00 BRGCOO BRGCOO is set with an 8 bit memory manipulation instruction RESET input sets BRGCOO to 00H Symbol 7 6 5 4 Address After Reset R W 3 2 1 0 oco remp o v o o rw c nw PS000 3 Bit Counter Source Clock Selection n fx 2 2 5 MHz fx 22 1 25 MHz fx 23 625 kHz fx 2 313 kHz fx 25 156 kHz fx 28 78 1 kHz
76. ce equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
77. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electr
78. ction execution Stop status Reset period Oscillation During normal operation lt oscillation oscillation m stabilization due operation stops stops time wait reset processing Jen PER RESET i l i xy Internal l i l reset signal Ae Delay Delay 156 CHAPTER 11 RESET FUNCTION Table 11 1 Hardware Status after Reset Hardware Status after Reset Program counter PC Nete 1 The contents of reset vector tables 0000H and 0001H are set Stack pointer SP Undefined Program status word PSW 02H RAM Data memory Undefinedgete 2 General register Undefinedgete 2 Port PO to P3 Output latch 00H Port mode register PMO to PM3 FFH Pull up resistor option register PUO 00H Processor clock control register PCC 02H Oscillation stabilization time select register OSTS 04H 8 bit timer event counter Timer register TMOO TMO1 00H Compare register CROO CRO1 Undefined Mode control register TMC00 TMC01 00H Watchdog timer Timer clock select register TCL2 00H Mode register WDTM 00H Serial interface Mode register CSIMOO 00H Asynchronous serial interface mode register ASIMOO 00H Asynchronous serial interface status register ASISOO 00H Baud rate generator control register BRGCOO
79. dapter emulation probe and interface adapter for connecting the host machine IE 70000 MC PS B AC adapter This is the adapter for supplying power from AC 100 V outlet IE 70000 98 IF C Interface adapter This adapter is needed when PC 9800 Series excluding notebook type is used as a host machine of IE 78K0S NS C bus supported IE 70000 CD IF ANete 1 PC card interface This PC card and interface cable are needed when a PC 9800 Series notebook type personal computer is used as a host machine of IE 78K0S NS PCMCIA socket supported IE 70000 PC IF C Interface adapter This adapter is needed when IBM PC AT compatibles are used as a host machine of IE 78K0S NS ISA bus supported IE 70000 PCI IFNote 1 Interface adapter This adapter is needed when a personal computer incorporating PCI bus is used as a host machine of IE 78KOS NS IE 789014 NS EM1 Emulation board Emulation board for emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator NP 28CTNete 2 Emulation probe Emulation probe for connecting the in circuit emulator and target system This is for 28 pin plastic shrink DIP NP 28GTNote 2 Emulation probe Emulation probe for connecting the in circuit emulator and target system This is for 28 pin plastic SOP Notes 1 Under development 2 The NP 28CT and NP 28GT are the products of Naitou Densei Machidaseisakusho Co Ltd 81 4
80. ddr A A sfr A c sfr sfr A sfr A A laddr16 A amp addr16 laddr16 A addr16 A PSW byte PSW c byte A PSW A PSW PSW A M N J jJ o N N N NINI N oj vj a PSW amp A A DE A DE DE A DE A A HL a A HL HL A HL A A HL byte A HL byte HL byte A N N HL byte A Notes Remark One instruction clock cycle is one CPU clock cycle fceu selected by processor clock control register A X Aox A Note 2 Aor A saddr A saddr A sfr A sfr A DE A e DE A HL A e HL A HL byte 1 Except r A 2 Except r A X PCC ojoj OO OD OD OD HILO DA OD ajoj oOo HR HRI OD oj o HR BR HR HR HR HR OD oO oa A HL byte CHAPTER 13 INSTRUCTION SET Mnemonic Operands Operation rp word AX saddrp rp word AX lt saddrp saddrp AX AX rpNete saddrp AX AX amp rp rp AXNete rp AX AX rpNete AX rp A CY A byte A byte saddr byte A r saddr CY lt saddr byte A CYc A r A saddr A laddr16 A CY A saddr A CY A addr16 A HL A HL byte A CY A HL A CY A HL byte A byte A
81. ddr bit 1 sfr bit sfr bit 1 A bit A bit 1 PSW bit o 5 oljlo m m rm rm al al al alalalalalalaloa o alalo a PSW bit 1 HL bit A o HL bit 1 saddr bit saddr bit 0 sfr bit sfr bit 0 A bit A bit 0 PSW bit ao A a PSW bit 0 HL bit PO wo nm wo wo wo WO N W Ww E o HL bit 0 CY CY lt 1 CY CY 0 CY Remark One instruction clock cycle is one CPU clock cycle fcru selected by processor clock control register PCC 170 MNI N N CY CY CHAPTER 13 INSTRUCTION SET Mnemonic Operands laddr16 Operation SP 1 PC 3 u SP 2 PC 3 PC addr16 SP SP 2 addr5 SP 1 PC t u SP 2 PC 1 L PCx 00000000 addr5 1 PC 00000000 addr5 SP SP 2 PCH SP 1 PCL SP SP e SP 2 PCH SP 1 PCL SP PSW c SP 2 SP SP 3 NMIS 0 PSW SP 1 PSW SP e SP 1 rp SP 1 rpu SP 2 rp SP SP 2 PSW PSW c SP SP SP 1 rp rpH SP 1 rp SP SP SP 2 SP AX SP AX AX SP AX SP laddr16 PC addri6 addr16 pO oO NIN PC amp PC 2 jdisp8 AX PCH A PCL e X saddr16 PC PC 2 jdisp8 if CY
82. de the time from STOP mode release to clock oscillation start a in the figure below regardless of release by RESET input or by interrupt generation STOP mode release de Remarks 1 fx system clock oscillation frequency X1 Pin Voltage Waveform Vss 2 Figures in parentheses applies to operation when fx 5 0 MHz 148 CHAPTER 10 STANDBY FUNCTION 10 2 Operation of Standby Function 10 2 1 HALT mode 1 HALT mode The HALT mode is set by executing the HALT instruction The operation status in the HALT mode is shown in the following table Table 10 1 HALT Mode Operating Status Item HALT Mode Operating Status Clock generator Enables system clock oscillation Stops clock supply to CPU CPU Stops operation Port Output latch Retains the status before setting the HALT mode 8 bit timer event counter Enables operation Watchdog timer Enables operation Serial interface Enables operation External interrupt Enables operation 149 i PY SY o ed CHAPTER 10 STANDBY FUNCTION 2 Releasing HALT mode The HALT mode can be released by the following three types of sources a Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request In this case if the interrupt request is enabled to be accepted vectored interrupt processing is performed If the interrupt is disabled the instruction at the next address is executed
83. ders Purpose Organization How to Read This Manual Conventions al Mie INTRODUCTION This manual is intended for user engineers who understand the functions of the uPD789014 Subseries to design and develop its application systems and programs Thetargetsubseriesisthe uPD789014 Subseries which consists ofthe uPD789011 789012 and 78P9014 This manual is designed to deepen your understanding of the following functions using the following organization Two manuals are available for the u PD789014 Subseries this manual and Instruction Manual common to the 78K 0S Series 78K 0S Series LPD789014 Subseries User s Manual User s Manual Instruction Pin functions CPU function Internal block functions Instruction set Interrupt Instruction description Other internal peripheral functions It is assumed that the readers of this manual have general knowledge on electrical engineering logic circuits and microcontrollers To understand the overall functions of the uPD789014 Subseries Read this manual in the order of the CONTENTS How to read register formats The name of a bit whose number is in brackets is reserved for the assembler and is defined for the C compiler by the header file sfrbit h To learn the detailed functions of a register whose register name is known Refer to APPENDIX C REGISTER INDEX To learn the details of the instruction functions
84. e Output Range of 8 Bit Timer Event Counter sssssssseseeeeereene 87 7 1 Runaway Detection Time of Watchdog Timer ssseeenenneem ener 91 7 2 Interval meissie meae etate ec obe nexu Pt tetas aca eat evade c UM Lebe ae teeta ces 91 7 3 Configuration of Watchdog Timer sssssssssseeeeeneeeeenene nnne nnne nnne nnn enre nnne nnns 92 7 4 Runaway Detection Time of Watchdog Timer cee ceeesceeeneeeeeneeeeeeaeeeeeeeetenaeeeeeneeeeneaeesesaeeeeeneeeegs 95 7 5 Interval Time of Interval Timer 1 iet UG RR eH ee REDEEM eina 96 8 1 Serial Interface 00 Configuration sessessssseseeeseeeee enne nennen nennen rennen enne nn nnne nennen 97 8 2 Serial Interface 00 Operating Mode Settings ssssssssssseseeeeenen nennen 103 8 3 Example of Relationship between System Clock and Baud Rate sssssssssssesses 107 8 4 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGCOO is set to 80H 108 8 5 Example of Relationship between System Clock and Baud Rate sssssssee 115 8 6 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGCOO is set to 80H 116 8 7 Receive Error Causes Lee RR Revenir dee c YR e edere eaea an aer wees 121 8 8 Number of Clocks Required to Read RXBOO Register sssssseeeeeeneneeeneenen 123 9 1 Interrupt Source List 0202 5 de hn a duit ea D ai del ne etat b 132 9 2 Flags Corresponding to In
85. e an instruction clock n n 4 to 10 under execution becomes n 1 the interrupt is accepted after the instruction under execution completes Figure 9 10 shows an example of the interrupt request acceptance timing for an 8 bit data transfer instruction MOV A r Since this instruction is executed for 4 clocks if an interrupt occurs for 3 clocks after the execution starts the interrupt acceptance processing is performed after the MOV A r instruction is completed Figure 9 11 Interrupt Request Acceptance Timing When interrupt request flag generates at the last clock during instruction execution 8 clocks Sec Spp ST Tp E T E ES ES EST pese spe es al i j Interrupt Saving PSW and PC jump t CPU NOP MOV A r to interrupt processing processing Interrupt If an interrupt request flag xxIF is set at the last clock of the instruction the interrupt acceptance processing starts after the next instruction is executed Figure 9 11 shows an example of the interrupt acceptance timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction In this case the MOV A r instruction after the NOP instruction is executed and then the interrupt acceptance processing is performed Caution Interrupt requests are reserved while the interrupt request flag register 0 IFO or the interrupt mask flag register 0 MKO is being accessed 9 4 3 Multiplexed interrupt processing Multiplexed interrupt processing in which
86. e assembler specifications for detail When there are two or more description methods select one of them Alphabetic letters in capitals and symbols and are key words and are described as they are Each symbol has the following meaning Immediate data specification Absolute address specification e Relative address specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parenthesis in the table below RO R1 R2 etc can be used for description Table 13 1 Operand Identifiers and Description Methods Identifier Description Method r X RO A R1 C R2 B R3 E R4 D R5 L R6 H R7 rp AX RPO BC RP1 DE RP2 HL RP3 sfr Special function register symbol saddr FE80H to FF1FH Immediate data or labels saddrp FE80H to FF1FH Immediate data or labels even addresses only addr16 0000H to FFFFH Immediate data or labels only even addresses for 16 bit data transfer instructions addr5 0040H to 007FH Immediate data or labels even addresses only word 16 bit immediate data or label byte 8 bit immediate data or label bit 3 bit immediate data or label Remark Refer to Table 3 4 Special Function Register List for symbols of special fu
87. e operation sesseenem eee 141 9 4 3 Multiplexed interrupt processing eeeseeeeeseeseeeeeeeeenene nennen nnnm nennen nnne 143 9 4 4 Interrupt request reserve esseesesesseesseeseseeene nennen einen nennen nnn en there nen enitn retenti nnne 145 CHAPTER 10 STANDBY FUNCTION eeeeeeeeeeeeeeeeen eene nnn nn nnn nn nnns nnne nnn nn nnne sensn nnne nn nnn 147 10 1 Standby Function and Configuration eeeeeeeeeeeeeeeeseeee enne nennen 147 10 171 Standby function c i RR etn etate ere d etc 147 10 1 2 Standby function control register ssssssseeeneeeennennee nennen nennen 148 10 2 Operation of Standby Function eeeeeeseeseseeeeeeeee eese nennen nnnm a nnne tassa annt 149 10 251 HALT Ode ie 3 vt ene etd teta E cee e ante E te 149 10 2 2 STOP mode uidet tei e feb eB Ee telum aus 152 CHAPTER 11 RESET FUNCTION 1 eccL Leeeee ccc eeee een s creada nnnm Dra aaa nn e Dc mE aane cr cran nnana nnen 155 CHAPTER 12 PD78P9014 inre uL cec ae eco caua oe ea cue Row E D cu nou Eae hanana ra cH De aK DERE 159 121 PROM Programmitg 225r ete iore intei tete eterne ae eee Eeoa Daaa Eusa 160 12 1 1 Operating MODES 5 05520 det e EP DR E 160 12 1 2 Program memory write procedure sesssseseeeeeeeeeeneneee mener nere 161 12 1 3 Program memory read procedure
88. e operation control flag CSIEOO0 until transmit receive ends To stop the 3 wire serial I O mode clear the operation control flag CSIEO0 0 after transmitting FFH once Moreover clear the transmit operation enable flag TXE00 0 after transmitting FFH as a UART mode transmission An example of a program for stopping the 3 wire serial I O mode is shown below Example 1 Transmission in 3 wire serial I O mode MOV CSIMOO 02H MOV BRGCODO 00H MOV ASIMOO 80H MOV TXS00 0FFH CLR1 CSIEO0 128 CHAPTER 8 SERIAL INTERFACE 00 3 When TXS00 is written to the SOO pin immediately becomes high level after 4 clocks However a clock rides the SCKO clock signal Example 2 Transmission in UART mode MOV CSIMOO 00H MOV BRGCOO 00H MOV ASIMOO 80H MOV TXS00 0FFH CLR1 TXEOO After 16 to 32 clocks following writing to TXSOO the SOO pin becomes high level By using this method the SCKO pin remains low level Transfer start Serial transfer is started by setting transfer data to the transmit shift register 00 TXS00 SIO00 when the following two conditions are satisfied e Serial operating mode register 00 CSIMOO bit 7 CSIEO0 1 Internal serial clock is stopped or SCKO is a high level after 8 bit serial transfer Caution If CSIEOO is set to 1 after data write to TXS00 SIOOO transfer does not start A termination of 8 bit transfer stops the serial transfer automatically and generates the interrupt
89. e pins constitute an 8 bit I O port and can be set in the input or output port mode in 1 bit units by using port mode register 1 PM1 When these pins are used as an input port an on chip pull up resistor can be used in the pull up resistor option register PUO LEDs can be driven directly 2 2 3 P20 to P22 Port 2 These pins constitute a 3 bit I O port In addition these pins provide the function to input output the data and clock of the serial interface LEDs can be driven directly Port 2 can be specified in the following operation modes in 1 bit units 1 Port mode In this mode port 2 functions as a 3 bit I O port which can be set in the input or output port mode in 1 bit units by using the port mode register 2 PM2 When the port is used as an input port an on chip pull up resistor can be used in the pull up resistor option register PUO 2 Control mode In this mode the pins of port 2 function as the data input output and the clock input output of the serial interface a SIO SOO These are the serial data I O pins of the serial interface b SCKO This is the serial clock I O pin of the serial interface c RxD TxD This is the serial data I O pin of asynchronous serial interface d ASCK This is the serial clock input pin of asynchronous serial interface Caution When using P20 through P22 as serial interface pins the I O or output latch must be set according to the functions to be used For the details of
90. eans of external clock from ASCK pin The transmit receive clock is generated by scaling the clock input from the ASCK pin The baud rate generated from the clock input from the ASCK pin is found from the following expression Baud rate D Hz fasck frequency of clock input to ASCK pin Table 8 4 Relationship between ASCK Pin Input Frequency and Baud Rate When BRGCOO is set to 80H Baud Rate bps ASCK Pin Input Frequency kHz 108 CHAPTER 8 SERIAL INTERFACE 00 nu ed 8 4 Serial Interface 00 Operation Serial interface 00 provides the following three types of modes Operation stop mode Asynchronous serial interface UART mode 3 wire serial I O mode 8 4 1 Operation stop mode In the operation stop mode serial transfer is not executed therefore the power consumption can be reduced The P20 SCKO ASCK P21 SO0 TxD and P22 SIO RxD pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operating mode register 00 CSIMOO and asynchronous serial interface mode register 00 ASIMOO a Serial operating mode register 00 CSIMOO CSIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMOO to 00H Symbol lt 7 gt Address After Reset R W CSIMOO ae oe Pea FF72H 00H R W csieon I Operation Control in 3 Wire Serial VO Mode Control in 3 Wire Serial I O Mode Operation stop Operation e
91. ed by means of pull up resistor option register PUO LEDs can be driven directly ASCK SCKO TxD SOO RxD SIO Input output Port 3 3 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register PUO LEDs can be driven directly INTPO TIO TOO INTP1 TI1 TO1 27 CHAPTER 2 PIN FUNCTIONS 2 Non port pins Pin Name Input Output INTPONete INTP1Note INTP2Note Function External interrupt input for which the valid edge rising edge falling edge or both rising edge and falling edge can be specified After Reset Alternate Function P30 TI0 TOO P31 TI TO1 P32 S oNote Input Serial interface serial data input P22 RxD SOO Output Serial interface serial data output P21 TxD SCKONote Input output Serial interface serial clock input output P20 ASCK RxDNote Input Serial data input for asynchronous serial interface P22 SIO TxD Output Serial data output for asynchronous serial interface P21 800 ASCKNote Input Serial clock input for asynchronous serial interface P20 SCKO TIoNote TI1 Note Input External count clock input to 8 bit timer TMO External count clock input to 8 bit timer TM1 P30 INTPO TOO P31 INTP1 TO1 TOO Output 8 bit timer output
92. eeeneneenenennen nennen neret nennen enne nnns 68 CHAPTER 5 CLOCK GENERATOR 44 eeeeeeeeeeeee enne enne nnn nnn en nnn tn ne nsn sns nnen nsn sn nnn sn sns nn nnn nn nn 69 5 1 Function of Clock Generator eeeeesseeeeeeseeeeeees seen nennen nnnm nn nnn a nsn n nennt 69 5 2 Configuration of Clock Generator eeeeseeeeeseseseeee eee nn enne nnne ann nenne nnan 69 5 3 Clock Generator Control Register eeeeeeeeeeseesseeeeeeeene seen ennt nani nnns 70 5 4 System Clock Oscillator ia a aa raaa ae aa aa aeara aae aaae ra sienne nena snnt nn nnn tn anita ann nn nns 71 541 System clock oscillator cena de eevee isin aire laren de re eb nieve 71 54 2 Divider CIECUlt uico e p n bob ot te be eil b date reb ecdesia 73 5 5 Operation of Clock Generator eeeeesseeseeseeeeeeeeseeeenn nennen nennen nnne nans n nennt 74 5 6 Changing Setting of CPU CIOCK eeseeeeseeeeeeeeees seen e nennen nennen nnn nn anna nennt nnna 75 5 6 1 Time required for switching CPU clock seen nennen 75 56 2 Switching GPU CIOCK iscsi isn ean aie i LU eet REED ELE EO a t 75 CHAPTER 6 8 BIT TIMER EVENT COUNTER 4 eeeeeeseeeee nenne enn nn nnne nnne n nnne nnn nn nennen nnn 77 6 1 Functions of 8 Bit Timer Event Counter ccccssccceseeeeseeeeeeseeeeeeeeesesneeeenseeeesseeenseeees 78 6 2 8 Bit Timer Event Counter Configu
93. en all possible steps to ensure that the documentation supplied to our customers is complete bug free and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may encounter problems in the documentation Please complete this form whenever you d like to report errors or suggest improvements to us Address North America Hong Kong Philippines Oceania NEC Electronics Inc NEC Electronics Hong Kong Ltd Corporate Communications Dept Fax 852 2886 9022 9044 Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America Taiwan NEC do Brasil S A NEC Electronics Taiwan Ltd Fax 55 11 6462 6829 Fax 02 2719 5951 Korea NEC Electronics Hong Kong Ltd Seoul Branch Fax 002 528 4411 Thank you for your kind support Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 435 9608 would like to report the following error make the following suggestion Document title Document number Page number If possible please fax the referenced page or drawing Document Rating Excellent Clarity Technical Accuracy Organization Acceptable
94. ended Connection of Unused Pins 32 CHAPTER 3 CPU ARCHITECTURE eire crore coe ada vecti tees cin e einn rn eed 33 3 1 Memory Space 2 a EE E A ose aces epi ea Sac nnl in iT MIN i i lr 33 3 1 1 Internal program memory space eseseeeeseeseeeetn ennemi nennen enne nnne nennen 36 3 1 2 Internal data memory internal high speed RAM space se 37 3 1 3 Special function register SFR area ssssssssssssseeeeeeeneennere nennen 37 3 1 4 Data memory addressing irte e a ERE RR IND eaaa aiae iiaia 38 3 2 Processor Regislers clerico erre enirn er eter eren r ert o entre sane caves sateteesdacuecndies 41 3 24 Control r gisters ni dp REA IRR RR e RE 41 3 2 2 General registers 5 serie weit a erbe d ei een 44 3 2 8 Special function register SFR sssssssssssssssseeeneen nennen nennen neret nnns 45 3 3 Instruction Address Addressing eee eene nnn 47 3 9 1 Relative addressing err e eden Lg ee Dep eta e Ree ER De a ca Decus 47 3 3 2 Immediate addressirg erga go OBRUO GE 48 3 3 3 Table indirect addressing onere retten ctv Rien ex Deci 49 3 3 4 Register addressirig tote ine tete ret oet er no det oim ter D orat secta 49 11 3 4 Operand Address Addressing eeseeeeeeeeess esee eeeeene seen nnne nn nnn nennen 50 3 44 Direct addressirig
95. equest so that this mode can be used for intermittent operation However some time is required until the system clock oscillator stabilizes after the STOP mode has been released If processing must be resumed immediately by using an interrupt request therefore use the HALT mode In both modes the previous contents of the registers flags and data memory before setting the standby mode are all retained In addition the statuses of the output latch of the I O ports and output buffer are also retained Caution To set the STOP mode be sure to stop the operations of the peripheral hardware and then execute the STOP instruction 147 i PY SY o ed CHAPTER 10 STANDBY FUNCTION 10 1 2 Standby function control register The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register OSTS OSTS is set with an 8 bit memory manipulation instruction RESET input sets OSTS to 04H However the oscillation stabilization time after RESET input is 2 5 fx instead of 217 fx Figure 10 1 Oscillation Stabilization Time Select Register Format Symbol 7 6 5 Address After Reset R W 4 3 2 1 0 OSTS1 OSTSO Oscillation Stabilization Time Selection 212 fx 819 us 2 5 fx 6 55 ms 217 fx 26 2 ms Otherthan above Setting prohibited Caution The waittime after the STOP mode is released does not inclu
96. er countries IBM DOS and PC AT are trademarks of International Business Machines Corporation HP9000 Series 700 and HP UX are trademarks of Hewlett Packard Company SPARCstation is a trademark of SPARC International Inc Solaris and SunOS are trademarks of Sun Microsystems Inc OSF Motif is a trademark of Open Software Foundation Inc NEWS and NEWS OS are trademarks of Sony Corporation TRON is an abbreviation of The Realtime Operating system Nucleus ITRON is an abbreviation of Industrial TRON The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is current as of September 2000 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibili
97. erating systems Windows 3 1 Windows 95 Windows NT Ver 4 0 175 APPENDIX A DEVELOPMENT TOOLS Figure A 1 Development Tools Embedded Software PROM Programmer Control Software OS PG 1500 controller Language Processing Software Assembler package C compiler package C library source file System simulator Integrated debugger Device file Host machine PC or EWS Interface adapter PROM Writing Environment TUN In circuit emulator PROM programmer CPU core board Emulation board Programmer adapter Product with Emulation probe on chip PROM Target system 176 APPENDIX A DEVELOPMENT TOOLS A 1 Language Processing Software RA78K0S Program that converts program written in mnemonic into object code that can be Assembler package executed by microcontroller In addition automatic functions to generate symbol table and optimize branch instructions are also provided Used in combination with optional device file DF789014 Caution when used under PC environment The assembler package is a DOS based application but may be used under the Windows environment by using Project Manager of Windows included in the assembler package Part number uSxxxxRA78K0S CC78K0S Program
98. erface mode register 00 ASIMOO 102 110 112 126 Asynchronous serial interface status register 00 ASISOO 105 113 Baud rate generator control register 00 BRGCOO 106 114 127 8 bit compare register 00 CROO 80 8 bit compare register 01 CRO1 80 8 bit timer mode control register 00 TMCOO 81 8 bit timer mode control register 01 TMCO1 82 8 bit timer register 00 TMOO 80 8 bit timer register 01 TMO1 80 External interrupt mode register O INTMO 137 Interrupt mask flag register 0 MKO 136 Interrupt request flag register O IFO 135 Oscillation stabilization time select register OSTS 148 Port 0 PO 59 Port 1 P1 60 Port 2 P2 61 Port 3 P3 64 Port mode register 0 PMO 66 Port mode register 1 PM1 66 Port mode register 2 PM2 66 Port mode register 3 PM3 66 83 Processor clock control register PCC 70 Pull up resistor option register PUO 67 Receive buffer register 00 RXBOO 100 Serial operating mode register 00 CSIMOO 101 109 111 125 183 i ri oY a ed APPENDIX C REGISTER INDEX T Timer clock select register 2 TCL2 93 Transmit shift register 00 TXSOO 100 IW Watchdog timer mode register WDTM 94 184 APPENDIX C REGISTER INDEX C 2 Register Symbol Index Alphabetic Order A ASIMOO ASIS00 B BRGCOO C CROO CRO1 CSIMOO 1
99. et Indicates the status of the special function register when the RESET signal is input 45 i rit id CHAPTER 3 CPU ARCHITECTURE Table 3 4 Special Function Register List Address Special Function Register SFR Name Manipulatable Bit Unit After Reset 1 bit 8 bits 16 bits Port 0 O Port 1 Port 2 Port 3 OJO O O Transmit shift register 00 SIO00 Receive buffer register 00 Undefined FFH Port mode register 0 Port mode register 1 Port mode register 2 Port mode register 3 00H Undefined 00H Timer clock select register 2 TCL2 Compare register 00 CROO 8 bit timer register 00 TMOO 8 bit timer mode control register 00 TMCOO Undefined 00H Compare register 01 CRO1 8 bit timer register 01 TMO1 8 bit timer mode control register 01 TMCO1 Asynchronous serial interface mode register 00 ASIMOO Asynchronous serial interface status register 00 ASISOO Serial operating mode register 00 CSIMOO Baud rate generator control register 00 BRGCOO Interrupt request flag register 0 IFO Interrupt mask flag register 0 MKO External interrupt mode register 0 INTMO Pull up resistor option register PUO Watchdog timer mode register WDTM Oscillation stabilization time select register OSTS OJOJO JOJO JO O OJOJOJOJOJ O O O O OJ O JOJO JOJO Processor clock control register PCC
100. get system on host machine SM78KO0S runs on Windows By using SM78KOS the logic and performance of an application can be verified independently of hardware development even when the in circuit emulator is not used This enhances development efficiency and improves software quality Used in combination with optional device file DF789014 Part number uS oxSM78K0S Remark xxxx in the part number differs depending on the host machines and operating system to be used USxxxxSM78K0S Host Machine Supply Media AA13 PC 9800 Series Japanese Windows 3 5 2HD FD AB13 IBM PC AT compatibles Japanese Windows 3 5 2HC FD BB13 English Windows 180 APPENDIX B EMBEDDED SOFTWARE The following embedded software is available for efficient program development and maintenance of the uPD789014 Subseries MX78K0S MX78KOS is a subset OS that is based on the uITRON specification Supplied with the MX78K0S OS nucleus The MX78KOS OS controls tasks events and time In task control the MX78KOS OS controls task execution order and then perform the switching process to a task to be executed Caution when used under PC environment The MX78KOS is a DOS based application Use this software in the DOS pane when running it on Windows 181 MEMO 182 APPENDIX C REGISTER INDEX C 1 Register Name Index Alphabetic Order A B E 0 P R S Asynchronous serial int
101. gister BRGCO0 Set Value Transfer RateNote 76800 System Clock High Speed Operation PCC1 0 System Clock Low Speed Operation PCC1 1 38400 19200 9600 4800 2400 119 1200 247 Note When fx 4 9152 MHz operation EXCL1 External clock frequency transfer rate x 24 fcPu CPU operation frequency 9 clocks Because interrupt processing is started one clock after the occurrence of an interrupt interrupt processing uses 8 clocks a total of 9 clocks are required x clocks Number of clocks until RXBOO read In the case of external clock satisfy the following equation EXCL1 Hz gt fceu Hz 9 clocks x clocks 123 CHAPTER 8 SERIAL INTERFACE 00 Example Number of clocks required to read RXBOO register if clock signal is input from external when 300 bps transfer is desired when fcru 1 MHz operation EXCL1 300 x 24 4 8 kHz 4 8 kHz gt 1 MHz 9 x x gt 1 MHz 4 8 kHz 9 x gt 199 3 Therefore in this case wait 200 clocks before reading the RXBOO register within the interrupt routine 124 CHAPTER 8 SERIAL INTERFACE 00 8 4 3 3 wire serial I O mode The 3 wire serial I O mode is useful for connection of peripheral I Os and display controllers etc which incorporate a conventional synchronous clocked serial interface such as the 75XL Series 78K Series 17K Series etc Communication is performed using three lines the se
102. granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
103. he watchdog timer mode 1 and 2 are used set TMIF4 flag to 0 2 Because port 3 has an alternate function as the external interrupt input when the output level is changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 135 CHAPTER 9 INTERRUPT FUNCTIONS 2 Interrupt mask flag register 0 MKO The interrupt mask flag is used to enable disable the corresponding maskable interrupt service MKO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets MKO to FFH Figure 9 3 Interrupt Mask Flag Register 0 Format Symbol 7 0 Address After Reset R W MKO TMMKO1 TMMK00 STMKO0 SRMK00 PMK2 PMK1 PMKO TMMK4 FFE4H FFH R W Interrupt Servicing Control Interrupt servicing enabled Interrupt servicing disabled Cautions 1 Ifthe TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1 and 2 its value becomes undefined 2 Because port 3 has an alternate function as the external interrupt input when the output levelis changed by specifying the output mode of the port function an interrupt request flag is set Therefore 1 should be set in the interrupt mask flag before using the output mode 136 CHAPTER 9 INTERRUPT FUNCTIONS 3 External interrupt mode register 0 INTMO This register is used to set the valid edge of INTPO to INTP2 INTMO is se
104. he operation transfer and bit manipulation instructions Manipulatable bit units 1 8 and 16 differ depending on the special function register type Each manipulation bit unit can be specified as follows 1 bit manipulation Describes a symbol reserved with assembler for the 1 bit manipulation instruction operand sfr bit This manipulation can also be specified with an address 8 bit manipulation Describes a symbol reserved with assembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved with assembler for the 16 bit manipulation instruction operand When addressing an address describe an even address Table 3 4 lists the special function register The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the implemented special function registers The symbols shown in this column are the reserved words of the assembler and have already been defined in the header file called sfrbit h of C compiler Therefore these symbols can be used as instruction operands if assembler or integrated debugger is used R W Indicates whether the special function register in question can be read or written R W Read write R Read only Ww Write only Manipulatable bit unit Indicates the bit units 1 8 16 in which the special function register in question can be manipulated After res
105. ime 2 5 fx has elapsed see Figures 11 2 through 11 4 Cautions 1 For an external reset input a low level for 10 us or more to the RESET pin 2 When the STOP mode is cleared by reset the STOP mode contents are held during reset input However the port pins become high impedance Figure 11 1 Block Diagram of Reset Function Reset control circuit Reset signal Over Count clock Watchdog timer TOW Interrupt function Stop 155 CHAPTER 11 RESET FUNCTION Figure 11 2 Reset Timing by RESET Input aCe pea iV During normal i Reset period Oscillation illati NRA Normal ration r oscillation gt stabilization ormal operatio operation stops mewait reset processing Dr RESET r bog l Internal 1 l reset signal i EL i m Delay Delay Hi Z Portpin y 0 0 5 AT eese umi usciti Scie SSSR er Figure 11 3 Reset Timing by Overflow in Watchdog Timer OE NIN NP NG NING oN ENN RN i Reset period Oscillation During normal operation 74 oscillation gt i stabilization continues time wait Normal operation reset processing watchdog timer Internal reset signal I i i l I Overflow in i I I I I I I I I I l I I I l l Port pin EE E ESEE CEE EEE E E E Figure 11 4 Reset Timing by RESET Input in STOP Mode A E aA AUS STOP instru
106. imer register x 28 TMOn 2 1 2 O ronP3w D INTPn TIn TIn P3n INTPn TOn TCEOn TCLOn1 TCLOnO TOEOn t 8 bit timer mode control register 0n TMCOn n 20 1 1 8 bit compare register On CROn 80 2 An 8 bit register to compare the value set to CROn with the 8 bit timer register On TMOn count value and if they match generate an interrupt request INTTMn CROn is set with an 8 bit memory manipulation instruction The 00H to FFH values can be set RESET input sets CROn to undefined Caution Be sure to rewrite the CROn value after stopping timer operation Remark n O 1 8 bit timer register On TMOn This is 8 bit register to count count pulses TMOn is read with an 8 bit memory manipulation instruction RESET input sets TMOn to OOH Remark n O 1 CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 3 8 Bit Timer Event Counter Control Registers The following two types of registers are used to control the 8 bit timer event counter 8 bit timer mode control registers 00 01 TMC00 TMCO1 Port mode register 3 PM3 1 8 bit timer mode control register 00 TMCOO0 This register enables stops operation of 8 bit timer register 00 TMOO sets the count clock of 8 bit timer event counter 00 and controls the operation of the output control circuit TMCOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMCOO to 00H Figure 6 2 8 Bit Timer Mode Control Register 00 Format
107. ister 00 Format Symbol 7 Address After Reset R W ASIMOO TXEOO RXEOO PSO01 P SET SLOO CEARA FF70H 00H R W TXEOO Transmit Operation Control Transmit operation stop Transmit operation enable RXE00 Receive Operation Control Receive operation stop Receive operation enable No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity 0 7 bits 1 8 bits O 1 bit 1 2 bits Cautions 1 Be sure to set 0 to bits 0 and 1 2 Set 00H to the ASIMOO at the 3 wire serial I O mode 3 Switching operation modes must be performed after the halt of serial transmit receive operation 4 In the UART mode if the operation is interrupted TXEOO z 0 during data transmission P21 which is the alternate function I O port pin of TxD cannot be used as a general purpose output port 102 CHAPTER 8 SERIAL INTERFACE 00 Table 8 2 Serial Interface 00 Operating Mode Settings 1 2 1 Operation stop mode ASIMOO CSIMOO P22 SIO RxD P21 SOO TxD P20 SCK0 ASCK Pin Function Pin Function Pin Function RXE00 CSIE00 DIROO CSCK00 0 0 x Other than above 2 Asynchronous serial interface mode ASIMOO CSIMOO CSIE00 DIROO CSCK00 Setting prohibited P20 Start External P22 SIO RxD Pin Function P21 SO0 TxD Pin Function TxD P20 SCKO ASCK Pin Function ASC
108. ive shift register 00 RXS00 If the data length is specified as 7 bits receive data is transferred to bits 0 to 6 of RXBOO and the MSB of RXBOO always becomes 0 RXBOO can be read with an 8 bit memory manipulation instruction It cannot be written to RESET input becomes undefined Caution RXBO0O and the transmit shift register 00 TXS00 are allocated to the same address and when an interrupt is executed the values are written to TXSO00 Transmit control circuit This circuit controls transmit operations by adding a start bit parity bit and stop bitto data written to the transmit shift register 00 TXS00 according to the data set to the asynchronous serial interface mode register 00 ASIMOO Receive control circuit This circuit controls receive operations according to the data set to the asynchronous serial interface mode register 00 ASIMOO It performs also parity error check etc during receive operations and when an error is detected it sets the value to the asynchronous serial interface status register 00 ASISO0 depending on the nature of the error CHAPTER 8 SERIAL INTERFACE 00 8 3 Serial Interface 00 Control Registers The following four types of registers are used to control the serial interface 00 Serial operating mode register 00 CSIMOO Asynchronous serial interface mode register 00 ASIMOO Asynchronous serial interface status register 00 ASISOO Baud rate generator control register
109. l name in the instruction code Register addressing is carried out when an instruction with the following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format X A C B E D L H AX BC DE HL and rp can be described with absolute names RO to R7 and RPO to RP3 as well as functional names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instruction code O 0 O0 0 1 0 1 0 Register specify code INCW DE When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specify code 53 CHAPTER 3 CPU ARCHITECTURE 3 4 5 Register indirect addressing Function The memory is addressed with the contents of the register pair specified as an operand The register pair to be accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format vmm Description example MOV A DE When selecting register pair DE Instruction code 0 O 1 0 1 0 1 1 Illustration 15 8 7 0 x 9 1 1 7 0 Memory address specified by register pair DE The contents of addressed memory are transferred 7 0 EL or oci 54 i wA j ed CHAPTER 3 CPU ARCHITECTURE 3 4
110. ll Up Resistor Option Register Format Symbol 7 6 lt 2 gt d lt 0 gt Address After Reset R W 5 4 lt 3 gt 2 euo o o e e Pucs Puce Puor Puce Frera o Rw Pm On chip Pull up Resistor Selection m 0 to 3 On chip pull up resistor not used On chip pull up resistor used 67 i wA j ed CHAPTER 4 PORT FUNCTIONS 4 4 Operation of Port Functions The operation of a port differs depending on whether the port is set in the input or output mode as described below 4 4 1 Writing to I O port 1 In output mode A value can be written to the output latch by using a transfer instruction The contents of the output latch can be output from the pins of the port The data once written to the output latch is retained until new data is written to the output latch Caution Executing a bit manipulation instruction or a logic operation instruction for the port with alternate output functions may fix the output pin level Therefore use an 8 bit data transfer instruction or a 16 bit data transfer instruction 2 In input mode A value can be written to the output latch by using a transfer instruction However the status of the pin is not changed because the output buffer is OFF The data once written to the output latch is retained until new data is written to the output latch Caution A 1 bit memory manipulation instruction is executed to manipulate 1 bit of a port However this instruction accesses the p
111. low voltage 1 8 V For small scale general purpose applications A D 4 uPD789217AY uPD789197AY 4 1 T r 4 4 1 Qe putts yuPD789842 For LCD drive uPD789417A uPD789407A _ 4 HPD789830 For ASSP uPD789840 uPD789800 JPD789810 RC oscillator version of the uPD789197AY EEPROM and SMB incorporated to the uPD789177 Enhanced A D of the uPD789167 Enhanced a timer of the uPD7891044A Enhanced A D of the uPD789146 EEPROM incorporated to the uPD789104A Enhanced A D of the uPD789124A RC oscillator version of the uPD789104A Enhanced A D of the uPD789104A Added an A D and multiplier to the PD789104 Inverter control circuit with on chip UART Enhanced A D of the uPD789407A Added A D to the uPD789026 and enhanced a timer On chip dot LCD and UART For a keypad with on chip POC For a PC keyboard with on chip USB function For an IC card with on chip security circuit CHAPTER 1 GENERAL The major functional differences among the subseries are listed below ROM Subseries Name Capacity Small scale general purpose Small scale general purpose A D Inverter control LCD drive Note uPD789046 Timer uPD789026 4Kto 16K 16 Bit Watch uPD789014 2Kto4 K LPD789217AY 16 K to 24 K uPD789177 uPD789167 uPD789156 8K to 16 K uPD789146 uPD789134A 2 K to 8 K HPD789124A UPD789114A UPD789104A uPD7
112. ls specified by a count value set in advance Select a count clock or interval time by setting bits 0 through 2 TCL20 to TCL22 of timer clock select register 2 TCL2 The watchdog timer starts operation as an interval timer when the RUN bit bit 7 of WDTM is set to 1 In the interval timer mode the interrupt mask flag TMMKA is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the interval timer and then execute the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when the watchdog timer mode is selected the interval timer mode is not set unless the RESET signal is input 2 The interval time immediately after the setting by WDTM may be up to 0 8 shorter than the set time Table 7 5 Interval Time of Interval Timer TCL22 TCL21 TCL20 Interval Time At fx 5 0 MHz 0 0 0 2 x 1 fx 1 23 x 1 fx 0 275 x 1 fx 1 27 x 1 fx fx system clock oscillation frequency 96 i wA j ed i ri oY a ed CHAPTER8 SERIAL INTERFACE 00 8 1 Serial Interface 00 Functions The serial interface 00 employs the following three modes Operation stop mode Asynchronous serial interface UART mode 3 wire serial I O mode 1 Operation stop mode This
113. mode is used when serial transfer is not carried out It enables power consumption reduction 2 Asynchronous serial interface UART mode In this mode one byte of data following the start bit is transmitted received and full duplex operation is possible A dedicated UART baud rate generator is incorporated allowing communication over a wide range of baud rates In addition the baud rate can be defined by scaling the input clock to the ASCK pin 3 3 wire serial I O mode MSB LSB start bit switchable In this mode 8 bit data transfer is carried out with three lines one for serial clock SCKO and two for serial data SIO SOO The 3 wire serial I O mode supports simultaneous transmit and receive operation reducing data transfer processing time It is possible to switch the start bit of 8 bit data to be transmitted between the MSB and the LSB thus allowing connection to devices with either start bit The 3 wire serial I O mode is effective for connecting display controllers and peripheral I Os such as the 75XL Series 78K Series and 17K Series which have internal conventional clock synchronous serial interface 8 2 Serial Interface 00 Configuration Serial interface 00 has the following hardware configuration Table 8 1 Serial Interface 00 Configuration Item Configuration Register Transmit shift register 00 TXS00 Receive shift register 00 RXS00 Receive buffer register 00 RXBOO Control register Serial operating mode regi
114. n Do not replace the asynchronous serial interface mode register 00 ASIMOO during a transmit operation If the ASIMOO register is replaced during transmission subsequent transmission may not be performed the normal state is restored by RESET input It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt INTST or the interrupt request flag STIFOO set by INTST 119 al Mie CHAPTER 8 SERIAL INTERFACE 00 d Reception When bit 6 RXE of the asynchronous serial interface mode register 00 ASIMOO is set 1 a receive operation is enabled and sampling of the RxD pin input is performed RxD pin input sampling is performed using the serial clock specified by ASIMOO When the RxD pin input becomes low the 3 bit counter starts counting and at the time when the half time determined by the specified baud rate has passed the data sampling start timing signal is output If the RxD pin input sampled again as a result of this start timing signal is low it is identified as a start bit the 3 bit counter is initialized and starts counting and data sampling is performed When character data a parity bit and one stop bit are detected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to the receive buffer register 00 RXBOO and a reception completion interrupt INTS
115. nable Caution Be sure to set 0 to bit 0 and bits 3 to 6 109 CHAPTER 8 SERIAL INTERFACE 00 b Asynchronous serial interface mode register 00 ASIMOO ASIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIMOO to 00H Symbol 7 Address After Reset R W ASIMOO TXEOO RXEOO PS001 PS000 CLOO SLOO TEIRA FF70H 00H R W ums Transmit Operation Control Transmit operation stop Transmit operation enable Receive Operation Control Receive operation stop Receive operation enable Caution Be sure to set 0 to bits 0 and 1 110 CHAPTER 8 SERIAL INTERFACE 00 8 4 2 Asynchronous serial interface UART mode In this mode the one byte data following the start bit is transmitted received and thus full duplex communication is possible This device incorporates a UART dedicated baud rate generator that enables communications at a desired transfer rate from many options In addition the baud rate can also be defined by dividing the input clock to the ASCK pin The UART dedicated baud rate generator also can output the 31 25 kbps baud rate that complies with the MIDI standard 1 Register setting The UART mode is set by serial operating mode register 00 CSIMOO asynchronous serial interface mode register 00 ASIMOO asynchronous serial interface status register 00 ASISOO and baud rate generator control register 00 BRGCOO a Serial operating mode register 00 CSIMOO
116. nction registers 165 i wA j ed CHAPTER 13 INSTRUCTION SET 13 1 2 Description of operation column r r m ooox UIV vor mo xx PSW CY AC Z IE NMIS XH XL A V v addr16 jdisp8 A register 8 bit accumulator X register B register C register D register E register H register L register AX register pair 16 bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data 16 bit immediate data or label Signed 8 bit data displacement value 13 1 3 Description of flag operation column 166 Blank Unchanged 0 1 x R Cleared to 0 Set to 1 Set cleared according to the result Previously saved value is restored CHAPTER 13 INSTRUCTION SET 13 2 Operation List Mnemonic MOV Operands r byte r byte Operation saddr byte saddr byte sfr byte sfr byte A Note 1 Aer r ANote 1 rcA A saddr A lt saddr saddr A sa
117. nder development changed to Developed for the uPD789011 789012 and 78P9014 Revised Chapters Whole manual Addition of Caution for I O port CHAPTER 4 PORT FUNCTIONS Modification of maximum time required for switching CPU clock CHAPTER 5 CLOCK GENERATOR Modification and addition of Caution to setting of watchdog timer mode register CHAPTER 7 WATCHDOG TIMER Addition of Caution to setting of external interrupt mode register 0 Addition of description of interrupt request acceptance timing in maskable interrupt CHAPTER 9 INTERRUPT FUNCTIONS Modification of timing chart of reset timing by RESET input Modification of timing chart of reset timing by overflow in watchdog timer Modification of timing chart of reset timing by RESET input in STOP mode CHAPTER 11 RESET FUNCTION Modification of recommended connection of unused pins CHAPTER 2 PIN FUNCTIONS Modification of part of register name and symbol of special function register CHAPTER 3 CPU ARCHITECTURE Addition of Caution to 8 bit compare register On Modification of symbol and flag name of 8 bit timer mode control register 00 Modification of symbol and flag name of 8 bit timer mode control register 01 Modification of description of interval timer operation Modification of description of external event counter operation Modification of description of square wave output operation CHAPTER 6 8 BIT TIME
118. nput to the RESET pin oscillation of the system clock is stopped Two types of CPU clocks fcru 0 2 us and 0 8 us at 5 0 MHz operation can be selected by the PCC setting Two standby modes STOP and HALT can be used The clock to the peripheral hardware is supplied by dividing the system clock The other peripheral hardware is stopped when the system clock is stopped except however the external clock input operation i PI P Y o j ed CHAPTER 5 CLOCK GENERATOR 5 6 Changing Setting of CPU Clock 5 6 1 Time required for switching CPU clock The CPU clock can be selected by using bit 1 PCC1 of the processor clock control register PCC Actually the specified clock is not selected immediately after the setting of PCC has been changed and the old clock is used for the duration of several instructions after that refer to Table 5 2 Table 5 2 Maximum Time Required for Switching CPU Clock Set Value before Switching Set Value after Switching PCC1 PCC1 PCC1 Remark Two clocks are the minimum instruction execution time of the CPU clock before switching 5 6 2 Switching CPU clock The following figure illustrates how the CPU clock switches Figure 5 5 Switching CPU Clock Voo RESET CPU clock m Low speed High speed p operation Wait 6 55 ms at 5 0 MHz operation Internal reset operation 1 The CPU is reset when the RESET pin is made low on power application The effec
119. ntrol the interrupt functions Interrupt request flag register O IFO nterrupt mask flag register 0 MKO External interrupt mode register 0 INTMO Program status word PSW Table 9 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 9 2 Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT TMIF4 TMMK4 INTPO PIFO PMKO INTP1 PIF1 PMK1 INTP2 PIF2 PMK2 INTSR INTCSIO SRIFOO SRMKOO INTST STIFOO STMKOO INTTMO TMIFOO TMMKOO INTTM1 TMIFO1 TMMKO1 134 CHAPTER 9 INTERRUPT FUNCTIONS 1 Interrupt request flag register 0 IFO The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input IFO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets IFO to 00H Figure 9 2 Interrupt Request Flag Register 0 Format Symbol 7 6 1 Address After Reset R W IFO TMIFO1 TMIFOO STIFOO SRIFOO PIF2 PIF1 PIFO FFEOH 00H R W Interrupt Request Flag No interrupt request signal is generated Interrupt request signal is generated Interrupt request state Cautions 1 TMIF4 flag is R W enabled only when a watchdog timer is used as an interval timer If t
120. nunnnnunnunnnnnnnnnnnnnnnnnnnnnnnnnn mannen nna 20 1 5 Y9K 0S Seres C UD aa ee a a a a ae aaa a e tanaoa i aana dia ieii de 22 1 6 Block Diagram sarcina eaae giv cecbedatees cctdbeeeseccueeeeedeebedapeesecadberesveeuners 24 1 7 Overview of Functions eeseeeeseeseeeeeeeeeeee nenne nnnn nnn nn nint nn sni nn sain nnne sanas anna nena 25 CHAPTER 2 PIN FUNCTIONS 4 naccrer ein croce ene ecce een ccr nien mre Ue pen vm or Cua e Nnnc rp evanescere Ee iEn c 27 2 1 List of Pin Functions eeeeeeeeeseeeeeeeeeeeene nennen nnne nennt nn snnt nn nennt nnn nane nnns 27 2 1 1 Pins in normal operating mode sssseeeeneeeneeeem eene nne 27 2 1 2 Pins in PROM programming mode sse nen neret nennen 28 2 2 Description of Pin Functions ness nnne nnn 29 2 2 1 POO to PO7 Port 0 i ous UR Ne dice E Ed etie 29 2 2 2 PT0 to PA7 BOrt 1 tinens d Ubi iban 29 2 2 3 P20 to P22 Port 2 nare qae o oe eet eiim dete ette 29 2 2 4 P3010 P32 POMS iei ted me pede daar i tege bre ec etie e ula 30 X ESE e 31 2 2 65 X1 2X2 cot Uta co ee ek SS lb ak fe RES ES LN M eee DM ILICE M RE e 31 2 2 3 MDDuinuniueib UR RR M MIA GU 31 2 2 8 MSS ein GE aer E UR BR U tie teet aep sete 31 22 9 MEP HPD78P9014 only e t DOE bte DOE ine n 31 2 2 10 IC mask ROM version only cessen ancii iei nnne nnne aeea 31 2 3 Pin Input Output Circuits and Recomm
121. of the 78K 0S Series Refer to 78K 0S Series User s Manual Instruction U11047E separately available Data significance Higher digits on the left and lower digits on the right Active low representation xxx overscore over pin or signal name Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numerical representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Related Documents Therelated documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Device Related Documents Document Name Document No English Japanese uPD789011 789012 Data Sheet U11095E U11095J HPD78P9014 Data Sheet U10912E U10912J uPD789014 Subseries User s Manual This manual U11187J 78K 0S Series User s Manual Instruction U11047E U11047J Documents for Development Tool User s Manual Document Name Document No English Japanese RA78KO0S Assembler Package Operation U11622E U11622J Assembly Language U11599E U11599J Structured Assembly Language U11623E U11623J CC78KO0S C Compiler Operation U11816E U11816J Language U11817E U11817J SM78KOS System Simulator Windows Based Reference U11489E U11489J SM78K Series System Simulator External Part User Open U10092E U10092J Interface Specifications ID78
122. of the execution of the next instruction even if the interrupt request maskable interrupt non maskable interrupt and external interrupt is generated during the execution The following shows such instructions interrupt request reserve instruction Manipulation instruction for the interrupt request flag register O IFO Manipulation instruction for the interrupt mask flag register 0 MKO 145 MEMO 146 CHAPTER 10 STANDBY FUNCTION 10 1 Standby Function and Configuration 10 1 1 Standby function The standby function is to reduce the power dissipation of the system and can be effected in the following two modes 1 2 HALT mode This mode is set when the HALT instruction is executed The HALT mode stops the operation clock of the CPU The system clock oscillator continues oscillating This mode does not reduce the power dissipation as much as the STOP mode but is useful for resuming processing immediately when an interrupt request is generated or for intermittent operations STOP mode This mode is set when the STOP instruction is executed The STOP mode stops the system clock oscillator and stops the entire system The power dissipation of the CPU can be substantially reduced in this mode The low voltage Vpp 1 8 V of the data memory can be retained Therefore this mode is useful for retaining the contents of the data memory at an extremely low current The STOP mode can be released by an interrupt r
123. ogram runaway when bit 4 WDTMA of the watchdog timer mode register WDTM is set to 1 The count clock runaway detection time interval of the watchdog timer can be selected by bits 0 to 2 TCL20 to TCL22 of the timer clock select register 2 TCL2 By setting bit 7 RUN of WDTM to 1 the watchdog timer is started Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started By setting RUN to 1 the watchdog timer can be cleared and start counting If RUN is not set to 1 and the runaway detection time is exceeded the system is reset or a non maskable interrupt is generated by the value of bit 3 WDTMS of WDTM The watchdog timer continues operation in the HALT mode but stops in the STOP mode Therefore set RUN to 1 before entering the STOP mode to clear the watchdog timer and then execute the STOP instruction Caution The actual runaway detection time may be up to 0 8 shorter than the set time Table 7 4 Runaway Detection Time of Watchdog Timer TCL20 Runaway Detection Time At fx 2 5 0 MHz 2 x 1 fx 21 x 1 fx 275 x 1 fx 2 x 1 fx fx system clock oscillation frequency 95 i PI P Y o j ed CHAPTER 7 WATCHDOG TIMER 7 4 2 Operation as interval timer When bits 4 and 3 WDTM4 and WDTM3 of watchdog timer mode register WDTM are set to 0 and 1 the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time interva
124. om Stack Memory ssssssssseseseeeneeeeneen eene nennen enne 43 3 12 General Register Configuration srs ineens teuere ipanen daaa greki aidie ia aioa 44 4 1 POTN POS fennaenn a a ca ot a a a re ee eS 57 4 2 Block Diagram of POO to PO iio titre Re RO TC e Laai epinar AN UAR Me 59 4 3 Block Diagram of P10 to P17 ui ese eer ndisse aed Re 60 4 4 Block Diagram of P20 nasce eene IRR iei em iens 61 4 5 Block Diagram of P27 5 5 2 Ie LEEREN EEUU Uu 62 4 6 Block Diagraiin of P222 oe cre cmn d e de er A dec reda c seed d dta t cent uds 63 4 7 Block Diagram of P30 and P312 ERR aar cn eee 64 4 8 Block Diagram of P392 eei neque b e ee e aie ae ae 65 4 9 Port Mode Register Fortran ATTE Ra OE ee a ERRARE Ir RR RARE 67 4 10 Pull Up Resistor Option Register Format essssssssseeeeeeneennneenene nennen nennen 67 5 1 Block Diagram of Clock Generator ssssssssssseseeeeeeeneenee nennen nnne nnne nnne nens 69 5 2 Processor Clock Control Register Format sesssssesesseeeeeeneenneee nennen nennen nene 70 5 3 External Circuit of System Clock Oscillator sse enne 71 5 4 Incorrect Examples of Resonator Connection sssssssssssssseseee esee enne 72 5 5 Switching CPU GIOCK iid et aeebun ted e pea RUOLO OA 75 6 1 Block Diagram of 8 Bit Timer Event Counter ssesssssesseeseeeeeeeeeneen nennen nennen nennen 80 6 2 8 Bit Timer Mode
125. on as square wave output Modification of symbol and flag name in Figure 8 3 Serial Operating Mode Register 00 Format and addition of Caution regarding transmit receive operation Modification of symbol and flag name in Figure 8 4 Asynchronous Serial Interface Mode Register 00 Format and addition of Caution regarding transmit operation Modification of 1 bit memory manipulation instruction enabled in 8 3 3 Asynchronous serial interface status register 00 ASISOO Modification of symbol and flag name in Figure 8 5 Asynchronous Serial Interface Status Register 00 Format Addition of explanation regarding transmit operation and explanation regarding read operation of RXBOO register in 8 4 2 Asynchronous serial interface UART mode Addition of explanation regarding transmit receive operation in 8 4 3 3 wire serial I O mode Modification of flag name in Figure 9 2 Interrupt Request Flag Register 0 Format Modification of flag name in Figure 9 3 Interrupt Mask Flag Register 0 Format Addition of Caution in Table 12 1 Differences between 4PD78P9014 and Mask ROM Versions Addition of Solaris M to operating system in A 1 Language Processing Software Addition of PA 17K DZ to PROM programmer adapter in A 2 1 Hardware Modification of PC card interface name to IE 70000 CD IF A and addition of IE 70000 PCI IF to interface adapter in A 3 1 Hardware The mark x shows major revised points Rea
126. onics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics User s Manual uPD789014 Subseries 8 bit Single chip Microcontrollers uPD789011 uPD789012 uPD78P9014 Document No U11187EJ3VOUMJ1 3rd edition Date Published September 2000 N CP K NEC Corporation 1996 Printed in Japan MEMO NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards
127. operation Serial interface Enables operation only when input clock from external is selected as serial clock External interrupt Enables operation 152 CHAPTER 10 STANDBY FUNCTION 2 Releasing STOP mode The STOP mode can be released by the following two types of sources a Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request In this case if the interruptis enabled to be accepted vectored interrupt processing is performed after the oscillation stabilization time has elapsed If the interrupt acceptance is disabled the instruction at the next address is executed Figure 10 4 Releasing STOP Mode by Interrupt Wait STOP set time by OSTS instruction lt gt Standby Y 1 release signal foc aeee nds Operation Oscillation stabilization Operation mode STOP mode wait status mode z aii Oscillation Clock Oscillation stops Oscillation cm i gt a Remark The broken line indicates the case where the interrupt request that has released the standby mode is accepted 153 CHAPTER 10 STANDBY FUNCTION b Releasing by RESET input When the STOP mode is released by the RESET signal the reset operation is performed after the oscillation stabilization time has elapsed Figure 10 5 Releasing STOP Mode by RESET Input Wait 2 5 fx 6 55 ms iea STOP instruction RESET i signal Oscillation Operation
128. ort in 8 bit units When this instruction is executed to manipulate a bit of an input output port therefore the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 2 In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arithmetic operation of I O port 1 In output mode An arithmetic operation can be performed with the status of a pin The result of the operation is written to the output latch The contents of the output latch are output from the port pins The data once written to the output latch is retained until new data is written to the output latch 2 In input mode The contents of the output latch become undefined However the status of the pin is not changed because the output buffer is OFF Caution A 1 bit memory manipulation instruction is executed to manipulate 1 bit of a port However this instruction accesses the port in 8 bit units When this instruction is executed to manipulate a bit of an input output port therefore the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined 68 CHAPTER 5 CLOCK GENERATOR 5 1 Function of Clock Generator
129. pplied to this pin when the PROM programming mode is set and when the program is written or verified Connect this pin directly to Vss in the normal operation mode 2 2 10 IC mask ROM version only The IC Internally Connected pin is used to set the PD789011 and 789012 in the test mode before shipment In the normal operation mode connect this pin directly to the Vss pin with as short a wiring length as possible If a potential difference is generated between the IC pin and Vss pin due to a long wiring length between the IC pin and Vss pin or an external noise superimposed on the IC pin a user program may not run correctly O Connect the IC pin directly to the Vss pin Vss IC 3 Keep short 31 CHAPTER 2 PIN FUNCTIONS 2 3 Pin Input Output Circuits and Recommended Connection of Unused Pins The input output circuit type of each pin and recommended connection of unused pins are shown in Table 2 1 For the input output circuit configuration of each type refer to Figure 2 1 Table 2 1 Types of Pin Input Output Circuits Input Output Circuit Type Input Output Recommended Connection of Unused Pins POO to P07 Input output Input Independently connect to Voo or Vss via a resistor Output Leave open P10 to P17 P20 ASCK SCKO P21 TxD SOO P22 RxD SIO P30 INTPO TIO TOO P31 INTP1 TH TO1 P32 INTP2 RESET IC mask ROM version Connect directly to Vss Ver uPD78P9014 Figu
130. r Event Counter Minimum Interval Time Maximum Interval Time Resolution 1 fx 200 ns 2 fx 51 2 us 1 fx 200 ns 25 fx 6 4 us 213 fx 1 64 ms 25 fx 6 4 us Remarks 1 fx system clock oscillation frequency 2 at fx 5 0 MHz operation 2 External event counter The number of pulses of an externally input signal can be measured 3 Square wave output A square wave of any frequency can be output Table 6 2 Square Wave Output Range of 8 Bit Timer Event Counter Minimum Pulse Width Maximum Pulse Width 1 fx 200 ns 2 fx 51 2 us 1 fx 200 ns 25 fx 6 4 us 213 fx 1 64 ms 25 fx 6 4 us Remarks 1 fx system clock oscillation frequency 2 at fx 5 0 MHz operation 78 CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 2 8 Bit Timer Event Counter Configuration The 8 bit timer event counter consists of the following hardware configuration Table 6 3 8 Bit Timer Event Counter Configuration Configuration Timer register 8 bits x 2 TMOO TM01 Register Compare register 8 bits x 2 CROO CRO1 Timer output 2 TOO TO1 Control register 8 bit timer mode control registers 00 01 TMCO00 TMC01 Port mode register 3 PM3 79 i rir SY o ed CHAPTER 6 8 BIT TIMER EVENT COUNTER Figure 6 1 Block Diagram of 8 Bit Timer Event Counter 8 bit compare register CROn output latch Match INTTMn fx 8 8 bit t
131. ration esee nennen nennen nnn 79 6 3 8 Bit Timer Event Counter Control Registers eese 81 6 4 Operation of 8 Bit Timer Event Counter eseeeeseeeeeeeeee seen entente nnn nnn 84 6 4 4 Operation as interval timer ioi fce tercie t tb Ain iie dtt nae 84 6 4 2 Operation as external event counter sssssssseseeeeeenneeenneen nene 86 6 4 8 Operation as square wave output ssssssssseeeeeneenneen nennen nene nneen nennen nnne 87 6 5 Notes on Using 8 Bit Timer Event Counters eese rnnt 89 12 a TE ad CHAPTER 7 WATCHDOG TIMER eren nennen nnne nnne nnne nnne nnne tnna stris tnn intra se nn san nn nnns 91 7 1 Functions of Watchdog Timer eene nnne nnne nnne nennen 91 7 2 Configuration of Watchdog Timer ueseeseeeeeeeeseeseeee nennen nnnm nnne naria nnns 92 7 3 Watchdog Timer Control Registers eeeeeeeeesseeeeeeeeeeeeee nennen nennen nnns 93 7 4 Operation of Watchdog Timer ueeeeesseeseeeeeeeeeeee seen nennen nannte nn nani nn nnns 95 7 4 1 Operation as watchdog timer sssssssssssseeeeeeeeneeennen nennen nennen nennen nnns 95 7 4 2 Operation as interval timer ssesesssesseseseeseeeeeeeeennne nennen nennen nnne tenen rennen nnns 96 CHAPTER 8 SERIAL INTERFACE 00 eee
132. rces This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon El instruction execution Zero flag Z When the operation result is zero this flag is set to 1 It is reset to 0 in all other cases Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set to 1 It is reset to 0 in all other cases Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution al Mie i ri oY a ed CHAPTER 3 CPU ARCHITECTURE 3 Stack pointer SP This is a 16 bit register to hold the start address of the memory stack area Only the internal high speed RAM area can be set as the stack area Figure 3 9 Stack Pointer Configuration 15 0 The SP is decremented ahead of write save to the stack memory and is incremented after read restore from the stack memory SP Each stack operation saves restores data as shown in Figures 3 10 and 3 11 Caution Since RESET input makes SP contents undefined be sure to initialize the SP before instruction execution Figure 3 10 Data to be Saved to Stack Memory PUSH rp CALL CALLT Interrupt Instruction Instructions SP SP 3 A SP SP 2 SP SP 2 SE
133. re 2 1 Pin Input Output Circuits pullup enable Vop data T5 output disable IN OUT Schmitt triggered input with hysteresis characteristics a Pre Voo VDD data 1l E P output N ch disable TT IN OUT input enable 32 3 4 Memory Space CHAPTER 3 CPU ARCHITECTURE The uPD789014 Subseries can access 64 Kbytes of memory space Figures 3 1 through 3 3 show the memory maps Data memo Figure 3 1 Memory Map uPD789011 FFFFH Special Function Registers 256 x 8 bits FFOOH FEFFH Internal High speed RAM 128 x 8 bits FE80H FE7FH Reserved ry space 07FFH 0800H 4 07FFH Program Area Program Internal ROM ee memory space 2048 x 8 bits DOE CALLT Table Area 0040H 003FH Program Area 0014H 0013H Vector Table Area 0000H 0000H Y 33 CHAPTER 3 CPU ARCHITECTURE Figure 3 2 Memory Map uPD789012 FFFFH Special Function Registers 256 x 8 bits FFOOH FEFFH Internal High speed RAM 128 x 8 bits FE80H FE7FH Reserved Data memory space OFFFH 1000H A OFFFH Program Area Program Internal ROM eae memory space 4096 x 8 bits Doe CALLT Table Area 0040H 003FH Program Area 0014H 0013H Vector Table Area 0000H 0000r 34 CHAPTER 3 CPU ARCHITECTURE Figure 3 3 Memory Map uPD78P9014 BEC eee FFFFH
134. ree quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also
135. rial clock SCKO serial output SOO and serial input S10 1 Register setting 3 wire serial I O mode settings are performed using serial operating mode register 00 CSIMOO the asynchronous serial interface mode register 00 ASIMOO and the baud rate generator control register 00 BRGCOO a Serial operating mode register 00 CSIMOO CSIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets CSIMOO to 00H Symbol 7 Address After Reset R W CSIMOO CO mE SECHS IE CHEN FF72H 00H R W Operation stop Operation enable DIROO Start Bit Specification 0 MSB 1 LSB ES Clock Selection in 3 Wire Serial I O Mode Input clock to SCKO pin from external Dedicated baud rate generator output Caution Be sure to set 0 to bit 0 and bits 3 to 6 125 CHAPTER 8 SERIAL INTERFACE 00 b Asynchronous serial interface mode register 00 ASIMOO ASIMOO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ASIMOO to 00H When the 3 wire serial I O mode is selected 00H must be set to ASIMOO Symbol 7 Address After Reset R W ASIMo0 See e E AA FE70H 00H RW Transmit operation stop Transmit operation enable Receive operation stop Receive operation enable No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity 0 7 bits 1 8 bits O 1
136. ssssseeeeeneemenee nennen nere nnne 162 12 1 4 One time PROM screening esssessesesssesseeeenneen nennen nennen nennen nest ee nnne nnne 163 13 CHAPTER 13 INSTRUCTION SET ressent nnnnnnnn teaser stes stria trs intr danse sess annm ananas 165 13 1 Operation eoruni LT LTD ME Medii Laid cae 165 13 1 1 Operand identifiers and description methods ssssssseeneeneeneeneene 165 13 1 2 Description of operation column ssssseeeeeeeneneemnenn eene nene 166 13 1 3 Description of flag operation column sseeenenenen eee 166 13 2 Operation Listi en 167 13 3 Instructions Listed by Addressing Type eee 172 APPENDIX A DEVELOPMENT TOOLS seseeeeeeeeeeseeennnne nnns nnnn nnns nas sn nina n sinn ases nan an nn 175 A 1 Language Processing Software eeeeeeeeeeeeseseee eene e nennen nnn nnn nnns 177 A2 PROM Writings TIOOls tects soceechec aa a Ee EA aaa a eaae are ra arae Ae aae a aara e ao aeta i 178 A 2 1 HarOW8re c ie EE REPERI CN RC UR E ET 178 A 2 2 SOftWale te oi sero ieee he aie et A A oh ND NEN e 178 A 3 Debugging Tools 1 aee riter LI eee redesign eei a er e ene 179 AGA Hardware ien eee eet ete ii ett i er ice ee educ idt 179 A 3 2 Software he ie eletto receta rada t edm ea ptu 180 APPENDIX B EMBEDDED SOFTWARE
137. stack pointer are control registers 1 Program counter PC The program counter is a 16 bit register which holds the address information of the next program to be executed In normal operation the PC is automatically incremented according to the number of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents is set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 7 Program Counter Configuration 15 0 PC 2 Program status word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 8 Program Status Word Configuration 7 0 ew e e o ee oe 41 CHAPTER 3 CPU ARCHITECTURE 42 a b c d Interrupt enable flag IE This flag controls interrupt request acknowledge operations of CPU When IE 0 the IE is set to interrupt disabled DI status All interrupt requests except non maskable interrupt are disabled When IE 1 the IE is set to interrupt enabled El status and interrupt request acknowledgement is controlled with an interrupt mask flag for various interrupt sou
138. ster 00 CSIMOO Asynchronous serial interface mode register 00 ASIMOO Asynchronous serial interface status register 00 ASISOO Baud rate generator control register 00 BRGCOO0 97 86 Figure 8 1 Block Diagram of Serial Interface 00 erges ta serial interface status register 00 fists Asynchronous serial interface mode register 00 ASIMOO Receive buffer register RXBOO SIOO00 Direction control circuit Receive shift register RXSO00 Transmit shift register TXS00 SIO00 T RxD SIO P22 gt t SCK output Transmit control circuit control circuit Receive control PM20 circuit INTSR INTCSIO INTST ASCK SCKO P20 5 4 Note 00 SOVSHALNI 1VIH3S 8 HdldVHO Baud rate generator fx 2 to fx 2 CSIEO0 L_ CSCK00 TXEOO RXEO0 eme ren nem die rate generator control register 00 Serial operating mode register 00 CSIMOO j Ca Internal bus Note For the baud rate generator configuration see Figure 8 2 CSIEO0 DIROO cso 66 Figure 8 2 Block Diagram of Baud Rate Generator BRGCOO write Pan TXE00 Io Clear Clear Transmit clock 12 3 bit counter CSIEO0 TXEOO RXE00 fx 28 fx 2 Selector ASCK SCKO P20
139. t 3 read signal WR port 3 write signal 64 CHAPTER 4 PORT FUNCTIONS Figure 4 8 Block Diagram of P32 PUOS p P ch Alternate 4 function RD x Sal Internal bus Output latch P32 4 P32 INTP2 PUO pull up resistor option register PM port mode register RD port 3 read signal WR port 3 write signal 65 CHAPTER 4 PORT FUNCTIONS 4 3 Port Function Control Registers The following two types of registers control the ports Port mode registers PMO to PM3 Pull up resistor option register PUO 1 Port mode registers PMO to PM3 These registers are used to set port input output in 1 bit units PMO to PM are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets these registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to Table 4 3 Caution As port 3 has an alternate function as external interrupt input when the port function output mode is specified and the output level is changed the interrupt request flag is set When the output mode is used therefore the interrupt mask flag should be set to 1 beforehand Table 4 3 Port Mode Register and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function Name Input Output P30 Input Input Output Input Input Output Input
140. t of resetting is released when the RESET pin is later made high and the system clock starts oscillating At this time the time during which oscillation stabilizes 2 fx is automatically secured After that the CPU starts instruction execution at the low speed of the system clock 1 6 us at 5 0 MHz operation 2 After the time during which the Vpp voltage rises to the level at which the CPU can operate at the highest speed has elapsed the processor clock control register PCC is rewritten so that the high speed can be selected 75 MEMO 76 CHAPTER 6 8 BIT TIMER EVENT COUNTER The uPD789014 Subseries provide the following on chip timers 1 8 bit timer event counters TM00 and TM01 These counters can be used as interval timers external event counters and for output of square waves of any frequency 2 Watchdog timer WDTM The watchdog timer can also be used to generate a non maskable interrupt maskable interrupt or RESET signal at any intervals set in advance refer to CHAPTER 7 WATCHDOG TIMER 77 CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 1 Functions of 8 Bit Timer Event Counter The 8 bit timer event counters have the following functions nterval timer External event counter Square wave output 1 8 bit interval timer When the 8 bit timer event counter is used as an interval timer it generates an interrupt at any time intervals set in advance Table 6 1 Interval Time of 8 Bit Time
141. t processing Retains HALT mode Non maskable interrupt request Executes interrupt processing RESET input Reset processing x don t care 151 CHAPTER 10 STANDBY FUNCTION 10 2 2 STOP mode 1 Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction Cautions 1 When the STOP mode is set the X2 pin is internally pulled up to Voo to suppress the current leakage of the crystal oscillation circuit block Therefore do not use the STOP mode in a system where the external clock is used as the system clock 2 Because the standby mode can be released by an interrupt request signal the standby mode is released as soon as itis set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset When the STOP mode is set therefore the HALT mode is set immediately after the STOP instruction has been executed the wait time set by the oscillation stabilization time select register OSTS elapses and then an operation mode is set The operation status in the STOP mode is shown in the following table Table 10 3 STOP Mode Operating Status Item STOP Mode Operating Status Clock generator Stops system clock oscillation CPU Stops operation Port Output latch Retains the status before setting the STOP mode 8 bit timer event counter Enables operation only when TIO or TI1 is selected as count clock Watchdog timer Stops
142. t with an 8 bit memory manipulation instruction RESET input sets INTMO to 00H Figure 9 4 External Interrupt Mode Register 0 Format Symbol 7 6 5 4 Address After Reset R W 3 2 1 0 INTMO ES21 ES20 ES11 ES10 ESO1 ES00 EE FFECH 00H R W ES21 ES20 INTP2 Valid Edge Selection Falling edge Rising edge Setting prohibited Both rising and falling edges Falling edge Rising edge Setting prohibited Both rising and falling edges Falling edge Rising edge Setting prohibited Both rising and falling edges Cautions 1 Be sure to set 0 to bits 0 and 1 2 Before setting INTMO register be sure to set the corresponding interrupt mask flag xxMKx 1 to disable interrupts After setting INTMO register clear the interrupt request flag xxIFx 0 clear the interrupt mask flag xxMKx 0 to enable interrupts 137 CHAPTER 9 INTERRUPT FUNCTIONS 4 Program status word PSW The program status word is a register used to hold the instruction execution result and the current status for interrupt requests The IE flag to set maskable interrupt enable disable is mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instruction and dedicated instructions El DI When a vectored interrupt request is acknowledged PSW is automatically saved into a stack and the IE flag is reset to O It is reset from the stack with the RETI and POP PS
143. tential as Vss Do not ground the capacitor to a ground pattern in which a high current flows Do not fetch signals from the oscillator Figure 5 4 shows incorrect examples of resonator connection 71 CHAPTER 5 CLOCK GENERATOR 72 Figure 5 4 Incorrect Examples of Resonator Connection 1 2 a Too long wiring b Crossed signal line PORTn n 2 0 to 3 Vss X1 X2 Vss X1 X2 CHAPTER 5 CLOCK GENERATOR Figure 5 4 Incorrect Examples of Resonator Connection 2 2 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates Voo High current Gs ladle Ts e Signal is fetched Vss x1 X2 ill 7ZT 5 4 2 Divider circuit The divider circuit divides the output of the system clock oscillator fx to generate various clocks 73 CHAPTER 5 CLOCK GENERATOR 5 5 Operation of Clock Generator 74 The clock generator generates the following clocks and controls the operation modes of the CPU such as the standby mode System clock fx e CPU clock fcPu Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register PCC as follows a The low speed mode 2fceu 1 6 us at 5 0 MHz operation of the system clock is selected when the RESET signal is generated PCC 02H While a low level is i
144. ternal NTP1 NTP2 NTSR End of serial interface 00 UART reception Internal NTCSIO End of serial interface 00 3 wire transfer NTST End of serial interface 00 UART transmission NTTMO Generation of matching signal of 8 bit timer event counter 00 NTTM1 Generation of matching signal of 8 bit timer event counter 01 Notes 1 Priority is the priority order when several maskable interrupts are generated at the same time 0 is the highest order and 7 is the lowest order 2 Basic configuration types A to C correspond to A to C in Figure 9 1 132 CHAPTER 9 INTERRUPT FUNCTIONS Figure 9 1 Basic Configuration of Interrupt Function A Internal non maskable interrupt Internal bus Vector table address generator gt Standby release signal Interrupt request B Internal maskable interrupt Internal bus T Vector table address generator Interrupt request gt IF gt Standby release signal C External maskable interrupt Internal bus External interrupt mode register 0 INTMO Vector table Edge address generator detector _ Standby release signal Interrupt request IF interrupt request flag IE interrupt enable flag MK interrupt mask flag 133 CHAPTER 9 INTERRUPT FUNCTIONS 9 3 Interrupt Function Control Registers The following four registers are used to co
145. terrupt Request Signal Name sse 134 9 3 Time from Generation of Maskable Interrupt Request to Processing seeeeese 141 10 1 HALT Mode Operating Status esses nennen nennen nnne tenen restes nennen nnns nnns 149 10 2 Operation after Release of HALT Mode nennen nmenn nnne enne nnne nnnnn nnns 151 10 3 STOP Mode Operating Status 2 etin eam utei d e eI ree altiores 152 10 4 Operation after Release of STOP Mode sssssssssseeeeeeenee nennen nennen neret enne 154 17 LIST OF TABLES 2 2 Table No Title Page 11 1 Hardware Status aiter ReSQL u icc pee de debe qe tet toii oett P egt do Pit ce on 157 12 1 Differences between uPD78P9014 and Mask ROM Versions eeeeeeeeee 159 12 2 Pins in PROM Programming Mode sese nnne nnne nnne rnnt 160 12 3 Operating Modes of PROM Programming ssssesseeseeeneeeeeneeen nennen nennen nennen tenens 160 13 1 Operand Identifiers and Description Methods sssseseeneneeeeeeneennn enne 165 18 CHAPTER 1 GENERAL 1 1 Features O ROM and RAM capacity Item Program Memory Data Memory Part Number Internal High Speed RAM uPD789011 2 Kbytes 128 bytes uPD789012 4 Kbytes uPD78P9014 8 Kbytes 256 bytes Minimum instruction execution time can be changed from high speed 0 4 us to low speed 1 6 us system clock at 5 0 MHz operation O
146. the setting refer to Table 8 2 Serial Interface 00 Operating Mode Settings 29 al Mie CHAPTER 2 PIN FUNCTIONS 2 2 4 P30 to P32 Port 3 30 These pins constitute a 3 bit I O port In addition they also function as external interrupt input and timer I O LEDs can be driven directly Port 3 can be specified in the following operation modes in 1 bit units 1 Port mode In this mode port 3 functions as a 3 bit I O port which can be set in the input or output port mode in 1 bit units by using the port mode register 3 PM3 When the port is used as an input port an on chip pull up resistor can be used in the pull up resistor option register PUO 2 Control mode In this mode the pins of port 3 function as external interrupt input and timer I O a INTPO to INTP2 These pins input external interrupt signals whose valid edge can be specified to either rising falling or both edges b TIO TI1 These pins input an external clock to the 8 bit timer event counter c TOO TO1 These are 8 bit timer output pins CHAPTER 2 PIN FUNCTIONS 2 2 5 RESET This pin inputs an active low system reset signal 2 2 6 X1 X2 These pins are used to connect a crystal resonator for system clock oscillation To supply an external clock input the clock to X1 and input the inverted signal to X2 2 2 7 VoD Positive power supply pin 2 2 8 Vss Ground pin 2 2 9 Vpp uPD78P9014 only A high voltage should be a
147. timer event counter as an interval timer the settings are required in the following order 1 Set the 8 bit timer register On TMOn to operation disable TCEOn bit 7 of 8 bit timer mode control register On TMCOn 0 2 Set count clock of 8 bit timer event counter refer to Table 6 4 3 Set count value to CROn 4 Set TMOn to operation enable TCEOn 1 When the count value of the 8 bit timer register On TMOn matches the value set to CROn the value of TMOn is cleared to 0 and TMOn continue counting At the same time an interrupt request signal INTTMn is generated Table 6 4 shows interval time and Figure 6 5 shows the timing of interval timer operation Caution When the count clock and TMOn operation enable are set simultaneously with TMCOn using the 8 bit memory manipulation instruction the error of a cycle from which a timer has been started may become one clock or more Therefore settings must be done in the above order to operate the 8 bit timer event counter as an interval timer Remark n O 1 Table 6 4 Interval Time of 8 Bit Timer Event Counter TCLOn1 TCLOnO Minimum Interval Time Maximum Interval Time Resolution 1 fx 200 ns 28 fx 51 2 us 1 fx 200 ns 25 fx 6 4 us 213 fx 1 64 ms 25 fx 6 4 us TIn input cycle 28 x Tin input cycle TIn input edge cycle TIn input cycle 28 x Tin input cycle TIn input edge cycle Remarks 1 fx system clock oscillation frequency
148. tion enable TCLO10 8 Bit Timer Register 01 Count Clock Selection fx 5 0 MHz fx 25 156 kHz Note Rising edge of TI1 Note Falling edge of TI1 Output disable port mode Output enable Note When clock is externally input timer output cannot be used Caution Be sure to select the count clock after stopping timer operation TCE01 0 For details refer to 6 4 Operation of 8 Bit Timer Event Counter Remarks 1 fx system clock oscillation frequency 2 at fx 5 0 MHz operation CHAPTER 6 8 BIT TIMER EVENT COUNTER 3 Port mode register 3 PM3 This register sets port 3 input output in 1 bit units When using the P30 INTPO TIO TOO and P31 INTP1 TI1 TO1 pins for timer output set PM30 PM31 and the output latch of P30 P31 to 0 PMB is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 6 4 Port Mode Register 3 Format Symbol 7 Address After Reset R W III I ear em om o P3n Pin Input Output Mode Selection n 0 to 2 Output mode output buffer ON Input mode output buffer OFF 83 i i id we v CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 4 Operation of 8 Bit Timer Event Counter 6 4 1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set to the 8 bit compare register 00 and 01 CROO and CRO1 in advance To operate the 8 bit
149. ty for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following th
150. ut output 22 Pull up resistor Total 22 internal pull up resistor can be connected by software 4 2 1 Port 0 This is an 8 bit I O port with output latch Port 0 can be specified in the input or output mode in 1 bit units by using the port mode register 0 PMO When P00 to P07 pins are used as input port pins on chip pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO Port 0 is set in the input mode when the RESET signal is input Figure 4 2 shows the block diagram of port O Figure 4 2 Block Diagram of P00 to P07 WRpeuo P ch RD HO WRport Output latch POO to P07 Internal bus P00 to P07 PMO0 to PM07 Remark PUO pull up resistor option register PM port mode register RD port 0 read signal WR port 0 write signal 59 i rit id ty NG CHAPTER 4 PORT FUNCTIONS 4 2 2 Port 1 This is an 8 bit I O port with output latch It can be specified in the input or output mode in 1 bit units by using the port mode register 1 PM1 When using P10 to P17 pins as input port pins on chip pull up resistors can be connected in 8 bit units by using the pull up resistor option register PUO This port is set in the input mode when the RESET signal is input Figure 4 3 shows the block diagram of port 1 Figure 4 3 Block Diagram of P10 to P17 P ch RD HO WRport
151. with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function QTOP and EEPROM are trademarks of NEC Corporation MS DOS Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or oth
152. x 200 ns 25 fx 6 4 us 213 fx 1 64 ms 25 fx 6 4 us Remarks 1 fx system clock oscillation frequency 2 atfx 5 0 MHz operation 3 n20 1 87 CHAPTER 6 8 BIT TIMER EVENT COUNTER 88 Figure 6 7 Square Wave Output Timing Count clock twon courtvave 00 or XJ YW Jos X 2 X Yom Yor X 2 0 A A Clear Clear i e lt lt lt 7 Count start Interrupt accepted Interrupt accepted X5 pp 3 TE ET Note The initial value of TOn during output enable TOEOn 1 becomes low level TCEOn Remark n O 1 i TAA j ed CHAPTER 6 8 BIT TIMER EVENT COUNTER 6 5 Notes on Using 8 Bit Timer Event Counters 1 Error on starting timer An error of up to 1 clock occurs after the timer has been started until a coincidence signal is generated This is because the 8 bit timer registers 00 and 01 TMOO and TMO1 are started in asynchronization with the count pulse Figure 6 8 Start Timing of 8 Bit Timer Register Count pulse A Aeg NA Mea ae ee TMOO and TMO1 00H 01H 02H 03H 04H count values Timer starts 2 Setting of compare register The compare registers 00 and 01 CROO and CR01 can be set to 00H Therefore one pulse can be counted when an 8 bit timer event counter operates as an event counter Figure 6 9 External Event Counter Operation Timing TIO and TI1 inputs Foe A QUIS II EI CRO00 CRO1 00H TMOO and T
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