Olimex STM32-P107 datasheet
Contents
1. EA E EAE AAEN AE EE EE E OLIMEX LTD BULGARIA i USB CIRCUIT USB HOST 3 3 MCU E WWW Ol imex com HN1x3 O Close H Open CLOSE Qs H U1 S von bs WKUP OTG_VBUS pm 45V HOST PWR USB HOSTI 74 ep PAO WKUP USART2 CTS ADC12 2 ETR TIV5 MI CRS ETH REF CLK s ETH REF CLK PWR 5V_HOST PWR E 5V HOST PWR 1 10d PA1 USART2 RTS ADC12 CHZ TIV CHZ ETH MI CLK ETH RMI REF ETH RMIT ETH OR NA USB HOST D USB HOST D _ 200 2d VOD PA2 USART2_TX TIMB_CH3 ADC12_IN2 TIV2_CH3 ETH USB HOST D USB HOST D 300 44 VDD PA3 USART2_RX TIM5_CH4 ADC12_IN3 TIV2_CH4 ETH_MI_COL CS CS MMC 42 ol e ol VDD PA4ISP1_NSS DAC_OUTI USART2_CK ADC12_IN4 E EET PAS SPI1_SCK DAC_OUT2 ADC12_IN5 Bi DAS este PA6 SP11_MSO ADC12_IN6 TIVB_CH1 TIM1_BKIN 2 ETH CRS DV ETH CRS DV USB D 5V USB A 4 uj ul 7 8 _ 12 CHZ2. LO S a 7 1975mil 4950mil 5200mil All measures are in mils AVAILABLE DEMO SOFTWARE NEW STM32 P107 demo package with Micrel PHY Blinking LED Demo software for EW ARM 5 50 Ethernet Demo software for EW ARM 5 50 USB Demo software for EW ARM 5 50 SD card Demo software for EW ARM 5 50 Page 16 ORDER CODE STM32 P107 assembled and tested How to order You can order to us directly or by any of our distributors Check our web www olimex com dev for more info Manual revision history REV Initial created December 2009 REV A edited by TU December 2010 REV B demo software added and mechanical dimensions detailed REV C Rev A schematic and added more programmers in BOARD USE REQUIREMENTS REV D edited June 2011 changed schematic REV E changed schematics to rev B added board revision history REV F added BOOTO E E description changed dimensions updated revision pictures updated disclaimer Board revision history rev A 1 ST2052BD is excha
3. PAS Pia 5 FET anay gt 13 4 STM32 P107 development board User s Manual Pb free Green All boards produced by Olimex are ROHS compliant Rev F August 2012 Copyright c 2012 OLIMEX Ltd All rights reserved Page 1 INTRODUCTION STM32 P107 prototype board provides easy way for developing and prototyping with the new STM32F107VCT6 connectivity line microcontroller produced by STMicroelectronics STM32 P107 has JTAG port for programming and debugging USB_OTG user button two status leds and most of the GPIOs are on extension headers where you can connect your additional circuits BOARD FEATURES CPU STM32F107VCT6 32 bit ARM based microcontroller with 256 KB Flash 64 KB RAM USB OTG Ethernet 10 timers 2 CANs 2 ADCs 14 communication interfaces connector with ARM 2x10 pin layout for programming debugging USB USB HOST 100Mbit Ethernet RS232 Mini SD MMC card connector UEXT connector Power Jack Two user buttons RESET button and circuit Two status leds Power on led battery connector Extension port connectors for many of microcontrollers pins FR 4 1 5 mm 0 062 soldermask silkscreen component print Dimensions 132 08x96 52mm 5 2x3 8 ELECTROSTATIC WARNING The STM32 P107 board is shipped in protective anti static packaging The board must not be subject to high electrostatic
4. 1 RXER 26 3306 1645 5 5 5 45 100nF CERTE XERIISO m LEDUTEST 25 330R Rag ES ELI x f INT PHYADO I __ Tino TM icis 8 a 8 c TX PC_DCD 1 100R 1 9994 emm s 555255851486 3 3V 4 5 lt 4 a Q OR ZG j USART2 RIS 1 R29 1 5 5 2 6 TAMPER 3 100R 1 R33 WKUP Og De A _USART2 3 7 I 1 es 330R amp 4 U2 USART2 CTS 4 8 95 Ri I 33 8 Tee KSBz24BLMM reo 3 3V BOOTO_E J 2 33 5 I d co _ 5 5 I 05 3 3V U3PWR R27 NA ENT 3 3V 1 E FX Pl C29 do UEXT_PWR_E HN XZ Open 154148 Hort 1 1 e c50 ule CLOSE Treo LN HEN E A 21 es 1 1 1 UEXT 47k 10uF 6 3V 10nF C48 11 4 2 14 3 USART3 TX 3 4 USARI3RX 2 ee ee ean ee ee ee eee Eee 100nF E I 201 SCL 5 6 2 1 SDA i S l l iil SPI
5. SS 8 076 12111 Hitt SMD jumpers 25222028220 4 M 208 2 ES ae a zm e Du C 2 OLIMEX COM DEU 2 187 Po F if WI 2 9 m s s E 2E 21 2 5 6 NL PWR jack 6 5 9 VDC d TAMPER SO MNC PTH jumpers Buttons SD MMC card Proto area RST_E amp BOOTO_E jumper POWER SUPPLY CIRCUIT STM32 P107 can take power from three sources PWR connector where 6 5 9 V DC 6V AC is applied by external power source 5V OTG PWR from USB 5 from JTAG The programmed board power consumption is about 70 mA RESET CIRCUIT STM32 P107 reset circuit includes JTAG connector pin 15 U2 STE101P pin 28 RESET R73 10k 74 330 R75 1000hm 1 76 C55 100nF STM32F107 pin 14 NRST and RESET button Page 8 CLOCK CIRCUIT Quartz crystal 25 MHz is connected to STM32F107 pin 12 OSC_IN and pin 13 OSC_OUT Quartz crystal 32 768kHz is connected to STM32F107 pin 8 14 5 32 and 9 PC15 OSC32 OUT JUMPER DESCRIPTION PWR_SEL 5 6 3 4 1 2 BO 0 0 1
6. as AF RX TX CTS RTS CK as AF RX TX CTS RTS lt em Ko lt Ko mene um juo nme MOSI SD MISO MCK gt spi2 i2se2 SCK CK NSS WS as AF MOSI SD MISO MCK 5 1293 P SCKCK NSS WS as AF OSC32 IN OSC32 OUT TAMPER RTC ALARM SECOND OUT device bxCAN1 device CAN1_TX as AF CAN 1_RX as AF a 512B C bxCAN2 device CT oe TX a AF CAN2 RX as AF Haw m VDDA DAC OUT as AF DAC_OUT2 as AF mw lt Page 5 OxFFFF FFFF 0 000 0000 OxDFFF FFFF 0xC000 0000 OxBFFF FFFF 0xB000 0000 OxAFFF FFFF 0x8000 000 Ox7FFF FFFF 0x6000 0000 FFFF 0x2000 0000 FFFF 0 0000 0000 512 Mbyte block 7 Cortex M3 s internal peripherals 512 Mbyte block 6 Not used 512 Mbyte block 5 Not used 512 Mbyte block 4 Not used 512 Mbyte block 3 Not used 512 Mbyte block 2 Peripherals 512 Mbyte block 1 SRAM 512 Mbyte block 0 Code Reserved BOOT pins 0x5000 0400 OxSFFF FFFF USB OTG FS 0x5000 0000 0x5000 Reserved 0x4003 0000 OxAFFF FFFF Ethernet 0x4002 8000 0x4002 9FFF Reserved 0x4002 3400 0x4002 7FFF 0x4002 3000 0x4002 33FF Reserved 0x4002 2400 0x4002 2FFF Flash interface 0 4002 2000 0x4002 23FF 0x4002 1400 0x4002 1FFF 0x4002 1000 0x4002 13FF Reserved 0x4002 0800 0x4002 OFFF 0x4002 040
7. zo 5 5 R9 5 STAT STAT2 8 R7 5 8 3 GNDA E I I 3 PIN G 300R 1 8 E a 1492 Ppa entsex sn creo Vel conan sashes 52 j CLOSE I J J eee eee eee eel BOARD LAYOUT 3V_battery PTH jumpers connector UEXT JTAG RST jumpers Mount hole wr eT hod bt ty ae 4 Ethernet STAG 1 wi Aes eee awe connector S NE 5 55 vi RESET gt EXE ITPhSO PPEPEDDIST VOLL ev 9 PESI ERI m LUEEEEEEHEEEEERCEEE 9 9 ie Q O E o T j U EI EI EI E E E EJ mica2R6 849 1 2 4 eco A O O O E Sr S R19 lofololo ec2 J d gd ogo gag aga ogri 4 z pcc JUL y SES pce g 7 mems i 5 2 a USB HOST s USB_OTG
8. 3 6 V Sample and hold capability Temperature sensor up to 2 MSps in interleaved mode 2 x 12 bit D A converters 12 channel DMA controller Page 3 Supported peripherals timers ADCs DAC 1758 SPIs and USARTs Debug mode Serial wire debug SWD amp JT AG interfaces Cortex M3 Embedded Trace Macrocell 80 fast I O ports 80 I Os all mappable on 16 external interrupt vectors and almost all 5 V tolerant 10 timers four 16 bit timers each with up to 4 IC OC PWM or pulse counter and quadrature incremental encoder input 1 x 16 bit motor control PWM timer with dead time generation and emergency stop 2 x watchdog timers Independent and Window SysTick timer a 24 bit downcounter 2 x 16 bit basic timers to drive the DAC 14 communication interfaces 2 x interfaces 5 USARTs ISO 7816 interface LIN IrDA capability modem control 3 SPIs 18 Mbit s 2 with a multiplexed I S interface that offers audio class accuracy via advanced PLL schemes 2 x CAN interfaces 2 0B Active with 512 bytes of dedicated SRAM USB 2 0 full speed device host OTG controller with on chip PHY that supports HNP SRP ID with 1 25 Kbytes of dedicated SRAM 10 100 Ethernet MAC with dedicated DMA and SRAM 4 Kbytes IEEE1588 hardware support MII RMII available on all packages CRC calculation unit 96 bit unique ID Page 4 BLOCK DIAGRAM TRACED 0 3 ETM ACE a
9. B1 0 B1 1 USB D USB D When position 1 2 is shorted the board is power supplied from When position 3 4 is shorted the board is power supplied from USB When position 5 6 is shorted the board is power supplied from External power source Default state is position 5 6 shorted When this jumper is in position 1 BOOTO is connected to 3 3V and when the jumper is in position B0 0 BOOTO is connected to GND Default state is BO 0 When this jumper is in position B1 1 BOOTI is connected to 3 3V and when the jumper is in position B1 0 is connected to GND Default state is B1 0 When is in position H connects 5bV HOST to VBUS When is in position connects 5 PWR to VBUS Default state is When is in position H connects USB HOST D to DP When is in position connects USB D to DP Default state is When is in position H connects USD HOST D to OTG DM When is in position O connects USB OTG D to OTG DM Default state is O When is closed disables Ethernet transceiver STE101P Power Down Mode is active Default state is closed Page 9 3 3V lt Q2 lt t 93 lt gt CU_E Enable microcontroller 3 3V power supply Default state is closed Enable regulator VR2 3 3V LM1117 D
10. TIMA_CHI USART1_TXICAN2 TX a OTG D C23 100nF bius 7 2 1 RX SCL 7 ll PBS TIM4 CH3 ETH MI TXD3 DC1 SCL CAN1 bg 2C1 SDA PRO C38 C39 2 10 202 SCLIUSARTS TXETH FX Gr in PB10 T ETT L1 RT URNA TXETH RX X 2 RM 11 2 2 SDA USART3 RX ETH TX RMI TX VREF PB12 SPi2_NSS I2S2_WS I2C2_SMBAL USART3_CK TIM1_BKIN CAN2_RX ETH_MI_TXDO ETH_RMI_TXDO 52 ETH TXD1 lt 33V 13 6 2 SCK PS2 CK USART3 CTS TMi CHINICAN2 MI TXDI ETH _RMILTXD1 SA PB14 SP2_MSOTIM_CH2NUSART3 RTS b4 CS UEXT Sots ucc 5 BOOTO 4 18 8 2 6 252 a a SSR 10k 94 POYADCI2 he ET RMD 9 1 1 HN1x3 BOOT FCUADCI2 INTI ETH 7 P JT AG M4G2 IRM3G2 SE SD MM 1 PC2 ADC12_IN12 ETH 2 95 10 10k 10k R24 bg _ 1 gt PC3 ADC12_IN13 ETH TX h3 ETH RXDO 2 CS MMC CS MMC 1M R5 e POAIADC12_INI4 ETH_MLRXDO ETH RMLRXDO 4 RXD1 B SPI3 MOSI SPI3 MOSI 1 co O BO 1 erus PCS ADC
11. manual differ from the latest revision of the board The product described in this document is subject to continuous development and improvements All particulars of the product and its use contained in this document are given by OLIMEX in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product OLIMEX Ltd shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product This evaluation board kit is intended for use for engineering development demonstration or evaluation purposes only and is not considered by OLIMEX to be a finished end product fit for general consumer use Persons handling the product must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards Olimex currently deals with a variety of customers for products and therefore our arrangement with the user is not exclusive Olimex assumes no liability for applications
12. 0 F7FF Ox1FFF 7FFF 0x0803 FFFF 0 0800 0000 Ox07FF FFFF 0x0008 0000 Aliased to Flash or system 0x0007 FFFF memory depending on 0 0000 0000 Page 6 3 3VA_MCU_E SCHEMATIC STM32 P107 rev B
13. 0 0x4002 07FF 0x4002 0000 0x4002 Reserved 0x4001 3C00 0x4001 FFFF 0x4001 3800 0x4001 3BFF Reserved 0x4001 3400 0x4001 37FF 0 4001 3000 0x4001 33FF 0 4001 2200 0x4001 0 4001 2800 0x4001 2BFF 0 4001 2400 0x4001 27FF 0 4001 1200 0x4001 23FF ARES 0x4001 1800 0x4001 1BFF 0x4001 1400 0x4001 17FF 0x4001 1000 0x4001 13FF 0 4001 0 00 0x4001 OFFF 0x4001 0800 0x4001 OBFF 0x4001 0400 0x4001 07FF 0x4001 0000 0x4001 3FFF Reserved 0x4000 7800 0x4000 FFFF 0x4000 7400 0x4000 77FF PWR 0x4000 7000 0x4000 73FF 0x4000 6 00 0x4000 6FFF bxCAN2 0x4000 6800 0x4000 6BFF bxCAN1 0x4000 6400 0x4000 67FF 0x4000 5 00 0x4000 63FF 2 2 0 4000 5800 0 4000 5BFF 1261 0 4000 5400 0 4000 57FF 1 UART5 0x4000 5000 0x4000 53FF UART4 0x4000 4C00 0x4000 4FFF USART3 0x4000 4800 0x4000 4BFF USART2 0x4000 4400 0 4000 47FF 5 251 0 4000 3 00 0x4000 3FFF 5 21252 0 4000 3800 0 4000 Reserved 0x4000 3400 0x4000 37FF IWDG 0x4000 3000 0x4000 33FF WWDG 0 4000 2C00 0x4000 2FFF 0x4000 2800 0x4000 2BFF Reserved 0 4000 1800 0x4000 27FF TIM7 0x4000 1400 0x4000 17FF TIMG 0x4000 1000 0x4000 13FF 5 0 4000 0 00 0x4000 OFFF TIM4 0x4000 0800 0x4000 OBFF TIM3 0x4000 0400 0x4000 07FF TIM2 0x4000 0000 0x4000 0 2001 0000 SRAM aliased 0x2000 FFFF by bit banding 0x2000 0000 Ox1FFF F800 OX1FFF FFFF Ox1FFF 800
14. 12_IN15 ETH_MI_RXD1 ETH_RMI_RXD1 s STATI qm RST ME 2 POB I2S2 STAT2 DI 1 In ais R14 253 2 5 8 TMS 1 SPI3 SCK I ie Po SC TRIG Fd E See 13 LO RM3G1 10k RM4G1 10k B zoll PCIOUART4_TXUSARTS_TXISAS SOK o MISO 2 SPI3 MISO TDO i EE gs oT 1 1 BERI RXUSART3 RXSPG MSO Bo SPIS MOSI 5 5 MOSI RST 5 i ALS RST 14 WT PCIZ UARTS TX USART3 5 MOSI TAMPER PC12 R T RM4G3 10k CL470nH 0805 1 76R 250mA RST 74 PCIS TAMPERRIC PC13 14 10pF RST 1442 RM464 5 1 14 PC14 0SC32 IN 7 oot 4 1 1 mm 470 6 PCIS OSC32 32768Hz amp pE QC 3 OpF OPEN p PEo Q PEDTIVA_ETR FDO OSC INCAN1 e IIS GS dl2 PE1 j FE FDI OSC OUTCAN TX B3 D1 2 2 ETRUARTS p4 USART2 CIS USART2 CTS C Lu I EQ I D ccc LE E 3 POS USART2_CTS l5 USART2 RTS USART2 RTS 2 5V A 4 4 RIS USART2 TX USART2 TX S FDSUSART2 TX p USART2 RX USART2 RX FEMM EIR PD6 USART2 RX USB VBUSON Sd CHAN POY USART2
15. 3 MSO 7 8 MOSI 1 5 SCK 9 10 CS UEXT 4 POWER SUPPLY Gl RCU IT 77 pe BATOS 3 3V 3 3VA ER R10 SPI3 SCK SPI3 MISO CS UEXT 2C1 SCL 2C1 SDA USART3 TXUSART3 NSS SPI1 SCK SPI1 MISO SPI1 MOSI USART2 TXUSART2 RXUSART2 RTS USART2 CTS I 3 3VA PWR 7 RUE oS 3 3V B 5V JTAG D2 1 58195 RED GYXSD TCO805SYRK f 3 3V E 2 U S L 05 3 3V RESET CIRCU IT 1 CLOSE B104 SMD VR1 5 0V 5 PWR D3 158195 i VR2 3 3V AME 1085 LM1117IMPXADJ 3 8VA E STAT2 Tok i 19V EXT D4 1 58195 1 5 ee s 3 4 1692 STATI qo c ADU GND CLOSE 04 10k P R6 C11 NA STM1001RWXG6F You 1136 o R62 1008 1 i5 we lis R8 R56 R57 RST B1 0 B1 1 240R 1 100nF I 330R 330R I I C I Bilis Wk 6599 al 2 FOR 9 rre gt R63 470UF 16VDC TF 4 3 1008 1 _
16. CK 65 USART3 TX USART3 TX 272939 5 PE8 4d an FOS USARTS_TXETH MI RX 5s USART3 RX USART3 RX PES amp _ 2 PIAL COELIAC EN ile 45 oj PE10 PD1O USART3 MI RX Di 10k R34 PE11 42 PD11 USART3_CTS ETH RX_D2 ES _ 44 E 12 lt 44 PD12 TIM4_CH1 USART3_RTS ETH_MIl_RX_D3 ETH RXER 10uF 6 3V 3 3V 1 PE13 ETH MDINT _ 48 POIS TIMA_CH2 PHY SOFT RST cu 100nF Q USB FAULT WA BKN POM 62 100nF d 3 Ci VDD 444 LAN SIM32F107VCT6 7 PHY_RSTN 3850 1 3 1 RST R36 R35 4 99k 1 SOFT RST R37 NA Ok re 211 ____________ __________ __ ___________ _ __ _ __________ Wer SSS Sa a ee eee 0 AX ay o 3 3V0 1 5k 196 Y e RST E BUTTONS ETH 1k 1 8 1 7 52 RS2 32 HN1x2 Open MDC 2 5 4 LO 5 1 1 3 3V 3 3V 4 33 53 1 INFIN U3 ETH RN RDI 5 5 32 RJLBC 060TC1 6 31 ST3232BDR SO16 M RM 5 ts Jely 3 3V 8 29 R28 GND1 LEDS NWAYEN 5 mm 5 10k i ETH CRS DV RXDV CRSDV PCS LFBK LEDO DURLEX 2 ee Cmm CS R39 RXC LED1 SPD100 NFEF 5
17. ETH DV ETH R17 33R 05 83 88888 4 PAS USART1_CK OTG FS SOF TMi CHI MCO bs VBUS HN1x3 O Close H Open 3 3VO 8344486 19 vss PAQ USART1_TX TIMI_CH2 OTG FS VBUS Es OTG 1D als 4 VSS PAMO USART1_RX TIM1_CH3 OTG FS 10 Os H 2 5 9j ves DM USB VBUSON cg PA11 USART1_CTS CAN1_RX TIM1_CH4 OTG FS 4 OTG DP USB HOST D ES PX 4d ETROTG FS bo TMS TMS 3 3V USB_OTG D USB FAULT 5 T 1 vss PA13 JTMS SWDIO 5 PATAUTCKISWOLK 19 TEK 06 LM3526 L 2 77 14 upra PA15 JTDVSP3_NSS TIM2_CH1_ETR SPI1_NSS OTG DP 228 R19 USB_D 223 33k Gist 21 FBO ADC12 MI OTG DM 2R mof E HN1x3 0 Close H Open T N USB_OTG Toute Lud 14 Vega FB1 ADC12 IN9 TIVG CHA ETH MI RXD3 TM1 B7 PB2 BOOT1 PB1 S TL H FB3 JTDO SR3_SCK TRACESWO TIN2 po m oe C34 NA USBLC6 2P6 ala PBAUNTRSTISHG EO USB HOST D 5V_OTG_PWR l _ 5V_OTG PWR VREF FBS PC1 MDSIETH OUT ETH RMI FS 6 RX PBS NA 47pF 100nF 5 R11 33R PB6 2C1_SOL
18. assistance customer product design software performance or infringement of patents or services described herein THERE IS NO WARRANTY FOR THE DESIGN MATERIALS AND THE COMPONENTS USED TO CREATE STM32 P107 THEY ARE CONSIDERED SUITABLE ONLY FOR STM32 P107 Page 18
19. efault state is closed Enables board 3 3V analog power supply Default state is closed 3 3VA_MCU_E WIN 8 GNDA E 2 Enables microcontroller 3 3V analog power supply Default state is closed Enables board analog GND Default state is closed Connects RST to TRST Default state is open RST E BOOT E jumpers Note that it is recommended to move those jumpers together either both should be open or both should be closed When both are closed RS232 boot is enabled Default states are RST E open BOOT E open INPUT OUTPUT Status green with name STATI connected to STM32F107 pin 63 PC6 DS2 MCK TIM3 Status LED2 yellow with name STAT2 connected to STM32F107 pin 64 7 1253 MCK TIM3 CH2 Power on LED red with name PWR this led shows that 3 3V is applied to the board User button with name WKUP connected to STM32F107 pin 23 PAO WKUP User button with name TAMPER connected to STM32F107 pin 7 PC13 TAMPER Reset button with name RESET connected to STM32F107 pin 14 NRST Page 10 CONNECTOR DESCRIPTIONS TAG 2 4 6 8 10 12 14 16 18 20 NN The JTAG connector allows the software debugger to talk via a JTAG Joint Test Action Group port directly to the core Instructions may be inserted and executed by the core thus allowing STM32F107 memory to be programmed with code and executed step by step by the host software For more detai
20. ls refer to IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture and STM32F107 datasheets and users manual TRST m p p 5 me GND GND GND GND GND GND GND GND ND PWR JACK Page 11 USB HOST Signal Name 5V HOST PWR USB OIG Signal Name 5 USB D USB OTG ID BAT Pin Signal Name P 1 VBAT 2 GND Page 12 RS232 The RS232 port can be used for communication when in bootloader mode To enter bootloader mode you need to close RST_E and jumpers Note that the default position of those jumpers is closed e g bootloader mode disabled Pins Signal Name NC Page 13 Signal Name 246 8 10 USART2_TX USART2_RX I2C1 SCL I2C1 SDA SPI3 MISO SPI3 SPI3 SCK CS UEXT 1 1 5 2 3 i 8 Lx _ _ L ee ow 14 Signal Name Page 15 MECHANICAL DIMENSIONS 55 0 ELECTRONICS 3800mil 3550mil
21. nged with LM3526 L 2 SD MMC signals are changed as follows SPI1 MOSI gt SPI3_MOSI 5 _5 gt SPI3_SCK MISO gt SPI3_MISO and SPI1_NSS renamed to CS_MMC 3 Changed the polarity to of C36 1 All libraries are updated 2 Ethernet PHY is changed from STE101P to MICREL s KS8721BLMM 3 All 10uF 6 3V TANT are changed to 0805 and a lot of element names are changed 4 PWR_SEL jumpers are replaced by diodes 5 USARTS is connected to UEXT while USART2 is connected to RS232 and bootloader functionality is enabled Two additional jumpers are added 6 Added UEXT_PWR_E jumper 7 A lot jumpers are added into jumpers description table Page 17 2012 Olimex Ltd Olimex logo and combinations thereof are registered trademarks of Olimex Ltd Other product names may be trademarks of others and the rights belong to their respective owners The information in this document is provided in connection with Olimex products No license express or implied or otherwise to any intellectual property right is granted by this document or in connection with the sale of Olimex products The hardware files are closed source Routing schematics and bill of materials are kept privite You may NOT reproduce the design for commercial use You may modify the design but you must then release a link to the creator website http www olimex com The software is released under GPL It is possible that the pictures in this
22. potentials General practice for working with static sensitive devices should be applied when working with this board Page 2 BOARD USE REQUIREMENTS Cables The cable you will need depends on the programmer debugger you use If you use ARM JTAG you will need LPT cable if you use ARM JTAG EW ARM USB OCD ARM USB OCD H ARM USB TINY or ARM USB TINY H you will need 1 8 meter USB A B cable for ARM USB OCD and ARM USB OCD H you will need RS232 cable too Hardware Programmer Debugger one of the Olimex ARM Programmers ARM JTAG ARM JTAG EW ARM USB OCD ARM USB OCD H ARM USB OCD TINY ARM USB OCD H Software ARM C compiler PROCESSOR FEATURES STM32 P107 board use ARM based 32 bit microcontroller STM32F107VCT6 with these features Core ARM 32 bit Cortex M3 CPU 72 MHz maximum frequency 1 25 DMIPS MHz Dhrystone 2 1 performance at 0 wait state memory access Single cycle multiplication and hardware division Memories 256Kbytes of Flash memory 64 Kbytes of SRAM Clock reset and supply management 2 0 to 3 6 V application supply and I Os PDR and programmable voltage detector PVD 25 MHz crystal oscillator Internal 8 MHz factory trimmed RC Internal 40 KHz RC with calibration 32kHz oscillator for RTC with calibration Low power Sleep Stop and Standby modes VBAT supply for RTC and backup registers 2x 12 bit 1 us A D converters 16 channels Conversion range 0 to
23. s AF SW JTAG SW JTAG JTCK SWCLK JTMS SWDIO JTDO as AF Bus Matrix MIl_TXD 3 0 RMII_TXD 1 0 TX CLK RMII TX TX TX EN RXD 3 0J RMII RXD 1 0 ER CLK RMII REF CRS DV _ MIl_COL RMII_COL MDC MDIO PPS_OUT Ethernet MAC 10 100 SOF Bug AHB2 APB2 SRAM 1 25KB EXT IT 80 Mui aie 15 0 lt gt GPIOpotA lt gt GPIO port B gt GPIO port C C GPIO port D 15 0 lt GPlOpotE gt 4 Channels 4 compl Channels coy a BKIN ETR input as AF Den PB 15 0 PC 15 0 PD 15 0 APB2 Fmax 48 72 MHz MOSI MISO oc SCK NSS as AF q USARTi s CK as AF Em 12bit ADC1 12bit ADC2 16 ADC12_INs common to ADC1 amp ADC2 VREF VDDA VREF AF alternate function on port pin AHB2 APB1 Power Voltage reg 3 3 V to 1 8 V Supply supervision 4 amp POR PDR Vpp 22 to 3 6 V Vss Flash 256 KB 64 bit Interface OSC IN OSC OUT HERE ES 3 25 MHz Reset amp clock control Standby interface 1 8 V to 3 6 V VBAT XTAL 32kHz Backup RTC AWU register E Backup interface qe C 4 Channels as AF q TIM3 C 4 Channels as AF 4 Channels ETR lt gt 4Channels
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