Home

P89LPC952/954 8-bit microcontroller with accelerated two

1. 0 P89LPC952 954 8 bit microcontroller with accelerated two clock 80C51 core 8 kB 16 kB 3 V byte erasable flash with 10 bit ADC Rev 04 24 July 2008 Product data sheet 1 General description 2 Features 2 1 The P89LPC952 954 is a single chip microcontroller available in low cost packages based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC952 954 in order to reduce component count board space and system cost Principal features B 8kB 16 kB byte erasable flash code memory organized into 1 kB sectors and 64 byte pages Single byte erasing allows any byte s to be used as non volatile data storage B 256 byte RAM data memory and a 256 byte auxiliary on chip RAM B 8 input multiplexed 10 bit ADC with window comparator that can generate an interrupt for in or out of range results Two analog comparators with selectable inputs and reference source Bi Two 16 bit counter timers each may be configured to toggle a port output upon timer overflow or to become a PWM output and a 23 bit system timer that can also be used as a RTC B Two enhanced UARTs with a fractional baud rate generator break detect framing error detection and automatic address detection 400 kHz byte wide I C bus communication port and SPI communication p
2. Product data sheet Rev 04 24 July 2008 45 of 69 NXP Semiconductors P89 LPC952 954 7 26 9 7 26 10 7 27 7 28 P89LPC952_954_4 8 bit microcontroller with 10 bit ADC Power on reset code execution The P89LPC952 954 contains two special flash elements the Boot Vector and the Boot Status bit Following reset the P89LPC952 954 examines the contents of the Boot Status bit If the Boot Status bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status bit is set to a value other than zero the contents of the Boot Vector are used as the high byte of the execution address and the low byte is set to OOH Table 9 shows the factory default Boot Vector setting for these devices A factory provided bootloader is pre programmed into the address space indicated and uses the indicated bootloader entry point to perform ISP functions This code can be erased by the user Users who wish to use this loader should take precautions to avoid erasing the 1 kB sector that contains this bootloader Instead the page erase function can be used to erase the first eight 64 byte pages located in this sector A custom bootloader can be written with the Boot Vector set to the custom bootloader if desired Table 9 Default boot vector values and ISP entry points Device Default Default Default bootloader 1 kB sector boot vector bootloader code range
3. The P89LPC952 954 has six I O ports Port 0 Port 1 Port 2 Port 3 Port 4 and Port 5 Ports 0 1 2 4 and 5 are 8 bit ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options and package chosen as shown in Table 7 Table 7 Number of I O pins available Clock source Reset option Number of UO pins Number of I O pins 48 pin package 44 pin package On chip oscillator or watchdog No external reset except during power up 42 40 oscillator External RST pin supported 41 39 External clock input No external reset except during power up 41 39 External RST pin supported 40 38 Low medium high speed oscillator No external reset except during power up 40 38 external crystal or resonator External RST pin supported 39 37 1 Required for operation above 12 MHz 7 13 1 7 13 1 1 7 13 1 2 P89LPC952_954_4 Port configurations All but three I O port pins on the P89LPC952 954 may be configured by software to one of four types on a bit by bit basis These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin 1 P1 5 RST can only be an input and cannot be configured 2 P1 2 TO SCL and P1 3 INTO SDA may only be configured to be either input only or open drain Quasi bidirectional output configuration Quasi bidirectional output t
4. tSPICLKH fF WM RY WS tsPIDV MOSI output Fig 20 SPI master timing CPHA 0 master MSB LSB out AN tsp tsPIDV IOH Y master LSB MSB out LN 002aaa908 P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 57 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC SS m Tspicyc tSPIF gt tSPIR tSPICLKL J amp tSPICLKH SPICLK A T CPOL 0 output tSPIF green i hr tsPIR SPICLKL P8 SPICLK tSPICLKH CPOL 1 output Y tsPIDSU tsPIDH MISO S input MSB LSB in p LSB MSB in tsPIDV tsPIOH tsPIDV tsPIDV tsPIF tsPIR MOSI N E output master MSB LSB out X N master LSB MSB out N LN 002aaa909 Fig 21 SPI master timing CPHA 1 ss I tsPIR m tsPIR TsPICYc tsPILEAD tsPIF rere I tsPIR tsPILAG e gt tSPICLKL tSPICLKH SPICLK A N f N L N CPOL 0 input tSPIF gt a tsPIR tSPICLKL e a SPICLK SPICLKH CPOL 1 input N Y y N Y tsPIA gt I tsPIOH tsPIOH gt tsPIOH tsPIDIS tsPIDV tsPIDv 74 y y MISO
5. 5 Functional diagram 8 bit microcontroller with 10 bit ADC 1 Fig 2 AD05 ADOO ADO AD02 ADOS 48 pin package KBIO CMP2 KB1 CIN2B KBI2 CIN2A kKBI3 CIN1B KBl4 gt CINIA KBI5 gt CMPREF KBl6 gt CMP1 KBI7 Ti gt CLKOUT XTAL2 lt XTAL1 Functional diagram Vss VDD AK lt lt PORT 04 E Kn d gt lt gt V P PORT 3 4 bd PaeLPCos2 P89LPCOSA 77 lt gt zi i lt gt PORT5477 NR lt gt A K PEA lt gt lt gt K nd 002aab358 PORT 1 PORT 2 PORT 4 TXDO lt RXDO gt TO gt SCL 4 INTO gt SDA INTI RST lt AD04 4 AD07 ADO06 gt MOSI gt MISO lt gt SS lt gt SPICLK TRIG TXD1 RXD1 gt TDI TCLK P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 5 of 69 NXP Semiconductors P89LPC952 954 6 Pinning information P89LPC952 954 4 6 1 Pinning 8 bit microcontroller with 10 bit ADC Fig 3 P3 0 XTAL2 CLKOUT P2 0 AD07 P0 2 CIN2A KBI2 ADO1 6 P1 4 INT1 5 P1 5 RST 4 P1 6 3 Vss P1 3 INTO SDA P1 2 TO SCL P1 1 RXDO P1 0 TXDO P3 1 XTAL1 P5 7 P5 6 P5 5 P5
6. NXP B V 2008 All rights reserved Prod uct data sheet Rev 04 24 July 2008 52 of 69 NXP Semiconductors P89LPC952 954 11 Dynamic characteristics Table 12 Dynamic characteristics 12 MHz Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified J 8 bit microcontroller with 10 bit ADC Symbol fosc RC fosc WD fosc T cy clk foLKLP Glitch filter tgr tsa Parameter internal RC oscillator frequency internal watchdog oscillator frequency oscillator frequency clock cycle time low power select clock frequency glitch rejection time signal acceptance time External clock tcHcx teLcx tcLCH tcHCL clock HIGH time clock LOW time clock rise time clock fall time Shift register UART mode 0 TXLXL tavxH txHax XHDX HUD serial port clock cycle time output data set up to clock rising edge time output data hold after clock rising edge time input data hold after clock rising edge time input data valid to clock rising edge time SPI interface lap P89LPC952 954 4 SPI operating frequency slave master Conditions nominal f 7 3728 MHz trimmed to 1 96 at Tamb 25 C clock doubler option OFF default nominal f 14 7456 MHz clock doubler option ON Vpp 2 7 V to 3 6 V see Figure 19 P1 5 RST pin any pin except P1 5 RST P1 5 RST pin any
7. 7 of 69 NXP Semiconductors P89LPC952 954 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Fig 5 P1 3 INTO SDA P1 2 TO SCL P1 1 RXDO P1 0 TXDO P2 7 P3 1 XTAL1 P3 0 XTAL2 CLKOUT Vpp P5 7 P5 6 P5 5 P5 4 ow O rA S ooo AAAA a cxx xx SE R Ss S M 0 ooo Y xxx lt zoo NOD x m C Ir S 22 S S Z 5 a z 000zaz2zzz ic LILLO So MO ee Ws Be T 0 004 09 rrr 0l lt wWuwNcoooc 000 75 S 0 DC GB GG 0 olini eo lholl oo lel ol a fool nm FIE ELE ELE EL 9 09 oo P89LPC954FBD48 Ol l OLIN Io al ollan IN lea l sll llle lle lel ledi ledi la m 9 99 a 4 HK G Goma au 024 lt D QQ S GC GC GC GC gt OG E a xXx xX E s GC G N zT eo oW T E n Xy F G G D LQFP48 pin configuration PO 4 CIN1A KBI4 ADO3 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 VREFP VDD P0 7 T1 KBI7 P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P2 6 P4 0 002aad095 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 8 of 69 NXP Semiconductors P89LPC952 954 6 2 Pin description 8 bit microcontroller with 10 bit ADC Table 3 Pin description Symbol Pin Type Description LQFP48 PLCC44 LQFP44 P0 0 to PO 7 lO Port 0 Port is an 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The opera
8. Data flows from master to slave on MOSI Master Out Slave In pin and flows from slave to master on MISO Master In Slave Out pin The SPICLK signal is output in the Master mode and is input in the Slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions SSis the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected Typical connections are shown in Figure 12 through Figure 14 P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 38 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 7 21 1 Typical SPI configurations master slave MISO MISO 8 BIT SHIFT N 8 BIT SHIFT REGISTER MOSI MOSI REGISTER SPI CLOCK 2 GENERATOR PORT SS J SPICLK SPICLK T 002aaa901 Fig 12 SPI single master single slave configuration master slave MISO 8 BIT SHIFT gt 8 BIT SHIFT REGISTER MS REGISTER SPI CLOCK zh SPI CLOCK GENERATOR SS GENERATOR SPICLK T 002aaa902 Fig 13 SPI dual device configuration where either can be a master or a slave
9. oscillator option is selected via the flash configuration CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Port 4 Port 4 is an 8 bit I O port with a user configurable output type During reset Port 4 latches are configured in the input only mode with the internal pull up disabled The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 11 Static characteristics for details All pins have Schmitt triggered inputs Port 4 also provides various special functions as described below P4 0 Port 4 bit O P4 1 Port 4 bit 1 TRIG Debugger trigger output P4 2 Port 4 bit 2 TXD1 Transmitter output for serial port 1 P4 3 Port 4 bit 3 RXD1 Receiver input for serial port 1 NXP B V 2008 All rights reserved Prod
10. 23 slave 0 160 160 ns tspipv SPI enable to output see Figure 20 21 22 23 data valid time slave 160 160 ns master 111 111 ns tsPIOH SPI output data hold see Figure 20 21 22 23 0 0 ns time tspiR SPI rise time see Figure 20 21 22 23 SPI outputs SPICLK 100 100 ns MOSI MISO SPI inputs SPICLK 2000 2000 ns MOSI MISO SS tsPiF SPI fall time see Figure 20 21 22 23 SPI outputs SPICLK 100 100 ns MOSI MISO SPI inputs SPICLK 2000 2000 ns MOSI MISO SS 1 Parameters are valid over operating temperature range unless otherwise specified 2 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz P89LPC952 954 4 NXP B V 2008 All rights reserved 56 of 69 Product data sheet Rev 04 24 July 2008 NXP Semiconductors P89LPC952 954 11 1 Waveforms 8 bit microcontroller with 10 bit ADC I TX output data Fig 18 Shift register mode timing write to SBUF txHDx txHDV gt set TI PUM QU CX Ka XeoX eX Ka KX gt clear RI i set RI 002aaa906 SPICLK CPOL 1 output tSPIDSU MSB LSB in D SPIDH MISO input tcLox Toy clk 002aaa907 Fig 19 External clock timing SS ni TsPICcYC tspiF gt a tsPIR le gt l lsPICLKL tSPICLKH SPICLK CPOL 0 N NF CX output tsPIF tsPIR tSPICLKL
11. 4 43 P0 0 CMP2 KBI0 AD05 42 P0 1 CIN2B KBI1 AD00 41 2 P1 7 AD04 1 44 P2 1 AD06 P89LPC952FA P89LPC954FA 27 P5 3 P5 2 19 PLCC44 pin configuration P4 6 24 Vss 22 P4 5 TDI 25 P5 0 21 P4 7 TCLK 23 P4 4 26 P4 3 RXD1 P4 2 TXD1 40 P0 3 CIN1B KBI3 AD02 002aab307 PO 4 CIN1A KBI4 ADO3 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 VDD P0 7 T1 KBI7 P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P4 0 P4 1 TRIG NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 6 of 69 NXP Semiconductors P89LPC952 954 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC P1 3 INTO SDA P1 2 TO SCL P1 1 RXDO P1 0 TXDO P3 1 XTAL1 P3 0 XTAL2 CLKOUT Vpp P5 7 P5 6 P5 5 P5 4 Fig 4 Vss 37 P0 0 CMP2 KBI0 AD05 36 P0 1 CIN2B KBI1 ADOO 35 P0 2 CIN2A KBI2 AD01 34 P0 3 CIN1B KBI3 AD02 44 P1 4 INT1 43 P1 5 RST 42 P1 6 40 P1 7 AD04 39 P2 0 AD07 38 P2 1 AD06 P89LPC952FBD P89LPC954FBD 21 22 P4 6 18 Vss 16 P4 5 TDI P5 3 112 P5 2 13 P5 0 15 P4 7 TCLK 17 LQFP44 pin configuration P4 4 20 P4 3 RXD1 P4 2 TXD1 002aab306 P0 4 CIN1A KBI4 AD03 P0 5 CMPREF KBI5 P0 6 CMP1 KBI6 VDD P0 7 T1 KBI7 P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P4 0 P4 1 TRIG NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008
12. B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 24 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC Fig 6 XTAL1 K jean reac FREQUENCY MEDIUM jean reac gt RTC XTAL2 lt LOW FREQUENCY m ADCO RCCLK 7 3728 MHz 14 7456 MHz 1 PCLK WATCHDOG i R WDT OSCILLATOR 400 kHz 30 20 PCLK Block diagram of oscillator control pem pow 105 DIVM CPU RC OSCILLATOR RCCLK ETE gt J WITH CLOCK DOUBLER TIMER 0 AND 2 TIMER 1 I C BUS UARTS 002aab409 7 7 7 8 7 9 P89LPC952_954_4 CCLK wake up delay The P89LPC952 954 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 992 OSCCLK cycles plus 60 us to 100 us If the clock source is either the internal RC oscillator watchdog oscillator or external clock the delay is 224 OSCCLK cycles plus 60 us to 100 us CCLK modification DIVM register The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register DIVM to generate CCLK This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events that would not exit Id
13. C1H FF 1111 1111 WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 1 Indicates SFRs that are bit addressable 2 All ports are in input only high impedance state after power up 3 BRGR1 0 and BRGRO 0 must only be written if BRGEN 0 in BRGCON 0 SFR is logic 0 If any are written while BRGEN 0 1 the result is unpredictable 4 The RSTSRC register reflects the cause of the P89LPC952 954 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx11 0000 5 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 6 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 7 The only reset source that affects these SFRs is power on reset JAY 10 01 YM 49 03u020J91U 110 8 v S6 6560d 168d SIOJONPUODIWIIBS dXN 8002 Aine pZ 0 eH jeeus ejep 19npoJd 69 JO LZ Y S6 Z969d168d peAJesei SIUDU IY 8002 8 dXN Table 5 Extended special function registers Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary ADCOHBND ADCO high_boundary FFEFH FF 1111 1111 register left MSB ADCOLBND ADCO low_boundary FFEEH 00 0000 0000 register MSB ADODATOR ADCO
14. Care should be taken when writing to AUXR1 to avoid accidental software resets Dual data pointers The dual Data Pointers DPTR provides two different Data Pointers to specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register Debugger interface This device contains a two wire serial debugger interface designed to be used with commercially available debugging tools An additional trigger output is provided that maybe triggered using the two wire debugger interface The Freeze register allows the user to selectively disable clocking of peripheral device timers while in the debugger mode The two wire serial debugger interface can also be used be used to program the code memory of these devices NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 43 of 69 NXP Semiconductors P89 LPC952 954 7 26 7 26 1 7 26 2 7 26 3 7 26 4 P89LPC952_954_4 8 bit microcontroller with 10 bit ADC Flash program memory General description The P89LPC952 954 flash memory provides in circuit electrical erasure and programming The flash can be erased read and written as bytes The Sector and Page E
15. If double buffering is enabled TB8 n must be updated before SnBUF is written as TB8 n will be double buffered together with SnBUF data 7 20 I C bus serial interface I C bus uses two wires SDA and SCL to transfer information between devices connected to the bus and it has the following features Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer e The I C bus may be used for test and diagnostic purposes A typical I C bus configuration is shown in Figure 9 The P89LPC952 954 device provides a byte oriented I2C bus interface that supports data transfers up to 400 kHz RPU RPU I2C bus P1 3 SDA P1 2 SCL OTHER DEVICE OTHER DEVICE 2 WITH I C BUS WITH I2C BUS ce MCU INTERFACE INTERFACE 002aab410 Fig9 l C bus configuration P89LPC952_954_4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 36 of 69 NXP Semiconductors P89LPC952 954 8 bit microcontroller with 10 bit ADC 8 aw INPUT FILTER P1 3 SDA OUTPUT STAGE gt BI
16. P1 5 RST pin can function as either a digital input P1 5 an active LOW reset input with an internal pull up a bidirectional reset input output open drain output with an internal pull up or as push pull reset output These modes are selected by the RPE Reset Pin Enable bit in UCFG1 and the RPE1 Reset Pin Enable 1 bit in UCFG2 Table8 Reset pin modes P1 5 RST mode RPE1 UCFG2 0 RPE UCFG1 6 General purpose input 0 0 Reset input with pull up 0 1 Bidirectional reset input output open drain with pull up 1 0 Reset output 1 1 Remark During a power up sequence the RPE and RPE1 selection is overridden and this pin always functions as a reset input An external circuit connected to this pin should not hold this pin LOW during a power on sequence as this will keep the device in reset After power up this pin will function as defined by the RPE and RPE1 bits Only a power up reset will temporarily override the selection defined by RPE and RPE1 bits Other sources of reset will not override the RPE and RPE1 bits Remark During a power cycle Vpp must fall below Vpor before power is reapplied in order to ensure a power on reset see Table 11 Static characteristics on page 51 Remark When using an oscillator frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp
17. P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 39 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC master slave MISO MISO 8 BIT SHIFT N 8 BIT SHIFT REGISTER MOSI MOSI REGISTER SPICLK SPICLK SPI CLOCK pas GENERATOR port SS 8 BIT SHIFT REGISTER SPICLK port 002aaa903 Fig 14 SPI single master multiple slaves configuration 7 22 Analog comparators Two analog comparators are provided on the P89L PC952 954 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logical one which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes The overall connections to both comparators are shown in Figure 15 The comparators function to Vpp 2 4 V When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 us The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate
18. Table 4 Special function registers continued Name IENO IEN1UI IEN2 IPolt IPOH IP10 IP1H IP2 IP2H KBCON KBMASK KBPATN Pol Pil Description SFR addr Bit address Interrupt A8H enable 0 Bit address Interrupt E8H enable 1 Interrupt D5H enable 2 Bit address Interrupt B8H priority O Interrupt B7H priority O high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Interrupt D6H priority 2 Interrupt D7H priority 2 high Keypad control 94H register Keypad 86H interrupt mask register Keypad pattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit functions and addresses Reset value MSB LSB Hex Binary AF AE AD AC AB AA A9 A8 EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 0000 0000 EF EE ED EC EB EA E9 E8 EST ESPI EC EKBI EI2C ool 00x0 0000 EST1 ES1 ESR1 EADC ool 00x0 0000 BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO ool x000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH PXOH ool x000 0000 PSRH FF FE FD FC FB FA F9 F8 PST PSPI PC PKBI PI2C ool 00x0 0000 PSTH PSPIH PCH PKBIH PI2CH 002 00x0 0000 PEST1 PES1 PADC ool 00x0 0000 PESR1 PEST1H PES1H PADCH ool 00x0 0000 PESR1H s S E E PATN KBIF ool xxxx xx0O SEL 00 0000 0000 FF 1111 1111 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B CMP2 8 KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RS
19. access This bit can then be set in software if CCLK is running at 8 MHz or slower The requirements in Section 7 3 5 High speed oscillator option for configuring P1 5 as an external reset input and using an external reset circuit when the clock frequency is greater than 12 MHz do not apply when using the internal RC oscillator s clock doubler option Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the P3 1 XTAL1 pin The rate may be from 0 Hz up to 18 MHz The P3 0 XTAL2 pin may be used as a standard port pin or a clock output When using an external clock input frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an external clock input frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode NXP
20. all modes except high Z lot 3 2 mA Vpp 2 4V to 3 6 V all ports all modes except high Z loH 20 pA Vpp 2 4 V to 3 6 V all ports quasi bidirectional mode lou 3 2 mA Vpp 2 4 V to 3 6 V all ports push pull mode lou 20 mA Vpp 2 4 V to 3 6 V Port 5 push pull mode on XTAL1 XTAL2 pins with respect to Vss except XTAL1 XTAL2 Vpp with respect to Vss 5 Min 1 5 0 22Vpp 0 5 0 7Vpp Vpp 0 3 Vpp 0 7 0 8Vpp Typi 11 14 55 0 5 0 4Vpp 0 6Vpp 0 2Vpp 0 6 0 2 Vpp 0 2 Vpp 0 4 Max 18 23 80 50 0 5 0 3Vpp 0 7Vpp 5 5 414 0 45 5 NXP B V 2008 All rights reserved Unit mA mA mA mA uA uA mV us 3 E 7 L lt lt lt l lt lt Product data sheet Rev 04 24 July 2008 51 of 69 NX P Semiconductors P89LPC952 954 Tabl 8 bit microcontroller with 10 bit ADC e11 Static characteristics continued Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Ciss input capacitance 6 15 pF liL LOW level input current Vi20 4V D 80 uA lu input leakage current Vi Vit Vins Or Vin ui 8 7 1 uA Ira HIGH LOW transition current all ports Vj 1 5 V at 9 30 450 uA Vpp 3 6 V Rnsr w n internal pull up resistance o
21. ep eg Hp 0 51 0 25 3 05 16 66 16 66 16 51 16 51 inches 0 02 0 0 12 0 656 0 656 0 650 0 650 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included OUTLINE VERSION IEC REFERENCES JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT187 2 112E10 MS 018 EDR 7319 Ego 99 42 27 01 11 14 Fig 25 Package outline SOT187 2 PLCC44 P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC LQFP44 plastic low profile quad flat package 44 leads body 10 x 10 x 1 4 mm SOT389 1 detail X DIMENSIONS mm are the original dimensions A max UNIT A1 A2 A3 bp c 1 6 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT389 1 136E08 MS 026 Ed Q 02 06 07 ISSUE DATE Fig 26 Package outline SOT
22. n nananaannna 25 7 8 CCLK modification DIVM register 25 7 9 Low power Select 25 7 10 Memory organization 26 7 11 Data RAM arrangement 26 7 12 Interr pts eomm ewRRRERS 26 7 12 1 External interrupt inputs 27 7 13 VO polle osea v ee URP Ves 29 7 13 1 Port configurations a se s auauua aaan 29 7 13 1 1 Quasi bidirectional output configuration 29 7 13 1 2 Open drain output configuration 29 7 13 1 3 Input only configuration 30 7 13 1 4 Push pull output configuration 30 7 13 2 Port 0 analog functions 30 7 13 3 Additional port features 30 7 14 Power monitoring functions 30 7 14 1 Brownout detection auauua saaana 30 7 14 2 Power on detection a n usasa naana 31 7 15 Power reduction modes 31 7 15 1 ldle mode sca RE EE E ETE 31 7 15 2 Power down mode 31 7 15 3 Total Power down mode 31 7 16 ROSEE rne a EE REESE 32 P89LPC952 954 4 7 16 1 7 17 7 17 1 7 17 2 7 17 8 7 17 4 7 17 5 7 17 6 7 18 7 19 7 19 1 7 19 2 7 19 3 7 19 4 7 19 5 7 19 6 7 19 7 7 19 8 7 19 9 7 19 10 7 20 7 21 7 21 1 7 22 7 22 1 7 22 2 7 22 3 7 23 7 24 7 25 7 25 1 7 25 2 7 25 3 7 26 7 26 1 7 26 2 7 26 3 7 26 4 7 26 5 7 26 6 7 26 7 7 26 8 7 26 9 7 26 10 7 27 7 28 8 bit microcontroller with 10 bit ADC Rese
23. open drain when used as output UGO SCL l C bus serial clock input output P1 3 INTO SDA 1 7 1 lO P1 3 Port 1 bit 3 open drain when used as output l INTO External interrupt O input UO SDA l C bus serial data input output P1 4 INT1 48 6 44 UO P1 4 Port 1 bit 4 P89LPC952 954 4 INT1 External interrupt 1 input NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 10 of 69 NXP Semiconductors P89LPC952 954 Table3 Pin description continued 8 bit microcontroller with 10 bit ADC Symbol P1 5 RST P1 6 P1 7 AD04 P2 0 to P2 5 P2 0 AD07 P2 1 AD06 P2 2 MOSI P2 3 MISO P2 4 SS P89LPC952_954_4 Pin LQFP48 PLCC44 LQFP44 47 5 43 46 4 42 43 2 40 42 1 39 41 44 38 30 34 28 29 33 27 28 32 26 Type Description UO UO UO UO UO UO UO UO UO UO UO P1 5 Port 1 bit 5 input only RST External Reset input during power on or maybe a reset input output if selected via UCFG1 and UCFG2 When functioning as a reset input or input output a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 When functioning as a reset output or input output an internal reset source will drive this pin LOW Also used during a power on sequence to force ISP mode When using an oscillator frequency above 12
24. pin except P1 5 RST see Figure 19 see Figure 19 see Figure 19 see Figure 19 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 18 Variable clock fosc 12 MHz Unit Min Max Min Max 7 189 7 557 7 189 7 557 MHz 14 378 15 114 14 378 15 114 MHz 320 520 320 520 kHz 0 12 MHz 83 ns 0 8 MHz 50 50 ns 15 15 ns 125 125 ns 50 50 ns 33 Tey clk teLcx 33 ns 33 Tey cik tCHCX 33 NnS 8 ns 8 ns 1 6Tey clk 2i 1333 ns 1 3Tey clk gt 1083 nS Tey cik 20 103 ns 0 0 ns 150 150 ns 0 cecus 0 2 0 MHz CCLKy 3 0 MHz NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 53 of 69 NXP Semiconductors P89LPC952 954 Table 12 Dynamic characteristics 12 MHz continued Vpp 2 4 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified J 8 bit microcontroller with 10 bit ADC Symbol Tspicyc tsPILEAD tsPILAG tsPICLKH tsPICLKL tspipsu tsPIDH tspia tspipis tspipv tsPIOH Lapin ispiF Parameter SPI cycle time slave master SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave SPICLK LOW time master slave SPI data set up time master or slave SPI data hold time master or slave SPI access time slave SPI disable time slave SPI enable to
25. pin has a Schmitt triggered input that also has a glitch suppression circuit Input only configuration The input only port configuration has no output drivers It is a Schmitt triggered input that also has a glitch suppression circuit Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Port 0 analog functions The P89LPC952 954 incorporates two Analog Comparators In order to give the best analog function performance and to minimize power consumption pins that are being used for analog functions must have the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port output into the Input Only high impedance mode Digital inputs on Port 0 may be disabled through the use of the PTOAD register bits 1 5 On any reset PTOAD 1 5 defaults to 0 s to enable digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software Pin P1 5 is input only Pins P1 2 and P
26. range entry point P89LPC952 1FH 1FOOH 1E00H to 1FFFH 1C00H to 1FFFH P89LPC954 3FH 3F00H 3E00H to 3FFFH 3C00H to 3FFFH Hardware activation of the bootloader The bootloader can also be executed by forcing the device into ISP mode during a power on sequence see the P89LPC952 954 User s Manual for specific information This has the same effect as having a non zero status byte This allows an application to be built that will normally execute user code but can be manually forced into ISP operation If the factory default setting for the boot vector 1FH 3FH is changed it will no longer point to the factory pre programmed ISP bootloader code After programming the flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H User configuration bytes Some user configurable features of the P89LPC952 954 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of the flash byte UCFG1 Please see the P89LPC952 954 User s Manual for additional details User sector security bytes There are eight sixteen User Sector Security Bytes on the P89LPC952 954 Each byte corresponds to one sector Please see the P89LPC952 954 User s Manual for additional details NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 46 of 69 NXP Semiconductors P89 LPC95
27. setting or clearing a bit in the interrupt enable registers IENO IEN1 or IEN2 The IENO register also contains a global disable bit EA which disables all interrupts NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 26 of 69 NXP Semiconductors P89 LPC952 954 7 12 1 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 IP1H IP2 and IP2H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are pending at the start of an instruction the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used to resolve pending requests of the same priority level External interrupt inputs The P89LPC952 954 has two external interrupt inputs as well as the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These exte
28. the ADC if enabled will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A D interrupt is enabled In Power down mode or Total Power down mode the ADC does not function If the ADC is enabled it will consume power Power can be reduced by disabling the ADC NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 49 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 9 Limiting values Table 10 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Tamb bias bias ambient temperature 55 125 C Tstg storage temperature 65 150 C loH O HIGH level output current per 20 mA input output pin loL vo LOW level output current per 20 mA input output pin lyote ma maximum total input output current 100 mA Vn voltage on any other pin except Vss with respect to 3 5 V VDD Ptot pack total power dissipation per package based on package heat 1 5 W transfer not device power consumption 1 The following applies to Table 10 a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over ambien
29. 0 19 8 v S6 6S60d 168d SIOJONPUODIWIS dXN Y v36 2660d 168d Jays Lep 19npoud 8002 Aine pZ t0 eH peAJese SIUDU IY 8002 8 dXN 69 JO 9L Table 4 Special function registers continued Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary DPH Data pointer 83H 00 0000 0000 high DPL Data pointer 82H 00 0000 0000 low FMADRH Program flash E7H 00 0000 0000 address high FMADRL Program flash E6H 00 0000 0000 address low FMCON Program flash EAH BUSY HVA HVE SV OI 70 0111 0000 control Read Program flash E4H FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD O control Write FMDATA Program flash EBH 00 0000 0000 data I2ADR I C bus slave DBH I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 address register Bit address DF DE DD DC DB DA D9 D8 I2CONU I C bus control D8H I2EN STA STO SI AA CRSEL 00 x000 00x0 register I2DAT I C bus data DAH register I2SCLH Serial clock DDH 00 0000 0000 generator SCL duty cycle register high I2SCLL Serial clock DCH 00 0000 0000 generator SCL duty cycle register low I2STAT l C bus status D9H STA 4 STA 3 STA 2 STA 1 STA 0 0 0 0 F8 1111 1000 register SJ10 19npuoolulesS dXN OAV 10 0 Ulm 1911071009079100 1q 8 v S6 6660d 168d 9002 Aine pZ v0 eH jeeus ejep 19npoJd 69 JO LL v v36 Z969d168d peniesei siuDu IY 8002 8 dXN
30. 009019100 Hq 8 v S6 6560d 168d NXP Semiconductors P89 LPC952 954 7 2 7 3 7 3 1 7 3 2 7 3 3 7 3 4 7 3 5 P89LPC952_954_4 8 bit microcontroller with 10 bit ADC Enhanced CPU The P89LPC952 954 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clocks Clock definitions The P89LPC952 954 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources see Figure 6 and can also be optionally divided to a slower frequency see Section 7 8 CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output The clock doubler option when enabled provides an output frequency of 14 746 MHz PCLK Clock for the various peripheral devices and is CCLK CPU clock OSCCLK The P89LPC952 954 provides several user selectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and includ
31. 1 when read P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 14 of 69 9002 Aine pZ t0 eH 1eeus ejep 19npoJd 69 Jo SL v v36 2560d 168d peAJesei SIUDU IY 8002 8 dXN Table 4 Special function registers Name Description SFR Bit functions and addresses Reset value addr usap LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACCH Accumulator EOH 00 0000 0000 ADOCON ADCO control 97H ENBIO ENADCIO TMMO EDGEO ADCIO ENADCO ADCSO1 ADCSOO 00 0000 0000 register ADOINS ADCO input A3H ADI07 ADI06 ADI05 ADI04 ADI03 ADIO2 ADIO1 ADIOO 00 0000 0000 select ADOMODA ADCO mode COH BNDIO BURSTO SCCO SCANO S 00 0000 0000 register A ADOMODB ADCO mode A1H CLK2 CLK1 CLKO 00 000x 0000 register B AUXR1 Auxiliary A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 function register Bit address F7 F6 F5 F4 F3 F2 F1 FO BID B register FOH 00 0000 0000 BRGRO 0 Baudrate BEH 00 0000 0000 generator 0 rate low BRGR1 0 Baudrate BFH 00 0000 0000 generator 0 rate high BRGCON 0 Baud rate BDH SBRGS 0 BRGEN 0 0021 XxXxX xx00 generator 0 control CMP1 Comparator 1 ACH CE1 CP1 CN1 OE1 CO1 CMF1 ool xx00 0000 control register CMP2 Comparator2 ADH CE2 CP2 CN2 OE2 CO2 CMF2 0082 xx00 0000 control register DIVM CPU clock 95H 00 0000 0000 divide by M control DPTR Data pointer 2 bytes OAV 10 0 Ulm 191107100901910
32. 1 3 are configurable for either input only or open drain Every output on the P89LPC952 954 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to Table 11 for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Power monitoring functions The P89LPC952 954 incorporates power monitoring functions designed to prevent incorrect operation during initial power up and power loss or reduction during operation This is accomplished with two hardware functions Power on detect and brownout detect Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level The default operation is for a brownout detection to cause a processor reset however it may alternatively be configured to generate an interrupt NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 30 of 69 NXP Semiconductors P89 LPC952 954 7 14 2 7 15 7 15 1 7 15 2 7 15 3 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Brownout detection may be enabled or disabled in software If brownout detection is enabled the brownout condition occurs when Vpp falls below the brownout trip vo
33. 1 overflow rate or the Baud Rate Generator described in Section 7 19 5 Baud rate generator and selection Baud rate generator and selection Each enhanced UART has an independent Baud Rate Generator The baud rate is determined by a baud rate preprogrammed into the BRGR1_n and BRGRO n SFRs which together form a 16 bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate If the baud rate generator is used Timer 1 can be used for other timing functions The UARTS can use either Timer 1 or their respective baud rate generator output see Figure 8 Note that Timer T1 is further divided by 2 if the SMOD bit PCON 7 is cleared The independent Baud Rate Generators use OSCCLK timer 1 overflow PCLK based SMOD sc n ad o baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 8 Baud rate sources for UART Modes 1 3 Framing error Framing error is reported in the status register SnSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SnCON 7 respectively If SMODO is 0 SnCON 7 is SMO n It is recommended that SMO n and SM1 n SnCON 7 6 are set up when SMODO is 0 Break detect Break detect is reported in the status register SnSTAT A break is detected when 11 consecutive bits are sensed LOW The break detect can be used to reset the device and force the device into ISP mod
34. 2 954 8 ADC P89LPC952 954 4 8 1 8 2 8 3 8 bit microcontroller with 10 bit ADC General description The P89LPC952 954 has a 10 bit 8 channel multiplexed successive approximation ADC module A block diagram of the ADC is shown in Figure 17 The ADC consists of an 8 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in combination with the SAR drives a DAC which provides the other input to the comparator The output of the comparator is fed to the SAR Features E 10 bit 8 channel multiplexed input successive approximation ADC E Eight result register pairs E Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode Bi Three conversion start modes Timer triggered start Start immediately Edge triggered 10 bit conversion time of 4 us at an A D clock of 9 MHz Interrupt or polled operation High and low boundary limits interrupt selectable in or out of range Clock divider Power down mode Block diagram CONTROL LOGIC CCLK 002aab103 Fig 17 ADC block diagram NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 47 of 69 NXP Semiconductors
35. 389 1 LQFP44 P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 63 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 detail X DIMENSIONS mm are the original dimensions UNIT Ar A2 Ag bp e 0 05 1 35 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT313 2 136E05 MS 026 E 03 02 25 ISSUE DATE Fig 27 Package outline SOT313 2 LQFP48 P89LPC952_954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 64 of 69 NXP Semiconductors P89LPC952 954 14 Abbreviations P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Table 17 Abbreviations Acronym ADC BOE CPU CCU CRC DAC EPROM EMI IAP LSB MSB PWM RAM RC RTC SAR SFR SPI UART Description Analog to Digital Converter BrownOut Enable Central Processing Unit Capture Compare Unit Cyclic Redundancy Check D
36. 40 C to 85 C for industrial applications unless otherwise specified JI 8 bit microcontroller with 10 bit ADC Symbol Parameter fosc Rc internal RC oscillator frequency fosewp internal watchdog oscillator frequency fosc oscillator frequency Tey clk Clock cycle time CLKLP low power select clock frequency Glitch filter tgr glitch rejection time tsa signal acceptance time External clock tcHcx clock HIGH time tcLox clock LOW time tcLcH clock rise time tcucL clock fall time Shift register UART mode 0 TxxL serial port clock cycle time tovxH output data set up to clock rising edge time txHax output data hold after clock rising edge time txHDx input data hold after clock rising edge time txHpv input data valid to clock rising edge time SPI interface lap SPI operating frequency slave master Tspicyc SPI cycle time slave master P89LPC952 954 4 Conditions nominal f 7 3728 MHz trimmed to 1 96 at Tamb 25 C clock doubler option OFF default nominal f 14 7456 MHz clock doubler option ON see Figure 19 P1 5 RST pin any pin except P1 5 RST P1 5 RST pin any pin except P1 5 RST see Figure 19 see Figure 19 see Figure 19 see Figure 19 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 18 see Figure 20 21 22 23 Variable clock fosc 18 MHz Unit Min Max Min Max 7 189 7 557 7 189 7 557 MHz 14 378 15 114 14 378 15 114 MH
37. 9 of 69 NXP Semiconductors P89LPC952 954 8 bit microcontroller with 10 bit ADC Table3 Pin description continued Symbol Pin Type Description LQFP48 PLCC44 LQFP44 P0 6 CMP1 34 37 31 l O PO 6 Port 0 bit 6 KBI6 O CMP1 Comparator 1 output l KBI6 Keyboard input 6 PO 7 TA KBI7 31 35 29 O P0 7 Port 0 bit 7 lO T1 Timer counter 1 external count input or overflow output l KBI7 Keyboard input 7 P1 0 to P1 7 O Port 1 Port 1 is an 8 bit I O port with a user configurable D output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 7 13 1 Port configurations and Table 11 Static characteristics for details P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below P1 0 TXDO 4 10 4 l O P1 0 Port 1 bit 0 O TXDO Transmitter output for serial port 0 P1 1 RXDO 3 9 3 UO P1 1 Port 1 bit 1 l RXDO Receiver input for serial port 0 P1 2 TO SCL 2 8 2 lO P1 2 Port 1 bit 2 open drain when used as output lO TO Timer counter 0 external count input or overflow output
38. CO data register 7 left FFF1H ADODAT7 9 2 MSB BNDSTAO ADCO boundary status FFEDH register BRGCON 1 Baud rate generator 1 FFB3H SBRGS 1 BRGEN 1 002 xxxx xx00 control BRGO 1 Baud rate generator 1 rate FFB4H low BRG1 1 Baud rate generator 1 rate FFB5H high FREEZE Peripheral clock freeze FFDOH RTC_F CCUF WDT E TF TO F 00 xxx0 0000 P4M1 Port 4 output mode 1 FFB8H P4M1 7 P4M1 6 P4M1 5 P4M1 4 PAM1 3 P4M1 2 P4M1 1 P4M1 0 FFH 1111 1111 P4M2 Port 4 output mode 2 FFB9H P4M2 7 P4M2 6 P4M2 5 P4M2 4 P4M2 3 P4M2 2 P4M2 1 P4M2 0 00 0000 0000 P5M1 Port 5 output mode 1 FFBAH P5M1 7 P5M1 6 P5M1 5 P5M1 4 P5M1 3 P5M1 2 P5M1 1 P5M1 0 FFE 1111 1111 P5M2 Port 5 output mode 3 FFBBH P5M2 7 P5M2 6 P5M2 5 P5M2 4 P5M2 3 P5M2 2 P5M2 1 P5M2 0 OO 0000 0000 S1ADDR Serial port 1 address FFB2H 00 0000 0000 register S1ADEN Serial port 1 address FFB1H 00 0000 0000 enable S1BUF Serial port 1 data buffer FFBOH Xx XXXX XXXX register SJ10 9npuoolulesS dXN peAJesei SIUDU IY 8002 8 dXN 69 JO ZC 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX QDPTR A instructions are used to access these extended SFRs 2 BRGR1 1 and BRGRO 1 must only be written if BRGEN 1 in BRGCON 1 SFR is logic 0 If any are written while BRGEN 1 1 the result is unpredictable OAV 10 0 Ulm 1911071
39. CS1 RTCSO ERTC RTCEN 60 2171 011x xx00 ool 0000 0000 oorl 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO O FE SM1_00 SM2 0 REN 0 TB8 0 RB8 0 TI 0 RI 0 00 0000 0000 _0 DBMOD 0 INTLO O CIDIS O DBISEL 0 FE 0 BR 0 OE 0 STINT O 00 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 SPIF WCOL 00 OOxx xxxx 00 0000 0000 SMO 1 FE SM1_1 SM2 1 REN 1 TB8 1 RB8 1 TI 1 RI 1 00 0000 0000 1 DBMOD 1 NTLO 1 CIDIS 1 DBISEL 1 FE 1 BR 1 OE 1 STINT 1 00 0000 0000 T1M2 TOM2 00 XXxx0 xxxO JAY 10 01 YM 19 03u020J91U 110 8 vS6 cS60d 168d SIOJONPUODIWIS dXN 8002 Aine pZ t0 eH 1eeus ejep 19npoJd 69 Jo 02 Y v36 Z969d168d peAJesei SIUDU IY 8002 8 dXN Table 4 Special function registers continued Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 8F 8E 8D BC 8B 8A 89 88 TCONE Timer 0 and 1 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 control THO Timer 0 high 8CH 00 0000 0000 TH1 Timer 1 high 8DH 00 0000 0000 TLO Timer 0 low 8AH 00 0000 0000 TL1 Timer 1 low 8BH 00 0000 0000 TMOD Timer 0 and1 89H T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 mode TRIM Internal 96H RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O 61 7 oscillator trim register WDCON Watchdog A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK ESI 7 control register WDL Watchdog load
40. M2 1 P3M2 0 002 XXXx Xx00 mode 2 PCON Power control 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 0000 0000 register PCONA Power control BSH RTCPD VCPD ADPD l2PD SPPD SPD O02 0000 0000 register A Bit address D7 D6 D5 D4 D3 D2 D1 DO PSWII Program DOH CY AC FO RS1 RSO OV F1 P 00 0000 0000 status word PTOAD Port 0 digital F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00 000x input disable RSTSRC Reset source DFH BOF POF R_BK R_WD R_SF REX i register JAY 10 01 YM 49 043u020J91U 110 8 vS6 cS60d 168d SIOJONPUODIWIBS dXN 9002 Aine pZ t0 eH 1eeus ejep 19npoJd 69 JO 6L Y S6 Z969d168d peAJese SIUDU IY 8002 8 dXN Table 4 Special function registers continued Name RTCCON RTCH RTCL SOADDR SOADEN SOBUF SOCONH SOSTAT SP SPCTL SPSTAT SPDAT S1CON S1STAT TAMOD SFR addr Description RTC control D1H RTC register D2H high RTC register D3H low Serial port A9H address register Serial port B9H address enable Serial Port 99H data buffer register Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H SPI control E2H register SPI status E1H register SPI data E3H register Serial port 1 B6H control Serial port 1 D4H extended status register Timer 0 and 1 8FH auxiliary mode Bit functions and addresses Reset value MSB LSB Hex Binary RTCF RT
41. MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage P1 6 Port 1 bit 6 P1 7 Port 1 bit 7 AD04 ADCO channel 4 analog input Port 2 Port 2 is an 8 bit I O port with a user configurable output type During reset Port 2 latches are configured in the input only mode with the internal pull up disabled The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 11 Static characteristics for details All pins have Schmitt triggered inputs Port 2 also provides various special functions as described below P2 0 Port 2 bit O ADO07 ADCO channel 7 analog input P2 1 Port 2 bit 1 ADO06 ADCO channel 6 analog input P2 2 Port 2 bit 2 MOSI SPI master out slave in When configured as master this pin is output when configured as slave this pin is input P2 3 Port 2 bit 3 MISO When configured as master this pin is input when configured as sl
42. P89 LPC952 954 8 4 8 4 1 8 4 2 8 4 3 8 4 4 8 4 5 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC ADC operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel An interrupt if enabled will be generated after the conversion completes Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the eight result register pairs The user may select whether an interrupt can be generated after every four or every eight conversions Additional conversion results will again cycle through the result register pairs overwriting the previous results Continuous conversions continue until terminated by the user Auto scan single conversion mode Any combination of the eight input channels can be selected for conversion A single conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel The user may select whether an interrupt if enabled will be generated after either the first four conversions have occurred or all selected channels have been converted If the user selects to generate an interrupt after the four input channels have been co
43. T 1 us NR tRH RST TRL i 002aaa912 Fig 24 ISP entry waveform P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 59 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 12 Other characteristics 12 1 Comparator electrical characteristics Table 15 Comparator electrical characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Vio input offset voltage Vic common mode input voltage 0 CMRR common mode rejection ratio 0l tres tot total response time 250 lcE ov chip enable to output valid time lui input leakage current 0 V Vi Vpp Max 10 Vpp 0 3 500 10 10 Unit mV dB ns us uA 1 This parameter is characterized but not tested in production P89LPC952_954_4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 60 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 12 2 ADC electrical characteristics Table 16 ADC electrical characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified All limits valid for an external source impedance of less than 10 kQ Symbol Paramet
44. T COUNTER ARBITRATION CCLK 2 INPUT AND SYNC LOGIC TIMING a FILTER AND d CONTROL Z nu SERIAL CLOCK Rule 7 OUTPUT interrupt z STAGE GENERATOR timer 1 _f overflow P1 2 I2CON CONTROL REGISTERS AND I2SCLH SCL DUTY CYCLE REGISTERS I SCLL ush STATUS stalls BUS DECODER I2STAT STATUS REGISTER NY 002aaa899 Fig 10 I C bus serial interface block diagram P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 37 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 7 21 SPI The P89LPC952 954 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master or Slave mode It has a Transfer Completion Flag and Write Collision Flag Protection MISO P2 3 CPU clock 8 BIT SHIFT REGISTER MOSI READ DATA BUFFER Pee SPICLK P2 5 DIVIDER BY 4 16 64 128 SPI clock master SS P2 4 CLOCK LOGIC A A A gt SPI CONTROL REGISTER SPI internal interrupt y data request bus 002aaa900 Fig 11 SPI block diagram The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices
45. T INT1 INTO SDA TO SCL RXDO TXDO 2 DAV 1 q 0L Ulm 1911071009079100 1q 8 t96 c969d168d SJ10 19npuoolulesS dXN 9002 Aine pZ t0 eH 1eeus ejep 19npoJd 69 Jo 8L v v36 Z969d168d peAJese SIUDU IY 8002 8 dXN Table 4 Special function registers continued Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 97 96 95 94 93 92 91 90 Palt Port 2 AOH SPICLK ss MISO MOSI 2 Bit address B7 B6 B5 B4 B3 B2 B1 BO P3lt Port 3 BOH XTAL1 XTAL2 2 P4 Port 4 B3H TMS RXD1 TXD1 TRIG T3EX 8 P5 Port 5 B4H T3 2 POM1 Port 0 output 84H POM1 7 POM1 6 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FEIZ 1111 1111 mode 1 POM2 Port 0 output 85H POM2 7 POM2 6 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 0012 0000 0000 mode 2 P1M1 Port 1 output 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D32 11x1 xx11 mode 1 P1M2 Port 1 output 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 ool2 00x0 xx00 mode 2 P2M1 Port 2 output A4H P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 EEIZ 1111 1111 mode 1 P2M2 Port 2 output A5H P2M2 7 P2M2 6 P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 0029 0000 0000 mode 2 P3M1 Port 3 output B1H P3M1 1 P3M1 0 0312 XXXX xx11 mode 1 P3M2 Port 3 output B2H P3
46. ange Frequency P89LPC952FA 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC952FBD 8 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC954FA 16 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC954FBD44 16 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC954FBD48 16 kB 40 C to 85 C 0 MHz to 18 MHz P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 3 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 4 Block diagram P89LPC952 954 ACCELERATED 2 CLOCK 80C51 CPU ra 8 kB 16 kB C y ART TXDO dne iem internal eT KE C D um ma DATA RAM U E 256 BYTE SCL AUXILIARY RAM 7 L 12C BUS SDA ADOO ADO1 Pee AD02 P910 Ent CONFIGURABLE 0s f 3 C ADCO ADOS AD04 B ADOS gs P4 7 0 plein CONFIGURABLE I Os iai SPICLK P3 1 0 m C y SPI Mes SS PO 7 0 o cuna CNB COMPARATORS CINTA CMP1 CIN1B TE C INTERRUPT DEBUGGER WATCHDOG TIMER 9 INTERFACE bi AND OSCILLATOR N OSCILLATOR DIVIDER Sock CRYSTAL XTAL1 CONFIGURABLE ON CHIP RC POWER MONITOR OR cae ee OSCILLATOR WITH POWER ON RESET OSCILLATOR RESONATOR AL 5 CLOCK DOUBLER BROWNOUT RESET 002aab305 1 44 pin package 2 48 pin package Fig 1 Block diagram P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 4 of 69 NXP Semiconductors P89LPC952 954
47. ash as data storage 44 Flash programming and erasing 45 e THEE 45 IAP illis dud ew x qud ue GE 45 IS sete datas sitit ard s i sedet eee dd 45 Power on reset code execution 46 Hardware activation of the bootloader 46 User configuration bytes 46 User sector security bytes 46 continued gt gt NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 68 of 69 NXP Semiconductors P89LPC952 954 8 1 8 2 8 3 8 4 8 4 1 8 4 2 8 4 3 8 4 4 8 4 5 8 4 6 8 5 8 5 1 8 5 2 8 5 3 8 6 8 7 8 8 10 11 11 1 11 2 12 12 1 12 2 13 14 15 16 16 1 16 2 16 3 16 4 17 18 ADCO iere MEE EM E 47 General description lille 47 Features so a sade bei ERR 47 Block diagram 0 Na K RTT T 47 ADC operating modes 48 Fixed channel single conversion mode 48 Fixed channel continuous conversion mode 48 Auto scan single conversion mode 48 Auto scan continuous conversion mode 48 Dual channel continuous conversion mode 48 Single step mode n anann 49 Conversion start modes 49 Timer triggered start llis 49 Start immediately lilius 49 Edge triggered nnna unnan naen 49 Boundary limits interrupt 49 Clock divider 0 0 2 0 00 000 cece 49 Power down and Idle mode 49 Limi
48. ata sheet the full data sheet shall prevail 16 3 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 17 Contact information For more information please visit http www nxp com to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purpos
49. ator allowing it to perform an oscillator fail detect function Programmable port output configuration options quasi bidirectional open drain push pull input only Port input pattern match detect Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern Controlled slew rate port outputs to reduce EMI Outputs have approximately 10 ns minimum ramp times Four interrupt priority levels Eight keypad interrupt inputs plus two additional external interrupt inputs Schmitt trigger port inputs Second data pointer Extended temperature range Emulation support NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 2 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 3 Ordering information Table 1 Ordering information Type number Package Name Description Version P89LPC952FA PLCCA44 plastic leaded chip carrier 44 leads SOT187 2 P89LPC952FBD LQFP44 plastic low profile quad flat package 44 leads SOT389 1 body 10 x 10 x 1 4 mm P89LPC954FA PLCC44 plastic leaded chip carrier 44 leads SOT187 2 P89LPC954FBD44 LQFP44 plastic low profile quad flat package 44 leads SOT389 1 body 10 x 10 x 1 4 mm P89LPC954FBD48 LQFP48 plastic low profile quad flat package 48leads SOT313 2 body 7 x 7 x 1 4 mm 3 1 Ordering options Table 2 Ordering options Type number Flash memory Temperature r
50. ave this pin is output P2 4 Port 2 bit 4 SS SPI Slave select NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 11 of 69 NXP Semiconductors P89LPC952 954 Table 3 Pin description continued 8 bit microcontroller with 10 bit ADC Symbol P2 5 SPICLK P2 6 P2 7 P3 0 to P3 1 P3 0 XTAL2 CLKOUT P3 1 XTAL1 P4 0 to P4 7 P4 0 P4 1 TRIG P4 2 TXD1 P4 3 RXD1 P89LPC952_954_4 Pin LOFP48 PLCC44 LQFP44 27 31 25 26 25 30 24 24 29 23 23 28 22 22 27 21 Type Description UO UO UO UO UO UO UO UO UO UO UO UO P2 5 Port 2 bit 5 SPICLK SPI clock When configured as master this pin is output when configured as slave this pin is input P2 6 Port 2 bit 6 P2 7 Port 2 bit 7 Port 3 Port 3 is a 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 11 Static characteristics for details All pins have Schmitt triggered inputs Port 3 also provides various special functions as described below P3 0 Port 3 bit O XTAL2 Output from the oscillator amplifier when a crystal
51. caler is either the PCLK or the nominal 400 kHz watchdog oscillator The watchdog timer can only be reset by a power on reset When the watchdog feature is disabled it can be used as an interval timer and may generate an interrupt Figure 16 shows the watchdog timer in Watchdog mode Feeding the watchdog requires a two byte sequence If PCLK is selected as the watchdog clock and the CPU is powered down the watchdog is disabled The watchdog timer has a time out period that ranges from a few us to a few seconds Please refer to the P89LPC952 954 User s Manual for more details NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 42 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 1 Fig 16 Watchdog timer in Watchdog mode WDTE 1 watchdog oscillator oc 32 H ALER Lo 8 BIT DOWN 1 PCLK i e PRESS d COUNTER reset MOV WFEED 1 0A5H N MOV WFEED2 05AH A A wocon army race pret ereo T T Ton worer woe Watchdog reset can also be caused by an invalid feed sequence or by writing to WDCON not immediately followed by a feed Sequence 002aaa905 7 25 7 25 1 7 25 2 7 25 3 P89LPC952 954 4 Additional features Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred
52. called through a common interface PGM_MTP Several IAP calls are available for use by an application program to permit selective erasing and programming of flash sectors pages security bits configuration bytes and device ID These functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at FFO3H The Boot ROM occupies the program memory space at the top of the address space from FFOOH to FEFFH thereby not conflicting with the user program memory space In addition IAP operations can be accomplished through the use of four SFRs consisting of a control status register a data register and two address registers Additional details may be found in the P89LPC952 954 User s Manual ISP ISP is performed without removing the microcontroller from the system The ISP facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC952 954 through the serial port This firmware is provided by Philips and embedded within each P89LPC952 954 device The Philips ISP facility has made in system programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vpp Vss TXD RXD and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature NXP B V 2008 All rights reserved
53. comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down and Idle modes as well as in the normal operating mode This fact should be taken into account when system power consumption is an issue To minimize power consumption the user can disable the comparators via PCONA 5 or put the device in Total Power down mode NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 41 of 69 NXP Semiconductors P89 LPC952 954 7 23 7 24 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks The Keypad Interrupt Mask Register KBMASK is used to define which input pins connect
54. data register 0 right FFFEH ADODATO 7 0 00 0000 0000 LSB ADODATOL ADCO data register O left FFFFH ADODATO 9 2 00 0000 0000 MSB ADODAT1R ADCO data register 1 right FFFCH ADODAT1 7 0 00 0000 0000 LSB ADODAT1L ADCO data register 1 left FFFDH ADODAT1 9 2 00 0000 0000 MSB ADODAT2R ADCO data register 2 right FFFAH ADODAT2 7 0 00 0000 0000 LSB ADODAT2L ADCO data register 2 left FFFBH ADODAT2 9 2 00 0000 0000 MSB ADODAT3R ADCO data register 3 right FFF8H ADODATS 7 0 00 0000 0000 LSB ADODAT3L ADCO data register 3 left FFF9H ADODAT3 9 2 00 0000 0000 MSB ADODAT4R ADCO data register 4 right FFF6H ADODAT4 7 0 00 0000 0000 LSB ADODAT4L ADCO data register 4 left FFF7H ADODATA 9 2 00 0000 0000 MSB ADODATSR ADCO data register 5 right FFFAH ADODATS5 7 0 00 0000 0000 LSB ADODAT5L ADCO data register 5 left FFF5H ADODAT5 9 2 00 0000 0000 MSB ADODAT6R ADCO data register 6 right FFF2H ADODATE6 7 0 00 0000 0000 LSB ADODAT6L ADCO data register 6 left FFF3H ADODATE 9 2 00 0000 0000 MSB ADODAT7R ADCO data register 7 right FFFOH ADODAT7 7 0 LSB OAV 10 0 Utm 1911071009079100 Hq 8 7S6 cS60d 168d SIOJONPUODIWIS dXN 1394S ejep 19npoud 8002 Aine pz t0 eH Y S6 Z969d168d Table 5 Extended special function registers continued Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary ADODAT7L AD
55. e Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SnBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters as long as the next character is written between the start bit and the stop bit of the previous character NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 35 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC Double buffering can be disabled If disabled DBMOD n i e SnSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD n 0 7 19 9 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART in double buffering mode the TI n interrupt is generated when the double buffer is ready to receive new data 7 19 10 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled TB8 n can be written before or after SnBUF is written as long as TB8 n is updated some time before that bit is shifted out TB8_n must not be changed until the bit is shifted out as indicated by the TI n interrupt
56. e allowing for the device to be programmed in circuit through the serial port The flash may also be programmed or erased using a commercially available EPROM programmer which supports this device This device does not provide for direct verification of code memory contents Instead this device provides a 32 bit CRC result on either a sector or the entire user code space ICP ICP is performed without removing the microcontroller from the system The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC952 954 through a two wire serial interface The Philips ICP facility has made in circuit programming in an embedded application using commercially available programmers possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Only a small connector needs to be available to interface your application to a commercial programmer in order to use this feature Additional details may be found in the P89LPC952 954 User s Manual IAP IAP is performed in the application under the control of the microcontroller s firmware The IAP facility consists of internal hardware resources to facilitate programming and erasing The Philips IAP has made in application programming in an embedded application possible without additional components Two methods are available to accomplish IAP A set of predefined IAP functions are provided in a Boot ROM and can be
57. e an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration When using a clock frequency above 12 MHz the reset input function of P1 5 must be enabled An external circuit is required to hold the device in reset at power up until Vpp has reached its specified level When system power is removed Vpp will fall below the minimum specified operating voltage When using a clock frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 23 of 69 NXP Semiconductors P89 LPC952 954 7 P89LPC952 954 4 3 6 7 4 7 5 7 6 8 bit microcontroller with 10 bit ADC in reset when Vpp falls below the minimum spec
58. ed to Port 0 can trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if enabled The PATN SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 1 not equal then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than six CCLKs Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count It consists of a programmable 12 bit prescaler and an 8 bit down counter The down counter is decremented by a tap taken from the prescaler The clock source for the pres
59. ent contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 16 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short d
60. er Conditions Min Typ Max Unit Vppaiapc ADC analog supply voltage Vpp 0 4 Vpp 0 4 V Vssa analog ground voltage Vss 0 4 Vss 0 4 V VvREFP voltage on pin VREFP Vpp 0 4 Vpp 0 4 V VyREFN voltage on pin VREFN Vss 0 4 Vss 0 4 V ViA analog input voltage Ves 0 4 Vpop 04 V Cia analog input capacitance 15 pF Ep differential linearity error lt S ti LSB EL adi integral non linearity 2 LSB Eo offset error S 2 LSB Ec gain error S x 2 LSB Eu tot total unadjusted error 4 3 LSB Mctc channel to channel matching H LSB Deport crosstalk between port inputs 0 kHz to 100 kHz 60 dB SRin input slew rate 100 V ms Tey ADO ADC clock cycle time 111 3125 ns tADC ADC conversion time ADC enabled S36Tcyapc HS P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 61 of 69 NXP Semiconductors P89LPC952 954 13 Package outline PLCC44 plastic leaded chip carrier 44 leads ia Z T pin 1 index 8 bit microcontroller with 10 bit ADC SOT187 2 scale DIMENSIONS mm dimensions are derived from the original inch dimensions Lp detail X t j Aa a UNIT A Ay Aa A3 max Pp b4 pd E0 e
61. es only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to warranty intellectual property rights infringement and limitation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights 16 4 Trademarks Notice All referenced brands product names service names and trade
62. etention supply voltage Vppn This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to Vppr therefore it is highly recommended to wake up the processor via reset in this case Vpp must be raised to within the operating range before the Power down mode is exited Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include Brownout detect watchdog timer comparators note that comparators can be powered down separately and RTC system timer The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled Total Power down mode This is the same as Power down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled If the internal RC oscillator is used to clock the RTC during power down there will be high power consumption Please use an external low frequency clock to achieve low power with the RTC running during power down NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 31 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 7 16 Reset The
63. ified operating voltage These requirements for clock frequencies above 12 MHz do not apply when using the internal RC oscillator in clock doubler mode Clock output The P89LPC952 954 supports a user selectable clock output function on the XTAL2 CLKOUT pin when crystal oscillator is not being used This condition occurs if another clock source has been selected on chip RC oscillator watchdog oscillator external clock input on XTAL1 and if the RTC is not using the crystal oscillator as its clock source This allows external devices to synchronize to the P89LPC952 954 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power On chip RC oscillator option The P89LPC952 954 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 96 at room temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies When the clock doubler option is enabled UCFG1 3 1 the output frequency is 14 746 MHz If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance
64. igital to Analog Converter Erasable Programmable Read Only Memory ElectroMagnetic Interference In Application Programming Least Significant Bit Most Significant Bit Pulse Width Modulator Random Access Memory Resistance Capacitance Real Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver Transmitter NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 65 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 15 Revision history Table 18 Revision history Document ID Release date Data sheet status Change notice Supersedes P89LPC952 954 4 20080724 Product data sheet P89LPC952 954 3 Modifications Figure 2 Functional diagram Updated port 2 information P89LPC952 954 3 20080605 Product data sheet P89LPC952 954 2 P89LPC952 954 2 20071219 Preliminary data sheet P89LPC952 1 P89LPC952 1 20050916 Preliminary data sheet P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet 66 of 69 Rev 04 24 July 2008 NXP Semiconductors P89LPC952 954 16 Legal information 16 1 Data sheet status 8 bit microcontroller with 10 bit ADC Document status JI2 Product statusi Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This docum
65. interrupt service P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 40 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC CP1 P0 4 CIN1A comparator 1 ero P0 3 CINTB CO1 p SETS P0 5 CMPREF Vref bg E S change detect CN1 jr interrupt T change detect EC Dc P0 2 CIN2A comparator 2 P0 1 CIN2B or CMP2 P0 0 CO2 i 74 OE2 CN2 002222904 Fig 15 Comparator input and output connections 7 22 1 7 22 2 7 22 3 P89LPC952 954 4 Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used The value of the internal reference voltage referred to as Vret pg iS 1 23 V 10 Comparator interrupt Each comparator has an interrupt flag contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector If both comparators enable interrupts after entering the interrupt service routine the user needs to read the flags to determine which comparator caused the interrupt Comparators and power reduction modes Either or both comparators may remain enabled when Power down or Idle mode is activated but both
66. ister pair ADODAT1R and ADODAT1L The first channel is again converted and its result stored in ADODAT2R and ADODAT2L The second channel is again converted and its result placed in ADODAT3R and ADODAT3L etc An interrupt is generated if enabled after every set of four or eight conversions user selectable NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 48 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 8 4 6 Single step mode 8 5 8 5 1 8 8 P89LPC952 954 4 ue 5 3 8 6 8 7 8 8 This special mode allows single stepping in an auto scan conversion mode Any combination of the eight input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the ADC waits for the next start condition May be used with any of the start modes Conversion start modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all ADC operating modes Start immediately Programming this mode immediately starts a conversion This start mode is available in all ADC operating modes Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge trigge
67. le mode by executing its normal program at a lower rate This can also allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC952 954 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to 1 to lower the power consumption further On any reset CLKLP is 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 25 of 69 NXP Semiconductors P89 LPC952 954 7 10 7 11 7 12 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Memory organization The various P89LPC952 954 memory spaces are as follows DATA 128 bytes of internal data memory space 00H 7FH accessed via direct or indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area DATA Indirect Data 256 bytes of internal data memory space 00H FFH accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it e SFR Special Function Registers Selected CPU registers and peripheral co
68. ltage Vbo see Table 11 Static characteristics and is negated when Vpp rises above Vpo If the P89LPC952 954 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating For correct activation of brownout detect the Vpp rise and fall times must be observed Please see Table 11 Static characteristics for specifications Power on detection The Power on detect has a function similar to the brownout detect but is designed to work as power comes up initially before the power supply voltage reaches a level where brownout detect can work The POF flag in the RSTSRC register is set to indicate an initial power up condition The POF flag will remain set until cleared by software Power reduction modes The P89LPC952 954 supports three different power reduction modes These modes are Idle mode Power down mode and total Power down mode Idle mode Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC952 954 exits Power down mode via any reset or certain interrupts In Power down mode the power supply voltage may be reduced to the data r
69. marks are the property of their respective owners I C bus logo is a trademark of NXP B V For sales office addresses please send an email to salesaddresses nxp com P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 67 of 69 NXP Semiconductors P89LPC952 954 18 Contents 1 General description Lee 1 2 Features 2 0c cece eee eee eens 1 2 1 Principal features llle 1 2 2 Additional features l l 2 3 Ordering information sse 3 3 1 Ordering options eae 3 4 Block diagram eeseee 4 5 Functional diagram e x e 5 6 Pinning information lesse 6 6 1 PINNING rererere epe RE pues 6 6 2 Pin description ee eccer RTE T RER X cee eee ee 9 7 Functional description 14 7 1 Special function registers 14 7 2 Enhanced CPU eee aee 23 7 3 GlOCKS ii es R K etter a blar sane R N 23 7 3 1 Clock definitions a na a aaea 23 7 3 2 CPU clock OSCCLK 04 23 7 3 3 Low speed oscillator option 23 7 3 4 Medium speed oscillator option 23 7 3 5 High speed oscillator option 23 7 3 6 Clock output 2 0 0 2 eee eee 24 7 4 On chip RC oscillator option 24 7 5 Watchdog oscillator option 24 7 6 External clock input option 24 7 7 CCLK wake up delay n
70. mmercial EPROM programmers Flash security bits prevent reading of sensitive application programs Serial flash In System Programming ISP allows coding while the device is mounted in the end application In Application Programming IAP of the flash code memory This allows changing the code in a running application Low voltage brownout detect allows a graceful system shutdown when power fails May optionally be configured as an interrupt Idle and two different power down reduced power modes Improved wake up from Power down mode a LOW interrupt input starts execution Typical power down current is 1 uA total power down with voltage comparators disabled On chip power on reset allows operation without external reset components A software reset function is also available Programmable external reset pin P1 5 configuration options open drain bidirectional reset input output reset input with pull up push pull reset output input only port A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets Only power and ground connections are required to operate the P89LPC952 954 when internal reset option is selected Configurable on chip oscillator with frequency range options selected by user programmed flash configuration bits Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz Oscillator fail detect The watchdog timer has a separate fully on chip oscill
71. n pin RST 10 30 KQ pin RST Vbo brownout trip voltage BOE 1 2 4 2 7 V Vief bg band gap reference voltage 1 19 1 23 1 27 V TCpg band gap temperature 10 20 ppm C coefficient 1 2 3 4 5 6 7 8 9 Typical ratings are not guaranteed The values listed are at room temperature 3 V The Ipp oper Ipp die and Ipp pa specifications are measured using an external clock with the following functions disabled comparators real time clock and watchdog timer The Ipp tpa specification is measured using an external clock with the following functions disabled comparators real time clock brownout detect and watchdog timer See Section 9 Limiting values for steady state non transient limits on lo or lon If loL lop exceeds the test condition VoL Voy may exceed the related specification This specification can be applied to pins which have A D input or analog comparator input functions when the pin is not being used for those analog functions When the pin is being used as an analog input pin the maximum voltage on the pin must be limited to 4 0 V with respect to Vss Pin capacitance is characterized but not tested Measured with port in quasi bidirectional mode Measured with port in high impedance mode Port pins source a transition current when used in quasi bidirectional mode and externally driven from logic 1 to logic 0 This current is highest when V is approximately 2 V P89LPC952 954 4
72. ntrol and status registers accessible only via direct addressing XDATA External Data or Auxiliary RAM Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR RO or R1 All or part of this space could be implemented on chip The P89LPC952 954 has 256 bytes of on chip XDATA memory plus extended SFRs located in XDATA CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC952 954 has 8 kB 16 kB of on chip Code memory Data RAM arrangement The 768 bytes of on chip RAM are organized as shown in Table 6 Table 6 On chip data memory usages Type Data RAM Size bytes DATA Memory that can be addressed directly and indirectly 128 IDATA Memory that can be addressed indirectly 256 XDATA Auxiliary External Data on chip memory that is accessed 256 using the MOVX instructions Interrupts The P89LPC952 954 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the many interrupt sources The P89LPC952 954 supports 17 interrupt sources external interrupts 0 and 1 timers 0 and 1 serial port O TX serial port 0 RX combined serial port 0 RX TX serial port 1 TX serial port 1 RX combined serial port 1 RX TX brownout detect watchdog RTC I C bus keyboard comparators 1 and 2 SPI and ADC completion Each interrupt source can be individually enabled or disabled by
73. nverted a second interrupt will be generated after the remaining input channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode Auto scan continuous conversion mode Any combination of the eight input channels can be selected for conversion A conversion of each selected input will be performed and the result placed in the result register pair which corresponds to the selected input channel The user may select whether an interrupt if enabled will be generated after either the first four conversions have occurred or all selected channels have been converted If the user selects to generate an interrupt after the four input channels have been converted a second interrupt will be generated after the remaining input channels have been converted After all selected channels have been converted the process will repeat starting with the first selected channel Additional conversion results will again cycle through the eight result register pairs overwriting the previous results Continuous conversions continue until terminated by the user Dual channel continuous conversion mode This is a variation of the auto scan continuous conversion mode where conversion occurs on two user selectable inputs The result of the conversion of the first channel is placed in the result register pair ADODATOR and ADODATOL The result of the conversion of the second channel is placed in result reg
74. ort B High accuracy internal RC oscillator option with clock doubler option allows operation without external oscillator components The RC oscillator option is selectable and fine tunable Fast switching between the internal RC oscillator and any oscillator source provides optimal support of minimal power active mode with fast switching to maximum performance B 2 4 V to 3 6 V Vpp operating range I O pins are 5 V tolerant may be pulled up or driven to 5 5 V E 44 pin and 48 pin packages with 40 and 42 I O pins minimum while using on chip oscillator and reset options B Port 5 has high current sourcing sinking 20 mA for all Port 5 pins All other port pins have high sinking capability 20 mA A maximum limit is specified for the entire chip B Watchdog timer with separate on chip oscillator requiring no external components The watchdog prescaler is selectable from eight values founded by Philips NXP Semiconductors P89 LPC952 954 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC 2 2 Additional features A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz This is six times the performance of the standard 80C51 running at the same clock frequency A lower clock frequency for the same performance results in power savings and reduced EMI Serial flash In Circuit Programming ICP allows simple production coding with co
75. output data valid time slave master SPI output data hold time SPI rise time SPI outputs SPICLK MOSI MISO SPI inputs SPICLK MOSI MISO SS SPI fall time SPI outputs SPICLK MOSI MISO SPI inputs SPICLK MOSI MISO SS Conditions see Figure 20 21 22 23 see Figure 22 23 see Figure 22 23 see Figure 20 21 22 23 see Figure 20 21 22 23 see Figure 20 21 22 23 see Figure 20 21 22 23 see Figure 22 23 see Figure 22 23 see Figure 20 21 22 23 see Figure 20 21 22 23 see Figure 20 21 22 23 see Figure 20 21 22 23 Variable clock fosc 12 MHz Unit Min Max BGL A CCLK 250 250 V CCLK YccLk ock SGL 100 100 0 120 0 240 240 167 0 z 100 2000 100 2000 Min Max 500 ns 333 ns 250 ns 250 ns 165 ns 250 ns 165 ns 250 ns 100 ns 100 ns 0 120 ns 240 ns 240 ns 167 ns 0 ns a 100 ns 2000 ns 100 ns 2000 ns 1 Parameters are valid over operating temperature range unless otherwise specified 2 Parts are tested to 2 MHz but are guaranteed to operate down to 0 Hz P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 54 of 69 NXP Semiconductors P89LPC952 954 Table 13 Dynamic characteristics 18 MHz Vpp 3 0 V to 3 6 V unless otherwise specified Tamb
76. r with automatic reload Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped Timer 0 in Mode 3 forms two separate 8 bit counters and is provided for applications that require an extra 8 bit timer When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 33 of 69 NXP Semiconductors P89 LPC952 954 7 17 6 7 18 7 19 7 19 1 7 19 2 7 19 3 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs are also used for the timer toggle outputs The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on RTC system timer The P89LPC952 954 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down The RTC can be a wake up or an interrupt source The RTC is a 23 bit down counter comprised of a 7 bit prescaler and a 16 bit loadable down counter When it reaches all 0 s the counter will be reloaded again and the RTCF flag will be set The clock source for
77. rase functions can erase any flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory ICP using standard commercial programmers is available In addition IAP and byte erase allows code memory to be used for non volatile data storage On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC952 954 flash reliably stores memory contents even after 400 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC952 954 uses Vpp as the supply voltage to perform the Program Erase algorithms Features Programming and erase over the full operating voltage range Byte erase allows code memory to be used for data storage Read Programming Erase using ISP IAP ICP or two wire serial debugger Internal fixed boot ROM containing low level IAP routines available to user code Default loader providing ISP via the serial port located in upper end of user program memory Boot vector allows user provided flash loader code to reside anywhere in the flash memory space providing flexibility to the user s Any flash program erase operation in 2 ms Programming with industry standard commercial programmers Programmable security for the code in the flash for each sector 400 000 typical erase program cycles for each byte 20 year minimum data retention Flash organization The program memo
78. rnal interrupts can be programmed to be level triggered or edge triggered by setting or clearing bit IT1 or ITO in Register TCON In edge triggered mode if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle the interrupt request flag IEn in TCON is set causing an interrupt request If an external interrupt is enabled when the P89LPC952 954 is put into Power down or Idle mode the interrupt will cause the processor to wake up and resume operation Refer to Section 7 15 Power reduction modes for details NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 27 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC IEO EX0 IE1 EX1 BOF EBO RTCF T T KBIF ERTC EKBI RTCCON 1 S WDOVF EWDRT CMF2 CMF1 EC wake up if in power down EA IEO 7 TFO ETO TF1 ET1 TI 0 and RI O RI O ES ESR TL 0 j interrupt EST to CPU uc El2c SPIF ESPI TI 1 and RI_1 RI_1 j gt ES1 ESR1 o uu TI 1 EST1 ENADCIO ADCIO ENBIO BNDIO EADE 002aab408 Fig 7 Interrupt sources interrupt enables and power down wake up sources P89LPC952_954_4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 28 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 7 13 I O ports
79. rs are ignored until the conversion has completed The edge triggered start mode is available in all ADC operating modes Boundary limits interrupt The ADC has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result is within or equal to the high and low boundary limits or when the conversion result is outside the boundary limits An interrupt will be generated if enabled if the result meets the selected interrupt criteria The boundary limit may be disabled by clearing the boundary limit interrupt enable An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits In this case after the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion meet the interrupt criteria i e outside the boundary limits an interrupt will be generated if enabled If the four MSBs do not meet the interrupt criteria the boundary limits will again be compared after all 8 MSBs have been converted A boundary status register BNDSTAO flags the channels which caused a boundary interrupt Clock divider The ADC requires that its internal clock source be in the range of 320 kHz to 9 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose Power down and Idle mode In Idle mode
80. ry consists of eight sixteen 1 kB sectors on the P89LPC952 954 devices Each sector can be further divided into 64 byte pages In addition to sector erase page erase and byte erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Using flash as data storage The flash code memory array of this device supports individual byte erasing and programming Any byte in the code memory array may be read using the MOVC instruction provided that the sector containing the byte has not been secured a MOVC instruction is not allowed to read code memory contents of a secured sector Thus any byte in a non secured sector may be used for non volatile data storage NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 44 of 69 NXP Semiconductors P89 LPC952 954 7 26 5 7 26 6 7 26 7 7 26 8 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Flash programming and erasing Four different methods of erasing or programming of the flash are available The flash may be programmed or erased in the end user application IAP under control of the application s firmware Another option is to use the ICP mechanism This ICP system provides for programming through a serial clock serial data interface As shipped from the factory the upper 512 bytes of user code space contains a serial ISP routin
81. s stored in RB8 n in Special Function Register SnCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator described in Section 7 19 5 Baud rate generator and selection Mode 2 11 bits are transmitted through TXDn or received through RXDn start bit logic O 8 data bits LSB first a programmable 9 data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 n in SnCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 n When data is received the 9th data bit goes into RB8 n in Special Function Register SnCON while the NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 34 of 69 NXP Semiconductors P89 LPC952 954 7 19 4 7 19 5 7 19 6 7 19 7 7 19 8 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC stop bit is not saved The baud rate is programmable to either 4G or 1 2 of the CPU clock frequency as determined by the SMOD 1 bit in PCON The SMOD bit controls the Timer 1 output rate available to both UARTs Mode 3 11 bits are transmitted through TXDn or received through RXDn a start bit logic 0 8 data bits LSB first a programmable 9 data bit and a stop bit logic 1 In fact Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer
82. slave MSB LSB out X N slave LSB MSB out Khot defined output Z N LN ZN ja La a tspipsu tsPIDH tsPIDSU isPIDSU tSPIDH ND GIA X X seem X input A MSB LSB in A A LSB MSB in AN 002aaa910 Fig 22 SPI slave timing CPHA 0 P89LPC952_954_4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 58 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC I tsPIR a SPIR a TsPIcvc R tsPIF lt gt tsPIR ee I tSPICLKL tsPILAG tSPICLKH SPICLK N J N N CPOL 0 input tSPILEAD a tsPIR tSPICLKL c SPICLK tsPICLKH CPOL 1 input tsPIOH tsPIDV gt tsPIOH a tsPIDV y not defined X slave MSB LSB out N tsPIDIS tSPIA gt MISO output d B MSB out p gt ja tsPIDSU tsPIDsU tsPIDH MOSI WV y N VA s X ossis KX V N 002aaa911 Fig 23 SPI slave timing CPHA 1 11 2 ISP entry mode Table 14 Dynamic characteristics ISP entry mode Vpp 2 4 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tyr Vpp active to RST active delay time pin RST 50 us tnu RST HIGH time pin RST 1 32 us tRL RST LOW time pin RS
83. t 3 High current source P5 4 Port 5 bit 4 High current source P5 5 Port 5 bit 5 High current source P5 6 Port 5 bit 6 High current source P5 7 Port 5 bit 7 High current source Ground 0 V reference negative ADC reference voltage Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes positive ADC reference voltage 1 Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 13 of 69 NXP Semiconductors P89 LPC952 954 8 bit microcontroller with 10 bit ADC 7 Functional description Remark Please refer to the P89LPC952 954 User s Manual for a more detailed functional description 7 1 Special function registers Remark SFR accesses are restricted in the following ways User must not attempt to access any SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a
84. t temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 50 of 69 NXP Semiconductors P89LPC952 954 10 Static characteristics Table 11 Static characteristics Vpp 2 4 V to 3 6 V unless otherwise specified Tamb 40 C to 85 C for industrial applications unless otherwise specified 8 bit microcontroller with 10 bit ADC Symbol IDD oper Ipp idle IDD pd IpD tpd dV dt dV dt Vpon VppR Vin HL Vit Vih LH Vin Vhys VoL VoH Vxtal Vn P89LPC952_954_4 Parameter operating supply current Idle mode supply current Power down mode supply current total Power down mode supply current rise rate fall rate power on reset voltage data retention supply voltage HIGH LOW threshold voltage LOW level input voltage LOW HIGH threshold voltage HIGH level input voltage hysteresis voltage LOW level output voltage HIGH level output voltage crystal voltage voltage on any other pin Conditions Vpp 3 6 V fose 12 MHz Vpp 3 6 V fosc 18 MHz Vpp 3 6 V fosc 12 MHz Vpp 3 6 V fosc 18 MHz Vpp 3 6 V voltage comparators powered down Vpp 3 6 V of Vpp of Vpp except SCL SDA SCL SDA only except SCL SDA SCL SDA only port 1 lo 20 mA Vpp 2 4 V to 3 6 V all ports
85. t vector cece eeee 33 Timers counters 0 and 1 33 Mode Q 000 cece eee eee 33 Mode T cece eee eee eee 33 Mode 2 oos eR EE EE E oe 33 Mode 9 cs iussi dale ERE RENE 33 0 leie PP 33 Timer overflow toggle output 34 RTO system timer a na nannan aaan 34 UARTS iiec Re RE hee REPRE bed 34 Moda 2 osa Lime cer pui Eds 34 Mode 1 2 susce i ene 34 les 27 icu xe ets A Bude Ra tede e X Rn 34 Mode 3 iol iipbRERPREDY bags Eb P EDS 35 Baud rate generator and selection 35 Framing error 2 2 x e e e e eese 35 Break detect ee eeee 35 Double buffering 0000 eae 35 Transmit interrupts with double buffering enabled Modes 1 2 and3 36 The 9th bit bit 8 in double buffering Modes 1 2 and 21 36 I2C bus serial interface 36 T Em 38 Typical SPI configurations 39 Analog comparators sa nessen 40 Internal reference voltage 41 Comparator interrupt 00 41 Comparators and power reduction modes 41 KBI s enu ene er eg E at en EN UE 42 Watchdog timer 0 0 ee 42 Additional features naeun aana 43 Software reset eee eee 43 Dual data pointers s a nananana 43 Debugger Interface nna nna nanana 43 Flash program memory 44 General description luus 44 Features eea Ree e K aa R R eee 44 Flash organization a na na anaana 44 Using fl
86. the address OOH The Boot address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device is forced into ISP mode during power on see P89LPC952 954 User s Manual Otherwise instructions will be fetched from address 0000H Timers counters 0 and 1 The P89LPC952 954 has two general purpose counter timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1 Both can be configured to operate either as timers or event counters An option to automatically toggle the TO and or T1 pins upon timer overflow has been added In the Timer function the register is incremented every machine cycle In the Counter function the register is incremented in response to a 1 to 0 transition at its corresponding external input pin TO or T1 In this function the external input is sampled once during every machine cycle Timer 0 and Timer 1 have five operating modes Modes 0 1 2 3 and 6 Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler In this mode the Timer register is configured as a 13 bit register Mode 0 operation is the same for Timer 0 and Timer 1 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register are used Mode 2 Mode 2 configures the Timer register as an 8 bit Counte
87. this counter can be either the CPU clock CCLK or the XTAL oscillator provided that the XTAL oscillator is not being used as the CPU clock If the XTAL oscillator is used as the CPU clock then the RTC will use CCLK as its clock source Only power on reset will reset the RTC and its associated SFRs to the default state UARTs The P89LPC952 954 has two enhanced UARTS that are compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC952 954 does include an independent Baud Rate Generator for each UART BRGO for UART 0 and BRG1 for UART 1 The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator associated with the specific UART In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection automatic address recognition selectable double buffering and several interrupt options The UARTS can be operated in 4 modes shift register 8 bit UART 9 bit UART and CPU clock 32 or CPU clock 16 Mode 0 Serial data enters and exits through RXDn TXDn outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 146 of the CPU clock frequency Mode 1 10 bits are transmitted through TXDn or received through RXDn a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit i
88. ting values sseeee 50 Static characteristics 51 Dynamic characteristics 53 Waveforms lesse 57 ISP entry mode nannan anaana 59 Other characteristics 60 Comparator electrical characteristics 60 ADC electrical characteristics 61 Package outline LLlus 62 Abbreviations 000 cece eee eee 65 Revision history esses 66 Legal information sse x e x e x x x e 67 Data sheet status 0 0 00 ee 67 Definitions 2 ERR ben oe eat ee bes 67 Disclaimers n on nnana c cee eee eee ees 67 Trademarks wissen 4 R ede ka eal be eee 67 Contact information 67 Contenlss cose SABE EE AUS 68 founded by 8 bit microcontroller with 10 bit ADC Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2008 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com All rights reserved Date of release 24 July 2008 Document identifier P89LPC952_954 4
89. tion of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 11 Static characteristics for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below P0 0 CMP2 40 43 37 O P0 0 Port 0 bit 0 KBIO ADOS O CMP2 Comparator 2 output l KBIO Keyboard input 0 l AD05 ADCO channel 5 analog input P0 1 CIN2B 39 42 36 O P0 1 Port O bit 1 KBIT ADOO l CIN2B Comparator 2 positive input B l KBI1 Keyboard input 1 l AD00 ADCO channel 0 analog input P0 2 CIN2A 38 41 35 O PO 2 Port 0 bit 2 KBI2 ADO1 l CIN2A Comparator 2 positive input A l KBI2 Keyboard input 2 l AD01 ADCO channel 1 analog input P0 3 CIN1B 37 40 34 O P0 3 Port O bit 3 KBI3 AD02 l CIN1B Comparator 1 positive input B l KBI3 Keyboard input 3 l AD02 ADCO channel 2 analog input P0 4 CIN1A 36 39 33 UO P0 4 Port 0 bit 4 KBI4 AD03 l CIN1A Comparator 1 positive input A l KBI4 Keyboard input 4 l AD03 ADCO channel 3 analog input P0 5 CMPREF 35 38 32 O P0 5 Port 0 bit 5 KBI5 P89LPC952_954_4 CMPREF Comparator reference negative input KBI5 Keyboard input 5 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008
90. uct data sheet Rev 04 24 July 2008 12 of 69 NXP Semiconductors P89LPC952 954 Table 3 Pin description continued 8 bit microcontroller with 10 bit ADC Symbol Pin LQFP48 PLCC44 LQFP44 P4 4 21 26 20 P4 5 TDI 20 25 19 P4 6 19 24 18 P4 7 TCLK 18 23 17 P5 0 to P5 7 P5 0 16 21 15 P5 1 15 20 14 P5 2 14 19 13 P5 3 13 18 12 P5 4 12 17 11 P5 5 11 16 10 P5 6 10 15 9 P5 7 9 14 8 Vss 17 45 3 22 16 41 VREFN 44 Vpp 8 32 13 36 7 30 VREFP 33 Type Description UO UO UO UO UO UO UO UO UO UO UO UO UO UO P4 4 Port 4 bit 4 P4 5 Port 4 bit 5 TDI Serial data input output for debugger interface P4 6 Port 4 bit 6 P4 7 Port 4 bit 7 TCLK Serial clock input for debugger interface Port 5 Port 5 is an 8 bit I O port with a user configurable output type During reset Port 5 latches are configured in the input only mode with the internal pull up disabled The operation of Port 5 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 7 13 1 Port configurations and Table 11 Static characteristics for details All pins have Schmitt triggered inputs Port 5 also provides various special functions as described below P5 0 Port 5 bit 0 High current source P5 1 Port 5 bit 1 High current source P5 2 Port 5 bit 2 High current source P5 3 Port 5 bi
91. will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when Vpp falls below the minimum specified operating voltage Reset can be triggered from the following sources External reset pin during power up or if user configured via UCFG1 UCGF2 Power on detect Brownout detect Watchdog timer e Software reset UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared For any other reset previously set flag bits that have not been cleared will remain set P89LPC952 954 4 NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 32 of 69 NXP Semiconductors P89 LPC952 954 7 16 1 7 17 7 17 1 7 17 2 7 17 3 7 17 4 7 17 5 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC Reset vector Following reset the P89LPC952 954 will fetch instructions from either address 0000H or the Boot address The Boot address is formed by using the boot vector as the high byte of the address and the low byte of
92. ype can be used as both an input and output without the need to reconfigure the port This is possible because when the port outputs a logic HIGH it is weakly driven allowing an external device to pull the pin LOW When the pin is driven LOW it is driven strongly and able to sink a fairly large current These features are somewhat similar to an open drain output except that there are three pull up transistors in the quasi bidirectional output that serve different purposes The P89LPC952 954 is a 3 V device but the pins are 5 V tolerant In quasi bidirectional mode if a user applies 5 V on the pin there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port driver when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 29 of 69 NXP Semiconductors P89 LPC952 954 7 13 1 3 7 13 1 4 7 13 2 7 13 3 7 14 7 14 1 P89LPC952 954 4 8 bit microcontroller with 10 bit ADC An open drain port
93. z 320 520 320 520 kHz 0 18 MHz 55 ns 0 8 MHz 50 50 ns 15 15 ns 125 125 ns 50 50 ns 22 Toy clk tcLcx 22 ns 22 Tey cik tcHcx 22 nS 5 5 ns 5 5 ns 1 6T cyclk S 888 S ns 1 3T cy clk S 722 S ns 2 Tey clk 20 Ji 75 ns S 0 0 ns 150 150 ns 0 ccu 0 3 0 MHz Ceu 45 MHz B B 333 ns CCLK z 222 ns NXP B V 2008 All rights reserved Product data sheet Rev 04 24 July 2008 55 of 69 NXP Semiconductors P89LPC952 954 Table 13 Dynamic characteristics 18 MHz continued Vpp 3 0 V to 3 6 V unless otherwise specified Tamp 40 C to 85 C for industrial applications unless otherwise specified J 8 bit microcontroller with 10 bit ADC Symbol Parameter Conditions Variable clock fosc 18 MHz Unit Min Max Min Max tspiLEaD SPI enable lead time see Figure 22 23 slave 250 250 ns tspi_ag SPI enable lag time see Figure 22 23 slave 250 250 ns tspicLkH SPICLK HIGH time see Figure 20 21 22 23 slave Yocik 167 ns master V CCLK 111 ns tspicLkL SPICLK LOW time see Figure 20 21 22 23 slave Yocik 167 ns master V CCLK 111 ns tspipsu SPI data set up time see Figure 20 21 22 23 master or slave 100 100 ns tePipH SPI data hold time see Figure 20 21 22 23 master or slave 100 100 ns Lapa SPI access time see Figure 22 23 slave 0 80 0 80 ns tePiDIS SPI disable time see Figure 22

P89LPC952/954 8-bit microcontroller with accelerated two

Contents

Download Pdf Manuals

Related Search

Related Contents