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CybraTech SOC-4000 Data Sheet

1. Port Latch Timer 0 P2 0 to P2 7 Port Latch FIGURE 7 CPU BLOCK DIAGRAM Revision B Page 15 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Memory Organization The SOC 4000 is an 8051 compatible device with an 80C310 memory chip As with all such devices the SOC 4000 has separate address spaces for Program and Data memory The program memory space can be programmed while the device is in circuit through the serial port e Flash memory memory space containing non volatile in circuit re programmable code and data such as calibration data The code in the Flash memory may be in circuit programmed at a byte level although it must first be erased the erasing being performed in page blocks The program memory space can be in circuit programmed through the serial port e RAM memory Temporary memory used as scratchpad memory for the software Program Memory Mapping The 805 1 compatible SOC 4000 supports a maximum code space of 64K Programs larger than 64K are handled by bank switching in order to select one of a number of code banks residing at one physical address In the SOC 4000 there is one 32K Common Program Area mapped from address 1000H to 7FFFH Figure 9 and 15 x 32K code banks mapped from code address 8
2. Sample Rae s ewe U i AID Converter Reference s v mm Reference Input a Revision B Page 3 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Digital Input PARAMETER UNIT COMMENTS ow vote ao 08 v rang a XTAL Input Vin Input High Voltage 2 5 V Mu Input Low Voltage 0 4 V Digital Output PARAMETER UNIT COMMENTS Vor Output High Voltage JL SESS e TTL Level set by user by external resistors Vor Output Low Voltage joo 08 vi TTL Level set by user by external resistors mcn 39 Y oo os Y Flash Memory Erase Full Memory 100 Single Block 4kByte Program Byte Revision B Page 4 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification CPU Enhanced 80C51TBO RESET Threshold Level 3 98 Start Up Time 500 e From Power On 1 e From Idle Mode 1 Oscillator power down not through OSCEN bit 500 Oscillator power down through OSCEN bit e From Power Down 1 From Watchdog Reset Frequency Source Input resonator Power Supply and Monitor re Voege won aso espv Poner rormpaentorion anon prac voras mava as sosav Darai votage input vo 96 33 foe v sopor carene wm Environmental Conditions PARAWETER MN me Temperature 0 20 49 Full performa
3. 41 STRETCHER CONTROLLER REGISTERS D SCRIpTION eme nennen enne 47 STROBE CLOCK ENABLE CONTROL REGISTER BIT FONCTIONS eine 47 TRIGGER REGISTER DEFINITIONS 48 STRETCHER CONTROLLER DATA REGISTER BIT DEFINITIONS eee 48 STRETCHER RESET REGISTER DEFINITIONS 7 49 PRINTER SENSORS INTERFACE 52 ADC CHANNEL 2 0UTPUT RANGE 2 2 2222 i 55 CLOCK FREQUENCY CONTROL REGISTER BIT SETTINGS nenne 58 WATCHDOG TIMER OPERATING PARAMETERS nono LLI nennen eren 59 WATCHDOG TIMER COMMAND SEOUENCER ene ene ese ese ese sse esee esee 59 POWER FAILURE INTERRUPT REGISTER BIT SETTINGS ei 61 CFR BIT CONFIGURATION en a rie tere etn bere te Redi i iro einen ernsten Pe CERE TEN 64 GEOBAP CER 67 C200H CLOCK ENABLE REGISTER 67 C200H CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS 68 C201H CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS e 68 CONTROLLERS RESET REGISTER GW sn een 69 BIT ORIENTED I O PORTS ADDRESSES PIN AND BIT ASSIGNMENT eee 71 BYTE ORIENTED OUTPUT PORTS ADDRESSES AND PIN ASSIGNMENT ecce 72 AVAILABLE PINS ON THE 80C51 VO PORT ad hE Taar 73 COMMUNICATION CHANNEL MULTIPLEXER CONTROL e eren enne nr en net 80 PC COMPATIBLE INTERFACE HARDWARE INTERFACE 84 SOC 4000 INTERFACE SIGNALS TO LCD DISPLAY 86 LCD DISPLAY MODULE INTERFACE SIGNALS e eene n
4. KEYBOARD CONTROLLER Features Functional Description e Supports up to 128 keys 8x16 Keyboard Controller Matrix Configuration Programmable anti bounce mechanism The keyboard matrix configuration showing the 4 18 ms 8 x 16 matrix is given in Figure 11 The key code e Automatic key matrix scanning values at each junction are in hexadecimal e Automatically detects excessively long or constant key depression e When Interrupt mode enabled generates an interrupt when any key is pressed or released Revision B Page 29 August 2002 Technical Specification SOC 4000 i Scale On Chip ASIC CybraTech 2000 Ltd KIN12 KIN13 KIN14 KIN15 KIN 8 KIN 9 KIN10 KIN11 KIN 7 co z NS KIN 1 KIN2 KIN 3 KIN 4 KIN 5 KIN 0 s S 18 n Ge 4B M b S e s G d Se 3 gt Ga Se 3 Li _ 3 Se 78 y E Ge 78 d ML s S 3 od s MU ee a 77 SC T MU gt N w N Sa M gt 55 75 S oL LI e S I G o 69 o o n SM e eM 9 QF SC 1 01 amp Nu 5 SC 6
5. 4 Check semaphore byte at address D201H If semaphore byte is Ready Bits 0 to 7 set to 0 write data to Data register addresses D201H to D218H 5 Set Write command at the controller Control register address D200H Repeat steps 4 and 5 for new data Revision B Page 38 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification PRINTER SERIAL INTERFACE CONTROLLER Features Supports paper and labels Up to 448 Dots line Up to 100 mm s printing speed Power voltage failure protection Auxiliary motor controller rewinder Head temperature sensor reading support Functional Description The printer head is supported by the serial data and serial clock pins 44 45 The frequency of the clock can be changed The dot printer energy may be controlled by up to six strobe lines STROBE STROBE6 Printer motor and sensors support see Strobe Controller page 45 and Interfacing the Printer Opto Sensors using ADC 2 channel page 51 NOTE The strobe lines also referred to as Output Enabled OE or Stretcher lines STR Power VPP Pin28 Vch Line of resistors dots Pin 36 Strobe 1 OE1 448 Dots Pin 41 Strobe 6 OE6 Pin43 PRN Latch Pin44 PRN SIData gt Up to
6. 4 19v The hystheresis of the Reset signal is set so that normal operation of the internal Flash memory is guaranteed Interrupt Vectors Revision B The interrupt vectors of the SOC 4000 I are shifted compared with the interrupt vectors of a standard 80C51TBO vectors by an offset of 1000H Table 2 details the SOC 4000 I interrupt vectors Page 20 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 2 INTERRUPT VECTORS DESCRIPTION INTERRUPT SOURCE FLAG VECTOR PRIORITY LOCATION External Interrupt 0 1003H 1 Highest Ice non 20 Revision B Page 21 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification ADC CONTROLLER INTERFACE Features e Resolution 20 bit e Programmable gain 0 5 0 75 1 1 5 2 e Programmable sample rate of 5 10 or 20 samples per second e Voltage detection input and alarm Controller Registers ADC Converter ADC controller interface includes a semaphore register one byte a control register two bytes and a data status register four bytes The ADC controller registers are defined in Table 3 TABLE 3 ADC CONTROLLER REGISTERS DESCRIPTION FUNCTION ADDRESS SES REMARKS Controller Clock Enable C200H 0 Disable 1 Enable Semaphore Register The semaphore register bit definitions are shown in Table 4 TABLE 4 ADC CONTROLLER INTERFACE SEMAPHORE REGISTER BIT DEFINITIONS ADD
7. Normal Operation 2 Reset a Stretcher controller by writing FFH to that register s address Table 22 page 49 3 Set data values for the Stretcher according to the desired length most and least significant byte 4 Write FF command at Stretcher controller Control register addresses to trigger its operation as defined in Table 20 page 48 5 Repeat steps 2 to 4 for all enabled stretchers Revision B Page 50 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification PRINTER MOTOR AND SENSOR INTERFACE Printer Motor Operation Figure 19 describes the timing diagram for driving the printer motor and the heating process timing relationship MOTORI and MOTOR are generating the PWM signals controlling the motor currents MOTOR3 and MOTOR4 are controlling the motor phases A and B MOTORS and MOTOR6 spare outputs available for the system designer All the motor outputs are OUTPUT pins that are controlled by the printer software driver The timing of these outputs should be set according to the printer head specification Motor Steps td Heating cycles FIGURE 19 PRINTER MOTOR TIMING DIAGRAM Interfacing the Printer Opto Sensors Opto sensor characteristics have very wide tolerances Thus usually it cannot be connected directly to a digital logic input The SOC 4000 opto sensor input pins are designed to interface opto sensors The input stage is a Smidt Trigger input with a pull up resist
8. TABLE 17 TABLE 18 TABLE 19 TABLE 20 TABLE 21 TABLE 22 TABLE 23 TABLE 24 TABLE 25 TABLE 26 TABLE 27 TABLE 28 TABLE 29 TABLE 30 TABLE 31 TABLE 32 TABLE 33 TABLE 34 TABLE 35 TABLE 36 TABLE 37 TABLE 38 TABLE 39 TABLE 40 TABLE 41 TABLE 42 Revision B LIST OF TABLES SOC 4000 PIN CONFIGURATION FOR PRINTER ener LLARY LL LLALL FFY nion 9 INTERRUPT VECTORS DESCRIPTION tea eE een nee io Eoi Cave e eo ao out 21 ADC CONTROLLER REGISTERS DESCRIPTION iii 23 ADC CONTROLLER INTERFACE SEMAPHORE REGISTER BIT DEFINITIONS eene 23 ADC CONTROLLER INTERFACE CONTROL REGISTER BIT FUNCTIONS eee 24 ADC CONTROLLER INTERFACE DATA REGISTER BIT DEFINITIONS eren 24 ADC CONTROLLER INTERFACE DATA REGISTER BIT 25 ADC OUTPUT COUNTS VS ADC STT 27 KEYBOARD CONTROLLER REGISTERS DESCRIPTION emere ennt enn nnne 31 KEYBOARD CONTROLLER CONTROL REGISTER BIT 31 KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS ee Y Y Y i HiN 32 LED SERIAL CONTROLLER DRIVER REGISTERS 36 LED VFD SERIAL INTERFACE DISPLAY CONTROL REGISTER BIT FUNCTIONS 37 LED VFD SERIAL INTERFACE DISPLAY DATA REGISTER BIT DEFINITIONS 38 PRINTER INTERFACE CONTROLLER REGISTERS DESCRIPTION i 40 PRINTER INTERFACE CONTROLLER CONTROL REGISTER BIT FUNCTIONS cc 40 PRINTER INTERFACE CONTROLLER DATA REGISTER BIT
9. 24 Digits MicroController Core And Delta Sigma ADC Peripherals 20 Bits PGA 1 Serial Communication 2 pw RS 232 RS 485 80C51TBO 512K x 8 Program Data Flash MUX Printer Head Aux Channel 512K x 8 RAM Printer Printer Controller Motor Power Down Detector Internal Bandgap Reference Frequency Controller Watchdog Timer 3 x 16 Bit Timers Power Supply Monitor 12C Compatible SPI Like Serial Interfaces UART Printer Sensors Keyboard Controller 8x 16 Revision B Oscillator Resonator Keyboard FIGURE 2 S0C 4000 MAXIMAL BLOCK DIAGRAM Page 2 X vo August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification SPECIFICATIONS Analog to Digital Converter ADC A D Converter Main Channel Wheatstone Bridge Load Cell Differential Input Voltage Ion TI Programmable Gain 0 5 2 Upto8toadce we Gain Drift vs Temperature E qe ppm C Integral Non linearity gt 0004 Offullscale o e que __ i weep Ham ER Offset Drift vs Temperature 4 B ws AID Converter Auxiliary Channel o hf pem n me 4 66
10. 51 ri 3 ae fon a S se ae 30 S A Se a G 70 KOUT 0 KOUT 1 KOUT 2 KOUT 2 KOUT 4 KOUT B KOUT 7 Key values are in hexadecimal FIGURE 11 KEYBOARD MATRIX CONFIGURATION August 2002 Page 30 Revision B CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Controller Registers Keyboard controller interface includes a control register one byte and a data status register two bytes The Keyboard controller registers are defined in Table 9 TABLE 9 KEYBOARD CONTROLLER REGISTERS DESCRIPTION FUNCTION ADDRESS REMARKS Controller Clock Enable C200H 2 0 Disable 1 Enable Controller RESET C400H AI OF Reset Data Registers F100H to F101H Al Read only Registers Description Control Register The keyboard control register bit definitions functions and settings are displayed in Table 10 TABLE 10 KEYBOARD CONTROLLER CONTROL REGISTER BIT FUNCTIONS ADDRESS FUNCTION SETTINGS F100H 0 2 Anti Bounce Timeout 000 4 ms 0 LSB 001 6 ms 010 2 8 ms 011 10 ms 100 12 ms 101 14 ms 110 16 ms 111 18 ms 1 Disable default Data Registers Keyboard data is stored in two 8 bit registers The data register bit definitions are shown in Table 11 Revision B Page 31 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specifica
11. KIN7 KING KIN5 KIN4 KIN3 KIN2 KIN1 KINO Keyboard Controller Input See Keyboard Controller page 29 1 0 P15 0 LO P15 1 LO P15 2 LO P15 3 1 0 P15 4 1 0 P15 5 1 0 P15 6 LO P15 7 1 0 See I O Operation on page 71 BUZZER Buzzer P1 7 CPU SCL IC Serial Clock P1 5 CPU SDA UC Serial Data P1 4 CPU XTAL OUT XTAL IN Frequency source TX RX TX2 RS485 RX2 Serial communication OUT P4 0 OUT P4 1 Outputs See I O Operation on page 71 LABEL DET Label detect input See page 53 LO P3 4 CPU AUTO DET Prepack label removal detector input See page 53 LO P3 5 CPU PAPER DET Revision B Paper detect input See page 53 Page 9 LO P1 6 CPU CPU I O Ports Or P3 4 TIMER 0 P3 5 TIMER 1 August 2002 CybraTech 2000 Ltd DESCRIPTION Printer head heater power control See Strobe Controller page 45 and Printer Head Data Interface Operation page 43 SOC 4000 i Scale On Chip ASIC DAL FUNCTION OUT P4 2 AUXMOTOR Auxiliary motor control OUT P4 3 MOTORI MOTOR2 MOTOR3 MOTOR4 MOTORS MOTOR6 Motor control See also Printer Motor Operation page 51 OUT P5 0 OUT P5 1 OUT P5 2 OUT
12. Load Cell Cable l Regulated 6 Wires 5 Reg 73 AVcc 72 SEN 71 SIG 70 SIG SOC 4000 69 SEN AGND 68 AGND FIGURE 28 6 WIRE LOAD CELL CONNECTION Page 78 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Load Cells Connected in Parallel The SOC 4000 may be connected to up to eight load cells connected in parallel Multiple load cells are required in heavy load applications such as weigh bridges that require from two to eight load cells Load cells connected in parallel typically result in lower output impedance which decreases in direct proportion to the number of load cells This results in a higher excitation current and higher sensitivity to factors that throw load cells out of balance The SOC 4000 eliminates this problem with its high Common Mode Rejection Ratio CMRR which allows the connection of a large number of load cells up to eight without losing measurement accuracy The multiple load cell connection is shown in Figure 29 IMPORTANT The load cells should be matched before connecting them to the SOC 4000 to ensure the same initial offset span and impedance This will eliminate error factors that are beyond the control of SOC 4000 electronics NOTE These large weighing platforms may also require a 6 wire interface connection as described above page 77 LOAD Cells J
13. 1 LED SI_CLK P13 0 VBAT CSLCD P12 2 WRLCD AD P121 RDLCD A1 P12 0 FIGURE 6 SOC 4000 PIN CONFIGURATION Page 13 Technical Specification August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification CPU 80C51TBO The reference source for data given here is Advantages M8051TBO Technical Specifications Virtual IP Group Inc Version M8051TS97DF02 Refer to this manual for a complete CPU specification e Fast running and improved performance e No wasted clock and memory cycles e Works efficiently with all types of peripheral Features devices e 8 bit CPU e Compatible with standard 80C31 e Four 8 bit I O ports e Three 16 bit timers e On chip oscillator and clock circuitry e 256 byte on chip 8051 compatible SFR RAM e 64Kbyte program memory with bank switching e 4Kbyte external RAM e High speed architecture of 4 cycles instruction e Improved power consumption characteristics e On chip Power On Reset Architecture The CPU block diagram is presented in Figure 7 e Dual data pointers e Full Duplex enhanced UART Port Latch P10 to P1 7 ADO to AD7 Timer 2 je gt Serial Port 0 Address N P3 0 to P3 7
14. 29 3 Program the keyboard controller as described in Keyboard Controller page 29 Page 81 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Revision B FIGURE 30 KEYBOARD INTERFACE Page 82 August 2002 Yu 1 1 5 HG JM 23 M M Mi Ma Koute 7 8 9 F2 F6 gt M9 Mi MTT 12 13 M14 15 16 SUIS 4 5 674 El Fr D Ce M17 8 9 20 21 22 23 24 KOUTA 1 2 GB GEF Mt Ma MOL 6 27 28 29 0 31 32 lt Pen TE Mn WY WAL Y Wm Koun 0 Enter 6 Bsp Esc O P M33 M34 35 36 37 M38 M39 40 mE QJ 1 3 173 M41 M42 M43 M44 M45 M46 M47 Mag A el DI IF IS MH TL KJ 1M49 M50 51 M52 M53 M54 M55 M56 KoUTO ZA TEL VI IB N CMMs 59 M60 M i M62 M i 64 82 83 84 1 2 3 4 5 74 75 76 TT 78 79 80 81 7 8 9 1
15. 80H to inhibit all the outputs from hardware controllers and therefore avoid damage to external hardware The application software should implement the following steps to initialize the ASIC 1 Cyn sus Program the Configuration Registers CFRs to support the application hardware as defined in Table 16 page 2 a Set registers C103H C104H C105H and C106H to AAH If an LED VFD Serial Interface Display is used set register C101H to AAH If an LCD Display is used set register C102H to DS Set the other CFRs as required according to the keyboard printer stretchers printer motors and sensors supported Initialize the applicable hardware controllers Enable the clock source of the controllers using register C200H and C210H Write 00H to the GLOBAL register C100H Enable the Watchdog timer Page 75 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification PERIPHERAL INTERFACE CONNECTIONS Load Cell Interface The SOC 4000 supports a wide range of load cell connection configurations each based on various combinations of the following connection options e 4 wire or 6 wire interface e Upto eight load cells connected in parallel e Load cell impedance range of 350 to 1000 ohms Individually and in combination these connection options enable the SOC 4000 to function on a wide range of application platforms each having different power consumption and system configuration requirement
16. P6 0 OUT P6 1 OUT P6 2 STROBE1 0E1 STROBE2 0E2 STROBE3 0E3 STROBE4 0E4 STROBES OE5 STROBE6 OE6 Printer head dot control See Strobe Controller page 45 OUT P6 3 Technical Specification DESCRIPTION PULL UP RESISTOR Outputs See I O Operation on page 71 OUT P7 0 OUT P7 1 OUT P7 2 OUT P7 3 OUT P8 0 Outputs See I O Operation on page 71 SWITCH Printer head switch detector input 1 0 P18 0 VO See I O Operation on page 71 PRN LATCH PRN_SI_DATA PRN_SI_CLK Printer serial data interface See Printer Serial Interface Controller page 39 and Printer Head Data Interface Operation page 43 OUT P8 1 OUT P8 2 OUT P8 3 Outputs See I O Operation on page 71 DO OUTPUT D1 OUTPUT D2 OUTPUT D3 OUTPUT D4 OUTPUT D5 OUTPUT D6 OUTPUT D7 OUTPUT LCD Display module interface data bus interface Output only See LCD Display Module Interface page 86 RDLCD A1 Read Signal for LCD display module See page 86 OUT P12 0 WRLCD A0 Write Signal for LCD display module See page 86 OUT P12 1 CSLCD Chip Select for LCD display module See page 86 OUT P12 2 Output See I O Operation on page 71 VBAT Revision B RAM backup voltage i
17. Reading Data DO LSB D19 MSB Gi PDi Gain Power Down cH active ADC Channel Revision B Page 25 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Operation Initialization To enable the ADC controller interface 1 Enable the ADC controller interface clock source in Clock Enable register C200H Set C200H Bit 7 to 1 Reset the ADC controller interface Write FF to register C406H Set the Configuration registers CFR address for ADC controller interface function CFR address C10CH 1FH Enable interrupt Set E101H Bit 0 to 1 Check the semaphore byte at address E100H If Receive semaphore bit at E100H is Ready Bit 0 0 signaling the CPU that the ADC controller can receive data the CPU performs the following operations a Sets the Transmit semaphore bit at E100H to Busy Bit 1 1 to prevent transmission of data from the ADC controller b Programs the control register E101 E102H of the ADC controller to initialize controller operation Normal operation 6 After the ADC controller has been initialized the following operations are performed c The CPU resets the Transmit semaphore bit at E100H to Ready Bit 1 0 to signal the ADC controller that it can now transmit data d The ADC controller sets the Receive semaphore bit at E100H to Busy Bit 0 1 to prevent further data transmission to the controller e The ADC controller sends ADC converter
18. Up to 128 keys VIN DE Buzzer KB 1 8 KBI 1 16 VIN Setpoints Vcc FIGURE 1 SOC 4000 TYPICAL APPLICATION Revision B Page 1 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification General Description The SOC 4000 ASIC is an 84 pin single chip scale intended to replace present day multiple component weighing printer scale electronic circuitry designs It includes the pre amplifier A D converter display drivers keyboard controller printer drivers serial communication embedded CPU and field programmable program and data memory As 8 stand alone unit it incorporates all scale hardware functions and represents a true breakthrough in scale manufacturing It eliminates the risks costs and inventory needs associated with discrete components The SOC 4000 comes with a comprehensive software library which implements hardware drivers such as the display keyboard and printer as well as most of the standard weighing functions A complete development environment is available enabling the user to tailor and customize the application according to specific needs The general SOC 4000 block diagram is presented in Figure 2 Advantages e Generic OIML R 76 approval e Minimize hardware and software development e Significantly cuts time to market e Reduces inventory needs Displays Ref Ref Load Cell Serial Display Controllers LCD LED VFD 20
19. gt LC 0 0 o Ch Op 0 Ch op Digit 6 Digit 5 Digit 3 Digit 1 b 1 Ve Ue Us Us lt lt DD TDI DD ef 0 0 O d d Cycle 8 010 01010 x x The controller transmits cycles 1 to 8 continuously FIGURE 12 LED VFD SERIAL INTERFACE DISPLAY BLOCK DIAGRAM Revision B Page 35 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification 20 us i 400 us gt sea T ES SL STROBE 20us gt i it1 8 psi FIGURE 13 LED VFD SERIAL INTERFACE CONTROLLER TIMING DIAGRAM Registers Description The LED Serial controller registers description is given in Table 12 TABLE 12 LED SERIAL CONTROLLER DRIVER REGISTERS DESCRIPTION Sempre reinar Pe eem Data Registers Control Register D200H ww Read Write LED data is stored in a 24 byte x 8 bit static display RAM The data registers are divided into three groups each group containing eight bytes with the segment data for eight digits Thus the LED display can be formatted to display eight 16 or 24 digits The display RAM has one Read Write control register containing the Command byte and a Read only semaphore byte that informs the system if the display is Busy or Ready to initiate writing of LED data The semaphore byte address also s
20. i Scale On Chip ASIC Technical Specification Normal Operation 6 Read keyboard key code value bits as follows e Read register F100H Bit 0 If 0 key code value is legal If 1 key code value is illegal Error e Read keyboard values from register F101H bits 0 to 6 When key pressed values are valid e Read F101H bit 7 If 0 Key pressed and keyboard values bits 0 to 6 are valid If 1 Key released and keyboard values are meaningless Revision B Page 33 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification LED VFD SERIAL INTERFACE DISPLAY CONTROLLER Features Functional Description e Supports up to 24 digits The LED VFD Serial Interface display e Serial interface comprises three groups of eight digits The controller diagram showing the division of the P bl trol signal polarit cU GU RU EL 24 byte register into three eight byte groups Programmable data registers and the operation cycle is given in Figure 12 gt un GORDON ED Ten The LED VFD Serial Interface Display Controller timing diagram is shown in Figure 13 The clock rate is 2 MHz Digit 8 Digit 7 Digit 6 Digit 5 Digit 4 Digit 3 Digit 2 Digit 1 b b b b b b b GV O NI cr ch pl Less L DI DD EI hod Le E UL UL Ch DP DP DP DP Digit 8 Digit 7 Digit 6 Digit 5 Digit 3 Digit 2 Digit 1 al dek 0 2 m lt gt lt gt lt lt gt come DI lt
21. oun emo pa us uz un me 7 6 5 4 o o teas oun emm us uz un o t9 mes em us 5 4 o o ours Exe of un uz un 9 moe eme o 8 5 4 e 6 teas oun men of ua uz un o moes em 7 8 5 o o ours Emo un uz un 9 me em 7 us 5 e e 65 teas ours cmm or Fa us uz un uo t Revision B Page 48 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification LEGEND NAME FUNCTION VALUE Stretcher Pulse length in For Auxmont and VPP maximal pulse length is 32 768 US micro seconds For STROBE1 6 maximal pulse length is 16 384 uS Lo always LSB of pulse length OE Output Enable 0 Disabled 1 Enabled Pulse Polarity 0 Positive 1 Negative TABLE 22 STRETCHER RESET REGISTER DEFINITIONS Revision B Page 49 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Operation At power on or reset the Stretcher controller is disabled Initialization To enable the Stretcher controller 1 Enable the Stretcher controller clock source in Clock Enable register C201H Setting the significant bit to 1 enables that Stretcher Table 19 page 47
22. pr Toscano Revision B Page 66 KOUT Keyboard Out KIN Keyboard In August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification SPECIAL FUNCTION REGISTERS SFR The SOC 4000 1 includes Special Function Registers SFR that enable the device hardware controllers and reset them Each controller description details its specific SFR operation This section details all the SFR registers and functions All these registers are mapped as XDATA memory area Global CFR Register Register C100H is used as a general enable disable of pin allocation to all the hardware controllers in the SOC 4000 i Upon power up or reset this register is set disabling all the hardware controllers Writing 0x00 to the register activates the allocation of pins to hardware controller as defined by programming the CFR registers TABLE Ss REGISTER ADDRESS FUNCTION REMARKS Oef C100H Enable Disable pin allocation 0x00 Enable OxFF Disable Operation 1 Upon power up or reset the Global CFR register is cleared disabling all pin allocation to the hardware controllers 2 Initialize the CFR registers according to the required hardware configuration as described in section Configuration Registers CFR page 55 3 Initialize the hardware controllers 4 Enable the Global CFR Register Write 0x00 to address C100H Controllers Clock Enable Registers Registers C200H C201H contro
23. sources may be connected to this input using open collector drivers operating in negative logic mode 0 is active interrupt A low voltage input triggers the INTO The application software applies a mechanism to determine whether the interrupt was generated by low battery voltage or by other interrupt source The external interrupt sources should be level type and not pulse It is recommended to add a LPF with R 330 Ohm C 1uF Using Timer0 and Timer1 inputs SOC 4000 pin 25 is connected to the 80C51 Timer 0 input P3 4 and pin 26 is connected to Timer input P3 5 These inputs may be used for counting or timer operations or as additional interrupt inputs to the device Using these inputs as interrupt inputs requires that the appropriate timer be set to OxFE The next event causes the counter to increase to OxFF and triggers the Timer 0 or Timer 1 interrupt 2 I C Compatible Interface The SOC 4000 supports a 2 wire DC compatible serial interface The PC compatible interface shares its pins with the CPU I O pins P1 4 P1 5 and is implemented in software Table 39 provides the hardware interface information TABLE 39 1 C COMPATIBLE INTERFACE HARDWARE INTERFACE PIN NAME DESCRIPTION SDA P1 4 Serial Data I O pin 16 SCL P1 5 Serial Clock pin Power Saving Schemes SOC 4000 provides several means to save power for battery operated systems e Set the CPU to IDLE or POWERDOWN operating modes see deta
24. 0 11 12 13 14 lt PIN KIN15 KIN14 KIN13 KIN12 KIN11 KIN10 KIN9 KIN8 KIN7 KING KINS KIN4 KIN3 KIN2 KIN1 KINO Signal CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification LED VFD Serial Display Interface The SOC 4000 interface supports Serial LED VFD displays as follows e Upto 24 digits each comprising eight segments seven segment digit plus Decimal Point DP e Three digit groups Weight Price and Total e Automatic hardware refresh mechanism to reduce power consumption To operate the LED VFD display common anode e Initialize the CFR registers to support operation in the LED VFD Serial display mode See Table 29 page 64 Segment ULN2003 x 4 SOC 4000 Pin 58 LED VFD 74HC595 Digit Driver High Current Drivers uni x 4 ULN2003 DY9953 in 61 x 1 x 4 FIGURE 31 SOC 4000 INTERFACE TO A LED VFD DISPLAY External Interrupt Sources External interrupt sources may be connected to the SOC 4000 using the following pins d Vdet INTO e P3 4 Timer counter 0 input f P3 5 Timer counter 1 input Revision B Page 83 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Using the Vdet input The Vdet input is connected to INTO of the 80C51TBO core In battery operated equipment this input is connected to the battery voltage divider and used to detect low battery voltage Other interrupt
25. 000H to FFFFH Figure 9 The code banks are selected using P1 0 to P1 3 as described below Program Memory Bank Select Register The program memory bank select register is implemented using the 80C51TBO Port 1 bits P1 0 P1 3 P1 0 is the least significant bit Manipulation of other Port 1 I O pins must be carried out without affecting these bits To enable the program memory access set registers C104H C105H and C106H to AAH as follows C104H AAH C015H AAH C106H AAH NOTE The page register is WRITE ONLY Reading P1 0 P1 3 may result in an ambiguous result Application Program Start Address The start address of the application program should be located at 1000H as the first 4kBytes are reserved for the SOC 4000 I system Revision B Page 16 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Serial Downloading In Circuit Programming Revision B As part of its embedded boot software the SOC 4000 facilitates serial code and data download via the standard UART serial port Serial download mode is automatically entered upon power up or reset if one of the following conditions exists e No valid program is programmed in the Flash memory e A request for download process was initiated via the UART during the first 200 ms after power up reset Once in this mode you can download code or data files into the Flash memory while the device is located in its target board The Cybra
26. 448 bits buffer registers Up to 448 bits shift registers Pin 45 PRN SlClock FIGURE 14 PRINTER INTERFACE BLOCK DIAGRAM Revision B Page 39 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Registers Description The Printer interface controller registers description is given in Table 15 TABLE asi INTERFACE CONTROLLER REGISTERS DESCRIPTION COMMAND ADDRESS BIT FUNCTION FUNCTION Controller Clock Enable C200H 0 Disable 1 Enable Covers e Lea bone Jmowwom bp Corr Regate oso Femme Semaphore Register The semaphore byte is located at address D801H The semaphore byte bit definitions are identical The settings are e Controller is Busy Bits 0 to 7 set to 1 FFH e Controller is Ready Bits 0 to 7 set to 0 00H Control Register The control register bit definitions and functions are given in Table 16 TABLE 16 PRINTER INTERFACE CONTROLLER CONTROL REGISTER BIT FUNCTIONS LSB 1 Positive Logic Sets the Data Rate i 5 SCH Ge 1 1 31 75 KHz 00001 208 bits 48 bits Revision B Page 40 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Data Registers Data length is variable between 25 bytes 200 bits and 56 bytes 448 bits according to the control register setting LO L4 The data register bit definitions are shown in Figure 28 The registers
27. B Page 87 August 2002 TEDEA HUNTLEIGH EXCELLENCE IN LOAD CELLS USA Tedea Huntleigh Incorporated 20630 Plummer Street Chatsworth California 91311 U S A Tel 1 818 701 2700 Fax 1 818 701 2799 Email sales tedea huntleigh com UK Tedea Huntleigh Europe Ltd 37 Portmanmoor Road Cardiff CF24 5HE United Kingdom Tel 44 0 29 20460231 Fax 44 0 29 20462173 Email sales tedea huntleigh co uk Taiwan Integrated Solutions Ltd Tel 886 2 2649 7254 Fax 886 2 2649 7253 CybraTech 1998 Ltd 5a Hazoran St PO Box 8381 Netanya 42506 ISRAEL Tel 972 9 8638832 Fax 972 9 8638822 Email info cybratech co il Website www cybratech com Document order number SOC 4000 0001 SP Germany Tedea Huntleigh GmbH Mimlingweg 18 D 64297 Darmstadt Eberstadt Germany Tel 49 6151 94460 Fax 49 6151 944640 France SEEA sa 16 Rue Francis Vovelle 28000 Chartres France Tel 33 2 37 33 31 20 Fax 33 2 37 33 31 29 CybraTech
28. CybraTech SOC 4000 i Scale On Chip ASIC Technical Specification August 2002 Document order number SOC 4000 0001 SP CybraTech SOC 4000 i Scale On Chip ASIC Technical Specification August 2002 Document order number SOC 4000 0001 SP CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification 2002 CybraTech 1998 Ltd All rights reserved CybraTech 1998 Ltd reserves the right to alter the equipment specifications and descriptions in this publication without prior notice No part of this publication shall be deemed to be part of any contract or warranty unless specifically incorporated by reference into such contract or warranty The information contained herein is merely descriptive in nature and does not constitute a binding offer for the sale of the product described herein CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE OF CONTENTS GENERA FYR NO IEEE TANA 1 GENERAL DESCRIPTION 2 4 2 2 2 0402 aan antenne han E AAA e 2 ADVANTAGES Rn in ERU EHE EROR E TRO Eee D EE Ee 2 SPECIFICATIONS ec 3 ANALOG TO DIGITAL CONVERTER ADC eene ener enne FD trennen rennen nnne nnne 3 A D Converter Main Channel Wheatstone Bridge Load Cell 3 A D Converter 3 A D 3 a A R 4 DIGITAL OUTPUE s E PE 4 EEASH MEMOR Y etti A a E dite een torpet Et pesi Ee ee 4 A rear reeves treet cet c
29. ISPLAY BLOCK DIAGRAM eene eene 35 LED VFD SERIAL INTERFACE CONTROLLER TIMING DIAOGRAM eene 36 PRINTER INTERFACE BLOCK DIAGRAM i 39 SERIAL HEAD TIMING DIAGRAM esee i 43 PRINTER STROBE STREICHER ata ee eege ege 45 AUXILIARY MOTOR AUXMOTOR PULSE STRETCHER PIN 29 i 46 PRINTER POWER VPP PULSE STRETCHER PIN 28 i 46 PRINTER MOTOR TIMING DIAGRAM i 51 OPTO SENSOR INTERFACE TO SOC 4000 52 END OFT ABEL DETECTOR eebe reete a he iaia sangen 53 PEEL OFF LABEL DETECTOR AUTO 53 EXAMPLE OF RESISTANCE TEMPERATURE VARIATION FOR THE THERMISTOR 54 THERMISTOR SENSOR tale 2 Seeders ele nete Rn ete petente desee e lie 55 CLOCK GENERATOR BLOCK DIAGRAM cere I emen nenne net nnne LL enne tenen n nnne seen 57 EOW VOLTAGE DETECTOR niit erectio rie 61 4 WIRE LOAD CELL CONNECTION 78 6 WIRE LOAD CELL CONNECTION nennen eene nee hne LLYR HYLL esee tear RA rentis seen tenes 78 MULTIPLE LOAD CELL LLY raene aei a E a E EAA A a a 79 KEYBOARD INTERFACE 55v eei Ze Nrct 82 SOC 4000 INTERFACE TO A LED VFD DISPLAY ee 83 LCD DISPLAY MODULE HARDWARE INTERFACE rennen enn etenn nnne 86 Page iv August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 TABLE 10 TABLE 11 TABLE 12 TABLE 13 TABLE 14 TABLE 15 TABLE 16
30. LLI ten nn nnne 87 REGISTERS ADDRESSES AND FUNCTION nee n nene n enne et LLI nin 87 Page v August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification GENERAL Features Scale On Chip System e Single Chip Printer Scale electronics e Full OIML R 76 compliance SOC 4000 3000 d SOC 40001 6000 d e Up to eight load cells e 6 wire load cell connection including Sense inputs Peripherals e Display Supports LCD LED and VFD LED Up to 24 digits VFD Up to 24 digits LCD Module 4 lines x 20 characters e Keyboard Up to 128 keys e Serial communication RS 232 485 e UO set points Up to 16 lines e Temperature sensor input Analog to Digital Converters e Resolution 20 bits e Sample Rate 5 10 20 samples sec e Programmable gain 0 5 0 75 1 1 5 2 CPU e Enhanced 80C51TBO e 4 cycles instruction e 512 KByte field programmable Flash program and data memory e Up to 512 KByte SRAM with battery backup support e 4KByte non volatile Data Flash Power e 5 3 3V operation 10mA e Power failure detector Applications e Price computing printer scales e Weighing indicators e Counting scales e Checkout scales LED Module 8 888 LCD Module VFD Module Exc Sig Load Cell ur SE SOC 4000 Sensors Printer x2 TX RX 4 7 RS 232 485 Head Motor gt 1 0 Buzzer Keyboard
31. OLLER sss ss sss ss sss eee eene eee sss soso osons 57 CONTROL REGISTERS D SCRIDTION ZRA LER n n nn n n nn n e e ERa He 58 OPERATION E 58 WATCHDOG TIMER LCS 59 CONTROL REGISTERS D SCRIDTION 2 n nnn n H aaaea ade 59 OPERATION Y YT re tito E 59 LOW VOLTAGE DETECTOR 0 61 POWER FAILURE INTERRUPT REGISTER se 61 CONFIGURATION REGISTERS 63 Revision B Page ii August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification SPECIAL FUNCTION REGISTERS SFR 67 GLOBAL CERCREGISTER uta a ell ala da 67 070 67 CONTROLLERS CLOCK ENABLE RpOoISTERS nono nana 67 CONTROLLERS RESET REGISTERS ie 69 VO OPERA TION E RTRT RTRT TRONTO TITTI RIN c 71 8051 COMPATIBLE ON CHIP 1 73 PARALLEL VO PORES u 22 ee ae ira 73 TIMErSICOUNIerSi 0 00 E 73 80C 4000 INITIALIZA TION REN 75 PERIPHERAL INTERFACE CONNECTIONS e ss sss eee sss sss s eta sae naonn annan anana naona ananas 77 LOAD CEEL INEEREACGE o EL E a id TT 4 Wire and 6 Wire 77 Load Cells Connected in Parallel 79 Lodd Cell Impedance eic ote esos ab ena ee eas Eda alari T e ort deem fs 80 SERIAL COMMUNICATION e e n n nnn nnne nnn nnn nnn n nnn n n nnn ener enn 80 RS 485 Serial Interface Transmit Receive Control 80 KEYBOARD INTERFACE augello Ee LARA ar 81 LED VFD SERIAL DISPLAY INTERFACE 83 EXTERNAL INTERRUPT SOURCES un se ov iex re int 83 Using the Vet
32. ON SOC 4000 i Scale On ChipM ASIC 0 6 N TLELELELELELELELELELELELELELELELELELELEL T P32 PIN 1 IDENTIFIER SOC4000 TTD VO DDD UU UU JULI UU UU LUI P33 P53 U N A ke on AR FIGURE 5 SOC 4000 PIN ARRANGEMENT Page 12 Technical Specification August 2002 CybraTech 2000 Ltd Revision B SOC 4000 i Scale On Chip ASIC K K K K K KOUTO P14 7 KIN2 P15 5 KIN1 P15 6 KINO P15 7 BUZZ P1 7 P1 5 P1 4 XTALOUT XTALIM TX RX TX2 P4 0 RS485 P4 1 RX2 Label Detect P3 4 Auto Detect P3 5 Paper detect P1 6 YPP 4 2 AuxMotor P4 3 Motori P5 0 Motor2 P5 1 Motor3 P5 2 e e N3 P15 4 N4 4 P15 3 NS P15 2 NG P15 1 NZ P15 0 Motor4 P6 0 34 Motors P6 1 rie ex DOO Jun fer on CX 100 00 109 35 36 Motore P6 2 Strobe1 P6 3 Strobe2 P7 0 Strobe3 P7 1 37 YDD 38 39 Strobe4 P7 2 KOUT1 P14 6 KOUT2 P 14 5 KOLIT3 P14 4 KOLIT4 P14 3 KOLITS P14 2 KOUT6 P14 1 SOC4000 Strobe5 P7 3 Strobe6 P8 0 Switch P18 Prn Latch 1 Prn SI Data P8 2 Prn SI Clk P8 3 40 41 42 43 44 45 46 KOUT P14 0 jo 00 100 KING P17 7 KINS P17 6 N10 P17 5 N11 P17 4 N12 P17 3 N13 P17 2 N14 P17 1 K K K K K KIN15 P17 0 AVCC SEN SIG1 SIG1 SEN AGND SIG2 SIG2 VDET GND RESET WCC LED SI Blank P13 3 LED SI Strobe P13 2 LED SI DATA P13
33. RESS BIT 7 BIT 2 BIT 1 BIT 0 LSB E100H Don t Care Tx Semaphore Rx Semaphore Controller to ADC Converter ADC Converter to Controller Revision B Page 23 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Control Register The control register bit definitions and its functions and are given in Table 5 page 24 TABLE 5 ADC CONTROLLER INTERFACE CONTROL REGISTER BIT FUNCTIONS BYTE ADDRESS FUNCTION SETTINGS E101H O Interrupt Enable 0 Disable LSB 1 Enable E102H Sample Rate 00 20 Hz default amp F S 100 000 Counts O 01 10 Hz amp F S 200 000 Counts LSB 10 10 Hz amp F S 100 000 Counts 11 5 Hz amp F S 200 000 Counts 000 0 50 001 0 75 010 1 00 Power Down 111 Power Down 5 ADC Channel 0 Main default channel 1 Secondary channel s porcas e Status Data Registers The data register bit definitions are shown in Table 6 The bit functions are described in Table 7 TABLE 6 ADC CONTROLLER INTERFACE DATA REGISTER BIT DEFINITIONS BYTE ADDRESS BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO LSB i pe or os o o se or oo feo ow ow oo on on oo o o pe s gt fo o o 0 cn ca Revision B Page 24 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 7 ADC CONTROLLER INTERFACE DATA REGISTER BIT FUNCTIONS ADC
34. ROLLER REGISTERS DESCRIPTION FUNCTION ADDRESS REMARKS Stretcher Clock C201H Enable Disable Stretcher operation Enable Register Reset Registers C407H to C40EH__ Reset Stretcher Trigger Registers E210H to E217H Trigger Stretcher operation Data Registers E200H to E20FH Pulse Length Register Strobe Clock Enable Control Register The clock register Command byte bit definitions and functions are given in Table 19 TABLE 19 STROBE CLOCK ENABLE CONTROL REGISTER BIT FUNCTIONS ADDRESS NAME SETTINGS 0 Auxmot LSB STROBE1 0 Disable STROBE2 1 Enable STROBE3 STROBE4 EX STROBE5 STROBE6 Revision B Page 47 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Trigger Registers TABLE 20 TRIGGER REGISTER DEFINITIONS STRETOHERNANE ADDRESS FUNCTION SETTINGS waer ENO Fees zess ver rer Mon E nog PP See es mostre Em G Mage TROBE TN STROBES reese E ager STROBES FFE Teer operation STROBES Hd grup Ene rnor STROBE es STROBES Hd grup E Feegeere Kee STROBES red ou O E Feuer FFE Tiger operation Data Registers The data register bit definitions are shown in Table 21 The registers are Write only TABLE 21 STRETCHER CONTROLLER DATA REGISTER BIT DEFINITIONS LSB Roma m 5 e eeu p cca i EEN E w emm u s s u o u u w emere em iw pum er un uo e me em a us i e 6 e e 9 teas
35. TO is normally used to interrupt the microprocessor so that data can be stored in non volatile memory before Vcc falls below 4 75 V and the RESET output goes low The Power Fail Comparator output returns to High when Vdet gt 2 27V Unregulated DC Vin Recommended Values SOC 4000 for R1 R2 Power Fail Comparator omparator 1 133K WE T 1 INTO is low 2 E400H Bit 17 0 Comparator Output 1 100 R i INTO AL 5 19V Typ INTO 47 5 3V Typ INTO goes low if Vdet 2 21V FIGURE 26 LOW VOLTAGE DETECTOR Power Failure Interrupt Register The address of the power supply interrupt register is E400H Read Write The bit settings at E400H that define the power failure interrupt and flag are given in Table 28 TABLE 28 POWER FAILURE INTERRUPT REGISTER BIT SETTINGS ADDRESS BIT BIT BIT BIT BIT BIT BIT 1 PFF BIT 0 LSB 7 6 5 4 3 2 POWER FAIL FLAG INTERRUPT ENABLE E400H Don t Care 0 If Voert gt VREF 0 Enabled 1 Normal 1 Disabled Operation 1 Enable INTO by setting BIT 0 0 2 After detecting INTO read the value of the PFF bit Power Fail Flag BIT 1 PFF 1 Normal ADC Interrupt PFF 0 Low Voltage Detected event Revision B Page 61 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification CONFIGURATION REGISTERS CFR Revision B Programming the CFR registers in the CPU sets the SOC 4000 pin fu
36. Tech Cloader executable is the PC serial download utility provided together with the device and its documentation and software library The SOC 4000 I may be programmed only if within 200ms after power up or RESET it established communication with the Cloader executable or if the application program is not available or not valid checksum error Figure 8 describe the startup procedure of the SOC 4000 Power Up Reset Start Programming mode Is the Application Program OK Start Application Program FIGURE 8 SOC 4000 I STARTUP PROCEDURE Page 17 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Using the Flash for Data Memory The Flash memory may be used for storing non volatile data To update the data area while the program is running the Flash must be defined as a DATA area and not as a CODE area CybraTech Flash Manager software manages this process in an efficient and reliable manner It provides the means to read write erase and update the Flash Data area A detailed description of the CybraTech Flash Manager function is included in the SOC 4000 Software Function Library user manual document number SOC 0000 SW01 OM FFFFH Flash Data MI Program Program Bank 1 Bank 2 Program 32K 32K Bank 15 32K 8000H 7FFFH Program Common Area 32K 10000 Bank 0 FFFH 4K Reserved by OOOOH Syst
37. UNCTION Connection Regulated BOX 5V 73 AVcc Output 72 SEN Trimming 71SIG Up to 8 Load Cells 70 SIG SOC 4000 Zero Offset 69 SEN Trimming AGND 68 AGND FIGURE 29 MULTIPLE LOAD CELL CONNECTION Revision B Page 79 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Load Cell Impedance Most load cells have output impedance of 350 ohms However in power restricted applications load cells of higher impedance typically a 1000 ohm bridge are used to reduce the cell s power consumption The SOC 4000 CMRR minimizes the error resulting from this high bridge impedance and ensures full and accurate performance under this limiting condition The result is economical power consumption without sacrificing weighing accuracy Serial Communication Channel Multiplexer The SOC 4000 supports two serial communication channels that are multiplexed to the embedded 80C31TBO controller UART Selection of the active serial channel is done via the control register at address C111H as defined in Table 38 TABLE 38 COMMUNICATION CHANNEL MULTIPLEXER CONTROL ADDRESS CONTROL ACTIVE COMMUNICATION SOC 4000 PIN REGISTER VALUE CHANNEL C111H o Te Rx Channel 1 20 21 Default 1 Re Channel 2 22 23 RS 485 Serial Interface Transmit Receive Control SOC 4000 supports managing the operation of an RS 485 driver transmit receive The control is implemented asserting p
38. are Write only The data is transmitted to the printer head serially in the following order a First byte data register D801H b In each data register the MSB Bit 7 is the first bit transmitted to the printer TABLE 17 PRINTER INTERFACE CONTROLLER DATA REGISTER BIT DEFINITIONS BYTE ADDRESS BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO LSB i omm 6 4 3 ow or es sa fe se si 3 oem or ee ss se we fo wo we 9e si T s wm or ee es 99e s omm or e es fm fo o 7 om ee ss fe ee 6 fo e mw or 9 wo s ow w w w w n w w w so me or ee os fo wo o ome o 9 fe si wo lu owe o wo s o o 9 9 wo o ome or ee es fo wo s ow or oe es se si wo se ow or e 9 fm se si wo Lo oem or me eT ow mm or fe es si o s wn or e 9 fm wo zo oss or e ss fm se wo ar om or e si wo m owe or ef si m os or e aa owe wo 9 se wo as owe or 9 fm wo ET I REA I WE so mm w w w w nu w w w Revision B Page 41 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Operation At powe
39. caution needed when changing the function of the pin TABLE 37 AVAILABLE PINS ON THE 80C51 I O PORT PIN 80C51 DEFAULT SPECIAL PRECAUTIONS PORT FUNCTION Buzzer Port 1 is used as the code memory page register Each port line should be handled bit wise without affecting P1 0 P1 3 None Port 1 is used as the code memory page register Each port line should be handled bit wise without affecting P1 0 P1 3 None Port 1 is used as the code memory page register Each port line should be handled bit wise without affecting P1 0 P1 3 P3 4 Label detect Timer 0 P3 5 Label removal Timer 1 detector P1 6 Paper detect Port 1 is used as the code memory page register Each port line should be handled bit wise without affecting P1 0 P1 3 The I O ports are controlled and accessible using the 80C51TBO Special Function Registers as described in its device specification Timers Counters The 80C51 Timers Counters external inputs are available for use on SOC 4000 pin 25 Timer 0 and pin 26 Timer 1 Using the timers is via the 80C51 Special Function Registers SFRs as described in the 80C51TBO specification Revision B Page 73 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification SOC 4000 INITIALIZATION Revision B On Power on Reset the SOC 4000 performs a self test and initializes all registers to 0 00H The GLOBAL register C100H is automatically set to
40. data to data registers at E103H to E106H After sending the data of registers E103H to E106H the ADC controller resets the Receive semaphore bit at E100H to Ready Bit 0 0 signaling the CPU that the controller can now receive new data One ADC controller operation cycle is now complete Steps 6 through 7 are repeated cyclically The ADC internal counts output is dependent upon the input signal the gain and the operation mode setting Table 5 defines the relation between the internal counts output of the zero signal input of the full scale signal and the ADC settings Revision B Page 26 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 8 ADC OUTPUT COUNTS Vs ADC SETTINGS GAIN SAMPLE ADC ADC OUTPUT AT MAXIMUM ADC OUTPUT RESOLUTION ZERO SIGNAL FULL SCALE cours MODE INPUT INPUT IN COUNTS COUNTS MILLI VOLTS 0 5 103 000 153 200 20 256 200 103 000 153 200 20 256 200 206 000 306 400 20 512 400 0 75 103 000 103 000 256 200 1 0 103 000 153 200 256 200 1 5 103 000 153 200 256 200 103 000 153 200 256 200 206 000 306 400 512 400 206 000 306 400 512 400 2 0 103 000 153 200 256 200 103 000 153 200 256 200 206 000 306 400 512 400 206 000 306 400 512 400 ADC Resolution mode is defined in Table 5 Register E102H bits 0 1 Sample Rate Revision B Page 27 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification
41. e 4 0 Disable 1 Enable STROBE5 read write Enable Strobe 5 0 Disable 1 Enable 7 STROBE6 read write Enable Strobe 6 0 Disable 1 Enable Page 68 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Controllers RESET Registers The SFRs listed in Table 34 provides the mechanism to reset the hardware controllers of the SOC 4000 1 TABLE 34 CONTROLLERS RESET REGISTER ADDRESS FUNCTION SETTINGS Write only Keyboard controller reset OxFF Reset Write only Serial LED display controller reset OxFF Reset Write only Printer controller reset OxFF Reset Write only Auxmot Stretcher reset OxFF Reset Write only VPP Stretcher reset OxFF Reset Write only STROBE1 Strobe reset OxFF Reset Write only STROBE2 Strobe reset OxFF Reset Write only STROBES Strobe reset OxFF Reset Write only STROBE4 Strobe reset OxFF Reset Write only STROBES Strobe reset OxFF Reset Write only STROBE5 Strobe reset OxFF Reset Write only ADC controller reset OxFF Reset Revision B Page 69 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification I O OPERATION VO operation is determined by the configuration registers CFRs The I O ports are composed of two groups 1 Byte Oriented Output Ports Data written to the port is byte oriented writing FFH to the port will set it to HIGH and writing 00H to the por
42. e interface with the module is shown in Figure 32 SOC 4000 LCD Module DBO DB7 RS Register Selection XX SOC 4000 Pin Number FIGURE 32 LCD DISPLAY MODULE HARDWARE INTERFACE The SOC 4000 signals and pin out are defined in Table 40 TABLE 40 SOC 4000 INTERFACE SIGNALS TO LCD DISPLAY MODULE SIGNAL NAME PIN NUMBER FUNCTION em banbmDremenssromaon CSLCD bo o Module select signal The LCD display module hardware interface is composed of 11 signals as described in Table 41 Notice that the SOC 4000 imposes several restriction on the module interface Revision B Page 86 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 41 LCD DISPLAY MODULE INTERFACE SIGNALS SIGNAL NAME NO OF I O FUNCTION SIGNALS DBO DB7 I O Tristate bidirectional data bus data is read from the module to the controller or writen to the module DB7 is the MSB DB7 is also used as a busy flag Operation start signal The signal activates data write or read Read Write selection signal Register selection signal Instruction register Write Busy flag and address counter Read Data register Write and Read Table 42 defines the registers addresses used to operate module and their function TABLE 42 REGISTERS ADDRESSES AND FUNCTION REGISTER ADDRESS READ WRITE FUNCTION F400H Write Instruction register F401H w write Data register Revision
43. ealed package If The packaging is damaged or has been removed perform the following drying procedure to assure that SOC 4000 components are completely dry e Components drying procedure Place the SOC 4000 components in their tray and put them into a baking oven to dry at a temperature of 105 C for a minimum of 6 hours 5 Reflow temperature profile should be set according to the paste parameters 6 Maximum reflow temperature should be less than 225 C 7 Recommended paste Koki AIM Multicore Type 3 NC RMA or equivalent 50 80 000000000000000990000 D0000000000000000000 0100000000000000000 Otel 000000000000000000000 1119 88 1210 1290 FIGURE 4 PCB BOARD LAYOUT Dimensions are in milli inches mil Revision B Page 7 August 2002 CybraTech 2000 Ltd PIN CONFIGURATION SOC 4000 i Scale On Chip ASIC Technical Specification Glossary of terms regarding SOC 4000 pin configuration are presented on page 12 The physical pin arrangement is shown in Figure 5 and Figure 6 page 12 KOUT4 KOUT3 KOUT2 KOUT1 KOUTO TABLE 1 SOC 4000 PIN CONFIGURATION FOR PRINTER DESCRIPTION Keyboard Controller output See Keyboard Controller page 29 ND FUNCTION 1 0 P14 3 1 0 P14 4 LO P14 5 1 0 P14 6 1 0 P14 7 DESCRIPTION VO See I O Operation on page 71 PULL UP RESISTOR VDD Digital Power Supply 3 3V
44. ee di op TTT 5 FREQUENCY SOURCE INPUT 5t bue ep Den teen ete eei eritis 5 POWER SUPPLY lt AND MONITO iioi donee a chads adi Sos ep DC Syd E dede aa oon ep ve EEN 5 ENVIRONMENTAL CONDITIONS we nei tp o trie ee AY EE EE 3 ABSOLUTE MAXIMUM RATING 6 DIMENSION Sonin naa a Reano sete RR ia lola iso 6 SCALE MAIN BOARD LAYOUT AND ASSEMBLY PROCESS PARAMETERS FOR SOC 4000 7 PIN CONFIGURATION roe M 9 CRU SOCSLT BO ec 15 MEMORY kiss aa Ta TL GWYLL AF GYF ibn ai 16 Organization e o dee ia rd ed pipe te deri 16 Program Memory Mapping ie eee ite c e RTT ERE Fete eee D eines 16 Program Memory Bank Select Register 16 Application Program Start Address 16 17 Using the Flash for Data Memory 18 Data Memory Mapping 4 d a rete d pee REALE A EGE 19 CPU SFRs and Configuration Registers 2 2 20 INSTRUCTION ETO ee us EEE dT YY Y FR fryn 20 RESETS dialer SY ed ad YD on YT a Y TG GYN A a 20 GORR 51 ER 20 ADC CONTROLLER INTERFACE icssesssssvassssssosseisensonsansvsncsesvsnssnsunsnesesecesssessaperssonnsnbvadsesbenssisevsonsssnss 23 CONTROLLER REGISTERS renes ege dal lla 23 Semaphore 23 Control Register iiia pee i tn iia 24 Status Data Registers cca A tuin atta ee e i led ere eta YF e re 24 Revision B Pagei August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification OPERATION una dia dd te 26 KEY BOARD CONTROLLER cssscicce
45. em FIGURE 9 SOC 4000 PROGRAM MEMORY MAP Revision B Page 18 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Data Memory Mapping The SOC 4000 data memory is stored in 3 areas a 256 bytes internal RAM mapped as IDATA b 4kByte RAM located at addresses 8000H 8FFFH This memory is mapped as XDATA memory and is used as the SOC 4000 working RAM and scratchpad memory c Upto 512kByte RAM with battery backup mapped at address range 0000H 7FFFH as XDATA memory mapped as 16 page of 32kByte each This area may be used as data area to store transactions PLUs and any other non volatile data required by the application RAM Bank Select Register CFR C113H bits 0 3 is the page register controlling the active RAM page To enable the C113H register set C104H C105H and C106H to AAH C104H AAH C015H AAH C106H AAH For SOC 4000 with 128kByte RAM only bits 0 1 are applicable bit 0 LSB For SOC 4000 with 512kByte RAM bits 0 3 are applicable bit 0 LSB Working RAM External RAM 7FFFH OH BANK 15 FIGURE 10 SOC 4000 DATA MEMORY MAP Revision B Page 19 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification CPU SFRs and Configuration Registers CFRs The CPU SFRs Special Function Registers are compatible with the 8051 instruction set Please refer to M8051TBO Technical Speci
46. erves as first address of the Write only data register The trigger for sending the data out to the display serial interface is programming the control register at address D200H As soon as the controller starts to send data it sets the semaphore byte to FFH indicating that it is busy When the controller has finished data output it resets the semaphore byte to 0 indicating that it is available for a new operation Revision B Page 36 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Control Register The definitions and functions of the control register Command byte bits are displayed in Table 13 TABLE 13 LED VFD SERIAL INTERFACE DISPLAY CONTROL REGISTER BIT FUNCTIONS ADDRESS NAME FUNCTION SETTINGS D200H Command bit 0 Command Only ES Command Data NA Don t Care a Sets the Blank polarity 0 Negative Logic 1 Positive Logic Strobe Polarity Sets the Strobe polarity 0 Negative Logic 1 Positive Logic 4 Clock Polarity Sets the Clock polarity 0 Negative Logic 1 Positive Logic 5 E Enables and disables the display 0 Disable Display 1 Enable Display Block Opens communication or blocks 0 Close communication the hardware communication lines 1 Open communication Semaphore Register The semaphore byte is located at address D201H which is the first address of the Write only data register This address is Read only for the semaphore byte The semap
47. f SOC 4000 based designs in order to achieve optimum performance from the Analog To Digital Converter Four layer boards are recommended where the outer layers are ground layers covering the whole surface and the inner layers are used for routing the signal lines The same ground plane should be used for both the digital and analog grounds Keep all ground connection as short as possible Make sure that the return paths of the signals are as close as possible to the paths that the currents took to reach their destinations Avoid digital signals flowing under the analog components area Wherever possible avoid large discontinuities in the ground plane since they force the return signals to travel on a longer path An example of correct implementation is routing all signals through the inner layers and keeping the outer layers for ground If you plans to connect fast logic signals rise fall time lt 5ns to any of the SOC 4000 digital inputs add a series resistor to each relevant line in order to keep rise and fall times longer than 5 ns at the SOC 4000 input pins A value of 100 Q or 200 Q is usually sufficient to prevent high speed signals from capacitive coupling into the SOC 4000 and affecting the accuracy of the ADC Revision B Page 85 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification LCD Display Module Interface The SOC 4000 supports direct connection of an LCD display module The hardwar
48. fications The CPU controls the peripherals and their operating modes through Configuration Registers CFRs The CFR registers for each peripheral are described in Table 29 page 64 Instruction Set Reset All instructions in the 8051 compatible SOC 4000 instruction set perform the same functions as in the 8051 They identically oversee bit and flag operations and other status functions Only the clock configuration differs For absolute timing of real time events the timing of software loops can be calculated However counter timers default to run at the older 12 clocks per increment In this way timer based events occur at the standard intervals with software executing at higher speed Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation In the SOC 4000 the MOVX instruction may take only two machine cycles or eight oscillator cycles while the MOV direct direct instruction uses three machine cycles or 12 oscillator cycles Thus the execution times of the two instructions differ This is because the SOC 4000 usually uses one instruction cycle for each instruction byte Note that a machine cycle requires just four clocks and provides one ALE pulse per cycle Many instructions require only one cycle but some require five The Reset signal is generated by an internal circuit in the ASIC The signal thresholds are e RESET falling edge on V 3 98v e RESET rising edge on V
49. g Operation The application software controls the watchdog operation It is automatically disabled in the Development System ICE mode and after power up or reset The application software should activate the watchdog as soon as it starts normal operation after power on or reset conditions The watchdog timer should be periodically re triggered during normal operation before the timer expires Expiration of the watchdog timer resets the CPU If required disable the watchdog by disabling the watchdog timer clock input Table 27 describes the operation of the watchdog timer TABLE 27 WATCHDOG TIMER COMMAND SEQUENCE COMMAND ADDRESS SETTING Retrigger Timer F800H mm Disable Watchdog C200H Revision 8 Page 59 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification LOW VOLTAGE DETECTOR The low voltage detector is a supervisory circuit in which the Power Fail Input V aet is compared to an internal 2 21 V reference Figure 26 The comparator output goes low when the voltage at Vay is less than or equal to 2 21 V and Bit 1 of register E400H equals 0 In order to enable this interrupt set CFR C10CH to IF Vae is usually driven by an external voltage divider which senses the unregulated DC input to the system 5V regulator The voltage divider ratio can be chosen such that the voltage at Va falls below 2 23 V several milliseconds before the 5V supply falls below 4 75V IN
50. hore byte bit definitions are identical The settings are e Controller is Busy Bits 0 to 7 set to 1 FFH e Controller is Ready Bits 0 to 7 set to 0 00H Data Registers The display data is stored in a 24 byte x 8 bit XDATA area The data register bit definitions for a 21 digit display are shown in Table 14 The registers are Write only Revision B Page 37 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 14 LED VFD SERIAL INTERFACE DISPLAY DATA REGISTER BIT DEFINITIONS SE BYTE ADDRESS BIT 7 BIT 6 BITS 4 BIT3 BIT2 BIT1 BITO 1 D201H EM oa po oe 9 f e d e b a BENE aaa A A A EA EEN Ep PE cgo ere EE s pes o fe 5 pe d E fe Se e fesa T9 s 9 to 16 D209H to D210H 17 to 24 D211H to D218H Operation At power on or reset the LED VFD Serial Interface display controller is disabled Initialization To enable the LED VFD Serial Interface display controller 1 Enable the controller clock source in Clock Enable register C200H Set C200H Bit 5 to 1 2 Reset the controller Write FF to register C403H 3 Check CFR address for LED VFD Serial Interface display controller function CFR address C101H AA Table 29 on page 64 This results in the following operations Enables serial controller output pins 58 to 61 Table 29 on page 64 Normal Operation
51. icating that 1t is busy When the controller has finished data output it resets the semaphore byte to 0 indicating that it is available for a new operation Revision B Page 42 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Printer Head Data Interface Operation The data is transmitted to the printer head using synchronous serial interface The SOC4000 hardware provides the PRN SI CLOCK Pin 45 and PRN SI Data Pin 44 signals After transmitting the data to the printer the printer driver asserts the Latch signal pin 43 to latch the data into the head registers When ready for printing the software printer driver should assert the Strobe signal s Strobel to Strobe6 pins 36 41 to enable the output of the data to the thermal dots The Serial out line and the Data Out lines are not used while operating with the SOC4000 printer driver Figure 15 describe the timing diagram for the serial head operation The timing requirements should be set according to the printer specification 1us lt t lt 32 768us Command Timing Diagram Command Stretcher ber Power Failure Block Diagram FIGURE 15 SERIAL HEAD TIMING DIAGRAM Revision B Page 43 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification STROBE CONTROLLER Features e Compromised of 8 signal lines e Programmable Pulse length 1 to 32 768 us e Positive or negative pulse polarit
52. ification Control Registers Description The clock frequency is programmed from a single 8 bit control register The address of the clock frequency control register is E800H The bit settings at E800H that define the clock frequency are given in Table 25 TABLE 25 CLOCK FREQUENCY CONTROL REGISTER BIT SETTINGS ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BITO CPU CLOCK LSB sso contese o peo wwe o fo fs eme contee H fs o ome contee H a ICI awe www i fo e ones HH fo m Operation At Power on or Reset the CPU frequency clock output is set to 16 MHz The clocks for the controllers is fixed and derived directly from the external frequency source The Frequency controller setting derives the CPU clock as defined in Table 25 Revision B Page 58 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification WATCHDOG TIMER Functions Functional Description e Monitor the correct operation of the CPU The operating parameters of the watchdog timer are presented in Table 26 TABLE 26 WATCHDOG TIMER OPERATING PARAMETERS PARAMETER VALUE Enable Disable By the control register ENWD Power Up Mode Disabled Control Registers Description Setting the Clock Enable register C200H bit 3 to 1 enables the watchdog timer Setting the Clock Enable register C200H bit 3 to 0 disables the watchdog timer Writing FFH to address F800H re triggers the watchdo
53. iled description in the M8051TBO Technical Specification Power Management section e Disable unused hardware controllers by disabling the controller clock via the Controllers Clock Enable Registers C200H C201H see Table 32 page 68 and Table 33 page 68 e Reduce the CPU frequency to minimum while idle by using the Frequency Controller The CPU frequency may be increased on the fly to 16MHz when an interrupt or an event occurred e Switch the power to the load cell using the I O pins of the SOC and an external switch Revision B Page 84 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification In Circuit Emulator ICE System The In Circuit Emulator ICE 3000 system provides full emulation of the SOC 4000 device It includes a plug in pod that replaces the SOC 4000 device thus enabling full emulation of the device in the target board It emulates the SOC 4000 device in real time simplifying the hardware software integration process The ICE 3000 is composed of 3 elements e DS 51 emulator e SOC 4000 Personality Probe e Windows based software debugger The system enables you to access all SOC 4000 device registers and memory locations and debug the application using free run or breakpoints and single step execution control Grounding and Board Layout Recommendations As with all high resolution data converters special attention must be paid to grounding and to the PCB layout o
54. inputs aisi RR ERR E Er e Re s 84 Using Timer0 and Timmer inputs coin 84 FO COMPATIBIE INTERFACE la ila 84 POWER SAVING SCHEMES 300 ilo aaa ica e dw i ee 84 IN CIRCUIT EMULATOR ICE SYSTEM 85 GROUNDING AND BOARD LAYOUT RECOMMENDATIONS 0 85 LCD DISPLAY MODULE INTERFACE nana 86 Revision B Page iii August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU FIGU Revision B RE l RE 2 RE 3 RE 4 RE 5 RE 6 RE 7 RE 8 RE 9 RE 10 RE ll RE 12 RE 13 RE 14 RE 15 RE 16 RE 17 RE 18 RE 19 RE 20 RE 21 RE 22 RE 23 RE 24 RE 25 RE 26 RE 27 RE 28 RE 29 RE 30 RE 31 RE 32 LIST OF FIGURES SOC 4000 TYPICAL APPLICATION asses 1 SOC 4000 MAXIMAL BLOCK DIAGRAM ii 2 MECHANICAL OUTLINE DRAWING vere 6 0 EA EAE EE E ATE 7 SOC 4000 PIN ARRANGEMENT s 12 SOC 4000 PIN CONFIGURATION oiin a n a a a a 13 CPU BLOCK DIAGRAM tria iaia a aa da iii hi 15 SOC 4000 I STARTUP PpoCRDURE 8 3 3 17 SOC 4000 PROGRAM MEMORY MAP emen Inrene enne n entes enne teres sete n sene etn ns ein 18 SOC 4000 DATA MEMORY Map 19 KEYBOARD MATRIX CONPIOGURATION i 30 LED VFD SERIAL INTERFACE D
55. l the clock source to the hardware controllers in the SOC 4000 I Each controller operation may be disabled by inhibiting its clock TABLE 31 C200H CLOCK ENABLE REGISTER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 n e Revision B Page 67 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 32 C200H CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS FUNCTION SETTINGS read write Enable LCD display controller clock 0 Disable 1 Enable read write None Always set to 0 Always 0 read write Enable keyboard controller clock 0 Disable 1 Enable read write Enable watch dog timer clock 0 Disable 1 Enable read write None Always set to 0 Always 0 read write Enables serial LED display controller 0 Disable 1 Enable Printer read write Enable Printer Controller 0 Disable 1 Enable Revision B read write Enables ADC controller clock 0 Disable 1 Enable TABLE 33 C201H CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS RE NAME TYPE FUNCTION SETTINGS Auxmot read write Enable Auxiliary Motor 0 Disable Stretcher 1 Enable read write Enable Power to the 0 Disable Printer Head 1 Enable HE read write Enable Strobe 1 0 Disable 1 Enable 3 STROBE2 read write Enable Strobe 2 0 Disable 1 Enable 4 STROBE3 read write Enable Strobe 3 O Disable 1 Enable 5 STROBE4 read write Enable Strob
56. nce Lam s pem o Revision 8 Page 5 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Absolute Maximum Rating peros he v Dinner 6 Pe E ss v Operaira empero 2 m __ Stage empero 20 __ Lead Temperature Manual soldering 300 C Soldering for 10 seconds Reflow soldering 225 C 60 seconds Dimensions The outline dimensions of the SOC 4000 case is shown in Figure 3 0 045 MES iL ELO dS 0 1 143 45 a D ELE EE EE EK EE E 11 Indicates relative locations of Pin 1 DT 1 150 29 20 1 158 29 41 lt Sq K 1 185 30 09 1 155 30 35 Sq FIGURE 3 MECHANICAL OUTLINE DRAWING Revision B Page 6 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Scale Main Board Layout And Assembly Process Parameters For SOC 4000 PCB Layout and Production Guidelines 1 Pad definition will be according to Figure 4 All dimensions are in milli inches mil 2 Solder mask opening should be 3mil total 6 mil 3 Board finish may be HAL hot air leveling immersion gold over nickel or immersion Assembly Guidelines 4 Verify that the SOC 4000 components are packaged in hermetically s
57. nctions The CFR registers include configuration registers that provide the interface between the CPU and the other on chip peripherals such as the keyboard LED VFD and LCD controllers and input output ports Each peripheral operates as designated in the CFR registers where each register may be programmed to perform alternative functions The complete CFR register bit configuration for all peripherals and input output and corresponding PLCC 84 pins are given in Table 29 Page 63 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 29 CFR BIT CONFIGURATION ALWAYS BIT 0 LSB C101H SI Serial Interface 7 6 10 io Printer Support 10 Printer Support Must be set to AAH 10 Printer Support Revision B Page 64 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification ve C107H SI Serial Interface 4 P CEE es T 2 Rr en LIC SW 10 Motor 6 OUT P6 2 P6 2 Cee NE es Dis Aux Motor 10 OUT P4 3 SE VPP 10 2 1 RS485 control OUT P4 1 i 10 OUT P4 0 nu C10DH 7 fo voPi87 t KINO KIN Keyboard In b peres ku Revision B Page 65 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification HEI ES A 0 u oo Fee Fan s kens kan P ken ker CC kee ku b kee km Glossary of Terms pr preme om io mou
58. nput Page 10 August 2002 CybraTech 2000 Ltd LED_SI_CLK LED_SI_Data LED_SI_ST LED_SI_BL DESCRIPTION LED VFD Serial Interface Display Module Clock Data Strobe and Blank See LED VFD Serial Display Controller page 47 SOC 4000 i Scale On Chip ASIC ND FUNCTION OUT 13 0 OUT 13 1 OUT 13 2 OUT 13 3 Technical Specification DESCRIPTION Output See I O Operation on page 71 PULL UP RESISTOR VCC Power Supply RESET Reset GND Digital Ground VDET INTO Power voltage detector input InterruptO Input SIG2 2nd channel input signal SIG2 2nd channel input signal AGND Analog Ground SEN Load cell Sense input SIG1 Load cell signal input SIG1 Load cell signal input SEN Load cell Sense input AVCC Analog power supply KIN15 KIN14 KIN13 KIN12 KIN11 KIN10 KIN9 KIN8 Keyboard Controller input See Keyboard Controller page 29 KOUT7 KOUT6 KOUTS Revision B Keyboard Controller Output See Keyboard Controller page 29 Page 11 1 0 See I O Operation on page 71 August 2002 CybraTech 2000 Ltd Revision B Glossary of Terms free 6 ki io kenger Ro jme P I 11 P1 P84 P75 MO
59. or to VCC This enables direct connection of the sensor to the input and saves external hardware components Simplified schematics of the opto sensor interface are shown in Figure 20 Revision B Page 51 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Depends on sensor specification FIGURE 20 OPTO SENSOR INTERFACE TO SOC 4000 Table 23 defines the supported sensors and switches TABLE 23 PRINTER SENSORS INTERFACE SENSOR NAME SOC 4000 PIN PORT ADDRESS Automatic Label removal Detector Auto Fo 5 CPU Paper detector P1 6 CPU Printer Head Switch P18 0 F229H To read a sensor input 1 Write 1 to the port address 2 Read Port value Revision B Page 52 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Implementing End Of Label detector End of label detector may be implemented by detecting the difference in the brightness of the reflected light from the label compared to the label backing paper Figure 21 describes a block diagram of such implementation Intensity Change Label Detector Pin 25 FIGURE 21 END OF LABEL DETECTOR Implementing Label peel off Detector This detector is a simple phototransistor located at the label exit Figure 22 describes the block diagram of the implementation Auto Ref Pin 26 M FIGURE 22 PEEL OFF LABEL DETECTOR AUTO Revi
60. ort P4 1 address F227H pin 23 to HIGH or LOW as required according to the function and the RS 485 driver used To operate the RS 485 1 Write 00H to F227H P4 1 sets the port to LOW 2 Write FFH to F227H P4 1 sets the port to HIGH Revision B Page 80 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Keyboard Interface Revision B The SOC 4000 supports direct connection of a keyboard of up to 128 keys arranged in an 8 x 16 matrix The hardware interface with an example of a scale keyboard is shown in Figure 30 The keyboard controller Keyboard Controller page 29 automatically scans the matrix by asserting a high signal on the output lines KOUT 0 to 7 and reading the input lines KIN 0 to 15 The key hardware code which is the code returned by the keyboard controller when the key is pressed is shown in Figure 11 page 30 The keyboard controller has a programmable anti bounce mechanism in which different delays can be programmed to avoid erroneous key activation due to bouncing of the keys The delay can be set to a discrete value from 4 to 18 milliseconds in two millisecond increments For programming the anti bounce mechanism see Table 10 page 31 To operate the keyboard 1 Initialize the CFR registers to support the required keyboard matrix See Table 29 page 64 Initialize the keyboard controller as described in Keyboard Controller page
61. r on or reset the Printer interface controller is disabled Initialization To enable the Printer interface controller 1 Enable the Printer interface controller clock source in Clock Enable register C200H Set C200H Bit6 1 2 Reset the Printer interface controller Write FF to register C405H 3 Check CFR address for Printer interface controller function CFR address C107H AA Table 29 page 64 This results in the following operations e Enables Printer interface controller output pins 41 43 44 45 Normal Operation 4 Check semaphore byte at address D801H page 40 If semaphore byte is Ready Bits 0 to 7 set to 0 write data to Data register addresses D801H to D838H page 41 5 Set Write command at Printer interface controller Control register address D800H page 40 6 Repeat steps 4 and 5 for new data The controller has one Read Write control register containing the Command byte and a Read only semaphore byte that informs the system if the printer is Busy or Ready to initiate writing of printer data The semaphore byte address also serves as first address of the Write only data register Data length is variable between 25 bytes 200 bits and 56 bytes 448 bits according to the control register setting LO L4 The trigger for sending the data out to the Printer interface is programming the control register at address D800H As soon as the controller starts to send data it sets the semaphore byte to 1 ind
62. s while using the same electronic hardware 4 Wire and 6 Wire Interfaces The SOC 4000 interface to the load cell carries the following electrical signals e SIG Signal Input e SIG Signal Input e SEN Excitation voltage Sense input e SEN Excitation voltage Sense input A typical 4 wire load cell connection in which the distance between the load cells and the SOC 4000 chip is small as in a standard retail scale is shown in Figure 27 However in platforms requiring long wires between the load cell and the electronic hardware such as weighing bridges the voltage drop over the cables is significant and affects accuracy The 6 wire interface eliminates this error factor by using the sense wires as shown in Figure 28 The sense wires serve as a reference for the A D converter thus eliminating the voltage drop over the long excitation voltage wires Revision B Page 77 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Load Cell Cable 4 Wires Unregulated Power I poe Regulated Reg 5V I I I I 73 AVcc I 72 SEN I 71 SIG t 70 SIG SOC 4000 I I i 69 SEN l i AGND 68 I I mm Revision B FIGURE 27 4 WIRE LOAD CELL CONNECTION Unregulated Power
63. sion B Page 53 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Connecting the Printer Head Thermistor to the SOC 4000 The thermistor is connected to channel 2 of the ADC using pins 66 and 67 of the SOC 4000 RESISTANCE TEMPERATURE VARIATION THERMISTOR 10000 1000 Rn 100KOhms 100 40 30 20 10 O 10 20 30 40 50 60 70 80 90 100 110 120 130 T C 25 C FIGURE 23 EXAMPLE OF RESISTANCE TEMPERATURE VARIATION FOR THE THERMISTOR Revision B Page 54 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification SIG2 66 SOC 4000 Printer Head 67 SIG2 FIGURE 24 THERMISTOR SENSOR The ADC channel 2 input is a differential input with a dynamic range of 0 0 8V The pull up and the pull down resistor values must be chosen accordingly to ensure that the Vth is always in range The voltage input to the ADC channel 2 will be Vth Cee R2 R1 Rth RI R1 Rth The ADC readings may be calculated by extrapolation according to Table 24 TABLE 24 ADC CHANNEL 2 OUTPUT RANGE ADC COUNTS Vth 0V 153 200 Vth 0 8V 254 000 Full Scale 100 800 Resolution According to the thermistor used temperature range R1 and R2 one may calculate or a look
64. sssiscessocssvceedesersesecscossousenncedesocovscoseseesseoes sevacescseevoesosdcnceedeseseedeoeceeenns 29 CONTROLLER REOISTERS ieri 31 REGISTERS DESCRIPTION cli deyd a dedd a aa 31 Control Register 2 02 a FD 31 Data Reorstenssgto 85 E S AUT ep A Be lle Sera 31 OPERATION cuarta td dt atado 32 LED VFD SERIAL INTERFACE DISPLAY CONTROLLER eesesessssooeseessssoooessessoooeoeessosocoeessssoooesse 35 REGISTERS DESGRIPTION RA YN are 36 GCORIFOLRESISIOEN ze cali TT 37 7 0 EE 37 Data Reeisters EE 37 OPERATION a e e bee EP e EE Ones 38 PRINTER SERIAL INTERFACE CONTROLLER es sss sss ee eee sss sss sss sss nns sese e teen nno 30 REGISTERS DESCRIPTION 2 2 u a er dE ee e EE 40 Semaphore Register rs isa a DDIG UN 40 40 Data Registers di A GERD GE Dei elia 4 OPERATION sani Rd ti 42 PRINTER HEAD DATA INTERFACE OPERATION 43 STROBE CONTROLLER 20 45 REGISTERIDESCRIP TON guana EA it 47 Strobe Clock Enable Control Register 47 7 48 RTE 48 OPERATION i ed Ym eon id a latina 50 PRINTER MOTOR AND SENSOR INTERFACE ccsssssssssccsssssssssccccssssssseccccssssssscccscsescsssscecsoees 51 PRINTER MOTOR OPERATION iaa dio 51 INTERFACING THE PRINTER OPTO SENSORS nono nn nana nana FL Fin 51 IMPLEMENTING END OF LABEL DETRCTOR see 53 IMPLEMENTING LABEL PEEL OFF DETECTOR anna anar 53 CONNECTING THE PRINTER HEAD THERMISTOR TO THE SOC 4000 54 PROGRAMMABLE FREQUENCY CONTR
65. t will set itto LOW 2 Bit Oriented Input Output I O Ports Data written to the port is byte oriented FFH to set the port 00H to reset the port Data read from the port is bit oriented only the port allocated bit is set reset The I O ports groups addresses and corresponding PLCC 84 pins are described in Table 35 and Table 36 TABLE 35 BIT ORIENTED I O PORTS ADDRESSES PIN AND BIT ASSIGNMENT a ow fm PPP PPP eo hoss Es KEKKKER e oss pm ebbe Bo oss Em Php 1 74 Revision B m lows i gt ER om fe KEE Page 71 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification TABLE 36 BYTE ORIENTED OUTPUT PORTS ADDRESSES AND PIN ASSIGNMENT e om Fee Revision B Page 72 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification 8051 COMPATIBLE ON CHIP PERIPHERALS This section describes the standard 8051 peripheral devices available to the user These functions are fully compatible with the standard 8051 CPUs and are controlled via the standard 8051 Special Function Registers SFRs Parallel I O Ports Some of the parallel I O ports of the 80C51TBO core are available on the SOC 4000 pins Most of the ports are already allocated to specific functions However the application design may require allocating different functions to these pins Table 37 list the available pins 80C51 I O port default function and special pre
66. tion NOTE When Control Register Address F101H bit 7 is set to 1 Released key code value bits 0 to 6 in address F101H are meaningless TABLE 11 KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS BYTE ADDRESS BIT 7 BIT 6 BIT 5 BIT4 BIT3 2 BIT 1 BIT O LSB 1 F100H x x x x X X X Key Error Flag 0 Legal 1 Error 2 F101H Release Sign D6 D5 D4 D3 D2 D1 DO 0 Pressed 1 Released Key Code Operation At power on the keyboard controller is reset and the scanning rate is set to 10 us Initialization To enable the keyboard controller 1 Enable the keyboard controller clock source in Clock Enable register C200H Set C200H Bit 2 to 1 2 Reset the keyboard controller Write FF to register C400H 3 Check CFR address for keyboard controller function CFR addresses C10DH C10EH C10FH FFH Table 29 page 64 This results in the following operations e Enables keyboard output pins 1 to 5 and 82 to 84 Table 29 page 64 Table 1 page 9 e Enables keyboard input pins 7 to 14 and 74 to 81 Table 29 page 64 Table 1 page 9 NOTE f less than 128 keys are required some of the pins may be allocated for I O operation See Table 29 CFR Bit Configuration page 64 and I O Operation page 71 4 Enable keyboard interrupt Set F100H Bit 3 to 0 5 Setanti bounce timeout Set F100H Bits 0 1 and 2 as shown in Table 10 Revision B Page 32 August 2002 CybraTech 2000 Ltd SOC 4000
67. up table the expected ADC readings at any temperature Revision B Page 55 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification PROGRAMMABLE FREQUENCY CONTROLLER Features e Programmable CPU clock frequency 16 8 4 2 1 or 0 5 MHz e Driven by a 16 MHz resonator or crystal oscillator Functions e Generates independent clocks for the CPU and controllers A D converter display keyboard watchdog timer etc Clock Generator Block Diagram The clock generator block diagram is presented in Figure 25 Functional Description Dividing the 16 MHz frequency source according to the control register setting generates the CPU clock frequency The CPU clock can be set to 16 8 4 2 1 or 0 5 MHz Switching CPU frequency e To switch from the 16 MHz frequency to any other frequency program the frequency controller control register as shown in Table 25 e To switch from any frequency other than 16 MHz to another frequency first switch to 16 MHz and then switch to the desired frequency 16 MHz 16 MHz Default gt Clock 8 MHz gt 1 2 4 MHz 2 MHz 1 2 1 MHz gt 1 2 0 5 MHz gt FIGURE 25 CLOCK GENERATOR BLOCK DIAGRAM Revision B Page 57 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Spec
68. y Functional Description e Printer Head Strobe OE Stretcher Pins 36 41 enable segmentation of the printer head into groups of dots up to 6 to limit current peaks e Auxiliary Motor Pulse Stretcher AUXMOTOR Pin 29 controlling the auxiliary motor operation label printing e Printer Power Stretcher VPP Pin 28 control the printer head power 1us lt t lt 16 384us Command Timing Diagram Command __ Stretcher a STB1 6 B STB Block Diagram Polarity FIGURE 16 PRINTER STROBE STRETCHER Revision B Page 45 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification gt 1us lt t lt 32 768s U Command Timing Diagram Command Stretcher AUXIMOT Block Diagram FIGURE 17 AUXILIARY MOTOR AUXMOTOR PULSE STRETCHER PIN 29 t 1us lt t lt 32 768s Timing Diagram Command Stretcher and ber Power Failure Block Diagram FIGURE 18 PRINTER POWER VPP PULSE STRETCHER PIN 28 Revision B Page 46 August 2002 CybraTech 2000 Ltd SOC 4000 i Scale On Chip ASIC Technical Specification Register Description The Stretcher controller registers description is given in Table 18 TABLE 18 STRETCHER CONT

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