Technical Information Manual
Contents
1. 8 2 1 8 22 POWER REQUIREMENTS 8 23 FRONI PANEL DISPLAYS n ane vane rosae Die ye e DREVER 8 24 JERONTPANHEE S qua us um au kan se asus 9 2 5 MOTHERBOARD 10 26 62 VENTE TERR TEE CEN uay usis 10 2 7 MEZZANINE BOARDS INSTALLATION nn nnns 11 2 8 FRONT PANEL CONNECTOR 11 3 OPERATING 13 UE ND 13 3 1 1 ALUNEIUTA RE 13 3 1 2 VOLTA AREE TASTE 14 32 FPGA PROGRAMMING gx sy kasa a aus shayaw kaqpas shu 15 3 2 1 FPGA au usa iha 15 3 2 2 FPGA USER una uuu c 16 4 17 4l REGISTER ADDRESS MAP u eerte ash 17 4 1 1 Configuration ROM sunum2. rom ooo lt r 2 rom oogc cr 2 GO G1 nou lt r GENERAL PURPOSE VME BOARD 2 1 Model V1495 front panel with 395 piggy back boards NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 9 CAEN ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 2 5 Motherboard Specifications The Mod V1495 Motherboard is composed by four I O sections see 1 2 described in the following table Table 2 2 V1495 Motherboard I O sections Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 1100hm Rt Robinson Nugent P50E A B 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34 34 pins input range 4 to 5V Fail Safe input feature LVDS Robinson Nugent P50E 32 Output Direct 068 P1 SR1 TG type 100ohm RI 250MHz 84434 pins TTL IN Direct NIM TTL OUT Direct selectable selectable NIM IN Invert 50 Rt NIM OUT Direct selectable 250MHz LEMO 00 2 6 Mezzanine Specifications The five I O Mezzanine
3. intent ennt 10 TABLE 2 3 V 1495 MEZZANINE BOARDS eee S S Q neo ge aevo 10 TABLE 4 1 ADDRESS MAP FOR THE MODEL V1495 17 TABLE 4 2 ROM ADDRESS MAP FOR THE MODEL V1495 nennen nennen en nennen terreni 17 TABLE 5 1 COIN REFERENCE SIGNALS e n eese 23 TABLE 5 2 V1495 MEZZANINE EXPANSION PORTS SIGNALS ener tenente 26 TABLE 5 3 PDL CONFIGURATION INTERFACE SIGNALS 26 TABLE 5 4 DELAY LINES AND OSCILLATORS tenentes 27 TABLE 5 5 SPARE INTERFACE SIGNALS cssccessssesceeessevcocecsssevencesssssncosecsssesencessssancceecsssevencessssancosesensssensessaes 27 TABLE 5 6 LED INTERFACE SIGNALS 12 rre LS PER Ye OE sd PELO SS RE RES CERE SEP eR EE ege 27 TABLE 5 7 COIN REFERENCE REGISTER MAP 29 TABLE 5 8 SELECTION OF THE DELAY LINE tese tnnt et restent enne 32 NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 5 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 1 General description 1 1 Overview The Mod
4. NS on apa laa SRC v1495ust_demo v1495usr_demo vhd SSS in Cyclone 11 FPGAs gg SRC v1495hal v1 halvam y LJ Software Files Fig 5 14 Quartus II compiler launching Quartus at this point launches in sequence the steps of the flow chart synthesis fitting place amp route then shows the correct compiling and the following screen Quartus C V1495 USER DEMO v1495usr demo v1495usr demo Compilation Report Flow Summary File Edit View Project Assignments Processing Tools Window Help S o essem G yor oO Project Navigator Entity Cyclone EP1C4AF400C6 2 2191 b Compilation Report Flow Su Logic Cells LC Registers Mer Compilation Report Legal Notice Flow summary EB Flow settings EB Flow Non Defaul Global Settir EB Flow Elapsed Time amp B FlowLog Analysis amp Synthesis Fitter Flow Status Successful Mon May 15 10 15 55 2006 cial Quartus Il Version 6 0 Build 178 04 27 2006 SJ Web Edition adr oad Revision Name vi495usr demo Toplevel Entity Name 149 demo Family Cyclone Device EP1C4F400C6 Timing Models Final Met timing requirements Yes Total logic elements 879 4 000 22 Total pins 275 301 91 Total vittual pins 0 Total memory bits 0 78 336 0 Total PLLs 0 2 0 Full Compilation _ Analysis amp Synthesis
5. SEES 34 FIG 5 5 a aae e a ee aae ae aie S i Ea 34 FIG 5 6 DELAY UNIT WITH DEOS L Il a ESEE OE EEEE 36 FIG 5 7 DEOS DELAY LINE TIMING gieste 36 FiG 5 8 QUARTUS II PROJECT 37 FIG 5 9 QUARTUS II MAIN 000000 ns sn renee 38 FIG 5 10 QUARTUS IL FILE MENU 38 FIG 5 11 QUARTUS II PROJECT cab ree sab dese dab ea dena Eaa aea do 39 FIG 5 12 QUARTUS IENETLIST ee avers hee anaes etate ee e pis a 40 FIG 5 13 QUARTUS II HIERARCHICAL STRUCTURE I 40 FIG 5 14 QUARTUS II COMPILER LAUNCHING 22 41 FIG 5 15 QUARTUS II COMPILING SUMMARY 2 4442 aa innen enne 41 LIST OF TABLES TABLE 1 1 AVAILABLE ITEMS Sana eene eene entente entente et teniente sites enne eate seen nest tnnt 6 TABLE 2 1 MODEL 1495 AND MEZZANINE BOARDS POWER REQUIREMENTS enne 8 TABLE 2 2 V1495 MOTHERBOARD I O SECTIONS
6. re Assembler Timing Analyzer ES Info Quartus II Timing Analyzer was successful D errors 4 warnings 4 Info Quartus II Full Compilation was successful 0 errors 13 warnings lt Processing Estra Info Into Message Dot 688 Location 1 For Help press F1 msa sj ide 0 sages Fig 5 15 Quartus II compiling summary At this point an updated RBF file is generated in the project directory This file can be used for updating the firmware as described in S 5 7 Filename Number of pages Page 00117 04 1495 MUTx 08 V1495_REV8 DOC 42 41 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 5 7 Firmware upgrade It is possible to upgrade the board firmware via VME by writing the Flash for this purpose download the software package and the CVUpgrade tool both available at http www caen it nuclear software_download php The instructions are explained by the README text file included in the CVUpgrade folder NPO Filename 00117 04 V1495 MUTx 08 Number of pages Page V1495_REV8 DOC 42 42
7. a aS aa 17 42 CONTROL REGISTER csiis ananas inana e iei aE iN rei e ES 18 4 3 STATUS REGISTER eter TREE REL EE Sa aS as qa REA SEEN ERE 18 4 4 INTERRUPT LEVEL REGISTER n nennen nnne nnn n nn 18 4 5 INTERRUPT STATUS ID REGISTER a 19 4 6 GEO ADDRESS REGISTER etr eH uD uuu a Sun uuu Sas 19 4 7 MODULE RESET REGISTER nenne nne e n n e e e 19 4 8 FIRMWARE REVISION 19 4 9 SCRATOHI6EEBGISTER 20 4 10 SCRA TCH32 REGISTER 2 20 4 11 SELECT VME FPGA FLASH 20 4 12 SELECT USER FPGA FLASH REGISTER 0000 20 4 13 VME FPGA FLASH MEMORY 20 NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 3 CAEN ls for Discovery Document type Tit
8. L IL Indy lt COUNT 2 COUNT 0 COUNT 1 COUNT 2 Fig 3 2 Gate pulse example FPGA USER drives a STARTx pulse and after Ten time FPGA USER will receive a PULSEx clock signal A counter with clock PULSEx implemented in the FPGA USER allows to generate a pulse with programmable duration It is possible to reduce to one half 5 5 the counter step by advancing the counter both sides of PULSEx Since the circuit is completely digital no recovery time is necessary between one stop and the following start it is thus possible to generate multiple gate pulses with very high rate Timer2 and Timer3 can be used together for handling one single Gate pulse from multiple overlapped triggers NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 14 Tools for Discovery Document type Title Revision date User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 3 2 ISTART 2 Coo T L LT LJ Ls COUNT 2 COUNT 0 COUNT 1 COUNT 2 ISTART 3 PULSE 3 COUNT 3 COUNT 0 COUNT 1 COUNT 2 GATE Fig 3 3 Timer2 and Timer3 used together for handling a Gate pulse FPGA Programming The programming of FPGA VME and FPGA USER are handled by two independent microcontrollers flash memory The updating of the firmware contained in the flash memories does not require the use of external tools and can be executed via VME The flash related to FPGA VME contains the fi
9. FLASH USER FPGA Asyn Timers 4 Fig 1 1 Mod V1495 Block Diagram NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 7 CAEN Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 2 Technical specifications 2 1 Packaging The module is housed in a 6U high 1U wide VME unit The board is provided the VME P1 and P2 connectors and fits into both VME standard and V430 backplanes 2 2 Power requirements The power requirements of the modules are as follows Table 2 1 Model V1495 and mezzanine boards power requirements Power supply 1495 A395A A395B A395C 950 A395E 5 V 1A 0 1A 0 1A 14 11 0 3A 2 3 Front panel displays The front panel refer to 2 4 hosts the following LEDs DTACK Colour green Function it lights up green whenever a VME read write access to the board is performed USER Colour green orange red Function programmable NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 8 CAEN Is for Discover Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 2 4 Front Panel Mod V1495 USER DTACK
10. Gate whenever an input signal Trigger occurs Gates can be produced in several ways according to the system set up which can be either synchronous or asynchronous Synchronous systems Input signals are referred to a system clock they can be sampled by the clock itself and the output is a gate signal obtained with a counter whose width and delay is a multiple of the clock period If the application requires a width and delay of the Gate signal synchronous but with step resolution higher than the system clock period this can be achieved by enabling the PLL in the USER FPGA and enter the reference clock on channel GO Asynchronous systems Input signals are not referred to a system clock As a consequence the gate signal will be generated without any time reference It is possible to use the implementation described above with the freedom of choosing the clock source between external or 40MHz internal The resulting Gate signal will have stable duration but with maximum position jitter equal to one clock period Such position jitter can be rejected by using the asynchronous timers present on the V1495 which allow to generate references synchronous with the occurred trigger 3 1 1 0 Timer1 NPO Each timer is based on a programmable delay line FRGA USER drives a STARTx pulse and after the programmed delay it receives the return signal PULSEx The time difference between transmission and reception logic impleme
11. without external hardware tools without disconnecting the board from the set up without resetting it or turning the crate off allowing quick debug operations by the developer with his own firmware A flash memory on the board can store the different programming file which can be loaded to the FPGA User at any moment Four independent digital programmable asynchronous timers are available for Gate Trigger applications It is possible to chain them for generating complex Gate Trigger pulse Table 1 1 Available items Code Description WV1495XAAAAA V1495 General Purpose VME Board WA395XAAAAAA 9 32 LVDS ECL PECL input channels WA395XBAAAAA A395B 32 LVDS output channels WA395XCAAAAA A395C 32 ECL output channels WA395XDAAAAA A395D 8 NIM TTL input output channels WA395XEAAAAA A395E 8 channel 16Bit x5V DAC WPERS0149501 V1495 Customization 3 A395C Mounting Option WA967XAAAAAA A967 32 Channel Cable Adapter 1x32 to 2x16 WFW1495SCXAA FW1495SC 128 Channels Latching Scaler for V1495 NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 6 CAEN ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 1 2 Block Diagram BRIDGE lt gt interface lt 8 bit USER PROGRAMMABLE FPGA FW LOADING optional Y LPT
12. MUTx 08 V1495 REV8 DOC 42 35 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 5 6 NPO Fig 5 6 Delay Unit with DLOs COINC DLOx_GATE 1 0 DLOx_OUT I LI LI LI 1 PULSE STARTDELAY DELAY COUNTER XY 1 2 3 40 STOPDELAY PULSE_OUT Fig 5 7 DLOs Delay line timing When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY enables the oscillator on external delay line DLOx selected via MODE register At the same time the DELAY_COUNTER is enabled The PULSE signal leading edge increases the counter until the value set via GATEWIDTH register is reached The PULSE signal corresponds in this reference with the selected PDL output On the first PULSE leading edge after the coincidence PULSE OUT is activated high and is kept high until a time GATEWIDTH times the period of the selected DLO The period in this case is constant The maximum pulse width is limited by the GATEWIDTH counter in the case of this reference design the GATEWIDTH register is 16 bit wide so a maximum width of 65536 Td Td is the intrinsic delay of the selected DLO Quartus II Web Edition Project The freely available Altera Quartus II it can be downloaded from the Altera Web site software must be used in order to generate a
13. Quartus II netlist The first time the project is launched the hierarchy includes only the name of the head of the project v1495usr demo At the end of the project flow the whole hierarchical structure of the project is shown Quartus C V1495 USER DEMO v1495usr demo v1495usr demo File Edit View Project Assignments Processing Tools Window amp Bam e Project Navigator n y O amp Cyclone EPIC4F400C6 vi495usr demo xl Fig 5 13 Quartus II hierarchical structure NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 40 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 NPO In order to generate a new programmation file it is necessary to launch the compiler by clicking on the red play button on the tool bar Quartus C V1495 USER DEMO v1495usr demo v1495usr demo File Edit View Project Assignments Processing Tools Window Help 5 demo dx SVE gt Project Navigator x Files Device Design Filed rap Pew SRC vI49Bust demo v1495usr pkg vhd Howntoat Ahac II SRE v1495usr_democoin_relerence yhd Ihe NEw i SAC v1495ustdemo spare_it_ttl vhd 01 SRC y1495ust_demo tistate_if_tttvhd
14. REGISTER DETAILED 31 5 5 1 V1495 Front Panel Ports Registers PORT A B C G a 31 5 5 2 V1495 Mezzanine Expansion Ports Registers PORT D E F 32 5 5 3 Delay 32 5 5 4 PDL DELAY VALUE SETTING AND 33 5 5 5 pe 34 5 5 6 Delay Unit using 35 5 6 QUARTUS WEB EDITION PROJECT 36 Dis 225522556 42 LIST OF FIGURES FIG 1 1 1495 BLOCK DIAGRAM FIG 2 1 MODEL 1495 FRONT PANEL WITH A395A B C PIGGY BACK BOARDS 9 FIG 2 2 MULTIPIN CONNECTOR PIN ASSIGNMENT err errre r rre 11 FIG 2 3 MOD A967 CABLE ese ese ese ese ese ase ese e ese e sees etes eset etes stesse 12 FIG 3 1 TIMERS DIAGRAM 14 FIG 3 2 Eie pee eH EC ya E ELE eee 14 FIG 3 3 TIMER2 AND TIMER3 USED TOGETHER FOR HANDLING GATE PULSE aa 15 FIG 3 4 FPGA
15. Standard image default IMAGE_SELECT Fig 4 5 USER FPGA Configuration Register Filename Number of pages Page V1495_REV8 DOC 42 21 CAEN Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 5 V1495 USER FPGA Reference Design Kit 5 1 Introduction The CAEN V1495 board provides a user customizable FPGA called USER FPGA The COIN REFERENCE reference design illustrates how to use the USER FPGA to implement a Coincidence Unit amp I O Register Unit This design can be customised by the user in order to adapt its functionality to his own needs ON BOARD DELAY LINES HARDWARE ABSTRACTION LAYER MEZZANINE CARD ON SLOT D MEZZANINE CARD ON SLOT N V E USER DEFINED LOGIC CAEN LOCAL BUS MEZZANINE CARD ON SLOT F L Port A 32 IN ECL LVDS Port B 32 IN ECL LVDS Port C 32 OUT LVDS Fig 5 1 USER FPGA block diagram 5 2 Design Kit 5 2 1 V1495HAL The V1495 Hardware Abstraction Layer V1495HAL is a HDL module provided in Verilog format at netlist level in order to help the hardware interfacing NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42
16. V1495 is a VME 6U board 1U wide suitable for various digital Gate Trigger Translate Buffer Test applications which can be directly customised by the User and whose management is handled by two FPGA s FPGA Bridge which is used for the VME interface and for the connection between the VME interface and the 2nd FPGA FPGA User through a proprietary local bus FPGA Bridge manages also the programming via VME of the FPGA User FPGA User which manages the front panel I O channels FPGA User is provided with a basic firmware which allows to perform coincidence matrix I O register and asynchronous timers functions FPGA User be also free reprogrammed by the user with own custom logic function see 5 1 It is connected as slave to the FPGA Bridge via CAEN Local Bus whose protocol shall be used in order to communicate with the FPGA Bridge and thus with the VME bus The I O channel digital interface is composed by four sections A B C G placed on the motherboard see 1 2 The channel interface can be expanded in the D E F sections by using up to 3 mezzanine boards see 2 6 and 2 7 which can be added choosing between the five types developed in order to cover the I O functions and the ECL PECL LVDS NIM TTL signals and 16bit DAC see 1 2 The maximum number of channels can be expanded up to 194 The FPGA User can be programmed on the fly directly via VME
17. necessary in order to install three A395C mezzanine boards on the V1495 see table 1 1 2 8 Front panel connector cabling Motherboard I O sections A B C and A395A A395B and A395C Mezzanine boards feature the Robinson Nugent P50E 068 P1 SR1 TG multipin connector whose pin set is shown in the following figure N C N C N C N C CH31 CH15 CH31 CH15 CH30 CH14 CH304 CH14 CH17 1 CH17 CH1 CH16 CH16 Fig 2 2 Multipin connector pin assignment Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 11 42 CAEN ls for Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 The CAEN Mod A967 Cable Adapter allows to adapt each Robinson Nugent Multipin Connector into two 1 17 17 pin Header type male connectors 3M 4634 7301 with locks through two 25 cm long flat cables CH17 CH16 00000000000000000 0099096927010 CICI DIECTCICICI LJ Fig 2 3 Mod A967 Cable Adapter NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 12 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 3 Operating modes 3 1 Timers Gate Trigger applications require the production of an output signal with programmable width
18. register allows USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 4 13 VME FPGA Flash Memory Base Address 0x8010 read write D16 This register allows the VME FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 4 14 USER FPGA Flash Memory Base Address 0x8014 read write D16 This register allows the USER FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 NPO Filename 00117 04 V1495 MUTx 08 Number of pages Page V1495_REV8 DOC 42 20 NPO 00117 04 V1495 MUTx 08 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 4 15 USER FPGA Configuration Register Base Address 0x8016 read write D16 This register allows the update of the USER FPGA configuration A write access to this register generates a configuration reload The configuration image Standard will be uploaded into the USER FPGA as the IMAGE_SELECT bit is set to 1 IMAGE SELECT 1
19. user firmware for the USER FPGA It includes the source of VHDL reference design which can be modified according to the decription provided with the manual in order to modify the card functionalities The tool provides a complete pinout of the FPGA it is also enabled to generate the file type of programming RBF format used fot the flash programming This software tool requires the Quartus Il Web Edition rel 5 1 and newer and can be freely downloaded at http www caen it nuclear software_download php Quartus manual is available at www altera com literature hb qts The following figure shows the typical project flow for generating the firmware for an ALTERA FPGA through the following steps Design Entry is the functional descritption of the circuit it could be either a description of the hardware VHDL Verilog AHDL or a scheme made with the tool provide by Quartus The reference design provided is developed through VHDL a VHDL knowledge is required in order to modify this design A different description can be developed with a different language among those allowed by the Quartus tool Syntesis translates the descritpion into a format compatible with the subsequent place amp route step Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 36 CAEN Tools for Discover Document type User s Manual MUT Place amp route starting from the netlist performs the placing place and the subseque
20. 22 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 5 2 2 COIN_REFERENCE Design COIN REFERENCE design VHDL entity is the interface to the V1495HAL If the User wishes to use V1495HAL to develop his own application on the V1495 platform the VHDL entity must not be modified this means that signals names and function of the COIN_REFERENCE entity must be used as shown in the following table Table 5 1 COIN REFERENCE signals PORT NAME DIRECTION WIDTH DESCRIPTION GLOBAL SIGNALS NLBRES IN 1 Async Reset active low LCLK IN 1 Local Bus Clock 40 MHz REGISTER INTERFACE REG_WREN IN 1 Write pulse active high REG_RDEN IN 1 Read pulse active high REG_ADDR IN 16 Register address REG_DIN IN 16 Data from CAEN Local Bus REG_DOUT OUT 16 Data to CAEN Local Bus USR_ACCESS IN 1 Current register access is at user address space Active high V1495 Front Panel Ports PORT A B C G INTERFACE A_DIN IN 32 In A 32 x LVDS ECL B_DIN IN 32 In B 32 x LVDS ECL C_DOUT OUT 32 Out C 32 x LVDS G_LEV OUT 1 Output Level Select 0 gt TTL 1 gt NIM G_DIR OUT 1 Output Enable 0 gt 1 gt Input G_DOUT OUT 2 Out G LEMO 2 x NIM TTL G_DIN IN 2 In G LEMO 2 x NIM TTL V1495 Mezzanine Expansion Ports PORT D E F INTERFACE D_IDCODE IN 3 D slot mezzanine Identif
21. DENCE TOROS PORT LOGIC COINC DOUT 0 PULSE OUT DELAY DOUT 1 DELAY SEL UNIT 0 READ ONLY REG PULSE_MODE GATEWIDTH 1 WRITE ONLY PDLO PDL1 DLOO DLO1 Fig 5 2 Front Panel Ports Interface Diagram NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 28 CAEN Tools for Disco Document type User s Manual MUT very Title Mod V 1495 General Purpose VME Board Revision date Revision 12 02 2010 8 The following table illustrates the the register map of the USER FPGA reference design COIN_REFERENCE Table 5 7 COIN_REFERENCE register map NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT 0x0000 A_STATUS_L D16 A_STATUS_H 0x0002 D16 B_STATUS_L 0x0004 D16 STATUS H 0x0006 D16 C STATUS L 0x0008 D16 C STATUS H 0x000A D16 D16 D16 D16 D16 D16 D16 16 A MASK H 0 000 L 0 0010 MASK 0x0012 C_MASK_L 0x0014 di D T EG Filename V1495 REV8 DOC i WO WO NPO 00117 04 V 1495 MUTx 08 Port A status This register reflects A 15 0 bit status Port A status This register reflects A 31 16 bit status Port B status This register reflects B 15 0 bit status Port B status This register reflects B 31 16 bit status Port C status This register reflects C 15 0 bit status Port C status This register reflects C 31 16 bit status Port A mask This regist
22. R 0 C A AND B MODE 5 PULSE_MODE See Description SCRATCH 0x0020 D16 RW This register is available to test 5 5 read and write to a register G CONTROL 0x0022 D16 w Only Bit 0 G CONTROL 0 is X 0000 used in this reference design It can be used to select G output level 0 TTL T NIM NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 30 CAEN ols for Disci Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 eosar owo pe jme fon os _______ _ REVISION 0x003C Firmware revision For example X XXYY the register conent for release 1 0 is X 0100 PDL CONTROL 0x003E It allows to either set the PDL 70001 delay though either on board Default PDL switches or via VMEbus delay is set by on board dip switches PDL DATA 0x0040 ID Code is 70007 E IDCODE 0x0044 F IDCODE 0x0046 5 5 REGISTER DETAILED DESCRIPTION mezzanine is plugged ID Code is 0007 D IDCODE 0x0042 i ID Code is 0007 mezzanine is plugged mezzanine is plugged 5 5 1 V1495 Front Panel Ports Registers PORT A B C G The Front Panel ports A B C G can be configured and accessed using a set of registers The x MASK y x can be y can be L or H registers can be used to selectively mask
23. RE_DIR OUT 1 SPARE Direction 5 3 8 LED Interface These signals when active for one clock cycle allow to generate a blink of the relevant Led Table 5 6 LED Interface signals RED_PULSE OUT 1 RED Led Pulse active high GREEN_PULSE OUT 1 GREEN Led Pulse active high 5 4 Reference design description The reference design preloaded into the USER FPGA is given as a design guide It is a full functional application of the usage of the board as a concidence and or I O register unit This reference design give access to A B C G ports So no mezzanine expansion cards are needed in order to use this design The MODE register can be used to set the preferred operating mode When the board is switched on the default operating mode is I O Register mode NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 27 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 In Register Mode C port is directly driven by the C CONTROL register The coincidence is anyway still active so that a pulse in generated on G port when a coincidence event is detected In Coincidence Mode the C port is used to report the coincidence operator on A and B port In this case the port can be masked through a mask register A gate pulse is generated on G port when data patterns on input ports A and B s
24. Technical Information Manual Revision n 8 12 February 2010 V1495 GENERAL PLIRPOSE VME BOARD NPO 00117 04 V1495 MUTx 08 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation 4 reserves the right to change partially entirely the contents of this Manual at time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products CAEN ls for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 TABLE OF CONTENTS 1 GENERAL DESCRIPTION 6 OVERVIEW AER 6 12 BEOCK DIAGRAM ayl uy sa rere 7 2 TECHNICAL SPECIFICATIONS
25. VME 15 FIG 3 5 FPGA USER DIAGRAM Lu s a LL tee Pe be ua 16 FGA Fe INTERRUPT EVEL REGISTER 5 u t eee ee ue EE EE CE TRE CENE EVEN CUENTE 18 FIG 4 2 INTERRUPT VECTOR REGISTER e ene e n enn 19 FIG 4 3 GEOGRAPHICAL ADDRESS 19 FIG 4 4 FIRMWARE REVISION REGISTER 19 NPO Filename Number of pages Page 00117 04 1495 08 V1495_REV8 DOC 42 4 CAEN ls for Discovery Document type Title Revision date Revision Users Manual Mod V1495 General Purpose VME Board 12 02 2010 8 FIG 4 5 USER FPGA CONFIGURATION REGISTER scceseceesseceseeessseceeeecnseceseeecsaeceneeeneeceaeeesaaeceneeeneeceeeesnaeesees 21 FIG 5 1 USER FPGA BLOCK DIAGRAM cscccesseceseeecsseeeseeecsaecesneecsaeceneecaaeceeeecsaeceeeecsaeceseeecsaeceeeeecsaeceeneeeaeeeees 22 FIG 5 2 FRONT PANEL PORTS INTERFACE DIAGRAM scccessecesreessseceseeecneeceseeeesaeceeneceneeceaeeeesaecenesenaeceeeeeneeesaes 28 FIG 5 3 PDL CONTROL BIT FIELDS q n a 33 4 DELAY UNIT SAE SE OAS KESS OERA
26. a bit of a port Each status register is split into two 16 bit register MASK L corresponds to MASK 15 0 while MASK H corresponds to MASK 31 16 There is not a NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 31 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 MASK register associated with G port Each bit of the input ports A B mask registers are internally used in a logic AND operation with the corresponding bit of the port so it is an active low mask bit For instance when MASK is set to 0 the A 0 bit is internally masked logic 0 Each bit of the output port C mask register is internally used in a logic AND operation with the corresponding bit of the internal signal so it is an active low mask bit For instance when MASK _ is set to 0 the C 0 bit is masked output bit is stuck at 0 The x STATUS y x can be y be L or H registers be used to read back eack port bit Each status register is split into two 16 bit register STATUS_L corresponds to STATUS 15 0 while STATUS H corresponds to STATUS 31 0 There is not STATUS register associated with G port The x STATUS vy register reflects the status of the unmasked input and output ports A control register C CONTROL is available to set the C port when the board is configured in I O regist
27. atisfy a trigger condition The trigger condition implemented in this reference design is true when a bit per bit logic operation on port A and B is true The logic operator applied to Port A and B is selectable by means of a register bit MODE Register Bit 4 If MODE bit 4 is set to 0 an AND logic operation is applied to corresponding bits in Port and B i e A 0 AND B 0 A 1 AND 1 etc In this case a trigger is generated if corresponding A and B port bits are 1 at the same time If MODE bit 4 is set to 1 an OR logic operation is applied to corresponding bits in Port A and B i e A 0 OR B 0 A 1 OR B 1 etc In this case a trigger is generated if there is a 1 on one bit of either port A or B Port A and B bits can be singularly masked through a register so that a 1 on that bit doesn t generate any trigger Expansion mezzanine cards can be directly controlled through registers already implemented in this design The expansion mezzanine is identified by a unique identification code that can be read through a register PORTA A_MASK C CONTROL PORT M ADIN Jal A 5 K M s M K B OR s K UNIT_MODE B_STATUS B_MASK COINCI
28. boards developed so far are described in the following table Table 2 3 V1495 Mezzanine boards Board No of Ch Direction Logic Signal Bandwidth Front panel connector LVDS ECL PECL single ended TTL optional 110ohm Rt Robinson Nugent P50E A395A 32 Input Direct Extended 200MHz 068 P1 SR1 TG type Common Mode 34 34 pins input range 4V to 5V Fail Safe input feature LVDS Robinson Nugent P50E A395B 32 Output Direct 100 250MHz 068 P1 SR1 TG type ohm RI 34434 pins Robinson Nugent P50E A395C 32 Output Direct ECL 300MHz 068 P1 SR1 TG type 34434 pins TTL IN Direct NIM TTL TTL OUT Direct selectable selectable NIM IN Invert 50 Rt NIM OUT Direct selectable A395D 8 250MHz LEMO 00 16bit resolution A395E 8 Output Analog 5V 10kQ RL N A LEMO 00 4V 2000 RL NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 10 CAEN Document type Title User s Manual MUT Mod V 1495 General Purpose VME Board NPO 2 7 Revision date Revision 12 02 2010 8 Mezzanine boards installation In order to install one A395x series mezzanine board on the V1495 motherboard it is necessary to follow these steps Remove unscrew the metal cover one at will Plug the mezzanine board into the 100 pin connector on the motherboard Fix the mezzanine board with the screws WARNING A Mounting Option is
29. d version The register content for the VME64 version is Ox1F 4 7 Module Reset Register Base Address 0x800A write only D16 A dummy access to this register allows to generate a single shot RESET of the module 4 8 Firmware Revision Register Base Address 0x800C read only D16 This register contains the firmware revision number coded on 8 bit For instance the REV 1 2 register content is COE ES o oro ojo ojoj1 oj ojoj ojo ojt o Ox1 0x2 Fig 4 4 Firmware Revision Register NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 19 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 4 9 Scratch16 Register Base Address 0x8018 D16 read write This register allows to perform 16 bit test accesses for test purposes 4 10 Scratch32 Register Base Address 0x8020 D32 read write This register allows to perform 32 bit test accesses for test purposes 4 11 Select VME FPGA Flash Register Base Address 0x800E read write D16 This register allows the VME FPGA configuration update stored into on board flash memory via VMEBUS The configuration can be updated by the user by means of the V1495Upgrade software developed and distributed by CAEN see 5 7 4 12 Select USER FPGA Flash Register Base Address 0x8012 read write D16 This
30. ementation See 5 7 4 1 1 Configuration ROM The following registers contain some module s information according to the Table 3 2 they are D16 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB Table 4 2 ROM Address Map for the Model V1495 Description checksum_length2 0x8104 checksum_length1 0x8108 EE checksum lengthO 0x810C MEM NPO Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495 REV8 DOC 42 17 CAEN Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 wen o we oere hmm oe 0x8130 m mn me was sernum1 0x8180 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration ROM 4 2 Control Register Base Address 0x8000 read write D16 This register allows performing some general settings of the module Not used for VME FPGA Rev 0 0 Foreseen for future development 4 3 Status Register Base 0x8002 read only D16 This register contains information on the status of the module Not used for VME FPGA Rev 0 0 Foreseen for future development 4 4 Inte
31. er A 15 0 Mask bit is active low Port A mask This register A 31 16 Mask bit is active low Port B mask This register B 15 0 Mask bit is active low Port B mask This register B 31 16 Mask bit is active low Port C mask This register C 15 0 Mask bit is active low Port C mask This masks C 31 16 register Mask bit is active low Gate signal width This number represents a multiple of the Number of pages 42 m mu X 0004 Page 29 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 NAME ADDRESS DATA SIZING ACCESS NOTES DEFAULT selected delay line period see detailed description C_CONTROL_L 0x001A D16 WO Port C control When the port C is X 0000 configured to be an output under register control see MODE register the status of C 15 0 is controlled by this register C_CONTROL_H 0x001C D16 WO Port C control When the port C is X 0000 configured to be an output under register control see MODE register the status of C 31 16 is controlled by this register MODE 0x001E D16 WO It configures the behaviour of the X 0008 system Default I O MODE 1 0 DELAY SEL Register MODE 3 UNIT MODE Mode 0 Coincidcence Unit 1 Register MODE 4 OPERATO
32. er mode 5 5 2 V1495 Mezzanine Expansion Ports Registers PORT D E F The mezzanine expansion ports D E F can be configured and accessed using a set of registers In this reference design no mask register is implemented for the expansion ports The x DATA y x can be D E F y can be L or H registers can be used to read back each port bit Each status register is split into two 16 bit register D DATA L corresponds to D 15 0 while D DATA H corresponds to D 31 16 The expansion ports can be bidirectional In case the port is configured as an output the register value set the port value In case the port is configured as an input the register content reflects current port value A x CONTROL register x can be D E F is available to set the corresponding port direction and logic level selection 5 5 3 Delay Selection The selection of the asynchronous timer is made through the MODE register by means of the DELAY SEL bit MODE 1 0 The selection of the delay line is made according to the following table Table 5 8 Selection of the delay line MODEHII MODE 0 DELAY LINE 0 0 PDL0 0 1 1 0 DLO0 l l DLO1 NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 32 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 5 5 4 PDL DELAY VALUE SETTING AND READBACK The programmab
33. fe fv1435uer_demo qpt Tipo file II Proj pt 2 gt Quartus II Project File quartus L 5 221 i Critical Warming Suppressed eT m For Help press F1 Tae NM Fig 5 11 Quartus II project browser Once the project is open the Project Navigator shows the following information There are 5 VHDL files filename vhd and a Verilog netlist istname vqm The reference design is included in the coin_reference vhd file The other files provide support to the project and shall not be midified by the developer HAL Hardware Abstraction Layer is implemented on the netlist Verilog v1495usr_hal vqm Filename Number of pages Page 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 39 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 Quartus II C 1495 USER DEMO v1495usr demo y File Edit View Project Assignments Processing Tools Window bi 495usr_derr Project Navigator ajx SY Files i a SRC 1485usr demo v1495usr pkg vhd SRC v1485usr demo coin reference vhd SRC v1495usr demo spare itl hd SACAVI 495ust_demo tristate_it_rtl vhd be SRC v1485usr demo v1495usr demo vhd Sega SPFPC v1435hal v1435usi_halvqm E Software Files L J Other Files Hierarchy Files i Design Units Fig 5 12
34. ier D_LEV OUT 1 D slot Port Signal Level Select the level selection depends on the mezzanine expansion board mounted onto this port NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 23 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 PORT NAME DIRECTION WIDTH DESCRIPTION D_DIR OUT 1 D slot Port Direction D DIN IN 32 D slot Data In Bus D DOUT OUT 32 D slot Data Out Bus E IDCODE IN 3 E slot mezzanine Identifier E LEV OUT 1 E slot Port Signal Level Select the level selection depends on the mezzanine expansioon board mounted onto this port E_DIR OUT 1 E slot Port Direction E_DIN IN 32 E slot Data In Bus E_DOUT OUT 32 E slot Data Out Bus F_IDCODE IN 3 F slot mezzanine Identifier F_LEV OUT 1 F slot Port Signal Level Select the level selection depends on the mezzanine expansion board mounted onto this port F_DIR OUT 1 F slot Port Direction F_DIN IN 32 slot Data In Bus F DOUT OUT 32 F slot Data Out Bus PDL CONFIGURATION INTERFACE PDL WR OUT 1 Write Enable PDL SEL OUT 1 PDL Selection 0 gt PDL0 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read DELAY LINES AND OSCILLATORS I O PDLO_OUT IN 1 Signal fro
35. justed setting the PDL delay using either on board dip switches or through register NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 34 CAEN Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 NPO When a coincidence occurs leading edge of COINC signal the STARTDELAY signal becomes active high STARTDELAY triggers a monostable in order to generate a pulse with a duration large enough to ensure maximum linearity performance of the This value should be more than 320 ns PDL see 3D3428 component datasheet The selected value in the reference design is 360 ns The PDL_PULSEOUT internal signal is generated as the logic OR of PDL_IN and PDL_OUT so generating a pulse whose width is proportional to the PDL actual delay The PDL_PULSEOUT signal falling edge is used to reset the flip flop state The pulse width Tp is Tp Tpd T pf Where Tpd is the delay of the selected PDL programmable via VME or by on board dip switches whichever mode is enabled Tpf is the delay introduced by the FPGA pad and internal logic The maximum pulse width is limited by the PDL maximum delay in this case 5 5 6 Delay Unit using DLOs The following diagram shows the implementation of the DELAY UNIT using two oscillators based on delay lines DLO present on the board DLOx DELAY COUNTER Filename Number of pages Page 00117 04 V 1495
36. le Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 4 14 USER FPGA FLASH MEMORY u u a pa g a ay Sasa ua 20 4 15 USER FPGA CONFIGURATION REGISTER 22 21 5 1495 USER FPGA REFERENCE DESIGN KIT 22 TINTRODUCTION 22 52 IDESIGN 22 5 2 1 Sas au 22 5 2 2 COIN REFERENCE Design 23 3 3 INTERFACE DESCRIPTION EP e E DEEP E e 25 5 3 1 25 3 3 2 REGISTER INTERFAGE uuu SO u R RSS SU a SS 25 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE 26 5 3 4 V1495 Mezzanine Expansion Ports PORT D E F INTERFACE 26 5 3 5 PDI Configuration Interface 26 5 3 6 Delay Lines and Oscillators 27 5 3 7 SPARE Interface E 27 5 3 8 PUDE rr E 27 5 4 REFERENCE DESIGN DESCRIPTION eese e ene ener nnne nn nnn e rte rte r err err EEE EEE 27 5 5
37. le delay lines chip available on board can be programmed with a specific delay using on board 8 bit dip switch SW6 for Delay 0 and SW5 for Delay1 on motherboard via VMEbus Two registers are available to configure PDLs PDL_CONTROL PDL_DATA PDL_CONTROL is used to Select target PDL for read write operations Enable delay update Select programming mode via VME register or by on board switches The PDL_CONTROL bit fields are shown in the following figure 15 14 13 12 10 9 JE 654321 Es PDL WR PDL DIR PDL SEL Fig 5 3 PDL CONTROL bit fields 0 PDL WR 1 enables the updating of the PDL delay value in this way the delay value set either via dip switch or via PDL DATA register is automatically loaded By setting this bit to 0 the delay value cannot be changed PDL DIR allows to select the source of data for PDL programming 0 the selected PDL has as delay value on its parallel programming bus the dip switch value 1 the selected PDL has as delay value on its parallel programming bus the PDL DATA register 8 LSB PDL SEL allows to select one of the PDL s PDLO and PDL1 for read write operations PDL DATA register is used to Write the delay value for the next delay update via VMEbus Read the on board switch status Examples updating of PDLO delay via switch the default value in the CONTROL allows to update the delay directly via dip switch just af
38. llows the following operations e FPGA USER flash memory programming FPGA USER updating NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 16 Tools for Discovery Document type User s Manual MUT Title Mod V Revision 8 Revision date 1495 General Purpose VME Board 12 02 2010 4 VME Interface 4 1 Register address map The Address map for the Model 1495 is listed in Table 4 1 All register addresses are referred to the Base Address of the board i e the addresses reported in the Tables are the offsets to be added to the board Base Address Table 4 1 Address Map for the Model V1495 ADDRESS REGISTER CONTENT ADDR DATA Read Write Base 0x0000 0x7FFC USER FPGA Access A24 A32 R W Base 0x8000 Control Register 24 2 0 8002 Status Register A24 A32 Base 0x8004 Interrupt Level A24 A32 Base 0x8006 Interrupt Status ID A24 A32 Base 0x8008 Geo Address Register A24 A32 Base 0x800A Module Reset A24 A32 Base 0x800C Firmware revision A24 A32 Base 0x800E Select VME FPGA Flash A24 A32 Base 0x8010 VME FPGA Flash memory 24 2 Base 0 8012 Select USER FPGA Flash A24 A32 Base 0x8014 USER FPGA Flash memory A24 A32 Base 0x8016 USER FPGA Configuration A24 A32 Base 0x8018 Scratch16 A24 A32 Base 0x8020 Scratch32 A24 A32 Base 0x8100 0x801FE Configuration A24 A32 Read Write capability depends on USER FPGA impl
39. m PDL0 Output PDL1_OUT IN 1 Signal from PDL1 Output DLO0_OUT IN 1 Signal from DLO0 Output DLO1_OUT IN 1 Signal from DLO1 Output 1 The channels of the A395D Mezzanine board are mapped on the 8 LSB of D DIN D DOUT E DIN E DOUT F DIN F DOUT signals NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 24 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 PORT NAME DIRECTION WIDTH DESCRIPTION PDLO_IN OUT 1 Signalto PDL0 OUT 1 Signal to Input DLO0_GATE OUT 1 Signalto Input DLO1_GATE OUT 1 Signal to DLOI Input SPARE INTERFACE SPARE_OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In SPARE_DIR OUT 1 SPARE Direction LED INTERFACE RED_PULSE OUT 1 RED Led Pulse active high GREEN_PULSE OUT 1 GREEN Led Pulse active high 5 3 Interface description NPO 5 3 1 Global Signals The nLBRES must be used as an asynchronous reset signal by the user An active low pulse will be generated when write is done at the Module Reset register address see 8 4 1 The LBCLK is a 40 MHz clock It is the FPGA main clock 5 3 2 REGISTER INTERFACE The signals of the Register Interface allows to read write into the USER FPGA registers which be accessed via VMEbus The COIN REFERENCE module shows how to implement a set of regi
40. nal F F_DIR Selects direction Bidirectional port F_DIN Read the logic level Input Bidirectional F_DOUT Set the logic level Output Bidirectional F IDCODE Read IDCODE for piggy back identification All F_LEV Set the logic level Output Bidirectional 5 3 5 PDL Configuration Interface PDL WR OUT 1 Write Enable PDL_SEL OUT 1 PDL Selection 0 gt PDL0 1 gt PDL1 PDL_READ IN 8 Read Data PDL_WRITE OUT 8 Write Data PDL_DIR OUT 1 Direction 0 gt Write 1 gt Read NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 26 CAEN Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 5 3 6 Delay Lines and Oscillators I O Delay Lines and Oscillators signals are as follows see also 5 5 5 and 5 5 6 Table 5 4 Delay Lines and Oscillators signals PDLO_OUT IN 1 Signal from PDLO Output PDL1_OUT IN 1 Signal from PDL1 Output DLO0_OUT IN 1 Signal from DLO0 Output DLO1_OUT IN 1 Signal from DLO1 Output PDL0_IN OUT 1 Signal to PDLO PDL1_IN OUT 1 Signal to Input DLOO_GATE OUT 1 Signal to DLOO Input DLO1_GATE OUT 1 Signal DLOI Input 5 3 7 SPARE Interface These signals allow to set and read the status of SPARE pin present on the board Table 5 5 SPARE Interface signals SPARE_OUT OUT 12 SPARE Data Out SPARE_IN IN 12 SPARE Data In SPA
41. nt Title Mod V1495 General Purpose VME Board Revision date 12 02 2010 Revision 8 interconnection route of the FPGA capabilities Simulation and timing analysis allow to verify the functionality of the project The reference design includes a minimum set of contraints in order to allow the design to perform the foreseen function The last important step is the generation of the programmation file Quartus allows to generate different formats the RBF format is the one used to program the FPGA USER via VME The provided reference project produces automatically this format in the project directory under the filename v1495usr demo rbf Includes block based design system level design amp software development Power Analysis Debugging Engineering Change Management Analysis Programming amp Configuration Fig 5 8 Quartus II project flow Timing Closure The following screenshot shows the main menu of Quartus II NPO 00117 04 V1495 MUTx 08 Filename V1495_REV8 DOC Number of pages 42 Page 37 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1495 General Purpose VME Board 12 02 2010 8 Quartus Edit View Project Assignments Processing Tools Window ju Project Navigator gt Hiero Implement dur Low Cost Proce
42. ntation inside the FPGA USER can be used to drive a gate signal The programming of the delay time can be done manually as binary value either via 8 bit dip switches SW4 SW5 or via VME register with a ins step resolution max step delay 255ns The software setting has higher priority with respect to the dip switches The following figure shows a diagram of the timers usage Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 13 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 lt Tperiod gt Twdh START 0 Tset Toffset Tdly Toffset Tset Toffset 30 2ns Tset SETBINARY Ins STARTx WIDTHMIN 320ns recommended 22ns absolute min STARTx PERIODMIN 640ns recommended 46ns absolute min Fig 3 1 Timers diagram The use of STARTx signals with timing shorter than those recommended is possible although the linearity on the set delay scale is no longer guaranteed 3 1 2 Timer2 Timer3 Each timer is made up of one digital circuit which produces a typical fixed time base with 10ns period and 50 duty cycle These timers are proposed for generating any Gate pulse gt 10ns with a 10ns step The following figure shows an example of a Gate generation made with Timer2 and n 3 PULSE width ISTART E 2 c Teny lt puse2__ L
43. rmware dedicated to the interface of the board with the FPGA USER and the VME bus such firmware is developed by CAEN The flash related to the FPGA USER contains the firmware developed by the User according to his own application requirements 3 2 1 FPGA VME NPO The microcontroller provides the firmware uploading at board s power on The flash memory contains two versions of the firmware which can be selected manually via jumper Standard or Backup FPGA VME Program Circuit P VME BUS VME FPGA lt FLASH lt lt FW SEL Fig 3 4 FPGA VME diagram Filename Number of pages 00117 04 V1495 MUTx 08 V1495_REV8 DOC 42 Tools for Discovery Document type Title Revision date Revision User s Manual Mod V 1495 General Purpose VME Board 12 02 2010 8 3 2 2 FPGA USER The microcontroller provides the firmware uploading at board s power on The flash memory contains one firmware image only Standard FPGA USER Program Circuit 2 o m FPGA VME lt gt gt FPGA USER egg FLASH C a Fig 3 5 USER diagram FPGA VME aim is to handle the operation of FPGA USER which can be programmed on the fly i e without turning off the system thus allowing quick debug operations by the Developer Register implemented on FPGA VME a
44. rrupt Level Register Base Address 0x8004 read write D16 The 3 LSB of this register contain the value of the interrupt level Bits 3 to 15 are meaningless Default setting is 0x0 In this case interrupt generation is disabled Not implemented in VME FPGA Rev 0 0 Available in next releases GRRE PP RPE EEE ST EVE Fig 4 1 Interrupt Level Register NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 18 Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 4 5 Interrupt Status ID Register Base Address 0x8006 read write D16 This register contains the STATUS ID that the V1495 places on the VME data bus during the Interrupt Acknowledge cycle Bits 8 to 15 are meaningless Default setting is 0xDD Not implemented in VME FPGA Rev 0 0 Available in next releases 15 1413121 1110 9 8 7 6 5 4 3 2 1 0 STATUS ID Fig 4 2 Interrupt Vector Register 4 6 GEO Address Register Base Address 0x8008 read D16 The register content is the following L GEO ADDR 0 GEO ADDR 1 GEO ADDR 2 GEO ADDR 3 GEO ADDR 4 Fig 4 3 Geographical address register This register allows readback of the level of GEO pins for the selected board The register content is valid only for the VME64X boar
45. ssor in Cyclone Il FPGAs QUARTUS 1 Version 6 Documentation poe Suppressed Message T Locate For Help press el aa Fig 5 9 Quartus II main menu Now select File gt Open Project Edit View Project Assignments Processing Tools Window Help i eer i eelo gt z gt Vownload b 44 Implement a G SS Low Cost Processor P in Cyclone Il FPGAs s gt auj anA La QUARTUS I 1 Export Version 6 Convert Programming Files File Properties Recent Files Recent Projects Exit System Processing Info Waming CitealWaning Enor Suppressed 2 Message p sasan Locate Opens an existing project msasa NM Fig 5 10 Quartus II file menu NPO Filename Number of pages Page 00117 04 1495 0 08 V1495_REV8 DOC 42 38 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 NPO browse the file project 1495 demo qpf File View P Project Navigator Xs Prog sang Tools Window Help sole dixX eew o x xr ej a A ad Compilation Hierarchy Cerca in V1495_USER_DEMD y casn II 6 0 Rise di rete Nome
46. ster access is valid only when USR_ACCESS is at logic level 1 5 3 3 V1495 Front Panel Ports PORT A B C G INTERFACE These signals allows to handle the interface with the motherboard ports A B C G A_DIN and B_DIN signals show the logic level of A and B ports 32 bit input only The output logic level on port C can be set via C_DOUT signal The logic level on port G LEMO connectors can be set via G_LEV signal the direction via G_DIR the datum to be written via G_DOUT or to be read via G_DIN 5 3 4 V1495 Expansion Ports PORT D E F These signals allows to handle the interface with the piggy back board D E F The following table explains the available signals Table 5 2 V1495 Mezzanine Expansion Ports signals PDL Configuration Interface signals are as follows Table 5 3 PDL Configuration Interface signals Port Signal Function Applies to D D_DIR Selects direction Bidirectional port D_DIN Read the logic level Input Bidirectional D_DOUT Set the logic level Output Bidirectional D IDCODE Read IDCODE for piggy back identification All D_LEV Set the logic level Output Bidirectional E E DIR Selects direction Bidirectional port E_DIN Read the logic level Input Bidirectional E DOUT Set the logic level Output Bidirectional E IDCODE Read IDCODE for piggy back identification All LEV Set the logic level Output Bidirectio
47. sters The following table shows the registers map as it is provided Each register address is coded via constants in V1495pkg vhd file This file allows to modify the registers map all registers allow D16 accesses write only read only or read write Registers default value is the value after a reset for write only and read write registers read only registers return the status of the signals read by the FPGA and have no default value The Register Interface allows to abstract the VME registers access The User can access a simple register interface two signals REG_WREN e REG_RDEN are pulses with a one clock cycle duration which enables respectively a write or a read access to a register REG_ADDR signal represents the register address Writing into a register In case of a write operation into a register via VME the 16 bit datum is available through the REG_DIN signal The datum is guaranteed stable on the CLK leading edge where REG_WREN is active The register access is valid only when USR_ACCESS is at logic level 1 Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 25 CAEN Document type Title User s Manual MUT Mod V 1495 General Purpose VME Board Revision date Revision 12 02 2010 8 Reading from a register In case of a read operation from a register via VME the datum to be returned must drive the REG_DOUT and be stable on the CLK leading edge where is active The regi
48. ter the board turning ON each change in the dip switch status set immediately a new delay value The sequence to be followed is Step 1 write Ox1 in the PDL CONTROL register Step2 update the dip switches value B updating of PDL1 delay via switch Step 1 write 0x5 in the PDL CONTROL register Step 2 update the dip switches value C updating of PDLO delay via VMEbus Step 1 write 0x3 the CONTROL register Step2 write the delay value in the PDL DATA register NPO Filename Number of pages Page 00117 04 V 1495 MUTx 08 V1495 REV8 DOC 42 33 CAEN Document type Title Revision date Revision User s Manual MUT Mod V 1495 General Purpose VME Board 12 02 2010 8 D updating of PDL1 delay via VMEbus Step 1 write 0 7 in the PDL_CONTROL register Step2 write the delay value in the PDL_DATA register GATE WIDTH USING Delay Line Oscillators The GATEWIDTH register can be used to set the gate signal width on the G port see Delay Unit using DLOs see 5 5 6 5 5 5 Delay Unit using PDLs The following diagram shows the implementation of the DELAY_UNIT using the one of the two programmable delay lines PDL available on the boards MONOSTABLE 360 ns pulse Fig 5 4 Delay Unit with PDLs Tmon COINC 1 PDLx_IN l PDLx OUT PDL_PULSEOUT STARTDELAY STOPDELAY Fig 5 5 PDLs Delay line timing The pulse width generated using PDLs Tp can be ad
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