eZ80F91 Modular Development Kit
Contents
1. eZoUFy1 Modular Development Kit User Manual C5 R26 47K 22pF i 36 VCC 33V 1 us MDIO RST y MDIO RST bat vob MDC VDDPLL F 25MH BXDS RXD3 PHYAD1 xi 5 7229F END pm RXD2 PHYAD2 GND pop AKDI PHYADI idee GND GND 8 vec VDDTX 41 TX R18 Axor 2 GND Tee TX VDDC BXCIK 2 RXDV PCS LPBK Tx 5 et FBI FB H RXC GND no HH RXER ISO vbDRCV 5 4 e gt e e i ae 2 GND REXT j VDDC VDDC anp L38 GND C7 Ferrite Bead 9 Ferrite Bead TROK te TXER GND 38 P Eu AE Sour ST sio u TREN TXC REFCLK FXSD FXEN Pd hpx Wa SE Pour TXEN Kale GND Tom 1x00 nx F2 4 34 Tepe TXD1 VDDRX Tos 102 PD p30 RIS ik coc TXD3 LEDS NWAYEN 32 CRS 1 COURMII LED2 DUPLEX aa 1 on 244 CRS RMIL BTB LED1 SPD100 noFEF 2L rEBTNK 3 vec 33y GND LEDO TEST L 24 ve INT PHYADDO BE 34 RI6 KS8721BL vppe Make sure that power connections Ar and nets VDD_PLL and VDDC have T the shortest route possible C13 Ci4 C15 os c19 0 fuF Our O 1UF 47uF Header 1 VCC 33V JP2 GND2. eZ80F91 Modular Development Kit User Manual ritoa 5 eZ80Acclaim MDS Adapter Board This section describes functions of the eZ80Acclaim MDS adapter board eZ80F91 Mini Enet Module Interface The eZ80F91 Mini Enet Module interface on the eZ80Acclaim MDS adapter board consists of two 56 pin mini module receptacles Almost all of these receptacles signals are connected directly to the CPU Three input signals offer options to the application developer by disabling certain functions of the eZ80F91 Mini Enet Module These three input signals are Disable IrDA DIS IrDA used only if you have installed an external SIR IrDA transceiver onto the eZ80F91 Mini Enet Module F9 WE e RTC Vpp A description of these three signals follows Disable IrDA When the DIS_IrDA input signal is pulled Low the IrDA transceiver located on the eZ80F91 Mini Enet Module is disabled As a result UARTO can be used with the RS232 or the RS485 interfaces on the eZ80 Development Platform F91 WE When the F91 WE signal is active Low internal Flash on the eZ80F91 chip is enabled for writing This signal is inverted from the F91_WP signal on the eZ80F91 chip RTC Vpp RTC Vpjy is a test point for the Real Time Clock power sup ply UM017001 0404 PRELIMINARY eZ80Acclaim MDS Adapter Board eZ80F91 Modular Development Kit User Manual zito Peripheral Bus Mini Module Connector J1 Figure 3 illustrates the
3. 23 Figure 8 eZ80Acclaim MDS Adapter Board Schematic 1 of 2 33 Figure 9 eZ80Acclaim MDS Adapter Board Schematic 2 of 2 4 Figure 10 eZ80F91 Mini Ener Module Schematic 1 of 2 35 Figure 11 eZ80F91 Mini Ener Module Schematic 2 of 2 36 UM017001 0404 PRELIMINARY List of Figures eZ80F91 Modular Development Kit User Manual Vill PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa ix List of Tables Table 1 eZ80Acclaim MDS Adapter Board Peripheral Bus Connector J1 Identification 7 Table 2 eZ80Acclaim MDS Adapter Board I O Mini Module Connector J2 Identification 11 Table3 eZ80Acclaim MDS Adapter Board Peripheral Bus External Connector 121 Identification 15 Table 4 eZ80Acclaim MDS Adapter Board VO External Connector JP21 Identification 19 Table 5 eZ80Acclaim MDS Adapter Board Jumper Settings 21 Table 6 Shunt JP1 628091 Mini Ener Module 28 UM017001 0404 PRELIMINARY List of Tables eZ80F91 Modular Development Kit User Manual PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual Introduction The eZ80F91 Modular Development Kit provides a general purpose plat form for creating a design based on ZiLOG s eZ80F91 microcontroller The eZ80F91 is a member of ZiLOG s eZ80Acclaim product family which offers on chip Flash capability
4. Jumper 19 on the eZ80Accaim MDS adapter board must be OFF to enable the control gate that drives the IrDA device Set port pin PD2 Low When this port pin and Jumper 19 are turned OFF the IrDA device is enabled Disable the RS232 output by installing a shunt on jumper J8 on the eZ80Acclaim MDS adapter board Contacting ZiLOG Customer Support For additional troubleshooting solutions see ZDS II Online Help For valuable information about hardware and software development tools visit ZILOG Customer Support online Download the latest released ver sion of ZiLOG Developer Studio Get the latest software updates from ZiLOG as soon as they are available UM017001 0404 PRELIMINARY Troubleshooting eZ80F91 Modular Development Kit User Manual 32 ziLOG Contacting ZiLOG Customer Support PRELIMINARY UM017001 0404 ES eZoUFy1 Modular Development Kit User Manual ziLOG connector 2 connector 1 J9 JP1 JP2 DS IRDA rA PN m Bie 2 2 S K 1 L a ES LEN rums XSDW Es PAT Ce HEADER 2 F91 amp 8 DIS IRDA GND 9 io VGC 33V VCC 33V 9 10 GND 11 12 A0 PB7 11 12 PB6 R14 ATO 13 A3 PBS 4 11 pBa gt gt PB6 VCC CUST VCC SRAM GND 15 18 VOC sav PBS 15 ig PB2 AS 1 18 A7 PBI 1 18 PBO 0 AT 19 0 A9 GND 19 20 7 ATS 21 22 A14 POS 21 PCS Ais 23 24 AT PCA 3 2a PC3 R15 25 es GND TBC2 35 26 PCI VCC 33V 27 28 PCO 27 28 PD7 Aa pao Am PD6 29
5. 211 0 6 eZ80F91 Modular Development Kit User Manual PRELIMINARY UMO17001 0404 ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www ZiLOG com eZ80F91 Modular Development Kit User Manual Z This publication is subject to replacement by a later edition To determine whether a later edition exists or to request copies of publications contact ZiLOG Worldwide Headquarters 532 Race Street San Jose CA 95126 Telephone 408 558 8500 Fax 408 558 8300 www zilog com Document Disclaimer ZiLOG is a registered trademark of ZiLOG Inc in the United States and in other countries All other products and or service names mentioned herein may be trademarks of the companies with which they are associated 2004 by ZiLOG Inc All rights reserved Information in this publication concerning the devices applications or technology described is intended to suggest possible uses and may be superseded ZiLOG INC DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION DEVICES OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION DEVICES OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE Except with the express written approval of ZiLOG use of information devices or technology as critical components of life support systems is
6. 30 GND 0 32 PD5 1 ap PD4 Ri Di A5 33 A PDS 34 PD2 5 5 AESI PD3 PD2 10K TEST 35 36 DSI H E PD1 45 D PDO 3 ZI LEDYEL a 3 Tas CC 33V Ppi 37 PDO 4 A22 39 40 A23 GND 39 40 TRIGOUT R3 CS0 41 42 CSI TCK 41 4 TMS PBS CS2 43 44 DO RTC VDDa 44 EZBOCLK Di 45 46 2 CSCL 330 D3 4 48 D4 TICSDA GND D5 49 50 DND 50 S1 D7 D6 53 DIS_IRDA PB3 i GND MREQ 53 54 __ IOREQ RST zl 54 WAT 97 9 GND 55 se AD VCU 33 se OND SW PUSHBUTTON 5 58 ___ INSTRD HALT SUP 5 sa NMI TEST BUSACK 59 60 BUSREQ CC 33V 59 60 EI E HEADER 30x2 SM HEADER 30x2 SM J8 Eis J12 v2 2 END ann M F DO 2 H k 25 ag po 22 6000 5V tt pi pa ED E Raa WA pa 33 D L8 AE 22 i8 ps 38 F z m Aa De F_D5 HEADER 2 EI Eemere Ds 20 r pe A ja pe A ES TN A7 IERCH TN oH A8 Ds HI GPRS MODEM 12 ar 9 Do 32 CONNECTORS PAK pio 24 EES AS pij 36 as AS 3 hi2 Dia 39 ig AE 4 A18 pis L41 Eram A18 H A14 D14 B A0 pa AT LI A15 D15 A 1 Ba Le 48 6 120 Am 18 A1 o an Ju ES P Ne Ei 24 21 n gu A19 NC RST GND RST NEP ont LA PODR roa 2 RESET Ge Hh pepo Pee RYBY B voc say 26 PC3 CTST PCS VPP veo L HEADER 9 PC5_DSRT PCS RD 28d SE C2 8 29 PC7_AN PCT FLASH EN 280 cc ND mg a Tag PCT AXDT PCT WR SS GND A HR E dw m GND YE HEADER 32 Am29LV160D Schematics Schematics eZ80Acclaim MDS Adap
7. Yes Yes Yes Yes Yes Low Low Low Low Low Ouput Output Output Output Input Symbol RD WR INSTRD BUSACK BUSREQ Pin 56 57 58 59 60 Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board schematics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device eZ80Acclaim MDS Adapter Board PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual 18 ritoa UO External Connector JP2 Figure 6 illustrates the pin layout of the I O Connector in the 60 pin header on the eZ80Acclaim MDS adapter board Table 4 identifies the pins and their functions PAT 2 Kz o 33V 5 SND IR PE z 5 2 7 a P827 GN 2 zien FCE 2 22 5 50 3 2 3 PC2 5 ER BC a PD EDE 2s GND EDS 3 2 4 PO3 2 33 2 ep2 eo ae gt Fae Den o H3 T a TDI GND is 41 TRIGOUT YA RTC VOG EZECCLK lICSCL 45 Fr ICSDA 47 2p GND q Was cn TEI DIS_JRDA AST 53 AT V jV zz 5 GNO Air a RJ VEC_33V ee Figure 6 eZ80Acclaim MDS Adapter Board UO External Connector JP2 eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ricoa 19 Table 4 eZ80Acclaim MDS Adapter Board UO External Connector JP2 Identification Pin
8. Symbol Signal Direction Active Level eZ80F91 Signal 1 8 PA7 to PAO Bidirectional n a Yes 11 18 PB7toPBO Bidirectional n a Yes 20 27 PC7to PCO Bidirectional n a Yes 28 29 PD7 PD6 Bidirectional n a Yes 31 36 PD5 to PDO Bidirectional n a Yes 37 TDO Output n a Yes 38 TDI O n a Yes 40 TRIGOUT Output n a Yes 41 TCK Input n a Yes 42 TMS Input n a Yes 43 RTC Vpp Input n a Yes 44 EZ80CLK Output n a Yes 45 IICSCL IO n a Yes 47 IICSDA IO n a Yes 49 FLASHWE Input Low No 51 CS3 Output Low Yes 52 DIS IRDA Input Low No 53 RST VO Low Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board schemat ics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device UM017001 0404 PRELIMINARY eZ80Acclaim MDS Adapter Board eZ80F91 Modular Development Kit User Manual 20 ritoa Table 4 eZ80Acclaim MDS Adapter Board UO External Connector JP2 Identification Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal 54 WAIT Input Low Yes 57 HALT SLP Output Low Yes 58 NMI Input Low Yes 60 unused n a n a n a Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80A
9. User Manual 22 ritoa eZ80F91 Mini Enet Module This section describes the eZ80F91 Mini Enet Module hardware its inter faces and key components including the CPU real time clock and mem ory Functional Description The eZ80F91 Mini Enet Module is a compact high performance module specially designed for the rapid development and deployment of embed ded systems Despite its small footprint the eZ80F91 Mini Enet Module provides a CPU Flash memory Ethernet interface SRAM and a real time clock This module is powered by the eZ80F91 microcontroller a member of ZILOG s eZ80Acclaim product family Fast Buffer A Fast Buffer is located on the data bus to Flash memory The purpose of this Fast Buffer is to avoid bus contention that can exist due to the slow turn off time of Flash memory and the fast bus turn around time of the eZ80F91 device a generic feature of the eZ80Acclaim family when is used in native mode The discussion that follows references Figure 7 Bus contention can occur when two or more devices drive a common bus CSO on the eZ80F91 device drives the Flash CE Upon accessing Flash memory CSO is driven High a maximum of 8 8ns after the next rising edge of the CPU Clock T6 please refer to the External Memory Read Timing diagram in the eZ80F91 Product Specification PS0192 for assis tance The Flash turn off time Top is 25 ns the duration from OE or CE going High to Flash output drivers in a hig
10. adapter board PRELIMINARY UMO017001 0404 User Manual Kit Features eZ80F91 Modular Development Kit User Manual ritoa 3 eZ80F91 Modular Development Kit Overview The purpose of the eZ80F91 Modular Development Kit is to provide the design engineer with a set of tools for designing an application based on the eZ80F91 microcontroller A block diagram of the eZ80Acclaim MDS adapter board is shown in Figure 1 Flash Memory not installed e 5 5 g o eo o o Ee bai bel i i n RS232 Dd o g IN 3 5 5 5 ui ZDI be H Power Supply Figure 1 eZ80Acclaim MDS Adapter Board Block Diagram UM017001 0404 PRELIMINARY Introduction eZ80F91 Modular Development Kit Figure 2 provides a block diagram of the eZ80F91 Mini Enet Module 128KB SRAM F91 Bus consists of 24 bits of address 8 bits of data 32 bits eZ80F91 of GPIO and control signals EMAC MII F91 Bus 56 Pin Connector J1 56 Pin Connector J2 Figure 2 eZ80F91 Mini Ener Module Block Diagram Schematics for the eZ80F91 Mini Enet Module and eZ80Acclaim MDS adapter board are provided in the Schematics section starting on page 33 UM017001 0404 User Manual 4 ritoa Ethernet PHY SIR IrDA not installed eZ80F91 Modular Development Kit OverviewPRELIMINARY
11. eZBOCLK A22 28 2 ADS Foo per 2R7 u2 02800 gt ESCH Cpg CS3 ono GND vec DEE PA 3 CC 33V 2 31 VCC 33V PD7 32 TMS MMA 0204 Sek elen CS2 24 33 FI WE PD5 34 3 PD6 1 LEDA peor EE RIC VDD 6 a5 53 PD4 PD3 gt GND rr 3 GND THIGDUT ag mem PDO 2 aes i POR HALT SLP 40 ag D7 N GND DEE Wi EEN Po 9 TCK IRDA SD rape ppio n EH AT 4 43 A2 PDO 44 43 TUI 0 LL Ag 46 45 A14 TDO 46 45 PD2 PD1 3 mo k ast ESL GND 48 4 GND GND 48 4 GND RM A5 49 A16 CSCL 50 49 DIS_TRDA 6 GND See RD vec 33V AT 52 51 Als IICSDA 59 51 WAT FE WR WR GND GND NMI RST ZHX1810 VOT SRAM 56 55 VCC SRAM VCC 33V 56 55 VCC 33V q Ri R7 2 2 10K r c HEADER 28x2 HEADER 28x2 Se wam WAT wu NML u3 AO Hao voje Ds S Al 3 4 Mja Ge GND 8 A3 4 42 voe D6 AH A3 V O3 8 AS 14 M VOS D SN74LVC2G04 Ro ya A5 VO5 Bo 10K 10K A kl A6 VO ER Dt AI A7 W i Ab 17 A18 18 48 TDI 5 Aig A10 TCK Ri3 H ai AB 21 m2 acon TRIGOUT it TMS 5 0 4 AT TDO Hats R AA as 24 VGC SRAM TRSTN A16 VCC VQC SRAM WR gl vecy AD WE OE CST a c2 C3 cs 0 001uF 0 tuF op 25 3 vec_33v GND vee 33V d o VCC 33V IDT71V124S SO VCC 33 vee aav UIA 9 UA GND DIS_IRDA Benes L PD2 IR SD 2 GND SN74LVC2G04 SE 4 74AHC1G32 E CONNECTORS GND Figure 10 eZ80F91 Mini Enet Module Schematic 1 of 2 UMO1 7001 0404 PRELIMINARY Schematics
12. is write protected Flash Loader Utility The Flash Loader utility integrated within ZDS II allows the user a conve nient way to program on chip Flash memory Please refer to the ZiLOG Developer Studio eZ80Acclaim User Manual UM0144 for more details Internal On Chip Flash Memory PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa 29 ZDS 1 ZiLOG Developer Studio II ZDS 11 Integrated Development Environ ment is a complete stand alone system that provides a state of the art development environment Based on the Windows Win98SE NT4 0 SP6 Win2000 SP2 WinXP user interfaces ZDS II integrates a language sensitive editor project manager C Compiler assembler linker librarian and source level symbolic debugger that supports the eZ80F91 device For more information on ZDS II refer to the ZiLOG Developer Studio eZ80Acclaim TM User Manual UMO144 UM017001 0404 PRELIMINARY ZDS Il eZ80F91 Modular Development Kit User Manual 30 ritoa ZDS II PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual 31 Troubleshooting Overview Before contacting ZiLOG Customer Support to submit a problem report please follow these simple steps If a hardware failure is suspected con tact a local ZiLOG representative for assistance IrDA Port Not Working If you plan on using the IrDA transceiver on the eZ80F91 Mini Enet Module make sure the hardware is set up as follows
13. t 7 018 _ C20 VCG 33V Our Omar 47uF p GND 1 on Our TX SCL wee TE Pai SDA IICSDA T PA7 R20 49 9 R P1 VCC 33V 1 ine H Txcr R22 493 Te R21 49 9 a R23 R24 VCCI S nxor 220 220 PB7 gt gt PA 0 7 R25 49 9 C24 8 VCC 33 SES GND 0 1uF ant 10 eri AN2 12 cT2 gt gt P8 TEDINK HFJTT 2450E PC7 SPEED PCS C25 C26 C27 C28 C29 C30 C31 C32 C33 Some 0 001uF 0 001uF 0 001uF 0 001uF 0 001uF 0 001uF 0 001uF 0 001uF 0 001uF PD7 GND C38 C39 C40 cat Our Our Gu O 1UF l 1 1 VCC 33V WE VCC 33V MS HALT SLP Ver a IRL ezgocLk OK voc 33V CPU amp PHY Puig E END GND Figure 11 eZ80F91 Mini Enet Module Schematic 2 of 2 PRELIMINARY Schematics PA6_PWM2_EC1 PA5_PWM1 TOUTI PA4 PWMO TOUTO PA3 PWM3 OC3 PA2 PWM2 OC2 Pai PWM1 OC PAO_PWMO_OCO PB7_MOSI PB6_MISO PB5 83 PB4_ICA2 PB3_SCK PB2_SS PB1 IC1 PBO ICO 0 7 RI PC6 DCD1 PC5 DSR1 PC4 DTR1 PC3 CTS1 PC2 RTS1 PC1 RXD1 PCO TXD1 PD7 RIO PD6 DCDO PD5 DSRO PD4 DTRO PD3 CTSO PD2 RTSO PD1 RXDO IRRXD PDO_TXDO_IRTXD HALT_SLP PHI iNSTRD TDO TRIGOUT BUSREQ NMI TMS TCK TDI TRSTN RESET WP MIL_CRS MII COL MIL_RXER MIL_RXDV MIL_RXD3 MIL_RXD2 MIL_RXD1 MIL_RXDO MIL RXCLK MIILTXCLK FILT_IN XIN XOUT PLL_VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD PLL VSS vss vss v
14. this data from being received After the eZ80F91 Mini Enet Module com pletes transmitting this bit is changed to allow for incoming messages The code that follows provides an example of how this function is enabled on the eZ80F91 Mini Enet Module 1nit IRDA Make sure to first set PD2 as a port bit an output and set it Low PD ALT1 amp OxFC PDO uartOtx PD1 uartO rx PD ALT2 0x03 Enable alternate function UART LCTLO 0x80 Select dlab to access baud rate generator BRG_DLRLO 0x2F Baud rate Masterclock 16 baudrate BRG DLRH0 0x00 High byte of baud rate UART_LCTLO 0x00 Disable dlab UART_FCTLO 0xC7 Clear tx fifo enable fifo UART_LCTLO 0x03 8016 1 stop IR_CTL 0x03 enable IRDA Encode decode and Receive enable bit UM017001 0404 PRELIMINARY eZ80F91 Mini Enet Module eZ80F91 Modular Development Kit User Manual 28 ritoa TRDA_Xmit IR_CTL 0x01 Disable receive Putchar 0xb0 Output a byte to the uartO port Internal On Chip Flash Memory To program the 32K boot block on the internal on chip Flash memory shunt JP1 on the eZ80F91 Mini Enet Module must be installed Table 6 lists the settings shunt JP1 Table 6 Shunt JP1 eZ80F91 Mini Enet Module Shunt Symbol Jumper Name Siatus Function Affected Device JP1 F91 WE In Default On chip Flash is enabled for On chip Flash writing to boot block Out On chip Flash memory boot block On chip Flash
15. 24 External Flash Memory 25 Reset Generator wos isa ni ENEE ee Ae EM ee 25 IrDA Transceiver server oenen ner ene derden eens 26 Internal On Chip Flash Memory 28 Flash Loader Utility eeen eee eee eene 28 VAD DL en 2 ea Ge 29 EEN ale 31 OVervieW Aa a a be EE d Re a ek ee Rha ee dE d 31 IrDA Port Not Working 31 Contacting ZiLOG Customer Support 31 UM017001 0404 PRELIMINARY Table of Contents UM017001 0404 eZ80F91 Modular Development Kit User Manual 0 0 13 2 3 eek eZ80Acclaim MDS Adapter Board Schematic eZ80F91 Mini Ener Module Customer Feedback Form PRELIMINARY eZ80F91 Modular Development Kit User Manual vii List of Figures Figure 1 eZ80Acclaim MDS Adapter Board Block Diagram 3 Figure 2 eZ80F91 Mini Ener Module Block Diagram 4 Figure 3 eZ80Acclaim MDS Adapter Board Peripheral Bus Mini Module Connector J1 Pin Configuration eege MEETS 6 Figure 4 eZ80Acclaim MDS Adapter Board VO Mini Module Connector J2 10 Figure 5 eZ80Acclaim MDS Adapter Board Peripheral Bus External Connector JP 14 Figure 6 eZ80Acclaim MDS Adapter Board VO External Connector JP2 18 Figure 7 Possible Bus Contention without Fast Buffer
16. 3V 5 7 1 AT 3 E 21 2 Als AIS 23 2 A16 ES GND 2 AD G AT 5 33 AIT DIS FLASH A21 37 V M A22 is A23 Esc 4 1 E DC Di 5 45 02 D3 4 Os ri D7 En 2 DE MREG 53 4 JOREO FA 55 GA En 2 Een BUSACK ze 8 SUSREQ Figure 5 eZ80Acclaim MDS Adapter Board Peripheral Bus External Connector JP1 eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001 0404 15 eZ80F91 Modular Development Kit User Manual ziILOG Table 3 eZ80Acclaim MDS Adapter Board Peripheral Bus External Connector JP1 Identification Signal Direction Active Level eZ80F91 Signal n a Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes n a Low n a n a n a n a n a n a n a n a n a n a n a n a n a n a n a n a Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Symbol unused TRSTN 46 AO A10 A3 A8 A7 A13 A9 A15 A14 A18 A16 A19 A2 A1 Pin 1 4 6 8 35 5 11 12 13 14 17 18 19 20 21 22 23 24 25 27 28 Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board schematics on pages 33 through 34 2 The Power and Ground nets are connected direc
17. 98D y 2 VCC 33V TA vee 33V TC74LVCOB JTAG GND GND p INTERFACE 10K GND R8 TDI M TDO 1 2 TC74LVT125 M GND TVCC_RESETn 7 8 TMS 9 10 12 J6 13 144 HEADER 2 Figure 8 eZ80Acclaim MDS Adapter Board Schematic 1 of 2 PRELIMINARY UMO1 7001 0404 eZoUFy1 Modular Development Kit User Manual 7 7 e 34 5V VCC 5V 2 N o e gt gt VCC sv VCC_33V Cope RXE160 l C4 A C5 le PWR JACK 0 1 TX Zur z mE US T GND TC74LVCOB ku 3 GND 44 vout 33V VGC Vs voc aav TC74LVT125 5 A GND 6 eg M R9 LT1086 3 3 TO220 YA S uac 680 TC74LVCOB Lal 4 310 M U3c EE U4D TC74LVT125 TC74LVCOB POWER SUPPLY C8 13 VCC 33V GND 0 1uF n a U6 MAX3222 9 2 O 1uF 3 v 8 cio E SE GND ci HE PUR TC74LVT125 USD 2 o car c 2 9 0 1UF NIS 0 tuF P2 zo 74LV05 xl oH IZI THN H En Ta RTSO 8 i PD2 D 8 T2OUT T2IN o PD1 oi RxDO 1 1 Sos Oz SI RUIN pour
18. H VCC 33V 6 cTso 9 10 R2IN R20UT Use l DB9 FEMALE EN bl UBA J8 11 4 14 uc 2 ec SHDN 0 1 1 SHDN 2 m d 74LV05 END RS232 1 DIS GND U8C U8F U8B 74LV05 1 Ste 4 4 3 5 lt PB6 74LV05 74LV05 R10 R11 R12 R13 10K 10K 10K GND 10K VCC 33V Figure 9 eZ80Acclaim MDS Adapter Board Schematic 2 of 2 UMO1 7001 0404 PRELIMINARY Schematics eZoUFy1 Modular Development Kit User Manual eZ80F91 Mini Enet Module Figures 10 through 11 diagram the layout of the eZ80F91 Mini Enet Module The IrDA device is not installed on the module it appears for ft 35 ence purposes only connector 1 connector 2 VCC 33V up Ji J2 3 WP 2 AJO 23 A 0 23 pl VCC 33V gt 1 VCC_33V PA4 p 1 PA3 Ri SN74LVC2G04 Dior SZ R2 AU 4 3 AG PAS PAT 10K 10 7 R3 AZ 8 5 A7 PO e CS 0 3 ESL 4 7K A AT 8 7 8 PAT g PES CSa AS 10 9 ATO EZB CLK 0 g VCC 33V 12 11 CND PB7 2 11 PBT HEADER 2 VCC_33v lt lt IICSDA D5 14 ia RD PB3 a 13 Pa JP1 IICSCL 8 ICSCL D4 16 15 DT PC7 16 15 PAG F91 WE D2 18 1 DO PA2 18 1 PB4 R4 ci HALT SLP DE jo ATT GND GND T HALT SLP ee OD 21 GND 6 PE 1 AT A19 Pr Bl pcs 5 68R RTC VDD Am 2 ES pet Ha oe 330nF
19. The eZ80F91 Modular Develop ment Kit features an eZ80F91 Mini Enet Module and an eZ80Acclaim MDS Adapter Board onto which the module mounts Kit Features The key features of the eZ80F91 Modular Development Kit are e780F91 Mini Ener Module eZ80F9 device operating at 50 1112 with 256KB of internal Flash memory and 8KB of internal SRAM memory 128KB of off chip SRAM memory On chip Ethernet Media Access Controller EMAC Ethernet port and PHY Real Time Clock with battery backup Footprint for an SIR IrDA transceiver Two 56 pin mini module connectors for attachment to the eZ80Acclaim MDS adapter board eZ80Acclaim MDS Adapter Board Footprint for 2M x 8 external Flash memory such as AM29LV160D Footprint for 10 bit bus switch such as 74CBTLV 3384 to support external Flash RS232 connector with interface circuit for 0 ZDI and JTAG debug connectors UM017001 0404 PRELIMINARY Introduction eZ80F91 Modular Development Kit Two 56 pin mini module connectors Two 60 pin interface connectors for connection to an external application or development board not supplied 32 pin header and footprint fora GPRS modem One green 3 3 OK LED One yellow Test LED and pushbutton SVDC external power supply Serial Smart Cable eZ80Acclaim Software and Documentation CD ROM ZiLOG ZTP TCP IP stack CD ROM Schematics for the eZ80F91 Mini Ener Module and eZ80Acclaim MDS
20. anual 26 ritoa with a duration of 200ms if the power supply drops below 2 93 V This reset pulse ensures that the board always starts in a defined condition The RESET pin on the I O connector reflects the status of the RESET line It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80F91 Modular Development Kit with a low impedance output e g a 100 Ohm push button IrDA Transceiver The eZ80F91 Mini Enet Module is shipped without an IrDA transceiver installed If you install an on board transceiver such as the ZiLOG ZHX1810 it is connected to PDO TX PD1 RX and PD2 Shutdown IR_SD The IrDA transceiver is of the LED type 870nm Class 1 The IrDA transceiver is accessible via the IrDA controller attached to UARTO on the eZ80F91 device To use the UARTO as a console or to save power the transceiver can be disabled by the software or by an off board signal when using the proper jumper selection The transceiver is disabled by setting PD2 IRDA SD High or by pulling the DIS_IRDA pin on the I O connector Low The shutdown feature is used for power savings To enable the IrDA trans ceiver DIS_IRDA is left floating and PD2 is pulled Low The RxD and TxD signals on the transceiver perform the same functions as a standard RS232 port However these signals are processed as IrDA 3 16 coding pulses sometimes called IrDA encoder decoder pulses When the IrDA function is enabled the final
21. cclaim MDS adapter board schemat ics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device eZ80Acclaim MDS Adapter Board Jumper Settings The eZ80Acclaim MDS adapter board contains four jumpers that are described in Table 5 eZ80Acclaim MDS Adapter Board Jumper SettingsPRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual 21 ritoa Table 5 eZ80Acclaim MDS Adapter Board Affected Device On board Flash when installed On board Flash when installed DB9 connector P2 IrDA transceiver when installed Jumper Settings Function On board Flash is enabled On board Flash is disabled On board Flash is disabled for writing On board Flash is enabled for writing RS232 output on connector P2 is disabled RS232 output on connector P2 is enabled IrDA transceiver on eZ80F91 Mini Enet Module is disabled IrDA transceiver on eZ80F91 Mini Enet Module is enabled Jumper Name Position J4 EL EN IN Default OUT J6 FL WEN IN OUT J8 RS232 1 DIS IN OUT J9 IRDA DIS IN Default OUT Notes 1 If AM29LV160 is used J6 and R6 should be OUT If AT49BV162 is used R6 should be IN and J6 should be OUT 2 Jumper J9 functions only when user has installed IrDA transceiver on eZ80F91 eZ80Acclaim MDS Adapter Board PRELIMINARY Mini Enet Module UM017001 0404 eZ80F91 Modular Development Kit
22. ges 33 through 34 2 Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the 6280 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UM017001 0404 PRELIMINARY eZ80F91 Mini Enet Module Interface eZ80F91 Modular Development Kit User Manual ziILOG 9 Table 1 eZ80Acclaim MDS Adapter Board Peripheral Bus Connector J1 Identification Continued Pin Symbol Signal Direction Active Level eZ80F91 Signal Note 44 Aii Bidirectional n a Yes 45 A14 Bidirectional n a Yes 46 A9 Bidirectional n a Yes 49 A16 Bidirectional n a Yes 50 A5 Bidirectional n a Yes 51 A15 Bidirectional n a Yes 52 A4 Bidirectional n a Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board sche matics on pages 33 through 34 2 Additional note external capacitive loads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive
23. h impedance state For fur ther information see the MT28F008 data sheet on www micron com eZ80F91 Mini Enet Module PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa 23 CPU Clock cso eZ80F91 Data Bus Flash Data Bus CS1 WR Figure 7 Possible Bus Contention without Fast Buffer Essentially after the eZ80F91 device accesses Flash memory a time duration of 8 8ns 25ns 33 8ns can transpire before Flash memory stops driving the data bus At that time the eZ80F91 device is well into the next bus cycle Assuming this next cycle is the Memory Write cycle then the data output of the eZ80F91 device is valid not later than T3 7 5ns and the write pulse is asserted not later than 4 5ns after the falling edge of the CPU Clock 14 5ns from the rising edge if the CPU Clock is S0MHz The duration of bus contention Tcon is 33 8ns 7 58 26 3ns Refer to the External Memory Write Timing diagram in the eZ80F91 Product Specification PS0192 for assistance UM017001 0404 PRELIMINARY eZ80F91 Mini Enet Module eZ80F91 Modular Development Kit User Manual 24 ritoa With the addition of a Fast buffer Flash turn off time is reduced from 25ns to 5 5ns Bus contention can still occur but the amount of time it consumes is not Tcon 26 3 ns but rather Tcon 8 8 ns 7 5ns 5 5ns 6 88 At this faster rate data that is being written does not become cor rupted because the write pulse is not yet a
24. levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UM017001 0404 PRELIMINARY eZ80Acclaim MDS Adapter Board eZ80F91 Modular Development Kit User Manual 10 ritoa UO Mini Module Connector J2 Figure 4 illustrates the pin layout of the 56 pin Peripheral Bus Mini Module Connector J1 on the eZ80Acclaim MDS adapter board Table 2 identifies the pins and their functions J2 F 2 PA3 4 PA 8 VCCO 33V dn 2 S Zen e 7 4 zc 3 Di 22 2 ET 2i cS 2 Iz 28 27 we 3 F PO A3 M 55 4 3 CO d an PO 4 3 TOO A 5 e d p 7 No NCSCL 5 3 MEJA NCSDA z2 NAT RU 3 Figure 4 eZ80Acclaim MDS Adapter Board UO Mini Module Connector J2 eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa 11 Table 2 eZ80Acclaim MDS Adapter Board UO Mini Module Connector J2 Identification Pin Symbol Signal Direction Active Level eZ80F91 Signal 1 PA3 Bidirectional n a Yes 2 PA4 Bidirectional n a Yes 3 PA7 Bidirectional n a Yes 4 PA5 Bidirectional n a Yes 5 PB5 Bidirectional n a Yes 6 PAO Bidirectional n a Yes 7 PB6 Bidirectional n a Yes 8 PA1 Bidirectional n a Yes 10 EZ80CLK Output n a Yes 11 PB1 Bidirectional n a Yes 12 PB7 Bidirectional n a Yes 13 PC4 Bidirectional n a Yes 14 PB3 Bidirectio
25. nal n a Yes 15 PA6 Bidirectional n a Yes 16 7 Bidirectional n a Yes 17 PB4 Bidirectional n a Yes 18 PA2 Bidirectional n a Yes 21 PB3 Bidirectional n a Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board schematics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device UM017001 0404 PRELIMINARY eZ80Acclaim MDS Adapter Board eZ80F91 Modular Development Kit Table 2 eZ80Acclaim MDS Adapter Board 1 Signal Direction Active Level eZ80F91 Signal Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes n a n a n a n a n a n a n a n a n a n a n a n a n a Low n a n a n a n a Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Output Input Bidirectional Bidirectional HO Mini Module Connector J2 Identification User Manual Pin Symbol 22 PBO 23 PC6 24 PC5 25 PC3 26 PC1 27 2 28 PCO 31 TMS 32 PD7 33 PD6 34 PD5 35 PD3 36 PD4 37 TRSTN 38 TRIGOUT 41 TCK 42 PD1 43 TDI Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire i
26. not authorized No licenses are conveyed implicitly or otherwise by this document under any intellectual property rights PRELIMINARY UMO017001 0404 eZ80F91 Modular Development Kit User Manual zivoa M Safeguards The following precautions must be observed when working with the devices described in this document N Caution Always use a grounding strap to prevent damage resulting from electrostatic discharge ESD UMO17001 0404 PRELIMINARY Safeguards eZ80F91 Modular Development Kit User Manual IV PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa V Table of Contents Safeguamds ast sn ik ee Iu Dev ERO en a dek EA d y EEN ans ii Table of Contents sara derden P OE RR RR TRO ned V List of Figures esie eR Oque care ae vii Last Of l ables ioi ua ae ix 1 Kit Fe tures u Re lebe ER aan ERR REN ds 1 6 8091 Modular Development Kit Overview seus 3 eZ80Acclaim MDS Adapter Board 5 eZ80F9 Mini Ener Module Interface 5 eZ80Acclaim MDS Adapter Board Jumper Settings 20 eZ80F91 Mini Enet Module 22 Functional Description 22 Past Buller ie wharves see adem site ive 22 Operational Description 24 eZ80F91 Mini Enet Module Memory
27. nterface is represented in the eZ80Acclaim MDS adapter board schematics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device UM017001 0404 PRELIMINARY eZ80F91 Mini Enet Module Interface 12 eZ80F91 Modular Development Kit User Manual 13 Table 2 eZ80Acclaim MDS Adapter Board UO Mini Module Connector J2 Identification Pin Symbol Signal Direction Active Level eZ80F91 Signal 44 PDO Bidirectional n a Yes 45 PD2 Bidirectional n a Yes 46 TDO Output n a Yes 49 DIS IRDA Input Low No 50 IICSCL UO n a Yes 51 WAIT Input Low Yes 52 IICSDA UO n a Yes 53 RST Low Yes 54 NMI Input Low Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board schematics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device UM017001 0404 PRELIMINARY eZ80Acclaim MDS Adapter Board eZ80F91 Modular Development Kit User Manual 14 ritoa Peripheral Bus External Connector JP1 Figure 5 illustrates the pin layout of Peripheral Bus External Connector JP2 in the 60 pin header on the eZ80Acclaim MDS adapter board Table 3 identifies the pins and their functions connector 1 3 TRSTN 6 GND 5 VCC 33V 1 14 A GND 5 1 HE 3
28. oads on RD WR IORQ MREQ D0 D7 and A0 A23 should be below 10pF to satisfy the timing requirements for the eZ80 CPU All unused inputs should be pulled to either Vpp or GND depending on their inactive levels to reduce power consumption and to reduce noise sensitivity To prevent EMI the EZ80CLK output can be deactivated via software in the eZ80F91 s Peripheral Power Down Register UM017001 0404 PRELIMINARY eZ80Acclaim MDS Adapter Board Note eZ80F91 Modular Development Kit User Manual Table 1 eZ80Acclaim MDS Adapter Board Peripheral Bus Connector J1 Identification Continued Signal Direction Active Level eZ80F91 Signal Yes Yes Yes Yes Yes Yes Yes No Jumper on board Yes Yes Yes Yes Yes Yes Yes Yes n a n a n a n a n a Low Low Low Low n a n a n a Low n a Low n a Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Output Input Output Bidirectional Input Bidirectional Output Bidirectional Ouput Bidirectional a Symbol A19 A18 A21 A20 A23 C80 C53 F91 WE CSO D3 RTC_Vpp D7 HALT_SLP A13 WR A12 rita Pin 23 24 25 26 27 28 29 33 34 35 36 39 40 41 42 43 Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board sche matics on pa
29. output to the RxD and TxD pins are routed through the 3 16 pulse generator Another signal that is used in the eZ80F91 Mini Enet Module s IrDA sys tem is Shut Down SD The SD pin is connected to PD2 on the eZ80F91 Mini Enet Module The IrDA control software on the user s wireless device must enable this pin to wake the IrDA transceiver The SD pin must be set Low to enable the IrDA transceiver On the eZ80F91 Mini Enet Module a two input OR gate is used to allow an external pin to shut Operational Description PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa 27 down the IrDA transceiver Both pins must be set Low to enable this func tion The eZ80F91 Mini Enet Module features an Infrared Encoder Decoder register that configures the IrDA function This register is located at address OBFh in the internal I O register map The Infrared Encoder Decoder register contains three control bits Bit 0 enables or disables the IrDA encoder decoder block Bit 1 if it is set enables received data to pass into the UARTO Receive FIFO data buffer Bit 2 is a test function that provides a loopback sequence from the TxD pin to the RxD input Bit 1 the Receive Enable bit is used to block data from filling up the Receive FIFO when the eZ80F91 Mini Enet Module is transmitting data Because IrDA signal passes through the air as its transmission medium transmitted data can also be received This Receive Enable bit prevents
30. pin layout of the 56 pin Peripheral Bus Mini Mod ule Connector J1 on the eZ80Acclaim MDS adapter board Table 1 identifies the pins and their functions VCC 33V VCC 33V m E D Da 4 1 1 47 DE E 3 17 22 2 GND 2 2 1 25 2 2 2 27 5 23 1 33V 2 VCC 33V SH ai UD GND 7 N ALT 57 EA gt 3 4 A12 AS AL r 23 A16 vi 2 A15 q V VCC_SRAI Figure 3 eZ80Acclaim MDS Adapter Board Peripheral Bus Mini Module Connector J1 Pin Configuration eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual 047 Table 1 eZ80Acclaim MDS Adapter Board Peripheral Bus Connector J1 Identification Pin Symbol Signal Direction Active Level eZ80F91 Signal Note 3 A6 Bidirectional n a Yes 4 AO Bidirectional n a Yes 5 A7 Bidirectional n a Yes 6 A2 Bidirectional n a Yes 7 A8 Bidirectional n a Yes 8 Al Bidirectional n a Yes 9 A102 Bidirectional n a Yes 10 A3 Bidirectional n a Yes 13 RD Output Low Yes 14 D5 Bidirectional n a Yes 15 D1 Bidirectional n a Yes 16 D4 Bidirectional n a Yes 17 DO Bidirectional n a Yes 18 2 Bidirectional n a Yes 19 A17 Bidirectional n a Yes 20 D6 Bidirectional n a Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board sche matics on pages 33 through 34 2 Additional note external capacitive l
31. pport Problem Description or Suggestion Provide a complete description of the problem or your suggestion If you are reporting a specific problem include all steps leading up to the occurrence of the problem Attach additional pages as necessary UM017001 0404 PRELIMINARY Customer Feedback Form
32. ss vss vss vss vss vss vss vss vss vss vss vss vss vss RTC_VDD RTC_XOUT RTC_XIN eZ80F91_BGA D 0 7 5 Do T war y AIT VCC 33V BUSREQ urd 10K wu y HM 6 TMS IMS TCK TDI TRSTN X CTRSTN 110g mer D I pd ror we EMP CRS pg ch rxv H GND RHXD3 2H AA an RXD2 5 0 056uF 8 RXDO Eg EIS 499 XCLK 06 270pF FILT IN Jio Ya XIN Hit sue 0 ous R19 C23 38 C22 18pF Wa VCC 33 RTC_VDD BIG VOD __ Y3 1 1 T 32 768KHz J 4 4 M8 c5 oe 22pF 22pF GND UMO1 7001 0404 eZ80F91 Modular Development Kit User Manual ziILOG 37 Customer Feedback Form If you note any inaccuracies while reading this User Manual please copy and complete this form then mail or fax it to ZiLOG see Return Information below We also welcome your sugges tions eZ80F91 Modular Development Kit Serial or Board Fab Rev Software Version Document Number Host Computer Description Type Customer Information Name Country Company Phone Address Fax City State Zip E Mail Return Information ZiLOG System Test Customer Support 532 Race Street San Jose CA 95126 Phone 408 558 8500 Fax 408 558 8536 ZiLOG Customer Su
33. sserted As of the date of publication of this document ZiLOG has not completed an analysis of the effect that this 6 8ns period of bus contention has on the design An Application Note from Cypress Semiconductor titled NoBL SRAM and Bus Contention further explains this bus contention issue Operational Description The purpose of the eZ80F91 Mini Enet Module as a feature of the eZ80F91 Modular Development Kit is to provide application developers with a design platform that enables them to make use of such eZ80F91 device features of the as on chip EMAC SRAM Flash etc eZ80F91 Mini Enet Module Memory Static RAM The eZ80F91 Mini Ener Module features 128 KB of fast SRAM Access speed is typically 12ns allowing zero wait state operation at 50MHz With the CPU at 50MHz SRAM can be accessed with zero wait states in eZ80 mode CS CTL CSI can be set to 08h no wait states gt Note The eZ80F91 Mini Enet Module is shipped with SRAM powered from the same power supply as the eZ80F91 device The SRAM may also be powered separately by battery To power SRAM from battery 1 Remove R15 2 Ensure that R14 is in place 3 Connect battery to GND 4 Connect battery to J10 Operational Description PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual 25 Flash Memory The eZ80F91 Mini Ener Module features 256 KB of on chip Flash mem ory which can be programmed a single byte at a time or in bursts of
34. ter Board Schematic Figures 8 and 9 provide a schematic for the eZ80Acclaim MDS adapter board The SRAM chip U2 and buffer U1 are not installed they are shown for reference purposes only Ji J2 r3 VCC 33V 2 1 VCO 33V PA4 PA3 AO 4 3 AG 5 4 PAT A A 5 Nr GAR 5 P OR vcc 33V A3 1 ATO EZB 1 VCC 33v GND GND PBT 21 e PBT J10 D5 14 ig RU PB3 i4 1 PCE 1 i pH BD Paz Hs Tor 18 1 4 e am HZ HEADER 1 GND ion Peo es 4 A8 24 23 A18 PCS PCS A20 AZT ru ror VCC SRAM R2 R22 28 L2 RES SS 27 EE 220 CS0 29 CS3 30 GND VCC 38V 39 31 VCC 38V PD7 32 a 1MS RTC VDD Em 5 S PD3 GND Lx Tas Laz Tem HATT SU 40 D7 Zw WR 42 41 A3 PDT 42 41 TCK F an Doi Hz 46 45 Als 46 45 48 4 GND 48 4 d A5 50 49 A16 IICSCL 50 49 DIS IRDA LN a AB lICSDA 2 51 WAT VCC SRAM Zi 56 38 wt SRAN x voc 56 L CC 33V EH E HEADER 28x2 HEADER 28x2 MINI MODULE CONNECTORS ut Do F DO my ein DE Or ps 1 9 188 Hm Dr 184184 D oi 10 ED VCC 33V 1A5 1B5 I D5 F D5 w Ha a Hi pr H 2a2 282 Dy d Of ta 28 2B3 Lig i di GND 2A4 2B4 GND 2A5 8 24 VCO 33V 1 FLASH EN Ix Kl ZDI 2 T i INTERFACE 74CBTLV3384 SO 0 001uF 5 VCC 33V PRSTn TCK HEADER 2 CS3 GND TDT RS 10K Header 3x2 R6 RST VCC 33V VCC 33V 10K RESET ER uaa 3 s2 pec LA ya i 15 2
35. tly to the eZ80F91 device eZ80Acclaim MDS Adapter Board PRELIMINARY UM017001 0404 eZ80F91 Modular Development Kit User Manual ritoa Table 3 eZ80Acclaim MDS Adapter Board Peripheral Bus External Connector JP1 Identification Pin Symbol Signal Direction Active Level eZ80F91 Signal 29 A11 Bidirectional n a Yes 30 A12 Bidirectional n a Yes 31 A4 Bidirectional n a Yes 32 A20 Bidirectional n a Yes 33 A5 Bidirectional n a Yes 34 A17 Bidirectional n a Yes 36 DIS FLASH Input Low Mo 37 A21 Bidirectional n a Yes 39 A22 Bidirectional n a Yes 40 A23 Bidirectional n a Yes 41 CSO Output Low Yes 42 CS1 Output Low Yes 43 CS2 Output Low Yes 44 49 D 0 5 Bidirectional n a Yes 51 D7 Bidirectional n a Yes 52 D6 Bidirectional n a Yes 53 MREQ Output Low Yes 54 IOREQ Output Low Yes Notes 1 For the sake of simplicity in describing the interface Power and Ground nets are omitted from this table The entire interface is represented in the eZ80Acclaim MDS adapter board schematics on pages 33 through 34 2 The Power and Ground nets are connected directly to the eZ80F91 device eZ80F91 Mini Enet Module Interface PRELIMINARY 4 eZ80F91 Modular Development Kit User Manual ritoa 17 Table 3 eZ80Acclaim MDS Adapter Board Peripheral Bus External Connector JP1 Identification Signal Direction Active Level eZ80F91 Signal
36. up to 256 bytes Write operations can be performed using either memory or I O instructions Erasing bytes in Flash memory returns them to a value of FFh Both the MASS ERASE and PAGE ERASE operations are self timed by the Flash controller leaving the CPU free to execute other oper ations in parallel Upon power up the on chip Flash memory is located in the address range 000000h 03FFFFh Four wait states are programmed in Flash control register F8h On chip Flash memory is prioritized over all external Chip Selects can be enabled or disabled power on enabled and can be programmed within any 256KB address space in the 16MB address range The eZ80F91 Mini Enet Module features the following memory configu rations e On chip SRAM 8KB Off chip SRAM 128KB On chip Flash 256KB Refer to the 62801791 Product Specification PS0192 for details on pro gramming internal Flash memory External Flash Memory The eZ80F91 Mini Enet Module provides a footprint for 2MB of external Flash The module supports additional external Flash devices via the full system bus which is available on the expansion interface connectors Reset Generator A supervisory chip on the eZ80Acclaim MDS adapter board is connected to the eZ80F91 Reset input pin via pin 53 of mini module connector J2 It performs reliable Power On Reset functions generating a reset pulse UM017001 0404 PRELIMINARY eZ80F91 Mini Enet Module eZ80F91 Modular Development Kit User M
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