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NB3N502DEVB Evaluation Board User`s Manual
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1. CLK DUT 5 Real Time Oscilloscope High Z Probe CLKOUT H ml CREE Figure 5 Typical Setup Table 5 PARTS LIST Manufacturer Ref Number MM Notes 1 and 2 22 uF 1095 Size C Tantalum Capacitor T494C226K016AT KEMET 0 01 uF 10 0603 Ceramic Capacitors 06035C103KAT2A 0 1 uF 10 0603 Ceramic Capacitors 06035C104KAT2A NB3N502 8 pin SOIC Pb Free ON Semiconductor SW1 SW4 Slide Switches 3 Position Miniature OS103011MS8QP1 J1 J6 6 SMA Edge Mount Connectors 142 0711 821 JMP1 JMP4 Jumper Header 100 mil 2 pins 1 row SPC20485 Vpp Plug Banana Plug Red 571 0500 GND Plug Banana Plug Black 571 0100 1 Specified parts are ROHS Compliant 2 Only RoHS compliant parts may be substituted http onsemi com 4 NB3N502DEVB BOARD LAYOUT The evaluation board is constructed with Getek material with 50 Q trace impedances and is designed to minimize noise achieve high bandwidth and minimize crosstalk Layer Stack L1 Signal L2 Ground L3 Vpp L4 Signal X1 CLK Se Figure 7 NB3N502 Evaluation Board SMA Ground Layer http onsemi com 5 NB3N502DEVB X1 CLK X2 S1 REF so 1741 ON Semiconductor OLK EVALUA FDN BOARD ali Figure 8 NB3N502 Evaluation Board Power Layer 12 04 480 858 1882 L SE a T E E p Figure 9 NB3N502 Evaluation Board Bottom Layer
2. Supply Voltmeter High Speed Cables with SMA Connectors High Impedance Probe Power Supply Connections External power supply of 3 V to 5 5 V must be provided to the board The NB4N502 has a positive supply pin Vpp and a ground pin GND Connect a single power supply to the evaluation board see Figure 2 by connecting Vpp to the positive supply 3 V to 5 5 V and GND to 0 V Power supply banana plug connectors for Vpp and GND are provided at the top corners of the board Table 1 POWER SUPPLY CONNECTIONS 3 to 45 5 V Hed Banana Plug Power Supplies GND 3 0 V to 25 5 V Figure 2 Power Supply Connections External Reference Clock An SMA connector is provided for X1 CLK if an external clock source is used on Pin 1 The metal trace at the package pin is intentionally open for crystal use and must be shorted for a connection to Pin 1 for external clock use Crystal and Crystal Load Capacitors Selection Guide A through hole or surface mount crystal can be used The metal traces at the crystal pins are intentionally open for crystal use and will have no impedance effect on the crystal pins The total on chip capacitance is approximately 12 pF per pin CIN1 and CIN2 A parallel resonant fundamental mode crystal should be used The evaluation board includes pads for small capacitors from X1 CLK to ground and from X2 to ground These capacitors CL1 and CL2 are used to adjust the stray capacitance
3. http onsemi com 6 NB3N502DEVB Figure 11 NB3N502 Evaluation Board Bottom Assembly http onsemi com 7 NB3N502DEVB ON Semiconductor and uJ are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized applic
4. of the board to match the nominally required crystal load capacitance CLOAD crystal Crystal load capacitors must be connected from each of the pins X1 and X2 to ground The load capacitance of the crystal CLOAD crystal must be matched by total load capacitance of the oscillator circuitry network CINX CSX and CLX as seen by the crystal see Figure 3 and equations below CLOAD1 CS1 Total capacitance on XI CLK CLOAD2 CIN2 CS2 CL2 Total capacitance on X2 CIN2 12 pF Typ Internal capacitance CS1 CS2 5 pF Typ External PCB stray capacitance CLOAD1 2 2 CLOAD Crystal CL2 CLOAD2 CIN2 CS2 External load capacitance on X2 CL1 CLOAD1 CIN1 CS1 External load capacitance on X1 CLK ag maalt M dc gy es eee SE Internal R to Device Crystal Figure 3 Using a Crystal as Reference Clock Control and Select Pins The NB4N502 evaluation board is equipped with SMA connectors to control the static input logic levels of the Multiplier Select pins SO and S1 see Table 2 Pin S1 defaults to M when left open Pin SO defaults to H when left open 3 Position slide switches are also provided to control the Multiplier Select pins To use the switches headers JMP3 and JMP4 must be shorted http onsemi com 2 NB3N502DEVB 1 Using the SMA Connectors Table 2 CLOCK MULTIPLIER SELECT TABLE a SMA connectors J3 and J4 DUT 6 and DUT 7 should be pu
5. NB3N502DEVB NB3N502DEVB Evaluation Board User s Manual Description The NB3N502 Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the performance and operation of the NB3N502 PLL Clock Multiplier This user s manual provides detailed information on the board s contents layout and use and it should be used in conjunction with the NB3N502 data sheet which contains full technical details on device specifications and operation www onsemi com Board Features e Fully Assembled Evaluation Board e Accommodates the Electrical Characterization of the NB3N502 in the SOIC 8 Package ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL e Supports the Use of a 5 MHz to 27 MHz Through hole or Surface Mount Crystal e SMA Connectors are Provided for Auxiliary Input and Output Interfaces Incorporates Onboard Slide Switch Controlled Multiplier Select Pins Minimizing Excess Cabling This Evaluation Board Manual Contains e Information on the NB3N502 Evaluation Board Appropriate Lab Setup e Evaluation Board Layout Bill of Materials Figure 1 NB3N502 Evaluation Board Semiconductor Components Industries LLC 2012 February 2012 Rev 1 Publication Order Number EVBUM2064 D NB3N502DEVB SETUP FOR MEASUREMENTS Basic Eguipment e Signal Generator for External Reference Clock Input e Oscilloscope Power
6. ation Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative EVBUM2064 D
7. lled to Vcc for logic level HIGH pulled to GND for logic level LOW and left OPEN for logic level M 2 Using the Slide Switches a Header pins JMP3 and JMP4 enable the slide switches for the clock multiplier select lines SO and S1 and should be jumpered b Switches SW3 DUT 6 and SW4 DUT 7 are used to select the clock multiplier value see Table 2 L GND OPEN unconnected The H position of the slide switch asserts a Pin 51 defaults to M when left open logic HIGH on the assigned pin the L asserts a Pin SO defaults to H when left open logic LOW and the M is an open where the pin floats to mid logic level by way of the device s internal pullup and pulldown resistors Table 3 HEADER PIN CONDITIONS Header Multiplier Control Multiplier Control Output Connections Connect the CMOS TTL outputs REF and CLKOUT to the oscilloscope Table 4 OUTPUT CONNECTORS Board Connector BUTS CLKOUT J2 DUT 5 Reference Clock Figure 4 NB3N502 Logic Diagram http onsemi com 3 NB3N502DEVB Open Traces Intentional VDD For Crystal Use DUT 1 If using the slide switches in stead of provided SMA con SMA DUT GND Signal Generator nectors short JMP3 and JMP4 see Table 3 L OUT 2 MHz to 50 MHz 50 Q Optional Vpp for Logic H 51 Open for Logic GND for Logic L 50 for Logic H GND for Logic L
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