8088 8-BIT HMOS MICROPROCESSOR 8088 8088-2
Contents
1. 76543210 76543210 76543210 11101001 disp low disp high 11101011 disp 11111111 mod 100r m 11101010 offset low offset high seg low seg high 11111111 mod 10 1 11000011 11000010 data low data high 11001011 11001010 data low data high 01110100 disp 01111100 disp 01111110 disp 01110010 disp 01110110 disp 01111010 disp 01110000 disp 01111000 disp 01110101 disp 01111101 disp 01111111 disp 01110011 disp 01110111 disp 01111011 disp 01110001 disp 01111001 disp 11100010 disp 11100001 disp 11100000 disp 11100011 disp 11001101 type 11001100 11001110 11001111 29 8088 ntel 8086 8088 Instruction Set Summary Continued Instruction Code 76543210 76543210 PROCESSOR CONTROL CLC Clear Carry 11111000 CMC Complement Carry 11110101 STC Set Carry 11111001 CLD Clear Direction 11111100 STD Set Direction 11111101 CLI Clear Interrupt 11111010 STI Set Interrupt 11111011 HLT Halt 311110100 WAIT Wait 10011011 ESC Escape to External Device 11011xxx mod x x x r m LOCK Bus Lock Prefix 11110000 NOTES AL 8 bit accumulator AX 16 bit accumulator CX Count register DS Data segment ES Extra segment Above bel2. AMWCI NC 5 TORE Bus ___ DEN OWC DTR AIOWC NC INTA T LATCH 0 2083 T ADDRESS TRANSCEIVER DATA 4 00 bw RAM 2 MCS 80 PERIPHERAL 8259A INTERRUPT CONTROL 7 231456 7 Figure 7 Fully Buffered System Using Bus Controller 8088 intel Bus Operation id throughout each bus cycle In addition the bus can be demultiplexed at the processor with a single The 8088 address data bus is broken into three address latch if a standard non multiplexed bus is parts the lower eight address data bits ADO desired for the system AD7 the middle eight address bits 8 15 and the upper four address bits 16 19 The ad Each processor bus cycle consists of at least four dress data bits and the highest four address bits are CLK cycles These are referred to as T1 T2 T3 and time multiplexed This technique provides the most 4 See Figure 8 The address is emitted from the efficient use of pins on the processor permitting the processor during T1 and data transfer occurs on the use of a standard 40 lead package The middle eight bus during T3 and T4 T2 is used primarily for chang address bits are not multiplexed i e they remain val 4 Tcv M 4 Tcv wo poma wmi on GOES INACTIVE THE STATE JUST PRIOR TO T ALE 52 50 ADDR STATUS X 57 8 X mons 57 53
3. TE cae 5088 COPROCESSOR Ap Lock SEE NOTE 1 NOTE 231456 19 1 The coprocessor may not drive the busses outside the region shown without risking contention HOLD HOLD ACKNOWLEDGE TIMING MINIMUM MODE ONLY gt 1 CLK CYCLE 1 OR 2 CYCLES CLK THVCH THVCH HOLD TCLHAV He ICLHAV p HLDA pM lt lt lt 8088 COPROCESSOR 8088 1 231456 20 25 8088 in 8086 8088 Instruction Set Summary Instruction Code DATA TRANSFER MOV Move 76543210 76543210 76543210 76543210 Register Memory to from Register 100010dw mod reg Immediate to Register Memory 1100011w mod000r m data data 1 Immediate to Register 1011wreg data data if w 1 Memory to Accumulator 1010000w addr low addr high Accumulator to Memory 1010001w addr low addr high Register Memory to Segment Register 10001110 mod 0 reg r m Segment Register to Register Memory 10001100 mod 0 reg r m PUSH Push Register Memory 11111111 1 1 Register 01010reg Segment Register 000reg110 POP Pop Register Memory 10001111 mod000r m Register 0101 1 Segment Register 000reg111 XCHG Exchange Register Memory with Register 1000011w mod reg r m Register with Accumulator 10010reg IN Input from Fixed Port 1110010w port Variable Port 1110
4. ADDR 5 8 BUS RESERVED DrD ADDRIDATA quor INS a 22 READY WAIT DEN MEMORY ACCESS TIME 231456 8 Figure 8 Basic System Timing 10 intel ing the direction of the bus during read operations In the event that a NOT READY indication is given by the addressed device states Tw are serted between T3 and T4 Each inserted wait state is of the same duration as a CLK cycle Periods can occur between 8088 driven bus cycles These are referred to as idle states Ti or inactive CLK cycles The processor uses these cycles for internal housekeeping During T1 of any bus cycle the ALE address latch enable signal is emitted by either the processor or the 8288 bus controller depending on the MN MX strap At the trailing edge of this pulse a valid ad dress and certain status information for the cycle may be latched Status bits 50 S1 and S2 are used by the bus con troller in maximum mode to identify the type of bus transaction according to the following table 52 1 50 Characteristics O LOW 0 0 Interrupt Acknowledge 0 0 1 Read I O 0 1 0 Write I O 0 1 1 Halt 1 HIGH 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive No Bus Cycle Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 throu
5. SEGMENT REGISTER FILE OFFSET 7 0 0 7 FFFFFH CODE SEGMENT XXXXOH STACK SEGMENT DATA SEGMENT 1 7 900008 231456 3 Figure 3 Memory Organization FUNCTIONAL DESCRIPTION Memory Organization The processor provides a 20 bit address to memory which locates the byte being referenced The memo ry is organized as a linear array of up to 1 million bytes addressed as 00000 H to FFFFF H The memory is logically divided into code data extra data and stack segments of up to 64K bytes each with each segment falling on 16 byte boundaries See Figure 3 All memory references are made relative to base ad dresses contained in high speed segment registers The segment types were chosen based on the ad dressing needs of programs The segment register to be selected is automatically chosen according to the rules of the following table All information in one segment type share the same logical attributes e g code or data By structuring memory into relocat able areas of similar characteristics and by automati cally selecting segment registers programs are shorter faster and more structured Word 16 bit operands can be located on even or odd address boundaries For address and data oper ands the least significant byte of the word is stored in the lower valued address location and the most significant byte in
6. TCL2CL1 CLK Fall Time 10 10 ns From 3 5V to 1 0V TDVCL Data in Setup Time 30 20 ns TCLDX Data in Hold Time 10 10 ns TR1VCL RDY Setup Time into 8284 35 35 ns Notes 1 2 TCLR1X RDY Hold Time into 8284 0 0 ns Notes 1 2 TRYHCH READY Setup Time into 8088 118 68 ns TCHRYX READY Hold Time into 8088 30 20 ns TRYLCL READY Inactive to CLK 8 8 ns Note 4 TINVCH Setup Time for Recognition 30 15 ns INTR NMI TEST Note 2 TGVCH RQ GT Setup Time 30 15 ns TCHGX RQ Hold Time into 8088 40 30 ns TILIH Input Rise Time Except CLK 20 20 ns From 0 8V to 2 0V TIHIL Input Fall Time Except CLK 12 12 ns From 2 0V to 0 8V 21 8088 intel A C CHARACTERISTICS Continued TIMING RESPONSES 8088 8088 2 i Test Symbol Parameter Min Max Min Max Units Conditions TCLML Command Active Delay 10 35 10 35 ns Note 1 TCLMH Command Inactive Delay 10 35 10 35 ns Note 1 TRYHSH READY Active to 110 65 ns Status Passive Note 3 TCHSV Status Active Delay 10 110 10 60 ns TCLSH Status Inactive Delay 10 130 10 70 ns TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns TSVLH Status Valid to ALE High 15 15 ns Note 1 TSVMCH Status Valid to MCE High 15 15 ns Note 1 TCLLH CLK Low to ALE Valid 1
7. ror Warp 231456 10 Figure 10 Medium Complexity System Timing 15 8088 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Case Temperature Plastic 0 C to 95 C Case Temperature CERDIP 0 C to 75 Storage Temperature 65 C to 150 C Voltage on Any Pin with Respect to Ground 1 0 to 7V Power 5 5 2 5 Watt D C CHARACTERISTICS intel NOTICE This is a production data sheet The specifi cations are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability TA 0 C to 70 Tcase Plastic 0 C to 95 C Tease CERDIP 0 C to 75 Ta 0 C to 55 C and 0 C to 75 C for P8088 2 only TA is guaranteed as long as is not exceeded 5V 10 for 8088 5V 5 for 8088 2 and Extended Temperature EXPRESS Symbol Parameter Min Max Units Test Conditions VIL Input Low Voltage 0 5 0 8 V Note 1 Input High Voltage 2 0 Voc 0 5 V Notes 1 2 VoL Output Low Voltage 0 45 V lo 2 0 mA VoH Output High Vo
8. 1 0 Write Memory 1 1 1 Passive intel 8088 Table 1 Pin Description Continued Symbol Pin No Type Name and Function RQ GTO 30 31 REQUEST GRANT pins are used by other local bus masters to force the RQ GT1 processor to release the local bus at the end of the processor s current bus cycle Each pin is bidirectional with RQ GTO having higher priority than RQ GT1 RQ GT has an internal pull up resistor so may be left unconnected The request grant sequence is as follows See Figure 8 1 A pulse of one CLK wide from another local bus master indicates a local bus request hold to the 8088 pulse 1 2 During a T4 or TI clock cycle a pulse one clock wide from the 8088 to the requesting master pulse 2 indicates that the 8088 has allowed the local bus to float and that it will enter the hold acknowledge state at the next CLK The CPU s bus interface unit is disconnected logically from the local bus during hold acknowledge The same rules as for HOLD HOLDA apply as for when the bus is released 3 A pulse one CLK wide from the requesting master indicates to the 8088 pulse 3 that the hold request is about to end and that the 8088 can reclaim the local bus at the next CLK The CPU then enters T4 Each master master exchange of the local bus is a sequence of three pulses There must be one idle CLK cycle after each bus exchange Pulses are active LOW If the request is mad
9. 1 1 ROL Rotate Left 110100vw 000 ROR Rotate Right 110100vw mod 0 0 1 RCL Rotate Through Carry Flag Left 110100vw mod 0 1 Rotate Through Carry Right 110100vw mod 0 1 1 r m AND And Reg Memory and Register to Either 001000dw mod reg r m Immediate to Register Memory 1000000w mod 100r m data data 1 Immediate to Accumulator 0010010w data data 1 TEST And Function to Flags No Result Register Memory and Register 1000010w mod reg r m Immediate Data and Register Memory 1111011w mod000r m data data 1 Immediate Data and Accumulator 1010100w data data if w 1 OR Or Reg Memory and Register to Either 000010dw mod reg r m Immediate to Register Memory 1000000w mod 0 0 1 data data 1 Immediate to Accumulator 0000110w data data 1 XOR Exclusive or Reg Memory and Register to Either 001100dw mod reg r m Immediate to Register Memory 1000000w mod 110r m data data 1 Immediate to Accumulator 0011010w data data if w 1 STRING MANIPULATION REP Repeat 11110012 MOVS Move Byte Word 1010010w CMPS Compare Byte Word 1010011w SCAS Scan Byte Word 1010111w LODS Load Byte Wd to AL AX 1010110w STOS Stor Byte Wd from AL A 1010101w CONTROL TRANSFER CALL Call Direct Within Segment 11101000 disp low disp h
10. TSVMCH PDEN DT R AD Ais INVALID ADDRESS TCLAV 52 51 50 NOTES 231456 16 1 All signals switch between Voy and Vo unless otherwise specified 2 is sampled near the end of 2 Tw to determine if Ty machines states are to be inserted 3 Cascade address is valid between first and second INTA cycles 4 Two INTA cycles run back to back The 8088 local ADDR DATA bus is floating during both INTA cycles Control for pointer address is shown for second INTA cycle 5 Signals at 8284 or 8288 are shown for reference only 6 The issuance of the 8288 command and control signals MWTC AMWC IORC IOWC AIOWC INTA and DEN lags the active high 8288 CEN 7 All timing measurements are made at 1 5V unless otherwise noted 8 Status inactive in state just prior to 24 intel WAVEFORMS Continued BUS LOCK SIGNAL TIMING ASYNCHRONOUS SIGNAL RECOGNITION MAXIMUM MODE ONLY 8088 CLK Any CLK NMI TINVCH see note 1 CLK INTR signal LOCK TEST NOTE 231456 17 1 Setup requirements for asynchronous signals only to guarantee recognition at next CLK Any CLK Cycle 231456 18 REQUEST GRANT SEQUENCE TIMING MAXIMUM MODE ONLY Any CLK Cycle 0 CLK Cycle PULSE 3 OPROCESSOR RELEASE COPROCESSOR RO PULSE 2 8088 GT Previous grant
11. data if w 1 SSB Subtract with Borrow Reg Memory and Register to Either 000110dw mod reg r m Immediate from Register Memory 100000sw mod 0 1 1 data data if s w 01 Immediate from Accumulator 000111w data data if w 1 DEC Decrement Register memory 1111111w mod 0 0 1 Register 01001 reg NEG Change sign 1111011w mod 0 1 1 CMP Compare Register Memory and Register 001110dw mod reg r m Immediate with Register Memory 100000sw mod 1 1 1 data data if s w 01 Immediate with Accumulator 0011110w data data if w 1 AAS ASCII Adjust for Subtract 00111111 DAS Decimal Adjust for Subtract 00101111 MUL Multiply Unsigned 1111011w mod 100 IMUL Integer Multiply Signed 1111011w mod 1 0 1 AAM ASCII Adjust for Multiply 11010100 00001010 DIV Divide Unsigned 1111011w mod 1 10 IDIV Integer Divide Signed 1111011w mod 1 1 1 r m AAD ASCII Adjust for Divide 11010101 00001010 CBW Convert Byte to Word 10011000 CWD Convert Word to Double Word 10011001 27 8088 n 8086 8088 Instruction Set Summary Continued Mnemonic and i o Instruction Code Description LOGIC 76543210 76543210 76543210 76543210 NOT Invert 1111011w 010 SHL SAL Shift Logical Arithmetic Left mod100r m__ SHR Shift Logical Right 110100vw mod 10 1 SAR Shift Arithmetic Right 110100vw mod 1
12. equivalent to SO the maximum mode The combination of SSO IO M and DT R allows the system to completely decode the current bus cycle status 10 M DT R sso Characteristics 1 HIGH 0 0 Interrupt Acknowledge 1 0 1 Read I O Port 1 1 0 Write I O Port 1 1 1 Halt O LOW 0 0 Code Access 0 0 1 Read Memory 0 1 0 Write Memory 0 1 1 Passive The following pin function descriptions are for the 8088 8288 system in maximum mode i e MN MX GND Only the pin functions which are unique to maximum mode are described all other pin functions are as described above Symbol Pin No Type Name and Function 52 1 0 26 28 STATUS is active during clock high of T4 1 and T2 and is returned to the passive state 1 1 1 during T3 or during Tw when READY is HIGH This status is used by the 8288 bus controller to generate all memory and I O access control signals Any change by S2 S1 or SO during T4 is used to indicate the beginning of a bus cycle and the return to the passive state in T3 and Tw is used to indicate the end of a bus cycle These signals float to 3 state OFF during hold acknowledge During the first clock cycle after RESET becomes active these signals are active HIGH After this first clock they float to 3 state OFF 52 51 50 Characteristics O LOW 0 0 Interrupt Acknowledge 0 0 1 Read I O Port 0 1 0 Write Port 0 1 1 Halt 1 HIGH 0 0 Code Access 1 0 1 Read Memory 1
13. is presently being used for data accessing These lines float to 3 state OFF during local bus hold acknowledge S4 S3 Characteristics 0 LOW 0 1 HIGH Alternate Data Stack Code or None Data S6 is 0 LOW 32 READ Read strobe indicates that the processor is performing a memory or I O read cycle depending on the state of the IO M pin or S2 This signal is used to read devices which reside on the 8088 local bus RD is active LOW during T2 T3 and Tw of any read cycle and is guaranteed to remain HIGH in T2 until the 8088 local bus has floated This signal floats to 3 state OFF in hold acknowledge READY 22 READY is the acknowledgement from the addressed memory or I O device that it will complete the data transfer The RDY signal from memory or I O is synchronized by the 8284 clock generator to form READY This signal is active HIGH The 8088 READY input is not synchronized Correct operation is not guaranteed if the set up and hold times are not met INTR 18 INTERRUPT REQUEST is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation A subroutine is vectored to via an interrupt vector lookup table located in system memory It can be internally masked by software resetting the interrupt enable bit INTR is internally synchronized This signal is active H
14. memory instruction without another system bus master receiving intervening memory cycles This is useful in multiprocessor system configurations to ac complish test and set lock operations The LOCK signal is activated LOW in the clock cycle following decoding of the LOCK prefix instruction It is deacti vated at the end of the last bus cycle of the instruc tion following the LOCK prefix While LOCK is active a request on a RQ GT pin will be recorded and then honored at the end of the LOCK 8088 ADo AD TYPE VECTOR 231456 9 Figure 9 Interrupt Acknowledge Sequence External Synchronization via TEST As an alternative to interrupts the 8088 provides a single software testable input pin TEST This input is utilized by executing a WAIT instruction The sin gle WAIT instruction is repeatedly executed until the TEST input goes active LOW The execution of WAIT does not consume bus cycles once the queue is full If a local bus request occurs during WAIT execution the 8088 3 states all output drivers If interrupts are enabled the 8088 will recognize interrupts and pro cess them The WAIT instruction is then refetched and reexecuted Basic System Timing In minimum mode the MN MX pin is strapped to Vcc and the processor emits bus control signals compatible with the 8085 bus structure In maximum mode the MN MX pin is strapped to GND and the processor emits coded status information w
15. the next higher address location The BIU will automatically execute two fetch or write cycles for 16 bit operands Memory Segment Reference Used Register Used Segment Selection Rule Instructions CODE CS Automatic with all instruction prefetch Stack STACK SS All stack pushes and pops Memory references relative to BP base register except data references Local Data DATA DS Data references when relative to stack destination of string operation or explicity overridden External Global Data EXTRA ES Destination of string operations Explicitly selected using a segment override intel Certain locations in memory are reserved for specific CPU operations See Figure 4 Locations from ad dresses FFFFOH through FFFFFH are reserved for operations including a jump to the initial system ini tialization routine Following RESET the CPU will al ways begin execution at location FFFFOH where the jump must be located Locations 00000H through are reserved for interrupt operations Four byte pointers consisting of a 16 bit segment address and a 16 bit offset address direct program flow to one of the 256 possible interrupt service routines The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts Minimum and Maximum Modes The requirements for supporting minimum and maxi mum 8088 systems are sufficiently
16. 0 160 10 100 ns TRLRH RD Width 2TCLCL 75 2TCLCL 50 ns TWLWH WR Width 2TCLCL 60 2TCLCL 40 ns TAVAL Address Valid to ALE Low TCLCH 60 TCLCH 40 ns TOLOH Output Rise Time 20 20 ns From 0 8V to 2 0V TOHOL Output Fall Time 12 12 ns From 2 0V to 0 8 NOTES 1 Signal at 8284A shown for reference only See 8284A data sheet for the most recent specifications 2 Set up requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T2 state 8 ns into T3 state 18 intel A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 24 1 5 4 TEST POINTS 1 5 DEVICE UNDER TEST 0 45 C 100 pF 231456 11 Testing Inputs are driven at 2 4V for a logic 1 0 45V for a logic 0 Timing measurements are made at 1 5V for both a logic 1 and logic 0 1 23145612 Includes Jig Capacitance WAVEFORMS BUS TIMING MINIMUM MODE SYSTEM TCLCL CLK 8284 Output VcL Ars Ag A19 S6 A16 53 ALE RDY 8284 Input SEE NOTES READY 8088 Input TCHICH2 T2 Ta Tw Ta Fe TCLCH AD DATA IN FLOAT pt k READ CYCLE d NOTE 1 TCHCTV TCLRL TCHCTV WR INTA _ DTIR TCVCTV P ER Y 231456 13 19 8088 n WAVEFORMS Continued BUS TIMING MINIMUM MOD
17. 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH Instructions which reference the flag register file as a 16 bit object use the symbol FLAGS to represent the file FLAGS X X X X OF DF IF TF SF ZF X AF X PF X CF Mnemonics Intel 1978 DATA SHEET REVISION REVIEW The following list represents key differences be tween this and the 005 data sheet Please review this summary carefully 1 The Intel 8088 implementation technology HMOS has been changed to HMOS II
18. 110w OUT Output to Fixed Port 1110011w port Variable Port 1110111w XLAT Translate Byte to AL 11010111 LEA Load EA to Register 10001101 mod reg r m LDS Load Pointer to DS 11000101 mod reg r m LES Load Pointer to ES 11000100 mod reg r m LAHF Load AH with Flags 10011111 SAHF Store AH into Flags 10011110 PUSHF Push Flags 10011100 POPF Pop Flags 10011101 26 in 8088 8086 8088 Instruction Set Summary Continued Instruction Code ARITHMETIC 76543210 76543210 76543210 76543210 ADD Add Reg Memory with Register to Either 000000dw mod reg r m Immediate to Register Memory 100000sw mod 0 0 0 r m data data if s w 01 Immediate to Accumulator 0000010w data dataifw 1 ADC Add with Carry Reg Memory with Register to Either 000100dw mod reg r m Immediate to Register Memory 100000sw mod 0 1 data data if s w 01 Immediate to Accumulator 0001010w data data 1 INC Increment Register Memory 1111111w mod000r m Register 01000reg AAA ASCII Adjust for Add 00110111 BAA Decimal Adjust for Add 00100111 SUB Subtract Reg Memory and Register to Either 001010dw mod reg r m Immediate from Register Memory 100000sw mod 1 0 1 data data if s w 01 Immediate from Accumulator 0010110w data
19. 5 15 ns Note 1 TCLMCH CLK Low to MCE Note 1 15 15 ns TCHLL ALE Inactive Delay Note 1 15 15 ns TCLMCL MCE Inactive Delay Note 1 15 15 ns TCLDV Data Valid Delay 10 110 10 60 ns TCHDX Data Hold Time 10 10 ns 20 100 pF fo r L r TCVNV Delay 5 45 5 45 ns All 8088 Outputs in Addition to TCVNX Control Inactive Delay 10 45 10 45 ns Internal Loads Note 1 TAZRL Address Float to 0 0 ns Read Active TCLRL RD Active Delay 10 165 10 100 ns RD Inactive Delay 10 150 10 80 ns TRHAV Inactive to Next TCLCL 45 TCLCL 40 ns Address Active TCHDTL Direction Control 50 50 ns Active Delay Note 1 TCHDTH Direction Control 30 30 ns Inactive Delay Note 1 TCLGL GT Active Delay 85 50 ns TCLGH GT Inactive Delay 85 50 ns TRLRH RD Width 2TCLCL 75 2TCLCL 50 ns Output Rise Time 20 20 ns From 0 8V to 2 0V TOHOL Output Fall Time 12 12 ns From 2 0V to 0 8V NOTES 1 Signal at 8284 or 8288 shown for reference only 2 Setup requirement for asynchronous signal only to guarantee recognition at next CLK 3 Applies only to T3 and wait states 4 Applies only to T2 state 8 ns into T3 state 22 intel 8088 TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT 24 UNDER TEST 1 5 TEST POINTS 1 5 0 45 C 2100 pF 231456 11 Testing Inputs are driven at 2 4V for a logic 1 0 45V for
20. 88 CPU Functional Block Diagram August 1990 Order Number 231456 006 8088 intel Table 1 Pin Description The following pin function descriptions are for 8088 systems in either minimum or maximum mode The local bus in these descriptions is the direct multiplexed bus interface connection to the 8088 without regard to additional bus buffers Symbol Pin No Type Name and Function AD7 ADO 9 16 1 0 ADDRESS DATA BUS These lines constitute the time multiplexed memory IO address T1 and data T2 Tw T4 bus These lines are active HIGH and float to 3 state OFF during interrupt acknowledge and local bus hold acknowledge 15 8 2 8 39 ADDRESS BUS These lines provide address bits 8 through 15 for the entire bus cycle 1 4 These lines do not have to be latched by ALE to remain valid A15 A8 are active HIGH and float to 3 state OFF during interrupt acknowledge and local bus hold acknowledge A19 S6 A18 S5 A17 84 A16 S3 35 38 ADDRESS STATUS During T1 these are the four most significant address lines for memory operations During I O operations these lines are LOW During memory and I O operations status information is available on these lines during T2 T3 Tw and T4 S6 is always low The status of the interrupt enable flag bit S5 is updated at the beginning of each clock cycle S4 and S3 are encoded as shown This information indicates which segment register
21. E SYSTEM Continued T2 Ts Tw Ta TCHICH2 TCL2CL1 Vcn p CLK 8284 Output TCLDV TCLAV TCHDX Cm TWHDX CVCTX WRITE CYCLE DEN NOTE 1 TWLWH WR TDVCL TCLOX FLOAT FLOAT TCHCTV TcHCTVv DT R INTA CYCLE 4 NOTES 1 3 RD WR V c ent INTA SOFTWARE HALT DEN RD WRINTA AD INVALID ADDRESS SOFTWARE HALT DT R INDETERMINATE 231456 14 NOTES 1 All signals switch between and Vo unless otherwise specified 2 is sampled near the end of 2 Tw to determine if Ty machines states are to be inserted 3 Two INTA cycles run back to back The 8088 local ADDR DATA bus is floating during both INTA cycles Control signals are shown for the second INTA cycle 4 Signals at 8284 are shown for reference only 5 All timing measurements are made at 1 5V unless otherwise noted 20 intel 8088 A C CHARACTERISTICS MAX MODE SYSTEM USING 8288 BUS CONTROLLER TIMING REQUIREMENTS Symbol Parameter 88 Units Test Min Max Min Max Conditions TCLCL CLK Cycle Period 200 500 125 500 ns TCLCH CLK Low Time 118 68 ns TCHCL CLK High Time 69 44 ns TCH1CH2 CLK Rise Time 10 10 ns From 1 0V to 3 5V
22. IGH TEST 23 TEST input is examined by the wait for test instruction If the TEST input is LOW execution continues otherwise the processor waits in an idle state This input is synchronized internally during each clock cycle on the leading edge of CLK n 8088 Table 1 Pin Description Continued Symbol Pin Type Name and Function NMI 17 NON MASKABLE INTERRUPT is an edge triggered input which causes a type 2 interrupt A subroutine is vectored to via an interrupt vector lookup table located in system memory NMI is not maskable internally by software A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction This input is internally synchronized RESET 21 RESET causes the processor to immediately terminate its present activity The signal must be active HIGH for at least four clock cycles It restarts execution as described in the instruction set description when RESET returns LOW RESET is internally synchronized CLK 19 CLOCK provides the basic timing for the processor and bus controller It is asymmetric with a 33 duty cycle to provide optimized internal timing Voc 40 Voc is the 5V 10 power supply pin GND 1 20 GND are the ground pins MN MX 33 MINIMUM MAXIMUM indicates what mode the processor is to operate in The two modes are discussed in the following sections The following pin function descripti
23. IO M T HIGH LOW This signal floats to 3 state OFF in local hold acknowledge 2 26 DATA ENABLE is provided as an output enable for the data bus transceiver in minimum system which uses the transceiver DEN is active LOW during each memory and I O access and for INTA cycles For a read INTA cycle it is active from the middle of T2 until the middle of T4 while for a write cycle it is active from the beginning of T2 until the middle of T4 DEN floats to 3 state OFF during local bus hold acknowledge 8088 Table 1 Pin Description Continued Symbol Pin No Type a intel Name and Function HOLD HLDA 31 30 HOLD indicates that another master is requesting a local bus hold be acknowledged HOLD must be active HIGH The processor receiving the hold request will issue HLDA HIGH as an acknowledgement in the middle of a T4 or Ti clock cycle Simultaneous with the issuance of HLDA the processor will float the local bus and control lines After HOLD is detected as being LOW the processor lowers HLDA and when the processor needs to run another cycle it will again drive the local bus and control lines HOLD and HLDA have internal pull up resistors Hold is not an asynchronous input External synchronization should be provided if the system cannot otherwise guarantee the set up time 0 34 STATUS LINE is logically
24. T is HIGH The low going transition of RESET triggers an internal reset se quence for approximately 7 clock cycles After this interval the 8088 operates normally beginning with the instruction in absolute locations FFFFOH See Figure 4 The RESET input is internally synchroniz ed to the processor clock At initialization the HIGH to LOW transition of RESET must occur no sooner than 50 us after power up to allow complete initiali zation of the 8088 NMI asserted prior to the 2nd clock after the end of RESET will not be honored If NMI is asserted after that point and during the internal reset sequence the processor may execute one instruction before responding to the interrupt A hold request active immediately after RESET will be honored before the first instruction fetch All 3 state outputs float to 3 state OFF during RESET Status is active in the idle state for the first clock after RESET becomes active and then floats to 3 state OFF ALE and HLDA are driven low Interrupt Operations Interrupt operations fall into two classes software or hardware initiated The software initiated interrupts and software aspects of hardware interrupts are specified in the instruction set description in the iAPX 88 book or the iAPX 86 88 User s Manual Hardware interrupts can be classified as nonmaska ble or maskable 11 8088 Interrupts result in a transfer of control to a new pro gram location A 256 element table containing ad dr
25. X Data in Hold Time 10 10 ns TR1VCL RDY Setup Time into 8284 35 35 ns Notes 1 2 TCLR1X RDY Hold Time into 8284 0 0 ns Notes 1 2 TRYHCH READY Setup Time 118 68 ns into 8088 TCHRYX READY Hold Time 30 20 ns into 8088 TRYLCL READY Inactive to CLK 8 8 ns Note 3 THVCH HOLD Setup Time 35 20 ns TINVCH INTR NMI TEST Setup Time 30 15 ns Note 2 TILIH Input Rise Time Except CLK 20 20 ns From 0 8V to 2 0V TIHIL Input Fall Time Except CLK 12 12 ns From 2 0V to 0 8V 17 8088 A C CHARACTERISTICS Continued TIMING RESPONSES 8088 Symbol Parameter bee Units Min Max Min Max Conditions TCLAV Address Valid Delay 10 110 10 60 ns TCLAX Address Hold Time 10 10 ns TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns TLHLL ALE Width TCLCH 20 TCLCH 10 TCLLH ALE Active Delay TCHLL ALE Inactive Delay TLLAX Address Hold Time to TCHCL 10 TCHCL 10 ALE Inactive TCLDV Data Valid Delay 10 10 TCHDX Data Hold Time 10 10 TWHDX Data Hold Time after WR TCLCH 30 TCLCH 30 TCVCTV Control Active Delay 1 10 10 Control Active Delay 2 10 10 TCVCTX Control Inactive Delay 10 10 TAZRL Address Float to READ 0 0 Active TCLRL RD Active Delay 10 10 TCLRH RD Inactive Delay 10 10 TRHAV RD Inactive to Next TCLCL 45 TCLCL 40 Address Active TCLHAV HLDA Valid Delay 1
26. a logic 0 Timing measurements are made at 1 5V for both a logic 1 and logic 0 231456 12 Includes Jig Capacitance WAVEFORMS Continued BUS TIMING MAXIMUM MODE SYSTEM TCLCL ITCH1CH2 TCL2CLt Tw I TCLCH ca 52 51 50 EXCEPT HALT f S NOTE 8 mom 19 56 5 33 ALE 8288 OUTPUT 5 TR1VCL TRYLC READY B088 INPUT TCHRYX TRYHSH TCLAK RYHC READ CYCLE TCLAV TCLAZ TDVCL AD AD DATA IN TAZRL Li TRHAV RD TcHOTL p pc DTA TCLML 8288 OUTPUTS MRDC IORC SEE NOTES 5 6 TCVNV DEN TCVNX 231456 15 23 8088 n i WAVEFORMS Continued BUS TIMING MAXIMUM MODE SYSTEM USING 8288 Ta Ta TCHSV dw VCH CLK E rctov WRITE CYCLE TCLAV TCLSH TCHDX re 5506 DATA NERE TCVNV DEN me EN 8288 OUTPUTS SEE NOTES 5 6 AMWC OR AIOWC TCLMH MWTC OR IOWC INTA CYCLE Ars Ag FLOAT RESERVED FOR SEE NOTES 3 4 CASCADE AODR FLOAT TCLDX POINTER FLOAT rc 8288 OUTPUTS SEE NOTES 5 6 DEN SOFTWARE TCVNX HALT DEN Vo RD MRDC IORC MWTC AMWC IOWC ATOWC INTA ADr ADo
27. a remains valid until at least the middle of T4 During T2 T3 and Tw the processor asserts the write control signal The write WR signal becomes active at the begin ning of T2 as opposed to the read which is delayed somewhat into T2 to provide time for the bus to float 13 8088 The basic difference between the interrupt acknowl edge cycle and a read cycle is that the interrupt ac knowledge INTA signal is asserted in place of the read RD signal and the address bus is floated See Figure 9 In the second of two successive INTA cycles a byte of information is read from the data bus as supplied by the interrupt system logic i e 8259A priority interrupt controller This byte identi fies the source type of the interrupt It is multiplied by four and used as a pointer into the interrupt vec tor lookup table as described earlier Bus Timing Medium Complexity Systems See Figure 10 For medium complexity systems the MN MX pin is connected to GND and the 8288 bus controller is added to the system as well as a latch for latching the system address and a transceiver to allow for bus loading greater than the 8088 is capable of han dling Signals ALE DEN and DT R are generated by the 8288 instead of the processor in this configu ration although their timing remains relatively the same The 8088 status outputs S2 S1 and SO pro vide type of cycle information and become 8288 in puts This bus cycle inf
28. different that they cannot be done efficiently with 40 uniquely de fined pins Consequently the 8088 is equipped with a strap pin MN MX which defines the system con RESET BOOTSTRAP PROGRAM JUMP FFFFFH FFFFOH 3FFH 3FOH 7H INTERRUPT POINTER FOR TYPE 1 4H INTERRUPT POINTER 3H FOR TYPE 0 231456 4 Figure 4 Reserved Memory Locations 8088 figuration The definition of a certain subset of the pins changes dependent on the condition of the strap pin When the pin is strapped to GND the 8088 defines pins 24 through 31 and 34 in maxi mum mode When the pin is strapped to Vcc the 8088 generates bus control signals itself on pins 24 through 31 and 34 The minimum mode 8088 can be used with either a multiplexed or demultiplexed bus The multiplexed bus configuration is compatible with the MCS 85 multiplexed bus peripherals This configuration See Figure 5 provides the user with a minimum chip count system This architecture provides the 8088 processing power in a highly integrated form The demultiplexed mode requires one latch for 64K addressability or two latches for a full megabyte of addressing A third latch can be used for buffering if the address bus loading requires it A transceiver can also be used if data bus buffering is required See Figure 6 The 8088 provides DEN and DT R to control the transceiver and ALE to latch the ad dresses This configurat
29. e while the CPU is performing a memory cycle it will release the local bus during T4 of the cycle when all the following conditions are met 1 Request occurs on or before T2 2 Current cycle is not the low bit of a word 3 Current cycle is not the first acknowledge of an interrupt acknowledge sequence 4 A locked instruction is not currently executing If the local bus is idle when the request is made the two possible events will follow 1 Local bus will be released during the next clock 2 Amemory cycle will start within 3 clocks Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied LOCK 29 LOCK indicates that other system bus masters are not to gain control of the system bus while LOCK is active LOW The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction This signal is active LOW and floats to 3 state off in hold acknowledge 051 050 24 25 QUEUE STATUS provide status to allow external tracking of the internal 8088 instruction queue The queue status is valid during the CLK cycle after which the queue operation is performed 51 950 Characteristics O LOW 0 No Operation 0 1 First Byte of Opcode from Queue 1 HIGH 0 Empty the Queue 1 1 Subsequent Byte from Queue 34 Pin 34 is always high the maximum mode 8088 64 KB
30. ess pointers to the interrupt service program loca tions resides in absolute locations 0 through 3FFH See Figure 4 which are reserved for this purpose Each element in the table is 4 bytes in size and cor responds to an interrupt type An interrupting de vice supplies an 8 bit type number during the inter rupt acknowledge sequence which is used to vector through the appropriate element to the new interrupt service program location Non Maskable Interrupt NMI The processor provides a single non maskable inter rupt NMI pin which has higher priority than the maskable interrupt request INTR pin A typical use would be to activate a power failure routine The NMI is edge triggered on a LOW to HIGH transition The activation of this pin causes a type 2 interrupt NMI is required to have a duration in the HIGH state of greater than two clock cycles but is not required to be synchronized to the clock Any higher going transition of NMI is latched on chip and will be serv iced at the end of the current instruction or between whole moves 2 bytes in the case of word moves of a block type instruction Worst case response to NMI would be for multiply divide and variable shift instructions There is no specification on the occur rence of the low going edge it may occur before during or after the servicing of NMI Another high going edge triggers another response if it occurs af ter the start of the NMI procedure The signal mu
31. execution proceeds as fast as the exe cution unit will allow The 8088 and 8086 are completely software com patible by virtue of their identical execution units Software that is system dependent may not be com pletely transferable but software that is not system dependent will operate equally as well on an 8088 and an 8086 The hardware interface of the 8088 contains the ma jor differences between the two CPUs The pin as signments are nearly identical however with the fol lowing functional changes A8 A15 These pins are only address outputs on the 8088 These address lines are latched in ternally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines has no meaning on the 8088 and has been eliminated intel SSO provides the SO status information in the minimum mode This output occurs on pin 34 in minimum mode only DT R IO M and SSO pro vide the complete bus status in minimum mode 8088 O M has been inverted to be compatible with the MCS 85 bus structure ALE is delayed by one clock cycle in the mini mum mode when entering HALT to allow the status to be latched with ALE 0 1 050 8088 N 2 2 WI T A19 S6 A16 S53 ALE 8288 RDY 8284 READY 8088 ADO 8088 15 RD DT R 8288 MRDC DEN E A19 A16 7 T4 Em ey S6 53
32. gh T4 S3 and S4 indicate which segment reg ister was used for this bus cycle in forming the ad dress according to the following table S4 53 Characteristics O LOW 0 Alternate Data Extra Segment 0 1 Stack 1 HIGH 0 Code or None 1 1 Data S5 is a reflection of the PSW interrupt enable bit S6 is always equal to 0 1 O Addressing In the 8088 I O operations can address up to a maximum of 64K I O registers The I O address ap pears in the same format as the memory address on bus lines A15 A0 The address lines 19 16 are zero operations The variable I O instructions 8088 which use register DX as a pointer have full address capability while the direct I O instructions directly address or two of the 256 I O byte locations in page 0 of the I O address space I O ports are ad dressed in the same manner as memory locations Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses with 8 bit address on both halves of the 16 bit address bus The 8088 uses a full 16 bit address on its lower 16 address lines EXTERNAL INTERFACE Processor Reset and Initialization Processor initialization or start up is accomplished with activation HIGH of the RESET pin The 8088 RESET is required to be HIGH for greater than four clock cycles The 8088 will terminate operations on the high going edge of RESET and will remain dor mant as long as RESE
33. hich the 8288 bus controller uses to generate MULTIBUS compatible bus control signals System Timing Minimum System See Figure 8 The read cycle begins in T1 with the assertion of the address latch enable ALE signal The trailing low going edge of this signal is used to latch the ad dress information which is valid on the address data bus ADO AD7 at this time into the 8282 8283 latch Address lines A8 through A15 do not need to be latched because they remain valid throughout the bus cycle From T1 to T4 the signal indicates a memory or I O operation At T2 the address is removed from the address data bus and the bus goes to a high impedance state The read control signal is also asserted at T2 The read RD signal causes the addressed device to enable its data bus drivers to the local bus Some time later valid data will be available on the bus and the ad dressed device will drive the READY line HIGH When the processor returns the read signal to a HIGH level the addressed device will again 3 state its bus drivers If a transceiver is required to buffer the 8088 local bus signals DT R and DEN are pro vided by the 8088 A write cycle also begins with the assertion of ALE and the emission of the address The IO M signal is again asserted to indicate a memory or I O write operation In T2 immediately following the address emission the processor emits the data to be written into the addressed location This dat
34. igh Indirect Within Segment 11111111 mod 0 1 Direct Intersegment 10011010 offset low offset high seg low seg high Indirect Intersegment 11111111 mod 0 1 1 28 8086 8088 Instruction Set Summary Continued 8088 Mnemonic and Description Instruction Code JMP Unconditional Jump Direct Within Segment Direct Within Segment Short Indirect Within Segment Direct Intersegment Indirect Intersegment RET Return from CALL Within Segment Within Seg Adding Immed to SP Intersegment Intersegment Adding Immediate to SP JE JZ Jump on Equal Zero JL JNGE Jump on Less Not Greater or Equal JLE JNG Jump on Less or Equal Not Greater JB JNAE Jump on Below Not Above or Equal JBE JNA Jump on Below or Equal Not Above JP JPE Jump on Parity Parity Even JO Jump on Overflow JS Jump on Sign JNE JNZ Jump on Not Equal Not Zero JNL JGE Jump on Less Greater or Equal JNLE JG Jump on Not Less or Equal Greater JNB JAE Jump on Not Below Above or Equal JNBE JA Jump on Not Below or Equal Above JNP JPO Jump on Not Par Par Odd JNO Jump on Not Overflow JNS Jump on Not Sign LOOP Loop CX Times LOOPZ LOOPE Loop While Zero Equal LOOPNZ LOOPNE Loop While Not Zero Equal JCXZ Jump on CX Zero INT Interrupt Type Specified Type 3 INTO Interrupt on Overflow IRET Interrupt Return
35. intal tel 8088 8 BIT HMOS MICROPROCESSOR 8088 8088 2 W 8 Bit Data Bus Interface W Byte Word and Block Operations W 16 Bit Internal Architecture W 8 Bit and 16 Bit Signed and Unsigned m Direct Addressing Capability to 1 Mbyte Arithmetic in Binary or Decimal of Memory Including Multiply and Divide Direct Soft tibilitv with m Two Clock Rates cua Software Compatibility with 8086 I5 MHz for ass 8 MHz for 8088 2 W Available in EXPRESS Standard Temperature Range 24 Operand Addressing Modes Extended Temperature Range m 14 Word by 16 Bit Register Set with Symmetrical Operations The Intel 8088 is a high performance microprocessor implemented in N channel depletion load silicon gate technology HMOS II and packaged 40 CERDIP package The processor has attributes of both 8 and 16 bit microprocessors It is directly compatible with 8086 software and 8080 8085 hardware and periph erals MEMORY INTERFACE MIN MAX MODE MODE GND Vee 14 15 A13 A16 S3 INSTRUCTION STREAM BYTE A12 17 54 QUEUE 11 A18 S5 A10 19 56 9 550 HIGH BUS 8 MNIMX INTERFACE aH UNIT AD7 RD EXECUTION UNIT 06 HOLD RQ IGTO CONTROL INS SYSTEM ADS HLDA ROIGTI AD4 WR COCK AD3 10 M 52 AD2 DTR 51 1 DEN 50 ADO ALE 050 ARITHMETIC LOGIC UNIT NMI INTA 051 EXECUTION INTR TEST UNIT CLK READY GND RESET 231456 2 Figure 2 8088 Pin Configuration 231456 1 Figure 1 80
36. ion of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing re quirements The maximum mode employs the 8288 bus control ler See Figure 7 The 8288 decodes status lines 50 S1 and S2 and provides the system with all bus control signals Moving the bus control to the 8288 provides better source and sink current capability to the control lines and frees the 8088 pins for extend ed large system features Hardware lock queue status and two request grant interfaces are provid ed by the 8088 in maximum mode These features allow co processors in local bus and remote bus configurations 8088 n Aa Aig ADDR DATA 8355 8755 ADDR 231456 5 Figure 5 Multiplexed Bus Configuration 8088 8284 CLOCK GENERATOR RES INTERRUPT CONTROL INT IRO 7 t t 4 c ADDRIDATA ADDRESS TRANSCEIVER DATA Il I We OD cs AD WA 2 PROM MCS 80 PERIPHERAL 231456 6 Figure 6 Demultiplexed Bus Configuration 8284A CLOCK GENERATOR RES MNIMX GND AUDDRIDA 2 21
37. ltage 2 4 V lou 400 pA loc 8088 340 mA Ta 25 C Power Supply Current 8088 2 350 P8088 250 lu Input Leakage Current 10 pA OV lt Vin lt Note 3 ILo Output and I O Leakage Current 10 pA 0 45V lt Vout lt VoL Clock Input Low Voltage 0 5 T 0 6 V VcH Clock Input High Voltage 3 9 Voc 1 0 V Cin Capacitance If Input Buffer 15 pF fe 1 MHz All Input Except ADo AD RQ GT Clo Capacitance of I O Buffer 15 pF fe 1 MHz ADo AD RQ GT NOTES 1 tested with MN MX Pin tested with MN MX Pin 5V Pin is a strap Pin 2 Not applicable to RQ GTO and Pins Pins 30 and 31 3 HOLD and HLDA I Min 30 pA Max 500 pA 16 intel 8088 A C CHARACTERISTICS TA 0 C to 70 C Tcase Plastic 0 C to 95 C CERDIP 0 C to 75 C Ta 0 C to 55 C and Tcase 0 C to 80 C for P8088 2 only Ta is guaranteed as long as is not exceeded Vcc 5V 10 for 8088 5V 5 for 8088 2 and Extended Temperature EXPRESS MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS 8088 8088 2 Symbol Parameter Units Conditions TCLCL CLK Cycle Period 200 500 125 500 ns TCLCH CLK Low Time 118 68 ns TCHCL CLK High Time 69 44 ns TCH1CH2 CLK Rise Time 10 10 ns From 1 0V to 3 5V TCL2CL2 CLK Fall Time 10 10 ns From 3 5V to 1 0V TDVCL Data in Setup Time 30 20 ns TCLD
38. ons are for the 8088 minimum mode i e MN MX Vcc Only the pin functions which are unique to minimum mode are described all other pin functions are as described above Symbol Pin No Type Name and Function 10 M 28 STATUS LINE is an inverted maximum mode 82 It is used to distinguish memory access from an 1 0 access becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle I O HIGH M LOW IO M floats to 3 state OFF in local bus hold acknowledge 29 WRITE strobe indicates that the processor is performing a write memory or write I O cycle depending on the state of the signal WR is active for T2 and Tw of any write cycle It is active LOW and floats to 3 state OFF in local bus hold acknowledge INTA 24 INTA is used as a read strobe for interrupt acknowledge cycles It is active LOW during T2 T3 and Tw of each interrupt acknowledge cycle ALE 25 ADDRESS LATCH ENABLE is provided by the processor to latch the address into an address latch It is a HIGH pulse active during clock low of T1 of any bus cycle Note that ALE is never floated DT R 27 DATA TRANSMIT RECEIVE is needed in a minimum system that desires to use a data bus transceiver It is used to control the direction of data flow through the transceiver Logically DT R is equivalent to S1 in the maximum mode and its timing is the same as for
39. ormation specifies read code data or I O write data interrupt ac knowledge or software halt The 8288 thus issues control signals specifying memory read or write read or write or interrupt acknowledge The 8288 provides two types of write strobes normal and ad vanced to be applied as required The normal write strobes have data valid at the leading edge of write The advanced write strobes have the same timing as read strobes and hence data is not valid at the leading edge of write The transceiver receives the usual T and OE inputs from the 8288 s DT R and DEN outputs The pointer into the interrupt vector table which is passed during the second INTA cycle can derive from an 8259A located on either the local bus or the system bus If the master 8289A priority interrupt controller is positioned on the local bus a TTL gate is required to disable the transceiver when reading from the master 8259A during the interrupt acknowl edge sequence and software poll The 8088 Compared to the 8086 The 8088 CPU is an 8 bit processor designed around the 8086 internal structure Most internal functions of the 8088 are identical to the equivalent 8086 functions The 8088 handles the external bus 14 intel the same way the 8086 does with the distinction of handling only 8 bits at a time Sixteen bit operands are fetched or written in two consecutive bus cycles Both processors will appear identical to the softwa
40. ow refers to unsigned value Greater more positive Less less positive more negative signed values if d 1 then to reg if d 0 then from reg if w 1 then word instruction if w 0 then byte instruction if mod 11 then r m is treated as a REG field if mod 00 then DISP 0 disp low disp high are absent if mod 01 then DISP disp low sign extended to 16 bits disp high is absent if mod 10 then DISP disp high disp low if r m 000 then EA BX SI DISP if 001 then EA BX DI DISP if r m 010 then EA BP SI DISP if r m 011 then EA BP DI DISP if r m 100 then EA SI DISP ifr m 101 then EA DI DISP ifr m 110 then EA BP DISP if r m 111 then EA BX DISP DISP follows 2nd byte of instruction before data if re quired except if mod 00 and r m then EA disp high disp low if ssw 01 then 16 bits of immediate data form the oper and if ssw 11 then an immediate data byte is sign extended to form the 16 bit operand if v 0 then count 1 if v 1 then count CL register x don t care z is used for string primitives for comparison with ZF FLAG SEGMENT OVERRIDE PREFIX 001 110 30 REG is assigned according to the following table 16 Bit w 1 8 Bit w 0 Segment 000 AX 000 AL 00 ES 001 CX 001 CL 01 CS 010 DX 010 DL 10 SS 011 BX 011 BL 11 DS
41. re engineer with the exception of execution time The internal register structure is identical and all instruc tions have the same end result The differences be tween the 8088 and 8086 are outlined below The engineer who is unfamiliar with the 8086 is referred to the iAPX 86 88 User s Manual Chapters 2 and 4 for function description and instruction set informa tion Internally there are three differences between the 8088 and the 8086 All changes are related to the 8 bit bus interface The queue length is 4 bytes in the 8088 whereas the 8086 queue contains 6 bytes or three words The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions This was required because of the additional time necessary to fetch instructions 8 bits at a time To further optimize the queue the prefetching al gorithm was changed The 8088 BIU will fetch a new instruction to load into the queue each time there is a 1 byte hole space available in the queue The 8086 waits until a 2 byte space is available The internal execution time of the instruction set is affected by the 8 bit interface All 16 bit fetches and writes from to memory take an additional four clock cycles The CPU is also limited by the speed of instruction fetches This latter problem only occurs when a series of simple operations occur When the more sophisticated instructions of the 8088 are being used the queue has time to fill and the
42. st be free of logical spikes in general and be free of bounces on the low going edge to avoid triggering extraneous responses Maskable Interrupt INTR The 8088 provides a single interrupt request input INTR which can be masked internally by software with the resetting of the interrupt enable IF flag bit The interrupt request signal is level triggered It is internally synchronized during each clock cycle on the high going edge of CLK To be responded to INTR must be present HIGH during the clock peri od preceding the end of the current instruction or the end of a whole move for a block type instruction During interrupt response sequence further inter rupts are disabled The enable bit is reset as part of the response to any interrupt INTR NMI software interrupt or single step although the FLAGS regis ter which is automatically pushed onto the stack re flects the state of the processor prior to the inter rupt Until the old FLAGS register is restored the 12 intel enable bit will be zero unless specifically set by an instruction During the response sequence See Figure 9 the processor executes two successive back to back interrupt acknowledge cycles The 8088 emits the LOCK signal maximum mode only from T2 of the first bus cycle until T2 of the second A local bus hold request will not be honored until the end of the second bus cycle In the second bus cycle a byte is fetched from the external in
43. terrupt system e g 8259A PIC which identifies the source type of the interrupt This byte is multiplied by four and used as a pointer into the interrupt vector lookup table An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period The interrupt return instruction includes a flags pop which returns the status of the original interrupt enable bit when it restores the flags HALT When a software HALT instruction is executed the processor indicates that it is entering the HALT state in one of two ways depending upon which mode is strapped In minimum mode the processor issues ALE delayed by one clock cycle to allow the sys tem to latch the halt status Halt status is available on and SSO In maximum mode the processor issues appropriate HALT status on S2 51 and 50 and the 8288 bus controller issues one ALE The 8088 will not leave the HALT state when a local bus hold is entered while in HALT In this case the processor reissues the HALT indicator at the end of the local bus hold An interrupt request or RESET will force the 8088 out of the HALT state Read Modify Write Semaphore Operations via LOCK The LOCK status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction This allows the processor to perform read modify write opera tions on memory via the exchange register with
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