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1. 51 Features 51 51 liue 51 Register descriptions eerie eee eee 52 Subaddress 00 Write UART Control 52 Subaddress 00 Read UART Status Register oo 53 Subaddress 01 Write Transmit Data Register 0 0 0 54 Subaddress 01 Read Receive Data 54 Subaddress 02 Write Ports A B 6 nne 54 Subaddress 02 Read Ports A B 54 Subaddresses 03 FF PIC Register 55 56 PTOCESSOTS 56 NTSC PAL Composite Video Capture eee eee estes seen enata tinea sens 56 Analog Video Capture aee 56 Digital Video Capt re iae cient ete ere sde viva 57 Digital Video 57 Camera Control PA Td 57 Analog Video Output pr 57 Monitor ero n L oene 0000 58 POT Interface 58 Interfaces ep 58 TROUBLESHOOTING 59 ALACRON TECHNICAL 5 60 Contacting Technical Support Leer
2. Port No Phys Pin Signal Direction Connection No P000 49 To From TM1 P001 48 VI2 CLK To From TM2 P002 46 VI3 CLK To From TM3 P003 45 4 P004 43 VO1 CLK To From TM1 P005 42 VO2 CLK To From TM2 P006 41 P007 38 VO4 CLK To From 4 P008 37 PROG CLK1 From TM1 P009 36 PROG CLK2 From TM2 P010 35 PIX CLK1 From Input Receivers P011 32 PIX CLK2 From Input Receivers P012 30 PIX CLK3 From Input Receivers P013 29 PIX CLK4 EVIP LLC From Input Receivers or 7111 P014 28 ADC1 CLK From FPGA1 to RS 170 ADC1 P015 24 TM VIDCK From Clock Generator P016 23 APMC PXCK1 To From PMC J4 Connector J3 P017 21 APMC PXCK2 To From PMC J4 Connector J3 P018 20 APMC PXCK3 To From PMC J4 Connector J3 P019 18 APMC_PXCK4 To From PMC J4 Connector J3 P020 17 FE OUTCLK To FPGA1 and FPGA2 P021 16 FPGA1 PXCK1 To FPGA1 P022 13 FPGA1 PXCK2 To FPGA1 P023 12 FPGA2 PXCK1 To FPGA2 P024 11 FPGA2 PXCK2 To FPGA2 P025 10 DO PXCK1 From I O Drivers To Channel Link FastChannel To Crosspoint Switch To MCLK Output P026 9 DO 2 From Drivers To FastChannel To Crosspoint Switch To MCLK Output P027 6 DO From Drivers To FastChannel To Crosspoint Switch To MCLK Output P028 5 DO PXCK4 From Drivers To FastChannel To Crosspoint Switch To MCLK Output P029 3 S3 LCLK To S3 GX2 P030 2 ADC3 CLK From FPGA2 to RS 170 ADC3
3. 28 ELTE 28 Reset verbia rimari esie 28 Analog and Digital Input Connector 11 29 Analog ChannelLink RS 232 Connector 12 enne enne 30 FastChannel Digital Input Output J5 31 5 05 114 3 EPEE AEE Ee etti Dem A nU 31 lunc 32 Giu DM DIR 32 JUMPErS sesso ER 33 B3 Sos mec REUS etenim RV RC RUE 33 iran de eheu matte nt 33 Se Teles oe ek eee UL eda aD SS 34 34 34 FASTIMAGE 1300 CABLES 5 eene ee esa daas aene 35 Cable Summary PD 35 Power eri f M 35 Digital 35 Analog Input 37 ChannelLink TV RS 232 seen oeenoeevoeneoene esse 38 ines ee 39 FastChannel Digital Output 34 J5 39 PROGRAMMING CONFIGURATION AND eene esee enne tene eter 40 1 P
4. FastChannel Crosspoint Switch Figure 15 FastChannel Input Output 20 At the lowest level the drivers and receivers are controlled by active low output enables and input enables At power on all enable signals are inactive high Software should maintain a direction and enable bit for each I O group Calls to the function to update these values should cause the bits to be translated into input and output enables and the updated values to be written to the registers Translation from direction and enable to input enable output enable is shown in the table below Direction Enable Output Enable Port 0 bit Input Enable Port 1 bit In Enabled 1 0 In Disabled 1 1 Out Enabled 0 1 Out Disabled 1 1 Table 3 FastChannel Interface Controls The registers are implemented using a Philips PCF8575 16 bit I O expander Ports are written at address 0x40 using multiple byte write Data is transferred to the output of the PCF8575 after the second byte of data is written Thus all 16 input and output enables are updated simultaneously The first byte of data after the address byte is the driver output enables The PCF8575 data sheet refers to this as Port 0 All driver output enables are active low i e writing a zero turns the drivers on The second byte of data after the address byte is the receiver input enables The PCF8575 data sheet refers to this as Port 1 All receiv
5. e Up to four 8 bit paths from the Fast4 input ports to the crosspoint when Fast4 is connected B Distribution fpga1 DO 0 7 DO 8 15 fpga2 DO 0 7 fpga2 DO 8 15 TriMedia Inputs Input Taps Front End Outputs FastChannel Digital Input Output Channel Link I O FastImage1300 TriMedia Outputs i D Distribution Figure 10 Main Crosspoint Switch Connections 14 The mapping of data sources to destinations is diagrammed in area B of the crosspoint diagram above Any source can connect to one or more destinations No two sources can be connected to i e drive the same destination The sources and destinations include any PMC daughter cards that are connected to the FastChannel PMC slots An installed daughter card connects to the data distribution crosspoint switch via one of the two special PMC FastChannel connectors on the Fastlmage1300 J1 is part of the Front PMC slot and J3 is part of the Rear slot The connector J3 shares data signals with the Channel Link Input connector When a FastChannel PMC daughter card is installed on J3 Channel Link Input lines will be replicated on J3 When Channel Link is installed a daughter card installed on J3 cannot simultaneously use its FastChannel connection The FastChannel I O signals share 28 lines with the Channel Link Output connector When Channel Link Output is to be installed FastChannel cannot be used simultaneously
6. Other Inputs Outputs 3 12 Outputs 3 2 FastChannel Digital Input Output 3 3 Channel Link Input Output 4 Daughter OCT Cm 4 F Local PCI Bus 4 THEORY OF 0 DI 102 V 07 Pr 5 Camera Type M 5 Analog Video enses ets tons toss onne onne eose eose oeen osav oeneoene een 5 1 NTSC PAL Composite and S Video Component 6 2 Monochrome and RGB Analog Video 7 C Digital H 7 1 Digital Control Inputs o eie He eee ended D 8 2 Camera ERA REVO E Urn HEAT 8 D FPGA Based Front End eee ee ee stas tatu sins tatu sens 20000080 00006 9 1 FPGA Run States etre ter rented etie 10 2 Input Signals from Line Cameras to 10 3 Input Signals from Frame Cameras to 11 4 NTSC PAL S Video Input Signals 11 5 JDataReorderng oeeeeto REED ID mee iE ERE 12 6 Image Distribution eiie ree rrr eR e ette t 12 7 Data Valid Signals eite tee ec EPOR ROS 12 E D
7. The 3 accelerator utilizes a 64Kx8 bit EPROM for video BIOS as well as program memory space This device shares a portion of the memory interface during boot up After the device has come up and been configured the EPROM pins go tri state and the SGRAM has control of the bus Any TriMedia processor can send its video output to the S8 VGA adapter This allows direct NTSC or PAL video output without a PMC module Alternately the S3 can be used to acquire video from an external source Three 0 to 1V RGB outputs plus TTL level synch signals drive a standard SVGA computer monitor SVGA monitor signals go out through a 68 pin high density connector J2 requiring use of Alacron monitor cables Two RS 170 level outputs provide either composite video NTSC or PAL or S video to drive a standard television monitor Composite and S video outputs share connector J2 with the SVGA outputs and the RS 232 port PCI PCI Bridge A Digital Semiconductor Intel 21150 PCI bridge chip isolates on board components from the host PCI bus while allowing a transparent data path between the host and on board secondary PCI buses This chip conforms to the PCI specification for bridges and is supported by most BIOSs While the bridge chip presents a single electrical load to the host PCI bus the four TriMedia processors SVGA adapter and PMC modules look like as many as seven devices to the host system BIOS The PCI standard allows each device behind a bridg
8. 022 60 43V 43V APMC 29 PMC1 D23 023 61 SCL SCL 30 43V PMC1 3V_APMC 62 PMC3 SDA SDA 31 PMC1_D24 APMC D24 63 4 SCL 32 PMC1 D25 025 64 4 SDA 4 SDA Table 9 PMC Pn4 Connectors J1 and J3 6 Power The Fastlmage Board has two Auxiliary Power Connectors a P5 5VDC for board 3 3VDC for APMC SLOT 43 Pin 1 2 amp 3 GND 4 45V All systems require at least one power cable supplying 5V to P5 b P13 3 3VDC PMC1 SLOT J1 Pin 1 3 3 PMC1 2 amp 3 GND 4 5V 7 Test Connectors a P10 Test TriMedia JTAG loop Pin Signal DBUG TRST Not used DBUG TCK DBUG TMS DBUG TDI DBUG TDO GND Table 10 Test Connector P10 OT CO N b P11 Test EVIP SAA7111A boundary scan Pin Signal 1 TDO BRIDGE 32 GND JTAG TRST JTAG TCK JTAG TMS JTAG TDI TDO EVIP N C N C GND Table 11 Test Connector P11 00 cd c P12 CPLD programming interface and boundary scan Pin Signal Pin Signal 1 GND 10 CPLD DIN 2 CPLD TDI 11 CPLD DOUT 3 CPLD TDO 12 CPLD CCLK 4 CPLD TMS 13 CPLD MODE 5 CPLD TCK 14 TST INO EXT TCK 6 GND 15 TST IN1 EXT TDI 7 CPLD PROG 16 TST IN2 EXT TMS 8 CPLD DONE 17 TST IN
9. ALACRON FASTSERIES FASTIMAGE 1300 HARDWARE USER S MANUAL FAST CAPTURE FAST PROCESSING FAST RESULTS FASTSERIES PCI BOARD FAST SEHIES PMCs FastVision FastMem Fastlmage 1300 Fast4 1300 FastFrame 1300 Fast 1300 30002 00176 COPYRIGHT NOTICE Copyright 2002 by Alacron Inc All rights reserved This document in whole or in part may be copied photocopied reproduced translated or reduced to any other electronic medium or machine readable form without the express written consent of Alacron Inc Alacron makes no warranty for the use of its products assumes no responsibility for any error which may appear in this document and makes no commitment to update the information contained herein Alacron Inc retains the right to make changes to this manual at any time without notice Document Name Fastlmage 1300 Hardware User s Manual Document Number 30002 00176 Revision History 2 0 June 4 2002 Trademarks Alacron is a registered trademark of Alacron Inc AltiVec is a trademark of Motorola Inc Channel Link is a trademark of National Semiconductor CodeWarrior is a registered trademark of Metrowerks Corp FastChannelO is a registered trademark of Inc FastSeries is a registered trademark of Inc Fast4 FastFrame 13006 Fastl O amp and FastVision are registered trademarks of Alacron Inc FireWire is a registered trademark of Apple Computer In
10. note that if is less than this signal will begin during one trigger cycle and end during the next The counters cannot be retriggered while running until the time programmed into COMP2 has elapsed The camera control signals provide a flexible control interface In a typical application a Cmp1 signal could be used to start camera exposure The corresponding Cmp2 signal could initiate transmission of the camera data to the Fastlmage The four external strobe signals on J1A J1B output the Cmp1 and Cmp2 signals from the two counters STROBE1 outputs Counter Cmp1 STROBE2 outputs Counter1 Cmp2 STROBES outputs Counter2 Cmp1 and STROBEA outputs Counter2 Cmp2 4 No Retrigger Cmp1Pls 100 gt iz Time 0 COMP2 Cmp2Pls Figure 5 Camera Control Output Signals b Master Clocks Four master clock outputs MASTER CKn to connector J1A J1B are provided to generate a time base for cameras These RS422 differential outputs are intended for use with line scan or area scan cameras which require an external time base Master clock outputs are generated by the primary and secondary TriMedias using the Al_OSCLK outputs Only one clock source is available on the single processor model These pins can generate any frequency from 1 Hz to 40 MHz in 07 Hz steps using the direct digital synthesizer of the TriMedia Nominal jitter on these outputs due to dig
11. 00 Crosspoint FPGAs enables use of register 36 as described below 0 1 IQ32B Crosspoint Switch U29 10 Front End FPGA 1 U31 Front End FPGA 2 U32 Table 23 Control Register Bits 1 0 48 36 45 4 52 Crosspoint control register 8 data bits Bit 0 selects the destination device for JTAG transfers see Table 23 Bit 1 when set to 1 resets Bits 0 and 1 of the Control Register register 35 described above to enable access to the Crosspoint FPGAs without re writing the control register Writing a 0 to this bit has no effect Bits 2 and 3 when set to 1 cause the Crosspoint FPGA1 and FPGA2 DONE lines to be driven low respectively When 0 the respective DONE line is tri stated Bit 4 selects the download mode when addressing either of the Crosspoint FPGA s bits 1 0 1x 1 in this bit position selects serial download the Xilinx style programming interface pins A 0 in this position selects download via the JTAG port Note that the JTAG port may also be used for boundary scan or for communication with user logic after download is complete Bits 5 and 6 when set to 1 cause the Crosspoint FPGA1 and FPGA2 INIT lines to be driven low respectively When set to 0 the respective INIT line is tri stated Bit 7 resets the device selected by bit 0 per Table 23 when written as 1 no action when written as 0 This is accomplished via the PROGRAM line which is pulsed low allowing re load of configuration data The bi
12. Control 19 38 Analog Input Cable 20 45 V 34 Interface Timing 20 38 NTSC S Video Conn P2 8 21 47 Low Speed Timing Signals 21 38 RS 232 Connector P4 22 47 Low Speed Timing Signals Fr 22 39 SVGA RGB Output Conn P5 23 48 Control Register Bits 24 49 Crosspoint Control register vi OTHER ALACRON MANUALS Alacron manuals cover all aspects of FastSeries hardware and software installation and operation Call Alacron at 603 891 2750 and ask for the appropriate manuals from the list below if they did not come in your FastSeries shipment 30002 00146 30002 00148 30002 00150 30002 00153 30002 00155 30002 00162 30002 00169 30002 00170 30002 00171 30002 00172 30002 00173 30002 00174 30002 00180 30002 00184 30002 00185 30002 00186 Fastlmage and FastFrame HW Installation for PCI Systems ALFAST Runtime Software Programmer s Guide amp Reference FastSeries Library User s Manual Fast Hardware User s Manual FastMem Hardware User s Manual FOIL FastSeries Object Imaging Library User s Manual ALRT Runtime Software Programmer s Guide amp Reference ALRT ALFAST amp FASTLIB Software Installation Manual for Linux ALRT ALFAST amp FASTLIB Software Installation for Windows NT Fastlmage 1300 Hardware User s Manual FastMem Programmer s Guide amp Reference FastMem Hardware Installation Manual Fast4 1300 Hardware User s Manual FastSeries Getting Started Manual FastVision Hardware
13. If the system includes a FastMem daughter card Ports A and B are inputs to the FastMem outputs from the Fastlmage1300 and Ports C and D are outputs from the FastMem inputs to the Fastlmage1300 If the system includes FastlO daughter card inputs the application may require a reordering of the data coming in to the FastlO from Taps 1 2 3 and or 4 and exiting the FastlO as FastChannel data ports A B C and D The mapping of input taps to FastChannel ports is shown in area C of the crosspoint Figure 10 above Each tap can connect to one or more of PortA PortB and PortD Multiple input taps can be multiplexed to PortA PortB or PortD FastChannel Port A also connects to the video input of the TriMedia processor TMO on the FastlO board Any data sent to FastChannel PortA from the FastlO also goes to TMO Some applications may require the ability to stream data to FastlO TMO via FastChannel PortA which acts as an output from the Fastlmage1300 in this case When PortA is used for streaming data from the Fastlmage1300 to the FastlO PortA cannot also be connected to any FastlO input taps FastChannel PortC is connected to the video output of TMO on the FastlO Port C cannot connected to any input taps Unused taps can be left unconnected When one is connected a Fast4 daughter card provides for distribution of data from any sources to multiple destinations within the board via its central crosspoint switch The desired mapping of data so
14. P3 8 TAP2 D5P 4 D5P P3 9 TAP2 D4P P3 10 TAP2 D3P 4 D3P P3 11 TAP2 D2P 4 D2P P3 12 TAP2 P3 13 TAP2 DOP 4 DOP P3 14 GND GND P3 15 TAP2 PXCKP 4 PXCKP P3 16 GPIN2P GPIN4P P3 17 TAP2 LVALP TAP4 LVALP P3 18 TAP2 FVALP TAP4 FVALP P3 19 N C N C P3 20 GPINSN GPINGN P3 21 STROBE 2N Output STROBE 4N Output P3 22 GPOUT2N Output GPOUTAN Output P3 23 MASTER CK2N Output MASTER CKAN Output P3 24 N C N C P3 25 TAP2 D7N 4 D7N P3 26 TAP2 D6N 4 D6N P3 27 TAP2 D5N 4 D5N P3 28 TAP2 D4N 4 D4N P3 29 TAP2 4 D3N P3 30 TAP2 D2N P3 31 TAP2 D1N 4 D1N P3 32 TAP2 DON 4 DON P3 33 N C N C P3 34 TAP2 PXCKN 4 PXCKN P3 35 GPIN2N 3 36 TAP2 LVALN 4 LVALN P3 37 TAP2 FVALN 4 FVALN Table 18 Digital Input Cable 10024 00161 DSUB37 Connector Analog Input Cable The Analog Input cable 10024 00162 has a 68 pin connector Cable P1 one end and four output connectors three BNC Cable P2 P3 and P4 and one DB 9F Cable P5 The Three BNC connectors are labeled P2 P3 and P4 Cable P1 mates with one of the 68 pin sockets in the dual 68 pin input connector J1A J1B on Fastlmage FastFrame and FastlO Table 18 shows the signals for the pins of P2 P3 P4 and P5 when connected to either J1A Conn Pin 1 1 Pin Signal J1B Signal P
15. Table 14 Jumper P9 4 P14 Jumper P14 enables programming of the EEPROMs for the four TriMedia processors Pin Signal 1 GND 2 FACT PGM 3 GND 4 SAFE BOOT Table 15 Jumper P14 Insert Jumper 1 2 to enable writing to all TriMedia boot EEPROMs Insert jumper 3 4 for safe boot up if EEPROM contents are invalid Jumper 3 4 must be removed after power on to allow the EEPROMS to be written 5 P16 Jumper P16 connects the various sources and destinations for interrupts Pin Signal HOST INTA APMC INTA TM1 INTB TM1 INTB GX2 INTA PMC1 INTA HOST INTC HOST INTA Table 16 Jumper P16 NI 01146 N For normal interrupt mode Host gets and 53 interrupts connect 1 2 5 7 and 6 8 For local interrupt mode TM1 gets and 53 interrupts connect 2 4 3 5 and 4 6 34 IV FASTIMAGE 1300 CABLES A Cable Summary The Fastlmage1300 uses the following cables e 10024 00160 Cable FastSeries Power e 10024 00161 Cable FastSeries Digital Input e 10024 00162 Cable FastSeries Analog Input e 10024 00175 Cable Fastlmage1300 Multifunction I O e 10024 00196 Cable Fastlmage1300 NTSC PAL and SVGA Output B Power Cables The auxiliary power cables 10024 00160 connect to the system power supply in the PC and to e Connector P5 required e Connector P13 optional Normally the auxiliary power cable P1 end is connect
16. in a single clock cycle 2 Local SDRAM Each TriMedia has 8 or 16 megabytes of local SDRAM The SDRAM is accessible from the host PCI bus via the bridge to allow the host to download programs and directly from the secondary PCI bus to allow the TriMedia to transfer data to each other at full PCI bandwidth All programs to be run in a TriMedia processor must reside in that processor s local SDRAM The 8 bit Video Input and Video Output from each TriMedia connect directly to the crosspoint 3 Video Data Paths Using the large crosspoint switch any TriMedia can receive video input from the SAA7111A video input processor or from an external analog or digital video source with or without frame buffering or directly from one of the PMC modules In all up to five video streams can be acquired at one time in the fully loaded configuration four by the TriMedias and one by the S3 Virge GX2 Each TriMedia has byte wide video input and output ports TriMedia video input ports accept ITU R BT 656 formerly CCIR656 encoded 8 bit color data as well as 8 and 10 bit raw data with sign or zero extend to 16 bits for 10 bit input When receiving color data in ITU R BT 656 mode the incoming data is automatically broken into three components and stored as separate arrays for Y Cr and Cb The maximum video input clock rate is 38 MHz in ITU R BT 656 mode or 80MHz in raw mode TriMedia video output ports can generate ITU R BT 656 encoded data streams
17. is broken into three fields The first consisting of just the MSB is the change detect bit A frame is only considered valid if this bit differs from the change detect bit of the previous frame The next field which is 7 or 6 bits for 8 and 9 bit data registers respectively denotes the internal register address The remaining low order 8 or 9 bits carry data Received frames are generated during JTAG download operations and in response to writes of the internal read request registers The most significant 4 bits of these frames identifies the source of the data in the lower 12 bits Note that when an odd number of frames are to be received a dummy read request is necessary to allow the DSP CPU to see the last frame because of the 32 bit internal interface of the V 34 SSI The TriMedia s V 34 SSI needs to be programmed to use separate clock and frame sync signals for transmit and receive This is accomplished by setting the V34 IO1 mode select bits to 10 and the V34 102 mode select bits to 11 The frame size and valid slot size should both be set to 1 slot All clock polarity shift direction sync mode and sync polarity bits should be set to 0 Endian mode select can be programmed as desired but in most cases should match the endian mode of the DSP CPU Internally the V 34 SSI uses a 32 bit interface This means that a minimum of two frames must be transmitted or received at a time When transmitting a single frame of valid data the other h
18. MASTER CK3P Output P2 5 GND GND P2 6 TAP1 D7P TAP3 D7P P2 7 TAP1 D6P D6P P2 8 2 9 2 10 P2 11 TAP1 D2P D2P P2 12 TAP3 D1P 2 13 TAP1 DOP DOP P2 14 GND GND P2 15 TAP1 PXCKP _ 2 16 GPIN1P GPINSP P2 17 TAP1 LVALP LVALP P2 18 TAP1 FVAL TAP3 FVALP P2 19 N C N C P2 20 EXT TRIG1N EXT TRIG2N P2 21 STROBE 1N Output STROBE Output P2 22 GPOUT1N Output GPOUTSN Output P2 23 MASTER CK1N Output MASTER Output P2 24 N C N C P2 25 TAP1 D7N TAP3 D7N P2 26 TAP3 D6N P2 27 TAP1 D5N 5 2 28 TAP1 D4N D4N P2 29 TAP1 D3N _ 2 30 TAP1 D2N 2 31 TAP1 D1N D1N P2 32 TAP1 DON TAP3 DON P2 33 N C N C P2 34 TAP1 PXCKN _ 2 35 GPIN1N GPIN3N P2 36 TAP1 LVALN TAP3 LVALN P2 37 TAP1 FVALN FVALN Table 17 Digital Input Cable 10024 00161 DSUB37 Connector P2 36 Conn Pin J1A Signal J1B Signal P3 1 GPINSP GPINGP P3 2 STROBE 2P Output STROBE Output P3 3 GPOUT2P Output GPOUTAP Output P3 4 MASTER CK2P Output MASTER CK4P Output P3 5 GND GND P3 6 TAP2 D7P TAP4 D7P P3 7 TAP2 D6P 4 D6P
19. Once set it stays on until the UART Status Register is read Receive parity error A one in this bit indicates that the most recently read character was received with incorrect parity This bit is not sticky if parity checking is desired the host must read status for each received byte Note that Mark and Space parity are not checked only Even or Odd parity Transmit Shift Register Empty A one in this bit indicated that the UART transmit shift register is empty All outgoing characters have been completely sent At this point the host may write two more characters without overrun Transmit Buffer Empty A one in this bit indicates that the host may write a new character to the transmit data buffer Previous characters may be still in process of transmission see Bit 2 Receive Data Available A one in this bit indicates that a new character is available for reading in the receive data buffer Characters must be read by the host before the next character is fully received to avoid overrun errors N B In order to reduce latency when reading the UART Status Register it is updated from internal flags when the subaddress becomes 00 This usually occurs as a result of writing 00 to address 0x54 but it can also occur due to wrap of internal subaddress after reading or writing subaddress Oxff Updating the status information has the side effect of clearing the internal sticky bits Rx and Tx overrun error bits 53 3 Su
20. P031 1 ADC2 CLK From FPGA1 to 5 170 ADC2 Table 5 1Q32B Signals Using the IQ32B crosspoint any of these clock signals can be connected to any other Each signal going through the crosspoint can be specified as an input output forced low or forced high signal The input output direction corresponds to the source of the clock Signals may be forced to low or high in the crosspoint a VI 1 4 and VO 1 4 The VI 1 4 CLK signals clock the video input data into the TriMedia while the VO 1 4 CLK signals clock the video output data out of the TriMedia Both these clocks can be generated and driven out by the TriMedia or received as inputs from the IQ32B Normally the Video Input clocks are connected via the IQ32B to some other clock signal and sent to the TriMedia while the Video Output clocks are sourced by the TriMedia b PROG CLK 1 2 PROG CLK1 and PROG are the Audio input over sampling clocks from the TriMedia They are spare clock sources programmable from 1 HZ to 40MHZ in increments of 0 3HZ c PIX CLK 1 4 26 The PIX CLK 1 4 signals are the master pixel clock for input data from the four taps These clocks are driven by the Digital Input taps and some Analog line scan cameras provide digital clocks The PIX CLK 1 4 signals are connected on the Fastlmage board to the FPGAs and the FPGA1 receives PIX CLK 1 3 while FPGA2 receives PIX CLK 1 3 and 4 For Analog input the EVIP
21. Specifications review the components and connections used for configuration and internal control diagrammed in Figure 19 IQ32B JTAG MAX521 DAC Crosspoint FPGAs Figure 19 Configuration and Control 1 2 Bus The primary TriMedia processor configures several peripheral devices via an internal 2 bus the Inter Integrated Circuit 2 wire serial bus Devices on the bus include the SAA7111A Enhanced Video Input Processor and the UART All peripherals the Fastlmage use 7 bit addressing The PCF 8575 Expander is accessed at 0x40 for a write 0x41 for a read The SAA7111A is accessed at 0x48 for writing and 0x49 for reading The MAX521 DAC is accessed at 0x50 for a write 0x51 for a read The UART is accessed at 0x54 for writing and 0x55 for reading The TriMedia processors also use their I2C bus lines to communicate to the front end FPGAs TM1 TM2 control FPGA1 while and TM4 control FPGA2 Cross connections between the FPGAs allow any processor to control either FPGA The TriMedia processor TM1 always present communicates with the UART via The UART provides transmit and receive data as well as one handshake input and one handshake output The handshake lines are under program control They typically tie to Data Terminal Ready and Data Set Ready lines of the remote equipment B V 34 SSI Interface TM1 to CPLD The CPLD accepts transmitted data from the primary TriMedia TM1 via t
22. as well as 8 bit raw data All video input and output data is passed between the port and the TriMedia local SDRAM 4 Local PCI Bus Data into and out of the Fastlmage can use the local PCI bus High speed devices connect to the secondary PCI bus via the PMC expansion connectors Video I O on the PMC card can use the PCI bus as well as the Video In Out ports of the baseboard The TriMedia supports this functionality directly via the image coprocessor unit When using the onboard S3 SVGA processed image data can be scaled and alpha blended as well 5 Interprocessor Communication The Fastlmage board uses the Video In and Video Out units for interprocessor communication as well as video I O A special message passing mode allows video outputs to connect to video inputs using 8 data bits along with start and stop message bits Figure 5 In message passing mode the Video Out unit can source data at up to 80 MB s and the Video unit can accept data at up to 80 MB s The Video Out unit has a programmable clock generator which can be programmed for byte rates of 4 to 80 MHz Thus interprocessor link byte rates can be tuned to optimize the bus and SDRAM usage TriMedia A TriMedia B VO DATA 7 0 VI DATA 7 0 STMSG VO 101 VI DATA 8 ENDMSG VO 102 VI DATA 9 VO CLK VI GLK 1 DVALID Figure 12 Message Passing Connections Video out in ports not in use for I O can tie to other TriMedia processors via t
23. assistance fix is not available right away often we can devise a work around that allows you to move forward with your project while we continue to work on the problem you ve encountered It is important that we are able to reproduce your error in an isolated test case You can help if you create a stand alone code module that is isolated from your application and yet clearly demonstrates the anomaly or flaw Describe the error that occurs with the particular code module and email the file to us at support alacron com We will compile and run the module to track down the anomaly you ve found If you do not have Internet access or if it is inconvenient for you to get to access copy the code to a disk describe the error and mail the disk to Technical Support at the Alacron address below If the code is small enough you can also FAX the code module to us at 603 891 2745 If you are faxing the code write everything large and legibly and remember to include your description of the error When you are describing a software problem include revision numbers of all associated software For documentation errors photocopy the passages in question mark on the page the number and title of the manual and either FAX or mail the photocopy to Alacron Remember to include the name and telephone number of the person we should contact if we have questions Alacron Inc 71 Spit Brook Road Suite 200 Nashua NH 03060 USA Telepho
24. data input and output registers it has several I O bits which can be accessed at different sub addresses Its internal registers are described in the UART Specification later in this manual M Power The Fastlmage1300 on board power supply provides the following DC DC conversions 23 3 3 16 5W typ 42 5V 10W typ Power connectors P5 and P13 supply additional 5V current using two Alacron 10024 00160 power cables P5 also supplies 3 3V power from an external source to the APMC inboard slot P13 also supplies 3 3V to the PMC1 outer slot N Clock Distribution The IQS32B crosspoint switch distributes the clock signals to the Fastlmage components as shown in Figure 17 24 CLK IQ32B APMC PXCK 1 4 PMC J4 TM1 VO1 CLK CONN J3 PROG CLK1 VI2 S3 LCLK PMC J4 CONN J1 TM2 VO2 CLK PROG CLK2 DO OR FastChannel 4 TM4 VO4 TM VIDCK Master Clock ppm 2 CLK Ted FPGA 1 FPGA1 ue 2 Channel Link DO PIXCK1 PIX CLK1 Input LE Drivers PIX CLK3 FPGA 2 RS 170 A Ds 3 These are normal I Os not global clock inputs to the FPGAs PIX CLK4 Figure 17 1032B Clock Distribution 1 1 2 Pins Ports and Signals Table 5 shows the signals to and from the IQ32B pins
25. from 600 to 19 200 bits per second 7or8 data bits e Selectable Odd Even Mark or Space parity RS 232 handshake lines software controlled one input one output General purpose parallel I O bits four outputs six inputs Simple programming interface e Direct access to PIC registers for ease of debugging e Powers on to 9600 Baud 8 data bits no parity handshake output high C Address The UART is addressed as a standard 7 bit peripheral at locations 0x54 write and 0x55 read Internal registers are accessed by sub address using the same procedure as accessing a standard EEPROM Multiple reads and writes are also possible The internal sub address is incremented after each access This again works just like a standard EEPROM D Interrupts The UART provides a common interrupt output pin This is an active low output Port A bit 4 intended for use as a level triggered interrupt source It is high inactive after a reset It is low active whenever received data is available It will also go low when a transmitted byte is moved from the internal transmit data buffer register to the UART transmit data buffer If no received data is present it will go high at the next access to sub address 00 This pin is pulled up and wired to the TriMedia PCI pin Note that the Transmit Buffer Empty condition will only create an interrupt when the state is entered Thus a program wishing to transmit UA
26. have given US he can solve the problem you ve cited When calling for an RMA number please have the following information ready Serial numbers and descriptions of product s being shipped back A listing including revision numbers for all software libraries applications daughter cards etc A clear and detailed description of the problem and when it occurs Exact code that will cause the failure A description of any environmental condition that can cause the problem All of this information will be logged into the report so it s there for the technician when your product arrives at Alacron Put boards inside their anti static protective bags Then pack the product s securely in the original shipping materials if possible and ship to Alacron Inc 71 Spit Brook Road Suite 200 Nashua NH 03060 USA Clearly mark the outside of your package Attention 80XXX Remember to include your return address and the name and number of the person who should be contacted if we have questions 61 C Reporting Bugs We at Alacron are continually improving our products to ensure the success of your projects In addition to ongoing improvements every Alacron product is put through extensive and varied testing Even so occasionally situations can come up in the fields that were not encountered during our testing at Alacron If you encounter a software or hardware problem or anomaly please contact us immediately for
27. loads clock and ID parameters from the EEPROM It then stays in a reset state waiting for the host to finish configuration The TriMedia reads all instructions from the local SDRAM After a reset it begins operation starting at the first location in SDRAM Thus the host is required to load code into each SDRAM before releasing the reset state of the TriMedia Standard PCI and Plug and Play reguires the host CPU to assign address bases and other parameters at start up 9 Peripheral Controls Each TriMedia processor can communicate with one of the two front end FPGAs via the internal bus TM1 and TM2 connect to FPGA1 and TM4 connect to FPGA2 Interconnections between the FPGAs allow any processor to control either or both FPGAs The TriMedia can send start stop or other messages to the FPGA via this bus TriMedia peripherals are controlled by registers located in the MMIO Memory Mapped I O aperture of each TM1300 s address space The memory map is shown figure 3 5 of the TM1300 data book Individual registers are described in detail in the chapters of their associated peripherals peripherals are accessed the primary TM1300 processor Devices on the bus include the PCF8575 Expander 16 bit port to control the FastChannel the SAA7111A Enhanced Video Input Processor the MAX521 DAC used for setting analog video gain and offset and the UART All C peripherals on the Fastlmage use 7 bi
28. number of processors also reduces the input bandwidth of the board The total input bandwidth is limited to 80 MB s per installed processor Also systems with just one processor will have one master clock output instead of two Each processor can have 8 16MB 32MB or 64MB of dedicated SDRAM All TMs on a given board must have the same amount of SDRAM C Analog and Digital Input The board has four inputs through each consists 8 bits data 2 bits control and pixel clock A TAP can be configured for analog input or for digital input but not both TAP1 through TAP3 can be populated as either digital input or 5170 compatible analog input 4 can be either digital input or composite analog input NTSC PAL SECAM or S Video Analog and digital video capture signals come in through the same dual 68 pin VHDCI connector J1A J1B In order to save pins analog and digital signals share pins allowing only one or the other for each of the four input taps Inputs from the four TAPs go to the Front End FPGAs with their associated frame buffers and then are routed via the crosspoint to the TriMedia or FastChannel 1 Analog Input Four RS 170 level video inputs allow selection from four composite video sources The same inputs can also be used in pairs to receive S video signals Note that only one composite component video stream can be captured at one time These inputs are multiplexed into a common conver
29. required LVDS and PECL interface drivers and receivers are available as selective stuffing options 8 bits Data CLK TAP1 LVAL FVAL 8 bits Data CLK TAP2 LVAL FVAL 8 bits Data CLK LVAL FVAL 8 bits Data CLK TAP4 LVAL FVAL Figure 4 Digital Video Input 1 Digital Control Inputs Four clock inputs TAPn PIXCK come in through the input connector J1A J1B These inputs are received by high speed RS422 differential receivers The outputs of these receivers go to the crosspoint PIX CLK1 should be used for multi tap cameras requiring both FPGAs Programmable clock polarity and input delay allow compensation for clock to data skew Eight additional control inputs TAPn LVAL and TAPn FVAL come in through the Digital input connector J1A J1B These inputs are received by high speed RS422 differential receivers The outputs of these receivers LVALn FVALn go to the FPGAs LVAL FVAL1 and 3 go to both FPGAs LVAL FVAL2 and 4 go to FPGA 1 only These lines may be used for frame valid and line valid signals when attaching multiple cameras Four general purpose static inputs GPINn are provided These inputs are received by RS422 differential receivers The outputs of these receivers go to the UART where they can be read by the primary TriMedia via the bus 2 Camera Controls Camera Controls are outputs sent back through the digital input connector J1A J1B Three kinds of controls are available start and exposur
30. tap B Analog Video Input Analog video capture signals come in the dual 68 pin VHDCI connector J1A J1B Three 8 bit RS 170 level video inputs can be used to capture images from three monochrome cameras or one RGB camera Each channel has sync detection and pixel clock generation to allow simultaneous acquisition from three independent non genlocked sources Sync and pixel clocks may also be driven from an external RS 422 source Independent offset and gain controls are available for each of the three channels Output from the A D converters can be further processed in the FPGA based digital front end 8 bits 5 170 A D c 8 bits RS 170 A D P TAP2 8 bits RS 170 A D c NTSC PAL S Video EVIP 4 Figure 3 Analog Video Input 1 NTSC PAL Composite and S Video Component Input A Philips SAA7111A Enhanced Video Input Processor digitizes composite or S video from any source adhering to the NTSC PAL or SECAM standards for 525 line 59 94 Hz and 625 line 50 Hz video The chip has four inputs VID1 through VID4 as shown in Table 1 Each input can receive a separate composite video sources one of which is selected to be sent through the processors Two S video sources can be connected Y on VID1 UV on VID3 or Y on VID2 UV on VIDA one of which is the selected input These inputs are multiplexed into a common converter two converters in S video mode The primary TriMedia controls the input sel
31. the Data Line Valid and CLK signals for the FPGA LVAL1 2 and 3 go to FPGA 1 LVAL1 3 and 4 go to FPGA2 A linear region of interest may be specified as begin and end points X Y To accommodate variations in camera timing the ROI may be specified as a negative value or as a point beyond the upper limit of the line Data 8 gt Region of Interest 0 X 1023 A 4 Line Valid To Crosspoint Figure 7 Line Camera Input Signals and Region of Interest 3 Input Signals from Frame Cameras to FPGA Data 8 Frame Valid Line Valid CLK To Crosspoint Figure 8 Digital Frame Camera Input Signals and Region of Interest For digital frame cameras the Data Line Valid Frame Valid and CLK input signals come directly from the digital input drivers For analog frame cameras the input data and controls go through the A D converters to be converted to the Data Line Valid Frame Valid and CLK signals for the FPGA LVAL1 FVAL1 2 and 3 go to FPGA 1 LVAL1 FVAL1 3 and 4 go to FPGA2 A rectangular region of interest may be specified as a rectangle with start and end pixels SP EP and start and end lines SL EL To accommodate variations in camera timing the ROI may be specified using negative values or outside the frame boundaries 4 NTSC PAL S Video Input Signals Composite or component video input to the SAA7111 Enhanced Video Input Processor EVIP is converted to YUV data that can be p
32. to external trigger inputs without a delay or on command of the primary TM1300 Camera exposure time is controlled by the delay between these signals and the line frame start signals Two master clock outputs are provided to generate a time base for cameras These RS422 differential outputs are intended for use with line scan or area scan cameras which require an external time base They are generated by the primary and secondary TM1300 s using the Al OSCLK outputs Only one of these signals is available on the single processor model These pins can generate any frequency from 1 Hz to 40 MHz in 07 Hz steps using the direct digital synthesizer of the TM1300 Nominal jitter on these outputs due to digital synthesis is 3 3 nanoseconds This will be reduced to less than 1 nanosecond in the TM1300 when the improved mode is used In TM1300 improved mode the frequency resolution is 0 3 Hz Four general purpose static outputs are provided These RS422 differential outputs can be written directly by the primary TM1300 via the bus D Other Inputs and Outputs The system can be configured with analog output FastChannel input output Channel Link input output or with no output 1 Analog Output Analog output can drive the system SVGA display and also provide NTSC TV output to a monitor SVGA monitor signals go out through 68 pin high density connector J2 Composite and S video outputs and the RS 232 port also share connector J2 and Chan
33. 2 JTAG ports Once the CPLD is programmed either by serial EEPROM or JTAG it will allow JTAG access to program all the other devices in its JTAG chain External programming of these devices is described in the CPLD Specification next section under External Five Wire Interface 43 VI CPLD SPECIFICATION The primary TriMedia processor communicates with this device via its V 34 synchronous serial interface The CPLD provides logic to convert the V 34 serial data to a JTAG stream for programming the IQ32B crosspoint switch and the two XCV50 FPGA s This device also provides variable time delays for camera and strobe control a capture control signal to the front end FPGAs and a clock mask loader for the PCI bridge chip A five wire auxiliary interface allows external connection to the JTAG interfaces for debug and test Note that each JTAG interface is accessed independently there are no chains This is accomplished by providing independent clocks TCK to each device and multiplexing the data outputs TDO from each device V 34 SSI Interface The CPLD accepts transmitted data from the V 34 SSI in 16 bit packets marked by the frame sync signal Each packet contains 8 9 bits of data and 7 8 bits of address control including a bit that must change state on each frame to indicate valid data This bit is necessary since the V 34 interface will continue transmitting the last data word when its transmit FIFO is empty The CPLD pr
34. 2 Center 10 Tap1 RS170 In Tap3 RS170 In P2 Shell 11 Tap1 RS170 Return Tap3 RS170 Return P3 Center 54 Not Used for Analog Tap4 EVIP VID3 In 37 P3 Shell 55 Not Used for Analog VID3 Return P4 Center 58 Tap2 RS170 In Tap4 EVIP VID1 In Comp Y P4 Shell 59 Tap2 RS170 Return EVIP VID1 Return 5 1 1 Tap1 Line Valid Pos Line Valid Pos 5 2 5 Tap1 Pixel Clock Tap3 Pixel Clock Pos 5 3 26 GND GND 5 4 27 Ext Trigger 1 Pos Ext Trigger 2 Pos 5 5 37 Strobe 2 Pos Strobe 4 Pos 5 6 2 Tap1 Line Valid Tap3 Line Valid Neg 5 7 6 Tap1 Pixel Clock Pixel Clock Neg 5 8 28 Ext Trigger 1 Neg Ext Trigger 2 Neg 5 9 38 Strobe 2 Neg Strobe 4 Neg Table 19 Analog Input Cable 10024 00161 The cable to J1A provides RS170 analog video inputs to Tap1 and Tap2 The cable to J1B provides RS170 analog input to Tap3 and composite or component video inputs to Tap4 A composite video source NTSC PAL SECAM can connect to either VID1 or VID3 the input to the EVIP is software downloadable A component S video source connects the Y luma component to VID1 and the C chroma component to VID3 E ChannelLink TV RS 232 Cable The Fastlmage1300 Multifunction cable 10024 00175 has a 68 pin connector Cable P1 on one end and five connectors on the other Two BNC connectors P2 for NTSC Luma Out and Cabl
35. 31 and 261532 footprint to allow upgrade to faster parts as required LVDS interface drivers and receivers are available as selective stuffing options 3 Digital Control Inputs Four special clock inputs are provided These inputs are received by high speed RS422 differential receivers The outputs of these receivers go to dedicated global clock inputs of the FPGA Programmable clock polarity and input delay allow compensation for clock to data skew Eight additional control inputs are provided These inputs are received by high speed RS422 differential receivers The outputs of these receivers go to the FPGA These lines may be used for frame valid and line valid signals when attaching multiple cameras Four general purpose static inputs are provided These inputs are received by RS422 differential receivers The outputs of these receivers can be read directly by the primary TM1300 via the bus 4 Digital Control Outputs Two outputs are provided for line or frame start These RS422 differential outputs are intended for uses with line scan or area scan cameras that require a scan start pulse They are generated in the CPLD in response to external trigger inputs after a programmed delay or on command of the primary TM1300 Two outputs are provided for exposure control These RS422 differential outputs are intended for uses with line scan or area scan cameras which require a scan start pulse They are generated in the CPLD in response
36. A eM 40 V 34 SSI Interface to CPLD oo oe enne seen sesta 40 Serial Communication Port 4 FPGA Serial Programming 41 42 JTAG Chain 1 Boundary Scan 21150 Bridge Chip and SAA7111A 42 TriMedia JTAG Chain 2 TriMedia 016 42 JTAG Chain 3 CPLD FPGAI FPGA2 Crosspoint FPGAs and IQ32B 43 CPLD SPECIFICATION 5 12 tee e e eai teet es eee o be ret aot deka saa AAK aUe osa s 44 34 SSLIMtErfAGE TRETEN 44 SOP GIRO VI AEP OF F ROSE SOF gt 5 NAWRWNS JTAG Titer lace 45 External Five Wire Interface eenseooonoonoonoonoonoonseosnaoononao on onnooosenoonaenoonae en suse tatnen snae 45 PCI Bus Secondary Clock Mask eee ee eee eee eerte seen s ense eese se enne eee 46 Low Speed Timing Functions eee esee ee seen en aeta ense on sens nae en suse tasse onne 0 46 CPLD Programming Requirements 47 Address Hex D scriptiOn eet 48 UART 5 H 51
37. Installation Manual FastVision Software Installation Manual vii INTRODUCTION A Fastlmage 1300 The Fastlmage1300 is an autonomous imaging system that can process up to four continuous video streams with minimal impact on the Host system The Fastlmage1300 system consists of a main board with one to four TriMedia TM1300 PCI media processors and memory Options include analog or digital input via a frame buffer unbuffered digital I O Channel Link I O analog output and one or two PMC daughter cards 24 bits RS 170 or Front End FastChannel RGB Analog Input FPGAs Digital O Frame CROSSPOINT Buffer FPGAs Channel Link Output NTSC PAL Svid video Analog Input Channel Link Input 32 bits Digital Input Fast Channel Fast PMC1 4 gt Analog Output Internal PCI Bus Fastlmage1300 Board PCI Bridge Host System PCI Bus Figure 1 Block Diagram of the FI1300 Board in a PC Chassis B Processors and Memory The Fastlmage 1300 can be configured with one or four Trimedia 1300 DSP processors 1 through TM4 The crosspoint switch eliminates the need to bypass missing processors video paths however zero ohm resistors will be required to complete the JTAG data loop in one CPU systems Sensing resistors will also be included to allow the bridge chip to disable unused clock lines on the secondary PCI bus Reducing the
38. JTAG header P10 is provided on the Fastlmage board Configuration bypass resistors are provided to complete the JTAG chain for the processors not installed The TM1300 processors that are standard on the Fastlmage support boundary scan However they also use the JTAG port for debugging from a remote host The TriMedia JTAG port allows access to internal registers for communication between a JTAG host and a debugger running in the TriMedia This is described in the TriMedia data book Note however that the JTAG port is not capable of downloading code or booting the TM1300 thus the basic SDRAM and PCI interfaces must be operational to use the debugger Each TriMedia processor along with its associated SDRAM and boot EEPROM makes up a complete subsystem which may be operated without bringing up the other processors In addition the SDRAM may be written and read by the host while the TriMedia processor is still held idle This allows simple host based memory testing before downloading TriMedia self test software Once the primary TriMedia has been tested other peripheral tests may proceed TriMedia peripheral operation can be tested using built in diagnostic loop back modes for both the Video In Out and Audio In Out systems 42 3 JTAG Chain 3 CPLD FPGA1 FPGA2 Crosspoint FPGAs and IQ32B A JTAG test header P12 is provided to allow cable access to the CPLD Front End FPGA 1 Front End FPGA 2 Crosspoint FPGA 1 and 2 and the 3
39. MP2 These are programmed to create timing events from 1 to 512 clock cycles after the trigger The value of COMP1 must be less than that of COMP2 Each counter can output four signals Two output signals Cmp1Pls and Cm2Pls are active high pulses 100 microseconds wide beginning at the times programmed in COMP1 and COMP2 A third output signal Cmp1 is an active high pulse which starts at the trigger and ends at the time programmed into COMP1 The fourth output signal Cmp2 is an active high pulse starting after the first 100 microsecond pulse and ending at the time programmed into COMP2 Cmp1 and Cmp2 from each counter run to the four strobe outputs 46 In external trigger mode the counters cannot be retriggered while running until the time programmed into COMP2 has elapsed The Strobe1 output will go high 150 to 250 microseconds after the rising edge of the trigger input Note that all inputs and outputs are differential High refers to the state where the STROBExP signal is high and STROBEXN signal is low After COMP1 1 100 microseconds Cmp1 will go low 100 microseconds later Cmp2 will go high COMP2 1 100 microseconds later Cmp2 will go low 100 microseconds later the circuit will be armed for triggering i No Retrigger Trigger Cmp1Pls A Cmp2 100 Sec n Cmp2Pls Figure 21 Low Speed Timing Signals External Trigger Mode In f
40. RT data should poll the status before sending the first byte under program control Subsequent bytes may be transmitted by the interrupt handler Also note that the interrupt may be cleared by reading incoming data during atransmission The interrupt handler should be prepared to handle this condition by checking to see if outgoing data is present and whether the transmit data buffer is empty after handling a received byte 51 Interrupts are not required to use the UART The UART Status Register can be polled to determine if received data is available and if the transmitter is ready to accept transmitted data Also the PCI INTC pin of the TriMedia which connects to the UART interrupt output can be programmed as a general purpose input pin and polled as well E Register descriptions 1 Subaddress 00 Write UART Control Register W 0 W 1 W 0 W 0 W 1 W 1 W 0 W 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 Reserved Should be set to zero for compatibility with future versions Bit 6 Handshake output Resets to one on power on The use of this bit is system dependant Writing a zero to this bit activates the RS 232 handshake output This may be wired to DCD and or DSR of the external device as required Bits 5 4 Parity These bits affect both transmit and receive parity Note that only odd or even parity are checked Mark or space parity is not checked Parity is always stripped from incoming data The bits encode as 00 No parity if 8 bit or spa
41. S EXT TRST 9 CPLD INIT 18 TST INA EXT ENA Table 12 Test Connector P12 B Jumpers The Fastlmage board has no user configurable jumpers The jumpers listed here are for Alacron use only 1 P3 Jumper block P3 is set at the factory to provide a basis for the CPU and DRAM clock speeds The TriMedia can multiply the external clock by 2 or 3 as selected by the EEPROM The default for 180 MHz TriMedia 1300s is CKn CPU 47 619 MHz SDRAM 142 85 MHz CPU to memory ratio 1 1 1 2 3 4 5 6 CKn CPU SDRAM CLK OUT OUT OUT 41 666 MHz 83 33 125 IN OUT OUT 44 444 88 89 133 33 OUT IN OUT 47 619 95 238 142 85 IN IN OUT 48 96 144 OUT OUT IN 50 100 150 IN OUT IN 55 556 111 11 166 67 OUT IN IN 57 143 114 29 171 43 IN IN IN 60 120 180 Table 13 Jumper P3 33 Jumper block P4 enables the S3 Virge GX2 bus control signals to go to the monitor Analog output P4 1 2 connects the SDA signal and P4 3 4 connects the SCL signal 3 P9 Jumper block P9 is set at the factory for other internal clock speeds The default for digital input is EL OSC1 80 MHz TM VIDCLK 80 MHz The default for analog input is EL OSC1 75 MHz TM VIDCLK 75 MHz 1 2 3 4 5 6 EL OSC1 TM VIDCLK OUT OUT OUT 73 MHz 73 MHz IN OUT OUT 74 74 OUT IN OUT 75 75 IN IN OUT 76 76 OUT OUT IN 77 77 IN OUT IN 78 78 OUT IN IN 79 79 IN IN IN 80 80
42. ack over the steps in the guide Check the programming examples supplied with the runtime software to see if you are using the software according to the examples Review the return status from functions and any input arguments Simplify the program as much as possible until you can isolate the problem Turning off any operations not directly related may help isolate the problem Finally first save your original work Then remove any extraneous code that doesn t directly contribute to the problem or failure 59 X ALACRON TECHNICAL SUPPORT Alacron offers technical support to any licensed user during the normal business hours of 9 a m to 5 p m EST We offer assistance on all aspects of processor board and PMC installation and operation A Contacting Technical Support To speak with a Technical Support Representative on the telephone call the number below and ask for Technical Support Telephone 603 891 2750 If you would rather FAX a written description of the problem make sure you address the FAX to Technical Support and send it to Fax 603 891 2745 You can email a description of the problem to support alacron com Before you contact technical support have the following information ready Serial numbers and hardware revision numbers of all of your boards This information is written on the invoice that was shipped with your products Also each board has its serial number and revision number written on either in i
43. alf of the 32 bit word can be filled with a copy of the valid word the second frame transmitted will be ignored by the CPLD because the change detect bit matches the first frame Alternately the unused half of the word can be all 15 or all 0 s which are not mapped to valid internal registers When using the latter approach it is important to note the order of transmission which is determined by the Endian Select bit in the SSI Control Register 1 Serial Communication Port UART A simple UART drives a four wire RS 232 interface J6 to allow asynchronous communication at 600 to 19 200 baud for camera setup and low speed control Two wires implement standard transmit and receive data The other two implement input and output handshakes These signals are directly programmable by the primary TriMedia using the bus to access the internal registers of the UART This port is provided primarily to allow camera configuration data to be downloaded without the use of a host system communication port See the UART Specification later in the manual 2 FPGA Serial Programming 41 The Xilinx serial data interface allows in system programming of the FPGA from the CPLD using the slave serial mode of the FPGA It is also possible to use the JTAG port for configuration This interface sends 8 bits of data for each data word written at 10 MHz Register bits are provided to drive the PROGRAM INIT and DONE lines and to read their current state Xilinx too
44. ansmitter is shut down The low 8 or 9 bits of the transmitted word contain data Internal registers and their function are described below Bits 15 through 10 of the received data indicate the data source as follows e 0101xx JTAG TDO read back of device xx xx is per Table 22 below 1000yy Internal Control register yy read back 110022 Crosspoint Control register zz read back 44 20MHz FQ 3 0 2009906000000000600900000000000060090 TxDATA em eee eese poo usc e PAGE DRESS A po a RxDATA eee eee Toni Figure 20 V 34 Interface Timing B JTAG Interface JTAG data is provided as pairs of 8 bit words one serialized onto the TMS line and the other onto the TDI line This is a standard format used by the l Cube tools to store JTAG stream data The clock line to be driven is selected by bits in the control register Actual transmission of the JTAG stream starts after the TDI word is written Thus a typical sequence would write a TMS byte followed by a TDI byte however during long downloads
45. baddress 01 Write Transmit Data Register Writing to the Transmit Data Register initiates a UART transmission Either 7 or 8 bits of data written to this register are valid depending on the word size selected in the UART Control Register The UART status register must be read to make sure the transmit buffer is empty before writing new data to the transmit data register Attempting to write data to the Transmit Data Register while the buffer is full will result in the new data being dropped and the Transmitter Overrun bit being set in the UART status register 4 Subaddress 01 Read Receive Data Register Data received by the UART can be read from the Receive Data Register UART status register bit O indicates when data is available to be read Reading this register when the Receive Data Available status bit is not set may result in loss of data 5 Subaddress 02 Write Ports A B latch Bits 7 6 Reserved Set to 00 for compatibility with future revisions Bit 5 Multitap bit A one in this bit position causes nibble swapping in the front end input logic so each FPGA gets half 4 bits of each input tap A zero in this bit position unswaps the nibbles so each FPGA gets two complete 8 bit taps Bit 4 Power Reset bit active low 0 reset This bit comes up 0 active It holds off the CPLD and clock chips from driving the V 34 IO pins Do not program this bit high until the V 34 IO pins have been programmed as inputs This fixes a
46. bug in the TriMedia SSI which causes the V 34 IO pins to initialize as outputs Caution while this fixes the bug at power on subsequent resets without power cycling can cause the V 34 to reset to its improper condition while the PIC has already been programmed to release the Power Reset bit It is probably a good idea to program this bit back to zero when the V 34 interface is not in use at least when using TriMedia processors Bits 3 0 General purpose outputs Writing these bits sets the output latches for the associated pins Bit 3 is general purpose output 4 to differential outputs on pins J1B 33 and J1B 34 Bit 2 is general purpose output 3 to differential outputs on pins J1B 31 and J1B 32 Bit 1 is general purpose output 2 to differential outputs on pins J1A 33 and J1A 34 Bit 0 is general purpose output 1 to differential outputs on pins J1A 31 and J1A 32 6 Subaddress 02 Read Ports B Pins Bits 7 4 General purpose inputs Reading these bits always results in the current value on the associated input pins Bit 7 is general purpose input 4 from differential inputs on pins J1B 61 and J1B 62 Bit 6 is general purpose input 3 from differential inputs on pins J1B 7 and J1B 8 Bit 5 is general purpose input 2 from differential inputs on pins J1A 61 and J1A 62 Bit 4 is general purpose input 1 from differential inputs on pins J1A 7 and J1A 8 Bit 3 Multitap bit Read back of current value Bits 2 1 General purpose inputs Reading th
47. c is a trademark of 3M Company MS 0056 is a registered trademark of Microsoft Corporation SelectRAM is a trademark of Xilinx Inc Solaris is a trademark of Sun Microsystems Inc TriMedia is a trademark of Philips Electronics North America Corp Unix is a registered trademark of Sun Microsystems Inc Virtex is a trademark of Xilinx Inc Windows Windows 95 Windows 98 Windows 2000 and Windows NT are trademarks of Microsoft Corporation trademarks are the property of their respective holders Alacron Inc 71 Spit Brook Road Suite 200 Nashua NH 03060 USA Telephone 603 891 2750 Fax 603 891 2745 Web Site http www alacron com Email sales alacron com or support alacron com TABLE OF CONTENTS Copyright Notice c ii Table of Contents iii Manual Figures amp Tables vi Other Alacron Manuals cece ee Hmmm eme ee ener vii UNTRODUCTION Br 1 A FastImage 1300 1 Processors and Memory oe enne 1 C Analog and Digital 2 1 Analog tne masai klaaskatus lila 2 2 Digital Input eret EE 2 3 Digital Control Inputs ioi teet eterne e ede ete re eee recede ends 2 4 d Digital Control Outputs 3
48. c P1 6 P5 11 MON 100 Mon I D 0 P1 41 P5 12 DDC SDA Mon 1 0 1 SDA P1 7 P5 4 MON ID2 Mon 1 0 2 P1 42 5 15 DDC SCL Mon I D 3 SCL Table 22 SVGA RGB Output Connector P5 F NTSC TV Out Cable The Fastlmage1300 NTSC TV Output cable 10024 00196 is the same as the 10024 00175 cable but without the RS 232 and Channel Link connections 10024 00196 has a 68 pin connector Cable P1 on one end Cable connector P1 mates with the 68 pin socket J2 on the Fastlmage1300 The three other connectors are the same as the TV and SVGA output connectors on the 10024 00175 cable Two connectors P2 for NTSC Luma Out and for Chroma Out The pinouts for these two connectors are identical to P2 and P3 on the 10024 00175 cable Table 18 e One D sub 15 connector P5 for RGB output the pinout for this connector is identical to P5 on the 10024 00175 cable Table 20 FastChannel Digital Output 4 J5 Digital output connectors J4 and J5 are 50 pin connectors on the top edge of the PCI Card Each connector outputs 16 bits of digital data and 12 bits of digital control All signals are differential consisting of a positive and a negative signal pair There is no Alacron cable for this output The customer can make a pair of 50 pin ribbon cables with standard cable hardware to route these signals to another board in the same chassis 39 V PROGRAMMING CONFIGURATION AND TEST This section along with the CPLD and UART
49. ce parity if 7 bit Power on default 01 Mark parity 10 Even parity 11 Odd Parity Note that parity other than 00 results in a 9 bit data word if 8 bit word length is selected An 8 bit data word with mark parity resembles 8 bit data with no parity and 2 stop bits Bit 3 Word length Selects number of bits exclusive of parity 0 7 bits plus parity 1 8 bits plus parity if not 00 power on default Bits 2 0 Baud rate Currently available standard Baud rates are 000 600 001 1 200 010 2 400 011 4 800 100 9 600 power on default 101 19 200 11x Reserved 52 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R x 1 6 5 4 3 2 1 Subaddress 00 Read UART Status Register Bit O Reserved for future use Currently reads zero but user code should not depend on this Handshake input The use of this bit is system dependant A zero in this bit indicates an active RS 232 handshake input This may be wired to DTR of the external device as required Transmitter overrun A one in this bit indicates that the host master has attempted to write data to the transmit buffer when it was still full This is a sticky bit Once set it stays on until the UART Status Register is read Receiver overrun A one in this bit indicates that the host master did not read the receive data buffer in time and an incoming character has been dropped This is a sticky bit
50. drives PIX CLK4 d ADC 1 3 The ADC 1 3 CLK clocks connect to the A D converters Some analog cameras provide an external clock this external clock is sent to the A Ds via the crosspoint Other analog cameras generate only VSYNC and HSYNC and for these the Front End FPGAs generate the ADC 1 3 CLK clocks Some multi tap analog cameras provide an external clock only on the first tap this clock may be sent to all three ADCs e TM VIDCK The Clock Generator a CY2292 part generates TM VIDCK which can serve as a Master Clock TM VIDCK is jumper selectable see the chapter Connectors and Jumpers for details on the available speeds f PXCK 1 4 The pixel clocks for the PMC connector J3 PXCK 1 4 can be generated by TriMedia on the daughter card connected to J3 or can be tied via the IQ32B to clocks originating on the Fastlmage g FPGA 1 2 PIXCK 1 2 and FE OUTCLK FPGA1 receives two general purpose pixel clocks FPGA1 PIXCK1 and FPGA1 PXCK2 and a shared clock FE OUTCLK commonly used to clock data between the FPGAs and the TMs FPGA2 receives two general purpose pixel clocks FPGA2 PIXCK1 and FPGA2 PXCK2 and the shared clock FE OUTCLK h DO PIXCK 1 4 DO PIXCK 1 4 is the clock for FastChannel digital O as well as for processors on PMC connector J1 DO PIXCK 1 4 can be generated by the FastChannel input or by TriMedia on the PMC daughter card connected to J1 or can be tied via the IQ32B
51. e P3 for Chroma Out One DB 9M connector P4 for RS 232 One D sub 15 connector P5 for RGB output One mini D 26 ribbon connector P6 for Channel Link Input not Output Cable connector P1 mates with the 68 pin socket J2 on the Fastlmage1300 Table 20 shows the signals for the pins of NTSC S Video connectors P2 and P3 when P1 is connected to J2 Cable P1 Pin Connects to Board Signal External Signal P1 8 P2 SHELL VGND CVBS return P1 9 P2 CENTER NTSC OUT CVBS Luma P1 43 P3 SHELL VGND Chroma return P1 44 P3 CENTER CHROMA OUT Chroma Table 21 shows the signals for the pins of RS 232 connector P4 when P1 is connected to J2 Table 20 NTSC S Video Connectors P2 and P3 Cable P1 Pin Connectsto Board Signal External Signal P1 12 P4 5 GND Ground P1 11 P4 3 RS232 TXD TxData P1 46 P4 2 RS232 RXD RxData P1 13 P4 4 RS232 HSHKO DTR P1 47 P4 6 RS232 HSHKI DSR Table 21 RS 232 Connector P4 38 Table 22 shows the signals for the pins of SVGA output connector P5 when P1 is connected to J2 Cable P1 Pin Connects to Board Signal External Signal P1 1 5 7 Green return P1 2 5 2 GREEN Green P1 36 5 6 VGND Red return P1 35 P5 1 RED Red P1 38 P5 8 VGND Blue return P1 37 P5 3 BLUE Blue P1 5 P5 10 VGND Hsync return P1 4 P5 13 HSYNC Hsync P1 40 P5 5 VGND Vsync return P1 39 P5 14 VSYNC Vsyn
52. e ee esee esee ee eene tenens etna etas eta seta sete stesse toast seen ae 60 Returning Products for Repair Replacements eere eee esee eese enata n oone ne 61 Reporting ce P 62 MANUAL FIGURES amp TABLES FIGURE PAGE SUBJECT TABLE PAGE SUBJECT 1 1 Block Diagram of the 1300 1 6 Composite Analog Video Inputs 2 5 Data Flow of the Fastlmage 2 7 8 Bit Analog Input Channel 3 6 Analog Video Input 3 21 FastChannel Interface Controls 4 7 Digital Video Input 4 21 I O Expander Registers 5 9 Camera Control Output Signal 5 IQ32B Signals 6 10 Front End Comp 8 Data Flow 6 29 A D Input Connector J1A J1B 7 11 Line Camera Input Signals 7 30 Analog Output CL RS232 Conn 8 11 Digital Frame Camera Input S 8 31 FastChannel Digital Conn 9 12 NTSCPAL S Video Input S 9 32 PMC PN4 Connectors J1 J3 10 14 Main Crosspoint Switch Conn 10 32 Test Connector P10 11 16 Processors and Memory 11 33 Test Connector P11 12 17 Message Passing Connection 12 33 Test Connector P12 13 18 Audio Connections 13 33 Jumper P3 14 19 Interrupts 14 34 Jumper P9 15 20 FastChannel Input Output 15 34 Jumper P14 16 22 Analog Output 16 34 Jumper P16 17 25 IQ32B Clock Distribution 17 36 Digital Input Cable DSUB37 P2 18 28 FI1300 Front Panel Bracket 18 37 Digital Input Cable DSUB37 19 40 Configuration amp
53. e internal V 34 to JTAG interface from the TriMedia is disabled At this point the remaining lines have the usual JTAG functions when accessing the crosspoint switches When either of the FPGAs is selected the EXT TRST line acts as the PROGRAM signal to the selected FPGA Once the CPLD has been configured its JTAG lines are available as I O pins These pins are available on the same header as the external five wire interface While EXT ENABLE is held low the CPLD s TDO line passes through the TDO signal from the selected device The TMS and TDI lines are used to select the device per Table 22 where 5 is bit 1 and TDI is bit 0 The CPLD s line should remain low during this time to prevent the boundary scan circuitry from inadvertently reprogramming the part CPLD INIT selects between the two crosspoint FPGAs when TMS TDI 0 0 In order to keep the interface as close as possible to a direct JTAG connection to the selected device all JTAG signals are routed combinatorial there is no shift register stage passing through the CPLD This added delay must be taken into consideration when selecting a test clock frequency for the external device D PCI Bus Secondary Clock Mask A parallel in serial out shift register is implemented in the CPLD to load the secondary clock mask into the 21150 bridge chip after PCI reset Sense signals from the PMC slots and TriMedia processors except the first which must always be prese
54. e signals master clocks and general purpose control signals Frame Line Start and Exposure Four strobe lines STROBE1 STROBEA are output to connector J1A J1B These RS422 differential outputs are for line scans or area scans cameras that require a scan start pulse readout or exposure control signals e g EXSYNC and PRIN to Dalsa cameras The CPLD has two counters for generating line frame start and exposure timing signals Figure 5 These 9 bit counters run at 10 KHz allowing timing from 100 microseconds to 50 milliseconds The counters are triggered by the rising edge of one of the two EXT TRIGn inputs from J1A J1B Upon triggering they count up from zero and stop when they reach maximum count 511 Two 9 bit compare registers 1 and COMP2 are associated with each counter These are programmed to create timing events from 1 to 512 clock cycles after the trigger In normal usage the value of COMP 1 is less than that of COMP2 Four output signals per counter Cmp1 Cmp1Pls Cmp2 and Cmp2Pls are run to the crosspoint where they can be selected to run to the four strobe lines Signals Cmp1Pls and Cmp2Pls are active high pulses 100 microseconds wide beginning at the times programmed in COMP1 and COMP2 is an active high pulse which starts at the trigger and ends at the time programmed into COMP1 Cmp2 is an active high pulse starting at the time programmed into COMP1 and ending at the time programmed into
55. e to have its own configuration space and the PCI BIOS code sets up these devices individually 22 21150 bridge chip has configuration space registers which are described in the data book chapter 14 Many of these registers are standard for all PCI to PCI bridges and should be handled by the system BIOS Registers which must be handled by Alacron software are listed in section 14 2 Device Specific Configuration Registers Of these the Secondary Clock Control Register is loaded by on board hardware Most of the other registers are left in their default states J Slots The Fastlmage incorporates two 32 bit PCI Mezzanine Card PMC slots The first PMC slot PMC1 connectors P1 P2 connects the FastlO or any single width standard length PMC module to the Fastlmage internal bus with access to the rear I O connector panel on the PC chassis The corresponding PMC FastChannel connector J1 on the board provides a direct connection to the crosspoint switch on the Fastlmage The second slot P6 P7 is available for boards with no requirement for panel space This slot is intended for adding TriMedia processors or memory The corresponding PMC FastChannel connector on the board provides a direct connection to the crosspoint switch on the Fastlmage NOTE The data pins on PMC2 FastChannel connector J3 are shared with the Channel Link digital input signals This connector can be used for communication wi
56. ection using the bus to access the SAA7111A registers J1B Pins J1B Signal Analog In to EVIP EVIP Input Pin 58 59 4 00 GND VID1 56 57 4 D1 GND VID2 Al12 54 55 TAP4 D2 GND VID3 21 52 53 GND VIDA Al22 Table 1 Composite Analog Video Inputs The SAA7111A outputs 8 bit parallel digitized video encoded per ITU R BT 656 which can be directly acquired by the TriMedia processors or the S3 Virge GX2 The pixel rate is phase locked to the horizontal scan rate of the input image and is nominally 13 5 MHz Since each pixel requires 16 bits of data the data output clock rate is 27 MHz Color video requires three values per pixel NTSC and PAL use Y luminance Cr red portion of chroma and Cb blue portion of chroma For eight bit resolution of each component 24 bits per pixel would be required The pixel size of 16 bits rather than 24 bits is realized by sub sampling the chroma portion of the input signal per ITU R BT 601 ITU recommendation broadcast television 601 formerly known as CCIR601 13 5 MHz 4 2 2 encoding standard The mnemonic 4 2 2 refers to the fact that for every four pixels luminance Y is sampled four times while chroma Cr and Cb components are only sampled twice This sub sampling is in line with the chroma bandwidth limits of the NTSC PAL standards and does not cause a degradation of picture quality 2 Monochrome and RGB Analog Video Inp
57. ed to the Fastlmage1300 connector P5 board at manufacture On the P1 end of the cable pin 4 is Vcc 5 pins 2 and 3 are GND pin 1 is 3 3V for the connectors Fastlmage connector P5 supplies 5V to the main board Two power cables are needed to operate two PMC daughter cards On each power cable connect the orange 3 3V wire to the system power supply When 3 3V supplies are hooked up P5 supplies 3 3V to the APMC slot the slot away from the rear panel and P13 supplies 3 3V to the PMC1 slot the daughter card slot near the rear panel C Digital Input Cable The Digital Input Cable 10024 00161 is a Y cable with one 68 pin connector Cable P1 and two 37 pin female DSUB37 connectors Cable P2 on the direct cable to Cable P1 and Cable at the end of the Y Cable P1 mates with one of the 68 pin sides on the dual 68 pin connector J1A J1B on both Fastlmage1300 Tables 1 and 2 show the signals at the pins of P2 and P3 respectively when connected to either J1A or J1B Each digital input signal is a differential pair The positive true signal has suffix P in the tables the negative true signal has suffix N 35 Conn Pin J1A Signal J1B Signal P2 1 EXT TRIG1P EXT TRIG2P P2 2 STROBE Output STROBE 3P Output P2 3 GPOUT1P Output GPOUTSP Output P2 4 MASTER Output
58. er card supplies additional digital or analog I O e FastMem daughter card supplies up to 512MB of global SDRAM Each of these products is described in its own documentation set F Local PCI Bus All other data into and out of the Fastlmage use the PCI bus High speed devices such as IEEE 1394 FireWire connect to the secondary PCI bus via the PMC expansion connectors Additional devices can be connected to the host s primary PCI bus Il THEORY OF OPERATION This chapter describes the camera connections internal data flow paths and other functional components of the Fastlmage board FastChannel Crosspoint Figure 2 Data Flow in the Fastlmage S3 VGA TV Outputs Input data from the camera is converted as needed into RGB or YUV digital data by the front end and distributed to the TriMedia processors via the crosspoint Output data from the TriMedia goes via the crosspoint to the S8 SVGA TV outputs and can also be routed among the TriMedia and to and from PMC daughter cards The FastChannel I O connects directly to the crosspoint as a separate source or as a destination for TriMedia output A Camera Types A camera can be digital or analog line or frame single or multi tap Common configurations are Three 8 bit RS 170 cameras plus one NTSC PAL S Video camera e Four 8 bit asynchronous digital cameras quad single tap e Two 16 bit digital cameras dual two tap e One 32 bit digital camera single four
59. er input enables are active low i e writing a zero turns the receivers on The bit layout of each register is the same as shown inTable 4 Any enabled inputs can potentially fight with the crosspoint switch if the switch is not properly configured A safe approach to enabling FastChannel I O is to disable all inputs and outputs while downloading the FPGAs Signal direction is not intended to be dynamic Direction should be specified in the digital output profile either as an 8 bit entry or 8 individual 1 bit entries Enables may also be specified in the digital output profile however there should also be an function to enable or disable O using an 8 bit mask If not specified in the profile signals should remain disabled until the API function is called Bit FastChannel I O Data Control Bits Affected 0 00 03 C1 CLK1 1 D4 D7 2 D8 D11 C2 C3 CLK2 3 D12 D15 4 016 019 C4 C5 CLK3 5 D20 D23 6 D24 D27 C6 C7 CLK4 7 D28 D31 Table4 Expander Registers 21 H Analog Output The S3 Virge GX2 2D 3D accelerator provides standard SVGA output at resolutions up to 1280 by 1024 pixels and 72 Hz frame rates non interlaced It also provides an NTSC PAL compatible monitor output for 525 line 59 94 Hz and 625 line 50 Hz video Crosspoint Switch SVGA Out J2 S3 GX2 SVGA Graphics Accelerator NTSC Analog Out J2 Internal PCI Bus Figure 16 Analog Output
60. ese bits always results in the current value on the associated pins Bit 2 is general purpose input 6 from differential inputs on pins J1B 29 and J1B 30 Bit 1 is general purpose input 5 from differential inputs on J1A 29 and J1A 30 54 Bit 0 Power Reset bit active low 0 reset Read back of current value 7 Subaddresses 03 FF PIC Register File Access to the entire register file of the PIC16C63 allows for debugging and some amount of control Note that indiscriminate writes to this area can crash the PIC program and make the UART inaccessible Among other things note that the register file includes access to the PIC program counter and the synchronous serial port C port control registers It also includes all of the USART registers allowing alternate uses of this port Some useful cases are listed below PORTA 05 PORTB 06 flags 26 UARTctrl 2A t ticks 2E SPBRG 99 The low order four bits are best accessed via the Port A B pins register at subaddress 02 Bits 4 and 5 are the UART interrupt active low output and the RS232 handshake active low output respectively This port has four outputs and four inputs which can be accessed via the Port A B pins register at subaddress 02 Reading PORTB directly allows you to read back the value of the four general purpose output bits Read this location to check UART status without clearing the sticky bits It contains a subset of the UART Status Register bit
61. f the Crosspoint FPGA2 and FPGA1 INIT signals respectively Bit 4 returns the current value of the Xilinx mode bit see Crosspoint control register bit 4 Bits 3 and 2 indicate the current state of the Crosspoint FPGA2 and FPGA1 DONE signals respectively Bit 1 returns 1 if the Crosspoint FPGAs are selected by bits 0 and 1 of the Control Register Bit 0 returns the currently selected device number Table 2 The bit layout of this register was intentionally designed to allow software to program the Crosspoint FPGAs in an identical manner to the Front End FPGAs 49 54 58 59 5 5 5 50 5E 5F 62 Read control and status Data bits are ignored Writing this location causes the control and status to be sent to the received data port Bits 15 through 12 of the received data are 1000 binary to indicate control and status read Bits 11 through 8 indicate the state of the external five wire interface lines except the clock Bit 7 returns the current state of the CAPTURE bit Bits 6 and 5 indicate the current state of the FPGA2 and 1 INIT signals respectively Bit 4 returns the current value of the Xilinx mode bit see control register bit 4 Bits 3 and 2 indicate the current state of the FPGA2 FPGA1 DONE signals respectively Bits 1 and 0 return the currently selected device number per Table 3 ST1C1 Slow timer 1 compare register 1 9 data bits Indicates delay to compare pulse 1 in units of 100 microsecond
62. he V 34 SSI in 16 bit packets marked by the frame sync signal Each packet contains 8 bits of data and 8 bits of address control including a bit which must change state on each frame to indicate valid data This bit is necessary since the V 34 interface will continue transmitting the last data word when its transmit FIFO is empty 40 The CPLD provides independent frame sync signals for transmit and receive sections of the V 34 SSI The transmit frame sync runs continuously one sync for each 16 clocks The receive frame sync only runs when there is data to be transferred from the CPLD to the TriMedia The receive clock is also gated off when there is no data available Note that with continuous receive channel transmission a protocol such as that used for the transmit channel could be used but it would burden the DSP CPU with regular interrupts whether or not data was being transferred 1 can access CPLD input and output bits via the V 34 SSI interface Writing output bits is similar to writing JTAG data Reading input bits requires a write to a control location which causes the data to be sent back on the receiver interface Because the TriMedia s V 34 receiver packs 16 bit frames into 32 bit words a dummy read is required to make the data available to the TriMedia processor when an odd number of reads are performed The 16 bit transmitted frame transmit vs receive is defined per the TriMedia data book from the perspective of the DSP CPU
63. he crosspoint switch to form a pipeline using message passing mode This allows DMA data transfer between connected processors at 80 megabytes per second without use of the PCI bus Independent video input and output modules in the TriMedia allow these data transfers to occur in parallel with CPU operations Simultaneous transfers can also occur between processors over the secondary PCI bus 6 Audio Input and Output TriMedia processors have built in Audio Input and Output interfaces These synchronous serial ports are intended for stereo digital audio processing but can be used as general purpose block DMA devices Each TM1300 has one audio input AISD1 and four outputs AOSD1 AOSD2 AOSD3 and AOSD4 The AISD1 and AOSD lines are from adjacent processors are brought to common connectors along with the corresponding clocks The output only lines go to separate connectors one per processor InOut1 InOut1 InOut1 Out2 4 Out2 4 Out2 4 TM2 TM3 TM4 Figure 13 Audio Connections 7 Interrupts In the normal configuration the primary TM1 sends and receives HOST INTA from the PCI interface on its PCI INTA pin The other three TriMedia processors receive HOST INTC on the PCI INTA pin and HOST INTA on the TM1_INTB pin as diagrammed in Figure 14 On the PMC slots HOST INTA connects to PCI B to B C to C and D to D Thus when a daughter card processor interrupts on PMC interrupt line A it gets back t
64. igital Crosspoint 13 F Processors Memory 15 1 T Media Processos e scat nr DR er 16 23 SDRAM ai dederit 16 3 Video Data Paths oue pev EE 16 4 PGL BUS eee EFE eg eter I rab E ME 17 5 Interprocessor COMMUNICATION 17 6 Audio Inp t and OUt sisne E A E EA EA E SN 17 T gt Interrupts A be cote o BSA ts lee eet ettet trees 18 8 TriMedia Configuration 20 9 Peripheral iie eee pene Decio e tute p De 20 G H I J K L M N RO O IV TOU Qa BS Oo FP V BE FastChannel Digital Input Output eee eese eese esee 20 WEIL M 22 PCLEPCE Bridge ei A A 22 ll c 23 CRED 23 UART and Serial Port teet etes seriei 23 luce 23 Cl ek Distrib tion oo tte eto erat ea eeu i kv 24 IQ32B Pins Ports and Signals a ede tren me eiie te le deer tee d eei etes 26 CONNECTORS AND JUMPERYS eerta eto
65. ins with return on the higher numbered pins J1A J1B J1A Signal J1B Signal J1A J1B J1A Signal J1B Signal Pins Pins 1 2 TAP1 LVAL TAP3 LVAL 35 36 STROBE 1 STROBE 3 3 4 TAP1 FVAL TAP3 FVAL 37 38 STROBE 2 STROBE 4 5 6 39 40 MASTER CK1 MASTER 7 8 GPIN1 GPIN3 41 42 MASTER CK2 MASTER CK4 9 GND GND 43 GND GND 10 11 TAP1 DO TAP3 DO 44 45 TAP2 D7 TAP4 D7 Analog RS170 Analog RS170 Input 1 Input 3 12 13 TAP1 D1 TAP3 D1 46 47 TAP2 D6 TAP4 D6 14 15 TAP1 D2 TAP3 D2 48 49 TAP2 D5 TAP4 D5 16 17 TAP1 D3 TAP3 D3 50 51 TAP2 D4 TAP4 D4 18 19 TAP1 D4 TAP3 D4 52 53 TAP2 D3 TAP4 D3 Analog Composite 4 S Video C2 20 21 TAP1 D5 TAP3 D5 54 55 TAP2 D2 4 D2 Analog Composite 3 S Video C1 22 23 TAP1 D6 TAP3 D6 56 57 TAP2 D1 4_ 1 Analog Composite 2 S Video Y2 24 25 TAP1 D7 TAP3 D7 58 59 TAP2 DO 4 DO Analog RS170 Analog Input 2 Composite 1 S Video Y1 26 GND GND 60 GND GND 27 28 EXT TRIG1 EXT TRIG2 61 62 GPIN2 GPIN4 29 30 GPIN5 GPIN6 63 64 TAP2_LVAL TAP4_LVAL 31 32 GPOUT1 GPOUT3 65 66 TAP2 FVAL TAP4 FVAL 33 34 GPOUT2 GPOUT4 67 68 TAP2 PXCK TAP4 PXCK Table 6 Analog and Digital Input Connector J1A J1B 29 3 Analog ChannelLink RS 232 Connector 42 Connector J2 is the 68 Pin connector on the Rear PCI Bracket It provides access to the SVGA and RBG TV ana
66. is register should be loaded before writing TDI These bits are shifted out synchronously with the TDI data written on a subsequent cycle Note that JTAG shift of TMS is non destructive shift register recirculates Thus back to back writes of TDI register cause the same 8 bit sequence of TMS data to be output This is useful to speed up long downloads when TMS remains at 0 for large numbers of bytes Control register 8 data bits Bits 0 and 1 select the destination device for JTAG transfers see Table 22 Bits 2 and 3 when set to 1 cause the FPGA1 and FPGA2 DONE lines to be driven low respectively When 0 the respective DONE line is tri stated Bit 4 selects the download mode when addressing either of the FPGA s bits 1 0 1x A 1 in this bit position selects serial download via the Xilinx style programming interface pins A 0 in this position selects download via the JTAG port Note that the JTAG port may also be used for boundary scan or for communication with user logic after download is complete Bits 5 and 6 when set to 1 cause the FPGA1 and FPGA2 INIT lines to be driven low respectively When set to 0 the respective INIT line is tri stated Bit 7 resets the device selected by bits 0 and 1 when written as 1 no action when written as 0 For the crosspoint switches this is accomplished via the TRST line For the FPGAs the PROGRAM line is pulsed allowing re load of configuration data Bits 1 0 Selected Device
67. ital synthesis is 3 3 nanoseconds This is reduced to less than 1 nanosecond in the TM1300 when the improved mode is used In TM1300 improved mode the frequency resolution is 0 3 Hz General Purpose Outputs Four general purpose static outputs GPOUTO 3 are provided to connector J1A J1B These RS422 differential outputs can be written out through the UART by the primary TriMedia via the bus D FPGA Based Front End Digital data inputs pass through two FPGAs each with an external SDRAM The FPGAs can perform multiplexing and re order incoming data for Odd Even and Left Right tapped cameras Data is divided into two 16 bit halves one to each FPGA When using three or four tap cameras half the bits from each tap are routed to each FPGA allowing the two parts to operate identically When using multiple smaller cameras each FPGA services a different camera or pair of cameras These FPGAs are in system reprogrammable allowing application specific operations to be performed Normal Tap1 0 3 FPGA1 Multitap i Frame TAP1 0 7 Normal Tap1 4 7 Buffer Multitap Tap3 0 3 Tap2 0 3 8 EPGA1 DOQ To Crosspoint TAP2 0 7 Normal Tap2 4 7 8 Multitap Tap4 0 3 FPGA1 DO1 Tap3 4 7 FPGA2 TAP3 0 7 Normal Tap3 0 3 Multitap Tap1 4 7 Frame Buffer Tap4 4 7 TAP4 0 7 8 FPGA2 Dog Normal Tap4 0 NEM Ti Multitap Tap2 4 7 Crosspoint FPGA2 DO3 Figure 6 Front End Components and Data Flow 1 FPGA R
68. l trigger inputs Two RS422 General purpose inputs Six RS422 Power No camera power provided G Analog Video Output e Continuous composite or S video NTSC PAL video output e Scaling and alpha blending for image examination and fusion e Built in S8 Virge GX2 SVGA with video capture and blending capability e 4 MB of video SGRAM for SVGA 57 800 MB s video memory bandwidth Composite output NTSC PAL S Video output NTSC PAL luma shared with composite H Monitor Output SVGA compatible output up to 1280x1024 at 72 Hz non interlaced e Non destructive overlay on the SVGA output Output type VGA standard analog RGB Resolution up to 1280 x 1024 non interlaced SVGA Frame rate up to 72 Hz Color depth up to 24 bits per pixel PCI Interface e 132 MB s peak local PCI bandwidth 33 MHz 32 bit primary PCI bus interface Transparent bridge to 33 MHz 32 bit local PCI bus e Full compliance with PCI bus revision 2 1 e Memory mapped host access to distributed SDRAM for bootstrap and program load Clock rate 33 MHz max Data width 32 bits Peak DMA rate 132 MB s Standards PCI Rev 2 1 compliance Mechanical Full length universal 5 0 3 3V card Power 12 at 100 mA max 5 at 8 amps 6 5 amps are drawn from a disk drive supply cable J PMC Interface e On board expansion slot for one sta
69. le processors One processor receives the first image and the other receives the second image Image distribution affects the buffering requirement in the front end Due to banking restrictions of the SDRAM multiple frames must be buffered when distributing images to multiple CPUs Two image buffers are required for each CPU used Thus when four TM1300s are needed to handle the input bandwidth requirements eight frames must be buffered This condition limits the frame size to 1 8 of the frame buffer or 2 megabytes 7 Data Valid Signals Four data valid signals are generated by the FPGAs one for each TriMedia Each signal is synchronous to the video input clock of the associated TriMedia Each signal connects to the VI DVALID pin of the TriMedia via the crosspoint to match the delay time of the data lines The data valid signals synchronize the data capture to the valid pixels from the camera in raw capture modes When using synchronous data buffering in the crosspoint the position of the data valid relative to the pixel data can be adjusted by varying the number of flip flop stages each goes through in the crosspoint input buffer Region of interest capture can be handled in the FPGA if logic cells and routing are available Another purpose of the data valid is to pad or truncate the frame to a multiple of 64 pixels This allows use of cameras with non binary height and width The 64 pixel limitation comes from the TriMedia which must define b
70. log outputs Channel Link and RS 232 Pin Signal Pin Signal 1 VGND 68 CL RXINSP 2 Green 67 CL RXIN3N 3 VGND 66 GND 4 HSYNC 65 GND 5 VGND 64 CL RXCLKINP 6 MON 100 63 CL RXCLKINN 7 MON ID2 62 GND 8 VGND 61 GND 9 NTSC OUT 60 CL RXIN2P 10 VGND 59 CL RXIN2N 11 RS232 TXD 58 GND 12 GND 57 GND 13 RS232 HSHKO 56 CL RXIN1P 14 GND 55 CL RXIN1N 15 CL TXOUTSP 54 GND 16 CL TXOUTSN 53 GND 17 GND 52 CL 18 GND 51 CL RXINON 19 CL TXCLKOUTP 50 GND 20 CL TXCLKOUTN 49 GND 21 GND 48 N C 22 GND 47 RS232 HSHKi 23 CL TXOUT2P 46 RS232 RXD 24 CL TXOUT2N 45 VGND 25 GND 44 CHROMA OUT 26 GND 43 VGND 27 CL TXOUTIP 42 DDC SCL 28 CL TXOUTIN 41 DDC SDA 29 GND 40 VGND 30 GND 39 VSYNC 31 CL TXOUTOP 38 VGND 32 CL TXOUTON 37 Blue 33 GND 36 VGND 34 GND 35 Red Table 7 Analog Output ChannelLink RS 232 Connector J2 4 FastChannel Digital Input Output J5 Digital output connectors J4 and J5 are 50 pin connectors on the top edge of the PCI Card Each connector sends and receives 16 bits of digital data and 12 bits of digital control All signals are differential consisting of a positive and a negative signal pair in the table they are combined e g differential signals DIG DO1P and DIG DO1N are shown as just DIG DO1 The positive signal is always the lower numbered pin in each pair the nega
71. ls provide the proper bitstream format for downloading configuration data to the FPGA The same format applies whether JTAG or Serial Slave mode configuration is used Unlike the bitstream files for the IQX crosspoint switch these files do not contain JTAG control information A description of the use of JTAG to configure Xilinx FPGA s is available as an application note XAPP017 Boundary Scan in XC4000 and XC5200 Series Devices JTAG Chains 1 JTAG Chain 1 Boundary Scan 21150 Bridge Chip and SAA7111A EVIP Header P11 for JTAG boundary scan chain testing is provided on the Fastlmage board The header connects the 21150 PCI Bridge and 7111A Enhanced Video Input Processor EVIP in a standard JTAG chain Since the bridge sits between the host bus and all other functions of the board it must be operational in order to run host based testing The 21150 have a standard JTAG port which may be used to run simple boundary scan tests while the bridge is not operating The 21150 JTAG port is first in the board test chain accessible from header P11 note that the PCI JTAG pins do not connect to the board test chain It is important to note that the host system plug and play BIOS will attempt to initialize the bridge chip at system startup It may be necessary to place the Fastlmage card in a passive back plane to allow JTAG testing of the primary bus 2 TriMedia JTAG Chain 2 TriMedia Processors A separate TriMedia JTAG chain with its own
72. ndard PMC module with back panel access to module e Second PMC expansion slot for additional CPUs Clock rate 33 MHz max Data width 32 bits Standards PCI Rev 2 1 PMC 3 3V Signalling compliance Mechanical Fits standard length single width module 10mm board stacking height Power 12V 5V supplied by PCI connector 3 3V can be supplied via an auxiliary connector on Fastlmage board 58 IX TROUBLESHOOTING There are several things you can try before you call Alacron Technical Support for help Make sure the computer is plugged in Make sure the power source is on Go back over the hardware installation to make sure you didn t miss a page or a section Go back over the software installation to make sure you have installed all necessary software Run the Installation User Test to verify correct installation of both hardware and software Run the user diagnostics test for your main board to make sure it s working properly Insert the Alacron CD ROM and check the various Release Notes to see if there is any information relevant to the problem you are experiencing The release notes are available in the directory usr alacron alinfo Compile and run the example programs found in the directory usr alacron src examples Find the appropriate section of the Programmer s Guide amp Reference or the Library User s Manual for the particular library and problem you are experiencing Go b
73. ne 603 891 2750 FAX 603 891 2745 Web site http www alacron com Electronic Mail sales alacron com support alacron com 62
74. nel Link Systems that have another video adapter in addition to the onboard S3 based SVGA can use the host s adapter and monitor to display video output in one or more possibly overlapping windows The TM1300 supports this functionality directly via the image coprocessor unit When using the onboard S3 SVGA processed image data can be scaled and alpha blended as well 2 FastChannel Digital Input Output The FastChannel interface provides 32 bits of digital input and output directly to and from the crosspoint via connectors J4 and J5 on the top edge of the board The interface includes 32 bits of RS422 or LVDS differential digital output drivers and receivers with RS422 digital video control and clock inputs outputs 3 Channel Link Input Output The Fastlmage1300 implements the 28 bit Channel Link digital I O interface as an option Compatible cameras or other input devices can be connected directly to the Channel Link inputs Channel Link outputs may be connected to another Fastlmage1300 for high speed inter board communication E PMC Daughter Cards Two PMC slots connect to the Fastlmage internal PCI bus via standard PMC connectors and to the crosspoint switch via the Alacron FastChannel connector Daughter cards from Alacron are available to extend the memory or processing power of a Fastlmage board via the PMC slots and FastChannel e Fast4 daughter card supplies one to four additional TriMedia processors FastlO daught
75. nk or in bar code form The version of the ALRT ALFAST or FASTLIB software that you are using You can find this information in a file in the directory usr alfast alinfo The type and version of the host operating system i e Windows 98 Note the types and numbers of all your software revisions daughter card libraries the application library and the compiler The piece of code that exhibits the problem if applicable If you email Alacron the piece of code our Technical Support team can try to reproduce the error It is necessary though for all the information listed above to be included so Technical Support can duplicate your hardware and system environment 60 B Returning Products for Repair or Replacements Our first concern is that you be pleased with your Alacron products If after trying everything you can do yourself and after contacting Alacron Technical Support you feel your hardware or software is not functioning properly you can return the product to Alacron for service or replacement Service or replacement may be covered by your warranty depending upon your warranty The first step is to call Alacron and request a Return Materials Authorization RMA number This is the number assigned both to your returning product and to all records of your communications with Technical Support When an Alacron technician receives your returned hardware or software he will match its RMA number to the on file information you
76. nt are used to determine which of the secondary clocks will be driven This reduces system noise when clocks are not needed The operation of this register is described in the 21150 data sheet in section10 2 The output mask is active low i e the clocks are enabled by a zero in the appropriate bit position s of the shifted data A pull down resistor on the printed circuit board will cause all clocks to go active if the release of PCI reset happens before the CPLD has been configured The CPLD can take as long as 50 milliseconds to configure The PCI specification only requires the reset line to remain low for 1 millisecond after power supplies are stable Note however that the CPLD will only load after power on and not after subsequent PCI resets e g from front panel reset switch or BIOS firmware while the bridge chip will re load the clock mask at each reset Typical PCI reset time from power good is 250 milliseconds E Low Speed Timing Functions The CPLD has two 9 bit counters for generating low speed timing signals These counters run at 10 KHz allowing timing from 100 microseconds to 50 milliseconds The two counters are triggered by a rising edge of the EXT TRIG1 and EXT TRIG2 signals respectively Alternatively they can be programmed to run free without an external trigger input Upon triggering each counter counts up from zero and stops when it reaches the maximum count 511 Each counter has two 9 bit compare registers COMP1 and CO
77. o the Host on the Host s interrupt line A and so forth The PMC slots have PCI device numbers 8 and 12 respectively The S3 has device number 2 the S3 interrupts the Host on HOST TM1 to TM4 have PCI device numbers 4 6 10 and 14 respectively TM1 PCI INTA HOST HOST INTA TM1 INTBi N C normally HOST TM1 INTC UART INT HOST INTC TM1_INTD TEST_LED1 HOST_INTD PCI INTA HOST INTC HOST INTA TM1_INTB HOST_INTA HOST_INTB TM1_INTC N C HOST_INTC TM1_INTD TEST_LED2 HOST_INTD TM3 TM2 3 4 IntB HOST INTC PRANIA PCI IntA SecPMC IntA TM1 INTB HOST INTA TM1 TM1_INTC N C TM1_INTD TEST_LED3 VGA IntA 1 PMC IntA PCI IntC TM4 P16 Normal Interrupts PCI INTA HOST INTC TM1 INTBE HOST INTA TM2 3 4 IntB 1 INTD amp TEST_LED4 TM1 IntB VGA PMC IntA PCI IntC P16 Local Interrupts Figure 14 Interrupts Normal interrupts are the default set by jumpers on P16 Alternatively P16 can be jumpered for local interrupts in this configuration the PMCs and the S3 interrupt 1 instead of the Host so that the TriMedia program can handle the interrupt 8 TriMedia Configuration EEPROM Each TriMedia has a small serial EEPROM which contains configuration data not shown in diagram Additional configuration data must be loaded by the system BIOS memory base addresses and by the run time software After a power on or PCI bus reset each TriMedia
78. ory 8 16 32 or 64 MB SDRAM per processor at 143 MHz 571 MB s peak access rate 143 MHz Instruction Cache 32K on chip cache per processor 8 way set associative 3928 MB s peak access rate Data Cache 16K on chip cache per processor 8 way set associative 1143 MB s peak access rate NTSC PAL Composite Video Capture Continuous image acquisition from one of four selectable composite NTSC PAL video streams via the SAA7111 EVIP Input levels 1V peak to peak nominal 0 3 to 1 2Vp p max Input impedance 75 Ohms Channel crosstalk 50 dB max Resolution 8 bits Bandwidth 6 MHz 1dB 36dB at conversion freq Conversion rate 12 8 to 14 3 MHz line locked Formats PAL BGHI PAL PAL M NTSC M NTSC N NTSC 4 43 supported NTSC Japan and SECAM Frame rates 50 Hz 625 line and 59 94 Hz 525 line nominal Horizontal line frequency Hz 15625 50 Hz or 15734 59 94 Hz 5 7 max Subcarrier frequency Hz 4433619 PAL BGHI 3579545 NTSC 3575612 PAL M 3582056 PAL N Subcarrier lock range 400 Hz Analog Video Capture Continuous simultaneous image acquisition of three analog video streams generated by line or area scan cameras Input levels 1V peak to peak nominal 2 0Vp p max 50mV minimum sync level when using composite sync Input impedance 75 Ohms 56 Resolution 8 bits x 3 channels Conversion
79. ovides independent frame sync signals for transmit and receive sections of the V 34 SSI The transmit frame sync runs continuously one sync for each 16 clocks The receive frame sync only runs when there is data to be transferred from the CPLD to the TriMedia The receive clock is also gated off when there is no data available Note that with continuous receive channel transmission a protocol such as that used for the transmit channel could be used but it would burden the DSP CPU with regular interrupts whether or not data was being transferred Data to and from the V 34 interface of the TriMedia is sent MSB first Data to and from the JTAG port is sent LSB first Data from the TriMedia to the CPLD is referred to as transmitted data Signals relating to transmitted data are TxFSX transmit frame sync and the 20 MHz free running clock Data from the CPLD to the TriMedia is referred to as received data Signals relating to received data are RxFSX RxDATA and RxCK Bit 15 MSB of the transmitted data is the change bit No action is taken if a word s change bit matches the change bit of the previous word This allows the TriMedia to let the transmitter under run since re transmitted words will have no effect Bits 14 through 8 14 through 9 for 9 bit registers are the internal register select bits Internal addresses are completely decoded Addresses are chosen with a mix of 1 s and 0 s to prevent unintended action when the TriMedia tr
80. rate 0 to 80 MHz Formats supported Line scan and area scan up to 4K pixels per line Clock sources Line locked with composite sync or external RS 422 D Digital Video Capture e Continuous simultaneous image acquisition from up to four digital video streams generated by line or area scan cameras e 16 MB frame buffer for versatile multitap camera capture e 320 MB s continuous digital capture bandwidth Common mode input range 0 to 5V 0 to 2 4 with LVDS option Input sensitivity 250 mV differential 100 mV with LVDS option Input hysteresis 50 mV typ Maximum clock 80 MHz 38 MHz for ITU R BT656 rate Maximum input 32 bits data width Formats ITU R BT 656 4 2 2 interlaced color 8 10 bit monochrome supported variable scan line scan 8 10 bit raw data 8 10 bit RGB E Digital Video Output Output levels RS 422 Maximum clock rate 80 MHz width Maximum output data 32 bits Formats supported ITU R BT 656 4 2 2 interlaced color 8 bit raw data F Camera Control Serial port Asynchronous RS232 600 to 19 200 Baud Frame line start outputs Two RS422 Exposure control outputs Two RS422 Master clock outputs Four RS422 programmable in 07 Hz steps up to 40 MHz General purpose outputs Four RS422 Pixel clock inputs Two RS422 Line frame valid inputs Four RS422 Externa
81. ration the crosspoint switch is used as a static interconnect for most applications The JTAG bit stream data can be generated by tools available from Xilinx The main crosspoint switch is the connection among the sources and destinations Sources are defined as inputs to the crosspoint e Four 8 bit input paths from the FPGAs to the crosspoint Four 8 bit paths from the Video Output of each TriMedia to the crosspoint e Four 8 bit paths from the FastChannel digital inputs to the crosspoint e Three or four 8 bit paths from the FastlO input ports to the crosspoint when a FastlO is connected Port A can be set as either input or output Ports B C and D are always inputs to the crosspoint Two 8 bit paths from the FastMem input ports and D to the crosspoint when a FastMem is connected e Up to four 8 bit paths from the Fast4 input ports to the crosspoint when Fast4 is connected Destinations are defined as outputs from the crosspoint e Four 8 bit paths from the crosspoint to the Video Input of each TriMedia e One 16 bit path from the crosspoint to the S3 GX2 for VDA and TV analog outputs e Four 8 bit paths from the crosspoint to the FastChannel digital outputs One 8 bit path from the crosspoint to the FastlO output port when a FastlO is connected Port A must be set as output from the Fastlmage1300 to the FastlO e Two 8 bit paths from the crosspoint to the FastMem output ports A and B when a FastMem is connected
82. ree running mode the period is COMP2 2 100 microseconds Thus if COMP2 contained 40 decimal the period would be 4200 microseconds The Cmp1 and Cmp2 pulse widths are as computed above for external trigger mode A COMP242 100uSec M Cmp1 100 uSec gt fat Cmp1Pls Pow A 100 B Cmp2Pls s Figure 22 Low Speed Timing Signals Free Running Mode The intent of the timing signals is to create readout and exposure control signals to line scan or area scan cameras e g EXSYNC and PRIN to Dalsa cameras Four RS 422 drivers are designated for these signals Counter1 Cmp1 and Cmp2 run to STROBE1 and STROBE2 respectively Counter2 Cmp1 and Cmp2 run to STROBES and STROBEA respectively F CPLD Programming Requirements The CPLD has fixed program which is downloaded from a serial EPROM each time the System is powered on It contains registers to set pulse timing and delay parameters It also provides the interface to the JTAG port of the crosspoint switch and FPGAs and to the serial download interface of the FPGAs Register definitions for this part are as follows 47 1 2 20 35 Address Hex Description TDI register 8 data bits Writing this register causes the JTAG state machine to shift out 8 bits of TDI and TMS data LSB first TDI data is supplied with this write TMS data must be written to the TMS register first TMS register 8 data bits Th
83. rocessed directly by the TriMedia The EVIP provides Frame Valid and Odd Even field signals NTSC PAL YUV Data or S Video Frame Valid Odd Even Field Figure 9 NTSC PAL S Video Input Signals 5 Data Reordering Data from Multitap cameras is re ordered using the SDRAM Incoming data is formed into groups of two 32 bit words inside each FPGA and written to the SDRAM location corresponding to its desired position in the output image When a complete image has been buffered in the SDRAM it is read out to the TM1300s while the next image is buffered in the other half of the SDRAM Four pairs of words are read then four pairs written to reduce the buffering requirements of the FPGA while keeping the SDRAM running near its optimal burst rate Depending on the Fastlmage1300 inputs the application may require a reordering of the data coming in to the Front End from Taps 1 2 3 and or 4 and exiting the Front End as data bytes FPGA1 DO 0 7 FPGA1 DO 8 15 FPGA2 DO 0 7 FPGA2 DO 8 15 The mapping of input taps to FPGA data bytes is diagrammed in area A of the Fastlmage1300 crosspoint Figure 14 Each tap can connect to one or more of FPGA1 DO 0 7 through FPGA2 DO 8 15 Multiple input taps can be multiplexed to one FPGA DO data byte Unused taps can be left unconnected 6 Image Distribution When the incoming data exceeds the input bandwidth of a single TriMedia processor 80 to 320 MB s the images are distributed among multip
84. s DO through D28 are shared with the Channel Link interface Pin J1 Signal J3 Signal Pin J1 Signal J3 Signal 1 PMC1 DO APMC DO 33 PMC1 D26 APMC D26 2 PMC1 D1 APMC D1 34 PMC1 D27 APMC D27 3 PMC1 D2 APMC D2 35 GND GND 4 PMC1 D3 D3 36 PMC1 D28 APMC D28 5 GND GND 37 PMC1 D29 APMC D29 6 PMC1 D4 APMC D4 39 PMC1 D30 APMC D30 7 PMC1 D5 APMC D5 39 PMC1 031 APMC D31 8 PMC1 D6 APMC D6 40 GND GND 9 PMC1 D7 APMC D7 41 PMC1 FVAL1 APMC FVAL1 10 GND GND 42 PMC1 FVAL2 APMC FVAL2 31 11 PMC1 D8 APMC D8 43 PMC1 FVAL3 APMC FVAL3 12 PMC1 D9 APMC D9 44 PMC1 FVAL4 FVAL4 13 PMC1 D10 D10 45 43V PMC1 43V APMC 14 PMC1 D11 011 46 PMC1 LVAL1 APMC LVAL1 15 43V PMC1 3V_APMC 47 PMC1_LVAL2 APMC_LVAL2 16 PMC1 D12 APMC D12 48 PMC1 LVAL3 LVALS3 17 PMC1 D13 D13 49 PMC1 LVAL4 APMC LVAL4 18 PMC1 D14 014 50 GND GND 19 PMC1_D15 APMC_D15 51 DO PXCK1 APMC PXCK1 20 GND GND 52 DO PXCK2 APMC PXCK2 21 PMC1 D16 D16 53 DO PXCK3 _ 22 PMC1 D17 017 54 DO PXCK4 _ 4 23 PMC1 D18 018 55 GND GND 24 PMC1 D19 019 56 SCL APMC1 SCL 25 GND GND 57 PMC1 SDA APMC1 SDA 26 PMC1 D20 D20 58 PMC2 SCL APMC2 SCL 27 021 021 59 PMC2 SDA APMC2 SDA 28 PMC1 D22
85. s Note for 9 bit data the address is shortened thus the LSB of the address 58 vs 59 is really the MSB of the data ST1C2 Slow timer 1 compare register 2 9 data bits Indicates delay to compare pulse 2 in units of 100 microseconds ST2C1 Slow timer 2 compare register 1 9 data bits Indicates delay to compare pulse 1 in units of 100 microseconds ST2C1 Slow timer 2 compare register 2 9 data bits Indicates delay to compare pulse 2 in units of 100 microseconds Slow Timer Control register Bit 0 enables free running mode for slow timer 1 Bit 1 enables free running mode for slow timer 2 50 VI UART SPECIFICATION A Purpose The Fastlmage board needs a simple asynchronous RS 232 port to set up certain intelligent cameras The TriMedia has no simple asynchronous serial communication port It also has no general purpose parallel data bus other than PCI the TM1100 s 8 bit bus shares pins with the PCI interface making it unusable in hosted systems This leaves one with the option of designing a PCI bus interface to add a standard UART chip or designing a UART which attaches to or one of the other complex interfaces such as audio or video I O ports or the V 34 serial interface port The PIC16C63 micro controller with its built in slave interface and USART was an ideal choice to implement the latter approach B Features slave Universal Asynchronous Receiver Transmitter Standard Baud rates
86. s See the program listing for a description of this register This is the UART Control Register accessed at subaddress 00 however writing to this location will not cause the hardware to be updated using the new values Reading this location is useful to verify current operating parameters since reading at subaddress 00 returns the status register instead of reading back the value written This indicates the time since reset in units of 26 67 milliseconds It holds at maximum count after approximately 6 8 seconds It is a legacy of earlier code versions which included power reset sequencing for the four TriMedia CPUs This is the baud rate divider register Read it to check current operating value Write it to set a non standard baud rate Actual baud rate is calculated by the formula 153 600 SPBRG 1 Many other useful and or destructive operations are possible Refer to the PIC16C6x data sheet for more information 55 VIII B C Processors SPECIFICATIONS Full computational power of one to four TriMedia TM1300 VLIW media processors 3GOPS applied to the video streams 32 or 64 MB of distributed SDRAM 8 16 or 32 MB per processor 2 3 GB s 4 x 571 MB s local memory bandwidth Memory mapped host access to distributed SDRAM for bootstrap and program load All on board and host PCI resources can be directly addressed by each processor Clock rate 143 to 180 MHz 200 MHz processors when available Mem
87. t addressing The PCF8575 is accessed at 0x40 for writing and 0x41 for reading The SAA7111A is accessed at 0x48 for writing and 0x49 for reading its internal registers are described in the data sheet section 17 The MAX521 is accessed at 0x50 for writing and 0x51 for reading The UART is accessed at 0x54 for writing and 0x55 for reading The bus is discussed further in Programming Configuration and Test below FastChannel Digital Input Output The bi directional Fast Channel I O interface provides 32 bits of differential RS422 or LVDS compatible I O Signal direction is programmable in groups of 4 bits In addition to the 32 data signals 8 control signals and 4 clocks are grouped into four sets of two control signals plus one clock The direction of each of these control signal groups is linked to the direction of the low nibble of each byte as shown in the block diagram below FastChannel I O RS 422 or LVDS FastChannel FastChannel FastChannel FastChannel FastChannel Control 0 1 and FastChannel FastChannel Control 2 3 and FastChannel FastChannel Control 4 5 and FastChannel FastChannel Control 6 7 and FastChannel Data Bits 0 3 Clock 1 Data Bits 4 7 Data Bits 8 11 Clock 2 Data Bits 12 15 Data Bits 16 19 Data Bits 20 23 Data Bits 24 27 Clock 4 Data Bits 28 31 4 4 A A 4 A A 4 A 5 i i LNY ry v E oe A A
88. t layout of this register was intentionally designed to allow software to program the Crosspoint FPGAs in an identical manner to the Front End FPGAs Bit 0 Selected Device 0 Crosspoint FPGA 1 U79 1 Crosspoint FPGA 2 U84 Table 24 Crosspoint Control Register Bit 0 General purpose output register Bit 1 when set to 1 turns on the Digital Output LED This bit no longer controls Digital Output RS 422 devices The Fastlmage 1300 has a new I2C part to enable or disable Digital I O on nibble by nibble basis Bit 0 when set to 1 turns on the test LED 11 This can be used as a simple way to debug V 34 communications Bits 2 through 7 are not used in the Fastlmage They are however used in the FastFrame and remain reserved for that reason BT261 control register and capture bit The Fastlmage has no Bt261 parts but bits O through 6 of this register are reserved Bit 7 is the CAPTURE bit The state of this bit is propagated to both front end FPGAs and is intended to start or stop image capture although its actual use depends on the FPGA program Read crosspoint status Data bits are ignored Writing this location causes the crosspoint status to be sent to the received data port Bits 15 through 12 of the received data are 1100 binary to indicate Crosspoint status read Bits 11 through 7 currently read all 0 however these bits may change in the future for revision control Bits 6 and 5 indicate the current state o
89. ter two converters in S video mode The primary TM1300 controls the input selection using the bus to access the internal registers of the SAA7111A Three additional RS 170 level video inputs can be used to capture images from three additional monochrome cameras or one RGB camera Sync detection circuitry for these inputs is very flexible allowing the use of asynchronous reset cameras as well as interlaced or progressive area scan cameras and line scan cameras 2 Digital Input Digital video input lines allow direct connection of digital line scan or area scan cameras of up to 32 bits The 32 Digital data inputs are received by high speed RS422 differential receivers whose outputs are run through the FPGA based front end to standard I O s on the crosspoint switch The switch can then route these to the data inputs of the TM1300 processors or the digital video input port of the S3 Virge GX2 All digital video data and control signals are differential RS 422 level signals with proper termination for twisted pair cable High speed line drivers and receivers are used on all digital signals however the RS 422 standard was not designed for very high data rates Thus the interface circuitry may limit the maximum practical data rate to considerably less than the 80 MHz video input bandwidth of the TriMedia chips unless the receivers are upgraded to the LVDS model Industry standard pin out devices are used for RS422 receivers and drivers 26LS
90. th the daughter card only when digital input from the Channel Link interface is installed K CPLD A Complex Programmable Logic Device CPLD provides some camera control and board interface logic The primary TriMedia processor communicates with this device via its V 34 synchronous serial interface The CPLD provides logic to convert the V 34 serial data to a JTAG stream for programming the main and clock crosspoint switches and to a Xilinx standard serial stream for programming the FPGAs This device also provides variable time delays for camera and strobe control The CPLD is downloaded from a serial EPROM each time the system is started See Programming Configuration and Test and the CPLD Specification later in this manual for details L UARTand Serial Port A simple RS 232 UART is provided for camera setup and low speed control It supports baud rates from 600 to 19 200 Although a host serial port could be used for this having the UART on board can simplify deliverable software The primary TriMedia processor communicates with the UART the Inter Integrated Circuit 2 wire serial bus The UART provides transmit and receive data as well as one handshake input and one handshake output The handshake lines are under program control They typically tie to Data Terminal Ready and Data Set Ready lines of the remote equipment The UART is accessed at address 0x54 for writing and 0x55 for reading In addition to serial
91. the TMS byte can stay at the same value over a large number of cycles The CPLD allows successive data words to be written to the TDI byte when the TMS byte is unchanged i e the CPLD re transmits the previous TMS data This effectively doubles the throughput for long downloads The maximum clock rate of the V 34 SSI is 20 MHz Since 16 bits are transmitted to write 8 bits of data the effective JTAG download rate is only 10 MHz when writing successive TDI bytes and 5 MHz when writing a TMS byte for each TDI byte The JTAG clock generated by the CPLD is always 10 MHz but stops between bytes when no new TDI data is available see Figure 20 During JTAG operations the TDO signal from the selected device is shifted into the CPLD and the data returned to the TriMedia via the V 34 receiver interface again with 8 data bits per 16 bit frame This data can be used to verify JTAG operation or to upload the current state of the device C External Five Wire Interface Five lines from a test header allow access to the JTAG ports of the crosspoint switches and FPGA from an external system for debugging or test These lines are defined as EXT EXT TDI EXT TMS EXT TRST and EXT ENABLE All lines are internally pulled up While EXT ENABLE is high inactive EXT EXT TRST EXT TMS and EXT TDI are ignored 45 When is brought low active the external interface is allowed to drive the JTAG lines and th
92. tive signal is the higher numbered pin Pins J4 Signal J5 Signal Pins J4 Signal J5 Signal 1 2 DIG DOO DIG DO16 27 28 DIG DO12 DIG DO28 3 4 DIG DO1 DIG DO17 29 30 DIG DO13 DIG DO29 5 6 DIG DO2 DIG DO18 31 32 DIG DO14 DIG 0030 7 8 DIG DOS DIG DO19 33 34 DIG DO15 DIG 9 10 DIG DO4 DIG DO20 35 36 GND GND 11 12 DIG DO5 DIG DO21 37 38 DIG COO DIG CO4 13 14 DIG DO6 DIG DO22 39 40 DIG DIG CO5 15 16 DIG DO7 DIG DO23 41 42 DIG CO2 DIG CO6 17 18 GND GND 48 44 DIG CO3 DIG CO7 19 20 DIG 008 DIG DO24 45 46 DO PXCK1 DO 21 22 DIG DO9 DIG DO26 47 48 DO PXCK2 DO PXCK4 23 24 0010 DIG DO26 49 50 GND GND 25 26 DIG DO11 DIG DO27 Table 8 FastChannel Digital Input Output Connectors J4 and J5 5 Slots J1 93 The Fastlmage1300 Board has the following Connections on the rear of the PCI Card Table 9 shows the pinout a PMC1 J1 Standard Pn1 Pn2 Pn4 installed Pn3 not installed Pn1 8 Pn2 function as standard PCI Pn4 has 32 bits of Digital input output 8 bits of control 4 clocks and I2C The PMC slot requires an Alacron PMC adapter for PMC boards with to extend the board to the next adjacent PCI slot b 43 Alacron PMC Pn1 Pn2 Pn4 installed Pn3 not installed Pn1 amp Pn2 function as standard PCI Pn4 has 32 bits of Digital Input output 8 bits of control 4 clocks and 12 Data signal
93. to clocks originating on the Fastlmage In addition DO PIXCKT 1 4 is connected on the Fastlmage board to the FastChannel I O the Master Clock output and the main crosspoint switch DO PIXCK1 connects to the Channel Link interface S3 LCLK S3 LCLK is the Local Peripheral Bus LPB clock to the 53 GX2 VGA chip 27 CONNECTORS AND JUMPERS A Connectors 1 Rear Bracket Connectors Digital Analog Input Connectors J1A J1B and NTSC RS232 VGA Channel Link I O Connector J2 are accessible from the PCI rear panel bracket Analog Digital Inputs JA J1B IOGHA 9 89 Channel Link Input Output 5 e RGB Monitor Output 9 TV Monitor Output nep MEE dE a 5 RS 232 lt 0 775 Standard PCI Bracket Figure 18 Fastlmage1300 Front Panel Bracket 28 2 Analog and Digital Input Connector J1A J1B The Analog and Digital Input connector is on the Rear PCI Bracket JA1 J1B is a Dual 68 Pin Connector with 32 bit Digital Inputs and Control or Analog Inputs Table 6 Digital signals are differential consisting of a positive and a negative signal pair in the table they are combined e g differential signals TAP1 LVALP and TAP1 LVALN are shown as just LVAL The positive signal is always the lower numbered pin each pair the negative signal is the higher numbered pin Analog signals connect to the lower numbered p
94. uffers in 64 byte increments Providing dummy garbage pixels at the end of the frame to fill out the buffer greatly simplifies programming in TriMedia raw capture modes Padding is accomplished with a 6 bit modulo 64 counter which runs only when data valid is active If the contents of the counter are not zero when the next frame sync arrives data valid is asserted until the counter rolls over to zero Note that this requires the frame synch signal to precede the first valid pixel by up to 63 clock cycles depending on the number of pixels in a frame This is not necessary for cameras with a multiple of 64 pixels per frame most line scan cameras and square format area scan cameras since the counter will be at zero after the last pixel of the frame E Digital Crosspoint Switch Two Xilinx Virtex XCV50 FPGAs form a switch matrix with flexible buffers at each port These parts also contain distributed RAM for buffering data as required Multiplexers can match the input data bus width to the TriMedia processors Demultiplexers can match TriMedia video output to the digital output bus In addition to the main data switch matrix a smaller switch I Cube IQ32B is used for flexible routing of clock signals with low latency and skew Configuration of the crosspoint switch matrix is SRAM based allowing reconfiguration in system Configuration data is downloaded to the part via a standard JTAG port Because of the relatively slow rate of configu
95. un States The input FPGAs control the operation This section is a general description of the FPGA s capabilities not specific to any application The FPGA has two states stopped and running When the FPGA is stopped no data flows in from any source When the FPGA is running data flows in from the selected source The data units can be one of three sizes pixels lines and frames A Transfer Counter TC internal to the FPGA counts the data units as specified in the program When the FPGA is stopped the TC is empty To change from stopped to running the program loads a number into the TC Two running modes are Fixed and Continuous e n fixed running mode the Transfer Counter receives a number of units and counts down as each pixel line or frame is clocked in When the TC counts down to zero the FPGA changes back to the stopped state e In continuous running mode the TC receives a maximum initial value which is also stored in a shadow register Each time the TC counts down to zero it is automatically reloaded from the shadow register and running continues In both fixed and continuous modes an end of word end of line or end of frame indication is available to the FPGA 2 Input Signals from Line Cameras to FPGA For digital line cameras the Data Line Valid and CLK input signals come directly from the digital input drivers For analog line cameras the input data and controls go through the A D converters to be converted to
96. urces to destinations is diagrammed in area B of the crosspoint Figure 10 above The sources are the four TriMedia outputs the destinations include the four TriMedia inputs and the four FastChannel ports A B C and D Any source can connect to one or more destinations No two sources can be connected to the same destination F Processors and Memory The processors and memory subsystem is diagrammed in Figure 11 Crosspoint Switch Internal PCI Bus Figure 11 Processors and Memory 1 TriMedia Processors One to four TriMedia TM1300 processors may be installed on the Fastlmage card Processor is always installed processors TM2 and TM4 are optional The TriMedia has built in PCI bus interfaces and glueless interface to 8 16 32 or 64 MB of local Synchronous Dynamic Random Access Memory SDRAM for program and data The heart of the TriMedia is a VLIW digital signal processor which can issue up to five instructions in a single clock cycle for up to 900 peak MIPS Special DSP instructions allow simultaneous operation on four 8 bit or two 16 bit operands in a single instruction This pushes the peak rate to over 3 3 billion operations per second for 8 bit data The TriMedia can issue up to four floating point operations per clock cycle for a peak rate of 720 MFLOPS The TriMedia does not have floating point multiply accumulate instructions but it can issue up to two floating point adds and two floating point multiplies
97. ut Three 8 bit A D converters are available for three channels of RS170 compatible monochrome video or one RGB video source in parallel with the EVIP Each channel has associated sync detection and pixel clock generation to allow simultaneous acquisition from three independent non genlocked sources Sync and pixel clocks may also be driven from an external RS 422 source Independent offset and gain controls are available for each of the three channels Maximum conversion rate pixel clock is 80 Mpixels s Pins Signal J1A 10 J1A 11 TAP1 D0 J1A 58 J1A 59 TAP2 D0 GND J1B 10 J1B 11 TAP3 DO GND Table 2 8 Bit Analog Input Channels Output from the A D converters can be further processed in the FPGA based front end Multitap operation is described later in the section on the Front End Digital Input Video capture signals come in through a dual 68 pin VHDCI connector J1A J1B To save pins analog and digital signals share pins allowing only one or the other for each of the four input taps Digital video input lines allow direct connection of digital line scan or area scan cameras of up to 32 bits All digital video data and control signals are differential RS 422 level signals with proper termination for twisted pair cable High speed line drivers and receivers are used on all digital signals Industry standard pin out devices are used for all RS422 receivers and drivers to allow upgrade to faster parts as

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