XEM3010 User`s Manual
Contents
1. Reconfiguration Using S1 When a jumper is installed across J2 S1 is electrically connected to the PROG B pin on the FPGA In this configuration 51 may be used to force the FPGA to reprogram itself using the im age in PROM Note that this mode is only available when the XEM3010 is configured for PROM configuration of the FPGA When the XEM3010 is configured for USB configuration no jumper should be installed across J2 PLL Connections The PLL contains six output pins one of which is left unconnected The other five are labelled SYS CLK1 through SYS CLK5 SYS CLKA connects to JP2 and SYS CLK5 connects to The other three pins are connected directly to the FPGA The pin mapping table at the end of this document details the PLL connections SDRAM Clock The SDRAM clock U14 F2 is connected to 5 5 CLK1 which is on the Cypress CY22393 PLL 08 10 Note that this connection is shared with FPGA GCLK3 U11 N9 www opalkelly com 13 XEM3010 User s Manual JTAG JP1 JTAG Connector JP1 is the 2mm 6 pin JTAG connector on board and connects to the on board JTAG chain which includes the FPGA configuration PROM and expansion connector These pins can be con nected to an external JTAG command converter such as the Xilinx JTAG cables for additional programming capability The JP1 pins are connected as shown below PPn Signa s mo JTAG Connection Chain The JTAG chain is configured as shown in the2. Select Rev 0 and to erase any existing configuration e PROM is Configuration Master Internal Clock e Clock Frequency set to 40 MHz e Configuration is Serial Mode www opalkelly com 21 XEM3010 User s Manual Adyanced PROM Programming Options Design Revision and Customer Code Select Design Revision and Enter Customer Code Max 64 Hex Digits Design Read Write Erase Verify Free Running Customer Revision Protect Protect Clock Code we FRC ml Dae oes ove rii AP we F vn Biss bey Default Revision 0 During Configuration _1 0 Configuration C PROM is Slave clocked externally Serial Mode Y PROM is Configuration Master select clock source Usercode C External Clock Enter 8 Hex Digits Usercode Internal Clock EE Clock Frequency 40 MHz M Load FPGA Heb Once you acknowledge this dialog the programming operation will start Once complete the PROM should be setup with your new FPGA programming file Booting from PROM In order to boot the XEM3010 from PROM you must remove the jumper on J1 This allows the PROM to configure the FPGA from power on If your FPGA design has MUXSEL 0 the design will still be able to communicate with FrontPanel if it is connected to a PC 22 www opalkelly com
3. MHz signal output from the USB microcontroller The PLL can output clocks up to 150 MHz and is config ured through the FrontPanel software interface or the FrontPanel API Xilinx Configuration PROM An 8 Mbit Xilinx PROM is included on some variants of the XEM3010 This PROM allows the XEM3010 to operate without its USB tether by automatically configuring the on board FPGA during power up This PROM may be programmed over the board s JTAG port using a Xilinx configuration cable and the iMPACT software 32 MByte Word Wide Synchronous DRAM The XEM also includes a 32 MByte SDRAM with a full 16 bit word wide interface to the FPGA This SDRAM is attached exclusively to the FPGA and does not share any pins with the expan sion connector The maximum clock rate of the SDRAM is 133 MHz The SDRAM is a Micron MT48LC16M16A2BG 75 D or compatible LEDs and Pushbuttons Eight LEDs and two pushbuttons are available for general use as debug inputs and outputs Expansion Connectors Two high density 80 pin expansion connectors are available on the bottom side of the XEM3010 PCB These expansion connectors provide user access to several power rails on the XEM3010 two clock generator outputs four FPGA clock inputs the USB microcontroller I2C lines the JTAG chain and 116 non shared I O pins the FPGA The connectors on the XEM3010 are Samtec part number BSE 040 01 F D A The table below lists the appropriate Samtec mating conne
4. USB specification However to support users who may not be consuming that much power in their design and who may still wish to use the XEM3010 in a bus powered situation we have provided a solder jumper 03 on the bottom of the XEM3010 Wlth a bead of solder in place across this jumper the USB 5V is connected to VDC Before relying on USB power you should be aware of the limitations and the fact that using USB power may render the XEM3010 a USB noncompliant device Supply Heat Dissipation IMPORTANT Due to the limited area available on the small form factor of the XEM3010 and the density of logic provided heat dissipation may be a concern This depends entirely on the end application and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM3010 Of primary focus should be the FPGA U11 the two switching power supplies U1 U2 and the SDRAM U14 Although the two switching supplies are high efficiency they are very compact and consume a small amount of PCB area for the current they can provide If you plan to put the XEM3010 in an enclosure be sure to consider heat dissipation in your de sign USB 2 0 Interface The XEM3010 uses a Cypress CY7C68013A FX2LP USB microcontroller to make the XEM USB 2 0 peripheral As a USB peripheral the XEM is instantly recognized as a plug and play peripheral on millions of PCs More importantly FPGA downloads to the XEM happen blazingly
5. an input and synchronizes its logic fabric to it typically using a DCM Source Synchronous In this mode the clock signal is sourced by the FPGA rather than the PLL To avoid signal con tention the corresponding output 5 5 CLK1 the PLL must be disabled or increased power consumption and potential damage may be done The FPGA pin 9 is configured as an output and provides the clock signal to the SDRAM Typi cally this setup uses the DDR features of the IOB to provide a clock that is well synchronized with the signals output to and input from the SDRAM thus minimizing signal skew with respect to the clock www opalkelly com 15 XEM3010 User s Manual Expansion Connectors 16 JP2 JP3 JP2 is an 80 pin high density connector providing access to FPGA Banks 2 and 3 Pins 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin 11 on this connector is SYSCLKA and is directly connected to CLKD on the Cypress CY22393 PLL Using FrontPanel s PLL Configuration Dialog you can configure the clock signal present on this pin Pin mappings for JP2 are listed at the end of this document in the Quick Reference section For each JP2 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair Os on the FPGA the FPGA signa
6. connected to JP1 JP2 on the BRK3010 according to the table below A similar mapping exists for JP3 on the XEM3010 ooo o e www opalkelly com XEM3010 User s Manual Xilinx Configuration PROM Some versions of the XEM3010 are built with a Xilinx configuration PROM inserted This PROM allows the FPGA to be configured upon power up without a USB connection as some applica tions may require the FPGA to control a user s device and only occasionally be connected to a PC The USB connection may therefore be used for extracting acquired data adjusting param eters and so on Getting the XEM3010 to boot from a PROM based FPGA configuration is a multistep process consisting of the following steps 1 Generate an FPGA programming file 2 Generate a PROM programming file from the FPGA programming file 3 Program the PROM Generate an FPGA Programming File This step is performed for either PROM boot or USB boot and is the final step in a typical FPGA synthesis flow It is assumed that the user is already familiar with this procedure and it will not be covered here Generate a PROM Programming File In this step the Xilinx iMPACT tool is used to format a PROM programming file with the FPGA programming file created previously In the next step the PROM programming file will be trans ferred e g via JTAG to the PROM Start IMPACT Once the FPGA programming file bitfile has been created you can start iMPACT from within Project Navi
7. fast virtual instruments under FrontPanel update quickly and data transfers are much faster than the parallel port interfaces common on many FPGA experimentation boards www opalkelly com 7 XEM3010 User s Manual On board Peripherals The XEM3010 is designed to compactly support a large number of applications with a small num ber of on board peripherals These peripherals are listed below Serial EEPROM A small serial EEPROM is attached to the USB microcontroller on the XEM3010 but not directly available to the FPGA The EEPROM is used to store boot code for the microcontroller as well as PLL configuration data and a device identifier string The PLL configuration data is loaded from EEPROM and used to reconfigure the PLL each time a new configuration file is loaded to the FPGA Therefore stable and active clocks will be pres ent on the FPGA pins as soon as it comes out of configuration The stored PLL configuration may be changed at any time using FrontPanel s PLL Configuration Dialog The EEPROM also stores a device identifier string which may be changed at any time using FrontPanel The string serves only a cosmetic purpose and is used when multiple XEM devices are attached to the same computer so you may select the proper active device Cypress CY22393 PLL A multi output triple PLL clock generator can provide up to five clocks three to the FPGA and another two to the expansion connectors JP2 and JP3 The PLL is driven by a 48
8. much of this power will be available to expansion devices using the expansion connectors DC Power Connector The DC power connector on the XEM3010 is part number PJ 102A from CUI Inc It has a stan dard 2 1mm 5 5mm power jack The outer ring is attached to DGND The center pin is attached 6 www opalkelly com XEM3010 User s Manual to VDC on expansion connector JP3 as well as the inputs to the two switching regulators on the XEM3010 Expansion Bus Power The expansion bus has pins for VDC 3 3V and 1 2V making it flexible for nearly any supply scenario In particular the following scenarios have been considered e VDC is provided to an expansion device which use or regulate it as necessary e VDC is provided by an expansion device to power the XEM3010 e 3 3V and or 1 2V are provided to expansion devices as regulated reliable supplies e 8 3V and or 1 2V are provided by an expansion device to power the XEM3010 In this case the switching regulators on the board must be removed This option may be useful to applications where a switching supply is not desired USB Bus Power The USB 2 0 specification allows for up to 2 5 W 500mA at 5v to be provided to external periph erals over the USB cable While power consumption of an unconfigured XEM3010 is quite low due to the flexibility allowed in FPGA design the Spartan 3 and SDRAM could easily consume over 2 5 W during operation with a user design thus violating the
9. 20051001 20060215 20060225 20060511 Added SDRAM to FPGA pin connections 20070221 20070226 20070519 20070604 20070613 Removed overline from SDRAM pin names LDQM UDQM 20070919 Made mandatory deassertion of MUXSEL clearer 20071127 Fixed typo Pushbuttons are pulled high to 2 5v Introducing the XEM SONG 5 PCB FOON dic a pd 5 BRK3010 Breakout Board 5 Functional Block 6 POWER SUDO dues sepu UR Rg 6 DG Power Connector eom aeter ITA RR T PERPE 6 Expansion Bus Power 7 USB Bus POWOI Te Uh ead HP We Supply Heat Dissipation 7 USB Tlenface eoim mah T On board 8 Serial EEPROM 99 ied eb ee 8 Cypress C 22393 derat Ro 8 Xilinx Configuration 8 32 MByte Word Wide Synchronous DRAM 8 LEDS and PustibUltloriss ironia aad 8 Expansion Connectors 8 FrontPanel SuppoOotLb 42241 ec PORE ee 9 Programmer s Interface 9 Applying the XEM3010 11 Host Interface acoso RR ERI 11 12 lC CO
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11. 7 Opal Kelly XEMS3010 User s Manual A compact 75mm x 50mm integration board featuring the Xilinx Spartan 3 FPGA and on board SDRAM The XEM3010 is a compact USB based FPGA integration board featuring the Xilinx Spartan 3 FPGA 32 MB 16 bit wide SDRAM high efficiency switching power supply Xilinx configuration PROM and two high density 0 8 mm expansion connectors The USB 2 0 interface provides fast configuration down loads and FPGA PC communication as well as easy access with our popular FrontPanel software and developer s API An on board clock generation device has three independent PLLs and five flexible outputs available to the FPGA SDRAM and expansion connectors Software documentation samples and related materials are Copyright 2006 2009 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History
12. BIS E ERSA Each of the samples installed with FrontPanel includes a copy of a template constraints file that lists all the XEM3010 pins and maps them to the appropriate FPGA pins using LOC location constraints You can use this template to quickly get the pin locations correct on a new design MUXSEL MUXSEL is a signal on the XEM3010 which selects the signal path to the FPGA programming signals and CCLK When low deasserted the FPGA and USB microcontroller are connect ed When high asserted the FPGA and PROM are connected In normal USB programmed operation J1 is inserted pulling MUXSEL low and connecting the FPGA and USB microcontroller at all times This allows USB based programming of the FPGA and subsequent USB communication with the FPGA design after configuration In order to allow the PROM to configure the FPGA J1 must be removed In order to deassert MUXSEL post configuration your design must deassert MUXSEL This allows the FPGA design to properly startup and allows for communication over USB even after the PROM has configured it The end result is that your FPGA design should tie HI_MUXSEL to 0 This is the case regardless of how the design was configured via PROM or USB and even if you have PROM less version of the XEM3010 For example in Verilog assign hi_muxsel 1 b0 C Connections The FPGA on the XEM3010 is attached to the lines from the USB microcontroller In order to avoid contention wit
13. MNECHONS no kl Sad be eed eoa 12 LEDs and PUshblittolts Seda oes 13 Reconfiguration Using 51 13 PEL COMMECUOMS 2 02 2 adn 13 SDRAM GIOOK o eara Pau veg ea 13 CE ELO TIL T 14 JP1 JTAG 14 Connection 14 SDRAM 14 Clock Configurati n 2032047 15 Expansion 5 16 doc ccr 16 nti eu 16 Setting I O 2 22 16 Power On I O State PCB revision 20070117 17 Considerations for Differential Signals 17 BRK3010 Breakout 18 Xilinx Configuration 19 Generate an FPGA Programming File 19 Generate a PROM Programming File 19 Programming the Configuration PROM 21 Booting from PROM Ebbene b III PIE 22 XEM3010 Mechanical Drawing 24 Contents XEM3010 User s Manual BRK3010 Mechanical Drawing XEM3010 Quick Reference XEM3010 Quick Reference www opalkelly com User s Manual Introducing the XEM3010 The XEM3010 is a compact 75mm x 50mm 2 95 x 1 97 FPGA board featuring the Xilin
14. User s Manual www opalkelly com 23 XEM3010 User s Manual XEM3010 Mechanical Drawing 50 00 47 00 34 50 18 90 47 00 42 33 3 00 3 00 2 33 0 0 TT 4 45 00 Re J w S Sn 2 8 58 B 8r H 85 Hie Bar S T H RUE AIN 12 60 4 S 1 57 CL 0 9 24 All dimensions mm www opalkelly com XEM3010 User s Manual BRK3010 Mechanical Drawing CN e cw ME NE e O ON ON OO AN Oo x e gt o 3 52 50 4 TPA TPS m bps PO P N 24 80 samo ow ome O 29 32 27 O O O O uae 50 90 mote olo f aloj seue E E S a 583000 3
15. ace There are 24 pins that connect the on board USB microcontroller to the FPGA These pins com prise the host interface on the FPGA and are used for configuration downloads After configura tion these pins are used to allow FrontPanel communication with the FPGA If the FrontPanel okHostIinterface module is instantiated in your design you must map the in terface pins to specific pin locations using Xilinx LOC constraints This may be done using the Xilinx constraints editor or specifying the constraints manually in a text file An example is shown below Xilinx constraints for okHostlnterface pin mappings www opalkelly com 11 XEM3010 User s Manual hi in 0 hi_in lt 1 gt hi_in lt 2 gt hi_in lt 3 gt hi_in lt 4 gt hi_in lt 5 gt hi_in lt 6 gt hi_in lt 7 gt hi_out lt 0 gt hi_out lt 1 gt hi_inout lt 0 gt hi_inout lt 1 gt hi_inout lt 2 gt hi_inout lt 3 gt hi_inout lt 4 gt hi_inout lt 5 gt hi_inout lt 6 gt hi_inout lt 7 gt hi_inout lt 8 gt hi_inout lt 9 gt hi_inout lt 10 gt hi_inout lt 11 gt hi_inout lt 12 gt hi_inout lt 13 gt hi_inout lt 14 gt hi_inout lt 15 gt N10 aN ae V3 RON apo VO MOVIES VIO Wallis Marie VOR IUOS e UO aU Saas VR
16. alkelly com 25 XEM3010 User s Manual XEM3010 Quick Reference JP2 Length Pin Connection LVDS mm peso s mer pmems Eres Gennes e peso pw Ee I 45 ks s ccn is Ets 121P 2 12288 Notes Pinis DCI pin with optionally installed resistors T Some routing on inner layer is not necessarily 500 26 JP2 Length Pin Connection LVDS mm E i 1 1 T xmo _ EE E a peo 1 LUN L24P 3 ps 46 peusas ust 2146 pw 1 T eo ss xsus4e ers 120P 2 14555 ss xeusae 2042 15685 so Host Interface Pin Imi o us m 7 m us Button FPGAPin 82 6 PLLPin Name SYS_CLK1 9 CLKB SYS_CLK2 FPGA P9 www opalkelly com User s Manual XEM3010 Quick Reference JP3 Length Pin Connection LVDS mm ERN BENE 0205 s wc T Eier psg 1 m sw 1 Hr veuss ri LUN S 120 6 LAN 6 6 EIE RN 45 veusze pec 22436 s pw ss veuss p 16298 JP3 Length Pin Connection LVDS
17. any cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application Due to space con straints some pairs are better matched than others Digitally Controlled Impedance The Xilinx Spartan 3 supports digitally controlled impedance This functionality is supported when precision resistors are connected externally between the FPGA VRN VRP lines and VCCO DGND respectively Pads for these resistors have been placed and routed on the XEM3010 but resistors have NOT been installed The end user must install these resistors in order to use DCI The table below lists the resistor designators and the banks they control Resistor FPGAPin FPGA Signal Connection BRK3010 Breakout Board 18 The BRK3010 is a simple two layer breakout board which can be used to evaluate or transition to the XEM3010 It provides standard 0 1 thru hole connections to the 0 8 mm high density con nectors on the XEM3010 The corresponding connections to the XEM3010 are labelled in silkscreen on the BRK3010 The BRK3010 connectors essentially mirror the connections on the XEM3010 left to right For ex ample the JP2 connector on the XEM3010 is electrically
18. ctors along with the total mated height 8 www opalkelly com XEM3010 User s Manual Samtec Part Number Mated Height BTE 040 01 F D A 5 00mm 0 1977 BTE 040 02 F D A 8 00mm 0 315 BTE 040 03 F D A 11 00mm 0 433 BTE 040 04 F D A 16 10mm 0 634 BTE 040 05 F D A 19 10mm 0 752 FrontPanel Support The XEM3010 is fully supported by Opal Kelly s FrontPanel software FrontPanel augments the limited peripheral support with a host of PC based virtual instruments such as LEDs hex displays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigu rable board and adds enormous value to the XEM3010 as an experimentation or prototyping system Programmers Interface In addition to complete support within FrontPanel the XEM3010 is also fully supported by the FrontPanel programmer s interface API a powerful class library available to Windows and Linux programmers allowing you to easily interface your own software to the XEM In addition to the library wrappers have been written for Java and Python making the available under those languages as well Java and Python extensions are available under Win dows and Linux Sample wrappers are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel www opalkelly com 9 XEM3010 User s Manual 10 www opalkelly com XEM3010 User s Manual Applying the XEM3010 Host Interf
19. diagram below The PROM and expansion port of this chain may be bypassed using optional resistors as shown R16 bypasses the PROM and has been inserted on PROM less versions of the XEM3010 R16 is not inserted on XEM3010 versions with the PROM R30 bypasses the expansion connector and has been inserted on all versions of the XEM3010 If your application places additional components in the JTAG chain you must remove R30 Note that the JTAG signal level on the XEM3010 is 2 5 v If your expansion board extends this chain it must also operate at 2 5 v or use level translation to be compatible TDI JP 1 4 PROM TDO P218 TDI P2 9 TDO R30 R16 SDRAM Connections The Micron SDRAM is connected exclusively to the 3 3v I O on Bank 0 and Bank 1 of the FPGA The tables below list these connections 14 www opalkelly com paw os Clock Configuration The XEM3010 has been designed to support SDRAM clocking in both system synchronous XEM3010 User s Manual p fa ps fe po cs pp es pn s and source synchronous modes Both configurations are often referenced in Xilinx application notes describing SDRAM controllers and interfaces System Synchronous In this mode the clock signal is sourced at the system level by the PLL on the XEM3010 The same clock is fanned out to both the FPGA pin N9 and the SDRAM CLK The FPGA there fore considers this signal
20. emove R43 Default Configuration HSWAP is allowed to float and an internal pull up pulls HSWAP EN high This disables the user I O pull up resistors allowing the I Os to float from power on throughout configuration Insert R43 0 O Resistor HSWAP EN is grounded This enables user I O pull up resistors from power on throughout con figuration See the Xilinx Spartan 3 Data Sheet for details regarding the characteristics of these pull ups Considerations for Differential Signals The XEM3010 PCB layout and routing has been designed with several applications in mind including applications requiring the use of differential LVDS pairs Please refer to the Xilinx Spartan 3 datasheet for details on using differential I O standards with the Spartan 3 FPGA FPGA I O Bank Voltages In order to use differential I O standards with the Spartan 3 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Spartan 3 datasheet Please see the sec tion above entitled Setting I O Voltages for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is 50 Q with the exception of routes that are labelled with T in the mapping table These exception routes are routed on inner layers without a proximity ground plane and therefore do not match the 50 O impedance exactly www opalkelly com 17 XEM3010 User s Manual Differential Pair Lengths In m
21. gator by clicking on Generate PROM ACE or JTAG File in the processes list t yay Implement Design Oe Generate Programming File ep Programming File Generation Report Generate PROM ACE or JTAG File Configure Device iMPACT This will start IMPACT When asked tell it you would like to create PROM File Setup PROM File Format At the next screen select Xilinx PROM as a target with the MCS format Here you can also specify a filename for your programming file www opalkelly com 19 XEM3010 User s Manual want to target PROM C Generic Parallel PROM PROM File Format MCS C format C EXO C HEX C BIN ISC Iu Swap Bits Checksum Fill Value 2 Hex Digit FF PROM File Name CountersPROM Location c prom Browse Select the PROM Device At the next screen check Enable Revisioning This is necessary in order to enable some features of the Xilinx PROM that allow it to boot the FPGA as a programming master Select the PROM device as xcf08p the device on the XEM3010 and add it to the list Auto Select PROM Enable Revisioning Number of Revisions 1 Enable Compression Select a PROM xcfO8p Add Position Part Name D xcf08p Delete All 20 www opalkelly com XEM3010 User s Manual Add Bitfiles to PROM The final step in creating the PROM is to add your bitfile t
22. h the I C bus these lines should be set to high impedance within your design If this is not done FrontPanel may timeout or hang when trying to communicate with the XEM3010 particularly when programming the on board PLL 12 www opalkelly com XEM3010 User s Manual The following lines in your UCF contraints file will attach pull ups to the lines NET 12 scl 013 PULLUP NET i2c_sda R13 PULLUP In addition you will need to set these signals to high impedance in your HDL Here is an exam ple of how to do this in Verilog assign i2c sda 1 assign i2c scl 1 bz LEDs and Pushbuttons There are eight LEDs and two pushbuttons on the XEM3010 Each is wired directly to the FPGA according to the pin mapping tables at the end of this document The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be brought high The pushbuttons are connected between their respective FPGA pin and DGND The FPGA side of the connection has a pull up resistor to 2 5VDD Therefore in the pressed state the FPGA pin will be at DGND low and in the unpressed state the FPGA pin will be at 2 5VDD high Note that the pushbuttons are not debounced on the XEM3010 In order to deglitch the signals from the pushbuttons proper debouncing should be done inside the FPGA
23. l names and routed track lengths have been provided to help you equalize lengths on differential pairs JP3 is an 80 pin high density connector providing access to FPGA Banks 6 and 7 Pins 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin 8 on this connector is SYSCLK5 and is directly connected to CLKE on the Cypress CY22393 PLL Using FrontPanel s PLL Configuration Dialog you can configure the clock signal present on this pin Pin mappings for JP3 are listed at the end of this document in the Quick Reference section For each JP3 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs Setting I O Voltages The Spartan 3 FPGA allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by the XEM3010 by allowing the user to connect independent supplies to the FRGA VCCO pins on four of the FPGA banks By default ferrite beads have been installed which attach each VCCO bank to the 3 3VDD supply If you intend to supply power to a particular I O bank you MUST remove the appropriate ferrite beads Power can then be supplied thro
24. mm 2 1l uw 1 T esae T Ho ue sa 1 jue so ma pw Ses I 46 ees s o 0540 Ha 1297 se veusae ra 121e 12971 o es irouz 1166 m oo o pw 1 Ll Notes Pinis a DCI pin with optionally installed resistors T Some routing on inner layer is not necessarily 500 www opalkelly com 27
25. o the PROM Simply select the file e g counters bit that you generated previously Once you complete the Wizard the MCS program ming file will be created in the directory specified In our case we have CountersPROM mcs Programming the Configuration PROM Once we have a PROM programming file we can transfer that file to the Xilinx Configuration PROM on the XEM3010 using a JTAG cable The Xilinx Parallel IV or Xilinx USB JTAG cables will work just fine for this process Connecting to the JTAG Chain At this point you may attach your programming cable to the XEM3010 Be sure to connect the pins correctly or you could damage the XEM3010 or the programming cable If you are still in iMPACT you can switch to Configuration Mode using the Mode menu at the top of the window Allow iMPACT to automatically discover the JTAG chain and you will end up with a graphical representation of the chain NH xcf 8p xc3s1500 File File TDI TDO Assign the PROM Configuration File Assign the PROM configuration file CountersPROM mcs that you created in the previous step to the XCFO8P device You may bypass the 351500 device since we will only be configuring the PROM Program the PROM Once a configuration file has been assigned to the PROM device you will be able to program it by right clicking on the device and selecting Program from the context menu In the options dialog setup the following options
26. terface XC3S1 000 4FG320 Bus PLL or XC3S1500 4FG320 1010 CY22393 2 Pushbuttons 8 LEDs gt YBUS JP3 Power Supply The XEM3010 is designed to be operated from one of three power sources depending on user requirements One of these three sources provides power for the two high efficiency switching regulators on board to provide 3 3v and 1 2v 2 5v and 1 8v are derived from the 3 3v supply us ing small low dropout LDO regulators The three sources and the respective XEM3010 configuration for each are shown in the table below In all configurations the XEM3010 requires a clean well regulated supply between 4 5v and 5 5v XEM3010 Configuration DC Power Jack P1 No configuration is required Attach a DC power source to P1 that supplies a clean regulated voltage of 4 5v to 5 5v Expansion Connector No configuration is required Provide a clean regulated voltage of JP3 4 5v to 5 5v to the VDC pins USB Bus Power See section on USB Bus Power IMPORTANT NOTE Only one power source should be connected at any time Attaching mul tiple power sources could damage the XEM3010 and possibly the power source and void the warranty on the XEM3010 There two switching regulators on board one for the 3 3v supply and one for the 1 2v supply Each supply has been designed to provide up to 3 A of continuous current It is unlikely that the XEM3010 will consume this much current so
27. ugh the expansion connectors The table below lists details for user supplied I O bank voltages I O Bank FPGA Pins Ferrite Bead 2 pese J12 H12 FTG N16 Ki2 K7 L7 N3 4 JP3 56 F3 H7 J7 FB5 www opalkelly com XEM3010 User s Manual Clock Inputs and Bank Voltages Note that the four clock inputs available on the expansion connectors are connected to FPGA banks 0 and 1 Bank voltages for these two banks are fixed the XEM3010 to 3 3VDD How ever Xilinx Answer Record 18095 states Differential Input Buffers are powered by VCCAUX and are not VCCO depen dent Consequently you can put LVDS 25 and LVPECL 25 input buffers in a 3 3V bank without damaging the device Instantiating LVDS_25 or LVPECL 25 input buffer in 3 3V bank does not generate a software error For more information on this please refer to the Xilinx Answer Record and other references avail able within that record Power On I O State PCB revision 20070117 In all versions of the XEM3010 prior to 20070117 YYYYMMDD datecode the HSWAP EN pin E6 on the FPGA was directly connected to DGND This enables pull up resistors on all User I Os from power on throughout configuration See the Spartan 3 Data Sheet from Xilinx With version 20070117 a 0 resistor has been added R43 By default this resistor IS NOT LOADED This resistor connects HSWAP EN to DGND Therefore for version 20070117 there are two possible configurations R
28. x Spartan 3 FPGA Designed as a full featured integration system the XEM3010 provides access to over 110 I O pins on its 320 pin Spartan 3 device and has a 32 MByte SDRAM available to the FPGA The XEM3010 is designed to work with small to medium sized FPGA designs with a wide variety of external interface requirements PCB Footprint A mechanical drawing of the XEM3010 is shown at the end of this manual The PCB is 75mm x 50mm with four mounting holes spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM3010 The two connectors USB and DC power overhang the PCB by approximately 4mm in order to accomodate mounting within an enclosure The XEM3010 has two high density 80 pin connectors on the bottom side which provide access to many FPGA pins power JTAG and the microcontroller s 12C interface BRK3010 Breakout Board A simple breakout board the BRK3010 is provided as an optional accessory to the XEM3010 This breakout board provides easy access to the high density connectors on the XEM3010 by routing them to lower density 0 1 spaced thru holes The breakout board also provides a conve nient reference for building boards that will mate to the XEM3010 A mechanical drawing of the BRK3010 is also shown at the end of this document www opalkelly com 5 XEM3010 User s Manual Functional Block Diagram PROM SDRAM XCFO8P MTA8LC16M16 USB 71 Spartan 3 FPGA Host In
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