EDP-CM-LPC1768 Command Module User Manual Version 2.03
Contents
1. Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPC B Coventry DEVELOPMENT TOOLS Date 07 04 2010 c Hitex UK Ltd Sheet4 of 5 File DAPCB Designs DXP EDP CM LPCx Rev B Jumpers SchDoc Author A Davison 2 3 4 6 7 8 3V3 C501 100nF C509 C510 100nF 10uF 10V SGND SGND A 4 DL TriStat 2 0501 3 lt OUTPUI GNE 1 Pl 4 ENET TX EN x 50 000MHZ XO53050USGND P1 0 TXDO I EDI 4 5 P1 9 RXDO 3V3 P1 10 RXDI 4 45 45 5 4 95 505 mm ENET CRS 957 195 ABI ENET MDIO ENET REF CLK V gt Y 509 4 87 1 min lt SGND SGND SGND 3V3 100nF SGND 0502 SPI MOSII CANO TX LOCAL SPI SCKI CANO RX LOCAL E SPI MISOI ST28008V1A SN65HVD230D SGND Checked By Title Hitex UK Ltd Ethernet CAN SD Card Sir William Lyons Road hitex Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPCx B Coventry DEVELOPMENT TOOLS Date 07 04 2010 c Hitex UK Ltd Sheet5 of 5 File DAPCB Designs DXP EDP CM LPCx Re2. 63 _ 2 6 18 tvos GPlO46 6 602 ________ 21 2 z3 P601 NEN p P602 P6 28 tVGl4 s 102 271 GPlOG3 101 EVGI6 GPIO64 s ____ 281 EVG17_GPIO65 6 30 EVG18 06 87 2 EVG19 GPlOG7 01 EVG20 GPIO69 Asco RIS 92 Poon GIO a 1 el EVMLGPIO3 4 1 9 EVM2 GPIO41 CAPADC __ 62 1 18 EVM3 GPIO33 64 1 19 GPIO5 6 20 ef 21 GPO49 70 22 _ 7 GP z PO pevmgcpioss 7411 6005 76 10 GPIO68 ASCO CTS 90 P601 eo 14 2 NEN Sor EK 602 NE P603 P603 P603 P603 P603 Electrocomponents plc Page 11 EDP CM LPC1768 CPU Module GPIO11 125 SDA P603 24 Corona omo a GPOI3 DS TX IK 34 pes 35 PO GPIOI5 DS TX SDA 36 GPIO2A ao GPIODS ADIS 46 GPIO26 avs 47 _____ GPIO27 ADI jeo f _ 49 GPIO29 ADI 59 GPOS0 aba 5 Nm P602 1 e gt e IN 1 ADI2 601 GPIO32_AD3
3. 5 MOTOR P2H CNTRL I2C SDA x MOTOR PWM CNTRL 2 SCL EMG TRP USB HOST D MOTOR H0 ENCO USB HOST D DC GENI SDA MOTOR H1 ENCI USB DEV D 12 SCL MOTOR H2 ENC2 USB DEV D CANI RX MOTOR TCO FB CANHO CANI TX m eU CANLO VCC_CM 3V3 lt gt 3V3 VCC_CM 3V3 lt gt 3V3 CM 3V3 lt gt 3V3 3V3 lt gt 3V3 5 lt gt 5 5V 4 gt 5 SGND SGND SGND SGND HV lt gt d 2 lt id Tyco Amp 100 Way 12VGND d 0 12VGND Tyco Amp 140 Way Checked By Title Hitex UK Ltd Module Connectors Sir William Lyons Road hitex Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPCx B Coventry DEVELOPMENT TOOLS Date 07 04 2010 c Hitex UK Ltd Sheet of5 File DAPCB Designs DXP EDP CM LPCx Rev B Module Connectors SchDoc Author A Davison 1 2 4 5 6 7 8 3V3 43V3 7 A A 1 JP201 3 AN REF 1 JP202 3 AN REF 1 203 3 A Solderlink Bolderlink A Bolderlink 3V3 A PO 0 1 2 1 7 3 PIO1 6 PO 4 PIOO 3 PO SS PIOT29 8 SD SPI 5 SPI MISOI SPI MOSII PO 10 2 0 PO II PIO2 11 CNTRL SPI CLK CNTRL SPIZCS NSS CNTRL SPI MRST CNTRL SPI MTSR 19 102 7 PO 20 PIO2 4 PO 21 PIO1 8 PO 22 PIO2 5 23 4 24 P2 0 PIO2 8 P2 I PIOO 6 EVM9 GPIOSS P2 3 PIO2 9 P2 4 PIO2 1
4. 21 P1 30 Vbus ADO 4 P1 31 SCK1 ADO 5 EVGO GPIO40 p421 48 PO 10 TXD2 SDA2 MAT3 0 EVG6 GPIO52 GPIO1 49 11 amp 02 12 1 EVG7 GPIO54 73 P22 PWMI BI CTSI TRACEDATA lt gt GPIO55 PO 2 TXDO ADO 7 MOTORPOH 9 EVG9 GPIO57 MOTORPOL 2 36 Jp1 22 MCOB USB PWRD MATA O EVG12 GPIO60 MOTORP1H EVG15 GPIO63 MOTORP1L P1 26 MC1B PWM1 6 CAPO 0 EVG16 GPIO64 MOTORP2H JP417 EVG17 GPIO65 MOTORP2L 18 EVG18 GPIO66 EMG TRAP P1 21 MCABORT PWM1 3 SSELO EVG11 GPIO59 MOTORHO 1 20 1 2 5 EVG10 GPIO58 MOTORH1 ENC1 JP413 es 37 P1123 MCFB1 PWM1 4 MISOO 1692 7 MOTOR FB mu mE 1P414 67 P216 PCAP1 0 RIM TRACECIK AS 29 38 P1 24 MCFB2 PWM1 5 MOSI0 EVG14 621062 33 P1 19 MCOA USB_PPWR CAP1 1 wo 2 gt gt 5 N P1 25 MC1A MAT1 1 1 458 GPIO7 125 RX CLK 81 Po a 125RX CLK RD2 CAP2 0 EVMO GPIO21 1 437 GPIO9 125 RX WS PO S I2SRX Ws TD2 CAP2 1 1 GPIO23 CPU DACOO GPIO17 P127Y CLKOUT USB OVRCR CAPO lt gt GPIO47 D P1 28 MC2A PCAP1 0 MATO 0 A P1 29 MC2B PCAP1 1 MATO 1 D Electrocomponents plc Page 13 EDP CM LPC1768 CPU Module R5 3 3V REF GPIO8 MCI DAT3 lt gt 0 SDA Vref GP
5. P602 12 GPIO33 AD11 sa 14 GPIO34 AD2 P602 GPIO35 AD10 P601 GPIO36 AD1 P602 GPIO37 AD9 P601 16 P602 15 P601 P603 P603 100 A Ww E N E UY 0 CO UY gt 00 5 44 11 10 P602 N 48 P601 45 P601 46 7 79 9 722 70 7 5 5 ID 5 O W BA m 601 601 W W 40 39 42 601 IB E P601 P603 P603 P603 P603 P602 P601 P601 P601 y go go D U U DIM P603 P603 P603 P603 P601 P601 P603 P603 P603 EM Electrocomponents plc Page 12 EDP CM LPC1768 CPU Module R5 2 5 Mapping Aids TP406 EVGO GPIO40 p 2 AN9 gt PO 24 ADO 1 I2SRX WS CAP3 1 AN2 101 26 P3 26 STCLK MATO 1 PWM1 3 lt gt gt 7__ PO 25 ADO 2 125RX_SDA TXD3 Ha diui d CPU DACOO GPIO17 70 P2 3 PWM1 4 DCD1 TRACEDATA 2 E EVG2 GPIO44 P408 gt PO 26 ADO 3 AQUT RXD3 CPU DACO1 GPIO19 3 69 Pp2 4I PWMA 5 DSR1 TRACEDATA 1 pum JP405 JP428 n 2 PAS PWMIS OTRI TRACEDATADO B P2 5 PWM1 6 DTR1 TRACEDATA O 0 EVG19 GPIO67 12 gt 407 EVG5_GPIO50 13 32 P1 18 USB UP LED PWM1LT CAP1 O EVG8 GPIO56 gt ANG gt PO 3 RXDO ADO 6
6. 19 102 7 P2 0 PIO2 8 P273 P1029 P2 4 PIO2 10 PO 11 102 11 XTAL2 USB DEV D USB DEV 19 103 0 P1 20 PIO3 1 22 PIO3 2 P1 23 PIO3 3 XTAL MUST BE POSITIONED CLOSE TO BOTH U201 AND U301 Checked By Title Hitex UK Ltd LPC1343 Sir William Lyons Road hitex Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPC B Coventry DEVELOPMENT TOOLS Date 07 04 2010 c Hitex UK Ltd Sheet3 of 5 File DAPCB Designs DXP EDP CM LPCx Rev B LPC1343 SchDoc Author A Davison 1 2 3 4 5 6 8 1 408 Solderlink DACOO GPIO17 2 19 0 2 9 57 MOTOR HO ENCO P1 20 PIO3 1 2 MOTOR P2H P1 28 PIOO 2 2 EVGI7 GPIO65 MOTOR P2L P1 29 PIOO 8 2 8 GPIO66 ASC1 TX TIL 1 ASCI TX TTL_ASCO DTR P2 BIOS EVM6 GPIO49 PO 22 PI02 5 GPIO2 MCIDATO EVMA GPIO45 PO 21 PIO1 8 GPIOI4 MCIPWR EMG TRP CANO RX MOTOR TCO FB EVM3 GPIO43 2 3V3 JP411 P1 21 PIO2 3 2 0 0 2 4 CANO RX LOCAL PO 20 PIO2 4 Solderlink A JP419 EVGII GPIOS
7. 2 link option 77 EVGA ink option 7 619 GPIO67 69 P2 AI PWMI SI DSRI TRACEDATA I 2linkoption CPU GPIO19 EVG3 GPIOAG 2 link option EVG3 GPIO46 P2 3 PWM1 4 DCD1 TRACEDATA 2 2link option CPU DACOO GPIO17 S OO Vdd 3V3 72 Vss 73 PXDJ PWMIBI CTSITRACEDATAB 0 O O 76 7 25 5 _ LocalSDSPL MOS 0 0 77 25 WS MISO1 MAT2 2 Local SD SPIMISO 78 7 CLK SCKI MAT2 1J 1 sD_sPICLK 79 PO G IZSRXSDA SSEL1 MAT2 0 toalSDCS SD J 80 7 PO SZSRX WS TD2 CAP21 3limkoptions GPIOS DS O DACOOGPIO 2 PADSI RK MCLK MAT2O TXD3 USB Debug ports FTDI chip 83 ss 84 9 85 MCLK MAT2 1 RXD3 USB Debug ports FTDI chip O Z O Z o 86 PIIZ ENET Ethernernet PHY chip 87 MDC Ethernernet PHY chip Ethernernet PHY chip J 89 PIIAENET RKER EhemeretPHYchp O o S O 90 PIIOJENET RXD1 Ethemernet PHY chip 91 PISENET RXDO amp hememetPHYchp O 92 Ethemernet PHY chie O o 93 PIENE TXEN EthememetPHY chie Electrocomponents plc Page 5 EDP CM LPC1768 CPU Mod
8. 1 MOTORP1H EVG15_GPIO63 BA 2 link options EVG16 4 IB E SS BA N Vdd reg 3V3 P1 27 CLKOUT USB_OVRCR CAPO 1 EVMS 62047 2 link options MOTORP2H 2 link options EVG17 GPIO65 9 P1 28 MC2A PCAP1 0 MATO O P1 26 MC1B PWM1 6 CAPO O 2 link options MOTORP1L P1 29 MC2B PCAP1 1 MATO 1 MOTORP2L EVG18 GPIO66 PO O RD1 TXD3 SDA1 CANO_TX CANO LOCAL I2C GENO SDA PO 1 TD1 RXD3 SCL1 CANO RX LOCAL I2C GENO SCL IS BA 4 N BA 8 PO 10 TXD2 SDA2 MAT3 0 GPIOO EVG6_GPIO52 PO 11 RXD2 SCL2 MAT3 1 GPIO1 EVG7 GPIOS4 4 Electrocomponents plc Page 4 EDP CM LPC1768 CPU Module R5 P2 13 HEINT3 I2STX SDA GPIO8 DAT3 a Tonens 53 7 2 2 IRQGPIO16 IC INT 2lnkoptons GPIOI8 ys o Vss o 2 int pO 2 int oo 7 2 CAPADC 60 61 7 CNIRLSPLMRST 62 SPLCLK NTL SP sp O 64 P2J USB CONNECI RXD2 2limkoptions ASCA RX TTL EVMIO 62068 ASCO __ 2 CANT 66 22 82 52 link options ASCL TX TIL ASCO DIR 68 P2 5 PWM1 6 DTR1 TRACEDATA O _
9. 1 TECOS papsen FESTES perdi IE S y Electrocomponents plc Page 9 EDP CM LPC1768 CPU Module WR 47 amp 48 49850 y __ AE up __ rr m ____ ___ 1412 4384 ___ P601 6l ANO ______ 2 4 6 1j ANA P2 a2 C feo al 3 ANS 2j _____ Poon _____ _____ P8 al ________ __ ___30 _______ 31 ______ _ 32 ________ 3 152 3 _______ 3 631862 Jo 63864 ________ P2 v Electrocomponents plc Page 10 EDP CM LPC1768 CPU Module CANHO 89 amp 90 P603 40 CANO 41 CNTRLDCSCL 79480 P603 CNRLDCSDA 77878 CNTRL SPI 5 NSS 75876 33 CNTRL SPCK 687 30 CNIRLSPLMRST 71872 CNTRLSPLMISR 1 73 4 9 CPU pacos Grios 40 71 CPU DACOO 38 753 7 EMG 14 peo ETHINKIED e 1 feo pez 22 ETHRG 0 9 62 ETHSPDIED adis 2 EIHD o 5 38 P EVE GPlO40 61 ____ Eves
10. JP427 2 3 Default MOTOR TCO FB User LEDO P2 7 RD2 RTS1 JP426 2 1 Default JP426 2 3 5 1 TX TTL ASCO DTR CAN1 RX P2 8 TD2 TXD2 JP425 2 1 Default JP425 2 3 5 1 TX TTL 1 TX P2 9 USB CONNECT RXD2 JP424 2 1 Default 1 424 2 3 5 1 RX TTL P2 10 HEINTO NMI 1 423 2 1 Default 1 423 2 3 GPIO16 CNTRL I2C INT GPIO18 I2C GENO INT Port P3 Options P3 25 MATO 0 PWM1 2 406 2 1 Electrocomponents plc Page 18 EDP CM LPC1768 CPU Module R5 JP406 2 3 Default User LED1 Selecting JP406 position 2 3 allows use of the on board user led LED1 0401 4 Zero Ohm Links CAN Load Resistor JP501 This link when inserted includes a 120 ohm resistor across CANHO and CANLO The default is connected AN REF This zero ohm link when inserted provides a 3 3V reference for the EDP platform The 3 3V used is the local supply voltage derived from a local voltage regulator This link should be used in the absence of a 3 3V voltage reference voltage provided by the Analogue Module when fitted The default position is not connected AGND amp VAGND This link when inserted provides a way of connecting the VAGND to the SGND This is the default position The two grounds alternatively can be connected to each other on the analogue module 5 Software Support The NXP Command Module for the RS EDP platform is supported by all of the necessary soft
11. 0 P2 5 102 2 P2 6 P2 7 PIO2 1 P2 8 P2 9 P2 10 GPIO4 MCIDATI GPIO6 MCIDAT2 GPIO8 MCIDAT3 Only with LPC1768 P3 25 PIOO 1 LPC2368 Only populate with 768 and LPC2368 3V3 N V USB DEBUG D As NO Co V Y USB DEBUG D A n A V Header 2X2 ASAAN 42 3V3 alulululalaolololelelololol loo V 25 il TRST 26 4 15 CNTRL 12C SDA 2 CNTRL 2 SCL 24 USB DEV D 29 USB DEV D 30 P1 ENET TXDO pm E TXDI al sil 5 al a 2X10 Header RXDO 10 RXDI 201 14 RX ER L lcxsv T1A 32 768kHz 15 ENET REF _ 32 768KHz C202 1 16 17 MDIO j SGND 18 PIO1 10 e 19 103 0 4 Only Populate for LPC1768 20 PIO3 1 Or LPC2368 21 PIO2 3 3 V3 CSTCE12M0G55 Y 3 P1 22 PI03 2 AO YB NAS NO eor OY oy eo NOE AAN V 45 45 i 5 oo oo o o o o o 12MH 23 R103 3 T 2 SGND TMS SWDIO P1 24 TCK SWCLK PI 25 x TDO SWO PI
12. 26 3 EVMS GPIO47 B 28 PIOO 2 P1 29 PIOO 8 al Header 5X2 1_30 1 1 11 a PI 31 A LPC2368FBD100 LPC1768FBD100 SGND MCP120T 300 TT 3V3 SGND Checked By Title Hitex UK Ltd LPC2368 and JTAG Sir William Lyons Road hitex Size Number Revision University of Warwick Science Park Approved By A3 EDP CM LPCx B Coventry DEVELOPMENT TOOLS Date 07 04 2010 c Hitex UK Ltd Sheet2 015 File DAPCB Designs DXP EDP CM LPCx Rev B LPC2368 SchDoc Author A Davison 2 3 4 5 6 7 8 1 2 3 4 5 6 8 3N3 C301 C302 100nF 100nF SGND 3N3 P3 25 PIOO 1 Tbo swo 8301 r 28 OR TMS SwpIo 302 TDO SWO PIO 1 34 ZIRST 35 _________________ TMS SWDIO pion 38 OR PO 23 PIO1 4 40 P3 25 PIOO 1 P1 28 PIOO 2 4 PIOO 3 CNTRL DC SCL CNTRL DC SDA P2 I PIOO 6 9 GPIOSS P1 29 PIOO 8 PIOO 9 TCK SWCLK TDI 5 GPIO47 PO 3 PIO1 6 2 PIO1 7 PO 21 PIO1 8 S PIOI 9 18 1 10 P11530 PIOT 11 ES R 0 33 30 3 42 1 AAALA melanie T LPC1343FBD48 PO 10 2 0 P2 1 P2 5 2 2 P1 3 20 PIO2 4 PO 22 PIO2 5 EVGI GPIO42
13. 5 JTAGinterfaceoniPCmodue 6 PODSIADOSJ AOUT RXD3 Slinkoptions OOO Bios Bink options CPU DACOO_GPIO17 ___ tink options 8 PO 24j ADO 1 I2SRX WS CAP3 1 2 link options 1 2 link options AN9 9 POf23 ADO O 2SRX 2 link options 2 link options 8 Electrocomponents plc Page 3 EDP CM LPC1768 CPU Module HRSTOUT 14 VREFN 20 P1 31 SCK1 ADO 5 ANS AN13 AN12 N E P1 30 Vbus ADO 4 XTAL1 XTAL2 PO 28 SCLO USB SCL PO 27 SDAO USB_SDA 23 N CNTRL 12 SCL CNTRL 12 SDA N N P3 26 STCLK MATO 1 PWM1 3 EVG1 GPIO42 N N P3 25 MATO 0 PWM1 2 2 link options EVGO_GPIO40 2 Link options User LED1 N Vdd 3V3 PO 29 USB D PO 30 USB D WIN lt N P1 18 USB_UP_LED PWM1 1 CAP1 0 3 link options EVG5 GPIO50 EVG8 GPIO56 EVGO GPIO40 P1 19 MCOA USB PPWR CAP1 1 MOTORPOH EVG9_GPIO57 P1 20 MCFBO PWM1 2 SCKO MOTORHO ENCO QJ 2 link options EVG10_GPIO58 P1 21 MCABORT PWM1 3 SSELO 2 link options EMG_TRAP Ww EVG11 6 059 P 1 22 MCOB USB_PWRD MAT1 0 MOTORPOL EVG12_GPIO60 P1 23 MCFB1 PWM1 4 MISOO MOTORH1_ENC1 2 link options EVG13 1 P1 24 MCFB2 PWM1 5 MOSIO MOTORH2_ENC2 EVG14 GPIO62 P1 25 MC1A MAT1
14. 9 Solderlink e I2C SDA e GPIO12 MCICMD ANO MOTOR POL CANO TX 4 GPIO48 EVM2 GPIO41 CAPADC PO 23 PIO1 4 P1 22 PIO3 2 2 1 2 4 CANO TX LOCAL P2 5 2 2 PO 19 PIO2 7 Solderlink 72420 0402 Solderlink MLED YELLOW e AN8 2 60 e I2C GENO SCL e EVGI9 GPIO67 e GPIO10 MCICLK ANS MOTOR H1 ENCI EVG3 GPIO46 EVMI GPIO23 2 NE JP437 Iderlink POSEE gt eee 10 02 0 P2 4 02 10 PO 5 9 B Solderlink e AN13 EVG13 GPIO61 e EVG6 GPIOS2 e CPU GPIO19 1 GPIO9 DSRX WS ANA MOTOR H2 ENC2 GPIOI EVG2 GPIO44 EVMO GPIO21 P1 30 PIO1 11 24 2 PO TI PIO2 11 P2 3 PIO2 9 PO 4 100 3 Solderlink e ANI2 e EVG14 GPIO62 e EVG7 GPIO54 e CPU DACOO GPIO17 1 GPIO7 DSRX EVGO GPIO40 MOTOR GPIOI6 CNTRL D2C INT 8 GPIOS3 ASCO TX TTL 1 TENE ed n E 439 1 406 1 415 1 423 Solderlink P3 25 PIOO 1 P1525 2 Solderink 2 1 0 6 2 PIO1 7 E 4 AN7 Q401 15 GPIO63 A GPIO18 2 GENO INT ASCI RX TTL 1 15 BC848C N 402 EVGS GPIOSO 330R MOTOR PIL ASCI RX TTL EVM7 GPIOSI ASCO RX TTL 1407 _ 420 Solderlink P416 Solderlink 18 PIO1 10 4 EVGO GPIO40 P1 26 2 5 P2 0 PIO2 8 PO 3 PIO1 6 E 4 6 D401 Solderlink YELLOW e EVGS8 56 6 GPIO64 e EVMIO GPIO68 ASCO CTS e ASCI TX TTL e 14 SGND Checked By Title Hitex UK Ltd Link Options Sir William Lyons Road hitex
15. BO PWM1 2 SCKO JP410 2 1 JP410 2 3 Default 3P410 2 1 MOTORHO ENCO P1 21 MCABORT PWM1 3 SSELO EMG_TRAP 1 411 2 1 1 411 2 3 Default P1 22 MCOB USB_PWRD MAT1 0 1 412 2 1 MOTORPOL JP412 2 3 Default P1 23 MCFB1 PWM1 4 MISOO 1 413 2 1 JP413 2 3 Default 1 P1 24 MCFB2 PWM1 5 MOSIO JP414 2 1 JP414 2 3 Default P1 25 MC1A MAT1 1 1 415 2 1 1 415 2 3 Default MOTORP1H P1 26 MC1B PWM1 6 CAPO 0 1 416 2 1 1 416 2 3 Default MOTORP1L P1 28 MC2A PCAP1 0 MATO 0 417 2 1 JP417 2 3 Default MOTORP2H P1 29 MC2B PCAP1 1 MATO 1 1 418 2 1 JP418 2 3 Default MOTORP2L P1 30 Vbus ADO 4 405 2 1 Default AN4 1 405 2 3 AN12 Electrocomponents plc Page 17 EDP CM LPC1768 CPU Module P1 31 SCK1 ADO 5 1 404 2 1 Default 5 1 404 2 3 13 Port P2 Options P2 0 PWM1 1 TXD1 1 432 2 3 1 432 2 1 Default 5 1 P2 1 PWM1 2 RXD1 JP431 2 3 JP431 2 1 Default 5 1 RX TTL P2 3 PWM1 4 DCD1 TRACEDATA 2 JP430 2 3 CPU DACOO GPIO17 JP430 2 1 Default P2 4 PWM1 5 DSR1 TRACEDATA 1 1 429 2 3 CPU DACO1 GPIO19 JP429 2 1 Default JP428 2 1 Default JP428 2 3 5 2 2 EA 2 gt rm gt gt 2 P2 6 PCAP1 O RI 1 TRACECLK 1 427 2 1
16. C_SDA lt gt SCL Paf17 ENET MDIO 87 P1 16 ENET 89 FTH TX P1 10 ENET_RXD1 FTH 91 P1 9 ENET_RXDO FTH RX P 3 P1 A4 ENET TX EN 94 P1 1 ENET TXD1 95 P1 O ENET TXDO VE 419 GPIO16 CNTRL 12 INT GPIO18 2 GENO INT D 3 Solder Link Options Many of the options for the Command Module board require a solder bridge to be made or a track to be cut The CM board has been designed to be configured in the most popular setting by using a small track between the options which will require cutting with a sharp knife before making the alternate connection options The options we have are as follows VDDA JP201 1 2 VDDA on the MCU is connected to 3 3V JP201 2 3 VDDA on the MCU is connected to AN REF on the backplane Vref Electrocomponents plc Page 14 EDP CM LPC1768 CPU Module R5 JP202 1 2 VREF on the MCU is connected to 3 3V JP202 2 3 VREF on the MCU is connected to AN REF on the backplane VBAT JP203 1 2 VBAT on the MCU is connected to 3 3V JP203 2 3 VREF on the MCU is connected to 3V3 BATT on the backplane Port PO Options PO O RD1 TXD3 SDA1 1 419 2 1 CANO_TX 419 2 4 Default CANO_TX_LOCAL 1 419 2 3 2 GENO SDA Position 2 1 puts the CAN logic level transmit traffic on the backplane A physical layer CAN transce
17. EDP CM LPC1768 CPU Module EDP CM LPC1768 Command Module User Manual Version 2 03 10th June 2010 Electrocomponents plc Page 1 EDP CM LPC1768 CPU Module Contents 1 Introduction 2 MCU Mapping 2 1 MCU Pin Allocation 2 2 Resources Used Available by the 1768 2 3 Alphabetical Listing of MCU pins 2 4 Backplane Signal Names and Connections 2 5 Mapping c 3 Solder Link Options 4 Zero Ohm Links 5 Software Support 5 1 SEG EDU 5 2 5 3 Suite E 5 4 ro ufo Electrocomponents plc Page 2 EDP CM LPC1768 CPU Module R5 1 Introduction The RS EDP platform is a system has been designed to utilise many different manufacturers microprocessors To support NXP range or ARM Cortex MCU s a single Command Module CM has been designed to accommodate four different device types These are LPC2368 ARM7 LPC1768 Cortex M3 LPC1343 Cortex M3 and LPC1113 Cortex MO Each of the boards come with its own suite of software to fully exercise the RS EDP Application Modules and the peripherals available on the MCU device In an RS EDP system there is usually one Command Module CM and one or more Applications Modules AM pl
18. IO6 MCI DAT2 lt gt 51 p 12 8EINT2 I25TX WS GPIO4 MCI gt 52 P2 11 kEINT1 125TX_CLK 3 3V JP433 Vdda 56 PO 22 RTS1 TD1 EVM6 GPIO49 e popajfarsi e 434 GPIO14 MCI PWR 203 lt lt 57 PO 21 RIT RD1 621045 57 21 RI1 Vbat VBAT AM ELLE JP435 3 3V GPIO12 MCI 58 PO 20 DTR1 SCL1 EVM3 GPIO43 SGND GPIO10 MCI CLK 436 VAGND 59 PO 19 DSR1 SDA1 EVM2 GPIO41 CAPADC lt HRESET gt RESET_OUT CNTRL SPI 60 __ CNTRL SPI MRST CNTRL SPI CNTRL SPI CS NSS 33V VCC CM Virtual UART 85 PA 29 TX MCLK MAT2 1 RXD3 i Debus USB 0 82 PA 28 RX 2 0 Debug USB D Do PO 29 USB 0 lt gt 30 PO 30 USB D EL pps ASC1 TX TTL 75 P2 0 PWMA 1 TXD1 EVM7_GPIO51 p TTL 74 P2 1 PWM1 2 RXD1 2 EVM8_GPIO53 ASC1 TX TTL ASCO DTR 66 P217 RD2 RTS1 ED EQ CAN1 RX 10825 ASC1 TX TTL 65 P2 8 TD2 TXD2 A 1 424 ASC1 RX TTL 64 P2 9 USB CONNECT RXD2 EVM10 GPIO68 ASCO CTS CANO_RX JP 423 46 PO O RD1 TXD3 SDA1 CANO_RX_LOCAL lt 2C GENO SDA 53 P2 10 amp EINTO NMI 1 420 CNTRL I2C SCL c 427 PO 1I TD1 RXD3 SCL1 TX LOCAL 25 po 27 sDA0 USB SDA CNTRL_I2
19. MD DSTX CLK HRESIN GPIO14 MCIPWR GPIOI5 DSTX SDA RESOUT IRQ GPIOI6 CNTRL DC INT CPU GPIO17 2 SDA IRQ GPIOI8 2 GENO INT CPU GPIOI9 12 GENO SCL IRQ GPIO20 GENI INT EVMO GPIO21 TENE GPIO22 DC INT EVMI GPIO23 15 ADIS GPIO24 AD7 GPIO25 ADIS 14 ADIA GPIO26 AD6 GPIO27 ADIA A13 ADI3 GPIO28 ADS GPIO29 ADI3 12 ADI2 GPIO30 GPIO31 ADI2 ADII GPIO32 AD3 GPIO33 ADII A10 ADIO GPIO34 AD2 GPIO35 ADIO A9 AD9 GPIO36 ADI GPIO37 AD9 A8 ADS GPIO38 ADO GPIO39 ADS 7 7 EVGO GPIO40 EVM2 GPIO41 CAPADC 6 GPIO42 EVM3 GPIO43 5 ADS EVG2 GPIO44 GPIO45 A4 EVG3 GPIO46 EVMS GPIO47 A3 AD3 4 GPIO48 EVM6 GPIO49 A2 AD2 5 50 EVM7 GPIOSI Al ADI EVG6 GPIO52 8 53 0 ADO EVG7 1054 EVM9 GPIOSS ALE 8 GPIO56 EVG9 GPIO57 RD GPIOS8 EVGII 59 ZWR EVGI2 GPIO60 EVGI3 GPIO61 ZWRH EVG14 1062 EVGIS 63 PSEN EVGI6 64 EVGI7 GPIO65 50 18_ 1 EVGI9 67 51 5 0 TTL 10 GPIO68 ASCO CTS 52 ASCO TX TIL EVG20 GPIO69 ASCO RTS CS3 ASCI RX TTL SPI SSC MRST MISO CANO RX ASC 1X TIL SPI SSC MTSR CANO TX ASCI TX 5 0 DTR SPI SSC CLK USB DEBUG D 5 TTL 5 0 DSR MOTOR POL USB DEBUG D SPI SSC 5 55 MOTOR POH CNTRL SPI CLK ETH TX P MOTOR PIL CNTRL SPI MRST e MOTOR P1H CNTRL SPI MTSR MOTOR P2L CNTRL SPI 5 NSS D
20. iver on the Communications Module can translate this in to the CANH and CANL physical layer for networking It is possible on the Communications Module to make this CAN isolated Position 2 4 routes the CAN logic level transmit traffic to a local physical layer CAN transceiver on the NXP Command Module The output of the CAN transceiver CANH and CANL is routed down the back plane to the Comms Module and output on a standard 9 way D connector Position 2 3 allows this pin to be used as a second I2C channel 2 GENO PO 1 TD1 RXD3 SCL1 1 420 2 1 CANO RX 1 420 2 4 Default CANO RX LOCAL 1 420 2 3 I2C GENO SCL Position 2 1 routes the CAN logic level receive traffic from the backplane to the 1 0 pin The traffic usually comes from the physical layer CAN transceiver present on the Communications Module It is possible on the Comms Module to have an isolated CAN stream Position 2 4 routes the CAN logic level receive traffic from the local physical layer CAN transceiver on the NXP Command Module Position 2 3 allows this pin to be used as a second 12C channel 2 GENO PO 2 TXDO ADO 7 JP439 2 1 Default ASCO TX TTL JP439 2 4 JP439 2 3 AN15 Position 2 1 is the main RS232 UART channel Outgoing logic level transmit traffic is routed to the Communication Module where it is translated into RS232 RS485 logic levels PO 3 RXDO ADO 6 1 440 2 1 Default ASCO TTL JP440 2 4 JP440 2 3 AN14 P
21. osition 2 1 is the main RS232 UART channel Incoming logic level receive traffic is routed from the Communication Module PO 4 I2SRX_CLK RD2 CAP2 0 Electrocomponents plc Page 15 EDP CM LPC1768 CPU Module JP438 2 1 Default PO 5 I2SRX WS TD2 CAP2 1 P437 2 3 JP437 2 1 Default JP437 2 4 PO 10 TXD2 SDA2 MAT3 O0 JP421 2 1 Default 1 421 2 3 JP422 2 1 Default 1 422 2 3 JP436 2 3 JP436 2 1 Default GPIO10 MCI CLK y y 2 HB HB 3 55 o 2 lt lt a gt 5 NJ Pp lt gt 59 PO 20 DTR1 SCL1 JP435 2 3 JP435 2 1 Default GPIO12 MCI CMD PO 21 RI1 RD1 JP434 2 3 JP434 2 1 Default GPIO14 MCI PWR PO 22 RTS1 TD1 JP433 2 3 JP433 2 1 Default GPIO2 MCI DATO 23 00 0 1258 0 403 2 1 Default ANO 403 2 3 AN8 PO 24 ADO 1 I2SRX WS CAP3 1 1 402 2 1 Default AN1 1 402 2 3 9 25 00 2 1258 SDA TXD3 JP401 2 1 Default AN2 401 2 3 AN10 PO 26 ADO 3 AOUT RXD3 1 408 2 1 Default 1 408 2 4 AN11 408 2 3 CPU DACOO GPIO17 Electrocomponents plc Page 16 EDP CM LPC1768 CPU Module Port P1 Options P1 18 USB UP LED PWM1 1 CAP1 O0 JP407 2 1 Default 1 407 2 3 1 407 2 4 P1 19 MCOA USB PPWR CAP1 1 1 409 2 1 JP409 2 3 Default P1 20 MCF
22. rs The software assumes you have an MC2 motor drive module fitted and you want to communicate to it via I2C packets This set of software therefore allows you communicate with the MC2 motor drive module across the 2 backplane network present in the RSEDP system You can have up to three MC2 motor drives fitted and this suite of software allows you to communicate with all of them 5 4 Easy Web This piece of software allows the NXP processor to serve a web page via its on board Ethernet port The software allows you to effectively test the Ethernet port is working correctly The software was written by Andreas Dannenberg at the University of Applied Science in Germany and has been modified to work on the RSEDP platform By using these suites of software you can fully exercise the RS EDP platform to ensure all of the items are working correctly You can also use the software as building blocks for your own projects Electrocomponents plc Page 20 1 2 4 5 6 7 8 Module Position 1 EDPCONI IO Connector 3V3 R101 AN REF OR ANS ANIO ANI2 ANI3 wins ANIA ANIS SGND m VAGND VAGND GPIOO GPIOI VAGND GPIO2 MCIDATO GPIO3 GPIO4 MCIDATI GPIOS DSTX WS EDPCON2 Bus Control Connector GPIO6 MCIDAT2 GPIO7 DSRX CLK GPIO8 MCIDAT3 GPIO9 DSRX WS GPIO10 MCICLK GPIO11 DSRX SDA P102 GPIO12 MCIC
23. ugged in to the Base Board BB These NXP modules have been designed as the Command Module for the system The Module in a system dictates whether the whole system is a 3 3V one or a 5 0V All of these modules use a 3 3V microprocessor and consequently the I O is mostly 3 3V also To tell the rest of the system the Command Module is a 3 3V one not a 5 0V one the Vcc CM line on the base board is connected to 3 3V by the tracking on the Command Module board This Vcc CM is used as a reference by the other modules such as the analogue module to limit the output voltage to 3 3V The command voltage line is also used by the HRESET circuit as the voltage reference to pull up to after the reset line has been asserted low The RS EDP CM NXP module maps the I O of the MCU on the board to the backplane of the RS EDP system As there are quite a few dual function pins on the NXP processors and hence several link options have been made to accommodate the various options the user may wish to use Extensive use of the I2C capability is used to communicate to the application modules in the system 2 MCU Mapping 2 1 MCU Pin Allocation The MCU pins have been connected to the backplane via the following configuration RS EDP BASE BOARD LPC1768BDM100 Comment mapping TD SWO 2o m JmAGiefaeontPCmodue 3 TMSSWDO JTAGiefaceontPCmodue 4 JTAGiefaeontPCmodue
24. ule R5 115 200 baud 8 data bits no stop bit no parity No flow control The default jumper options for JP439 and JP430 should be left in place to ensure serial traffic is routed to the communication module Always check the software to see if the baud rate has been changed Some of the provided software includes 5 1 RSEDP Test Suite This software exercises the NXP LPC1768 MCU peripherals including the on board ADC PWM output input capture I2C CAN and 1 0 The software also allows you to exercise the basic Application Modules which are the Communication Module the Digital I O Module and the Analogue Module A suite of drivers and test menus are provided to fully exercise all the hardware on these boards 5 2 MC1 Test Suite This is similar to the RSEDP Test Suite but the test menus provided are for the MC1 Brushed DC Motor Drive Application Module The motors are nominally 12V brushed DC motors running in a full H bridge configuration The test suite allows you to accelerate the motor change its direction turn the brake on and off as well as allowing the monitoring of motor current DC link voltage and tacho feedback signals The MC1 motor drive module also has many external inputs for limit switch detection and conditioning of motor related stimuli The provided software library will therefore allow you to fully exercise your motor 5 3 MC2 Test Suite This is similar to the test suite but for brushless DC AC moto
25. ule R5 P1 1 ENET TXD1 Ethernernet PHY chip P1 0 ENET_TXDO Ethernernet PHY chip Vdd 3V3 98 PO 2 TXDO ADO 7 3 Link options ASCO TX TTL 3 link options TF 99 7 S Link options ASco Rx TTL po Bink options pf 1 0 O 2 2 Resources Used Available by the LPC1768 The following resources are available to be used by the MCU Resources Used Available Electrocomponents plc Page 6 EDP CM LPC1768 CPU Module CNTRL SPI MTSR Electrocomponents plc Page 7 EDP CM LPC1768 CPU Module 2 3 Alphabetical Listing of MCU pins Alphabetic Listing of Available I O HRESET HRSTOUT 17 14 4 13 46 47 81 79 78 77 76 48 49 62 63 61 59 58 57 56 7 25 24 29 30 95 94 93 92 91 88 87 32 33 34 35 36 37 38 39 40 43 44 Electrocomponents plc Page 8 EDP CM LPC1768 CPU Module 45 P1 29 MC2B PCAP1 1 MATO 1 P1 31 SCK1 ADO 5 70 5 6 6 5 5 5 8 8 100 TCK SWDCLK TMS SWDIO 19 28 54 71 84 Vdd reg 3V3 10 Vdda VREFN VREFP 5 4 3 0 27 26 5 2 1 2 16 18 2 1 55 55 55 55 55 15 12 31 41 55 72 83 2 4 Backplane Signal Names and Connections Break Out Base Board Signal Name EDPCON1 EDPCON2 Connector 5486 6 1 588
26. v B Ethernet SchDoc Author A Davison 3 4 5 6 8 30 Q mam BEE 80 00 ES o DO NEN JP440 JP404 E ERE ES HEH JP405 Ea R303 R301 E HH R302 R304 P101 g m_i nee 4 R207 1 LO e O JP425 JP426 JP427 5 R505 1
27. ware drivers to make driving of the platform very easy the low level support for the devices controlled by I2C for example have been written as well as a test menu to exercise each of the modules independently of the others This therefore provides working example of the code which will allow students and users to cut and paste various sections into their own applications Each Applications Module has its own header file which provides the support for the functions that control it Each module has its own set of high level functions that can be called to operate and control the hardware This makes life a lot easier for the user who can then spend most of his time working at the higher level application layer The software has been packed up as several ZIP file which can be downloaded and unpacked Most of the projects have been written for the Keil uVision environment The majority of the applications written use the serial comm channel ASCO for outputting data to a terminal emulator With this in mind a serial terminal emulation program should be used to read traffic outputted from the RS EDP platform Hyper Terminal is included in windows as part of the Windows Operating system but this does not work reliability With this in mind it may be worth looking at other terminal emulator especially if they are to be used with USB RS232 converters The terminal emulator should be set up for Electrocomponents plc Page 19 EDP CM LPC1768 CPU Mod
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