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USER`S MANUAL

1. 3 9 3 10 Direct Addressing for Load Instructions I 3 10 3 11 Direct Addressing for Call and Jump Instructions 3 11 3 12 Indirect Addressing erc Ee E E 3 12 3 13 Relativec Addressing yt usnu m rn aeri dar ob tpa ie IER nap 3 13 3 14 Immediate entente nnns nnns enne 3 14 4 1 Register Description Format nnne nnn nnne 4 3 S3F80N8 MICROCONTROLLER xi List of Figures continued Figure Title Page Number Number 5 1 SSF8 Series Interrupt 4 na anaa 5 2 5 2 8 8 Interrupt Structure esses eene entente nns 5 3 5 3 ROM Vector AddressS Area cte nite e te er etae 5 4 5 4 interrupt Function DIagrar eerte te tete tee tn eee ES 5 6 5 5 System Mode Register SYM u 5 8 5 6 Interrupt Mask Register enne 5 9 5 7 Interrupt Request Priority Groups sse 5 10 5 8 Interrupt Priority Register IPR ua usapu s nnn 5 11 5 9 Interrupt Request Register 1 5 12 6 1 System Flags Register FLAGS u 6 6 7 1 Crystal Ceramic Oscillat
2. 11 1 Chapter 12 Electrical Data PC EE 12 1 Chapter 13 Mechanical Data tail hl a ridge Rede ete tas 13 1 Chapter 14 S3F80N8 Flash MCU ten obse 14 1 On Bodrd WEUnDgo s m ud a LA ML mi ce mt us 14 3 Chapter 15 Development Tools COVER VIC Weer eet uy LI M TE 15 1 Target Boards c eta mo Ee Sen Eo D es 15 1 Programming Socket Adapter U 15 1 TB80N8 Target Board tol De E S EDU eat GM e ig des rd en OA ROM NIE 15 3 OTP MTP Programmer Wiriter nn 15 8 x S3F80N8 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 Block Diagram niet hg tiet di bere he ie nh 1 3 1 2 S3F80N8 Pin Assignments 32 pin SOP SDIP senes 1 4 1 3 S3F80N8 Pin Assignments 28 pin SOP a 1 4 1 4 Pin Circuit Type Aiii ei itera ie te e a uu e e o ees 1 6 1 5 Pin Circuit TY pe B eite e eere tee et be e e E ee E D te bean 1 6 1 6 Pin Circuit Type Quiere re etel eu e eter 1 7 2 1 Program Memory Address Space seen 2 2 2 2 iuri ATTI 2 3 2 3 meme E LL 2 4 2 4 8 Byte Working Register Areas Slices 2 5 2 5 Contiguous 16 Byte Working Register Block
3. S3F80N8 32 SOP SDIP S3F80N8 S3F80N8 UM_REV1 10 Vpp P1 0 INT0 SCLK P1 1 INT1 SDAT P1 2 INT2 P1 3 INT3 P1 4 INT4 P1 5 INT5 P1 6 INT6 P1 7 INT7 P2 0 P2 1 P2 2 CLO P2 3 TOCLK S3F80N8 Pin Assignments 32 pin SOP SDIP VDD O INTO SCLK A INT1 SDAT 2 INT2 3 INT3 A INT4 5 INT5 6 INT6 7 INT7 P2 0 P2 1 P2 2 CLO P2 3 TOCLK P2 4 T0 Figure 1 3 S3F80N8 Pin Assignments 28 SOP ELECTRONICS S3F80N8 UM_REV1 10 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1 1 S3F80N8 Pin Descriptions 32 pin ELECTRONICS Pin Pin Circuit Names Type Pin Description Type PN Shared pins P0 0 P0 7 lO I O port with bit programmable pins Configurable to input or open drain push pull output mode Pull up resistors can be assigned by software P1 0 lO I O port with bit programmable pins INT0 SCLK P1 1 Configurable to input or open drain INT1 SDAT push pull output mode Pull up resistors 1 2 P1 7 can assigned software can INT2 INT7 also be assigned individually as external interrupt pins P2 0 lO I O port with bit programmable pins 14 19 2 1 Configurable to input or open drain push pull output mode Pull up resistors P2 2 can be assigned by software Pins can CLO P2 3 also be assigned individually as TOCK P24 alternative function pins TO P2 5 P3 0 P3 3 lO I O port with bit programmable pins 15 18 Configurable to
4. a 9 10 9 12 Port Control Register 9 11 9 13 Port 3 Pull up Control Register P3PUR aa 9 12 10 1 Basic Timer Control Register 10 2 10 2 Oscillation Stabilization Time on RESET senes 10 4 10 3 Oscillation Stabilization Time on STOP Mode 10 5 10 4 Basic Timer Block Diagram enne 10 6 10 5 Timer 0 Control Register T0CONJ aa 10 8 10 6 Simplified Timer 0 Function Diagram Interval Timer Mode 10 9 10 7 Simplified Timer 0 Function Diagram PWM 10 10 10 8 Simplified Timer 0 Function Diagram Capture 10 11 10 9 Timer Block Diagram E e M RR E i RA 10 12 xii S3F80N8 MICROCONTROLLER List of Figures continued Figure Title Page Number Number 11 1 Low Voltage Reset CIrCUiL Bett tete ori Erit iR cre aea 11 2 12 1 Stop Mode Release Timing When Initiated by External Interrupt 12 4 12 2 Stop Mode Release Timing When Initiated by 12
5. sse 12 5 RC Oscillation Mode2 Characteristics 12 7 Oscillation Stabilization n nsn 12 7 Input Low Width Electrical Characteristics 12 8 LVR Circuit Characteristics 12 8 ESD Characteristics 2 ded e e d p reed e uet edo mie 12 9 Descriptions of Pins Used to Read Write the Flash ROM 14 2 Components of TB80N8 n 15 4 Setting of the Jumper in TB80N8 15 5 XV List of Programming Tips Description Page Number Chapter 2 Address Spaces Setting RegisterPOInters eee ete etu ott etc deett 2 6 Using RPs to Caculate the Sums of a series of 2 7 Addressing the Common Working Register Area esee 2 11 Standard Stack Operations Using PUSH and POP L 2 16 S3F80N8 MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number BTCON Basic Timer Control Register sess 4 4 CLKCON Glock Control Register u u riri eet eor d 4 5 EXTINT External Interrupt Enable 4 6 EXTPND External Interrupt Enable Register
6. register Ewemalineruprenabieregster extwT Rw 235 Em o of of o of of External interrupt pending register nw 236 o o of Location EDH is not mapped For 2eonroriegeer gne Peconn ee T T T a ofofo zem reser wr Pecon nw es ern fof el of of of of Port 2 pull up resistor m P2PUR R W FOH register Locations F1H is not mapped Pon Scontolregster Pacon aw ee ojojo 0 0 0 0 Port 3 pull up resistor enable P3PUR R W 243 F3H 1111 register Locations F4H FAH are not mapped STOP STOPcoN nw 21 re o o o o o o o o Location FCH is not mapped Basic timer counter register BTCNT R 253 o o ojo ojojo o m Location FEH is not mapped m aw ss re NOTES 1 The reset value of P2 5 setting is open drain output 2 reset value of P3PUR is OFH this value enables the pull up resistor 4 2 ELECTRONICS S3F80N8 UM_REV1 10 Bit number s that is are appended to the register name for bit addressing Register ID CONTROL REGISTER Name of individual bit or related bits Register address Register name hexadecimal FLAGS System Flags Register D5H Bit Identifier RESET Value Read Write Bit Addressing Mode oz s 5 4 3 2 o x x x x x x gt 0 R W R W R W R W R W R W R W R W Register addres
7. aaa 6 84 Test nder Mask deiecit aW a e et ctn e aee tel ede dee 6 85 Wait a ne deeds egeta a vee aa ug eco ra eee 6 86 Logical Exclusive OB uuu sto eid dde da d 6 87 S3F80N8 MICROCONTROLLER S3F80N8 UM_REV1 10 PRODUCT OVERVIEW PRODUCT OVERVIEW S3F8 SERIES MICROCONTROLLERS Samsung s S3F8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various flash programmable ROM sizes Important CPU features include Efficient register oriented architecture Selectable CPU clock sources idle and Stop power down mode released by interrupt Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3F80N8 MICROCONTROLLER The S3F80N8 single chip CMOS micro controller is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture Its design is based on the powerful SAM8RC CPU core Stop and idle power down modes were implemented to reduce power consumption The S3F80N8 is a micro controller with a 8K byte multi time programmable Flash ROM embedded Using a proven modular design approach Samsung enginee
8. nw fofofo Port 2 pull up resistor E P2PUR R W FOH register Locations F1H is not mapped PortScontoiregster Pacon aw ze re Port 3 pull up resistor enable P3PUR R W 243 F3H 1111 register Locations F4H FAH are not mapped STOP contoivegiter stoPcon Rw Fea o o 0 o 0 e o Location FCH is not mapped Basio timer counter register BTCNT R 253 o o ojo oj oj of o s Location FEH is not mappe Interrupt priority register RW 255 FFH x x x x x x x x 8 4 ELECTRONICS S3F80N8 UM_REV1 10 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted except the IVC Interval Voltage Converter module That is the on chip oscillator for system clock stops and the supply current is reduced to about 2 5 uA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by external interrupts NOTE Do not use stop mode if you are using an external clock source because X input must be restricted internally to Vss to reduce current leakage Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level all system and peripheral co
9. a e 8 1 LM te 8 1 Normal Mode Reset Operation U eene enne n a nns 8 3 Flardware Reset Values sende tei ner goad ix eroi pad i UT E E RE MEO Eines 8 3 Power DownrMOode s L in det o ES RED Acn d ecu qe ER OE 8 5 SOP EE EE 8 5 11 MOGE EE 8 6 Chapter 9 Ports TM s E 9 1 Port Data Registers ii oso en pee I p nera De S ede reed 9 2 DOO etos Lotte s esce eeiam o ccs hd e tear duce M UR C Hune tL c 9 3 EE 9 5 Port 2 ka Mol eris i AM E 9 9 Port3 32 pin S9EBONGS etiam teo te rd intret ted e ha aao aaa ttd 9 11 Chapter 10 Basic Timer and Timer 0 E eh e E 10 1 Basic Timer BT nieder Ete ca Rei eerie eee eee g 10 1 Basic Timer Control Register BTCON n nennen sassa 10 2 Basic Timer Function Description 10 3 8 bit Timer Counter sau aaa rtt sired He o bad He eet ieee ene 10 7 Timer Counter 0 Control Register T0CON ener nennen nne nnne nennen sinn 10 7 Timer 0 Function Description isere laora adie n etadi a a ie e a aN a a E 10 9 S3F80N8 MICROCONTROLLER Table of Contents Continued Chapter 11 Low Voltage Reset OLETA
10. contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H 04H LDC nete 01H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC R0 1000H RR2 lt contents of program memory location 1104H 1000H 0104H 88H R2 01H 04H LDE RO0 1000H RR2 contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H LDC R0 1104H lt contents of program memory location 1104H 88H LDE R0 1104H lt contents of external data memory location 1104H 98H LDC note 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3F80N8 UM REV1 10 LDCD LDED Load Memory and Decrement LDCD LDED dst src Operation Flags Format Examples dst src rr 17 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded int
11. o o om 5 mw Figure 10 3 Oscillation Stabilization Time on STOP Mode Release ELECTRONICS 10 5 BASIC TIMER and TIMER 0 S3F80N8 UM_REV1 10 RESET or STOP Bits 3 2 v Basic Timer Control Register Data Bus Write 1010xxxxB to disable Clear 1 4096 Y 8 Bit Up Counter in BTCNT Read Only Start the CPU NOTE NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until BTCNT 4 is set Figure 10 4 Basic Timer Block Diagram 10 6 ELECTRONICS S3F80N8 UM_REV1 10 BASIC TIMER and TIMER 0 8 BIT TIMER COUNTER 0 Timer counter 0 has three operating modes one of which you select using the appropriate TOCON setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P2 4 pin PWM mode Timer counter 0 has the following functional components Clock frequency divider fosc divided by 4096 256 8 or external clock P2 3 T0CK with multiplexer 8 bit counter TOCNT 8 bit comparator and 8 bit reference data register TODATA I O pins for capture input or PWM output P2 4 TOCAP TOPWM Timer 0 overflow interrupt IRQ2 vector EAH and match capture interrupt IRQ2 vector ECH generation Timer 0 control register TOCON D2H read write TIMER COUNTER 0 CONTROL REGISTER TOCON You use the timer 0 control register TOCON to Select the timer 0 operating mode interval timer capture mode
12. 2 6 2 6 Non Contiguous 16 Byte Working Register Block 2 7 2 7 16 Bit HRegister Pall di ce E ed a ce RARE RR 2 8 2 8 Register File Addressing U entente nent 2 9 2 9 Common Working Register Area U nnns 2 10 2 10 4 Bit Working Register Addressing 2 12 2 11 4 Bit Working Register Addressing Example sese 2 12 2 12 8 Bit Working Register Addressing sse 2 13 2 13 8 Bit Working Register Addressing Example 2 14 2 14 Stack Operallohs 2 15 3 1 Register ACCreSSING uu uu u u u GS 3 2 3 2 Working Register Addressing sse nennen nnns 3 2 3 3 Indirect Register Addressing to Register 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register File 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data
13. u en 4 7 FLAGS System Flags Register nnne 4 8 IMR Interrupt Mask ideia 4 9 IPH Instruction Pointer High Byte 4 10 IPL Instruction Pointer Low Byte 1 nennen 4 10 IPR Interrupt Priority sus ai ia 4 11 IRQ Interrupt Request Register 4 12 POCONH Port 0 Control Register High Byte 4 13 POCONL Port 0 Control Register Low Byte a 4 14 POPUR Port O Pull Up Register meesi ineat fierce ete eee epe eat 4 15 P1CONH Port 1 Control Register o eene aane aan 4 16 P1CONL Port 1 Control Register cid tg a eiue ga ens 4 17 P1PUR Port 1 Pulp Register eicere rate ioo ete dea 4 18 P2CONH Port 2 Control Register High Byte sse 4 19 P2CONL Port 2 Control Register Low Byte nennen 4 20 P2PUR Port 2 PullUp Reglster uu uu iiid ie ae ee 4 21 P3CON Port 3 Control Registe i u z a naa tp gi eic Ete ae aee 4 22 P3PUR Port 2 PullUp Beglister uuu tior td lette 4 23 PP Register Page PoIntel ua eens aie ne eee dete AE 4 24 RP0 Register Pointer ecc 4 25 RP1 Register Pointer a ea Ace cea i AE 4 25 SPL Stack Poi
14. as the active 16 byte working register block COH C7H RP1 8 This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH NOTE In the S8F80N8 microcontrolle only Page 0 is implemented Figure 2 9 Common Working Register Area 2 10 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESS SPACES 9 PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Use working register addressing instead SRP 0C0H LD R2 40H R2 2 lt the value in location 40H Invalid addressing mode 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0 ADD R3 45H lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working r
15. PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value 0000H and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR lt IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given Register 00H 03H register 01H 05H and register 02H 1AH PUSHUD 00H 01H Register OOH 02H register 01H 05H register 02H 05H If the user stack pointer register for example contains the value 03H the statement PUSHUD 00 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 6
16. 01H R1 register 02H 02H LO LD R0 10H gt LD R0 01H gt LD 01H RO gt LD R1 RO gt LD RO R1 gt LD 00H 01H gt LD 02H 00H gt LD 00H 0AH gt LD 00H 10H gt LD 00H 02H gt LD RO LOOP R1 gt LD LOOP RO R1 gt Uo S3F80N8 UM REV1 10 AH register 01H register 20H 30H and register 3AH OFFH RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 register 01H Register 00H 20H register 01H 20H Register 02H 20H register 00H 01H Register OOH OAH Register OOH 01H register 01H 10H Register 01H register 01H 02 register 02H 02H RO OFFH R1 0AH Register 31H OAH 01H R1 OAH ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb ro NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit
17. ELECTRONICS 6 57 INSTRUCTION SET S3F80N8 UM REV1 10 L DW Load Word LDW Operation Flags Format Examples dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR C5 RR IR dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register 00H 1AH register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register 00H 03H register 01H OFH register 02H 03H register R2 03H R3 OFH Register 04H 03H register 05H R6 12H R7 34H Register 02H OFH register OEDH LDW RR2 R7 LDW 04H 01H LDW RR6 1234H LDW 02H 0FEDH 0FH fy In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register OOH and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3F80N8 UM_REV1 10 MULT Multiply Unsigned MULT Operation Flags Format Examples dst src dst lt dst x src The 8 bit destination operand even register of the register p
18. Format Example PC SP SP lt SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 8 internal stack AF 10 internal stack Given SP 00FCH SP 101AH and PC 1234 RET gt 101AH SP 00FEH The statement RET pops the contents of stack pointer location 00FCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if
19. No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BITR R11 o R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET BITS Bit set BITS Operation Flags Format Example dst b dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R13 gt R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3F80N8 UM REV1 10 BOR BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 OR src b or dst b dst b OR src 0 The specified bit of the source or the destination is logically ORe
20. S3F80N8 UM REV1 10 ELECTRONICS S3F80N8 UM_REV1 10 ELECTRICAL DATA Table 12 3 Current Characteristics 40 to 85 C Vpp 2 0 V to 5 5 V Supply Ipp4 Run mode 10 MHz 5 0 10 0 Current 1 Vpp 5 V 10 Crystal oscillator 4 195 MHz 3 5 7 0 C1 C2 22pF Vpp 5 V 10 Crystal oscillator C1 C2 22pF os 32 Vpp 2 0 5 5 V LVR disable Vpp 2 0 5 5 V 35 70 NOTES 1 Supply current does not include current drawn through internal pull up resistors 2 l ppgis current when system clock oscillation stops mA ELECTRONICS 12 3 ELECTRICAL DATA S3F80N8 UM_REV1 10 Table 12 4 Data Retention Supply Voltage in Stop Mode TA 40 C to 85 C Data retention supply current IpppR Vpppn 1 2 V TA 25 Stop mode Oscillation Stabilization Time 31 Stop Mode PES SEM Idle Mode lt Data Retention A Execution of STOP Instruction Normal Operating Mode Interrupt NOTE twarr is the same as 16 x 1 BT clock Figure 12 1 Stop Mode Release Timing When Initiated by External Interrupt RESET Occurs Oscillation Stabilization lt Stop Mode gt lt Time Normal lt Data Retention Mode gt Operating Mode 5 Execution of STOP Instrction nRESET NOTE is the same as 4096 x 16 x 1 fxx Figure 12 2 Stop Mode Release Timing When Ini
21. 02H XOR RO R1 gt RO OE4H R1 02H register 02H 23H XOR 00H 01H gt Register 00H 29H register 01H 02H gt gt XOR 00H 01H Register 00H 08H register 01H 02H register 02H 23H XOR 00H 54H Register 00H 7FH In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 INSTRUCTION SET S3F80N8_UM_REV1 10 NOTES 6 88 ELECTRONICS S3F80N8 UM_REV1 10 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The S3F80N8 microcontroller CPU and peripheral hardware operate on the system clock frequency supplied through the clock circuit The maximum CPU clock frequency of S3F80N8 is determined by CLKCON register settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal ceramic resonator RC oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON STOP control register STOPCON ELECTRONICS 7 1 CLOCK CIRCUIT MAIN OSCILLATOR CIRCUITS XIN XOUT Figure 7 1 Crystal Ceramic Oscillator fosc Vcc XOUT XIN Figure 7 3 RC Oscillator MODE 2 fosc S3F80N8_UM_REV1 10 XIN XOUT Figure 7 2 External
22. 02H and R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 0AH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET CPIJE CPIJE Operation Flags Format Example Compare Increment and Jump on Equal dst src RA If dst src 0 lt PC RA Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex ds
23. 11 IRQ1 Request Pending ot pending x ending 0 Lev I 0 IRQ0 Request Pending Not pending B Pending 4 12 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER Port 0 Control Register High Byte E4H Bit Identifier Reset Value Read Write Addressing Mode 7 6 3 2 ELECTRONICS _ 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P0 7 Configuration Bits 0 0 Nomainot 0 1 Outputmode push pull o O 1 0 Outputmode open drain O P0 6 Configuration Bits o o Nmamu o i ovpu mose prp ie jowwmoeopndan P0 5 Configuration Bits o o Nmamu Fo ovpu mode pp ie owmwmoeopendan P0 4 Configuration Bits 0 0 Nomainot 0 1 jOupumodepushpul I 1 0 JOuputmodeopemdrin 4 13 CONTROL REGISTERS S3F80N8 UM_REV1 10 POCONL Port 0 Control Register Low Byte E5H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 Configuration Bits 0 0 Nomainot 0 1 Outputmoae push pull I I 1 0 Outputmode open drain 5 4 P0 2 Configuration Bits o o Nmamu o i ouput mode prp 3 2 P0 1 Configuration Bits o o Nmamu
24. All system and peripheral control registers are then reset to their default hardware values The on chip Low Voltage Reset features static Reset when supply voltage is below a reference value Typ 2 2V 3 9 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference value When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop and normal RUN mode ELECTRONICS 8 1 RESET and POWER DOWN S3F80N8 UM_REV1 10 Watchdog RESET Internal System RESETB Comparator When the Vpn level is lower than VuvR Smart Option 3EH 5 3EH 6 NOTES 1 The target of voltage detection level is the one you selected at smart option 3EH 2 IVR is Internal voltage Reference Figure 8 1 Low Voltage Reset Circuit In summary the following sequence of events occurs during a reset operation 8 2 All interrupt is disabled The watchdog function basic timer is enabled Ports 0 3 are set to input mode P2 5 is open drain output mode and pull up resistors of PO P1 and P2 are disabled for the I O port but pull up resistors of are enabled for the I O port Peripheral control and data register settings are d
25. NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address rr and the source address XL rr are each two bytes 4 The DA andr source values for formats 7 and 8 are used to address program memory the second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC RO OGRR2 lt contents of program memory location 0104H RO R2 01H 04H LDE RO OGRR2 lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H LDC nete ogRR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R8 no change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers R2 R8 no change LDC R0 201H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H 04H LDE R0 01H RR2
26. O O O O O Bits 0 3 Value Hex 0 9 0 3 0 9 0 3 0 9 0 3 0 9 6 0 9 6 Number Added to Byte 00 06 06 60 66 66 60 66 66 00 00 06 60 9A 66 Set if there was from the most significant bit cleared otherwise see table Set if result is 0 cleared otherwise Setif result bit 7 is set cleared otherwise Unaffected Unaffected Format 2 5 V Undefined D H ELECTRONICS dst Bytes 2 Cycles 4 Opcode Hex 40 41 Carry After DA a Addr Mode dst R IR 6 33 INSTRUCTION SET S3F80N8 UM REV1 10 DA Decimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO C lt H lt 0 Bits 4 7 3 bits 0 3 C lt 3CH DA R1 R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 2
27. R3 lt Stack address HP1 Stack address RP0 Stack address OFDH PP Stack address ELECTRONICS S3F80N8 UM_REV1 10 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3F series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3F80N8 UM_REV1 10 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 3 2 Program Memory Register File 8 b
28. high order bits LM MEME d Together they create an 8 bit register address Figure 2 10 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register Instructi 01110 address 0110 1110 INCRE 76H Figure 2 11 4 Bit Working Register Addressing Example 2 12 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESS SPACES 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 12 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RP0 or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 13 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of 8 bit instruction ad
29. opc 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 04H CPIJNER1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F80N8 UM_REV1 10 DA Decimal Adjust DA dst Operation dst DA dst Instruction Carry Before DA 0 0 0 ADD 0 ADC 0 0 1 1 1 0 SUB 0 SBC 1 1 Flags C INSTRUCTION SET The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Bits 4 7 Value Hex 0 9 0 8 0 9 9 0 2 0 2 0 3 0 9 0 8 7 6 H Flag Before DA O
30. or PWM mode Select the timer 0 input clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 overflow interrupt or timer 0 match capture interrupt Clear timer 0 match capture interrupt pending condition ELECTRONICS 10 7 BASIC TIMER and TIMER 0 S3F80N8 UM_REV1 10 TOCON is located at address D2H and is read write addressable using Register addressing mode A reset clears TOCON to 00H This sets timer 0 to normal interval timer mode selects an input clock frequency of fogc 4096 and disables timer 0 interrupt You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 The timer 0 overflow interrupt TOOVF is interrupt level IRQ2 and has the vector address EAH When a timer 0 overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer 0 match capture interrupt IRQ2 vector ECH you must write TOCON 1 to 1 To detect a match capture interrupt pending condition the application program polls TOCON 0 When 1 is detected a timer 0 match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a 0 to the timer 0 match capture interrupt pending bit TOCON O Timer 0 Control Register TOCON D2H R W Timer 0 input clock selection bits Timer 0 match interrupt pending bit 00 fosc 4096 0 No interrupt pending W
31. register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110001B the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3F80N8 UM REV1 10 RRC Rotate Right Through Carry RRC Operation dst dst 7 C C lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R C1 IR Given Register 00H 55H register 01H 02H register 02H 17H and C 0 RRC OOH gt Register 00H 2AH C 1 01H gt Register 01H 02H register 02H 0BH C 1 In the first
32. the basic timer counter value is cleared to Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to OOH Immediately following the write operation the BTCON O value is automatically cleared to 0 4 4 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER System Clock Control Register D4H Reset Value _ _ _ 0 0 _ _ _ Read Write _ _ _ R W R W _ _ _ Addressing Mode Register addressing mode only 7 5 Not used for the S3F80N8 4 3 CPU Clock System Clock Selection Bits note 2 0 Not used for the S3F80N8 NOTE After a reset the clock not divided is selected as the system clock To select other clock speeds load the appropriate values to CLKCON 4 and CLKCON 3 ELECTRONICS 4 5 CONTROL REGISTERS S3F80N8 UM_REV1 10 EXTINT External Interrupt Enable Register EB Bit Identifier 27 6 5 4 3 2 o 0 0 0 0 0 0 0 Reset Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 INT7 External Interrupt Enable Bit INT7 interrupt disable INT7 interrupt enable 6 P1 6 INT6 External Interrupt Enable INT6 interrupt disable INT6 interrupt enable B 5 P1 5 INT5 External Interrupt Enable Bit NT5 interrupt disable NT5 interrupt enable 1 4 P1 4 INT4 External
33. 10 OTP MTP PROGRAMMER WRITER Continued DEVELOPMENT TOOLS US pro Portable Samsung OTP MTP FLASH Programmer e Portable Samsung OTP MTP FLASH Programmer e Small size and Light for the portable use e Support allof SAMSUNG OTP MTP FLASH devices e Convenient USB connection to any IBM compatible PC or Laptop computers e Operated by USB power of PC e PC based menu drive software for simple operation e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Support Samsung standard Hex or Intel Hex format e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Support Firmware upgrade SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com GW uni Gang Programmer for OTP MTP FLASH MCU e 8 devices programming at one time e Fast programming speed 1 2Kbyte sec e PC based control operation mode or Stand alone e Full Function regarding OTP MTP program Read Program Verify Protection Blank e Data back up even at power break After setup in Design Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Flash writing adapter board e Special flash writing socket only for S3F
34. CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET XOR Logical Exclusive OR XOR dst src Operation dst dst XOR src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 r Ir src dst 3 6 B4 R R B5 R IR dst src 3 6 B6 R IM Examples Given RO 0C7H R1 02H R2 18H register 2BH register 01H 02H and register 02H 23H XOR RO R1 gt RO OC5H
35. Enable unmask 1 Interrupt Level 1 IRQ1 Disable mask Enable unmask 0 Inte rupt Level 0 IRQ0 Disable mask 1 Enable unmask NOTE When an interrupt level is masked the CPU does not recognize any interrupt requests that may be issued D ELECTRONICS 4 CONTROL REGISTERS S3F80N8 UM_REV1 10 IPH instruction Pointer High Byte DAH Bit Identifier 27 6 5 4 3 o x x x x x x x x Reset Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 1P8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 10 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER IPR Interrupt Priority Register FFH Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for In
36. Immediate addressing mode Immediate long addressing mode ELECTRONICS Actual Operand Range See list of condition codes in Table 6 6 Rn n 0 15 Rn b n 0 15 b 0 7 Rn n 2 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where p 0 2 14 addr addr 0 254 even number only n 0 15 Rn or reg 0 255 n 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where p 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where p 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTRUCTION SET S3F80N8 UM REV1 10 Table 6 5 Opcode Quick Reference OPCODE MAP LT TG a 3 DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM ro Rb POP POP AND AND AND AND AND BITC R
37. MICROCONTROLLER List of Tables Title Page Number KS86C0004 Pin Descriptions 1 5 S3F80N8 Register Type Summary n u 2 4 p 4 1 Interrupt Control Register Overview nennen 5 5 Interrupt Source Control and Data 5 7 Instruction Group Summary sse L nnne nens 6 2 Flag Notation Conventions U nennen nnns nnne nens 6 8 Instruction Set Symbols sse entente 6 8 Instruction Notation Conventions enne nens 6 9 Opcode Quick Reference sss esent 6 10 Condition Codes ative eee 6 12 S3F80N8 Register and Values after 8 3 S3F80N8 Port Configuration Overview 9 1 Port Data Register Summasry I eene nennen enne 9 2 Absolute Maximum 0 eene nennen nnne en 12 1 DC Electrical Characteristics L a 12 2 Current 12 3 Data Retention Supply Voltage in Stop 12 4 Input output Capacitance U n nana 12 5 System Oscillation Characteristics
38. Opcode Hex Normal opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast 1 6 In the figure below the instruction pointer is initially loaded with 100 in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The un
39. R1 12H R2 03H register 01H 21H register 02H 03H register O3H OAH AND RI R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 03H gt gt AND 01H 02H Register 01H 00H register 02H 03H AND 01H 25H Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Giv
40. Reset features static reset when supply voltage is below a reference voltage value Typical 2 2 3 9 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 11 1 LOW VOLTAGE RESET S3F80N8 UM_REV1 10 Watchdog nRESET nRESET Internal System nRESET When the VDD level is Lower than 2 2 3 9V J NOTES 1 The target of voltage detection level is 2 2 3 9V at VDD 5V 2 IVR is the Internal voltage Reference Figure 11 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 11 2 ELECTRONICS S3F80N8 UM_REV1 10 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter S3F80N8 electrical characteristics are presented in tables and graphs The
41. S W External interrupt 1 S W External interrupt 0 S W Timer 0 match capture interrupt S W EAH TT Timer 0 overflow interrupt H W NOTE External interrupts are triggered by falling edge or both rising edge and falling edge Figure 5 2 S3F80NG8 Interrupt Structure ELECTRONICS 5 3 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 Interrupt Vector Addresses All interrupt vector addresses for the S3F80N8 interrupt structure is stored in the vector address area of the first 256 bytes of the program memory ROM You can allocate unused locations in the vector address area as normal program memory lf you do so please be careful not to overwrite any of the stored vector addresses The program reset address in the ROM is 0100H Decimal 8191 8K byte Program Memory Area 100H lt Reset FFH Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area 5 4 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE Enable Disable Interrupt Instructions El DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at
42. VPP TEST P0 0 P0 1 nRESET P0 2 O1 ON 7 INT7 P2 0 P2 1 P2 2 CLO 32 SOP SDIP P2 3 TOCLK P2 4 TO P3 0 P3 1 Figure 14 1 S3F80N8 Pin Assignments 32 pin SOP SDIP ELECTRONICS 14 1 S3F80N8 FLASH MCU S3F80N8 UM_REV1 10 VDD P1 0 INTO SCLK P1 1 INT1 SDAT S3F80N8 P1 2 INT2 P1 3 INT3 P1 4 INT4 P1 5 INT5 P0 2 P1 6 INT6 P0 3 P1 7 INT7 P0 4 P2 0 P0 5 P2 1 P0 6 P2 2 CLO P0 7 P2 3 TOCLK P2 5 P2 4 T0 Vss XOUT XIN VPP TEST P0 0 P0 1 nRESET 1 2 3 4 5 6 7 8 9 Figure 14 2 Pin Assignment 28 pin SOP Table 14 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming P1 1 SDAT 30 32 pi lO Serial data pin output when reading Input 26 28 pi when writing Input and push pull output port can be assigned SCLK 32 pin Serial clock pin input only pin 7 28 M Power supply pin for flash ROM cell writing indicates that MTP enters into the writing mode When 11 V 0 25V is applied MTP is in writing mode and when 5 V is applied MTP is in reading mode Option nRESET nRESET 7 Chip Initialization VDD VSS Vpp Vss 32 1 32 pin Logic power supply pin 28 1 28 pin NOTE S3F80N8 s flash ROM must be programmed by VPP 11 0V 0 25V Some tools for example Openice i500 only support VPP 12 5V so it must not be connected to TEST pin directly We suggest to use SPW uni AS pro US pro and other tools which support VP
43. W R W R W Addressing Mode Register addressing mode only 7 4 NOTE Not used for the S3F80N8 P3 3 Pull up Resistor Enable Bit Pull up disable Pull up enable EH P3 2 Pull up Resistor Enable Bit Pull up disable EH Pull up enable P3 1 Pull up Resistor Enable Bit Pull up disable EH Pull up enable P3 0 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable The reset value of PSPUR is OFH this value enables the pull up resistor ELECTRONICS 4 N CONTROL REGISTERS S3F80N8 UM_REV1 10 PP _ Register Page Pointer DFH Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Not used for the S3F80N8 NOTE In S3F80N8 only page 0 settings are valid Register page pointer values for the source and destination register page are automatically set to OOH following a hardware reset These values should not be changed during normal operation 4 24 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER RP0 Register Pointer 0 D6H Bit Identifier Reset Value Read Write Addressing Mode 7 1 1 0 0 0 _ R W R W R W R W R W _ _ _ Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 144 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working
44. a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File or RP1 Value used in points to Instruction enin working register block Program Memory wod Base Address NO peran dst src x Instruction Point to One of the Example Woking Register 1 of 8 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3F80N8 UM_REV1 10 INDEXED ADDRESSING MODE Continued 3 8 Register File MSB Points to RP0 or RP1 gt RP0 or RP1 Selected RP points to start of Program Memory as block OFFSET NEXT 2 Bits 4 bit Workin Register you Point to Working N i ad OPCODE Register Pair 16 Bit address added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits Value used in 16 Bits Instruction Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded int
45. address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src S3F80N8 UM REV1 10 Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stac
46. arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 91 IR Given Register 00H register 01H 02H and register 02H 17H RL OOH gt Register 00H 55H C 1 RL 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 INSTRUCTION SET S3F80N8 UM REV1 10 Rotate Left Through Carry RLC Operation dst dst 0 lt C C lt dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 4 11 IR Given Register 00H register 01H 02H and
47. complemented If C 1 the value of the carry flag is changed to logic zero if C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET S3F80N8 UM REV1 10 CLR Clear CLR dst Operation dst lt 0 The destination location is cleared to 0 Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 B0 R 4 B1 IR Examples Given Register 00H 4FH register 01H 02H and register 02H 5EH CLR OOH gt Register OOH OOH CLR 01H gt Register 01H 02H register 02H 00H In Register R addressing mode the statement CLR 00H clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 6 28 ELECTRONICS S3F80N8 UM_REV1 10 COM Complement COM Operation Flags Format Examples dst dst lt NOT dst INSTRUCTION SET The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7
48. destination value 12H and stores the result 0FH in destination register R1 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET SWAP SWAP Operation Flags Format Examples Swap Nibbles dst dst 0 3 lt gt dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 FO R F1 IR Given Register 00H SEH register 02H 03H and register O3H 0A4H SWAP 00H gt Register 00H SWAP 02H gt Register 02H 03H register 4AH In the first example if general register contains the value 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the 00H register leaving the value 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3F80N8 UM REV1 10 TCM rest Complement Under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source ma
49. fosc 2 11 fosc 1 Figure 7 5 System Clock Control Register CLKCON STOP Control Register STPCON FBH R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101B Otherwise the STOP instruction will not execute as well as reset will be generated Figure 7 6 STOP Control Register STPCON 7 4 ELECTRONICS S3F80N8 UM_REV1 10 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW By smart option 3EH 5 in ROM user can select internal RESET LVR or external RESET The S3F80N8 can be reset in four ways by external power on reset by the external reset input pin pulled low by the digital watchdog timing out by the Low Voltage reset circuit LVR During a power on reset the voltage at Vpp goes to High level and the nRESET pin is forced to Low level The nRESET signal is input through an Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings the S3F80N8 into a known operating status To allow time for internal CPU clock oscillation to stabilize the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance Whenever a reset occurs during normal operation that is when both Vpp and nRESET are High level the nRESET pin is forced Low level and the reset operation starts
50. generate a timer 0 match interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TOPWM P2 4 pin is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to tc x 256 see Figure 10 7 Du TOOVF IRQ2 Overflow INT Match Interrupt Enable Disable TOCON 1 8 Bit Up Counter Capture Signal TOCON 2 Overflow Interrupt Enable Disable TOINT IRQ2 TOCON O 8 Bit Comparator Match INT Pending TO PWM Output P2 4 TOCON 5 4 Timer 0 Buffer Register High level when Match Signal data counter Overflow Signal Lower level when TOCON 3 data counter Timer 0 Data Register Figure 10 7 Simplified Timer 0 Function Diagram PWM Mode 10 10 ELECTRONICS S3F80N8 UM_REV1 10 BASIC TIMER and TIMER 0 Capture Mode In capture mode a signal edge that is detected at the TOCAP P2 4 pin opens a gate and loads the current counter value into the timer 0 data register You can select rising or falling edges to trigger this operation Timer 0 also gives you capture input source the signal edge at the TOCAP P2 4 pin You select the capture input by setting the values of the timer 0 capture input selection bits in the timer 0 control register TOCON 5 4 D2H The timer 0
51. gt Register 55H SP 00FCH POP 00H gt Register 01H register 01H 55H SP OOFCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location 00FBH 55H into destination register 00H and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3F80N8 UM REV1 10 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register 00H 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 200H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operati
52. if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir src dst 3 6 44 R R 45 R IR dst src 3 6 46 R IM Given 15H R1 2AH R2 01H register 08H register 01H 37H and register 08H 8AH OR RO R1 gt R1 2 R0 R2 gt 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01H 00H gt Register 00H 08H register 01H OR 00H 02H gt Register In the first example if working register RO contains the value 15H and register R1 the value 2 the statement OR RO R1 logical ORs the RO and H1 register contents and stores the result SFH in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL 0D9H 0FBH and stack register 0FBH 55H POP 00H
53. in length Given RO 06H and general register 00H 05H LDB R0 00H 2 gt RO LDB 00H 0 RO gt RO 07H register 00H 05H 06H register 00H 04H In the first example destination working register RO contains the value 06H and the source general register the value 05H The statement LD RO0 00H 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in register RO In the second example is the destination register The statement LD 00H 0 R0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register 00H ELECTRONICS 6 51 INSTRUCTION SET S3F80N8 UM REV1 10 LDC LDE Load Memory LDC LDE Operation Flags Format 10 dst src dst src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or values an even number for program memory and odd odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ope dst sre 2 10 C3 r Irr 2 10 D3 Irr r 3 12 E7 opc src dst 3 12 F7 XS rr r opc dst src XL XL 4 14 A7 r XL rr src dst XL XLy 4 14 B7 XL rr r DA DA 4 14 A7 r DA opc DA DA 4 14 B7 DA r DA DA 4 14 A7 r DA opc DA DA 4 14 B7 DA r
54. input or open drain push pull output mode Pull up resistors can be assigned by software TO lO Timer 0 PWM output and capture input INTO INT7 External interrupt input pins 20 27 P1 0 P1 7 XIN System clock input and output pins 2 Xour TEST Test signal input for factory use only 4 must be connected to Vas _ System reset pin O7 y ENS s 1 5 PRODUCT OVERVIEW S3F80N8 UM_REV1 10 PIN CIRCUITS Open drain Enable O Pull up Resistor lt Pull up Enable Data Output Disable Digital Input Figure 1 4 Pin Circuit Type A Open drain Enable Pull up Resistor H lt Pull up Enable Data Output Disable Digital Input Interrupt Input Figure 1 5 Pin Circuit Type B 1 6 ELECTRONICS S3F80N8 UM_REV1 10 PRODUCT OVERVIEW Open drain ae Pull up Resistor P2CONH 1 0 H lt Pull up Enable P2CONL 5 4 CLO M U TO o4 X Output Disable Digital Input Figure 1 6 Pin Circuit Type C ELECTRONICS 1 7 PRODUCT OVERVIEW S3F80N8 UM_REV1 10 NOTES 1 8 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3F80N8 micro controller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3F80N8
55. instructions such as AND OH XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H R W Bank address status flag BA Carry flag C Fast interrupt Zero flag Z status flag FIS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero in
56. interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed How to Enter into Stop Mode Handling STPCON register then writing Stop instruction keep the order LD STOPCON 10100101 STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN S3F80N8 UM_REV1 10 IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fosc because CLKCON 0 and CLKCON 1 are cleared to 00 If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 1 and CLKCON 0 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initi
57. match capture interrupt is generated whenever the counter value is loaded into the timer 0 data register By reading the captured data value in TODATA and assuming a specific value for the timer 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the TOCAP pin see Figure 10 8 8 Bit Up Counter Interrupt Enable Disable TO CAP input TOCON 1 TOINT IRQ2 TULONO Capture INT Pending Figure 10 8 Simplified Timer 0 Function Diagram Capture Mode ELECTRONICS 10 11 BASIC TIMER and TIMER 0 S3F80N8 UM_REV1 10 TOCON 2 gt Data BUS TOCON 3 fosc 4096 fosc 1024 DIV fosc 8 bit Up Counter p Clear fosc 128_ M Read Only R TOCON 1 BTCON O P2 3 TOINT STCON 8 Bit Comparator M TOCK U TOCON O 5 x Match signal TOOVF TOCON 3 Bits 5 4 Timer 0 Data Register UX P2 4 TOPWM Timer 0 Buffer Register TOCAP x Data BUS Figure 10 9 Timer 0 Block Diagram 10 12 ELECTRONICS S3F80N8 UM_REV1 10 LOW VOLTAGE RESET 1 1 LOW VOLTAGE RESET OVERVIEW The S3F80N8 can be reset in four ways by external power on reset by the external reset input pin pulled low by the digital watchdog timing out by the Low Voltage reset circuit LVR During an external power on reset the voltage VDD is High level and the nRESET pin is forced Low level The nRESET signal is input through a Schmitt trigger circuit wher
58. program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst dst 2 6 ccB RA cc 0 to F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LABEL_X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET L D Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 rC r IM r8 r R r OtoF D7 Ir r src dst 3 E4 R R E5 R IR dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R 5 6 8 x 5 r ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Continued Examples Given
59. register space After a reset RPO points to address COH selecting the 8 byte working register slice COH C7H 2 0 Not used for the SSF80N8 RP1 Register Pointer 1 D7H Reset Value 1 1 0 0 1 _ _ _ Read Write R W R W R W R W R W _ _ _ Addressing Mode 7 3 ELECTRONICS Register addressing only Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 144 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H selecting the 8 byte working register slice Not used for the SSF80N8 4 25 CONTROL REGISTERS S3F80N8 UM_REV1 10 SPL stack Pointer Low Byte D9H Reset Value x x x x x x x X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The SP value is undefined following a reset 4 26 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER STOPCON Stop Control Register FBH Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTES 1 Before execute the STOP instruction set this STPCON register as 101001016 2 When STOPCON register is not 0A5H value if
60. tia eee ael ese OE Ee Une dtd 2 1 Smart e ITE 2 2 Register ArChitecture l u roe hate ge tA w a d endete sia tede Sa ine e 2 4 Working Registers not re eee eei ret sha ted an t ere tbe Perte ce t e deett 2 5 Using The Register Points e te E nb i eb e E RE etd 2 6 Register Addressing expri nee EE wa ced rdi dite Po anita ed eed 2 8 Common Working Register Area sss n n nnne trenes 2 10 4 bit Working Register sesidir L n L E aS eene Aaa Siaka nnne nnne 2 11 8 bit Working Register Addressing U 2 13 System and User Stack eerte than eti n e ea Er a m akana shay s 2 15 Chapter 3 Addressing Modes Oi EE 3 1 Register Addressing Mode Ri rione enden td eee Ree e a a egere dee idein ren 3 2 Indirect Register Addressing Mode 1 nennen nnne nre 3 3 Indexed Addressing Mode X pese del en ttd eee tere en darte eee eene een ren 3 7 Direct Address Mode IDAN ie UI teet ee ee cele en ee pv Eee ed erus 3 10 Indirect Address Mode ler ee Pene d Fed Ras ius 3 12 Relative Address Mode R me LI ere I ee ope ne le en duit e d cre LA pk Ld ned Rae uen 3 13 Immediate Mode IN u etre ect tee etd e eite tie n tI er ted Pre ELA ed ER 3 14 S3F80N8 MICROCONTROLLER vii Table of Contents Continued Chapt
61. value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3F80N8 UM REV1 10 DIV pivide Unsigned DIV dst src Operation dst src dst UPPER REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 03H R2 40H register 40H 80H DIV RR0 R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO 03H R1 80
62. 1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 r1 2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IRZ RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA IA1 IR1 IM Ir1 r2 HR HR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 IRR1 IR2 R1 DA1 r2 1 xs 6 10 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3F80N8 UM REV1 10 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z
63. 15 BRBRRRRRRRRRBRR 28 SOP 375 10 45 0 30 7 70 0 20 O pee a 18 02 MAX 17 62 0 20 2 50 MAX 2 S I LO gt LTIEJEILEILILILILHLHLBHLBLLHLBHErT 0 10 MAX EPR TT U2 poe 0 10 0 41 0 05 NOTE Dimensions are in millimeters Figure 13 1 28 SOP 375 Package Dimensions ELECTRONICS MECHANICAL DATA S3F80N8 UM_REV1 10 32 SOP 450A 12 00 0 30 8 34 0 20 o EN o I m 2 00 0 10 2 20 wx 0 40 0 10 0 05 MIN NOTE Dimensions are in millimeters Figure 13 2 32 SOP 450A Package Dimensions ELECTRONICS S3F80N8 UM_REV1 10 9 10 0 20 32 SDIP 400 O 29 80 MAX 29 40 0 20 0 45 0 10 1 37 1 00 0 10 gt NOTE Dimensions are in millimeters Figure 13 3 32 SDIP 400 Package Dimensions ELECTRONICS e N I 0 51 MIN 5 08 MAX 3 30 0 30 MECHANICAL DATA MECHANICAL DATA S3F80N8 UM_REV1 10 NOTES 13 4 ELECTRONICS S3F80N8 UM_REV1 10 S3F80N8 FLASH MCU S3F80N8 FLASH MCU OVERVIEW The S3F80N8 single chip CMOS microcontroller is the Flash MCU version It has an on chip Half Flash ROM instead of a masked ROM The Half Flash ROM is accessed by serial data format VDD 0 INTO SCLK 1 INT1 SDAT 2 INT2 S3F80N8 2 3 INT3 4 INT4 5 INT5 6 INT6 Vss XOUT XIN
64. 2 This instruction is useful when implementing threaded code languages contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 1F The diagram below shows one example of how to use an ENTER statement After Address Data IP Address Data 40 Enter 1F 41 Address H 01 42 Address L 10 43 Address H Enter PC Address H Address L Address H SP 20 00 110 Routine 21 IPL 50 22 Data Memory Stack ELECTRONICS 6 41 INSTRUCTION SET S3F80N8 UM REV1 10 EXIT Exit EXIT Operation Flags Format Example Address IP PC SP 20 21 22 6 42 IPH 00 i 50 Data Stack IP lt SP SP lt 2 lt IP IP lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack The diagram below shows one example of how to
65. 4 12 3 Operating Voltage Range n 12 6 12 4 RC Oscillation Mode 2 5 imet trt he Pe Ere dade 12 6 12 5 Clock Timing Measurement at X N sss nennen nennen 12 7 12 6 Input Timing for External Interrupts U nennen 12 8 12 7 Input Timing for saus sanu nennen entente nnne sinn enne 12 8 12 8 EVR Reset Timing situ np n m be ote boa ee diete it e tes 12 9 12 9 The Circuit Diagram to Improve EFT 12 9 13 1 28 SOP 375 Package 1 13 1 13 2 32 SOP 450A Package Dimensions U eene 13 2 13 3 32 SDIP 400 Package Dimensions 13 3 14 1 S3F80N8 Pin Assignments 32 pin SOP SDIP 14 1 14 2 Pin Assignment 28 pin SOP uuu asia Da ua 14 2 14 3 PCB Design Guide for on Board Programming sess 14 3 15 1 Development System Configuration eee 15 2 15 2 TB80N8 Target Board Configuration 15 3 15 3 50 Pin Connector Pin Assignment for user 15 6 15 4 TB80N8 Probe Adapter 15 6 S3F80N8 MICROCONTROLLER xiii Table Number 6 1 6 2 6 4 6 5 6 6 12 11 14 1 15 1 15 2 S3F80N8
66. 4 D4 IA Given RO 35H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 1AH 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C The carry flag C is
67. 6 lt RR6 1 77H contents of is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H 2FH R7 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples dst src rr rr 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Ir Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 R0 RR6 lt RR6 1 contents of RO is loaded into program memory location 2200H 21FFH 1H 7FH 22H R7 OOH LDEPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into external data memory location 2200H 21FFH 1H 7FH 22H R7 OOH
68. 7 INSTRUCTION SET S3F80N8_UM_REV1 10 PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 83 IR R Given Register register 01H 05H and register 04H 2AH PUSHUI 900H 04H Register 04H register 01H 05H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example RCF C 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to O No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 2 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3F80N8 UM REV1 10 RET Return RET Operation Flags
69. 7 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES S3F80N8 UM_REV1 10 IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is uselul for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the S3F80N8 control registers are presented in an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this reference chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part 1 of this manual The locations and r
70. 7H RO C lt lt 0 Bits 4 7 3 bits 0 3 1 DA R1 31 0 leave the value 31 BCD in address 27H R1 ELECTRONICS S3F80N8 UM_REV1 10 DEC Decrement DEC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex opc dst 2 4 00 01 Given R1 03H and register 03H 10H DEC Ri gt R1 02H DEG QHR1 gt Register 03H 0FH INSTRUCTION SET Addr Mode dst R IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value 0FH ELECTRONICS 6 35 INSTRUCTION SET S3F80N8 UM REV1 10 D ECW Decrement Word DECW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Se
71. 80N8 32SDIP 32SOP 28SOP SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com Operation status displayed in LCD panel C amp A technology e TEL 82 2 2612 9027 e FAX 82 2 2612 9044 e E mail wisdom cnatech com e URL http Awww cnatech com 15 9 DEVELOPMENT TOOLS S3F80N8 UM REV1 10 NOTES 15 10 ELECTRONICS
72. 80N8 UM REV1 10 SPW uni Ex Single OTP MTP FLASH Programmer e Download Upload and data edit function e PC based operation with USB port w JJ e Fullfunction regarding OTP MTP FLASH MCU Read Program Verify Blank Protection Fast programming speed 4Kbyte sec Support all of SAMSUNG OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC New devices will be supported just by adding device files or upgrading the software SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com AS pro On board programmer for Samsung Flash MCU e Portable amp Stand alone Samsung OTP MTP FLASH Programmer for After Service e Small size and Light for the portable use e Support all of SAMSUNG OTP MTP FLASH devices e HEX file download via USB port from PC e Very fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second e Internal large buffer memory 118M Bytes e Driver software run under various O S Windows 95 98 2000 XP e Full function regarding OTP MTP programmer Read Program Verify Blank Protection e Two kind of Power Supplies User system power or USB power adapter e Support Firmware upgrade SEMINIX e TEL 82 2 539 7891 e FAX 82 2 539 7819 e E mail sales seminix com e URL http www seminix com ELECTRONICS S3F80N8 UM_REV1
73. ADD RO R1 RO lt RO ADC RO R2 RO lt RO R2 G ADC RO R3 RO lt RO R3 C ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS 2 7 ADDRESS SPACES S3F80N8 UM_REV1 10 REGISTER ADDRESSING The S3F8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that spac
74. BC dst src Operation dst lt dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Set if a borrow occurred src dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir src dst 3 6 34 R R 35 R IR dst src 3 6 36 R IM Examples Given R1 10H R2 03H C 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 03H register 03H OAH SBC 01H 02H gt Register 01H 1CH register 02H SBC 01H 02H gt Reg
75. D6H to 40H and register pointer 1 RP1 at location 0D7H to 48H The statement SRP0 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET STOP Stop Operation STOP Operation Flags Format Example The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the nRESET pin must be held to Low level until the required oscillation stabilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adequate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F The statement STOP halts all microcontroller operations NOP NOP NOP ELECTRONICS 6 81 INSTRUCTION SET S3F80N8 UM REV1 10 SU B subtract SUB Operation Flags Format Examples dst src dst lt dst src The source op
76. DRESSING MODE Concluded Register File MSB Points to RP0 or RP1 or RP1 Selected RP points to start of working register oe ee Program Memory 4 bit Working Register Address Register Next 2 bit Point Pair References either Register Pair Program Memory or 1 of 4 Data Memory 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in Instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in
77. EGISTER 2 Port 2 Control Register High Byte EEH Reset Value _ _ _ _ 1 0 0 0 Read Write _ _ _ _ R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3F80N8 3 2 P2 5 Configuration Bits 0 0 Nomainot 0 1 jOupumodepushpul o O 1 0 JOupumodeopendrin I O 1 0 P2 4 Configuration Bits ESEJ Normal input or TO capture input oja Output mode push pull K EJ Output mode open drain Alternative function T0 PWM output NOTE The reset setting of P2 5 is open drain output ELECTRONICS 4 19 CONTROL REGISTERS S3F80N8 UM_REV1 10 P2CONL 2 Control Register Low Byte EFH Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 Configuration Bits ESSE Normal input or TO clock input ESSEN Output mode push pull 1 0 Outputmode open drain 5 4 P2 2 Configuration Bits _ Fo output mose pupal Outputmode opens _ 3 2 P2 1 Configuration Bits o o Nmamu Fo mode pn ie jowwmoeopendan 1 0 P2 0 Configuration Bits 0 0 Nomainot o O 0 1 Outputmoae push pul o O 1 0 Outputmode open drain O 4 20 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER P2PUR Port 2 Pull up Control Register FOH Reset Value _ 0 0 0 0 0 0 Read Write _ _ R W
78. ELECTRONICS USER S MANUAL S3F80N8 8 Bit CMOS Microcontrollers November 2008 REV 1 10 Confidential Proprietary of Samsung Electronics Co Ltd Copyright 2008 Samsung Electronics Inc All Rights Reserved Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3F80N8 8 Bit CMOS Microcontrollers User s Manual Revision 1 10 Publication Number 21 10 S3 F80N8 112008 2008 Samsung Electronics Typical parameters can and do vary in different applica
79. Flags Format Example dst src b If src b is a 0 then PC lt PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F80N8 UM REV1 10 BTJRT sit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruct
80. H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation Flags Format Example r dst 1 If r 0 lt PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE In case of using DJNZ instruction the working register being used as a counter should be set at the one of location OCOH to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0 DJNZ R1 LOOP DJNZ is typic
81. ICS S3F80N8 UM_REV1 10 ADDRESS SPACES ROM Address 3CH Must be initialized to 0FFH ROM Address 3DH Must be initialized to 0FFH ROM Address 3EH ___ LVR level selection bit Not used 10 2 2V Oscillator selection bits f 11 3 9V 000 frc 1 RC oscillation mode2 LVR control bit 001 2 RC oscillation mode2 00 LVR disable in run mode disable in stop mode 010 tnc 4 RC oscillation mode2 01 LVR disable in run mode enable in stop mode 911 tnc 8 RC oscillation mode2 10 LVR enable in run mode disable in stop mode 111 External crystal ceramic 11 LVR enable in run mode enable in stop mode ROM Address 3FH Must be initialized to OFFH NOTE The unused bits must be initialized to 1 Figure 2 2 Smart Options ELECTRONICS 2 3 ADDRESS SPACES S3F80N8 UM_REV1 10 REGISTER ARCHITECTURE In case of S3F80N8 the total number of addressable 8 bit registers is 192 Of these 192 registers 48 bytes for CPU and system control registers or for peripheral control and data registers 16 bytes are used as shared working registers and 128 registers are for general purpose use Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3F80N8 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common working register area 144 CPU and system control registers Mapped clock periph
82. Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory 4 Next Instruction LSB Must be Zero uen urren Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE x Program Memory Address Used eem Displacement Current Instruction OPCODE Signed Po Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 12
83. Interrupt Enable Bit NT4 interrupt disable NT4 interrupt enable 3 P1 3 INT3 External Interrupt Enable Bit interrupt disable interrupt enable 2 P1 2 INT2 External Interrupt Enable Bit NT2 interrupt disable NT2 interrupt enable 1 INT1 External Interrupt Enable Bit NT1 interrupt disable NT1 interrupt enable 0 P1 0 INTO External Interrupt Enable Bit INTO interrupt disable NTO interrupt enable 4 6 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER EXTPND External Interrupt Pending Register ECH Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Port 1 7 INT7 External Interrupt Pending Bit No interrupt pending when read Pending bit clear when write ite Interrupt is pending when read No effect when write 6 Port 1 6 INT6 External Interrupt Pending Bit E Port 1 4 INT4 External Interrupt Pending Bit No interrupt pending when read Pending bit clear when write ite Interrupt is pending when read No effect when write ELECTRONICS 4 7 CONTROL REGISTERS S3F80N8 UM_REV1 10 FLAGS System Flags Register D5H Reset Value x x x x x 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or borrow condition 1 Operation generates a carry out or borrow into hig
84. Oscillator fosc ELECTRONICS S3F80N8 UM_REV1 10 CLOCK CIRCUIT CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers timer counters and watch timer Idle mode is released by a reset or by an external or internal interrupt INT release STOP enable Stop Release CLKCON 7 1 2 1 4096 E Basic Timer Main System Oscillator Circuit Frequency Timer 0 Dividing Circuit System Clock STOP OSG inst 1 1 1 2 1 8 1 16 CKCONA 3 Selector CPU Clock IDLE Instruction Figure 7 4 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK CIRCUIT S3F80N8 UM_REV1 10 SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located at address D4H It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated the fosc is selected as the CPU clock If necessary you can then increase the CPU clock speed fosc 16 fosc 8 or fosc 2 System Clock Control Register CLKCON D4H R W Divide by selection bits for CPU clock frequency 00 fosc 16 01 fosc 8 10
85. P 11 0V for SSF80N8 programming 14 2 ELECTRONICS S3F80N8 UM_REV1 10 S3F80N8 FLASH MCU ON BOARD WRITING The S3F80N8 needs only 6 signal lines including VDD and GND pins for writing internal flash memory with serial protocol Therefore the on board writing is possible if the writing signal lines are considered when the PCB of application board is designed Circuit design guide At the flash writing the writing tool needs 6 signal lines that are GND VDD RESET TEST SDA and SCL When you design the PCB circuits you should consider the usage of these signal lines for the on board writing In case of TEST pin normally test pin is connected to GND but in writing mode and programming these two cases a resistor should be inserted between the TEST pin and GND Please be careful to design the related circuit of these signal pins because rising falling timing of VPP SCL and SDA is very important for proper programming SCL I O To Application circuit To Application circuit To Application circuit SPW uni GW uni AS pro US pro Figure 14 3 PCB Design Guide for on Board Programming NOTE The recommended value of Rvpp is 330 ohm The recommended value of Cvpp is 0 1uF ELECTRONICS 14 3 S3F80N8 FLASH MCU S3F80N8 UM_REV1 10 NOTES 14 4 ELECTRONICS S3F80N8 UM_REV1 10 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The dev
86. Port 2 has two 8 bit control registers 2 for P2 4 2 5 and P2CONL for P2 0 2 3 A reset clears the P2CONH registers to 08H and P2CONL registers to 00H configuring all pins to input mode except that P2 5 open drain output You use control registers settings to select input or output mode push pull or open drain and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module Port 2 Pull up Resistor Control Register P2PUR Using the port 2 pull up resistor control register P2 PUR you can configure pull up resistors to individual port 2 pins Port 2 Control Register High byte 2 EEH R W Not used P2 5 P2 4 TO P2CONH bit pair pin configuration settings Normal input mode or TO Capture input Output mode push pull Output mode open drain Alternative function TO PWM output The reset value of P2 5 is open drain output Figure 9 9 Port 2 High Byte Control Register P2CONH ELECTRONICS 9 9 PORTS Port 2 Control Register Low byte P2CONL R W P2 2 CLO P2 3 TOCLK P2CONL bit pair pin configuration settings 00 Input mode 01 Output mode push pull Output mode open drain Alternative function TOCLK CLO Figure 9 10 Port 2 Low Byte Control Register P2CONL Port 2 Pull up C
87. R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3F80N8 2 5 Pull up Resistor Enable Bit EE Pull up disable Pull up enable 4 P2 4 Pull up Resistor Enable Bit E Pull up disable Pull up enable 3 P2 3 Pull up Resistor Enable Bit EN Pull up disable Pull up enable 2 P2 2 Pull up Resistor Enable Bit Pull up disable Pull up enable 1 P2 1 Pull up Resistor Enable Bit Pull up disable Pull up enable 0 P2 0 Pull up Resistor Enable Bit Pull up disable Pull up enable N _ ELECTRONICS 4 CONTROL REGISTERS S3F80N8 UM_REV1 10 P3CON Port 3 Control Register F2H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 Configuration Bits 0 0 1 Outputmode push pull 1 0 Outputmode open drain 5 4 P3 2 Configuration Bits o o Nmamu o i ovpu mode prp 3 2 P3 1 Configuration Bits o o Nmamu o i ovpu mode purp ie jowwmoeopendan 1 0 P3 0 Configuration Bits 0 0 Nomainot ooo 0 1 Outputmode push pull 1 0 JOuputmodeopemdrin 4 22 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER P3PUR port 3 Pull up Control Register F3 Bit Identifier 5 4 3 2 Reset Value _ 1 1 1 1 Read Write _ _ _ _ R W R
88. SD characteristic ICE amp Writer updated 15 Development tool iv SSF80N8 MICROCONTROLLER REVISION DESCRIPTIONS FOR REVISION 1 1 Chapter Subjects Major changes comparing with last version Chapter Name 9 paring 12 Electrical Data Idd3 revision from 2 5 5uA 25 C to 2 5 10uA 40 85 C 14 S8F80N8 Flash MCU TEST voltage when write FLASH ROM is changed from 11 0V to 11 0V 0 25V S3F80N8 MICROCONTROLLER v Preface The S3F80N8 Microcontroller User s Manual is designed for application designers and programmers who are using the S3F80N8 microcontroller for application development It is organized in two main parts Part Programming Model Part II Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to SSF80N8 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register ad
89. The service routine starts and the source s pending bit is cleared to 0 by hardware or by software gt m The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 Reset clear to 0 the interrupt enable bit in the SYM register SYM O to disable all subsequent interrupts 2 Save the program counter PC and status flags to the system stack 3 Branch to the interrupt vector to fetch the address of the service routine 4 Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request 5 14 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt
90. air is multiplied by the source INSTRUCTION SET operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Set if result is 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles src dst 3 22 22 22 Given Register 00H 20H register 01H 03H register 02H MULT OOH 02H gt Register 00H 01H register 01H MULT 00H gt Register 00H 00H register 01H Opcode Addr Mode Hex dst 84 RR 85 RR 86 RR src 09H register O3H 06H 20H register 02H 09H MULT 00H 30H gt Register 00H 06H register 01H 00H In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register 00H of the register pair 00H 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair 01H ELECTRONICS 6 59 INSTRUCTION SET S3F80N8 UM REV1 10 NEXT Next NEXT Operation lt IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two Flags No flags ar
91. ally used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3F80N8 UM REV1 10 EI Enable Interrupts El Operation Flags Format Example SYM 0 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 9F Given SYM 00H El Ifthe SYM register contains the value 00H that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET ENTER Enter ENTER Operation Flags Format Example SP lt 5 2 QSP lt IP IP lt lt IP IP IP
92. any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 1 Interrupt Control Register Overview Control Register iw RW Function Description Interrupt mask register IMR R W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQ0 IRQ7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The eight levels of SSF80N8 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode regist
93. ated idle mode is executed 8 6 ELECTRONICS S3F80N8 UM_REV1 10 PORTS I O PORTS OVERVIEW The S3F80N8 microcontroller has four bit programmable ports P0 3 This gives a total of 26 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special instructions are required All ports of the S3F80N8 can be configured to input or output mode Table 9 1 gives you a General overview of the S3F80N8 I O port functions Table 9 1 S3F80NG8 Port Configuration Overview Port Configuration Options Bit programmable port Normal CMOS input or push pull open drain output mode selected by software software assignable pull ups Bit programmable port Normal CMOS input or push pull open drain output mode selected by software software assignable pull ups Alternately P1 0 1 7 can be used as inputs for external interrupts INTO NT7 Bit programmable port Normal CMOS input or push pull open drain output mode selected by software software assignable pull ups Alternately P2 2 P2 3 can be used as CLO TOCK P2 4 can be used as TOPWM or PORT2 5 0 can sink 80mA current Bit programmable 1 0 port Normal CMOS input or push pull open drain output mode selected by software software assignable pull ups NOTE PORT2 5 0 can sink 80mA current However only one PORT can be used to sink as large as 80mA curr
94. conditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 0to F dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W LABEL 1000H PC 1000H JP 00H gt 0120 The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3F80N8 UM REV1 10 JR Jump Relative JR Operation Flags Format Example cc dst If cc is true PC PC dst If the condition specified by the condition code cc is true the relative address is added to the
95. configuration Normal input mode Output mode push pull Output mode opne drain Not used Figure 9 2 Port 0 Low Byte Control Register POCONL Port 0 Pull up Control Register POPUR E6H R W P0 6 P0 7 POPUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up resistor Figure 9 3 Port 0 Pull up Control Register POPUR SS3F80N8 UM REV1 10 ELECTRONICS S3F80N8 UM_REV1 10 PORTS PORT 1 Port 1 is an 8 bit port with individually configurable pins Port 1 pins are accessed directly by writing or reading the port 1 data register P1 at location E2H P1 0 1 7 can serve as inputs as outputs push pull or open drain or it can be configured the following functions External interrupt INTO INT7 Port 1 Control Registers P1 CONH P1CONL Port 1 has two 8 bit control registers P1 CONH for P1 4 1 7 and P1CONL for P1 0 1 3 A reset clears the P1CONH and P1CONL registers to 00H configuring P1 0 1 7 pins to input mode with interrupt on falling edge You use control registers setting to select input or output mode push pull or open drain Port 1 Pull Up Resistor Control Register P1PUR Using the port1 pull up resistor control register P1 PUR EAH you can configure pull up resistors to individual port 1 pins Port 1 Interrupt Control Registers EXTINT EXTPND To process external interrupts at the port 1 pins two additional control registers are provided the external
96. d Jump on 6 31 CPIJNE Compare Increment and Jump on Non Equal sse 6 32 DA Decimal AdJUSE s ria a e oce dg acea e aa usqha 6 33 DEC ec 6 35 DECW Decrement une a 6 36 DI Disable Interrupts det eee cete ade dg e ARE 6 37 DIV Divide Unsignedy rate ee an cre ae a 6 38 DJNZ Decrement and Jump if Non Zero U nennen nennen 6 39 El Enable InterruptSu n tu iecur abs ag e dede Qa aaa uapa u anaes 6 40 ENTER za a a E 6 41 EXIT cim mL 6 42 IDLE Operation EE 6 43 Mieremet E 6 44 INCW Increment WOId w uu Aa nete Wield sede ce e epe a 6 45 IRET Interrupt Beluffik c 6 46 JP NJ 6 47 JR Jump Relative ges E ua Fea etae di cua ded ec 6 48 LD LOA ni ada i SW uha 6 49 LDB Load Bills aaa S Q 6 51 S3F80N8 MICROCONTROLLER xxi Instruction Mnemonic LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD LDCPI LDEPI LDW MULT NEXT xxii List of Instruction Descriptions continued Full Register Name Page Number Load Memory cides cae ee ile eene d ep 6 52 Load Memory and eene 6 54 Load Memory and i iid
97. d with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR R1 01H 1 gt R1 07H register 01H 03H BOR 01H 2 R1 gt Register 01H 07 1 07 In the first example destination working register R1 contains the value 07 00000111 and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 0000001 1B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET BTJRF Bit Test Jump Relative on False BTJRF Operation
98. de open drain Output mode push pull 5 4 P1 6 Configuration Bits Fo CMOS input INT6 external falling edge interrupt input KB CMOS input INT6 external both falling edge and rising edge interrupt input Output mode open drain Output mode push pull 3 2 P1 5 Configuration Bits CMOS input INT5 external falling edge interrupt input CMOS input INT5 external both falling edge and rising edge interrupt input KE EJ Output mode open drain Output mode push pull 1 0 P1 4 Configuration Bits EJES CMOS input INT4 external falling edge interrupt input Kg CMOS input INT4 external both falling edge and rising edge interrupt input EBE Output mode open drain Output mode push pull 4 16 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER P1CONL Port 1 Control Register Low Byte E9H Bit Identifier Reset Value Read Write Addressing Mode 7 6 ELECTRONICS _ 5 4 3 2 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Register addressing mode only P1 3 Configuration Bits EJEA CMOS input INT3 external falling edge interrupt input CMOS input INT3 external both falling edge and rising edge interrupt input K EJ Output mode open drain Output mode push pull P1 2 Configuration Bits Fo CMOS input INT2 external falling edge interrupt input CMOS input INT2 external both falling edge and rising edge interrupt input K EJ Output
99. de push pull Figure 9 5 Port 1 Low Byte Control Register P1CONL 9 6 ELECTRONICS S3F80N8 UM_REV1 10 PORTS Port 1 Pull up Control Register P1PUR EAH R W P1 6 P1 7 P1PUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up resistor Figure 9 6 Port 1 Pull up Control Register P1PUR External Interrupt Enable Register EXTINT EBH R W INTO INT1 INT2 INT4 INT5 INT6 INT7 INTn bit configuration settings 0 Disable interrupt 1 Enable interrupt NOTE 5 0 1 2 3 4 5 6 and 7 Figure 9 7 External Interrupt Enable Register EXTINT ELECTRONICS 9 7 PORTS SS3F80N8 UM REV1 10 External Interrupt Pending Register EXTPND ECH R W INT5 INT6 INT7 EXTPND bit configuration settings No interrupt pending when read Pending bit clear when write Interrupt is pending when read No effect when write NOTE n is 0 1 2 3 4 5 6 and 7 Figure 9 8 External Interrupt Pending Register 9 8 ELECTRONICS S3F80N8 UM_REV1 10 PORTS PORT2 Port 2 is an 6 bit port with individually configurable pins Port 2 pins are accessed directly by writing or reading the Port 2 data register P2 at location E2H P2 0 2 5 can serve as inputs and as outputs push pull or open drain or you can configure the following alternative functions e P222 CLO e P23 TOCK e P2 4 TOPWM TOCAP Port 2 Control Registers P2CONH P2CONL
100. ded Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 9 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA _IRQO IRQ1 GroupB IRQ2 IRQ4 GroupC IRQ5 IRQ6 IRQ7 21 22 C21 C22 IRQO IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B C A The setting 101B would select the relationship C gt B gt A The functions of the othe
101. dicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when
102. dress The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address 0ABH 10101011B Selects RP0 or RP1 Address These address bits indicate 8 bit Pa ae co 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bits 8 bit physical address Figure 2 12 8 Bit Working Register Addressing ELECTRONICS 2 13 ADDRESS SPACES S3F80N8 UM_REV1 10 RP0 01100 000 Selects RP1 R11 8 bit address Register 1100 011 form instruction 10101 011 address LD R11 R2 OABH Specifies working register addressing Figure 2 13 8 Bit Working Register Addressing Example 2 14 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESS SPACES SYSTEM AND USER STACK The S3F8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations The S3F80N8 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their origina
103. dressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the SSF8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3F80N8 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S8F8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S3F8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detail
104. e Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Figure 2 7 16 Bit Register Pair 2 8 ELECTRONICS S3F80N8 UM_REV1 10 Special Purpose Registers General Purpose Register Registers System HOgISters c Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file After a reset RP0 points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE In the SSF80N8 microcontroller only Page 0 is implemented Can be Pointed by Register Pointer Figure 2 8 Register File Addressing ELECTRONICS ADDRESS SPACES 2 9 ADDRESS SPACES S3F80N8 UM_REV1 10 COMMON WORKING REGISTER AREA COH CFH After a reset register pointers and RP1 automatically select two 8 byte register slices locations
105. e affected Format Bytes Cycles Opcode Hex opc 1 10 The following diagram shows example of how to use the NEXT instruction Before After Address Data Address Data PC 0120 Address H 01 PC 0130 44 Address L 10 Address Data 43 Address Data 43 Address H 44 Address L 45 Address H 45 Address H 120 130 Routine ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET No Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3F80N8 UM REV1 10 OR Logical OR OR Operation Flags Format Examples dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set
106. e it is then synchronized with the CPU clock This brings the S3F80N8 into a known operating status To ensure correct start up the user should take that reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a reset is approximately 6 55 ms 2 6 fosc fosc 10MHz When a reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal reset will be activated The S3F80N8 has a built in low voltage reset circuit that allows detection of power voltage drop of external Vpp input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the reset operation of MCU This Low Voltage reset includes an analog comparator and Vref circuit The value of a detection voltage is 2 2 3 9V The on chip Low Voltage
107. e used Figure 5 1 S3F8 Series Interrupt Types 5 2 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE S3F80N8 INTERRUPT STRUCTURE The S3F80N8 microcontroller supports ten interrupt sources Every interrupt source has a corresponding interrupt address As shown in Figure 5 2 level of three interrupt are recognized by the CPU in this device specific interrupt structure When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed Vectors Sources Reset Clear 100H Basic timer overflow H W External interrupt 7 S W FAH T External interrupt 6 S W External interrupt 5 S W F6H External interrupt 4 S W External interrupt S W F2H External interrupt 2
108. ead write characteristics of all mapped registers in the S3F80N8 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 sess wa Tas e 5 2 Timer OCounterRegisr moont R ew oon o olo olo olofo Timer 0 Regier TOCON RW o olo of o olofo Basic Timer Cono Reger nw en oon o o of of o olofo Cock Cont Register cucow nw em oan o of o System Fags Register Lacs Rw x x x x x x 0 0 RegisterPoinero Re aw ew oe o olo RogisterPoinert Re Rw ew om 1 e ols Request Register ma n em of o of of imemmMekRegsr ma Rw 221 of o of of of of of NOTE Not mapped or not used x Undefined an ELECTRONICS 4 1 CONTROL REGISTERS S3F80N8 UM_REV1 10 Table 4 1 Registers continued Register NAME malis Reset Value bit 5 om pm EXISTE JL NUS M E EIE 5 EC roof of of of of Port 0 pull up resistor Se POPUR EE EN register Locations E7H is not mapped Porti control register High byte PICONH Rw 282 Port 1 control register Low byte PICONL Rw 283 Port 1 pull up resistor enable P1PUR RAN 234 EAH
109. ed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3F80N8 microcontroller Also included in Part II are electrical mechanical data It has 9chapters Chapter 7 Clock Circuit Chapter 12 Electrical Data Chapter 8 RESET and Power Down Chapter 13 Mechanical Data Chapter 9 I O Ports Chapter 14 S3F80N8 Flash MCU Chapter 10 Basic Timer amp Timer0 Chapter 15 Development Tools Chapter 11 Low Voltage Reset Two order forms are included at the back of this manual to facilitate customer order for SSF80N8 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative vi S3F80N8 MICROCONTROLLER Table of Contents Part Programming Model Chapter 1 Product Overview S3F8 Series Microcontrollers 1 1 S3F80N8 Microcontroller 1 1 EID 1 2 Block Diagrams aiio t rtp teat dar sie atc Pii Aad aww adito ua 1 3 Phi ASSIQMIMONG 1 4 Pin DOSGMPUOMS c 1 5 an 1 6 Chapter 2 Address Spaces ilm EE ERES 2 1 Program Memory 2 2 ota ep aea i eee tere epe EO e
110. egisters very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RP0 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 10 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 11 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC is which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B ELECTRONICS 2 11 ADDRESS SPACES S3F80N8 UM_REV1 10 Selects RP0 or RP1 Address OPCODE l 4 bit address Register pointer provides three provides five low order bits
111. elopment support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 and SK 1200 for the S3C7 S3C9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all the S3C8 SSF8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB80N8 is a specific target board for the development of application systems using S3F80N8 PROGRAMMING SOCKET ADAPTER When you program S3F80N8 s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for S3F80N8 ELECTRONICS 15 1 DEVELOPMENT TOOLS S3F80N8 UM REV1 10 Development System Configuration IBM PC AT or Compatible Emulator SK 1200 RS 232 USB or Reade MS OPENIce 1 500 RS 232 1 Target Application System Probe Adapter TB80N8 Target Board EVA Chip Figure 15 1 Development System Configuration 15 2 ELECTRONICS S3F80N8 UM_REV1 10 DEVELOPMENT TOOLS TB80N8 TARGET BOARD The TB80N8 target board can be used for development of S3F80N8 The TB80N8 target boa
112. ement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b lt dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R11 o R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register 0D5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3F80N8 UM REV1 10 BITR Bit Reset BITR Operation Flags Format Example dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination
113. en R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit 0 value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F80N8 UM REV1 10 Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison C Unaffected Z Set if the two bits are the same cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src NOTE In the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 000001 11B and the source register 01H contains the value 01H 00000001B the stat
114. ent in the same time ELECTRONICS 9 1 PORTS S3F80N8 UM REV1 10 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all four S3F80N8 port data registers Data registers for ports 0 1 2 3 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary 9 2 ELECTRONICS S3F80N8 UM_REV1 10 PORTS PORT 0 Port 0 is an 8 bit port with individually configurable pins Port 0 pins are accessed directly by writing or reading the port 0 data register PO at location EOH P0 0 0 7 can serve as inputs and as outputs push pull or open drain Port 0 Control Registers POCONH POCONL Port 0 has two 8 bit control registers POCONH for P0 4 0 7 and POCONL for P0 0 0 3 A reset clears the POCONH and POCONL registers to You use control registers setting to select input or output mode push pull or open drain Port 0 Pull Up Resistor Control Register POPUR Using the portO pull up resistor control register POPUR E6H you can configure pull up resistors to individual port Port 0 Control Register High byte POCONH E4H R W 5 4 3 2 0 P0 4 P0 5 P0 6 P0 7 P0CONH bit pair pin configuration Normal input mode Output mode push pull Output mode open drain Not used Figure 9 1 Port 0 High Byte Control Register POCONH ELECTRONICS 9 3 PORTS 9 4 Port 0 Control Register Low byte POCONL E5H R W POCONL bit pair pin
115. er 4 Control Registers NI ie EI ME 4 1 Chapter 5 Interrupt Structure MP M a EE 5 1 MEUD Ty POS pee ee ae 5 2 S3F80N8 Interrupt Structure a 5 3 System Level Interrupt Control Registers naa nnn innen neni 5 5 Interrupt Processing Control Points L L n nennt nnns nennen 5 6 Peripheral Interrupt Control Registers enne nnns nnne 5 7 System Mode Register SYM a 5 8 Interrupt Mask Register MR e ereen aeaee eT aE 5 9 Interrupt Priority Register u el E 5 10 Interrupt Request Register IRQ I n nn nan 5 12 Interrupt Pending Function 5 13 Interrupt Source Polling Sequence 5 14 Interrupt Service Routines U L S 5 14 Generating interrupt Vector Addresses n nasa 5 15 Nesting of Vectored Interrupts n nn n n n 5 15 Instruetioni Pointer 1p rct er persi ee ita er e aS 5 15 Fastnterr pt Processihgi uite in teh em ir e EH ERR Ee e ER Idee rto T 5 15 Procedure for Initiating Fast Interrupts U L n
116. er SYM This register enables disables fast interrupt processing and dynamic global interrupt processing NOTE All interrupts must be disabled before IMR register is changed to any value Using DI instruction is recommended ELECTRONICS 5 5 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El s Q IN Interrupt Request Register Polling Read only Cycle nRESET R IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM O manipulation Figure 5 4 Interrupt Function Diagram 5 6 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral contro
117. eral control and data 48 registers Total Addressable Bytes o 4092 AAA AAA AAA AAA SS IS CPU and system control registers Prime Register General purpose registers Area Peripheral registers and ports Figure 2 3 Register file 2 4 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 192 byte register file one that consists of 24 four 8 byte register groups or slices Each can be seen by the programmer slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RP0 two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces One working register slice is 8 bytes eight 8 bit working registers R0 R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register poi
118. erand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 22 r r src 6 23 r Ir src dst 3 6 24 R R 25 R IR dst src 3 6 26 R IM Given R1 12H R2 03H register 01H 21H register 02H 03H register O3H SUB R1 R2 R1 OFH R2 03H SUB R1 R2 R1 08H R2 03H SUB 01H 02H Register 01H register 02H 03H SUB 01H 02H SUB 01 90 SUB 01H f65H Register 01H 17H register 02H 03H Register 01H 91H C S and V 1 Register 01H and 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the
119. esistor NOTE The reset value of P3PUR is pull up enable Figure 9 13 Port 3 Pull up Control Register P3PUR S3F80N8 UM REV1 10 ELECTRONICS S3F80N8 UM_REV1 10 BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3F80N8 has two default timers an 8 bit basic timer and one 8 bit general purpose timer counter The 8 bit timer counter is called timer 0 BASIC TIMER BT You can use the basic timer BT in two different ways 5 watchdog timer to provide an automatic reset mechanism in the event of a system malfunction signal the end of the required oscillation stabilization interval after a reset or a stop mode release The functional components of the basic timer block are Clock frequency divider fosc divided by 4096 1024 128 with multiplexer 8 bit basic timer counter BTCNT FDH read only Basic timer control register D3H read write ELECTRONICS 10 1 BASIC TIMER and TIMER 0 S3F80N8 UM_REV1 10 BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in address D3H and is read write addressable using Register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of fosc 4096 To disable the watchdog fu
120. evel A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Read only IR IRQ1 an IRQ2 IRQS IRQ5 IRQ4 IRQ6 IRQ7 Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 12 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits
121. even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034 OC5H external data memory locations 1033H ODDH and 1034 0D5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3F80N8 UM REV1 10 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src rr rr 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes an even number for program memory and odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given RO 77H R6 30H and R7 00H LDCPD RR6 RO RR
122. example if general register contains the value 55H 01010101B the statement RRC 00H rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register 00H The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET SB0 Select Bank 0 SB0 Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3F80N8_UM_REV1 10 SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3F8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex 1 4 Example The statement SB1 Sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET SBC subtract with Carry S
123. h order bit 7 6 Zero Flag Z Operation result is a non zero value B Operation result is zero 5 Sign Flag Operation generates a positive number MSB 0 5 1 Operation generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D Add operation completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 1 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bank 0 is selected 1 Bank 1 is selected 4 8 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER IMR Interrupt Mask Register DDH Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Disable mask 1 Enable unmask 6 Interrupt Level 6 IRQ6 Disable mask Enable unmask 5 Interrupt Level 5 IRQ5 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Disable mask 1 Enable unmask 3 Interrupt Level 3 IRQ3 Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Disable mask 1
124. has an internal 8 Kbyte flash programmable ROM There are 192 mapped registers in the internal register file Of these 144 are for general purpose This number includes a 16 byte working register common area used as a scratch area for data operations 128 byte prime register areas 48 registers are used for the CPU and the system control and are also mapped for peripheral controls and data registers In the 48 register locations 12 are not mapped PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3F80N8 has 8K bytes internal program memory The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H ELECTRONICS 2 1 ADDRESS SPACES S3F80N8 UM_REV1 10 Decimal 8191 8K Byte Internal Program Memory Area Interrupt Vector Area Figure 2 1 Program Memory Address Space SMART OPTION Smart option is the program memory option for starting condition of the chip The program memory addresses used by smart option are from 3CH 3DH and 3EH to 3FH The S3F80N8 only uses 3EH The unused bits must be initialized to 1 The default value of program memory is FFH 2 2 ELECTRON
125. hen read 01 fosc 256 0 Clear pending bit when write 10 fosc 8 1 Interrupt is pending When read 11 External clock P2 3 TOCLk 1 no effect When write Timer 0 interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer 0 overflow interrupt enable bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 0 counter clear bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 operating mode selection bits 00 Interval mode match interrupt can occur 01 Capture mode capture on rising edge counter running capture interrupt can occur 10 Capture mode capture on falling edge counter running capture interrupt can occur 11 PWM mode match and OVF interrupt can occur Figure 10 5 Timer 0 Control Register TOCON 10 8 ELECTRONICS S3F80N8 UM_REV1 10 BASIC TIMER and TIMER 0 TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts IRQ2 Vectors EAH and ECH The timer 0 can generate two interrupts the timer 0 overflow interrupt TOOVF and the timer 0 match capture interrupt TOINT TOOVF belongs to interrupt level IRQ2 vector EAH TOINT also belongs to interrupt level IRQ2 but is assigned to a separate vector address ECH A Timer O overflow interrupt pending condition is automatically cleared by hardware when it has been service However the timer 0 match capture interrupt pending condition must be cleared by the application s interrupt service routine by
126. information is arranged in the following order Absolute maximum ratings D C electrical characteristics Current Characteristics Data retention supply voltage in stop mode Input output capacitance Oscillation characteristics Oscillation stabilization time Input Low Width Electrical Characteristics Operating voltage range LVR circuit characteristics LVR reset timing Table 12 1 Absolute Maximum Ratings Ta 25 C Parameter Condo w 98 9 79 Output Current Low All pins active 279 ELECTRONICS 12 1 Unit ELECTRICAL DATA Table 12 2 DC Electrical Characteristics TA 40 to 85 Vpp 2 0 V to 5 5 V Operating Vdd Voltage Input High Vin Ports 0 1 2 3 Voltage nRESET Input Low Vind Ports 0 1 2 3 Vpp 2 0 to 5 5 V Voltage nRESET Output High Vou loH 10mA Vpp 3 0 to 5 5 V lo 20mA 4 5 to 5 5 V Voltage 1 Port 0 1 3 Output Low 80mA Vpp 5 0 V Voltage 2 ld Port 2 TA 25 C Leakage Current except iio Input Low All input pins Vi 20V Leakage Current except nRESET and live Output High All output pins Leakage Current Output Low loy All output pins Vour 0 V Leakage Current Pull up Resistor 0 V all ports Vpp 5 0 V except nRESET 25 Rp 0 nRESET Vpp 5 0 V 25
127. interrupt enable register EBH and the external interrupt pending register ECH The EXTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the register at regular intervals In EXTINT when the interrupt enable bit of any port 1 pin is 1 a falling edge at that pin will generate an interrupt request The corresponding pending bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must clear the pending condition by writing a O to the corresponding EXTPND bit ELECTRONICS 9 5 PORTS SS3F80N8 UM REV1 10 Port 1 Control Register High byte P1CONH T LI aden P1 5 INT5 P1 6 INT6 P1 7 INT7 P1CONH bit pair pin configuration CMOS input External falling edge interrupt input CMOS input External both falling edge an rising edge interrupt input Output mode open drain Output mode push pull Figure 9 4 Port 1 High Byte Control Register PI CONH Port 1 Control Register Low byte P1 CONL E9H R W nu 0 INTO P1 1 INT1 P1 2 INT2 P1 3 INT3 P1CONL bit pair pin configuration CMOS input External falling edge interrupt input CMOS input External both falling edge an rising edge interrupt input Output mode open drain Output mo
128. ion is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 000001 1 1B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET BXOR Bit XOR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 XOR src b or dst b dst b XOR src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source add
129. ions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address or 1 lt _ LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3F80N8 UM_REV1 10 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the
130. is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles dst 2 Given R1 07H and register 07H 0F1H COM RI gt 1 OF8H COM R1 gt R1 07H register 07H OEH Opcode Addr Mode Hex dst 60 R 61 IR In the first example destination working register R1 contains the value 07H 000001 11B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET S3F80N8 UM REV1 10 Operation Flags Format Examples dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst 2 4 A2 r r src 6 A3 r Ir opc src dst 3 6 A4 R R A5 R IR dst src 3 6 A6 R IM 1 Given R1
131. isabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed ELECTRONICS S3F80N8 UM_REV1 10 RESET and POWER DOWN NORMAL MODE RESET OPERATION In normal mode the Test pin is tied to Vss A reset enables access to the 8 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON HARDWARE RESET VALUES Table 8 1 and 8 2 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values A 1 ora 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3F80N8 Register and Values after Reset BE dim mmm Desma me 7 s 5 3 2 o HmeroComerRegse
132. ister 01H 15H register 02H register OAH SBC 01H 428AH gt Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3F80N8_UM_REV1 10 SCF set Carry Flag SCF Operation Flags C Format Example lt 1 The carry flag C is set to logic one regardless of its previous value Set to 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF Sets the carry flag to logic one ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 C lt dst 0 dst lt dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex d
133. it Register File Address dst gt OPERAND Point to One OPCODE Register in Register One Operand File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RP0 ot RP1 RPO or RP1 e 34 Selected RP points to start of working Program Memory PEED register orking Register dst block OPCODE Point to the OPERAND LA Working Register Two Operand 1 of 8 Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing ELECTRONICS S3F80N8 UM_REV1 10 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations COH FFH set 1 using the Indirect Register addressing mode Program Memory Regis
134. it XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3F80N8 UM_REV1 10 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst CPU Control Instructions CCF DI El IDLE NOP RCF SB0 SB1 SCF SRP src SRP0 src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode INSTRUCTION SET S3F80N8 UM REV1 10 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic
135. k Push user stack decrementing Push user stack incrementing ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F80N8 UM REV1 10 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src B
136. l locations The stack address is always decremented before a push operation and incremented after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 14 High Address PCL Top of stack Flags Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 14 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers Register location D9H contains the 8 bit stack pointer SP that is used for system stack operations After a reset the SP value is undetermined Because only internal memory space is implemented in the S3F80N8 the SP must be initialized to an 8 bit value in the range 00H 7FH ELECTRONICS 2 15 ADDRESS SPACES S3F80N8 UM_REV1 10 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP SP 07FH PP RP0 RP1 R3 R3 SP lt 7 Normally the SP is set to 07FH by the initialization routine Stack address 0FEH PP Stack address 0FDH RP0 Stack address OFCH RP1 Stack address lt R3
137. l registers that let you control the interrupt generated by the related peripheral see Table 5 2 Table 5 2 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s P1 7 external interrupt EXTINT EBH P1 6 external interrupt EXTPND ECH P1 5 external interrupt P1CONH E8H P1 4 external interrupt P1 3 external interrupt IRQ1 EXTINT EBH P1 2 external interrupt EXTPND ECH P1 1 external interrupt P1CONL E9H P1 0 external interrupt Timer 0 match capture IRQ2 TOCON D2H Timer 0 overflow TOCNT DOH TODATA D1H ELECTRONICS 5 7 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 SYSTEM MODE REGISTER SYM The system mode register SYM DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM 0 to 0 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH R W V dm Global inte
138. les Opcode Addr Mode Hex dst dst opc 1 4 rE r r 0 to F dst 2 4 20 R 21 IR Given RO 1BH register 00H 0CH and register 1BH 0FH ING RO gt RO 1CH INC OOH gt Register 00H 0DH INC RO gt RO 1BH register 01H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register 00H assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET INCW ncrement Word INCW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 A0 RR A1 IR Given RO 1AH R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW R1 gt Register 02H 10H register 00H In the first example the wo
139. lock P2 3 TOCK 5 4 Timer 0 Operating Mode Selection Bits Interval mode Capture mode capture on rising edge counter running OVF can occur K EJ Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur 3 Timer 0 Counter Clear Bit te No effect Clear the timer 0 counter when write 2 Timer 0 Overflow Interrupt Enable bit EJ Disable Overflow interrupt Enable Overflow interrupt 1 Timer 0 Match Interrupt Enable Bit EN Disable Match interrupt Enable Match interrupt 0 Timer 0 Match Interrupt Pending Bit No interrupt pending When read Clear pending bit when write Interrupt is pending When read No effect When write NOTE When T0CON 3 is set to 1 the timer 0 counter value is cleared to Immediately following the write operation the TOCON 3 value is automatically cleared to O ELECTRONICS 4 29 CONTROL REGISTERS S3F80N8 UM_REV1 10 NOTES 4 30 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3F8 series interrupt structure has three basic components levels vectors and sources The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit fo
140. lt cleared otherwise Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H 03H and register 03H OAH R1 R2 gt R1 14H R2 03H R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H 01H 02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET ADD add ADD dst src Operation dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if a carry from the low
141. mode open drain Output mode push pull P1 1 Configuration Bits CMOS input INT1 external falling edge interrupt input CMOS input INT1 external both falling edge and rising edge interrupt input ERES Output mode open drain Output mode push pull P1 0 Configuration Bits Fo CMOS input INTO external falling edge interrupt input MB CMOS input INTO external both falling edge and rising edge interrupt input KE EJ Output mode open drain Output mode push pull 4 17 CONTROL REGISTERS S3F80N8 UM_REV1 10 P1PUR Por 1 Pull up Control Register EA Bit Identifier _ 5 4 3 2 0 0 0 0 0 0 0 0 Reset Value 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 1 7 Pull up Resistor Enable Pull up disable Pull up enable 6 P1 6 Pull up Resistor Enable Bit Pull up disable Pull up enable 5 P1 5 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 P1 4 Pull up Resistor Enable Bit Pull up disable Pull up enable 3 P1 3 Pull up Resistor Enable Bit Pull up disable Pull up enable 2 P1 2 Pull up Resistor Enable Bit Pull up disable Pull up enable 1 P1 Pull up Resistor Enable Bit Pull up disable B Pull up enable 0 1 0 Pull up Resistor Enable Pull up disable Pull up enable 4 18 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL R
142. n TB80N8 This is LED is ON when the evaluation chip S3F80N8 is in idle mode STOP LED This LED is ON when the evaluation chip S3F80N8 is in stop mode ELECTRONICS Defaul JP Description 1 2 Connection 2 3 Connection 2d Setting JP1 Target board mode selection H Test Mode L User Mode Join 2 3 JP6 Operation Mode H Main Mode L EVA Mode Join 2 3 JPO Clock source selection When using the internal clock source which is generated Emulator from Emulator join connector 2 3 and 4 5 pin user 2 3 wants to use the external clock source like a crystal user 4 5 should change the jumper setting from 1 2 to 5 6 and connect Y1 to an external clock source SWS3 Smart option at address Dip switch for smart option This 1byte is mapped address 3EH for special function Refer to the page 2 3 Y1 External clock source Connecting points for external clock source To User Target System is supplied Target Board is not supplied Target Board is supplied Join 2 3 Vcc Vpp Vpp from user System Vpp from user System IDLE LED 15 5 DEVELOPMENT TOOLS S3F80N8 UM REV1 10 USER VDD P1 0 INTO P1 1 INT1 P1 2 INT2 P1 3 INT3 P1 4 INT4 P1 5 INT5 P1 6 INT6 P1 7 INT7 P2 0 P2 1 P2 2 CLO P2 3 TOCLK P2 4 TO P3 0 Vss NC XOUT NC XIN TEST P0 0 P0 1 DEMO_RSTB P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 P2 5 P3 3 P3 2 P3 1 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss V
143. nction you must write the signature code 1010B to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT FDH can be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for all timers input clock you write a 1 to BTCON O Basic Timer Control Register BTCON D3H R W Watchdog timer enable bits Divider clear bit for timer 1010B Disable watchdog function 0 No effect Others value Enable watchdog function 1 Clear divider Basic timer counter clear bits 0 No effect 1 Clear BTCNT Basic timer input clock selection bits 00 fosc 4096 01 fosc 1024 10 fosc 128 11 Invalid selection Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3F80N8 UM_REV1 10 BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from
144. nennen sns nennen 5 16 Fast Interrupt Service Routine U L L nnns 5 16 Relationship to Interrupt Pending Bit 5 16 Programming Guidelines U U n 5 16 Chapter 6 Instruction Set OVGIVIOW t a Sa i etr alte unie INE MAIL S ad ite ra 6 1 Data TY POS oso tae eec eatem aetates ev ite Saha hu abu ec d tatu 6 1 Register Addressing euim etu dtd eret eee eiae eei fedus 6 1 Addressing Modes e Ite oed ne ea DIC Heat andere na nva foeda 6 1 El gs hegister FEAGS ia utet tate ilt ca teet erret fe sss 6 6 Flag Desceriptions aede et o ette iuit furti f Saba D kusa 6 7 Instruction Set Notation 6 8 0965 M 6 12 Instructiony Descriptions uite i ee eee aed enit eo 6 13 viii S3F80N8 MICROCONTROLLER Table of Contents Continued Part Il Hardware Descriptions Chapter 7 Clock Circuit G VOIVISW MCI s ce LI E MUI LEE 7 1 IEEE 7 1 Main Oscillator Circuits s u una 7 2 Clock Status During Power Down Modes U n 7 3 System Clock Control Register CLKCONJ L n 7 4 Chapter 8 Reset and Power Down naam s Uo cS
145. nly way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends 5 16 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8RC instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit
146. nnne enne 6 55 Load Memory with Pre Decrement u u 6 56 Load Memory with Pre Increment uu 6 57 Load tL et 6 58 Multiply Bnsigried 5 ordinances cea au ace Pug dea uua 6 59 Mec 6 60 exerum 6 61 Logical OR EE 6 62 POP TOM Stack coute tg ag ep ev 6 63 Pop User Stack Decrementing essent 6 64 Pop User Stack Incrementing sse 6 65 PUSNit0 MEL 6 66 Push User Stack Decrementing sse 6 67 Push User Stack Incrementing r 6 68 Reset Carry Flag eei dedi diese get pates Pu u 6 69 aU pM 6 70 Rotate RE 6 71 Rotate Left through 6 72 Rotate Ec 6 73 Rotate Right through Carry 6 74 Select Bank 0 eerte tod a rd cet Pup e Da 6 75 Select Bank iii do teme ci a en dee due edes PU uec 6 76 Subtract with ere dae 6 77 Set Garry Flag itur redeo eoe ani aes een dadas e cu dg e etu ua 6 78 Shift Right Arithimetic 2 2 etd i Gua apad 6 79 Set Register Polniter uidi en o ee paca dt eue eva arene 6 80 Stop ie reine terea aa da qe deae rug dag 6 81 SUB c EE 6 82 Swap Nibble C E 6 83 Test Complement under Mask
147. nte tive ei a a 4 26 STOPCON STOP Mode Control Register 4 27 SYM System Mode aaa aa aa a entren 4 28 TOCON Timer 0 A Control Register ener enne nnne 4 29 SSF80N8 MICROCONTROLLER xix List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADG Add With a etit e e aly Coven aan adh cava 6 14 ADD u ee 6 15 AND Logical AND u u ie ana ati hos ta eee i deg ue td ee aN ma sas 6 16 BAND BIEAND iiid nd y e dn a e etsi ecu F ge e tue de ea age aa les 6 17 BCP Bit pL 6 18 BITC A 6 19 BITR Bit Rosten a oder adi aqu 6 20 BITS EE 6 21 BOR Bit OP EE 6 22 BTJRF Bit Test Jump Relative on False a 6 23 BTJRT Bit Test Jump Relative on True nennen enne 6 24 BXOR psu 6 25 CALL aite eet etie cti Oa etd eu gute dua 6 26 CCF Complement Carry Flag esses enne enne nnne nen tenens nnns nenas 6 27 CLR Grm hua aaa 6 28 Complements ain ences Wea eee 6 29 EP 6 30 Compare Increment an
148. nter to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area COH CFH Slice 24 11111XXX Slice 23 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting total 16 byte working register block 00000XXX RPO Registers RO R7 Slice 2 Slice 1 Figure 2 4 8 Byte Working Register Areas Slices ELECTRONICS 2 5 ADDRESS SPACES S3F80N8 UM_REV1 10 USING THE REGISTER POINTS Register pointers RP0 and RP1 mapped to addresses D6H and D7H are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RP0 points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 5 and 2 6 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 5 In some cases it may be neces
149. ntrol registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fosc because CLKCON 0 and CLKCON 1 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the SSF80N8 interrupt structure that can be used to release Stop mode are External interrupts 1 0 1 7 INTO INT7 Please note the following conditions for Stop mode release Ifyou release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register f you use an external interrupt for stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering stop mode When the Stop mode is released by external interrupt the CLKCON 1 CLKCON O bit pair setting remains unchanged and the currently selected clock value is used The external
150. o i ovpu mode psr ie jowwmoeopendan 1 0 P0 0 Configuration Bits 0 0 Nomainot o O 1 Ouputmodepush pul S O 1 0 Outputmode open drain O 4 14 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER POPUR Port o Pull up Control Register E6H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 PO 7 Pull up Resistor Enable Bit Pull up disable Pull up enable 6 PO 6 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 5 PO 5 Pull up Resistor Enable Bit Pull up disable Pull up enable 4 0 4 Pull up Resistor Enable Pull up disable Pull up enable 3 P0 3 Pull up Resistor Enable Bit Pull up disable Pull up enable 2 P0 2 Pull up Resistor Enable Bit Pull up disable Pull up enable 1 P0 1 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable 0 P0 0 Pull up Resistor Enable Bit Pull up disable 1 Pull up enable eo ELECTRONICS 4 CONTROL REGISTERS S3F80N8 UM_REV1 10 P1CONH Port 1 Control Register High Byte E8H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 7 Configuration Bits CMOS input INT7 external falling edge interrupt input CMOS input INT7 external both falling edge and rising edge interrupt input EST Output mo
151. o register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset ELECTRONICS S3F80N8 UM_REV1 10 ADDRESSING MODES INDEXED ADDRESSING MODE Concluded Register File e 5 RPO or RP1 a gt RP0 or RP1 Selected BEEN RP points to start of working register ui Program Memory OFFSET block OFFSET NEXT 2 Bits 4 bit Working dst src E Register Address OPCODE Register Pair a ee gt Register Point to Working Pair 16 Bit address added to gt Program Memory offset LSB Selects or Data Memory lt 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions The values in the program address RR2 1000H are loaded into register R4 Identical operation to LDC example except that external program memory is accessed LDC R4 1000H RR2 LDE R4 1000H RR2 Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES S3F80N8 UM_REV1 10 DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instruct
152. o the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 OCDH R6 10H R7 32H RR6 RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by RR6 lt HRR6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst lt src rr rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes
153. occurring To do this the BTCNT value must be cleared by writing 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fosc 4096 for reset or at the rate of the preset clock source for an internal and external interrupt When BTCNT 3 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or external interrupt occurs to trigger the stop mode release and oscillation starts 2 power on reset occurred the basic timer counter will increase at the
154. on Flags Format Example dst src dst lt src IR lt 1 The POPUI instruction is used for user defined stacks in the register The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 900H gt Register 00H 02H register 01H 70H register 02 70H If general register 00H contains the value 01H and register 01H the value 70H the statement POPUI 02 00 loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3F80N8 UM REV1 10 PUSH Push To Stack PUSH Operation Flags Format Examples SIC SP SP 1 QSP src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH SPH 00H and SPL 00H
155. ontrol Register P2PUR FOH R W Not used P2 5 P2PUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up resistor Figure 9 11 Port 2 Pull up Control Register P2PUR S3F80N8_UM_REV1 10 ELECTRONICS S3F80N8 UM_REV1 10 PORTS PORTS 32 PIN S3F80N8 Port 3 is a 4 bit I O port with individually configurable pins Port 3 pins are accessed directly by writing or reading the Port 3 data register P3 at location E3H P3 0 3 3 can serve as inputs and as outputs push pull or open drain Port 3 Control Registers P3CON Port 3 has an 8 bit control registers PSCON for P3 0 3 3 A reset clears the P3CON registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull or open drain Port 3 Pull up Resistor Control Register P3PUR Using the port pull up resistor control register PSPUR F3H you can configure pull up resistors to individual port 3 pins Port 3 Control Register F2H R W 5 4 3 2 0 P3 0 P3 1 P3 2 P3 3 P3CON bit pair pin configuration settings Input mode Output mode push pull Output mode open drain Not used Figure 9 12 Port 3 Control Register PSCON ELECTRONICS 9 11 PORTS Port 3 Pull up Control Register P3PUR P3 2 P3 1 F3H R W P3 0 P3 3 Not used P3PUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up r
156. or fosc L 7 2 7 2 External Oscillator OSC 7 2 7 3 RC Oscillator MODE 2 fosc a enne 7 2 7 4 System Clock Circuit ener 7 3 7 5 System Clock Control Register 7 4 7 6 STOP Control Register 7 4 8 1 Low Voltage Reset Circuit a u asnu Su G a na 8 2 9 1 Port 0 High Byte Control Register 9 3 9 2 Port 0 Low Byte Control Register POCONL sse 9 4 9 3 Port 0 Pull up Control Register POPUR aa 9 4 9 4 Port 1 High Byte Control Register P1CONH 9 6 9 5 Port 1 Low Byte Control Register P1CONL sse 9 6 9 6 Port 1 Pull up Control Register P1PUR a 9 7 9 7 External Interrupt Enable Register EXTINT sse 9 7 9 8 External Interrupt Pending Register aa 9 8 9 9 Port 2 High Byte Control Register 2 9 9 9 10 Port 2 Low Byte Control Register P2CONL sse 9 10 9 11 Port 2 Pull up Control Register P2PUR
157. order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir src dst 3 6 04 R R 05 R IR dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H 0AH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H 03H ADD 01H 425H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS 6 15 INSTRUCTION SET S3F80N8 UM REV1 10 AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir src dst 3 6 54 R R 55 R IR dst src 3 6 56 R IM Given
158. ow Each vector can have several interrupt sources In the S3F80N8 interrupt structure there are ten possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 INTERRUPT TYPES The three components of the S3F8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source 54 Type 2 One level IRQn one vector V4 multiple sources S S Type 3 One level IRQn multiple vectors V multiple sources S4 S5 S4 4 Spam In the SSF80N8 microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 IRQn Vi 51 1 2 IRQn S2 5 Type 3 IRQn NOTES 1 The number of Sn and Vn value is expandable 2 In the SF80N8 implementation interrupt types 1 and 3 ar
159. products are designed and manufactured in accordance with the highest quality standards and Samsung Electronics Co Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea Box 37 Suwon 449 900 TEL 82 031 209 5238 FAX 82 031 209 6494 Home Page URL Http www samsungsemi com Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR Samsung Electronics SSCR PRODUCT NAME S3F80N8 8 bit CMOS Microcontroller DOCUMENT NAME S3F80N8 User s Manual Revision 1 10 DOCUMENT NUMBER 21 10 S3 F80N8 112008 EFFECTIVE DATE November 2008 DIRECTIONS Revision 1 10 REVISION HISTORY Preliminary Spec for internal release only 2007 S3F80N8 MICROCONTROLLER ili REVISION DESCRIPTIONS FOR REVISION 1 0 Chapter Chapter Name Page 01 Product Overview External clock Range is changed from 1MHz to 6MHz 1MHz to 10MHZz operating voltage is changed from 2 2V 5 5V to 2 0 V 5 5 02 Address Space Figure 2 2 Smart Option LVR level 3 9V Selection Bits is changed from 01 to 11 Subjects Major changes comparing with last version 12 Embedded Flash 12 2 TEST pin voltage when read write FLASH ROM is changed from Memory Interface 12 5V to 11 0V 13 Electrical Data The max value of Vol2 is changed from 1 0V to 1 5V The pull up resister of ports is changed from 70kO 100 to 25kO 50kO 100kQ Add E
160. r ze Primero Regier Rw ven o of of of of o of Basi Timer Control Register ercon Aw zr oan of olol of of oloo Cock control Register mw 212 par of System Fags Register nw e vod lt x Register Porrero Re aw zw ve 1 1 of of RegiterPoiters Re Rw 218s om spol o 11 Location D8H is not mapped Register Page Register PP RW 223 ELECTRONICS 8 3 RESET and POWER DOWN S3F80N8 UM_REV1 10 Table 8 1 S3F80N8 Register and Values after nRESET Continued Decimal Hex 7 6 5 4 3 2 1 0 o RW za of Pon dataregister RW zs em o of of of of of of o Pont2dataregister Pe RW 2 0 of of of of o Pors aata register Pe aw zz Ee of Gs EDIT EI Poon ww ofofo Port 0 pull up resistor Se POPUR RAN E6H register Location E7H is not mapped wen mw 1 ole Pot comogsertowtym ees fof Port 1 pull up resistor Se P1PUR RAN EAH ia www zs e External interrupt pending register EXTPND R W 0 m Location EDH is not red Erro DID S sss
161. r IPR bit settings are as follows IPR 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C PR 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 10 ELECTRONICS S3F80N8 UM_REV1 10 Group priority D7 D4 D1 0 0 Undefined 1 gt gt 0 gt gt 1 gt gt 0 gt gt 1 gt gt 0 gt gt 1 Undefined 0 0 0 0 1 1 1 1 INTERRUPT STRUCTURE Interrupt Priority Register IPR RW 0 IRQO gt IRQ1 1 IRQ1 gt IRQ0 Group B 0 IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 Subgroup B 0 IRQ3 gt IRQ4 1 IRQ4 gt IRQ3 Group G 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that l
162. r interrupt priority assignment and recognition All peripherals and blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F80N8 interrupt structure recognizes three interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for SSF8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3F80N8 uses 10 vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overfl
163. rate of fosc 4096 If an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter is set When BTCNT 4 is set normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER and TIMER 0 S3F80N8 UM_REV1 10 Oscillation Stabilization Time Normal Operating mode Reset Release Voltage RESET trst RC gt I Internal Reset Release Oscillator Xour I I Oscillator Stabilization Time 10000B 00000B twAIT 4096x16 fosc 1 Basic timer increment and CPU operations are IDLE mode NOTE Duration of the oscillator stabilization wait time t WAIT when it is released by a Power on reset is 4096 x 16 fosc tRsr RC and C are value of external power on Reset Figure 10 2 Oscillation Stabilization Time on RESET 10 4 ELECTRONICS S3F80N8 UM_REV1 10 BASIC TIMER and TIMER 0 Normal STOP Mode Oscillation Stabilization Time Normal Operating 4 p Operating Mode Mode STOP Instruction STOP Mode Execution Y Release Signal External Interrupt RESET STOP Release Signal Oscillator XOUT 10000B 00000B QUEE s M Timer Increment NOTE Duration of the oscillator stabilzation wait time t WAIT it is released by interrupt is determined by the setting in basic timer control register BTCON o wee amm
164. rd is operated as target CPU with Emulator SK 1200 OPENIce 1 500 To User O00 o U 74HC11 In Circuit Emulator RESET A JP1 TEST_MODE 5 5 IDLE STOP SK 1200 OPENIce 1 500 RUN_MODE J0j2euuo utd 00L 100 Pin Connector 128QFP S3E80N8 EVA Chip 50 Pin Connector MAIN MODE EVA MODE Figure 15 2 TB80N8 Target Board Configuration NOTES 1 TB80NSG should be supplied 5 0V normally 2 The symbol 4 marks start point of jumper signals ELECTRONICS 15 3 S3F80N8 UM REV1 10 DEVELOPMENT TOOLS Table 15 1 Components of TB80N8 Symbols Usage Description J1A 100 pin connector Connection between emulator and TB80N8 target board J2 50 pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to S3F80N8 EVA chip VCC GND POWER connector External power connector for TB80N8 IDLE STOPLED STOP IDLE Display Indicate the status of STOP or IDLE of S3F80N8 EVA chip on TB80N8 target board JP1 JP6 MODE Selection Selection of Flash tool user mode and Eva Main chip mode ELECTRONICS S3F80N8 UM_REV1 10 DEVELOPMENT TOOLS Table 15 2 Setting of the Jumper i
165. register 02H 17H 0 RLC OOH gt Register 00H 54H C 1 RLC gt Register 01H 02H register 02H 2 0 In the first example if general register 00H has the value 0AAH 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register 00H resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst n lt dst n 1 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 E0 R 4 E1 IR Given Register 00H 31H register 01H 02H and register 02H 17H RR OOH gt Register 00H 98H C 1 RR gt Register 01H 02H
166. ress is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3F80N8 UM REV1 10 CALL Call Procedure CALL Operation Flags Format Examples dst SP lt 1 SP lt PCL SP c SP 1 SP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 3 14 F6 DA dst 2 12 F4 IRR opc 2 1
167. rking register pair RRO contains the value 1AH in register and 02H in register R1 The statement INCW RR0 increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW 2 R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP RRO LD 2 1 R2 R0 JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3F80N8 UM REV1 10 IRET Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal IRET Fast FLAGS lt SP PC lt gt IP SP lt SP 1 FLAGS lt FLAGS lt FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles
168. rrupt enable bit Always logic O 0 Disable allinterrupts processing Fastinterruptlevel 1 Enable all interrupts processing selection bits Fast interrupt enable bit 0 Disable fast interrupts processing Not used for the 1 Enable fast interrupts processing S3F80N8 OOOO 3 OO0O 00 o 0 00 Figure 5 5 System Mode Register SYM 5 8 ELECTRONICS S3F80N8 UM_REV1 10 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH R W IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt level enable bit 0 Disable mask interrupt level 1 Enable un mask interrupt level Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommen
169. rs have developed the S3F80N8 by integrating the following peripheral modules with the powerful SAM8RC core Three programmable I O port including two 8 bit ports one 6 bit port for a total of 22 pins 28 pin One 8 bit basic timer for oscillation stabilization and watchdog functions system reset One 8 bit timer counter with selectable operating modes The S3F80N8 is a versatile general purpose microcontroller which is especially suitable for use as MWO controller It is currently available in a 28 pin SOP 32 pin SOP and 32 pin SDIP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU SAM8RC CPU core Memory e ROM 8K Bytes flash or mask ROM e RAM 144 Bytes Instruction Set e 78 instructions e Idle and Stop instructions added for power down modes Instruction Execution Time 4001 at 10 MHz fosc minimum Ports e Two 8 bit I O ports PO P1 one 4 bit 1 0 ports P3 P1 can be used for 8 external interrupt One 6 bit I O port P2 Open drain output each pin with big driving current 80 function gt 26 I O 32 pin e Two 8 bit I O ports PO P1 P1 can be used for 8 external interrupt One 6 bit I O port P2 Open drain output each pin with big driving current 80 function gt 22 I O 28 pin Interrupts e interrupt levels and 10 interrupt sources 8 external interrupt by falling edge or both rising edge and falling edge and 2 internal interrupt e Fas
170. s when Vpp is equal to the minimum oscillator voltage range idth Vpp 0 1V 0 1V Figure 12 5 Clock Timing Measurement at ELECTRONICS 12 7 ELECTRICAL DATA S3F80N8 UM_REV1 10 Table 12 9 Input Low Width Electrical Characteristics TA 40 to 85 C Vpp 2 0V to 5 5 V Interrupt input low tity tint All interrupt Vpp 5 V width nRESET input low tres Input Vpp 5 V width NOTE If width of interrupt or reset pulse is greater than min value pulse is always recognized as valid pulse Figure 12 6 Input Timing for External Interrupts nRESET Figure 12 7 Input Timing for nRESET Table 12 10 LVR Circuit Characteristics 25 C Vpp 2 0 V to 5 5 V Mn Tp Max Unit fet 3 6 3 9 4 2 UT 12 8 ELECTRONICS S3F80N8 UM_REV1 10 ELECTRICAL DATA VLVR MAX VLVR VLVR MIN Figure 12 8 LVR Reset Timing S3F80N8 Figure 12 9 The Circuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using power capacitor near S8F80N8 like Figure 12 9 Table12 11 ESD Characteristics Parmeter Sms coo we um Electrostatic discharge ELECTRONICS 12 9 ELECTRICAL DATA S3F80N8 UM_REV1 10 NOTES 12 10 ELECTRONICS S3F80N8 UM_REV1 10 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F80N8 microcontroller is currently available in 28 SOP 32 SOP and 32 SDIP package
171. sary to define working register areas in different non contiguous areas of the register file In Figure 2 6 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70 RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO AOH RP1 lt nochange CLR RPO RPO lt OOH RP1 lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 24 8 Byte Slices 00001 X XX 8 Byte Slice 16 Byte Contiguous Working 00000XXX 8 Byte Slice Register block RPO Figure 2 5 Contiguous 16 Byte Working Register Block 2 6 ELECTRONICS S3F80N8 UM_REV1 10 ADDRESS SPACES F7H R15 8 Byte Slice I FOH R8 Register File Contains 24 8 Byte Slices 8 Byte Slice Figure 2 6 Non Contiguous 16 Byte Working Register Block 16 Byte non Contiguous Working Register block 11110XXX RP1 00000XXX RPO PROGRAMMING Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRP0 80H RPO lt 80H
172. se steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register FAST INTERRUPT SERVICE ROUTINE When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically D RELATIONSHIP TO INTERRUPT PENDING BIT TYPES As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software PROGRAMMING GUIDELINES Remember that the o
173. sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes mer eee 0000 1000 0111 note note 0110 note Always false Always true Carry No carry Zero O note 1111 note note 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal 1110 note Not equal 1001 Greater than or equal 0001 Less than 1010 Greater than 0010 Less than or equal 1111 note Unsigned greater than or equal 0111 note Unsigned less than 1011 Unsigned greater than 1 0 0 1 1 0 1 0 O O R S XOR V 0 XOR V 1 0011 Unsigned less than or equal NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 Foroperations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is incl
174. sing mode only Carry Flag C 0 Operation does not generate a carry or borrow condition 1 Operation generates carry out or borrow into high order bit 7 Zero Flag Z Operation result is non zero value Operation result is zero Sign Flag S Operation generates negative number MSB 1 R Read only W Write only R W Read write Bit number MSB Bit 7 LSB Bit 0 Description of the effect of specific bit settings Not used Type of addressing that must be used to address the bit 1 bit 4 bit or 8 bit ELECTRONICS RESET value notation Not used x Undetermined value 0 Logic zero 1 2 Logic one Figure 4 1 Register Description Format 4 3 CONTROL REGISTERS S3F80N8 UM_REV1 10 BTCON Basic Timer Control Register D3H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset Disable watchdog timer function Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits fosc 4096 s 1 1 mvaiasetinss O 1 Basic Timer Counter Clear Bit 1 o No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for all Timers 2 EN No effect Clear both clock frequency dividers NOTES 1 When 1 is set to 1
175. sk The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM RPoO R1 gt RO 0C7H 02H Z 1 TCM RO R1 gt RO 0C7H R1 02H register 02H 23H Z 0 TCM 00H 01H gt Register 2BH register 01H 02H Z 1 TCM 00H 01H Register OOH 2BH register 01H O2H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2 Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET TM Test Under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are
176. specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO 0C7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM RO R1 gt RO OC7H 02H Z TM Ro R1 RO 0C7H R1 02H register 02H 23H Z 0 00H 01H gt Register 00H 2BH register 01H 02H Z 0 TM 00H 01H Register 2BH register 01H 02H register 02H 23H Z 0 TM 00H 54H gt Register 00H 2BH Z 1 In the first example if working register R0 contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM R0 R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3F80N8 UM REV1 10 WFI wait for Interrupt WFI Operation Flags Format Example The
177. ss Vss Vss Vss Q N 10 U ld 0S Figure 15 3 50 Pin Connector Pin Assignment for user System Target Board User System J2 Joj euuo Uld 0S I 5 g U O 5 2 9 Figure 15 4 TB80N8 Probe Adapter Cable 15 6 ELECTRONICS S3F80N8 UM_REV1 10 DEVELOPMENT TOOLS Third parties for Development Tools SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer In Circuit Emulator for SAM8 family OPENice i500 SmartKit SK 1200 OTP MTP Programmer SPW uni AS pro US pro QGW uni 8 gang programmer Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools 8 bit In Circuit Emulator OPENice i500 System TEL 82 31 223 661 1 FAX 82 331 223 6613 E mail openice aijisystem com URL http Awww aijisystem com SK 1200 Seminix TEL 82 2 539 7891 FAX 82 2 539 7819 E mail sales seminix com URL http www seminix com ELECTRONICS 15 7 DEVELOPMENT TOOLS OTP MTP PROGRAMMER WRITER S3F
178. st opc dst 2 4 D0 R D1 IR Given Register 00H 9AH register 02H 03H register 0BCH and C 1 SRA 00H gt Register 00H 0CD C 0 SRA 02H gt Register 02H register 0 In the first example if general register 00H contains the value 9AH 10011010B the statement SRA 00H shifts the bit values in register 00H right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value OCDH 11001101B in destination register ELECTRONICS 6 79 INSTRUCTION SET S3F80N8_UM_REV1 10 SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src If src 1 1 and src 0 Othen RPO 3 7 lt src 3 7 If src 1 Oand src 0 1 then RP1 3 7 lt src 3 7 If src 1 0 and src 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 RP1 4 7 lt 4 7 RP1 3 1 The source data bits zero LSB determine whether write both of the register pointers RP0 and 1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location 0
179. t if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 81 IR Given 12H R1 34H R2 register 0FH and register 31H 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RR0 addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RR0 LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI Ifthe value of the SYM register is 01H the statement DI leaves the new
180. t interrupt processing feature 1 2 S3F80N8 UM REV1 10 Timers e Basic timer One programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e One 8 bit timer with three operating modes Interval capture and PWM mode Two Power Down Modes e Idle mode only CPU clock stops e Stop mode system clock and CPU clock stop Oscillation Source e External Clock 1 0 to 10MHz fosc e External RC oscillator Mode 2 1 to 10MHz Built in RESET Circuit LVR Low Voltage check to make system reset Viyg 7 2 2 3 9V by smart option Operating Temperature Range e 40 C to 85 Operating Voltage Range e 2 0V to 5 5V Package Type e 28 SOP 32 SOP and 32 SDIP package ELECTRONICS S3F80N8 UM_REV1 10 PRODUCT OVERVIEW BLOCK DIAGRAM P0 0 P0 7 P1 0 P1 7 INTO INT7 Internal Bus XIN XOUT P2 0 P2 1 Port I O and Interrupt Port 2 P2 2 CLO exam iq Control P2 3 TOCLK P2 3 TOCLK 2 4 2 5 2 4 P3 0 P3 3 8 Bit Port 3 Timer Counter 144 byte Register File Lil TEST nRESET J VDD Vss LVR Figure 1 1 Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW PIN ASSIGNMENT Vss XOUT XIN VPP TEST P0 0 P0 1 nRESET P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 P2 5 P3 3 P3 2 Figure 1 2 Vss XOUT XIN VPP TEST P0 0 P0 1 nRESET P0 2 P0 3 P0 4 P0 5 P0 6 P0 7 P2 5
181. t src 3 12 C2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 02H R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 0000001 0B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3F80N8 UM REV1 10 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 lt RA Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src
182. ter File BbtRegster sp ADDRESS OPCODE Point to One Register in Register File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3F80N8 UM_REV1 10 INDIRECT REGISTER ADDRESSING MODE Continued Register File Program Memory Example REGISTER Instruction dst eo References OPCODE Points to Program Register Pair 16 Bit Memory Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F80N8 UM_REV1 10 INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPoorRP 1 L or RP1 Program Memory S dst src p Register Pat wawaman Register OPCODE Foi to ime ADDRESS Working Register Address 1 of 8 OPERAND Sample Instruction Value used OR R3 R6 Instruction ADDRESSING MODES Selected RP points to start fo working register block Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3F80N8 UM_REV1 10 INDIRECT REGISTER AD
183. terrupt Groups A B and C note SS oS Group priority undefined 6 Interrupt Subgroup C Priority Control Bit IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group Priority Control IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 2 Interrupt Group Priority Control IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQ0 gt IRQ1 RQ1 gt IRQ0 NOTE Interrupt Group IRQ0 IRQ1 Interrupt Group B IRQ2 IRQ3 IRQ4 Interrupt Group C IRQ5 IRQ6 IRQ7 _ ELECTRONICS 4 1 CONTROL REGISTERS S3F80N8 UM_REV1 10 IRQ Interrupt Request Register DC Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Not pending Pending 6 Level 6 IRQ6 Request Pending Bit Not pending Pending 5 Level 5 IRQ5 Request Pending Bit Not pending Pending 4 Lev 14 IRQ4 Request Pending Not pending Pending 3 Lev I 3 IRQ3 Request Pending Not pending Pending 2 Lev I 2 IRQ2 Request Pending Not pending Pending 1 Lev
184. that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the S3F80N8 interrupt structure the timer 0 overflow interrupt IRQ2 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address
185. tiated by RESET 12 4 ELECTRONICS S3F80N8 UM_REV1 10 ELECTRICAL DATA Table 12 5 Input output Capacitance TA 25 C Vpp 0 V Parameter Symbol Cr we Input f 2 1 MHz unmeasured pins Capacitance are connected to Vss Output Cour Capacitance Capacitance Table 12 6 System Oscillation Characteristics TA 40 to 85 Crystal Oscillation 4 5V 5 5 V a Frequency Ceramic Oscillation 4 5V 5 5 V 1 10 Frequency External Xin input 4 5 V 5 5 V 1 10 Clock Frequency a EE ELECTRONICS 12 5 ELECTRICAL DATA S3F80N8 UM_REV1 10 CPU Clock 10 MHz 8 MHz 4 MHz 3 MHz 2 MHz 1 MHz Supply Voltage V Figure 12 3 Operating Voltage Range Vcc XOUT XIN Figure 12 4 RC Oscillation Mode2 12 6 ELECTRONICS S3F80N8 UM_REV1 10 ELECTRICAL DATA Table 12 7 RC Oscillation Mode2 Characteristics TA 40 C to 85 Vpp 2 0V to 5 5 V Accuracy of RC e Vpp 5V 10 T4 25 Oscillation 2 NOTES 1 The resistor is connected between Vpp and pin We recommend using 40K 9 resistor for 4MHz and 20K 9 for 8MHz 2 Data based on characterization results not tested in production Table 12 8 Oscillation Stabilization Time 40 C to 85 C 2 0V to 5 5 V Oscillator Test Condition M Crystal fx gt 1 MHz Ceramic Oscillation stabilization occur
186. tions All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics objectives Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 semiconductor
187. to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3F8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP7 IP0 FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F80N8 UM_REV1 10 FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When a fast interrupt occurs the contents of the FLAGS register are stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the SSF80N8 microcontroller the service routine for any one of the eight interrupt levels IRQO IRQ7 can be selected for fast interrupt processing PROCEDURE FOR INITIATING FAST INTERRUPTS To initiate fast interrupt processing follow the
188. uded in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F80N8 UM REV1 10 ADC Add with carry ADC Operation Flags Format Examples dst src dst dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 H Set if there is a carry from the most significant bit of the low order four bits of the resu
189. use an EXIT statement Before After Address Data IP 0052 Data Address Data PC 0060 PCL old 60 Main PCH SP 0022 Exit 22 Data Memory Stack ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation In application programs a IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6 _ Example The instruction IDLE stops the CPU clock but not the system clock NOP NOP NOP ELECTRONICS 6 43 INSTRUCTION SET S3F80N8 UM REV1 10 INC Increment INC Operation Flags Format Examples dst dst lt dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cyc
190. vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location o gi d t mm Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends execute DI restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above
191. writing a to the TOCON O interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register TODATA The match signal generates a timer 0 match interrupt TOINT vector ECH and clears the counter If for example you write the value 10H to TODATA the counter will increment until it reaches 10H At this point the timer 0 interrupt request is generated the counter value is reset and counting resumes Interrupt Enable Disable Capture Signal 8 Bit Up Counter lt TOINT IRQ2 TOCON 0 8 Bit Comparator TOCONO Match INT Pending TO PWM Output P2 4 TOCON 5 4 Timer 0 Buffer Register Match Signal TX Overflow Signal TOCON 3 Timer 0 Data Register Figure 10 6 Simplified Timer 0 Function Diagram Interval Timer Mode ELECTRONICS 10 9 BASIC TIMER and TIMER 0 S3F80N8 UM_REV1 10 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TOPWM P2 4 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from 00H Although you can use the match signal to
192. you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET S3F80N8_UM_REV1 10 INSTRUCTION SET NOTATION Table 6 2 Flag Notation Conventions Carry flag Zero flag O Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Z S V D H 0 1 Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols dst Destination operand src Source operand Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register D5H RP Register pointer Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc Opcode 6 8 ELECTRONICS S3F80N8 UM_REV1 10 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode
193. you use STOP instruction PC is changed to reset address ELECTRONICS 4 27 CONTROL REGISTERS S3F80N8 UM_REV1 10 SYM System Mode Register DEH Reset Value 0 _ 0 0 Read Write R W _ _ R W R W R W R W R W Addressing Mode Register addressing mode only 7 Tri state External Interface Control Bit 1 Normal operation disable tri state operation Set external interface lines to high impedance enable tri state operation 6 5 Not used for the S3F80N8 4 2 Fast Interrupt Level Selection Bits 2 1 Fast Interrupt Enable Bit 3 lo Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit 4 EN Disable all interrupt processing Enable all interrupt processing NOTES 1 Because an external interface is not implemented SYM 7 must always be 0 2 Youcan select only one interrupt level at a time for fast interrupt processing 3 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 4 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O 4 28 ELECTRONICS S3F80N8 UM_REV1 10 CONTROL REGISTER rimer 0 Contro Register D2H Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer 0 Input Clock Selection Bits DUNT NN External c

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