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Q552.1A LA, 3122 785 18990, 100402

Contents

1.
2. 1E01 1 D5 3E79 F2 IE23 C2 1E01 2 H5 3E80 C10 IE48 G2 1202 C13 3E82 D10 IE51 G10 1E12 D4 3E83 E10 IE52 H2 1E18 F4 3E84 E10 IE53 D1 1E19 F4 3E85 F10 1 54 E1 1E22 H4 3E86 F10 IE55 F1 RESET AVPIP Ss 1E23 14 3EA1 D6 IE56 E9 1224 111 2 06 57 9 AP SCART QUT R 3E63 1 1225 14 7 1 A7 1 59 E8 UN UO 2EA4 IEG7 c 1E26 G11 7 2 13 1 60 6 AP SCART OUT R gt e 4 T 1227 11 7 3 13 IE61 4 1008 _ 8 470R 1 100 16V gle o 5 1231 B4 7 4 B7 1 62 H10 7 01 1 6 ieu 8 tos 1E45 A11 3EB1 E6 IE67 A8 N oly 8 de duh af ale T E 5 1E48 C11 3EB6 2 H13 IE89 D7 PUMH7 1E49 D11 3EB6 3 H13 IE90 D7 O IN2 1 20 FE61 L TES 1E52 F11 4 _ IE91G6 j aEA
3. 1M84 dL L 660525 fd on een amp 20051 5 27502 523021 611057 3161622001 5 27203 6102202 2364 09 al Mom 5 1M83 was 980759955 9 a 7103 E uqta 4 1202 3104 313 6381 2 11 84 8 T8208 BERIE 1620 8 zu 47807 59 2804 9 9 7C20 7C22 es 7001 002 3104 313 6381 2 18770 602 100216 eps 100218 back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM LZ 10 5 AL1 820400090592 AmbiLight Common Everlight LED Common 1 AL1 A Everlight 15 LED Common 10 11 12 13 14 1M83 C1 2B00 E8 e 2801 F8 2802 E9 mem d 2803 114 3V3 A FH12 25S 0 5SH 55 FBO1 9 24V O AUN 2804 TEMP SENSOR 2805 3V3 FB06 BLANK gt e FBO7g_ PROG 08 FB10 LATCH 11 e SPI CS 3V3 12 7B26 1 TLC5946RHB 3800 1 1 8 31 1508 24 gt 3B18 26 PWM R1 PWM G1 PWM B1 PWM G3 PWM R3 PWM R2 PWM G2 PWM B2 PWM B3 PWM G4 PWM R4 PWM B4 PWM B5 PWM G5 PWM R5 DATA
4. 1205 B2 1FC1 B4 1FC2 B4 1FC3 C4 1 4 1FC5 04 FECT dees 1FC6 F4 V R VGA 2FC1 B4 UNE 2FC2 B4 PUE 2FC3 C4 C4 FOS Eus 2FC5 04 2FC6E4 518 E TANEL 2FC7 E4 1E05 0 2FC8 F4 3FC1 D3 2 Ux a gt a 3FC2 E3 gle 8 3FC3 C6 VGA S RS 06 FEE erro ss 3FC5 A6 i DRM 20090 H SYNC VGA 3FC6 B6 7 15 g an SALES 6FC1 B5 6FC2 B5 Wy 6FC3 C5 M 5 V SYNC VGA 6FC4 C5 o MEN Sob D 6FC5 D5 ETE E g ge RS 6FC6 E5 RES a 9FC1 gt VGA SDA EDID HDMI oFC7 E5 i Pu n 9FC2 gt VGA SDA EDID 6FC8 F5 i 5 nd 9FC1 D6 5 5 97768 9FC2 E6 9FC3 E6 E snes 9FC3 gt VGA SCL EDID HDMI E 4 E 6 o lt gt VGA SCL EDID 9FC5 C6 9FC6 06 D UE FFC1 A4 i i FFC2 B4 ae FFC3 C4 FFC4 C3 F 8 PAVOR F FFC5 FFC6 D2 1 d FFC7 04 FFC8 04 FFC9 4 IM 0 22 TUNER HDMLS 8204 000 8994 18770 508 100118 5 100118 back to 2 Circuit Diagrams PWB Layouts Q552 1A LA ES
5. 2800 A2 2801 A3 2802 A3 3B02 1 C7 3B02 2 B6 3B02 3 C7 1V8 2 DDR2 VREF DDR Eae d 2 03 3802 4 B6 2804 3B03 09 2 05 3B04 1 C12 2806 A4 3B04 2 B13 s s s 4 s s 4 2807 4 3B04 3 812 E CN E 8 8 5 N iS meme TIT SS 8 2809 B8 3B05 1 C13 L d 2B10 B8 3805 2 C13 2811 B9 3 05 3 12 EDE1108AGBG 1J F 58 2B12 B9 3805 4 C13 H8 AT T POINT DDRZAI p 2813 9 3806 H
6. M 00 _1 53 11M59 5 16517 I p 1 G4I 1 86 1 SSN VS 69 Ur 0691 V o z 1186 TREE T EE COXI 5154 08 1 1 e P VB 3n s t 29 V 0 an 61 ae HL NIDE x RSA pe TEE 2 169 E gt e E lt A j 54 04 5 5 L LI a 0 i Y q 1 D 0 O 7800 7220 1 09 BB17 gt e 81 Ps 2 0087 gt 2 lt D gt 9048 7800 lt 5 E JE 8700 E ilg LO M bsa LL 2 lt 8 4 GZ4 i 3581 2 rs N 6 AN 385 i g 3F31 id stas as 5 5 IN 29 5 TF s 8 Pg O i HAG man 8584 2 5273 s HHIH HSS 5 2 62 2 x GO
7. 3V3 3V3 1 7GE1 o c 5 e ul 5 PDTC114EU OS w z PNX SPI CSBn ue IGEO B PNX SPI CLK 18 ee ate BL SPI CLK 47R 3GEO 1 17 1 8 BL SPI SDO PNX SPI SDO 16 1 3 6 3 47R AMBI SPI CLK OUT R 15 478 5 4 3GE1 4 a AMBI SPI SDO OUT R AMBI SPI SDI OUT G1 R 14 3GE3 47R RES lt PNX SPI SDI BL SPI SDI 13 3GE4 47R RES E 478 C PNX SPI CLK 7 96 0 2 2 gt BL SPI CLK PNX SPI SDO 6 90 0 3 3 Ss BL SPI SDO BL SPI SDI 9GE1 S PNX SPI SDI 9GE2 PNX SPI CS BLn IGE14 5 9GEO 4 4 gt BL SPI CSn PNX SPI CS AMBIn 9GE3 AMBI SPI CS OUTn R2 R Buffer Direct E 2010 02 div table 2GEO A2 3GEO 1 B4 3GEO0 3 B4 3GE1 3 B4 3GE1 4 B3 3GE2 A4 B4 3GE4 GEO 7GE1 A4 9GEO 1 C3 9GEO 2 C3 9GE0 3 9GE1 C3 9GE2 D3 9GE3 D3 IGEO B3 IGE1 D2 LVDS Non DVBS 8204 000 8957 ____ 18770 568 100125 5 Circuit Diagrams PWB Layouts Q552 1A LA E 10 15 09 820400089812 Non DVBS Con Non DVBS Connector Board Non DVBS Connector Board
8. 1 i 7 e m gil 1101 2 86 SES ET SN 623 63 6FC7 6 5 a 6FC3 6FC2 6FC1 v 6 6FC8 3104 313 6364 3 back to div table 2010 Apr 02 1 5 18770 580 100216 5 100219 Circuit Diagrams PWB Layouts Q552 1A LA Overview bottom side 616 9 a m p UH yp 2 JE DOOR 3104 313 6364 3 NI enero enero J VZ J OC GLOVES f Op Senn Hi 0 1 ae x JAN L AY 201 BE 2 551 40 jr
9. 5FEO IF63 IF64 2V5 BRA gt s s s s 1V2 BRA VDDC 30R cs wmwtioutsutottsoutsg ow T m iL tc m AGND 2 E s s s 2 s s VY Y 4 3V3 BRA N cw co eg C gt LL Q LL m e AGND 5FE5 IF67 IF68 m m lt q 1V2 BRA DR1 30R we r r rle 5 2 e IF69 HL 5FE8 s s a 2V5 BRA 30R 1FEO e gt uas E 25M4 412 g 2 Pre N N roosira S 8 amp 2888 eses 59 2 AGND AGND AGND VDD VDD a 5 8 5i 2FH5 1 5 18 a 58 E 3FG6 4 4 5 gt TS FE VALID DFE6 3 53 4 9F27 4 5 1S DVBS VALID 2 Ex DFE7 IF 2FG4 10n IF17 30 IF E 2FG6 10 29 55 BEES 2 9F27 2 7 __ TS DVBS SOP 2FG7 100n BFE1 28 59 3FG6 3 3 6 TS FE SOP 2FG8 100n e Z7 _ BEES AGND BFE 52 9F28 sp TS DVBS CLOCK 2289 100n 3 24 L 2FH6 100n e 25 N AD VREF 61 3FG7 33R 4 TS FE CLOCK AGND BFE5 i E 2FH7 100 26 60 3FG6 2 2 7 TS FE DATA L DFF1 AGND 39 DTCLK 38 1 9 27 1 8 Se T
10. OOOOOOO O O O OOOOOOO O O O O O OOOOOOO OOOOOOO O O O O O O O O O O O O O O O OOOOOOO gt T Transparent top view Figure 8 3 Internal block diagram and pin configuration back to 2010 Apr 02 div table LVDS for flat panel display single dual or quad channel analog CVBS analog Y C analog audio 25 18770 308 100217 5 100217 IC Data Sheets Q552 1A LA EM 8 4 Diagram Audio TPA3120D2PWP IC7D10 Block diagram SIMPLIFIED APPLICATION CIRCUIT 12002 1 pF 0 22 uF Left Channel ll H 22 uH 470 uF Right Channel 4 mL 1 uF 0 68 uF 0 68 uF lt gt BYPASS dl AGND 22 uH 470 uF 0 22 10 V to 30V 10 V to 30 V VCLAMP Shutdown Control 1 uF Mute Control a Gain Control Pinning information PWP TSSOP PACKAGE TOP VIEW PVCCL 10 PGNDL SD 2 PGNDL PVCCL 3 LOUT MUTE 4 BSL LIN AVCC RIN 6 AVCC BYPASS 7 GAINO AGND 8 GAIN 1 AGND 9 BSR PVCCR 10 ROUT VCLAMP 11 PGNDR PVCCR 12 PGNDR Figure 8 4 Internal block diagram and pin configuration back to div table 18020 142 eps 100402 2010 Apr 02 GEJ E Q552 1A LA IC Data Sheets 8 5 Diagram DC DC TPS53126PW IC7U03 Block diagram D VREG
11. ssa 5880 p 2523 B6 255 G11 R 2526 A6 2S5P F5 3 5 3 2 2527 2560 A6 E 2528 B3 2561 A6 Jc T oum 2829 C6 2562 A7 A 4 2 5 A 2S43 B2 2S63 A7 als als 2545 F11 2364 A7 2546 F11 2865 A7 gt E 254 B12 2566 A7 Pp x 22 254 C11 2568 s 2 s s s s s S 8 m 2S4Q B3 2S6A A11 254 B4 256 A11 lt 2001 m _ 5593 2545 F5 256 11 B PNX85500 Sj mE 22 dm o LO Bi 3 i iaa B 2541 H11 2S6D B11 1V1 Ke s s s s A EP VDDA 1V1 020 5 58 ES 2540 D1 1 2S6E B1 1 e oo 3 2 E T d ae si si B 3 03 020 A 284V D11 2S6F C11 RATS 4 58 o q Pr eT eRT Tear oTr Ts ABs HDMI VDDA 2 5 021 ES 2S4W 011 2560 C11 3 M 9 I I Es VDDA 3vV3_TERM U22 m lt V5 LVDS 2547 D11 2S6H H11 L 2 25 ar x T 2547 E11 2S6K H11 s Al zT J 918 VDD 2V5 NZ 2 8 2 8 2550 E1 1 2S6L 1 1 ol 55 55155 55 5515 co L S E Tue a zg gT S S 2529 3 2V5 LVDS en e lt 2852 E9 256 C11 e e cie F 5 s Ec Pe a Ec I G s 2553 H11 256 C12 i an 878078078878 4718 2855 G11 2SHW 111 790042 gg jee as i uuu L 2556 G11 5580 A12 15 lt 3V3 STANDBY 2S57 G11 5S81 A12 1 ui v
12. 1 2 3 4 5 6 1 53 09 5754 1M09 5 9T50E7 S 1M20 B9 FC83 B4 1 59 A5 FT50 C7 1M71 E5 FT51 C7 AMBI SPI CLK OUT s 1T85 F4 FT52 D8 A AMBLSPLSDLOUT 61 gt d A 1786 B4 FT53 08 m 2170B3 FT54 D8 AMBI PWM CLK B2 gt 24 iu 3175 100p 2776 7 FT55 08 AMBLSPI CS OUTn R2 gt FT74 100R _ 2177 2177 A7 FT56 E8 P que TO 2178B7 FT57 E8 RC AMBLBLANK Ri gt LED PANEL 2779 B7 FT58 E8 AMBI LATCH2 DIS FT78 IT74 FT88 1 20 2180 B7 FT59 F7 200200 org RB ur B 3V3 STANDBY a 5 2183 4 FT64 E7 RLS 93 F e 2184 E4 FT68 D3 LED T5 109p 8 2185 F5 FT69 i Foss me E 2186 C7 FT70 A5 Wa 8 2T87D7 FT71A4 FT95 3T79 2788 07 FT72 5 3 0 v a 2789 07 7 4 258 0 58H 55 2190 E7 FT74 A4 FT5O 3T84 id 2791 F7 FT75 5 2792 F7 76 B4 317082 FT77 B5 3171 E7 FT78 1M09 TEN jd 3T85 3174 FT79 B4 100R 3175 A7 80 5 T 3176 A7 FT81 B5 3177 B7 FT82 B5 HOTEL TV 366 SEEDS BL SPI CLK vv 78 7 87 7 3190 RES 3179 7 FT88 B9 3V3 1F53 3180 04 89 B9 FAN CTRL1 3191 FT52 TE E gt MA 37881 gt 81 E4 90 9 FT68 5780 WR F153 3782 E4 91 lt P rs E C 3183 E4 92 B9 SCL BL
13. 10 11 12 13 14 TNR SER1 3501 1 E2 3501 2 3501 3 3501 4 3502 1 3502 2 E2 3502 3 E2 A 3802 4 3503 5 lt 3504 1 XO Do 3504 2 To 3815 B6 B23 XIO D05 3S1 R F7 A22 z XIO D06 Fas XIO D09 3S1T G7 E XH 3S1UG7 E25 e 1526 3815 3523 G7 25 lt TET 3524 G7 2 015 L 3S28 G7 B22 lt XIO OEn J C22 XIO WEn 3829 H7 B21 7500 11 E3 E21 NAND CE1n 7S00 5 A4 021 9800 5 9508 c5 t lt TD IS00 Pen E 1526 D N26 lt CA MDOO P cDo E a 23 x CA MDO3 24 p CA MDO4 s M25 z CA MDO5 M26 E CA MDO6 S L21 x CA MDO7 K23 lt CA VS1n gt 24 9500 E CA MOCLK 5 A CD2n 3V3 TS FE DATA SSIR TS FE CLOCK 3515 Gd i TS FE VALID 3S1T idi l TS FE SOP 3S1U 560R G 1X06 T21 TS FE DATA TS FE DATA 3523 HOLE T23 lt TS FE ERR RES 470R T22 p TS FE CLOCK N TS FE CLOCK 3824 R23 lt TS FE VALID RES 470R R22 lt TS FE SOP TS FE VALID 3S28 4 TS FE SOP 3829 nem 470R 5 6 7 8 9 10 11 12 13 14 OBEN 8204 0008050 18770 511 100118 eps 100218 2010 02 back to div table Circuit Diagrams PWB Layouts Q552 1A LA ES LEM PNX S
14. 10 10 1 84 10 2001 B6 7203 7204 4 7205 5 9 LED Lit 4 iteOn 8204 000 8969 AL 2K10 3104 313 63812 ____ 18770 610 100212 5 100218 Circuit Diagrams PWB Layouts Q552 1A LA 10 LI 9 LED LiteOn 9 LED LiteOn 1 2 3 4 5 6 7 8 9 10 11 12 13 2D10 D13 M 3002 1 A1 A M A 3002 2 5 BC847BS COL 3D02 3 B1 gt 3D02 4 C1 3 gt 3005 3 C1 3005 4 01 E m 3D10 B12 Y nad estes cess B ma T 3011812 y 5 6 5 6 5 6 5 6 5 6 5 6 270R 3D12 B12 525 2 gt 3D13 1 C12 5 i 3013 2 12 ics 3013 3 12 C 56 3013 4 012 mee eU 7300 B5 apige 7301 B6 42 Bun D 7303 B8 i 3E 7304 B10 D Bc D 7305 11 7001 1 2 7001 2 B2 7002 2 2001 B1 2002 C1 E 00301 1 2 3 4 5 6 7 8 9 10 11 12 13 DECR 9 LED LiteOn 8204 000 8969 _____ L AL 2K10 3104 313 63812 ie 18770_611_100212 eps 100212 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 LIN 10 3 AL1 820400089703 15 LED LiteOn 15 LED LiteOn 15 LED LiteOn 1 2 3 4 5 6 8 9 10 1 84 A10 2001 B6 7203 A3 7204 A4 7205 A5 5 FD18C7 FH12 25S 0 5SH 55
15. 2010 02 div table USB Hub B01 USB Hub Circuit Diagrams and PWB Layouts Q552 1A LA ES LEN IF44 5V a 3V3 10 LO N Y EN E jd 5V USB1 4 3F26 1 err 1 100K IF43 3F26 2 s s s s s s USB OC1n 2 7 100K cN co c 3F26 3 Nao aS 6 3 6 LL LL LL LL LL LL LL LL CN CN CN 100 N e E 100 3V3 o gt 7F25 3V3 USB DP ss 9F25 USB DP2 24M USB DM 9F26 USB DM2 D eala Es USB HUB gt 1 gt DNIIPRT DIS 7 E USB DP1 Es m XTALOUT USBDM DNIIPRT DIS M1 5 gt USB DM1 o o IF30 BC_EN1IPWRTPWR1 5V USB1 1 RESET USBn 26 IF36 USB DM1 FF34 gt s 9 RESET gt e s 2 eer DN2IPRT DIS P2 USB DP2 4 2 1 2 gt 42 USBDM DN2IPRT DIS USB DM2 SUSP INDILOCAL PWRINON EN2IPWRTPWR2 E3 10K d IF37 2923034 USB DP 4 7 31 DP OSC3 19 u USB OC3n IF32
16. Motion accurate VIDEO pixel processing DECODER SCALER SSIF LR AUDIO DEMOD DE INTERLACE AND DECODE AND NOISE REDUCTION AUDIO DACS SPDIF AUDIO IN AUDIO DSP AUDIO OUT HDMI RECEIVER DS SYSTEM 500 MHz DRAWING CONTROLLER MIPS32 ENGINE 8051 24KEf CPU Scatter Gather TS Demux PWM x SPI UART GPIO Flash USB2 0 SD Ethernet x10 Memory MAC Card Pinning information PNX8550xE 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11131517 19 2129 25 ball A1 index area OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOO OOOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OO OO O O O O O OO OOO OOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOO OOOOOOOOOO OOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOO OOO OOO O O O O Qs O O lt lt lt O O O O O OO c m F Om O O O O gt UJ O O O O O gt
17. 1210 5002 5005 2012 2201 ONCNCNCN 22u 1006 2208 1008 25V 220 7 3002 2 2 015 1 C847BS COL 4 3002 4 5 4K7 D15 2 C847BS COL 4K7 1009 5001 5004 _ 1007 2011 3002 v Y YYW 1 21 ui ai 22u ines 220R mom 3002 B4 3002 C4 3004 2 3D06 1 F4 3D06 2 F4 3D06 3 F3 3D06 4 F3 3D09 A3 3D10 1 D8 3 3 5 3D10 2 08 3010 3 07 MAINS SWITCH 3D10 4 D7 eo 3014 1 8 3014 2 8 1035 3014 3 7 7011 2 5 4 2 DETECT2 3D14 4 B7 BC847BS COL 3D15 1 E2 GND AUDIO 3D15 2 E3 3D15 4 D5 3D16 A5 5001 C7 5002 C7 5003 7 5004 C8 5005 C8 1038 5007 4 4 5008 A6 2 2 6001 3 3 7D03 1 A5 1735446 3 7D03 2 F5 7D10 1 B6 7D10 2 E5 7D11 1 D2 F 7D11 2 D3 7D13 1 E1 7D13 2 E2 7D15 B3 Ben 7D15 C3 WEM a 100K 10u Sn 02 FD03 B1 05 LEFT SPEAKER 6 2 7 B 1 3 5 4 GND AUDIO 2016 1029 2D17 1100 ED 100 ID30 AUDIO MUTE UP ID37 A STBY 2 4 1989 22K 3D10 4 22K 3D10 3 22K 3D10 2 22K 2021 220n 2D27 7D11 1 BC847BS COL 43V3 STANDBY 10 47K s Boa elg 70102 388 8 GND AUDIO 8 8 TPA3120D2PWP 2 ID36 7013 1 BC84
18. Ite lt 2165 6 3 e N m VINT VIO 7GAO XC9572XL 10VQG44C0100 VOGINT PXCLK54 4 IXO1 43IGCK1 GCK2 1 IXO1 44IGCK2 GCK3 IXO1 1IGCK3 PNX SPI CS AMBIn 2 IXO1 2 PNX SPI CS BLn 3 IXO1_3 PNX SPI SDO 39 IXO1 39 PNX SPI SDI 20 IXO1 40 PNX SPI CLK IXO1_41 42 IXO1 42 GTS1 35 IXO2 3615781 GTS2 m 2 34lGTS2 GSR 2 33IGSR AMBI SPI CS OUTn R2 R AMBI PWM CLK B2 sy 29 AMBI SPI CS OUTn R2 2 2 7 3G14 100R 1 30 AMBI LATCH1_G2 lt 3G11 2 4 5 31 h 3G11 4V 32 CPLED3 37 CPLED2 38 11 9 D tc 24 es O ON ro gs2 10 5 5 N N N 3V3 a U a DEBUG ONLY 1G36 1G35 1 L 2 1 8 1008 e 2 2 3GA2 2 2 7 1008 FGA6 3 3 3GA2 3 3 6 100R FGA4g 4 4 3GA24 4 5 10081 FGA5 e 5 e 9 FGA3 6 t lt d 3 1 1 SD51022 ale c L 418 LI LI LI LI 06 peace div table IGA3 C11 2009 10 22 18770 567 100125 eps 3G11 2 3613 7 3GA1 E6 3GA2 3 G3 3GA5 2 B12 3GA6 1 F13 3GA6 4 F12 6GAO F12 6GA3 F13 7GA1 2 013 9GAO0 H5 FGA1 B4 FGA4 G4 IGAO C11 3G11 4 E4 3G14 E4 3GA2 1 G3 3GA2 4 G3 3GA5 3 B12 3GA6 2 F13 5GAO 6GA1 F12 7GAO D5 7GA2 1 E12 9GA1 D7
19. 18770 504 100118 eps 100118 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 LI HDMI amp HDMI amp CI 1F75 B5 2F62 B10 2F70 B10 2F75 B8 2F80 B9 2F86 D1 2F93 C2 3F76 C2 3F80 C9 5F71 B9 6F72 C7 9F02 A8 9F71 E4 FF00 B2 FF76 B1 IF12 C9 IF72 C5 IF77 B6 IF82 C4 IF90 D7 1T01 A1 2F63 C9 2F71 A7 2F76 B9 2F81 B1 2F88 E5 2F94 D7 3F77 C4 3F81 C9 5272 4 TF70 08 9F03 A8 AF70 B3 FF01 C4 FF81 C1 IF13 C9 IF73 B6 IF78 B8 IF86 C5 2F59 B1 2F64 C9 2F72 A9 2F77 B9 2F82 B9 2F90 C6 3F71 C7 3F78 C7 3F82 B10 5F73 C5 TF75 9F04 B3 AF71 B3 FF71 A1 FF82 C2 IF14 C9 IF74 B8 IF79 C5 IF87 C2 2F60 B1 2F65 B10 2F73 A9 2F78 B6 2F84 C1 2F91 D6 3F72 C7 3F79 1 B8 5 66 C10 5F74 B10 9F00 A6 9F05 C4 AF72 B9 FF74 B1 IF10 A5 IF15 C9 IF75 B6 IF80 B8 IF88 D2 2F61 B1 2F66 C10 2F74 B6 2F79 B8 2F85 C4 2F92 C7 3F75 D2 3F79 4 B8 5F70 D6 5F76 B10 9F01 A6 9F06 C4 AF73 B9 FF75 B2 IF11 A5 IF16 B10 IF76 B8 IF81 B6 IF89 D5 1 2 3 4 5 6 7 8 9 10 IF10 IF11 s A 1101 A TX31XX PNX IF P FF71 S 5 5
20. lt 5 3C00 4 4 10K 3000 3 6 10K 200020 Y en 7104 B6 Ld dni LTW 008RGB LTW 008RGB LTW 008RGB 7105 5 zi u VA 5 6 Blue 7200 F8 4 BC847BS COL 3 WA 1 7201 F9 5 m 3 B 7202 F10 ue 7B50 1 T 7B50 2 B3 5 em G 7B51C3 7 20 1 1 5 7C20 2 F3 7 22 G3 FB70 B3 FB71 C3 FB72 03 FCO1 2 1 3C06 1 8 e 10K 1 L i 7 3 06 2 gt L PWM R3 lt e 1 2 3 4 5 6 8 9 10 11 12 AL 2 1 0 LiteOn 5 2009 10 28 15 LED Common 8204 000 8978 EY 2 20090703 18770 601 100212 eps 100212 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM 67 10 2 820400089691 9 LED LiteOn 9 LED LiteOn AL2A 9 LED LiteOn 1 2 3 4 5 6 7203 7204 7205 LTW 008RGB LTW 008RGB LTW 008RGB Blue 5 6 lt 24 Green 1 2 1 Red 3 4 sls B003 B004 E back to 2010 Apr 02 div table SPI CLOCK BUF 1M84 SPI DATA OUT SPI DATA RETURN PWM CLOCK BUF SPI CS LATCH PROG BLANK TEMP SENSOR YY ww VW ww ESENCO N 2004 24V p gt 7 gt 7 7 Ne 7 M x
21. LL AS ESI Ep HE e exe QE RC bsid 5 s 2576 CHARH O UM gt PEZ f 2010 Apr 02 back to 1X03 Hi AL 9 bc UP 2H OU 18770_581_100216 eps 100216 Styling Sheets Q552 1A LA EM 11 Styling Sheets 11 1 Matisse 32 46 MATISSE 32 46 SS 3 PosNp Rear Cover with left amp right diffuser Leading edge cover I O bracket side bracket bottom Switch bracket Mid High S
22. 85500 SoC TV with integrated analogue demodulator Below find a block diagram of the front end application for this region 7 5 Circuit Descriptions Q552 1A LA T EM Serial TE 18770 236 100127 5 100219 Figure 7 7 Front End block diagram Brazil region HDMI In this platform the Silicon Image Sil9x87 HDMI multiplexer is implemented Refer to figure 7 8 HDMI input configuration for the application New in this platform is the implementation of the Audio Return Channel ARC pin 14 on HDMI 1 The ARC in HDMI1 4 enables a TV via a single HDMI cable to send audio data upstream to an A V receiver or surround audio controller increasing user flexibility and eliminating the need for any separate SPDIF audio connection HDMIA R X Sil3187 4 HDMI Side 1P 04 1 03 1 02 optional HD MI 2 optional HDMI 1 with 18770 243 100203 eps 100203 Figure 7 8 HDMI input configuration The following multiplexers can be used e Sil9187A does not support Instaport technology for fast switching between input signals e Sil9287B supports Instaport technology for fast switching between input signals The hardware default IC addresses e Sil9187A OxBO OxB2 random software workaround e Sil9287B OxB2 fixed The Sil9x87 has the following specifications e 5 detection mechanism e Stable clock detection mechanism e Integrated
23. D a gt N gt B p p e m 62 18770 302 100217 eps 100217 Figure 8 8 Internal block diagram and pin configuration back to div table 2010 Apr 02 LEM E Q552 1A LA IC Data Sheets TMDSO TMDSO 53 TMDS3 TMDSO TMDS3 TMDSO TMDS3 I TMDSO TMDS3 53 SiI9287B Top view TMDS3 VCC33 RSVDL DDCO_BUS TMDS3 DDCO_BUS SIGO LVTTL O TMDS O TMDS O TMDS O SIGO LVTTL 1 DDC1 BUS DDC1 B US SIG1 LVTTL O SIG1 LVTTL Figure 8 9 Internal block diagram and pin configuration 8 9 Diagram HDMI 040 5119287 IC Block diagram CEC A CBUS DDC 2 RX1 RX2 RX3 Pinning information TMDS1 1 TMDS1 TMDS1 TMDS1 1 51 TMDS1 TMDS1 1 TMDS1 VCC33 RSVDL TMDS2 TMDS2 TMDS2 TMDS2 TMDS2 TMDS2 TMDS2 TMDS2 2010 Apr 02 back to div table POWER DOWN CTL IO HDMI CTL HDMI CTL 5104 LVTTL DDC4 BUS DDC4 BUS SIG3 LVTTL lO SIG3 LVTTL DDC3 BUS DDC3 BUS SIG2 LVTTL lO SIG2 LVTTL O DDC2 BUS DDC2 BUS VCC33 VCC33 OUT 18770 303 100217 eps 100217 IC Data Sheets Q552 1A LA EM 57 8 10 Diagram Headphone TPA6111A2DGN 7EE1 Block diagram Bias Control Pinning information D OR DGN PACKAGE TOP VIEW 8 IN1 LI 7 EI
24. E 2010 02 div table 4 5 6 7 8 9 10 11 12 13 2D10 C13 2D11 H13 3D02 1 1 3D02 2 At 3D02 3 B1 3D02 4 B1 3D03 3H2 3 03 4 G2 3004 1 F2 7300 7301 7302 7308 sani lt q 2 3D04 2 G2 ad MN m m Phase dii 3004 4 F2 i l 3005 3 1 3005 4 01 3010 B12 EJ 3D11 B12 3012 B12 HOAN 3013 1812 sts 3D13 2 C12 3013 3 12 7 3D13 4 C12 al 3D15 F12 3D16 F12 D 3D17F12 3D18 1 G12 3D18 2 G12 3D18 3 G12 3D18 4 G12 7300 B5 E 7301 B6 7302 B7 7303 B8 7304 B10 7305 B11 zm T un 4 2 7400 F5 en Rases me ins is Ei p I 7402 F7 s s s sin 7403 F8 7404 F10 13018 1 7405 F11 mt 7001 1 2 EJ 7D01 2 B2 L 7D02 C2 AS 7003 1 Els 7D03 2 F2 7004 G2 H 001 1 FD02 C1 FD03 D1 2004 F1 2005 G1 FDO6 H1 4 5 6 7 8 9 10 11 12 13 2 4 7 2 2009 10 07 15 LED LiteOn 8204 000 8970 AL 2K10 3104 313 63823 IE L 18770_621_100212 eps 100219 Circuit Diagrams PWB Layouts Q552 1A LA EM LE 10 4 AL1 3104313 63895 63812 Layout AmbiLight LiteOn AmbiLight LiteOn 3104 313 6389 5
25. 5v 45V BO3c B03e 01 45VCA T E c r a 0 33 BO3c am 3V3 3V3 B03e 5V 5V 7 3F25 5V USB1 p 2 77 ssv use2 B03c gt T mM jspcap 3V3 3V3 B03e 3F40 3V3 SD B03b o ee B03d PNX85500 CONTROL B03d 3V3 3V3 B03e Boge 43V3 STANDBY 43V3 STANDBY BO3c 5V 5V 0 amp 45V TUN 45V TUN B03c 9F71 45V TUN PIN 5 gt B03c 3V3 B03e gt 1V2 BRA VDDC B03c 1V2 BRA DR1 03 E _ 1 05 HDMI SIDE a acid CONNECTOR ee 1 1 05 45V VGA CONNECTOR PETI l TEMP SENSOR HEADPHONE 43V3 43V3 B03e Po 1V2 BRA VDDC 1V2 BRA VDDC gt 1V2 BRA DR1 1V2 BRA DR1 gt gt i 3V3 3V3 gt gt 3V3 BRA 3V3 BRA FLT 5V 5V P 5FE9 2V5 BRA PNX85500 NANDFLASH CONDITIONAL ACCESS 43V3 3V3 PNX85500 SDRAM 1V8 1V8 3520 DDR2 VREF CTRL3 AW gt 3506 DDR2 VREF CTRL2 2 E 5500 Diarra IN
26. 7203 7204 7205 1M84 LTW 008RGB LTW 008RGB LTW 008RGB SPI CLOCK BUE SPI DATA OUT 2 Blue 5 6 3 4 Green 1 2 PWM CLOCK BUF 5 3V3 6 Red 3 4 SPI CS 7 B LATCH 8 B oOo 9 EE S PROG 10 BLANK 44 3V3 p gt 12 14 TEMP SENSOR 15 16 17 18 19 20 21 22 C 23 24 24 p gt 25 FD18 1 8003 B004 8005 15 LED LiteOn 8204 000 8970 AL 2K10 3104 313 63823 18770 620 100212 5 100218 E back to 2010 Apr 02 div table 15 LED LiteOn Circuit Diagrams and PWB Layouts Q552 1A LA ES LUE 2 15 LED LiteOn 1 24V 8 3D02 1 1 10K 2 7D01 1 BC847BS GOL 2 2 3D02 2 7 10K FDo1 PWM B4 e 1 24 6 3002 3 3 10K 7D01 2 BC847BS COL 5 4 3D02 4 5 10K 02 PWM R4 e 4 lt 3 3D05 3 6 10K 7D02 BC847BW 3 1 7D03 1 BC847 BS COL 1 7D03 2 BC847 BS GOL 4 e te FDO3 PWM G4 e x 24V E ix e 2 te 45x e FD04 Fae PWM B5 e F 24V 12x e 4 5 N 4 e N FD05 PWM R5 e Z 24V LO ex 7D04 RSS BC847BW 3 1 B ook e FD06 PWM G5 e
27. BRX2 gt 50 i 9EC3 m 3ECG I3 FECP F2 BIN 5V BRX2 RES 3ECH A10 FECR E10 CRX HOTPLUG 3ECL RES HDMI CONNECTOR 1 oon 3ECJ 010 FECW H9 gt CRX24 CRX DDC SDA 10R 0 3ECK D11 FECY E10 am EE 3ECL E11 FECZ CRX1 54 lt 1 F8 IE11 2 omo XN geo VV Yoon lt gt SPAS 2 8 IE12D10 i Q ec T 3 08 IE42 B8 10 Gm 2 4 B8 IE43 08 i FECJ E 8 CRX2 gt 1 B8 1 44 E8 ie FECK e GRX DDC SCL CRX DDC SCL gt DRX HOTPLUG 2 D8 IE45 F8 in o EC CRX DDC SDA CRX DDC SDA 15044 ss a 3ECN 3 E8 IE65 17 CRX HOTPLUG i DRX DDC SDA 198 E 3ECN 4 F8 IE66 7 1 5 lt DRX DDC SC 77 4 m 5 1 B10 G3 i 2 nes 22k omm 2 3 10 5 G3 RES un ied a 3ECU 2 I8 IEC6 G4 gt d 3ECU 418 H3 7 HIT DRX1 x ws 9ECO E gt eae Allis DRX2 88 1008 IEC4 C3 5 DRX2 89 FECW 525 3V3 STANDBY 3 NON INSTAPORT 91874 4 3K3 3K3 H INSTAPORT 9287B 4X 100K 100K 5V p 4 5V VGA BAT54 g DDCA SDA E 23ECU 2 3V3 10K FECZ 2ECU DDCA SCL V Es 49ECUA 5 10K 100K 1uO 5V EDID
28. 2 LM324 P AB6 Sun 9 7 3 L 3517 3 6 AIN1 3 6 10K 2530 22K 100 3517 1 3513 1 8 AUDIO IN4 L gt 10K 22k 8 100 2 3817 7 2532 22K 1 0 AUDIO IN3 R x i AD7 3530 2 2 7 ADAC 3 536 4 AD6 4 5 ADAC 4 AE6 IS1S 33R AF6 3S36 3 10K AD4 3 6 D AD1 5 4 10K 3536 4 AD2 353 AUDIO IN4 R gt 2 3913 2 2S2L 100R 1u0 IS1B 1519 a IS1A gt 3S3F 3S13 4 C2 gt ADAC 5 2S2H 3514 9 33R 3816 1 B3 WA ADAC 6 E 3516 2 24V AUDIO VDD 3816 3 B3 3816 4 C3 3817 1 C3 3817 2 D3 3817 3 C3 7 ADAC 5 3 end 3817 4 C3 3818 1 G7 3818 2 G8 3818 3 G8 3819 H5 3525 H9 3532 G12 3534 G11 3536 1 C12 3537 3561 3536 2 B11 22K 3536 3 011 AE1 2 T oon 56R 2530 1 0 2530 1 0 2S3B 1 0 283A 1 0 2539 1 0 2538 1 0 0888 2S3F 10u 2S3E 100n 2S3H 10u 2538 100 AUDIO OUT L E ji 9906 252 3536 4 012 3537 F11 3538 B13 F 3V3 3V3 ARC 3S39 C13 24V AUDIO VDD 3S3F E4 7 Y 3536 1 C7 9 3536 2 08 1RO 3S3G 3 C8 3S3G 4 07 3S3H D7 3S3U D8 3551 C6 4 5 780
29. Close ComPair After start up of the Hyperterminal fill in a name f i logging in the Connection Description box then apply the following settings 1 2 Bits per second 115200 3 Data bits 8 4 Parity 2 none 5 Stop bits 1 6 Flow control 2 none During the start up of the TV set the logging will be displayed This is also the case during rebooting of the TV set the same logging appears time after time Also available in the logging is the Display Option Code useful when there is no picture look for item DisplayRawNumber in the beginning of the logging Tip when there is no picture available during rebooting you are able to check for error devices in the logging LAYER 2 error which can be very helpful to determine the failure cause of the reboot For protection state there is no logging 5 8 7 Loudspeakers Make sure that the volume is set to minimum during disconnecting the speakers in the ON state of the TV The audio amplifier can be damaged by disconnecting the speakers during ON state of the set 5 8 8 PSL In case of no picture when CSM test pattern is activated and backlight doesn t light up it s recommended first to check the inverter on the PSL wiring LAYER 2 error 17 is displayed in SDM 5 8 9 Tuner Attention In case the tuner is replaced always check the tuner options 5 8 10 Display option code Attention In case the SSB is replaced always check the d
30. Error Codes Introduction The error code buffer contains all detected errors since the last time the buffer was erased The buffer is written from left to right new errors are logged at the left side and all other errors shift one position to the right When an error occurs it is added to the list of errors provided the list is not full When an error occurs and the error buffer is full then the new error is not added and the error buffer stays intact history is maintained To prevent that an occasional error stays in the list forever the error is removed from the list after more than 50 hrs of operation When multiple errors occur errors occurred within a short time span there is a high probability that there is some relation between them New in this chassis is the way errors can be displayed errors are there the LED should not blink at all in CSM or SDM No spacer must be displayed as well There is a simple blinking LED procedure for board level repair home repair so called LAYER 1 errors next to the existing errors which are LAYER 2 errors see Table 5 2 LAYER 1 errors are one digit errors LAYER 2 errors are 2 digit errors In protection mode From consumer mode LAYER 1 From SDM mode LAYER 2 Fatal errors if 2 bus is blocked and the set reboots CSM and SAM are not selectable From consumer mode LAYER 1 From SDM mode LAYER 2 e In mode
31. lt gt DDR2 D15 3B00 1 C6 7B00 G4 12 B7 3B16 0082 0080 P DDR2 A11 K7 DOES ata 3 L8 A8 3B17 33R DDR2 DOSO N DDR2 A12 x L2 B7 2 3B18 DDR2 DOS1 P 3BOO 2 B7 7801 G1 0 2846 RES DDR2 A13 L8 A8 3B1 33R 0082 0051 m z me 73 oN DDR2 BA1 S a DDR2 BA2 G1 DDR2 BA1 s G3 A2 DDR2 ODT DDR2 BA2 G1 H RES F9 DDR2 ODT 3 H 3B01 C3 FBOO H1 DDR2 CLK P 2 3806 2408 E8 gt 3B09 RES F9 Se DDR2 CLK_ N lt DDR2 CLK gt 2408 E8 89 DDR2 CKE S F2 DDR2 CLK_N S 5 Fo CS G8 DDR2 CKE FBOO DDRA RAS z Fr L3 lt DDR2 A14 J DDR2 CS 2 DDR2 VREF DDR lt e DDR2 CAS G7 L7 DDR2 RAS 5 lt DDR2 A14 DR2 WE F3 DDR2 CAS G7 L7 lt 3B25 B3 DDR2 WE F3 33R DDR2 DQM1 gt 3B26 B3 B 33R e 2009 12 07 2 07 DDR 4 LL jJ 8204 000 8953 I 18770 534 100119 100218 E back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EE 10 14 B06 820400089572 LVDS Non DVBS Display Interfacing VDisp BO6A Display Interfacing VDisp 1 2 3 4 5 6 7 8 1G00 C4 1G03 B4 A 2G43 C4 2G44 C3 3G28 C5 5G01 C3 5G02 C3 6G00 C6 FGOH C5 5 B IG11C5 5601 1000 RES FGOH VDISP INT gt RES cA s VDISP 5G02 RT RES E C 3628 11 gt gt 6G00 s gt 2K2 LTST C190KGKT B D E F 1 2 3 4 5 6 7 8 LVD
32. 1 0 63 ki A V RES 308 8204 000 8951 ____ j _____ 18770_525_100118 5 100118 back to 2010 02 table Circuit Diagrams PWB Layouts Q552 1A LA EE Fan Control 1 2 3 4 9 6 7 8 9 21192 A7 T L 3US2 A3 va 3US3 B3 3US4 1 A4 48 3054 2 04 4 25 2 Pa 3054 3 CA B 27 3054 4 5 d 3US5 1 B6 22g 3US5 2 A6 3US5 3 A5 3US5 4 B5 3US6 C6 _ 3057 4 3059 B6 FAN DRV 7US1 1 A5 m 7US1 2 B5 M M 7US1 3 C5 vo RS 7US1 4 D5 D 7 7052 4 7US3 B6 9050 D4 1180 05 IUS3 A5 1154 B5 1185 C5 TACHO 056 1187 B7 105886 1189 B6 IUT1 4 IUT2 B4 3US5 2 2 3US2 10K FAN CTRL1 3V3 3US3 3 7051 2 B 11 LM339P 1 1054 _ 3055 4 4 IUT2 3 BC807 25W 7053 12 478 9050 RES 3US4 2 7 AAAC 4 10K TACHO2 sd DC DC 8204 000 8951 L Ej 18770 526 100118 eps 100118 E 2010 02 div table Vdisp Switch Circuit Diagrams and PWB Layouts Q552 1A LA 10 VDisp Switch 1 12VD 3UUO 3 3V3 STANDBY 47K IUUO 6 7UU2 1 PUMD12 1 1 1 1 A JJ 42 1 62 1 42 rm
33. 22K 3003 16 17 L GND SIG 22K 1002 L GND SIG i L E GND SIG 1025 B F 3V3 STANDBY 3 00 pe 41 1 P 10K 8 5 38 1 T il 1018 GND SIG 1 E 5 5 GND SIG b 1019 x lt lt SENSE 1V1 100R 1 225 2 eo 28 8 1020 s s S5 Ss 2 gt 5 5 icai 3U22 e e ave 3U08 1004 330R 1 1KO 1 1021 ac ase i GND SIG GND SIG GND SIG CU00 H GND SIG GND SIG L GND SIG 1 2 5 7 8 9 10 12 13 14 15 DC DC 8204 000 8951 2010 Apr 02 back to div table 100118 Circuit Diagrams PWB Layouts Q552 1A LA 10 DC DC B03C 2 3 4 5 6 7 8 9 1 95 1 3U84D2 1M99 C1 6040 1040 E2 7040 1 F4 2041 B1 7040 2 E4 2042 2 7U41 1 F4 2043 02 7041 2 F5 2044 03 7042 B5 2045 03 7043 2046 D3 7048 1 3V3 STANDBY 2U47 E1 7U48 2 2048 F1 9041 5 2049 F1 9042 B4 2050 F1 FUO7 C3 NE 2U51 D1 FU48 C1 Y 2U52 D1 FU49 C1 2053 D2
34. 85507 irr PGAMMA amp UPD8O9900F VOM amp FLASH 20274 VIDEO STREAM 7KQB 1 00 M25P32 ig LVDS PX1 PX1 7 01 TO DISPLAY TO DISPLAY TCON ON DISPLAY TCON ON SSB TO TCON SSB 74LVC245APW 20 3V3 5VCA R VGA PX 2 CONDITIONAL OMA ACCESS ISL24837IRZ 1920 1080 m 151 100 120 2 NENNEN GMA 8 x 7F75 UPC3221GV i a 1 ANALOG VIDEO E 2F90 1F75 2F74 2 U vv TO DISPLAY TCON SSB AT 5 2178 TCON ON DISPLAY 7KUE LOT SAW 36MHZ17 B MAX17079GTL g HAGC CONTROL _ 4 PX4 PX4 SELECT SAW PNX IF AGC VDISP i x 1 217 193 ANALOGUE EXTERNALS A M BEEN ssB 3104 3136344 _ 2 SSB3104313 sam USB HUB 819187 SII9287BCNU 1 01 18 AV1 R CONROL 14 AV1 G agis k EXT 1 Y E 10 AVI B bo 3 R26 USB DM 9626 USB DM2
35. 2 18 lt MOCLK 4 2F05 G6 100R 3F03 1 IF02 10K j 1 8 3 17 o lt 3F03 2 2 7 100R 4 16 Te CA ADDENn 1 32081 i 2F06 H6 1008 IF03 18 210 3F01 A2 MOVAL 3 3F08 3 0 3F02 4 9 11 10K MOSTRT aS 4 03 1 A4 10K 1 Mum d 3F032 4 2F02 MDO1 2 30927 4 3 04 1 RES 3F09 3 3F04 2 C4 m L 3F09 4 19 V 3F04 3 C4 10K d 19 _ IF05 L MDO4 4 3104 8 i 3F04 4 C4 CA MDOO c 3F04 1 1 8100R 2 18 lt MDOO 3F 10 2 3F05 1 C4 IF06 MDO5 5 3F04 3 3 si00R ar i6 5 unos 3F103 6 i 3F05 2 C4 G 3F05 4 1 ERR 5 u lt em MDO7 4 0 4 9 C 3F05 3 CA CA MDOS 3F05 2 2 71008 7 13 MDO5 10K CA MDO6 lt 3F05 3 3 6 1008 8 12 MDO6 3F05 4 C4 CA MDO7 3F05 4 4 51008 4 9 11 MDO7 nun CA RDY x 3 3 06 9 CA WAITn 23211 27 10K 3F07 1 A9 CA INPACKn B n 5VCA 3F07 2 A9 10K 15 ADDRESS E RES CRNE 4 3F11 4 5 TALVC245A T d CA VS1n BINA 1 lt 6 3 3 diio AS 1 E 10K s D GND1 D 3F07 4 A9 19 CA D3 I s enn 5 3F08 1 A9 Ss 18 2 gt 00 CA D05 lt XIO A01 Ss 17 3 gt CA A01 oon gt 2 XIO A02 sS 16 4 s CA A02 1 _ x 05 2 13 7 05 CA A11 1 3F08 4 B9 XIO 12 8 CA A06 CA A09 G 1 9 CA A07 09 1 9 13 m 14 E
36. 6 m gt B co e m You can download this information from the following websites http www philips com support http www p4c philips com back to 2010 Apr 02 div table Technical Specifications Diversity and Connections Q552 1A LA Em 2 3 Connections Side Rear connectors connectors 8 SERV U VIDEO L S VIDEO 000000 E EN N IN Rear J connectors 0000005 Y DIGITAL e 2 AUDIOIN 750 VGA DVI VGA ANTENNA AUDIO OUT 18990 001 100401 eps 100401 Figure 2 1 Connection overview Note The following connector colour abbreviations are used 4 01 Data channel e acc to DIN IEC 757 Bk Black Bu Blue Gn Green 5 Shield Gnd Grey Rd Red Whz White Yellow 6 D1 Data channel e 7 D0 Data channel 2 3 1 Side Connections 8 Shield Gnd 9 00 Data channel e 10 CLK Data channel b 68p See diagram HDMI amp CI eo as Gind 12 CLK Data channel e 13 Control channel eO 2 USB2 0 14 n c 15 DDC SCL DDC clock 16 DDC SDA DDC data cO 10000 022 090121 eps 17 Ground Gnd 090121 18 5V 19 HPD Hot Plug Detect Figure 2 2 USB type A 20 Ground Gnd L 1 5V 2 3 2 Rear Connections 2 Data cO 3 Data eG s round Gnd 1 4 8045 Ethernet optional
37. Pi pem FT56 84 C7 FT93 B9 FT69 1008 FT97 2 3188 2 TP FT57 8 3T85 C7 FT94 B9 TACHO2 FT98 BL SPI SDI 2 f a 9 r gt 3 lt jon oT e 318607 FT95 C7 E eae RES 3T83 2 83 1755346 4 P8 E FT96 4 E e a 13 gt 3188 1 07 FT97 E4 14 gt FAN CTRL2 gt RES BACKLIGHT PWM ANA DISP NA FO g 15 3188 2 E7 FT98 5 3193 ggg 008 PEU a i 3788 4 F7 99 F5 3V3 3T90D3 IT73A7 OK FAN DRV e 99 3179104 IT74 B7 5T54 BL SPI CSn s 4 E 3T92 E4 IT75B7 3V3 Be e s 1908 _ lt ENS 3793 IT78F4 2 5153 F3 F BACKLIGHT PWM BL VS F REF EMC HOLE 5153 100R 12V IT78 2 2 30R RES 0 22 Non DVBS LJ CONNECTOR BOARD 8204 000 8981 ____ 18770 569 100125 eps 100218 E back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM 10 16 310431363643 SSB Layout Overview top side
38. SCL SMBCLK SEL 0 SDA SMBDATA NON REM 1 E a gt a gt RESET_N NC NC NC USB2512 12A 12B USB2512i 12Ai 12Bi Top View QFN 36 Ground Pad i i must be connected to VSS 210 21 E VDD33 NC NC NC NC USBDP DN USBDM DN USBDM DN USBDP DN Figure 8 1 Internal block diagram and pin configuration back 2010 02 div table 18770 301 100217 eps 1002017 IC Data Sheets Q552 1A LA EM LIUM 8 2 Diagram Temp Sensor Headphone B01J LM75BDP 7FD1 Block diagram Vcc LM75B BIAS POINTER CONFIGURATION REFERENCE REGISTER REGISTER TEMPERATURE s REGISTER BAND GAP TEMP SENSOR 11 SIGMA DELTA A to D TOS CONVERTER REGISTER OSCILLATOR COMPARATOR THYST INTERRUPT REGISTER POWER ON RESET OS LOGIC CONTROL AND INTERFACE A2 A1 SCL SDA GND Pinning information 18770 300 100217 eps 100217 Figure 8 2 Pin configuration back to _ _ div table 2010 Apr 02 LEM E Q552 1A LA IC Data Sheets 8 3 Diagram PNX NandFlash Conditional Access B02A 85500 7500 Block diagram PNX8550x MEMORY CONTROLLER TS input MPEG SYSTEM TS out in for PROCESSOR PRIMARY PCMCIA VIDEO 1 OUTPUT DVB T C DVB channel decoder AV PIP SUB PICTURE VIDEO CVBS Y C DECODER 3D COMB RGB SECONDARY VIDEO ENCODER OUTPUT Low IF DIGITAL IF MULTI Direct IF
39. Temp Sensor Headphone Temp Sensor Headphone 1 2 4 5 6 7 8 2 1328 D6 1329 6 1FD2 4 1FD3 05 2FD1 A4 2FDC D5 2FDD D5 A os 3FD1 A3 3FD2 B5 3FD3 B3 3FD4 B2 B 3FD6 C4 LM7SBDP 3FD7 C4 7 3FDG 1 D4 6 3FDG 2 04 5 IFD5 6FD1 6FD2 D4 6FD3 D5 bo ai 7FD1 9FD1 A4 C C 9FD2A4 9FD5 C5 FFDA 05 FFDB 05 3 FFDC D6 502382 0370 IFD1 B4 IFD2 B3 D FFDA 1328 D IFD3 M IE IFD4 B3 IFD5 B4 F 0 9FD1 9FD2 3FD2 RES 1KO IT 42 24 ST C190KGKT F IFD2 3FD3 1 SDA SSB E 3 04 1008 IFD4 SCL SSB E 100R 3FD6 RES 1KO 3FD7 RES ww 1 3FDG 1 8 1KO 2 3FDG 27 1KO 1FD2 4 6FD2 CDS4C12GTA 12V 1FD3 6FD3 CDSAC12GTA 12V 2FDC 1nO 2FDD 1nO UJ 2 5 no co U gt U I 8204 000 8994 18770 509 100118 5 100118 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 LIN Tuner Brazil Tuner Brazil
40. m zig 2 88 4 9 06 G4 s P mE IES7 5 79 2 3E86 5 chs S afl ele 2E89 09 9E07 F4 lt e 2 90 4 9 08 F4 YPBPRI PR AP ud m ni 9E10 gia DEMOS 2E91 D4 9 09 G4 F 9E54 9 55 t i T ele 2E92 010 9E10 F4 3E78 188 9E05 Y el 1 1 2E93 E10 9E50 D1 IE55 5E76 BEC5 3E79 FE81 2E94 E9 9E51 D2 AIR 4 271 t gt 2E95 F10 9E52 E1 gig 818 xis 2E96 F9 9E53 E2 T 8 s MTJ 505H 01 NI LF 2E97 E8 9E54 F1 5 9 09 2 98 8 9E55 F2 RES 9E06 IE96 ak 5 2 99 E8 010 2 4 A7 BEC1 E10 FE83 i 7 e 7205 IE92 45 1251 2EA5 B7 2 F10 Fa BC847BW 9 4 V gt CVBS OUT SC1 JJ NAV2 BLK 1 G 2EB1 D6 02 y 7E09 2 2EB3 E7 BEC4 E2 _ m 225 PUMH7 NEC c 3 07 1 C3 5 F2 vs Hox oe q 07 2 FE55 09 7 e ON urs 3E07 3H13 FE60 12 MRC 021V 29 PC RES a m 3E07 4 FE61 B12 IE48 zt ANN 3 11 1 B11 62 12 AV1 BLK 6 1E01 2 68R 1 c L 1 2 100R 7 11 2 113 FE63 012 7 09 1 2 MT 3E37 3 3E11 3 113 FE64 D12 PUMH7 um 62 im 11 4 11 66 E12 1 b AV2 CVBS 16 D11 FE67 E12 lt s s 3E07 2 gt MRC 021V 29 PC 128 AVOS8 8 5 8
41. 2EC2 MO 7ECO G3 gt E 2EC3B10 9 2 6 B9 9ECO G4 ame T Emo WE on 2EC7 B9 9EC2 C11 i _ 6 PNE sl sles 2EC8 B9 9EC3 E11 axe o ae T ATS 2ECC G8 FECO A9 gt T 8 l 2ECM B8 FEC1 B2 Pu 3 I 2ECN D8 FEC2 B2 ccc TABXDDC SDA 2 8 FEC3 A10 17 FECA 1 8 S 2ECQ F8 B2 19 5 lt ARX HOTPLUG Y 25 lt FEC5B FEC6 21 m m 108 HECM 9 BECP Ps 5 2ECU 13 5 2 ARX DDC SCL 49 2ECV A9 FEC6 B2 gt A y 25 lt 54 VGA SCL EDID HDMI 2ECW B10 FEC7 A10 HDMI CONNECTOR 2 23 4 FECA F3 amo MEN EAMA 184 gt BRX2 1 3EC1 3 B4 FECC D2 um 3EC3 E10 FECD D2 Ime S 3EC5 E10 FECE D2 Y BRX HOTPLUG 57 gt HDMIA RX2 gt 1 04 FECFD2 E cit s ou tc 2 04 FECG D2 gt BRXC i BRX DDC SDA 1 58 HDMIA RX1 i 5 PCEC HDMI 5 g BRX DDC SCL m MUS 3ECA 3 F4 FECJ F2 FECC BRX DDC SCL BRX DDC SCL BRXC gt 60 E HDMIA RX0 3EC A 4 F4 FECK F2 BRX DDC SDA INBRX DDC SDA lt BRXC 3ECD G3 FECL F 2 gt eyes 9 e ONY 23 mo T H3 2 FECG Scu Hn E 01 MICOM VCC33 E ee id AN ad FECN F2
42. AGC AM AP AR ASF ATSC ATV Auto TV AV AVC AVIP B G BDS BLR BTSC B TXT CEC CL CLR ComPair CP CSM CVBS DAC DBE DCM DDC D K DFI switch control signal on A V board 0 loop through AUX to TV 6 play 16 9 format 12 play 4 3 format Automatic Aspect Ratio Adaptation algorithm that adapts aspect ratio to remove horizontal black bars keeps the original aspect ratio Automatic Channel Installation algorithm that installs TV channels directly from a cable network by means of a predefined TXT page Analogue to Digital Converter Automatic Frequency Control control signal used to tune to the correct frequency Automatic Gain Control algorithm that controls the video input of the feature box Amplitude Modulation Asia Pacific Aspect Ratio 4 by 3 or 16 by 9 Auto Screen Fit algorithm that adapts aspect ratio to remove horizontal black bars without discarding video information Advanced Television Systems Committee the digital TV standard in the USA See Auto TV A hardware and software control system that measures picture content and adapts image parameters in a dynamic way External Audio Video Audio Video Controller Audio Video Input Processor Monochrome TV system Sound carrier distance is 5 5 MHz Business Display Solutions iTV Board Level Repair Broadcast Television Standard Committee Multiplex FM stereo sound system originating from t
43. No No To keep this flowchart readable the exact display turn on description is not copied here Please see the Semi standby to On description for the detailed display startup During the complete display time of the Startup screen visible Startup screen the preheat condition of sequence 100 PWM is valid initialize tuner and channel decoders E Initialize source selection il Initialize video processing IC s initialize AutoTV by triggering CHS AutoTV Init interface Initialize Ambilight with Lights off Semi Standby 18770 252 100216 eps 100216 Figure 5 5 Off to Semi Stand by flowchart part 2 back to _ _ div table 2010 Apr 02 18 EM Q552 1A LA service Modes Error Codes and Fault Finding Constraints taken into account Display may only be started when valid LVDS output clock can be delivered by the AVC To have a reliable operation of the EEFL backlight the backlight should be driven with a maximum PWM duty cycle during the first seconds Only after this first one or two seconds the PWM may be set to the required output level Note that the PWM output should be present before the backlight is switched on To minimize the artefacts the picture should only be unblanked after these first seconds Semi Standby Wait until previous on state is left more than 2 seconds ago to prevent LCD display problems Assert RGB video blanking and audio mute Th
44. Options 2 Gives the option codes of option group 2 as set in SAM Service Alignment Mode e 12NC SSB Gives an identification of the SSB as stored in NVM Note that if an NVM is replaced or is initialized after corruption this identification number has to be re written to NVM ComPair will foresee in a possibility to do this This identification number is the 12nc number of the SSB 12NC display Shows the 12NC of the display 12NC supply Shows the 12NC of the supply e 12NC 200Hz board Shows the 12NC of the 200Hz Panel Software versions e Current main SW Displays the build in main software version In case of field problems related to software software can be upgraded As this software is consumer upgradeable it will also be published on the Internet Example Q555X 1 2 3 4 Standby SW Displays the build in stand by processor software version Upgrading this software will be possible via ComPair or via USB see section 5 9 Software Upgrading Example STDBY 88 68 1 2 e UM version Displays the electronic user manual SW version Quality items e Signal quality bad average good e Ethernet MAC address Dispays the MAC address present in the SSB e Wireless MAC address Displays the wireless MAC address to support the Wi Fi functionality BDS key Indicates if the set is in the BDS status e Cl slot present If the common interface module is detected e Event counter How to Exit CSM P
45. POPPOr eo E DDO OOOO 3 1 3 2 3 3 3 3 1 Precautions Notes and Abbreviation List Q552 1A LA EM 5 3 Precautions Notes and Abbreviation List Index of this chapter 3 1 Safety Instructions 3 2 Warnings 3 9 Notes 3 4 Abbreviation List Safety Instructions Safety regulations require the following during a repair e Connect the set to the Mains AC Power an isolation transformer 800 e Replace safety components indicated by the symbol only by components identical to the original ones Any other component substitution other than original type may increase risk of fire or electrical shock hazard Of de set ontploft Safety regulations require that after a repair the set must be returned in its original condition Pay in particular attention to the following points Route the wire trees correctly and fix them with the mounted cable clamps Check the insulation of the Mains AC Power lead for external damage Check the strain relief of the Mains AC Power cord for proper function e Check the electrical DC resistance between the Mains AC Power plug and the secondary side only for sets that have a Mains AC Power isolated power supply 1 Unplug the Mains AC Power cord and connect a wire between the two pins of the Mains AC Power plug 2 Setthe Mains AC Power switch to the on position keep the Mains AC Power cord unplugged 3
46. 03 D1 FD04 F1 2005 G1 006 15 LED Everlight 8204 000 9062 2 AL 2K10 3104 313 64211 L 18770_661_100212 eps 100212 Circuit Diagrams PWB Layouts Q552 1A LA EM LUE 10 8 AL1 3104313 64201 64191 64211 Layout AmbiLight Everlight AmbiLight Everlight 3104 313 6420 1 eaea 1 1M83 DEZ IN due 45 1559 1 M83 omis 7807 8 e 786 Ral 7204 5 1 04 5 1 3 6419 1 284 7C22 3104 313 6419 1 Eod 7103 7104 2 7105 27850 7 51 8004 Bead B007 0901 806 zi ETE p A02 rz ES 1 771 428 e 47807 00564 2804 1M84 452021 2 2298 3551 9535 7 026830 1 393 9 308 7409491 5492
47. 2009 10 22 8204 000 8952 o 18770 531 100118 eps 100118 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 111 1 2 4 5 6 7 8 9 2EEO C5 2EE1 D5 2EE2 4 3V3 STANDBY 2 2 2 4 2 05 2EE6 E6 2EE7 E6 1 3EE0 3 F3 B 4 _ 3EE1 1 C5 L RESET AUDIO 2 7 0 1 1 2 D8 E 3EE1 3 D8 3EE1 4 D5 3EE2 1 D7 2 2 7 e 3EE2 3 E7 3EE2 4 E7 0 1 B5 7 2 B6 7EE1 D4 FE35 E7 D FE36E7 FEEO B4 IEEO 2 E IEE1 2 33R IEEO 2EE3 IEE 1 AMPLIFIER 2 6 IEE7 3 22 6 J IEE2 E2 2 3EE1 2 7 22K 3 3EE1 3 6 22K ADAC 3 e 8 1 e ize 0 2EE4 10K 4 AV 100u 33R ADAC 4 4 T E 1u0 10K IEEA m 3 6 ss AMP2 IEE4 E3 AV 100 33R IEE5 F3 33R IEE6 E4 IEE7 E6 1 10K 5 3EE0 3 A PLOP Ss 3 AUDIO 8204 000 8952 18770 532 100119 eps 100119 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 10 13 B05 820400089535 DDR DDR I 1 2 3 4 5 6 7 8 9 10 11 12 13
48. 3V3 3V3 85500 AUDIO 3V3 gt 3511 3V3 ARC 42V5 AUDIO 24V AUDIO POWER 24V AU DIO POWERI 3807 24V AUDIO VDD PNX85500 MIPS 3V3 3V3 3y9 STANDBY 43V3 STANDBY 1V1 1V1 L 3V3 STANDBY 3V3 STANDBY 3V3 STANDBY Puxessoo POWER gt 11 1V2 1V2 41V8 1V8 2 5 2V5 2V5 AUDIO 2V5 AUDIO 2V5 LVDS 1 8 43V3 3V3 3va STANDBY 3V3 STANDBY 24V AUDIO POWER 424V AUDIO POWER p p 3009 AVCC 3V3 STANDBY 3V3 STANDBY BO1k ae BO1k 7003 TPS53126PW 12VAV8 W ws COVERSION Dual Synchronous 5U00 1V8 d Controller 1 NAY 12VAV1 COVERSION B03c B03b B03c B03e B03e B03c B03e B03c B03c B03e B03e B03e B03e B03c 0 0 BO3c lt B02h 1V8 1V8 1V2 ae 7UA3 2 5 gt CUAO 42V5lVDS gt NOT FOR 5000 SERIES B03e B03c B03e div table B03c 12V 7 gt p ee Em VDISP SWITCH 1 43V3 43V3 3V3 STANDBY 43V3 STANDBY 1
49. HDMI 1 CRXC 62 3S0W 43V3 6000 Serie SIL9187 non Instaport 8000 Serie mux SIL9287 Instaport 18990_402_100331 eps S back to u NN 9 3 Block Diagram Audio 1T01 2F90 3 7EC1 SII9187ACNU SII9287BCNU ARC eHDMI 1F75 SAW 36MHZ17 Block Diagrams Q552 1A LA 9 GOE 1 00 D CONDITIONAL ACCESS 7F75 5V TUN PIN UPC3221GV 1 4 2874 2 5 2118 3 mp gt AGC CONTROL PNX IF AGC 6000 Serie mux SIL9187 non Instaport 8000 Serie mux SIL9287 Instaport eHDMI COMMON INTERFACE 74LVC245APW 20 CA MDO 0 7 1201 90 6 AUDIO IN1 L DRX2 89 2 AUDIO IN1 R DRX1 86 pRxo4 84 DRX0 83 DRXC 81 1 02 HDMI SIDE DRXC 80 6 AUDIO IN2 L CONNECTOR p c el 2 AUDIO IN2 R 310 959 ANALOGUE EXTERNALS 1E08 HDMI 3 6 AUDIO IN3 L CONNECTOR Only 8000 LR AUDIO IN3 R 1 09 AUDIO IN4 L DVI AUDIO AUDIO IN4 R 3 3 1P03 me E DIGITAL BRX2 41 Rs e 1 SPDIF OUT BRX1 39 I OUT 4 BRX1 39 BRX0 36 BRXO 35 BRXC 33 2 BRXC 32 PRI CIE CONNECTOR HDM
50. 1 is the first one which will come across according the wire connection track as follows start by the small signal panel and proceed towards the ambilient modules This module pixel 1 will be connected to the next module pixel 2 and etc e Align the brightness compared with the neighbour modules The brightness will be automatically stored e Select one of the 10 matrixes which most color respond towards the neighbour modules The alignment is stored automatically back to div table TCON Alignment In TV sets with forward integration where the TCON device is located on the small signal board or 200 Hz board all TCON values needs realignment for every SSB display swap due to repair or upgrade The TCON alignment during assembly is normally supported by a special testpattern and the use of a camera hence very difficult to simulate for home repair A more practical way with predefined settings is described below e Go to SAM dial 062596 OK button pressed Select Alignments e alignment value with 4 digits this can be changed by RC transmitter entry according the values listed in Table 6 6 The value shall be stored in STVM100DC for Sharp MAX9668 for LGD e Reset TCON alignment here a default value according the display option code will be copied from the display file to the TCON and changes the current value to the default value Option Settings Introduction The microprocessor communicates
51. 5V USB2 1 iae UAR DM2 SIDE USB USB DP2 H CONNECTOR ___________________ _______________8000 777 1 7 9 21 n ps USB DM1 SIDE USB USB DP1 CONNECTOR L _________________________________6 Serie 0082 0 0 31 7803 EDE1108AGBG 7801 EDE1108AGBG IDDR2 A 0 13 1V8 DDR2 VREF DDR 8000 Serie 512MB 18990 403 100331 eps Block Diagrams Q552 1A LA 9 LIN 9 4 Block Diagram Control amp Clock Signals CONTROL CLOCK SIGNALS TO AMBILIGHT MODULE COMMON INTERFACE 94 Y PNX85500 515164 AMBILIGHT 7GA0 XC9572XL 7S00 PNX85507EB Ez PXCLK54 43 1M59 22 AMBI SPI CLK OUT VIDEO STREAM PNX SPI CLK 41 27 AMBI SPI SDO OUT PNX SPI SDI 40 23 AMBI SPI SDI OUT G1 PNX SPI SDO 39 29 AMBI PWM CLK_B2 Mast 30 AMBI SPI CS OUTn_R2 CA MDI O 7 91 AMBI LATCH1 G2 I 19 AMBI PROG_B1 20 R1 mer CONTROL 22 PNX SPI CS BLn 3 28 AMBI LATCH2_DIS MDO 0 7 CA MDO 0 7 k w23 PNX SPI CS AMBIn 2 21 AMBI SPI CS EXTLAMPSn 7F02 32 AMBI TEMP 20274 FLASH I PCMCIA AF1 SENSE 1V1 CA A 00 14 XIO A 0 14 B03B i AA15 SENSE 1V2 CONDITIONAL B03D ACCESS 7F04 uu I c I s ETT MEMORY CA D 0 7
52. 7S00 3 PNX85500 CONTROL 3545 1805 1 13956 2 gt SDA UP MIPS NNASDA UP MIPS x 3969 1F10 p gt BOOTMODE 1 100R 1 2 3857 S SCL UP MIPS SCL UP MIPS e 356 4K7 AKT EJTAG TRSTn PNX85500 lt FS44 10K 3558 08 EJTAG TMS PNX85500 BOOTMODE 1 2 SDA SET SDA SET 3S6B 4K7 EJTAG TDO PNX85500 GPIO 0 3 3V3 p gt VV e 01 GPIO 1 1008 1 2 3S5W SCL SET SCL SET 5 3566 4K7 E JTAG TCK PNXB85500 FOR FACTORY z 100R 10K MES gt GPIO 2 3S5Y man EJTAG TDI PNX85500 5 USE ONLY 3S82 RES GPIO 3 1008 1 2 3557 2 3S6E 2K2 i ava BOOST PWM RXD2 MIPS gt GPIO 4 S SCL SSB SCL SSB lt EJTAG DETECTn lt 7 10K TXD2 MIPS lt GPIO 5 3S60 100R FS10 02 5 1 2 SDA TUNER NSDA TUNER 3S6F 4K7 3V3 J gt sg1 lt GPIO 6 Se 10K e FS11 RXD2 MIPS PNX SPI CS BLn lt GPIO 7 100R i508 2 3S61 s SCL TUNER SCL TUNER 3566 4K7 10K BOOST PWM m SPI CS GPIO 10 3521 ia SPI CS AMBIn SELECT SAW GPIO 11 lt EJTAG TRSTn PNX85500 EJTAG TRSTn PNX85500 g 3S6K T 10K 1504 EJTAG TMS PNX85500 EJTAG TMS PNX85500 1 8 3S6H 1 10K 4 3 3 5 3V3 MN 3562 PNX SPI CS BLn USB DM gt DN lt EJTAG TCK PNX85500 EJTAG TCK PNX85500 g 10 3 6 3S6H 3 3V3 p gt USB DP s DP USB gt EJTAG TDO PNX85500 EJTAG TDO PNX85500 4 10 2 7 3S6H 2 2 1542 EJTAG TDI PNX85500 EJTAG TDI PNX85500 10 4 5
53. AAA e s e 2 3013 2 24 1K5 3D13 3 9 1K5 ws 7D02 RSS BC847BW 3 4 3013 4 5 e 1K5 i lt T tO N PWM G4 e 5 24V E e 7D03 1 5 lt 5 BC847BS GOL 2 u 1 t 2504 B5 e 3D15 s lt 24V 24V 7400 7401 7402 7403 7404 7405 68R F Y 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D dt BER i5 5 6 5 6 5 6 5 6 5 6 5 6 lt BC647BS GOL 1 2 1 2 1 2 1 2 1 2 1 2 NM 68R i 5 3 4 3 4 3 4 3 4 3 4 3 4 4 32 T 3018 1 ed 1 8 205 L A G e 2 3018 2 7 7 1K5 3 3018 3 6 1K5 ex 7D04 n BC847BW 3 4 3018 4 5 1K5 15 a es 2006 PWM G5 e E 2010 02 div table 11 12 13 2D10 C13 2D11 H13 3002 1 A1 3002 2 A1 3002 3 B1 3002 4 B1 3D03 3 H2 3D03 4 G2 3004 1 F2 3D04 2 G2 3D04 3 E2 3004 4 F2 3005 3 C1 3005 4 D1 3D10 B12 3D11 B12 3D12 B12 3D13 1 B12 3D13 2 C12 3013 3 C12 3D13 4 C12 3D15 F12 3D16 F12 3D17 F12 3D18 1 12 3D18 2 G12 3D18 3 G12 3D18 4 G12 7300 B5 7301 B6 7302 B7 7 303 B8 7304 B10 7305 B11 7400 F5 7401 F6 7402 F7 7403 F8 7404 F10 7405 F11 7001 1 A2 7001 2 B2 7002 C2 7003 1 E2 7003 2 F2 7004 G2 FDO1 A1 FDO2 C1
54. GND SPI DATA RETURN SPI DATA IN SPI CLOCK 1 48 AL2A SPI CLOCK BUF SPI DATA OUT SPI DATA RETURN GND PWM CLOCK BUF 3V3 SPI CS LATCH GND 10 PROG 11 BLANK 12 43V3 13 N C TEMP SENSOR GND GND GND GND GND 24V 24V 24 24 24 1M95 8V3 STANDBY STANDBY GND GND GND 12 12V 12 24V AUDIO POWER 10 GND AUDIO 11 MAINS OK 1 99 12VD 12VD GND GND LAMP ON BACKLIGHT PWM_BL VS BACKLIGHT BOOST BACKLIGHT PWM ANA DISP POWER OK 1M20 Boga 9 NO Or GN LIGHT SENSOR GND RC LED 2 3V3 STANDBY LED 1 KEYBOARD 5V 14 AMBI SPI CS EXTLAMPSn E Z back to 2010 Apr 02 div table 1735 B03A 1 LEFT SPEAKER 2 GND AUDIO 3 GND AUDIO 4 RIGHT SPEAKER 1KA1 B14E 1 GND 11 VLS_15V6 12 VLS_15V6 33 VCC_3V3 34 VCC 3V3 78 VGH_25V 79 VGL 6V 80 GND 1KA2 B14E 1 GND 11 15 15 6 12 VLS 15V6 33 VCC_3V3 34 VCC_3V3 78 VGH_25V 79 VGL_6V 80 GND 18990_400_100330 eps 100330 Block Diagrams Q552 1A LA 9 LIN 9 2 Block Diagram Video VIDEO 00 0 VIDEO OUT LVDS CONTROL SHARP MINILVDS SHARP 1KA1 7S00 4
55. Tz 2010 02 back to div table 10 11 12 PNX85500 13 13 8204 000 8950 1502 B8 2810 B6 2811 B5 2813 B6 2837 B5 2 40 254 2 254 B9 284G B9 254 G10 3518 C2 3 1 C1 3S1D C2 3S1E C1 3S1F C2 3516 02 3S1H D1 381J D2 3S1K D1 3S1L E2 1 D11 352A 02 3S2F 07 3526 07 3S2H D7 3S2K 07 3S2L D10 3S2M E10 3525 E10 3S2V F11 3S3L C2 3S3M C1 3S3N C2 5 C1 3530 C2 D2 3535 D1 3S3T D1 3S3W E9 3S3Y 09 3841 D12 3842 C11 3843 C11 3844 C11 3846 D10 3547 E10 3849 E10 3S6V C11 3S6W 012 5504 B6 7900 9 B6 7920 G10 9500 G9 950 G9 9524 B6 DS50 B8 2502 G11 FS45 G9 520 B6 IS2U G10 IS2V D7 IS2Z D7 IS3B 1530 C10 IS3E C10 IS3F C10 6 2009 12 07 18770 517 100118 eps 100118 Circuit Diagrams PWB Layouts Q552 1A LA EM GE PNX Power PNX Power 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2821 F6 285 4 C5
56. a FUUO 7UUO SI4835DDY RES 513441 0 C 7001 VDISP INT 47K RES IUU3 7UU2 2 3UU1 23003 2 9 478 iuui 100 IUU2 47K RES gt 3UU0 2 5 47K lt 2 VDISP SWITCH 555 2010 02 back to div table 7003 RES BC847BW p 3 3UU2 4K7 RES 47K RES e 54 N 3V3 1005 43V3 47K RES 2UUO C6 2UU1 C4 3UUO 1 C4 3UUO 2 C4 3UU0 3 C2 3UU1 C4 3UU2 D6 3UUS 1 C4 3UU3 2 C5 3UU3 3 C6 3UU3 4 C7 7000 7001 B5 7UU2 1 C3 7UU2 2 C3 7003 C6 9UUO 1 A4 9UUO 2 A4 9UUO 3 A4 9UUO 4 A4 9001 1 A4 9UU1 2 A4 9UU1 3 A4 9UU1 4 A4 FUUO A5 IUUO IUU1 C4 IUU2 C5 1003 IUUA C6 005 C7 006 06 _____ DC DC CLASS D 8204 000 8951 UQ 2009 10 22 18770 527 100118 eps 100118 Circuit Diagrams PWB Layouts Q552 1A LA 10 107 10 12 B04 820400089524 Analog I O Analogue Externals A Analogue Externals 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1200 A4 78 F2 IE22 B2
57. will effectively work while V LNB is held at a level around 11V7 via diode 6T55 After 7105 is initialized the second channel of 7 will start and generates a voltage higher then LNB RF1 with 0 8 5V DVBS start up will imply 3V3 DVBS start up with a small delay of a few milliseconds gt 2V5 DVBS and 1V DVBS will be enabled If 24V drops below 15V level then the DVB S2 supply will stop even if 3V3 is still present Debugging The best way to find a failure in the DC DC converters is to check their start up sequence at power on via the mains cord presuming that the standby microprocessor and the external supply are operational Take STANDBY signal high to low transition as time reference When 12 becomes available maximum 1 second after STANDBY signal goes low then 1 1 is started immediately After ENABLE 3V3 goes low all the other supply voltages should rise within a few milliseconds Tips e Behaviour comparison with a reference TV550 platform can be a fast way to locate failures e f 12V stays low check the integrity of fuse 1040 e Check the integrity at least no short circuit between drain and source of the power MOS FETs before starting up the platform in SDM otherwise many components might be damaged Using a ohmmeter can detect short circuits between any power rail and ground or between 12V and any other power rail e Short circuit at the output of an integrated linear stabiliser
58. x 4 29 pu USBDP_DN3IPRT_DIS Z gt USB DP3 ad 3V3 VBUS_DET USBDM_DNSIPRT_DIS_M3 5 USB DM3 1241 45 BC 3F34 1 E FF33 RBIAS 7 e 45V USB2 3 31 3 12K 140 100K 3 6 22 9 24 _ 1 2 2 gt 10K 3 31 4 5 IF39 o5 SCLISMBCLKICFG SELO 5 USB OC2n HS SEL1 100K d 10K ES 3F34 3 6 A arae 100K ds 888 3V3 USB OC3n E 10K L L 100K SIDE USB TOP 1P08 5V USB2 1 USB DM2 2 USB DP2 U 7 3 4 1 45 FF32 4 292303 4 Frag USB DM3 M x Se 2 4 FF31 5 502382 0570 TUNER amp 2010 02 back to div table B01C 1 24 9 1F25 B1 1P07 B9 1 08 09 2F25 A2 2F26 A2 2F27 A2 2F28 A4 2F29 A4 2F30 A4 2F31 A5 2F32 5 2F33 5 A 2F34 B1 2F35 B2 3F25 A8 3F26 1 A8 3F26 2 A8 3F26 3 A8 3F26 4 B8 3F28 B2 3F30 C2 3F31 2 C2 3F31 3 C2 3F31 4 D2 B 3F32 C8 3F34 1 C8 3F34 2 C8 3F34 3 D8 3F34 4 D8 3F35 B1 3F36 D6 7F25 B2 9F20 B7 9F21 B7 9F25 B8 9F26 B8 C FF30 E8 FF31 E9 FF32 E9 FF33 C9 FF34 C7 FF35 C7 FF36 D7 FF37 D7 FF38 E9 FF39 E8 FF40 A8 D IF30 C2 IF31 C1 IF32 C1 IF33 B2 IF34 B2 IF35 B5 IF36 C5 IF37 C5 IF39 D2 IF40 C2 IF41 C2 IF42 C2 IF43 A3 IF44 IF45 D9 2009 10 22 ____ ____ 18770 502 100118 eps 100118 8204 000 8994 SD Card SD Card Cir
59. 12345678 3 HDMI Digital Video Digital Audio In 19 1 E 10000 025 090121 eps 10000 017 090121 eps 090121 090428 Figure 2 4 Ethernet connector Figure 2 3 HDMI type A connector 1 TD Transmit signal Qe 1 02 Data channel 2 2 Transmit signal 2 Shield a 3 RD Receive signal 3 D2 Data channel 4 CT Centre Tap DC level fixation back to 2010 Apr 02 div table EM Q552 1A LA Technical Specifications Diversity and Connections 5 CT Centre Tap DC level fixation 6 RD Receive signal 7 GND Gnd 8 GND 5 CVI 2 Cinch Video YPbPr In Audio In Gn Video Y 1 75 ohm 9 Bu Video Pb 0 7 Vpp 75 ohm 9 Rd Video Pr 0 7 Vpp 75 ohm 4900 Rd Audio 0 5 10 kohm 9 Wh Audio L 0 5 10 X 6 Service Connector UART 1 Ground Gnd 1 2 UART Transmit 3 UART Receive 7 Cinch Video CVBS In Audio In Ye Video CVBS 1 Vpp 75 ohm Wh Audio 0 5 10 kohm 4900 Rd Audio 0 5 10 kohm 9 8 S Video Hosiden Video Y C In 1 Ground Y Gnd 1 2 Ground C Gnd 3 Video 1 Vpp 75 ohm 4 Video 0 3 VppP 75 ohm 9 Head phone Output Bk Head phone 32 600 ohm 10 mW OF 2 3 3 Rear Connections Bottom 10 1 Video RGB In CVBS In Out Audio In Out See 5 2 Cinch Video YPbPr In Audio In 11 Cinch S PDIF Ou
60. 1A LA EMI 6 6 3 Use of repaired SSBs instead of new SSBs on stock will obviously already contain main TV software This implies that only a main software upgrade is required if you use a repaired SSB for board swap instead of a new SSB Hardware Info Display TV amp Standby SW version and CTN serial B Standby processor version e g STDBY 42 42 0 0 Eg e g see type plate Operation hours Displays the accumulated total of operation hours TV switched on off amp every 0 5 hours is increase one Errors Reset error buffer Colour temperature Dealer options i Auto store mode Alignment White point LLL O S Bonn Seam n Reset TCON alignment used when a new display code after a SSB exchange is keyed in and if you do not have alignment values from production _ SS p div table E Clears all content in the error buffer 3 different modes of colour temperature can be se id Cool LCD White Point Alignment For values see Table 6 4 White tone default setting 42 1 until 6 5 White tone default setting 46 used when a new display code after a SSB exchange is keyed in and if you have alignment values from production see Table 6 6 TCON default settings Select Virgin mode On Off TV starts up does not start up once with a language selection
61. 2F58 D2 A A 3F51 B1 3V3 STANDBY 3V3 STANDBY 3F52 B3 3F53 C6 3V3 STANDBY Pu m 3F54 D7 9 Y Y Y 3F58 E1 3F59 E3 3F60 3F62 D5 B 3F63 E5 7F53 RES 3F64 PDTA114EU 5V 3F65 F5 3F66 B7 m 3F67 S 7654 1 RES 3F68 C7 7 a4 3V3 STANDBY 3F69 07 e 4 gt gt SP PROG F52 B2 C 7253 B7 7F54 1 C7 7F54 2 C7 7F58 D1 MES 9CHO C7 FF04 C4 x FF29 C4 MAIN NVM 4 B 55 3V3 ES D Y D FF56 E3 DEBUG ONLY FF57 E 3F51 10K 2F52 3F66 3F52 10K 7 52 25 05 6 sese 4 IF51 IF50 PNX SPI SDO IF52 3F67 10K RES lt a PNX SPI CLK IF53 PNX SPI CSBn i PNX SPI WPn BOOST PWM Ss IF55 A A A A FFo4 F62 e gt SDM 3 100 RES RES SCLSSB 2 SCL FF61 D4 SDA SSB lt 3F63 2 SDA FF62 D7 FF63 E4 FF64 F7 e e FF65 F4 FF66 F4 ini Wi E SDA UP MIPS E 751 B1 752 LEVEL IF53 B3 IF54 C3 SHIFTED 1F51 IF55 C6 FF65 3F64 e FOR IF56 C7 8Kx8 EEPROM 59 55 58 DEBUG 5232 INTERFACE RXD UP mer UP IF57 C7 RESET STBYn 100R DEBUG F SPI PROG AAA YW IF58 D2 IF59 E1 IF61 C4 IF62 C4 GQ NN USE ONLY 8204 000 8994
62. 302 2 5 518 p FUA d d 2UBO C7 3UB7 4 C2 8 lt 208106 5 y 2UB2 D7 7006 1 F2 Ke ag t 2083 F6 7006 2 F1 4 E g 2UB4F6 7UA0 B2 B Bog 2085 F8 7UA1 1 A5 L i v o Te as 2UB6 F8 7UA1 2C5 MEME 2UB7F7 5V5 TUN p gt io 5V TUN 1 a UE 2088 02 7UA3 C6 3012 7UA4 E5 AG L ak 31013 C3 70 5 E8 nl LLLA __ 3U15 1C8 7UA6 C 300 UE oy 1 8 7UA7 1 C3 y I 1 3915 18 3V3 3016 1 TUAT 2 D2 3084 ANN 3U15 4D8 7UCO A8 130861 3 _IUB5 1 7UA7 1 85377 Bog 3U16 1 C9 CUAO B9 EE BCBA7BS COL 7UA1 2 7 100R 100R 3016 2 C9 AAA 2 o8 UA7 2 FUA2 3UBO IUA5 3U15 3 3U16 3 FUAO A2 7 3 6 3 6 uos w VA V 3U16 3D9 FUAT A7 BC847BS 24 2 430154 43016 4 5 3016 4 09 FUA2 D5 xm a o p 1V2 100R 100R 3U25 1 E3 FUAS3 D7 57 8 E S ST E 3U25 2 E3 FUAA B9 D lt 8 UA 373 2 3 D 3025 3 E2 1026 L Meng 1 418 9 NOT FOR 5000 SERIES 3025 4 2 029 2 9 3026 1 IU30 lt ENABLE 1V8 3026 2 IUA1 4 4 3925 4 5 3U26 3 F3 IUA2 B5 100K RES Mg 4 VA T 1 3U26 4 F3 3U25 3 2 ___ 3029 1 6 ri 3029 1 ii i 3U29 2 E3 IUAS
63. 356 4 10K RREF lt 4 3800 RESET SYS gt RESET SYSTEMn 3S64 FS64 Box BACKLIGHT PWM 3V3 gt e BL PWM gt 10K CLK 54 OUT BSS NSS HSS 022 Q2 Q2 3883 10K 3584 3V3 3V3 TXD1 MIPS 3872 IS40 10K 4 gt PXCLK54 47 3V3 5 SCL DISP SCL DISP 2 1 2 lt seg 4KT 8 SCL BL SCL BL 2 1 gt lt 3867 SCL SET 4 SDA DISP SDA DISP 2 1 7 2 3968 SDA SET Se SDA BL SDA BL do FS31 AMETE m Emm 9810 SCL BL IS08 SCL SET 4 s 9511 e S2w SCL DISP 12 FS2Y 95 e SDA DISP 1509 SDA SET gt 9513 Se SDA BL 7800 4 PNX85500 ETH RXCLK s ETHERNET ETH RXD 0 gt ETH RXD 1 s lt ETH TXCLK ETH RXD 2 gt 550 ETH RXD 3 gt gt ETH TXD 0 S ETH TXD 1 ETH RXDV gt 5 ETH TXD 2 ETH RXER S 5 ETH TXD 3 s ETH TXEN SDIO DAT3 gt Se ETH TXER SDIO CLK lt lt ETH COL SDIO CMD lt lt ETH CRS SDIO DATO gt gt ETH MDC SDIO DAT1 Se 5 SDIO DAT2 S SDIO CDn S SDIO WP s B back to 2010 02 DIS 10 11 12 13 PNX85500 14 8204 000 8950 1F10 A12 2589 08 3500 B5 3821 B1 3526 5 3827 C6 3840 A1 3845 A1 3555 C3 3556 A5 3557 A6 3558 A5 3557 3S5Y B5 3552 B6 3560 B5 3561 B6 3562 B1 3564 C1 3565 E11 3566 E11 3567 E11 3568 E11 3569 A9 3S6A A8 3S6B A9 356 B8 3560 B9 3S6E B8 3S6F
64. 3B01 1 PWM B1 24V 3807 1 4 10K lt SPI CLOCK gt 8 3 100R 5 SPSCLOCK ByF 7B23 1 BC847BS GOL 2 2 3B07 2 gt 10K FB30 PWM R1 45 5 3807 4 4 10K 7000 7001 7002 7003 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 7B23 2 7004 99 235 RSBB7C A24 2D 2 Z 3B11 T 2B08 3004 s 10K RES 2B09 10 3B39 1 1K5 196 7005 99 235 RSBB7C A24 2D 3B35 270R 3B36 270R BC847BS GOL 3B37 5 3 L8 3B07 3 6 10K 68R 1 PWM G1 24 3813 3 6 10K 7B25 BC847BW 8 1 L5 3B13 4 10K FB32 B007 10 eU x 11 12 13 1 3B03 1 8 1K5 2 3B03 2 7 1K5 3 3B03 3 6 1K5 4 3B03 4 5 1K5 B 4 24 14 3831 B10 3834 013 3835 G14 3836 G14 3837 G14 3839 1 13 3839 2 012 3839 3 013 7000 G5 7001 G7 7002 G8 7003 G10 7004 G11 7005 G13 7806 D3 7807 04 7820 1 08 7820 2 E8 7B23 1 F4 7B23 2 G4 7B25 H3 7B26 1 A8 7B26 2 C9 7B30 D13 FBO1 A1 FBO3 04 B1 FBO05 6 B2 07 FBO08 FB10 B2 FB11 B1 FB12 B2 FB13 C1 FB15 C1 FB16 C1 FB20 B7 FB30 G3 FB31 FB32 FB35 A8 FB40 012 FB41 E138 AL 2K10 Everlight 15 LED Common 8204 000 9059 2009 11 27 2009 11 03 18
65. 5 2 Error code overview which causes the failure of the TV This approach will especially be used for home repair and call centres The aim here is to have service diagnosis from a distance Blinking LED procedure LAYER 2 error Via this procedure the contents of the error buffer can be made visible via the front LED In this case the error contains 2 digits see table 5 2 Error code overview and will be displayed when SDM hardware pins is activated This is especially useful for fault finding and gives more details regarding the failure of the defective board Important remark For an empty error buffer the LED should not blink at all in CSM or SDM No spacer will be displayed 5 7 2 When one of the blinking LED procedures is activated the front LED will show blink the contents of the error buffer Error codes greater then 10 are shown as follows 1 long blinks where 1 to 9 indicating decimal digit 2 Apause of 1 5s short blinks where 1 to 9 4 pause of approximately s 5 When all the error codes are displayed the sequence finishes with a LED blink of 3 s spacer 6 The sequence starts again Example Error 12 8 6 0 0 After activation of the SDM the front LED will show 1 Onelong blink of 750 ms which is an indication of the decimal digit followed by a pause of 1 5 5 2 Two short blinks of 250 ms followed by a pause of 3 s 3 Eight short blinks
66. 5582 50 31 7 00 7 02 EDE1116AGBG EDE1116AEBG 7803 7801 3 EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG FLASH NANDO2GWSB2DN6F un M NANDO4GWSB2DNG6F 0 2 0 13 6000 Serie 256MB CE O sa A p 8000 Serie 512MB PNX85500 MIPS EWJ USB HUB SELECT SAW 21 04 ETHERNET SERVICE 173 ETHERNET I BACKLIGHT PWM 2 7E10 52 AE4 RESET SYSTEMn Cee 45V USB2 i i3 RESET SYS EREZA LAN8710A EZK 2 SPI CS 8710 428 PNX SPI CS AMBIn 813 1P08 SPI CS P GPIO 7 STE 2 USB_DN SIDE USB I USB DP2 E 7 ETH RXCLK AA3 USB DP 20 _ 7 AA2 SE eee rcc i Lc cuc 2 as CONNECTOR p 5V USB1 1 i RJ45 Y23 RXD1 MIPS 1P07 UART va TXD1 MIPS SERVICE USB DM1 p SIDE USB DVBS CONNECTOR BOARD pc CONNECTOR USB DP1 CONNECTOR CONNECTORS E NN 6000 Serie PNX85500 STANDBY CONTROLLER PNX85500 CONTROL 9CHO BOOST PWM BACKLIGHFBOOST
67. 6 7 Total Overview SAM modes 6 1 General Alignment Conditions 6 3 1 Perform all electrical adjustments under the following conditions Power supply voltage depends on region AP NTSC 120 or 230 Vac 50 Hz 10 AP PAL multi 120 230 Vac 50 Hz 10 EU 230 Vac 50 Hz 10 LATAM NTSC 120 230 50 Hz 10 US 120 VAc 60 Hz 10 e Connect the set to the mains via an isolation transformer with low internal resistance Allow the set to warm up for approximately 15 minutes Measure voltages and waveforms in relation to correct ground e g measure audio signals in relation to AUDIO GND Caution It is not allowed to use heat sinks as ground Test probe 10 Ci lt 20 pF e Use an isolated trimmer screwdriver to perform alignments 611 Alignment Sequence e First set the correct options n SAM select Option numbers Fill in the option settings for Group 1 and Group 2 according to the set sticker see also paragraph 6 4 Option Settings Press OK on the remote control before the cursor is moved to the left submenu Option numbers select Store and press OK on the RC OR In main menu select Store again and press OK on the RC Switch the set to Stand by e Warming up 15 minutes 6 2 Hardware Alignments Not applicable 6 3 Software Alignments Put the set SAM mode see Chapter 5 Se
68. 7204 4 7205 5 7203 7204 7205 1M84 D 1 8 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D SPLOLOCIEBUF SPI DATA OUT 2 Blue 5 6 a 3 4 Green 1 2 1 PWM CLOCK BUF 5 3V3 6 Red 3 4 1 SPI CS 7 LAT B on 9 BLANK i 3V3 12 14 TEMP SENSOR las 16 17 18 20 21 22 23 24 24 p gt 25 FD18 26 2 8003 8004 8005 15 LED Everlight 8204 000 9062 AL 2K10 3104 313 64211 18770 660 100212 5 100219 E back to 2010 Apr 02 div table 15 LED Everlight Circuit Diagrams and PWB Layouts Q552 1A LA EM LUE AL2B 15 LED Everlight 1 8 3D02 1 1 10K 2 7D01 1 BC847BS GOL 2 il 2 3002 2 7 10K 1 11 12 13 B4 3D10 24 24V 7300 7301 7302 7303 7304 7305 68R 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D RES gs 505 5 6 5 6 5 6 5 6 5 6 5 6 B Ace BC847BS GOL 1 2 1 2 1 2 1 2 1 2 1 2 3D12 e 68R i 5 3 4 3 4 3 4 3 4 3 4 3 4 A 4 12 T e 3D13 1
69. 7UCO 7002 or 7UD3 will heat up this device strongly Switching frequencies should be 500 kHz 600 kHz for 12 V to 1 1 V and 12 V to 1 8 V DC DC converters 900 kHz for 12 V to 3 3 V and 12 V to 5 V DC DC converters The DVB S2 supply 24 V to 5 V and 24 V to V LNB DC DC converters operates at 300 kHz while for 5 V to 1 1 V DC DC converter 900 kHz is used Exit Factory Mode When is displayed in the screen s right corner this means the set is in Factory mode and it normally happens after a new SSB is mounted To exit this mode push the VOLUME minus button on the TV s local keyboard for 10 seconds this disables the continuous mode 2010 Apr 02 LI EH Q552 1A LA service Modes Error Codes and Fault Finding Then push the SOURCE button for 10 seconds until the disappears from the screen 5 8 6 Logging When something is wrong with the TV set f i the set is rebooting you can check for more information via the logging in Hyperterminal The Hyperterminal is available in every Windows application via Programs Accessories Communications Hyperterminal Connect a ComPair UART cable 3138 188 75051 from the service connector in the TV to the multi function jack at the front of ComPair box Required settings in ComPair before starting to log Start up the ComPair application Select the correct database open file Q55X X this will set the ComPair interface in the appropriate mode
70. 97493 52404 7205 7204 7209 SIE EO DA 7301 8 IL xc 7401 7402 7403 7404 E 7202 a ss reos e aliod Em 25 7001 2582 7003 7004 3104 313 64211 3104 313 6421 1 18770 672 100216 eps 100325 back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM 10 9 B01 820400089943 Tuner HDMI amp CI Common Interface B01 A Common Interface 1 2 3 4 5 6 7 8 9 10 11 1P00 A D10 1P00 B G10 2F00 A6 ava 2F01 A2 3F06 CA RST 100K T y sn TRANSPORT STREAM FROM 200 RES aod 2F02 B6 T 100n 3 Tk 1 N s DUE 2 7 2 7 2203 06 10K A x 19 CA DATAENn 3F07 3 6 4 4 33 2F04 E6 ha 10K L CA MOCLK lt TA
71. B14b B03e B03e 1M59 3V3 VINT 5HA1 VIO 11 72 24V ___ eese 11 NET TCONCONTROL SHARP 0 E B14b vpisP 4VDISP 12 1 5KAA VDD12 i E LVDS AVDD 1 l mini_AVDD SSCG_AGND ava L gt VDD33 E ue mg EN SHARP 1 1 2 1V2 VDISP INT VDISP INT VDISP VGH_35V 6 C GAMMA 8 amp FLASH SHARP vcc ava vcc ava VDISP VLS_15V6 VLS_15V6 7KQA ISL248371RZ M VREF 15V2 3V3 15V2 15 2 gt gt VDISP VDISP vis 15ve VLS 15V6 MMC i BO6b EEG vivos 7 0 vaL 6 VGL 6V VGH_35V VGH_35V 3V3 VLS_15V6 vLS 15V6 BERE EAE connectors 43V3 3V3 3V3 STANDBY 43V3 STANDBY 5V 1M20 Bila 12 12 IR LED PANEL B08a B14b B14a c d B14c d e B14a c d e B14e B14e B14d TO IR LED PANEL 18990 406 100331 eps 100331 Circuit Diagrams PWB Layouts 10 LIN 10 Circuit Diagrams and PWB Layouts 10 1 AL1 820400089786 AmbiL
72. B9 3S6G B8 3S6H 1 B8 3S6H 2 B9 3S6H 3 B9 3S6H 4 B9 3569 C5 3S6K B9 3872 C6 3580 B1 3581 B1 3582 B1 3583 C1 3584 C1 7500 3 4 7500 4 G12 7501 E8 9510 8 9511 8 9512 8 9513 8 0552 2 FS10 B2 FS11 B2 FS2W F9 FS2Y F9 FS31 F8 FS44 A12 2549 A12 FS50 A12 FS51 B12 FS52 B12 FS53 B12 FS57 B12 FS64 C2 1504 B2 1505 A2 1508 F8 1509 F8 1540 C6 1547 1550 G12 6 2009 12 07 2 07 18770 515 100118 eps 100118 Circuit Diagrams PWB Layouts Q552 1A LA ES LIN PNX Video Out LVDS PNX Video Out LVDS 7500 7 PNX85500 1 4 A7 1 22 7 PXIB C8 PXIBe 2 B8 PXICLK g C10 PX1CLK 2 B10 1 A9 2 B9 D PXID A11 PXID g B11 1 C12 2 812 PX2A 14 2 814 2 15 2 2 15 PX2CLK g C17 E PX2CLK 17 2 g A16 PX2C 2 816 PX2D A18 PX2D B18 PX2E g C19 PX2E 2 B19 2010 Apr 02 LOUT1 LOUT3 LOUT2 LOUT4 back to div table D7 __ 7 Se __ 8 Sp PX3B D8 __ 10 10 D9 __ E9 Se PX3C D11 __ E11 PX3D E12 D12 Se __ 014 E14 __ 15 PX4B D15 4
73. BS10 F10 8513 E9 BS15 F9 BS17 F10 1511 F13 IS4V B10 IS4W C10 155 09 IS5D E9 IS5E E9 IS5F E9 IS5G E9 IS5H 9 IS5J E9 8204 000 8950 6 2009 12 07 18770 519 100118 eps 100118 Circuit Diagrams PWB Layouts ELLEN EIE 10 11 820400089514 CLASS D Audio Audio 2001 AUDIO R gt 9 24V AUDIO POWER p 3D09 7003 1 BC847BS COL FD14 ID14 4R7 O 5 ols C N N N A 5D07 220R 5D08 7 10u 35V 24V AUDIO POWER A PLOP 3D02 3 6 3 gt FD03 AUDIO L gt 4K7 ID15 D 7 220u 35V 2 D 1 GND AUDIO 7D10 1 TPA3120D2PWP 22K GND AUDIO 3D14 4 22K 3D14 3 22K 3D14 2 22K 2D22 220n 2D26 1735 E8 1038 E9 1050 E8 1052 F8 2001 F7 2002 F4 2003 2005 A5 2006 A5 2007 B5 2008 B6 2009 C7 2010 C7 2011 C8 2012 C8 2013 F8 2014 E8 2016 C4 2017 C4 2019 B6 2020 B5 202108 2022 B8 2D23 B4 2D24 B4 2D26 B8 2D27 D8 2D28 B2 2029 B2 FD06 E8 2007 F4 FD14 A5 IDO5 C8 1206 C8 1007 1008 1009 7 1010 C7 ID11 A4 ID12 A5 1013 ID14 B3 ID15 B3 ID18 C5 ID19 C5 ID27 B6 ID28 B6 ID29 C5 ID30 C5 ID31 C6 ID32 C6 1033 1034 D3 ID35 D3 ID36 E2 ID37 D4 ID38 D5 ID39 E2 3D01 1 D3 3D01 2 D3 3D01 4 E2 C 3D02 B3 RIGHT SPEAKER
74. C6 S Y ag 3029 3 IUA6 E5 029 ll 3U29 2 RES 3029 4 IUA7 470R 7UA4 a E de DS 4 3029 36 RES TS431AILT e 3UA1 IUA9 B6 Ys m 9 g SUAZ B3 IUBO F6 4 3029 4 2 um 1 B4 IUB1 E8 Me RES SUA4 A4 IUB2 C2 ae 5 6 IUB3 C3 F 3U262 RES 1 F 3UA6B5 1084 03 470R gt vi AA i dd ene i 3UA7 B6 IUB5 C2 3 p 4 100K 1KO m 22n 3UAB8 B5 IUB6 B3 470R 9 05 ANS T RES 3UBO D6 3UB1 E6 1 2 3 4 5 6 7 8 9 DC DC 8204 000 8951 L Ej 18770 523 100118 eps 100118 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 DC DC 1 2 3 4 5 6 7 8 2027 B8 2028 08 2000 A2 2001 A2 2002 2003 B3 5000 IUS 2004 5 12 3 amp 30R 5V5 TUN 2005 5 2006 B6 IUD3 500 IUD7 GUDO FUD3 2UD7 B6 4 WYN J 5V 2008 C2 3u6 5536 1 1 es T 7UDO 1 OL O ST1S10PH 10u U RES 1nO 2004 22u 2UD5 22u 2UD6 7 220 16 00 RES 2UE9 22u 6 RES 2U27 7005 1 2 BC847BS COL 1027 RES 1 96 3UDO 68K 3UD1 10K 2U
75. Circuit is built around item no 7850 7851 7C20 and 7C22 diagram AL 1B Refer to figure 7 19 Overvoltage Protection Circuit 7B23 1 BC847BS COL 6 7000 7001 7002 7003 7004 7005 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D BLUE BLUE 65 BLUE 6 5 BLUE 6 GREEN 7B25 BC847BW 3 18770 218 100126 eps 100126 Figure 7 19 Overvoltage Protection Circuit 7 9 TCON This section describes the application with the TCON integrated on the SSB For the basic application refer to figure 7 20 TCON architecture back to 2010 Apr 02 div table LIUM Q552 1A LA Circuit Descriptions LVDS 10 bit Timing Controller TCON Mini LVDS Control Signals Gamma Reference Source Drive IC aa e LO LO gt 16 TFT LCD Panel Vau 28 Vat 6 V Gate Drive IC Main Platform LCD Panel 18770 238 100127 eps 100402 Figure 7 20 TCON architecture For the TCON block diagram refer to figure 7 21 TCON block diagram Timing Controller IC Spectrum Mini LVDS Transmitter Data Path LVDS Receiver Block Line Buffer Mini LVDS Transmitter LVDS Gate Driver Receiver Ctrl Signals gt Formatter Serializer Power Control Contrast Control Optimum Drive Circuit Dynamic Vertical amp Horizontal Timin eneration Source Driver 99
76. Ctrl Signals Hsync Enc 55 Spread Spectrum Clock EEPROM 18770 239 100127 eps 100127 Figure 7 21 TCON block diagram back to 2010 Apr 02 div table Circuit Descriptions Q552 1A LA EN 47 Notes to figure 7 21 TCON block diagram e Timing Control Function generates control signals to e LVDS receiver converts the data stream back into RGB column drivers and row drivers Source Enable SOE data and SYNC signals Vsync Hsync Data Enable DE Gate Enable GOE Gate Start Pulse GSP ODC Over Drive Circuit to improve LC response For an overview of the TCON DC DC converters refer to figure e Data Path Block the video RGB data input to data path 7 22 ICON DC DC converters block is delayed to align the column driver start pulse with the column driver data Where Used To Gate Drivers Gate High Voltage DC DC Controller To Gate Drivers Gate 6V Low Voltage Timing Controller IC nons Supply Voltage Timing Controller IC Supply Voltage 1V2 Gamma Reference Source Driver Supply piove Voltage 18770 240 100128 eps 100128 Figure 7 22 TCON DC DC converters 7 9 1 TCON Programming For LGD TCONs the EEPROM can be programmed via ComPair via 2 communication For Sharp TCONSs the data can be flashed with a SPI Programmer via SPI communication This device has to be ordered separately via Philips 7 9 2 TCON Alignment The purpos
77. E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 LIN Toshiba Supply Toshiba Supply 2 2FA2 C1 2FA3 C2 2FA4 C3 A A B2 2 C2 FFAF B2 1V2 BRA DR1 1V2 BRA VDDC B B 7FA3 lt iC rx LD1117DT12 Ts gt FFAF n IN OUT a COM i 6 215 O EO L lt FFA2 e Not yet implemented 1 2 3 8204 000 8994 18770 506 100118 5 100118 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA ES LIN HDMI 1P05 B1 3FBF 1 C4 3FBF 2 C4 FFB1 C2 FFB2 C2 FFB3 C2 FFB4 C2 FFB5 C1 FFB6 C2 1 2 3 4 HDMI CONNECTOR SIDE 1P05 2 DRX2 y 3 DRX1 B L 5 gt DRX1 5 DRX0 E DRXO x _ DRXC E LL 11 1 gt DRXC m 5 PCEC HDMI 14 i a DRX DDC SCL N DRX DDC SCL DDC DDC 7 i DRX DDC SDA 7 DRX DDC SDA 2 DIN 5V 17 47K C 18 e _ gt pin sv C e E DRX HOTPLUG 5 21 FFB6 8204 000 8994 18770 507 100118 eps 100118 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM VGA
78. EB 7B23 1 F4 7B23 2 G4 7B25 H3 7B26 1 A8 7B26 2 C9 7830 D13 FB01 A1 B1 FB04 B1 05 B1 FB06 B2 FB07 B1 FBO08 B1 FB10 B2 FB11 B1 FB12 B2 FB13 C1 FB15 C1 FB16 C1 FB20 B7 FB30 G3 1 FB32 13 2835 8 FB40 D12 FB41 E13 8204 000 8978 DEZEN ESTA 18770_600_100212 eps 100218 Circuit Diagrams PWB Layouts Q552 1A LA ES LIN LiteOn LED Common 2 AL1 B LiteOn 15 LED Common 2 AL1 B 1 2 4 5 6 7 8 9 10 11 12 2850 C11 3850 B7 3B51 B7 mM o A 3B52B7 3B53 1 B7 3B53 2 C7 3B53 3 C7 3B50 3B53 4 C7 7105 7104 7103 7102 7101 7100 LTW 008RGB LTW 008RGB 270R LTW 008RGB LTW 008RGB LTW 008RGB LTW 008RGB 3855 1 C3 lt 5 3B55 4 4 10K 3 3B55 3 6 10K FB70 PWM B2 lt 9 z D i i B 3B55 2 B3 i52 x 7B50 2 BC847BS COL 3 1 2 3852 1 68R 4 3853 1 3B55 3 A3 3 55 4 3857 2 03 3B57 3 C3 uu 3 00 1 03 S L 3 00 2 F3 Des 3C00 3 F3 3 00 4 3 06 1 G3 3 06 2 3C10 F4 3C11 F4 3C12 F4 3C15 1 G4 3C15 2 G4 3C15 3 G4 M 3015 4 G4 7100 B11 i 7101 B10 7102 B9 7103 B7 5 8 1 3B55 1 8 10K wo wo pA B50 00 T 2871 PWM G2 lt e 2 3 3B57 3 6 LJ 10K 1 FB72 U 7 3857 2 gt 10K 2 lt
79. F2 1061 E4 4 gt 5 1U40 Ma9 5 ies x 6 x po T 3 0A 32V D A BOBA eU gt 2 3082 5 1964 C6 5 Pu p gt 24V AUDIO POWER 2 f 8 3083 1 06 10 FU68 3U76 Misco BC847BS COL 3083 2 5 11 7 s 5i TEES 3U83 3 5 Bru Wo 5 g 3U60 1 ENABLE 3V3n 17846 G _ NTS 3298 828 lt 3U83 4 C5 F GNDADO o lt 3U73 Soet 1056 u 4 ust 22 S S 5 S 5 3V3 STANDBY p gt 8 I Ami x i s 7U41 1 5 lt BC847BS COL 2 gt 1 1 2 3 4 5 6 7 8 9 DC DC 8204 000 8951 18770 522 100118 eps 100118 back to 2010 02 table Circuit Diagrams PWB Layouts Q552 1A LA EE 2UAO A5 3UB3 F6 2UA1 A4 3084 F5 2UA2 B5 3UB5 F5 ee 2UAA A7 3UB6 2 C2 Y Y 2UA5 B6 3UB6 3 C2 A 12V i 2UA0 1 A 2UA6 B7 3UB6 4 C2 Y DA og won 2UA7D4 3UB7 1 D3 5 TS ol UAE 4 x 8 2UA8 05 3UB7 2 D2 325 3 2UA9D5 3087
80. FGA2 G3 FGA5 G5 IGA1 C11 3G12 E6 3G15 E2 3GA2 2 G3 5 1 B12 3GA5 4 B12 3GA6 3 F12 5GA1 B2 6GA2 F13 7GA1 1 D13 7GA2 2 E12 FGAO A5 FGA3 G5 FGA6 G4 IGA2 C11 6 8 9 10 11 12 13 14 15 DEBUG ONLY 1837 3V3 p gt 1 GCK3 lt 3GA5 4 4 5 3 GTS1 lt 3GA5 3 3 6 1008 4 GTS2 E 3GA5 2 2 7 100R 5 GSR 3GA5 1 1 8 100R 6 100R SD51022 IGAO CPLED1 e IGA1 CPLED2 e IGA2 CPLED3 e 3V3 3 AMBI SPI CLK OUT R AMBI SPI SDI OUT_G1 R GCK3 Se 5 7GA1 2 AMBI SPI SDO OUT R 3V3 5 PNX SPI CSBn 6 9GA1 BACKLIGHT PWM 6 7 8 CPLED1 GTS1 Ss 2 7GA1 1 12 BL SPI SDO BC847BS COL 13 BL SPI SDI 14 lt BL SPI CSn 3 3 16 3GA1 m BACKLIGHT PWM BL VS 18 47R s BL SPI CLK 3 19 3 6 AMBI PROG B1 GTS2 5 7GA2 2 20 3G10 3 100R 2 7 AMBI BLANK R1 BC847BS COL 21 1 8 3G10 2 100R AMBI SPI CS EXTLAMPSn 4 22 3910 1 1008 AMBI SPI CLK OUT 3V3 23 i 3G13 100R AMBI SPI SDI OUT G1 27 3812 108 4 5 Gs AMBI SPI SDO OUT 6 28 8 1 3G10 4 100R s AMBI LATCH2 DIS 3G11 1 100R GSR Se 2 7GA2 1 n BC847BS COL UM i E _ EM Bo e S S 8 Y 2c 9 S Te 8 8 S S 518 328 328 5 28 328 2 2 VE aN 770 5 515 21 5 5 BACKLIGHT PWM 6 7 8 9 10 11 12 13 14 15 LVDS Non DVBS 8204 000 8957 2010 02 back to 100125 Circuit Diagrams PWB Layouts Q552 1A LA 10 LE SPI Buffer B06 D SPI Buffer 1
81. L L 1 d Tg 54 9 ele 2 44 14 6E29 H3 IE53 7 1 IE90 a 2 AV1 B lt i a pos 555 o o o s vA 9 54 STF 2 50 12 6E30 1 18R lt 1 01 1 RES 8 5 2 51 12 6 1 111 els gle Son ele 359 3 EU L 2E 0 Q12 1669219 u u 2E73 H7 6E34 E11 5 AV2 STATUS 2 A IE89 lt 2 74 7 6E35 F11 L ar RES 3E16 12K 2E75 6E36 G11 YPBPR2 SYNCIN2 gt 8 8 2 76 14 6E37 H11 EU xe 2E99 WSs Bove S ETE 2 77 012 7 01 1 A6 ege m 3E83 18R 2E78 112 7E01 2 B6 AVI STATUS w v m 5p6 2E79 D1 7E04 H6 FE73 E AP A B da ob a e BC847BPN COL p OE 2E81 IE59 5E80 CVBS MON OUT1 Av4 Y IE56 5 78 3E84 E ES 1 YPBPR1 SYNCIN1 9E52 9E53 S 5 5 FE ij u 05 lt 99 e 5 7 3EB1 IE60 2 2 s 10 ET 1u8 18R i 2E82 C12 7 06 2 E6 7 18R 9 8 75 2L 2 8 1 8 8 78 5 8 2 83 F1 7 09 1 H2 28 05 8 2 84 F2 7E09 2 G10 o IE54 5E74 BEC4 3E77 FE8o L L Q 2 85 F1 9E01 D6 o 7 L t RES 2E86 F2 9 02 07 18 18R gt 2E87 A4 9E05 F4 a BU 5 3E85 18R 1EP2 8 8 8 8
82. LA Alternative BOM identification It should be noted that on the European Service website Alternative BOM is referred to as Design variant The third digit in the serial number example AG2B0335000001 indicates the number of the alternative B O M Bill Of Materials that has been used for producing the specific TV set In general it is possible that the same TV model on the market is produced with e g two different types of displays coming from two different suppliers This will then result in sets which have the CTN Commercial Type Number e g 28PW9515 12 but which have a different B O M number By looking at the third digit of the serial number one can identify which B O M is used for the TV set he is working with If the third digit of the serial number contains the number 1 example AG1B033500001 then the TV set has been manufactured according to B O M number 1 If the third digit is a 2 example AG2B0335000001 then the set has been produced according to B O M no 2 This is important for ordering the correct spare parts For the third digit the numbers 1 9 and the characters A Z can be used so in total 9 plus 26 35 different B O M s can be indicated by the third digit of the serial number Identification The bottom line of a type plate gives a 14 digit serial number Digits 1 and 2 refer to the production centre e g AG is Bruges digit 3 refers to the B O M code dig
83. Measure the resistance value between the pins of the Mains AC Power plug and the metal shielding of the tuner or the aerial connection on the set The reading should be between 4 5 and 12 4 Switch off the set and remove the wire between the two pins of the Mains AC Power plug Check the cabinet for defects to prevent touching of any inner parts by the customer Warnings All ICs and many other semiconductors are susceptible to electrostatic discharges ESD Careless handling during repair can reduce life drastically Make sure that during repair you are connected with the same potential as the mass of the set by a wristband with resistance Keep components and tools also at this same potential careful during measurements in the high voltage section Never replace modules or other components while the unit is switched on When you align the set use plastic rather than metal tools This will prevent any short circuits and the danger of a circuit becoming unstable Notes General e Measure the voltages and waveforms with regard to the chassis tuner ground 4 or hot ground depending on the tested area of circuitry The voltages and waveforms shown in the diagrams are indicative Measure them in the Service Default Mode with a colour bar signal and stereo sound L 3 kHz R 1 kHz unless stated otherwise and back to div table 3 3 2 3 3 3 3 3 4 3 3 5 picture
84. PSL stands for Power Supply with integrated LED drivers e PSLS stands for a Power Supply with integrated LED drivers with added Scanning functionality added microcontroller 2010 Apr 02 LIUM Q552 1A LA Circuit Descriptions e PSDL stands for a Power Supply for Direct view LED backlight with 2D dimming 7 2 3 Connector overview 73 DC DC Converters The on board DC DC converters deliver the following voltages depending on set execution 3V3 STANDBY permanent voltage for the standby controller LED IR receiver and controls connector 1M95 pin 1 e 12V input from the power supply for TV550 common active mode connector 1M95 pins 6 7 and 8 e 24V input from the power supply for DVB S2 in active mode connector 1 9 pins 1 and 2 1V1 core voltage supply for PNX85500 has to be started up first and switched off last diagram 1V2 supply voltage for analogue blocks inside PNX85500 1V8 supply voltage for DDR2 diagram 2V5 supply voltage for analogue blocks inside PNX85500 see diagram BOSE e 3V3 general supply voltage diagram BOSE 5V supply voltage for USB and CAM diagram BOSE e 5 V TUN supply voltage for tuner diagram BOSE V LNB input voltage for LNB supply IC item no 7T50 5V DVBS input intermediate supply voltage for DVB S2 diagram BO8A 3V3 DVBS clean voltage for silicon tuner and DVB S2 channel decoder e 2V5 DVBS clean
85. SWITCH 3B31 3V3 BLANK gt PWM CLOCK BUF 1K8 PROG 4 3800 4 5 L SPI CLOCK BUF 150R SPI DATA IN BUF lt SPI DATA IN 3 SPI DATA OUT 3 lt 3B21 5 20 LATCH 2 180062 1508 0 100 1 2804 1 100 2 2B04 2 7 2B04 1 B7 2B04 2 B6 2B04 3 B8 2B04 4 B7 2808 E12 2B09 E12 2B10 F9 2B11 A9 2B17 D8 2B20 D4 3004 E12 3800 1 3800 2 B6 3800 3 B6 2K0 3B00 4 B6 3B01 1 E7 3B01 2 D7 3B02 1 E3 C 3802 2 E5 3803 1 14 3803 2 14 3803 3 14 3803 4 14 3807 1 3807 2 23 3807 3 3 3807 4 23 100K RES 3B11 E12 Y Y Y 3B13 4 3B18 A8 3B21 B7 4 TEMP SENSOR A 47 gt e PWM CLOCK lt SPI DATA RETURN 8154 SPI DATA IN FB16 SPI CLOCK Ww VIA VIA 3B34 D SPI DATA IN BUF gt 3V3 SPI CLOCK BUF gt 3V3 7B30 FB40 lt i 3B39 2 1K5 196 3B39 3 1K5 1 PWM CLOCK 2 S 27 1 3830 1 5 PWNLCLOCIC BUF 7B06 74LVC1G32GW SPI CS gt 1 3B22 B8 3B30 1 D9 3B30 4 E9 100R DATA SWITCH 2 10K 10n 2 B001 B002 SPI DATA RETURN 3V3 3 02 1 10K 7B20 2 74LVC2G17 3V3 1
86. Vos BYPASSLLT 6 IN2 5 LISHUTDOWN 18770 309 100217 eps 100217 Figure 8 10 Internal block diagram and pin configuration back to _ _ div table 2010 Apr 02 LIE EM Q552 1A LA IC Data Sheets Personal Notes 10000 012 090121 eps 090121 back to 2010 Apr 02 div table Block Diagrams Q552 1A LA EM GEJ 9 Block Diagrams 9 1 Wiring diagram Matisse 42 46 WIRING DIAGRAM 42 46 MATISSE e co TJ 8M83 Board Level Repair Component Level Repair Only For Authorized Workshop BACKL CONDITIONAL ACCESS NET HDMI HDMI HDMI TO DISPLAY TO DISPLAY wet gt an T LOADSPEAKER LEFT 5215 4 LOADSPEAKER RIGHT 5215 LCD DISPLAY 1004 TCON MAINS CORD mmm 3191 1M59 B13 1 AMBI SPI CLK OU AMBI SPI SDO OUT AMBI SPI SDI OUT GI GND AMBI PWM CLK B2 V AMBI AMBI SPI CS OUTn R2 AMBI LATCH1 G2 GND 10 AMBI PROG 11 AMBI BLANK R1 12 V AMBI 13 AMBI LATCH2 DIS AMBI TEMP GND GND GND GND GND 24 24 24 24 24 1 38 AL1A 24 24V 24V 24V 24V GND GND GND GND 10 GND 11 TEMP SENSOR 12 N C 13 N C 3V3 BLANK PROG GND LATCH SPI CS 3V3 PWM CLOCK
87. When entering CSM error LAYER 1 will be displayed by blinking LED Only the latest error is shown n SDM mode When SDM is entered via Remote Control code or the hardware pins LAYER 2 is displayed via blinking LED e Error display on screen n CSM no error codes are displayed on screen n SAM the complete error list is shown Basically there are three kinds of errors Errors detected by the Stand by software which lead to protection These errors will always lead to protection and an automatic start of the blinking LED LAYER 1 error see section 5 6 The Blinking LED Procedure e Errors detected by the Stand by software which not lead to protection In this case the front LED should blink the involved error See also section 5 5 Error Codes 5 5 4 Error Buffer Extra Info Note that it can take up several minutes before the TV starts blinking the error e g LAYER 1 error 2 LAYER 2 error 15 or 53 Errors detected by main software MIPS In this case the error will be logged into the error buffer and can be read out via ComPair via blinking LED method LAYER 1 2 error or in case picture is visible via SAM How to Read the Error Buffer Use one of the following methods Onscreen the SAM only when a picture is visible E g 00 00 00 00 00 No errors detected 23 00 00 00 00 Error code 23 is the last and only detected error 37 23 00 00 00 Error code 23 was first dete
88. backlight panels colour analyser Minolta CS 200 Cool 11000K Normal 9000K Warm 6500K 0 276 0 287 0 313 0 282 0 296 0 329 If you do not have a colour analyser you can use the default values This is the next best solution The default values are average values coming from production Selecta COLOUR TEMPERATURE e g COOL NORMAL or WARM e Set the RED GREEN and BLUE default values according to the values in Table 6 4 and Table 6 5 e When finished press OK on the RC then press STORE in the SAM root menu to store the aligned values to the NVM Restore the initial picture settings after the alignments 6 4 6 4 1 Table 6 4 White tone default setting 42 White Tone Black level offset 5 Nomad Cool 127 t b d Wam 309 302 T2 ws Notes 1 data is preliminary and will be updated in next release Table 6 5 White tone default setting 46 offset LZ MER 154 Table 6 6 TCON default settings Screen size TCONAlgnment 6 4 2 6 4 3 Alignment of the Ambilight modules 6 4 4 Method e Goto SAM press 062596 OK button Select Alignments e Select Ambilight a white testpattern shall be displayed Select the number of module pixel that have to be aligned Module pixel
89. based fault finding program and an interface box between PC and the defective product The II interface box is connected to the PC an USB cable For the TV chassis the ComPair interface box and the TV communicate via a bi directional cable via the service connector s The ComPair fault finding program is able to determine the problem of the defective television by a combination of automatic diagnostics and an interactive question answer procedure How to Connect This is described in the chassis fault finding database in ComPair TOTV UART SERVICE I2C SERVICE UART SERVICE CONNECTOR CONNECTOR CONNECTOR ComPair RC out SRM do Optional Power Link Mode Switch Activity Il Developed P lips Brugge Optional power 5V DC 10000 036 090121 eps 091118 Figure 5 10 ComPair Il interface connection Caution It is compulsory to connect the TV to the PC as shown in the picture above with the ComPair interface in between as the ComPair interface acts as a level shifter If one connects the TV directly to the PC via UART ICs will be blown 5 5 2 How to Order order codes e ComPair ll interface 3122 785 91020 Software is available via the Philips Service web portal e ComPair UART interface cable for Q55x x using 3 5 mm Mini Jack connector 3138 188 75051 Note While encounting problems contact the local support desk back to div table
90. carrier at 475 25 MHz for PAL or 61 25 MHz for NTSC channel 3 Where necessary measure the waveforms and voltages with and without aerial signal Measure the voltages in the power supply section both in normal operation D and in stand by These values are indicated by means of the appropriate symbols Schematic Notes Allresistor values are ohms and the value multiplier is often used to indicate the decimal point location e g 2K2 indicates 2 2 e Resistor values with no multiplier be indicated with either an E or an R e g 220E 220R indicates 220 All capacitor values are given in micro farads u x 10 nano farads x 10 or pico farads p x 10 12 e Capacitor values may also use the value multiplier as the decimal point indication e g 2p2 indicates 2 2 pF e asterisk indicates component usage varies Refer to the diversity tables for the correct values e The correct component values are listed on the Philips Spare Parts Web Portal Spare Parts For the latest spare part overview consult your Philips Spare Part web portal BGA Ball Grid Array ICs Introduction For more information on how to handle BGA devices visit this URL http www atyourservice magazine com Select Magazine then go to Repair downloads Here you will find Information on how to deal with BGA ICs BGA Temperature Profiles For BGA ICs you must
91. followed by a pause of 5 4 Six short blinks followed by a pause of 3 s 5 Onelong blink of 3 s to finish the sequence spacer 2010 Apr 02 back to div table 6 The sequence starts again How to Activate Use one of the following methods Activate the CSM The blinking front LED will show only the latest layer 1 error this works in normal operation mode or automatically when the error protection is monitored by the standby processor In case no picture is shown and there is no LED blinking read the logging to detect whether error devices are mentioned see section 5 8 Fault Finding and Repair Tips 5 8 6 Logging Activate the SDM The blinking front LED will show the entire content of the LAYER 2 error buffer this works in normal operation mode or when SDM via hardware pins is activated when the tv set is in protection Protections Software Protections Most of the protections and errors use either the stand by microprocessor or the MIPS controller as detection device Since in these cases checking of observers polling of ADCs and filtering of input values are all heavily software based these protections are referred to as software protections There are several types of software related protections solving a variety of fault conditions Related to supplies presence of the 5V 3V3 and 1V2 needs to be measured no protection triggered here Protections related to breakdown of the safety ch
92. is the serial number as printed on the back of the TV set Note that if an NVM is replaced or is initialized after corruption this production code has to be re written to NVM ComPair will foresee in a possibility to do this Operation Hours Displays the accumulated total of operation hours not the stand by hours Every time the TV is switched on off 0 5 hours is added to this number Errors followed by maximum 10 errors The most recent error is displayed at the upper left for an error explanation see section 5 5 Error Codes Reset Error Buffer When cursor right or the OK button is pressed and then the OK button is pressed the error buffer is reset e Alignments This will activate the ALIGNMENTS sub menu See Chapter 6 Alignments Dealer Options Extra features for the dealers e Options Extra features for Service For more info regarding option codes 6 Alignments Note that if the option code numbers are changed these have to be confirmed with pressing the OK button before the options are stored Otherwise changes will be lost Initialize NVM The moment the processor recognizes a corrupted NVM the initialize NVM line will be highlighted Now two things can be done dependent of the service instructions at that moment Save the content of the NVM via ComPair for development analysis before initializing This will give the Service department an extra po
93. menu after the mains switch is turned on for the first time virgin mode Select E sticker On Off USP s on screen back to 2010 Apr 02 GES Q552 1A LA Alignments Submenu Subsmenus pss Digital features Off On Select Ethernet On Off No sensor On backside In display Sensor present Yes No and in case Yes where On SSB Temperature LUT N A Off On Select E box amp monitor On Off Video reproduction Off On Select Light sensor On Off Light sensor type 0 1 2 3 Select Light sensor type form O to 3 for difference styling Pixel Plus type Select type of picture improvement Natural motion type Perfect Natural Motion Natural motion type selection HD Natural Motion Ambilight Select type of Ambilight modules use 2 sided 3 3 2 sided 4 4 2 sided 5 5 2 sided 6 6 2 sided 7 7 3 sided 5 5 5 3 sided 6 6 6 3 sided 7 7 7 3 sided 6 9 6 Ambilight sunset Off On Ambilight sunset On Off Audio reproduction Acoustic system WWW Cabinet design used for setting dynamic audio pa rameters Source selection EXT1 AV1 type SCART CVBS RGB LR Select input source when connected with external CVBS Y C YPbPr LR equipment CVBS Y C YPbPr HV LR EXT2 AV2 type SCART CVBS RGB LR Select input source when connected with external CVBS LR equipment YPbPr LR None EXT3 AV3 type Select input source when connected with external CVBS equipmen
94. sies R25 USB DP USB DP2 CONNECTOR U MISIT X 1202 FLASH 1 U 7F20 nv HDMI SIDE Pr 15 TD NANDO2GW3B2DN6F B5MWUBB 1 NAND04GW3B2DN6F I 1P07 MEN EXT 11 AV4 Y x 7 AV4 PB AD14 A125 USB DP1 ee Oe _ 1205 123 a 43V3 H SYNC VGA MEMORY I V SYNC VGA AC IDDR2 D 0 31 VGA 7 00 7802 EDE1116AGBG EDE1116AEBG 7B03 7B01 AC15 C1 AE1 T EXT34 VIDEO 2 5lv ci 39 AD15 a Y SVHS AC12 DDR2 A 0 13 1ECB ATV_CVBS_Y3 m En 33 SVHS IN 5 C SVHS AF13 DDR2 VREF DDR 2 32 a 6000 Serie 256MB 8000 Serie 512MB CONNECTOR L re lt DDR2 VREF CTRL2 DDR2 VREF CTRL3 62 HDMIA RXC W25 2 72 o 025 63 HDMIA RXC W26 e 60 HDMIA RX0 V25 E E 61 V26 66 58 1 025 CRXO 65 2200 21 56 HDMIA RX2 T25 57 HDMIA RX2 T26
95. x lag 2858 H11 5982 A12 Lis m q 2559 111 5583 012 D ava sBv v18 de al D 2S5A A11 5S84 E12 Mh VDDA 1V1 LVDS 813 n lt vi 255 A11 5585 C12 zu es 3 5 255 B11 5587 F12 VDDA 1V2 2S5D B11 5S88 G12 voon ash To ME ur 013 Qa Me 2000 SENSE 1V2 U15 VDDA 2V5 ADAC gt 2S5G 4 B5 5S93 B12 E u17 VDDA 2 5 pcs 7 L 1 gs E J6 BENE 2S5H 1 B5 5894 F5 ane VDDA 2V5_LvDS Ba P 3 2S5H 2 5S95 E10 E T20 lt g VDDA_2V5_USB 2S5H 3 B5 7S00 10 B6 G9 8 VDDA 2V5 13 42V5 AUDIO 2S5H 4 B5 7500 12 e A i oca Bes z VDDA 295 vbac 19 5 8 2559 1 C5 IS3K 010 2 RES 5 5 5 5 MED 2 4 EE 2S5J 3 IS3Q A10 F i 42V5 AUDIO F 285J 4 C5 1535 A10 2 8 2S5K 1 C4 1558 110 s 2S5K 2 C4 c000 E13 L ex 2S5K 3 C4 c001 B5 Y Y Y 4 2 5 G lt q 2V5 LVDS S 85 5589 9 215 2S6H 100n 2S6K 100n 2558 10u 1 1 4 v5 ES c gt N T N 15 ore 1358 5892 lt 22 3 55858 e on A a 1 2 4 5 6 7 8 9 10 11 12 13 14 6 2009 12 07 2 07 8204 000 8950 jJ 18770 518 100118 eps 100118 PNX8
96. 0 7 50 1 T zo 7 50 2 7 Eo 7B51 C3 7 20 1 poe 7C20 2 F3 7C22 G3 FB70 B3 FB71 C3 FB72 D3 FC01 F3 FCO2 G3 1 2 3 4 5 6 7 8 9 10 11 12 FC03 EUH 1 27 AL 2 1 0 Everlight 2009 11 03 15 LED Common 9204 000 9059 l 2 18770 671 100212 5 100212 1 3C00 1 8 10K 1 3 06 1 8 10K 1 7 3 06 2 2 10K PWM R3 lt e E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM LUZ 10 6 AL1 820400090601 9 LED Everlight 9 LED Everlight 9 LED Everlight 1 2 3 4 5 6 7 8 9 10 1M84 10 2D01 B6 7203 A3 7204 4 7205 A5 7203 7204 7205 1M84 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D SPI CLOCK BUF SPI DATA OUT 2 5 6 SPI DATA RETURN 3 4 1 2 PWM CLOCK BUF gt C 5 3V3 3 4 1 SPI CS 7 2 B LATCH lt a B 8 8 9 3V3 p gt C 12 13 14 15 116 17 C 18 19 20 C 21 24 24 s C 125 B003 B004 11 9 LED Everlight 8204 000 9060 AL 2K10 3104 313 64191 I 18770 640 100212 5 100219 E back to 2010 Apr 02 div table Circuit
97. 17 PXACLK 017 PX4CLK 016 16 __ 018 __ 18 Se PX4D E19 D19 PX4E 10 10 11 11 12 12 13 13 PNX85500 14 14 7S00 7 C8 A B C D E G 8204 000 8950 jJ 18770_516_100118 eps 100118 PNX Stand by Controller PNX Stand by Controller 3V3 STANDBY Circuit Diagrams and PWB Layouts Q552 1A LA ES LIN RES 5804 2837 2811 3V3 STANDBY gt 3V3 STANDBY gt 2540 3518 ind RC RC 3516 RES 10K TACHO lt 10K ssp CEC HDML TN CEC HDMI x 3S1E RES 27K Q BACKLIGHT PWM ANA DISP BACKLIGHT PWM ANA DISP 10K 3S1F gt SDM N SDM gt 10K 3531 RES gt LCD PWR ONn N LCD PWR ONn gt s 353M 10K 1 EJTAG DETECTn NEJTAG DETECTn lt 10K 3S3N RES LAMP ON 2 353P 10K STANDBY STANDBY 40K 3530 4 FAN CTRL1 N FAN CTRL1 RES 3535 10K 2 gt 10K 3538 POWER OK POWER OK c 383 10K RES 4 ENABLE 3V3n 7 N ENABLE 3V3n E OK Se 881H 10K TXD UP AN TXD UP 10K DETECT2 352 RES SERERE 10
98. 1L F5 IS1N C7 1515 07 544 H9 1 4 2528 C12 252 012 282J G12 252 F12 2521 04 2S2R B7 2828 B9 2521 B8 252 B3 252 2527 C3 2527 B3 3807 2530 C3 24V AUDIO POWER gt 2831 C3 487 24V AUDIO VDD 2532 D3 100R 3V3 2533 C3 3853 2 7808 3 6 LD3985M25 2 Fs03 2538 E9 2539 E9 LM324 44 3538 AUDIO L B 2830 ae 2S3D E8 2S3E 2S3F E2 2530 I 2S3H E3 I k 2530 B11 2 2S3K G6 s 2S3L H8 253 H9 C 2530 G5 2841 C6 2542 C6 3507 A11 3539 gt AUDIO R 3S10 D4 toon 3511 F5 3812 1 B2 3812 2 B2 3512 3 B2 3812 4 C2 3813 1 C2 3813 2 D2 3813 3 C2 3853 1 2V5 AUDIO 1 3516 1 8 1008 2S2W AUDIO IN1 L 95121 g 10K 3553 3 FS08 22K 100 1008 2 3553 4 c A 7 B 2 3512 2 3516 252 AAA 8 8 AUDIO IN1 R gt 7 10 1008 22K 1u0 3516 3 3 6 8812 3 g 2527 AUDIO IN2 L gt 10K 22K 100 s 3816 4 4 8812 4 ISOV 4 IN2 10K AUDIO IN2 R gt 5 0 22K 1u0 4 3817 4 1513 3514 12 7S05 4 ADAC 1 22K 2 3536 2 7 10K 3851 487 1u0 54 M 71 100u 4V 5 7800 2 2531 PNX85500 E E 2536 AUDIO ADACL AB7 3813 4 ISOR C AUDIO IN3 L gt i 5 10K 22K 1u0 24V AUDIO VDD 1799614 ADAC 1 tu 33R 3939 3 1503 4 3 6 10 7505 3 gt ADAC 2
99. 2 Figure 8 7 Internal block diagram and pin configuration back 2010 02 div table 8 8 Block diagram MODEO gt MODE1 gt MODE2 gt Control Management nRST RMIISEL Auto MODE Control Su lt E id Negotiation IC Data Sheets Q552 1A LA EM LEM Diagram Ethernet Service 4 LAN8710A EZKH IC 7E10 HP Auto MDIX 10M Transmit Section 100M Tx 100M Ls RXP RXN MDIX Control REN B XTAL1 CLKIN 100M Rx DSP System Analog to TXER TXCLK pita XTAL2 Data Recovery Equalizer gt nINT RXD 0 3 2 dpe i i 100M PLL RXER Receive Section RXCLK 7 gt LED1 o 10M Rx ane LED Circuitry gt a quelc COL CRS DV umm 10M PLL lt Bias MDIO PHY Address 0 0 2 Pinning information VDD2A LED2 nINTSEL LED1 REGOFF XTAL2 XTAL1 CLKIN RXCLK PHYAD1 RXD3 PHYAD2 Latches 27 VDD1A 32 RBIAS 25 TXD3 1 24 TXD2 2 23 TXD1 3 EN TXDO 4 21 TXEN LAN8710 LAN8710i 32 PIN QFN Top View 5 20 TXCLK 6 19 nRST y 18 nINT TXER TXD4 8 17 MDC NU O N 2 0 gt gt
100. 20 F11 3U23 2 C9 3U24 2 F9 3U28 D5 5003 A13 7U02 1 B6 H7 FUOS3 C14 1001 1005 03 1109 C6 1013 07 1017 F9 1021 H9 2002 04 2006 F1 2010 10 2014 14 2018 09 2022 08 2029 G14 3003 3009 3017 G10 3021 G13 3023 3 9 3U24 3 F9 5000 C10 6000 E8 7002 2 C6 FUOO G13 FU04 F4 1102 1106 1010 B6 1014 E8 1018 F9 1022 B13 2003 E2 2007 H3 2U11 F9 2U15 C10 2U19 B12 2U23 B5 3000 F1 3004 03 3010 3018 G10 3022 G2 3U23 4 C8 3U24 4 F8 5001 E10 7U00 F1 7003 ES FUO1 E14 2005 B9 IUOS F1 1007 04 1011 C6 1015 C9 1019 G10 1023 C9 1 2 5 6 4 8 10 12 13 14 15 5U03 RES 30R FU05 5002 1022 lt 12V 30R 9 7U02 1 a 3 D S o B 3 SI4952DY 2 2 5 o spe 1010 12V 1V8 CONVERSION 5 2021 FUO2 5000 FU03 id e N gt 1 8 1011 220p M co 3u6 ace els SMOS2DY 35 355 ay a C IU09 1023 n s 1015 7001 SI4778DY TN 3927 012 zy PONE 41 198 123 D 5 8 T 5 ed Stu 76 9 2U22 2002 1005 13 220p 100n S lt Ssg 7U04 7U03 SI4778DY TPS53126PW 5678 1024 1 14 1014 5 12V 1V1 CONVERSION gt 1 10 12 00 1V1 p 4 2 AS 5 mes gt 1V1 alo 1V8 9 13 4 5 200 5 TS DENN 15 GND SIG 8 15 3 T aoe ace 8 5 5 gt g 3U02 IUO SSS SSF 3255355 SSS u 5 x BC847BW
101. 278 AAA 3E17 E10 FE68 D12 e a cle 3E18 E7 FE70 A5 H z 8 B 8 3E07 3 H 3E19 E7 FE71 B4 L L L L 3 6 24 C7 FE72 C4 52 3E62 7 i 3EA7 2 3EB6 2 3E25 C13 FE73 E4 CVBS 2 7 AV1 CVB lt Bm a Tur dip 1 FE74 E4 5 BC847BW rv 3E32 E3 FE75 E4 hg e 7 3 6 3 3 6 1 8 68R lt 3E37 1 C3 FE76 G12 EN t E BSE s 9 s ele 6 470R 3 37 2 013 77 H12 9 8 9 on B 8 88652 3E37 3H13 FE78H12 42 2 7 7 4 FE79 F13 uM NES z P 3E39 H10 E4 VBS OUT SC1 gt T 44 6 3E43 H2 FE81 F4 49 Fond TS 3E44 G2 FE82 F4 BS 1 8 eR 5 4 45 G7 FE83 G4 i E OE gt 2 wo 7 3E48 G7 FE84 G4 8 m 3E11 3 3E49 7 FE85 G5 3E 222 2 H7 FEAO A7 all L L 3E61 G11 FEA1 B7 3E62 H2 FEC8 B13 63 1 A11 1205 D10 3E63 2 113 IEO8 E5 3E63 3 113 IE13 D6 3E63 4 B11 IE14 F5 1 2 3 4 5 6 7 8 9 10 11 12 13 ee G 75 D2 1 18 REF EMC HOLE 3E76 E2 IE20 B10 77 E2 IE21 C10 2009 10 22 I 8204 000 8952 _____ 18770 528 100118 eps 100218 E back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 Analogue Externals B B04B A
102. 2VD VDISP INT 4 B14b EU 3V3 p 5V B14b a ee 3 3 43V3 p 5E08 3V3 ET ANA Y p 107 19 HDMI 43V3 43V3 Bogh 5ECO 43V3 HDMI 43V3 STANDBY 43V3 STANDBY 45V VGA 45V VGA gt b 5V EDID 4 5 W A 5V B02b h B03d Bosa Tl AIN 5V CONNECTOR gt HDMI 2 BIN 5V CONNECTOR Hows 1202 CIN 5V B14b CONNECTOR 5 gt DiN sV DIN 5V ME L UU B14b _________ ____ __ __ __ __ __ __ HEADPHONE 1 ava gt 43V3 STANDBY 43V3 STANDBY ee 2010 Apr 02 back to 41V8 3B20 DDR2 VREF DDR BO2h gt TA DISPLAY INTERFACING VDISP 1 VDISP INT VDISP BO2h BO2h BO ava amer VDISP e c E ava BO01 a b c d e g jjk B14f SGA0 VINT B02a c d e h 5GA1 B03c f g h vo 2 2 m B06b c d E 09 SPI BUFFER 43V3 3 3 le kr cha cd B03c d B04a d 11 PPPW 2 aune B14f ava 3V3 STANDBY 3V3 STANDBY 1M20 8145 B14c 8145 B14b B14b B14b B14b
103. 3 4n7 100n 2E49 10u 2E48 5 7E10 1 LAN8710A EZK 10p 3E66 RES 10K 10K 3E33 10K 2 55 1 26 ETH RXD 0 x ETH RXD 1 9 ETH RXD 2 4 ETH RXD 3 lt 3E69 x 10K li 3E70 RES IE63 ETH COL RES 10K Y V WWW AA 9E43 3E71 10K RES ETH TXEN ETH TXD 0 ETH TXD 1 ETH TXD 2 D ETH TXD 3 ETH TXER w 10K 3E34 3E68 10K 2 m 42 w YYYYW Yw ETH MDC End ETH MDIO gt 196 3 40 12K1 SE51 1K5 4 3 22 3 26 228 98 228 RES 3 22 1 RES 3 95 1 RES gEos 3 6E47 6E48 6E49 6E50 RES ETH TXP ETHERNET CONNECTOR 1N00 ETH TXN FE27 e 00 28 e BE01 aww lt BE02 FE30 e FE31 3 e BE03 ETH INTSEL RES 2256 15p 15p 15p 2E58 RES 2 57 l RES 15 RES ETH REGOFF O G N 1551151 1 Resistor POP EMPTY 3E64 RES 3E65 RES 3E66 RES 3E67 RES 3E68 RES 3E69 RES 3E70 RES 3E71 RES 3E72 PHYADD 0 1 PHYADD 1 1 PHYADD 2 1 mode selected Inter
104. 3059 23359 40647 33551 34310 00000 00000 Important after having edited the option numbers as described above you must press OK on the remote control before the cursor is moved to the left 6 6 1 Reset of Repaired SSB A very important issue towards a repaired SSB from a Service repair shop SSB repair on component level implies the reset of the NVM on the SSB A repaired SSB in Service should get the Service Set type 00 0000000000 and Production code 00000000000000 Also the virgin bit is to be set To set all this you can use the tool After a repaired SSB has been mounted in the set set repair on board level the type number CTN and production code of the TV has to be set according to the type plate of the set For this new in this platform you can use the NVM editor in SAM This action also ensures the correct functioning of the Net TV feature and access to the Net TV portals The loading of the CTN and production code can also be done via ComPair Model number programming 6 6 2 In case of a display replacement reset the Operation hours display to 0 or to the operation hours of the replacement display SSB identification Whenever ordering a new SSB it should be noted that the correct ordering number 12nc of a SSB is located on a sticker on the SSB The format is 12nc SSB gt lt serial number The ordering number of a Service SSB is the same as the ordering number of a
105. 3F09 2 B9 SERES lt 3F09 3 B9 5VCA TT RES CA MIVAL 16 09 4 9 TALVC245A 100n gs CAD 12 10 1 9 1 CA A07 06 19 lt CA ADDENn XCA A05 3F1 0 2 C9 04 XIO A08 gt 18 2 gt CA A08 CA A03 10 3 9 02 XIO A09 17 3 CA A09 AN CA A01 A1 F 3F10 4 C9 F 10 S 16 4 s CA A10 CA A00 XIO A11 s 15 5 11 000 DO 3F11 1 D9 x 1 12 8 14 lt 2 WPJIOIS16 3F11 2 C9 3F11 3 09 10074595 11 4 9 3V3 RON 3F1 2 C9 BIT DATA 2 05 RES G i Troin CA CD1n lt G 7F00 A5 74LVCBASA MDO3 1 x CA DATADIR T MDO4 5 TF01 B5 O5 19 T CA DATAENn MbOS 5 7202 05 MDO7 XIO D00 18 2 gt CA D00 CA CE2n 7F03 E 5 CA VS1n lt 3 E eadem 7F04 G5 7 05 15 i 13 7 12 5 Wert mr gt IF01 A4 H XIO D07 11 9 s CA D07 lt CA NDI3 s H IF02 A5 5VCA CA IF03 A4 CA MDI6 CONTROL 2606 ges IF04 B9 lt TALVC245A a 4 IFOS C4 REF EMC HOLE REF EMC HOLE 1 1 1 IF06 C5 19 nd IF07 C5 L j 18 2 CA REGn xNpoo XIO D11 gt gt i XIO D09 17 3 gt CA CE1n pee IF08 09 2 XIO D08 lt CAEN CA CD2n lt L L gt 14 6 2 CAWER XIO D44 13 7 CA IORDn XIO D15 5 12 8 s CA IOWRn 10074595 050MLF
106. 3V3 when provided that 12V detected via 7U40 and 7U41 is present 5 8 5 back to div table 12V is considered OK gt DETECT2 signal becomes high 12V to 1V8 12V to 3 3 12V to 5V DC DC converter can be started up if it rises above 10V and doesn t drop below 9V5 Asmall delay of a few milliseconds is introduced between the start up of 12V to 1V8 DC DC converter and the two other DC DC converters via 7U48 and associated components Description DVB S2 e LNB RF1 OV disabled 14V or 18V in normal operation LNB supply generated via the second conversion channel of 7T03 followed by 7T50 LNB supply control IC It provides supply voltage that feeds the outdoor satellite reception equipment e 3V3 DVBS 3V3 nominal 2V5 DVBS 2V5 nominal and 1V DVBS 1 03V nominal power supply for the silicon tuner and channel decoder 1V DVBS is generated via a 5V to 1V DC DC converter and is stabilised at the point of load channel decoder by means of feedback signal SENSE 1V0 DVBS 3V3 DVBS and 2V5 DVBS are generated via linear stabilisers from 5V DVBS that by itself is generated via the first conversion channel of 7T03 At start up 24V becomes available when STANDBY signal is low together with 12V for the basic board when 3V3 from the basic board is present the two DC DC converters channels inside 7 are activated Initially only the 24V to 5V converter channel 1 of 7TO3 generating 5V DVBS
107. 5 4V 3 7V ox V5FILT vo1 2 02 vBST1 VBST2 DRVH1 _ DRVH2 3112 DRVL1 DRVL2 PGND1 PGND2 9 ozo 2 N N gt 5 50 V5FILT UY di m Ref VFBx THOK Om cio 5 Control logic TRIPx gt 5 H 2 DRVHx C LLx PGNDx IAE 7 VREGS DRVLx PGNDx LLx bd HE Git x inimun On OVP Foult Discharge Sdn Control PGNDx ENx gt Pinning information U 42 18250_300_090319 eps 100402 Figure 8 5 Internal block diagram and pin configuration back to 2010 Apr 02 div table IC Data Sheets Q552 1A LA EM GBEN 8 6 Diagram DC DC BOSE ST1S10PH 7900 Block diagram SA w 4 Same Block 9 P CONTROL LOGIC SN em 7 FE IHH AGHO Pinning information 4 x 4 PowerSO 8 18010 083 eps 100402 Figure 8 6 Internal block diagram and pin configuration back to 2010 Apr 02 div table LIN E Q552 1A LA IC Data Sheets 8 7 Diagram DC DC LD1117DT25 7902 Block diagram LD1117DT CURRENT j GENERATOR THERMAL THERMAL COMPENSATIO PROTECTION VOLTAGE GENERATOR VOUT GND SC08251 Pinning information 8 j Vin C 2 Vout GND PC11630 DPAK F 15710 166 eps 10040
108. 5 2 ADAC 6 M324 7 HS IS06 gt 6 AUDIO OUT R 7S09 1 11 3S53 1 A6 7ALVCOOAPW 3553 2 B6 G gt SPDIF OUT PNX SPDIF OUT PNX 1 253 G 3553 3 B6 1514 3553 4 B6 3834 3832 3561 F12 3S6M H8 wc OUR 7800 2 5 7805 1 12 7505 2 G12 7805 3 12 7805 4 B12 7508 7509 1 G6 7509 2 6 7509 3 7 7509 4 17 9506 4 9858 E4 FS03 B12 FS08 B7 503 C11 7509 4 1506 G11 7ALVCOOAPW 1207 E11 ISOR C2 ISOV C2 1512 B8 1513 B9 1519 03 IS1A IS1B D4 IS1D G5 IS1E H5 100n 220R 3V3 3V3 e a 220R 220R 3V3 ARC ES E 3819 10K 7509 3 74LVCODAPW 2931 IS1K 253M 1844 wa eHDMI gt 100 3S6M 100n H H SEL HDMI ARC gt Pa 3V3 3525 688 3V3 6 2009 12 07 18770 514 100118 eps 100118 ua 8204 000 8950 back to 2010 02 div table PNX Mips PNX Mips Circuit Diagrams and PWB Layouts BL LIPE 10 3V3 11 12 13 14
109. 5500 back to 2010 02 table Circuit Diagrams PWB Layouts Q552 1A LA ES LIN PNX Analog Video PNX Analog Video AVI CVBS 2887 22n r 1 gt 5 2579 22n 829 EU 257 _ AV1 B 2S7H AV1 G S c x 22n n g C 257M YPBPR1 SYNCIN1 10n 2871 22 gt o gt 257 AV3 PR EU YPBPR1 227 r lt gt 8 7800 1 PNX85500 s A T E AB15 lt 5 AC13 8 lt o AD13 AE13 AV2 CVBS 2586 AF15 A AE15 ean AC15 l aSr AD15 QOS E AB14 AF14 2570 YPBPR2 SYNCIN2 gt AE14 a 14 AD14 AF16 AD16 AE16 AV4 Y 2578 18 7 AC18 EU 5 2 22n AD24 AP 2 6 0 AD25 F CVBS AV4 PR gt 2570 22 coe LE 2S7E AV4 PB 8 A 22 o G 52 9 e 2584 R VGA g g 22n gt 9 2885 gt 22 H a 2586 B VGA u s 22n 4 EU o gt 8 AP VGA S5T 1 ale H SYNC VGA gt 1 9857 1 100R V SYNC VGA 33957 36 1008 VGA SCL EDID Sg 9953 6 1008 VGA SDA EDID 1 3857 1 8 1008 VGA SCL EDID TCON lt 9S14 VGA SDA
110. 6 DFES E6 DFF1 E6 DFF2 F6 C12 IF17 D4 IF18 D4 IF27 E7 IF28 E7 IF29 F4 IF48 C12 IF49 F4 IF63 A4 IF64 A5 IF65 B4 IF66 B5 IF67 B4 IF68 B5 IF69 C6 2009 10 22 18770 510 100118 eps 100118 Circuit Diagrams PWB Layouts Q552 1A LA ES 10 10 BO2 820400089506 PNX85500 PNX NandFlash Conditional Access B02 A PNX NandFlash Conditional Access 1 2 3 7500 5 PNX85500 NAND ALE gt D22 NAND CLE gt C21 XIO A00 lt J25 XIO A01 lt J26 XIO A02 lt H21 XIO A03 lt H22 XIO A04 lt H23 XIO A05 lt H24 XIO A06 lt H25 XIO A07 lt H26 XIO A08 lt G21 XIO A09 lt G22 XIO A10 lt G23 XIO A11 lt G24 12 lt G25 XIO A13 lt G26 XIO A14 lt F22 XIO A15 4 1525 5 F23 7500 11 85500 CA MDIO 3801 1 8 P21 0 CA MDI1 lt 33R 3501 2 2 P22 CA MDI2 lt 3501 3 6 3338 P23 CA MDI3 lt 33R 5 3S02 4 4 P24 7 39022 2 25 5 CA MDI5 8 3902 11 26 5 CA MDI6 lt 6 3 33R 21 x CA MDI7 lt 3S02 3 33R 5 3S01 44 N22 5 33R CA ADDENn lt J22 CA DATADIR lt K25 CA DATAENn lt K26 3S03 CA MICLK lt N23 108 CA MOCLK 125 3504 2 CA MISTRT 7 2 Ms 3504 1 33R CA MIVAL 8 1 N25 33R CA MOSTRT gt 122 CA MOVAL gt L23 J21 CA RDY gt L24 CA RST lt L26 J23 J24 4 VIDEO_STREAM
111. 6 IE75 B7 IE76 C6 IE77 C7 w 12V E22 10p 0 2 1 43 CDS4C12GTA 1E44 CDS4C12GTA 12V RES 6E46 RES 6E40 0 2E67 1E28 RES 6E51 LP 4 CDS4C12GTA 12V MTJ 032 21B 41 NI FE 9E58 76 3 90 1 77 1 04 2 1 FE42 a w 0 2 68 1E39 RES 6E52 CDS4C12GTA 12V YKC21 5598 1E08 3 6 FE50 5 exe RED S e FE43 e a A o 4 1229 2bE39 gt RES CDS4C12GTA 12V 00 7 a a gt w 4 lt 1E42 CDS4C12GTA 12V 00 2E71 RES 6E38 MSJ 035 10A o H 2E36 1n0 1 37 gt 4 i CDS4C12GTA 12V E 0 a a a w 1KO 2E37 110 1 8 4 NOM TR CDS4C12GTA 12V jj 00 4 1E75 RES 6E15 CDS4C12GTA 12V lt 1E76 RES 6E16 CDS4C12GTA 12V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2009 10 22 8204 000 8952 jJ 18770 529 100118 eps 100118 ANALOG E 2010 02 div table Circui
112. 6 eps 100126 Figure 7 13 Communication protocol outside LED board Refer to figure for an overview of the communication inside the LED board Extra 18770 213 100126 eps 100219 Figure 7 14 Communication protocol inside LED board The buffer is built around item no 7820 diagram AL1A and regenerates the clock signals Refer to figure 7 15 Ambilight buffer 2010 Apr 02 18770 214 100126 eps 100126 Figure 7 15 Ambilight buffer The temperature sensor is built around item no 7B30 diagram and indicates overtemperature of the board Refer to figure 7 16 Temperature sensor 100K RES 3V3 10K RES 18770 215 100126 eps 100126 Figure 7 16 Temperature sensor EEPROM item 7807 diagram contains alignment information about the mounted LEDs and is programmed during the alignment process in production Refer to figure 7 17 EEPROM 18770 216 100126 eps 100126 Figure 7 17 EEPROM The LED driver is built around item no 7826 diagram AL1A and controls the LEDs Refer to figure 7 18 LED driver Circuit Descriptions Q552 1A LA EN 45 7B26 1 TLC5946RHB BLANK PWM CLOCK BUF Sp 4 3800 4 5 NSPECLOGKBUE 7 VV Viso LOCK BUF 150H SPI DATA IN 3 6 PI DATA OUT 3B00 3 1508 _ _ 3B21 1508 LATCH 2 3 00 2 7 FB20 3V3 150R PWM B4 18 PWM B 7 DATA SWITCH 3B31 18770 217 100126 eps 100126 Figure 7 18 LED driver The Overvoltage Protection
113. 7 p 2B25F4 3810 3 G12 DDR2 DQM2 gt 3B23 B3 DDR2 WE S F3 gt 33R DDR2 DQM 3B24 B3 2B26 F6 3B1 0 4 G1 2 dh 2B27 F8 3B11 1 G12 2B28 F8 3B11 2 G13 2B29 F9 3B11 3 G12 L 2B30 F9 3B11 4 G13 2831 F9 3B12 C7 2B32 F9 3B13 C6 2B33 F9 3B14 C13 DDR2 VREF DDR M 2B34 F10 3B15 C12 2B35 F11 3B16 H7 DDR2 VREF DDR 2B36 A6 3B17 H7 4 9 9 2B37 A11 3818 H13 gl SERS 2838 F6 3819 12 FT E 5855 2B39 F11 3B20 H1 2B40 A2 3B21 11 D ow x 2841 B8 3B22 B1 EDE1108AGBG 1J F 2 2842 F2 3B23 D3 Pies lt s 2843 F8 3824 09 2 A1 H3 DDR2 A0 H8 DDZ Az H7 E 0 C8 42 572 lt DDR2 D0 DDR2 A1 H3 em 238102 2844 C6 3B25 I3 DDR2 A3 J2 C23B08 4 4 5 33R DDR2 D1 DDR2 A2 H7 DDR2 D8 G DDR2 A4 98 D7 33R 3 6 3807 3 DDR2 D3 DDR2 A3 2 42 5 11 3 3 6 33R 5 DDR2 D9 G 2B45 C1 2 3B26 I9 DDR2 A5 5 J3 5 3 D3 3B08 2 2 7 335 2 0082 02 DDR2 A4 s J8 4 2 10 3 EE AG 33R 5 DDR2 D10 DDR2 A6 J7 01 33R 1 E lt DDR2 D4 7 N DDR2 A5 S 5 3 03 2 PH DDR2 D11 2846 H6 3B27 C1 K2 D9 4 4 5 E DDR2 D12 DDR2 AS 33R 3 AA6 85083 DDR2 D6 008247 s 0998104 4 5 3811 1 388 2 DDR2 D1 2847 3828 C1 0082 49 K3 B9 3B07 1 1 8 33R 2 07 0082 48 5 K8 8 6 B1 33R 4 5 sen DDR2 D14 B H2 33R K3 B93B10 1 1 8 33R T DREAM K7 gt 7
114. 7 4 2 2EA5 IE68 8 z 1E53 C4 9 1 H6 1 92 G7 AUDIO IN1 R x ps 3E074 js Rb 4 ae 1E54 04 9 2 113 IE93H7 318 ale 1E55 E4 3EB9 3113 1 94 H6 B lt 7 01 2 3 e gt a mr A a B 1E56 E11 9 4 16 IE96 G6 S S gt N gle 5 8 FEC8 1E57 E11 5E73 D2 IECO A7 8 554 08 B 8 1EP2 F13 5E74 E2 IEC1 A6 27 3V3 5 2 01 5 76 2 1 2 B7 5 FE62 PUMH7 L 3E63 4 2 2 04 D3 5E77 D10 L loc 100R 2 06 5E78 E10 2E10 C3 5E79 F10 AP SCART OUT L A AA e 3 8 31 5 8 927 2E12 F4 SE80 E8 1 100R 8 3E24 a a 2E13 G11 6 01 5 2 14 F4 6 02 11 ele 8 818 i RN 2E15 04 6E03 B3 C u8 58 ETE SCART2 C 2E16 D12 6E07 C3 e a 8 lt 2E17 E12 6E08 B11 4 ko 5 AV2 2E18 E4 6E09 D3 iE T EU 5 1E02 2E19 F12 6E10 A11 AUDIO IN1 L lt gt 5 8 L XA 58 Y 8 8 2E24 G2 6E12 C11 1 8 o d 2E29 A10 6E14 C11 45V 3E80 188 2E30 B10 6E22 E3 s YPBPR1 PB 9E51 5 8 8 8 8 T c PB ig aTe WM NT Lee GENE 2E32 C10 6E24 D11 EN o 8 avers FSS 2E33 E12 6E26 F3 z oe 18 2 41 H12 6 28
115. 7 C8 2 27 0082 016 0082 41 H3 3928 _ DDR2 CLK DDR2 A3 J2 23802 4 4 a SR S DDR2 D17 NDDR2 A2 2 0 G3 3 5 EA m DDR2 D24 2B14 B9 3B07 1 G6 J8 D7 3 6 3B00 3 DDR2 D18 DDR2 A3 DDR2 D25 2 acp s 233802 2 2 7 222 DDR2 D19 N DDR2 A4 gt s p wa DDR2 D26 2B15 B9 3B07 2 G7 7 01 33R 1 3802 1 DDR2 D20 DDR2 A5 J3 0082 027 2 DDR2 CLK DEED K2 B D93B00 4 4 5 33R DDR2 D21 DDR2 A6 7 a Bod d 1 83805 15 0082 028 2B1 6 B1 0 3807 3 G7 DDR2 A8 K8 B1 3 6 3B02 3 DDR2 D22 DDR2 A7 K2 DDR2 D29 MOR gt Ks 8 S 380011 8 20 DDR2 D23 DDR2 A8 4 5 Bt 5 980546 DDR2 D30 2B17 A11 3B07 4 G6 DDR2 A10 H2 33R DDR2 A9 DDR2 D31 pe DDR2 CLK P DDR2 A11 2 K Es s DDR2 A10 33R 281 8 22 3808 1 G7 0082 0052 DDR2 A11 C DDRACLK N DDB2A13 L8 1 3813 33R 125 0082 0052 4 12 12 87 3814 0082 0083 P 2819 3B08 2 m ma 33R DDR2 A13 18 A8 EE N 33R 45 DDR2 DQS3 N 2B20 F3 3B08 3 G7 DDR2 BA1 2 G3 A2 DDR2 BA0 Se G2 2p2 DDR2 BA2 G1 DDR2 BA1 E 2 2821 3808 4 G6 DDR2 ODT lt DDR2 BA2 G1 RES F9 DDR2 CLK P y m 2408 E8 HORE gt 3B03 RES F9 2B22 F3 3B09 H9 En DDRA CLK P gt 2408 2B29 F3 3B10 1 G12 E G8 DDR2 CKE F2 DORLRAS 2 009209 2824 F4 3B10 2 G13 Fa 6
116. 770 670 100212 eps 100219 Circuit Diagrams PWB Layouts Q552 1A LA EM Everlight LED Common 2 AL1 B Everlight 15 LED Common 2 1 R 1 2 4 5 6 8 9 10 11 12 2 50 11 3850 7 3B51 B7 3B52 B7 3B53 1 B7 3B53 2 C7 3B53 3 C7 3853 4 C7 7105 7104 7103 7102 7101 7100 3B55 1 C3 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D 99 235 RSBB7C A24 2D lt gt 5 3855 4 4 NC BC847BS COL 6 A 2 3385536 10K 4 FB70 PWM B2 y e B 2 u 5 3855 2 1 BC847BS COL 3 1 2 Y 1 3B55 3 mac 3B55 4 42 Pow r 3857 2 03 T 3B57 3 C3 UT E uh 3 00 1 G3 Re 1 3 00 2 F3 1K5 3 00 3 F3 3 00 4 3C06 1 G3 3 06 2 3C10 4 3C11 F4 3C12 F4 3C15 1 G4 3C15 2 G4 3C15 3 G4 u E _ 3C15 4G4 mls 7100 B11 7101 B10 7102 B9 7103 B7 7B51 BC847BW 3 3 3B57 3 6 10K 1 1 7 3857 2 5 10K FB72 PWM R2 lt e 5 3C00 4 4 10K 2 3C00 3 6 10K FC01 PWM B3 lt 1 3C10 2 Y e 9 Z3S RSBB7C A24 2D 09 295 RSBB7C A24 2D 9 ZXS RSBB7C A24 2D 71 04 B6 7105 5 5 270R 7200 8 9 BC847BS COL 3 3C12 n 688 7201 F9 5 1 3 15 1 8 TM 7202 F1
117. 7BS COL i LEFT SPEAKER GND AUDIO AVCC 3D15 1 3D15 2 1 8 7 2 IDI3 9 3 4K7 4K7 GND AUDIO ID39 5 GND AUDIO 1D50 4 V NOM E 7D13 2 BC847BS COL A BZX384 C lt MAINS OK 2K2 3D04 5D03 GND AUDIO 220R _ L GND AUDIO GND AUDIO 8 5 GND AUDIO GND AUDIO 3 7003 2 BC847BS COL 1 35 6 DO LEFT SPEAKE Ss 3D06 3D06 2 735446 4 400K 5 RIGHT SPEAKER 1D52 4 V NOM RIGHT SPEAKER 2009 10 22 18770 520 100118 eps 100218 8204 000 8951 E back to 2010 Apr 02 div table DC DC B03B DC DC Circuit Diagrams and PWB Layouts Q552 1A LA 10 AD BOSB 1024 ES 1025 F4 2009 10 22 18770 521 100118 eps 2000 D2 2004 F4 2008 G9 2012 F11 2016 10 2020 14 2024 B5 3001 F1 3005 4 301186 3019 G9 3U23 1 C9 3U24 1 F9 3U27 D5 5002 B13 7001 08 7104 8 FUO2 B9 FU06 E8 1004 G3 1008 D4 1012 07 1016 E5 1020 G9 2001 2005 F4 2009 9 2013 F12 2017 9 2121 C6 2025 B12 3002 2 3108 G2 3014 07 30
118. CA WAITn lt 11 9 s XIO D10 2009 10 22 1 2 3 4 5 6 7 8 9 10 11 TUNES PDMS L 8204 000 8994 18770 500 100118 5 100218 E back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 Flash B01B B01B 2F20 A3 3F20 1 B1 3F20 4 C2 3F21 3 C1 3F22 2 C1 3F23 C2 IF21 C3 2F21 A3 3F20 2 B2 3F21 1 C1 3F21 4 C2 3F22 3 C2 3F24 D2 IF22 D3 3F19 D2 3F20 3 B1 3F21 2 C2 3F22 1 C2 3F22 4 C2 7F20 B3 IF23 D3 A 3 3 c CN N LL LL N 7F20 NANDO4GW3B2DN6F G pc 1 VCC B FLASH 3 4Gx16 4 5 XIO D0O Ss 3F20 1 1 8 100R 29 6 XIO D01 s 3F20 2 2 7 100R 30 10 XIO D02 3F20 3 3 6 100R 31 B 11 XIO D03 gt 3 20 4 4 5 1008 32 14 XIO D04 3F21 1 1 8 100R 41 4 15 XIO D05 x 3F21 2 2 7 1008 42 20 XIO D06 3F21 3 3 6 1008 43 E 21 XIO D07 21 4 4 5 1008 44 5 22 23 IF21 a C NAND CE1n 25 C NAND CLE 3F22 2 2 7 100R 16 27 3F22 3 3 6 100R 17 28 3V3 23 10 9 33 gt 3F22 1 1 8 100R 8 34 XIO WEn 3 22 4 4 5 1008 18 35 NAND WPn a IF22 19 38 313 24 7 39 2 2 40 NAND RDY1n 45 IF23 46 47 3F19 10K 43V3 gt 2009 10 22 8204 000 8994 y ____ l 18770_501_100118 eps 100118 TUNER HDMI amp CI E
119. Colour Television Chassis 552 1 Service LA Service Service 8990_000_100330 eps 100330 rvice Manua Contents Page Contents Page 1 Revision List 2 2 Technical Specifications Diversity and Connections2 3 Precautions Notes and Abbreviation List 5 4 Mechanical Instructions 9 5 Service Modes Error Codes and Fault Finding 12 6 Alignments 30 7 Circuit Descriptions 36 8 IC Data Sheets 48 9 Block Diagrams Wiring diagram Matisse 42 46 59 Block Diagram Video 60 Block Diagram Audio 61 Block Diagram Control amp Clock Signals 62 Block Diagram 2 63 Supply Lines Overview 64 10 Circuit Diagrams and PWB Layouts Drawing PWB AL1 820400089786 AmbiLight Common 65 71 AL1 820400089691 9 LED LiteOn 67 71 AL1 820400089703 15 LED LiteOn 69 71 AL1 820400090592 AmbiLight Common 72 AL1 820400090601 9 LED Everlight 74 AL1 820400090621 15 LED Everlight 16 01 820400089943 Tuner HDMI ZH 118 90 99 10 B02 820400089506 PNX85500 B03 820400089514 CLASS D B04 820400089524 Analog I O 107 118 B05 820400089535 DDR 112 118 B06 820400089572 LVDS Non DVBS 113 118 B09 820400089812 Non DVBS Con 117 118 11 Styling Sheets Matisse 32 46 120 Copyright 2010 Koninklijke Philips Electronics N V All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying or otherwise without t
120. D procedure when SDM is switched on service modes CSM SAM and SDM are accessible during this failure observed in the Uart logging as follows lt lt ERRO gt gt gt C First Error 1919 Layer 1 2 Layer 35 Error 36 Tuner DVB S When there is communication towards the DVB S tuner during start up LAYER 2 error 36 will be logged and displayed via the blinking LED procedure when SDM is switched Error 42 Temp sensor Only applicable for TV sets equipped with temperature devices Error 53 This error will indicate that the PNX8550 has 5 7 read his bootscript when this would have failed error 15 would blink but initialization was never completed because 5 7 1 of hardware problems NAND flash or software initialization problems Possible cause could be that there is no valid software loaded try to upgrade to the latest main software version Note that it can take a few minutes before the TV starts blinking LAYER 1 error 2 or in SDM LAYER 2 error 53 Error 64 Only applicable for TV sets with an controlled Screen 5 6 The Blinking LED Procedure 5 6 1 Introduction The blinking LED procedure can be split up into two situations Blinking LED procedure LAYER 1 error In this case the error is automatically blinked when the TV is put in CSM This will be only one digit error namely the one that is referring to the defective board see table
121. D9 C2 2UEO C3 2UE1 D5 2UE2 D6 2UES3 06 20 4 06 2UE5 E4 2UE6 RES 3UO06 2UE7 F4 EN 208 F5 2UE9 3006 B8 C 3107 D8 3UDO B5 3UD1 B5 3002 B6 1V1 3UD3 D5 5 3004 05 3005 05 7005 2 5 1028 5000 A2 E 7UD1 1 Q Q ST1S10PH 10u ENABLE 3V3 5V gt D3 196 100K 2UE2 22u 20 22u 2UEA 7 220 16 3 BC847BS COL RES 2028 1 5001 5 5002 C5 5003 C2 6000 6001 E4 7005 1 B7 7005 2 D7 7000 1 4 7000 2 B4 7UD1 1 C4 7UD1 2 D4 7UD2 E5 IUD2 10K 3UD4 1M0 3UD5 33K 1 RES 3U07 7UD2 LD1117DT25 gt 2V5 E 5V p gt n 3 our FOR 5000 SERIES ONLY N NOT FOR 5000 SERIES E E FUD3 A7 1027 B8 028 08 IUDO A2 F IUD1 C2 IUD2 05 IUD3 A5 IUD4 C5 IUD5 E4 IUD6 B6 1007 A5 DC DC 8204 000 8951 L jm 18770 524 100118 eps 100118 3 313 Ee 22u 16V 1 7UD3 LD1117DT33 1 E 2010 02 div table Circuit Diagrams PWB Layouts Q552 1A LA EM 104 Temp Sensor AmbiLight Temp Sensor AmbiLight 1 2 3 4 5 6 1UMO A4 5UMO A3 5UM1 FUMO A5 A IUMO A4 3v3p 2 2 ida V AMBI A
122. DIMMING DIMMING TO SENSOR SENSOR RES See SDA BL 9810 2 1 al Only for SHARP display with on SSB E E back to 2010 Apr 02 div table ES Programmable via USB Programmable via ComPair SW Pre programmed device 18990_405_100331 eps 100331 9 6 Supply Lines Overview SUPPLY LINES OVERVIEW Block Diagrams Q552 1A LA 9 LIN 1M99 412VD 8019 12V GND1 gt lij PSU ci LAMP ON PE 162 BACKLIGHT PWM_BL VS Boost 5 BACKLIGHT BOOST B03e RE 3 BACKLIGHT PWM ANA DISP 26 BOK I POWER OK 5026 pm 00 fab N C et Optional 1M99 is 12 pin connector e 7 j LUN cT B03e 1 95 195 3V3 STANDBY B01e B02e 3V3_ST STANDBY p STANDBY h GND1 2 B11d B14f GND1 y GND1 gt lt 12V B03b d e g 12V 2 P BO8b B09a 12V 0 0 B11d B14f gt 12V 24V AUDIO POWER VSND z gt 5 GND_SND gt lt NC MAINS OK 0 sva 3V3 P 5V 45V B03e gt E 21 B03e COMMON 11114 3 3 43V3 B03e
123. DRAM B02B PNX SDRAM Bo2B 1 2 3 4 5 6 7 8 9 10 11 2512 DA 2517 E7 2520 7 2524 E7 2525 7 A 3506 D3 3507 03 3S0V F8 3520 02 3522 02 3530 7 7500 8 85500 3533 C8 DDR2 BAO lt H1 0 0 gt DDR2 A0 DDR2 BA1 H2 DDR2 A1 1 1 DDR2 BA2 G1 S DDR2 A2 lt i S DDR2 A3 DDR2 DQM0 lt D1 0 4 s DDR2 A4 3S6Q E1 0 DDR2 DQM1 05 1 5 DDR2 A5 DDR2 DQM2 lt R3 2 6 S DDR2 A6 7S00 8 B6 DDR2 DQM3 T5 sS DDR2 A7 lt 4 s DDR2 A8 DDR2 D0 gt F3 s DDR2 A9 FS01 D3 C DDR2 D1 C2 gt DDR2 A10 C 41V8 DDR2 D3 22 2 Se DDR2 A11 DDR2 D2 DDR2 A12 FS02 D2 DDR2 D6 B4 4 DDR2 A13 DDR2 D5 F1 DDR2 A14 poreo 4 542 8 E1 DDR2 CLK N 2 gd 2 i 2 DDR2 CLK P 5 a 5 DDR2 D8 Se F4 108 3533 2 CLK_ 9 T 2 T me DDR2 D9 i B2 10R gt 8 5286 a 0082 010 E5 m 0082 0080 DDR2 D11 C5 DDR2 DQSO P DDR2 VREF CTRL3 ae 501 DDR2 D12 E DDR2 VREF CTRL2 lt q e DDR2 D13 Ss G5 DDR2 DQS1_N 5 DDR2 D14 B3 S DDR2 DQS1_P D SS DDR2 D15 F5 D 9 9 29 DDR2 D16 gt DDR2 DQS2_N 0082 017 S P2 lt 0082 0082 gt 0082 019 U2
124. Diagrams PWB Layouts Q552 1A LA 10 LUE 9 LED Everlight AL2B 9 LED Everlight 1 2 3 4 5 6 y 8 9 24V T 7D01 1 e 855 BC847BS GOL 2 i e V lt q 24 24 7300 7301 7302 7303 7304 7305 270R 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D 99 135 RSGBB7C A24 2D 1 2 7001 2 2 6 270R BC847BS COL 5 3012 4 5 3 4 te 4 4 s gt e 3D13 1 1 8 1K5 PWM R4 2 3D13 2 5 24V 1K5 3 3D13 3 6 1K C ocx 7D02 lt BC847BW 3 4 3013 4 5 e 1K5 5 8 N T 0x e te 4 FDO3 PWM G4 e 5 D FD04 e E 2010 02 div table 2D10 C13 3002 1 A1 3002 2 A1 3D02 3 B1 3002 4 B1 3D05 3 C1 3005 4 C1 3D10 A12 3D11 B12 3D12 B12 3D13 1 B12 3D13 2 C12 3D13 3 C12 3D13 4 C12 7300 B5 7301 B6 7302 B7 303 B8 7304 B10 7305 B11 7001 1 7001 2 7002 C2 FDO1 A1 FDO2 C1 03 D1 FDO4 D1 DEM 9 LED Everlight 8204 000 9060 AL 2K10 3104 313 64191 i L 18770_641_100212 eps 100212 Circuit Diagrams PWB Layouts Q552 1A LA EM LUE 10 7 AL1 820400090621 15 LED Everlight 15 LED Everlight AL2A 15 LED Everlight AL2A 1 2 3 4 9 6 7 8 9 10 1M84 A10 2001 B6 7203 A3
125. EDID e RT control control e Sync detection e TMDS output control CEC control back to div table 7 6 EDID stored in Sil9x87 therefore there are no EDID pins on the SSB Video and Audio Processing PNX85500 The PNX85500 is the main audio and video processor or System on Chip for this platform It has the following features e Multi standard digital video decoder MPEG 2 H 264 4 e Integrated DVB T DVB C channel decoder e Integrated CI Integrated motion accurate picture processing MAPP2 High definition ME MC 2D LED backlight dimming option e Embedded HDMI HDCP keys e Extended colour gamut and colour booster e Integrated USB2 0 host controller Improved MPEG artefact reduction compared with PNX8543 e Security for customers own code settings secure flash The TV550 combines front end video processing functions such as DVB T channel decoding MPEG 2 H 264 decode analogue video decode and HDMI reception with advanced back end video picture improvements It also includes next generation Motion Accurate Picture Processing MAPP2 The 2 technology provides state of the art motion artifact reduction with movie judder cancellation motion sharpness and vivid colour management High flat panel screen resolutions and refresh rates are supported with formats including 1366 x 768 100Hz 120Hz and 1920 x 1080 100Hz 120Hz The combination of Ethernet Cl a
126. EDID ICON 9815 TCON ONLY CVBS Y1 CVBS R C3 AV1 CVBS Y7 C7 CVBS1 OUT CVBS2 OUT RESREF VGA IN Gur VSYNC SCL EDID TUNER 2010 02 back to div table 2S8A 14 Y SVHS 22n 2522 478 C SVHS 22 3505 CVBS MON OUT1 3S5E 560R 3508 5608 3509 8K2 els E N N N N N NTR 3575 PNX IF AGC 47K 3576 PNX RF AGC 47K 10 EIS PNX IF N 10 N N bL sb s Gos gos 059059 o59 o gt N Ut N 2514012 2515 012 2516 012 2518 012 2519 012 2522 11 2540 B11 2575 F11 2576 F11 2577 F12 2578 G12 2S7E G6 2S7H 2 7 257 B6 25171 2 7 C6 2S7N D6 257 D6 2570 2578 F6 2570 F6 2584 G6 2585 H6 2586 H6 2587 288A A11 2586 3505 11 3508 B11 3509 C11 3546 G6 354 354 3541 B6 5 06 354 D6 3S4T D6 3540 F6 3S4W F6 3550 H6 3552 H6 3554 16 3559 355 11 3S5E B11 3551 3555 9 3S5T 1 15 3S5T 2 111 3S5T 3 3S5T 4 111 355 1 5 355 2 112 355 3 15 355 4 112 3575 12 3576 F12 7900 1 08 9514 9515 9517 A13 BS09 F9
127. Es EE 7F52 ver M25P05 AVMN6P LIGHT SENSOR AE26 _ Z PNX SPI CLK PNX SPI WPn RC SPI 3V3 STANDBY 019 spiten AF23 PNX SPI CSBn 1025 ENIMS 7 PNX SPI SDO TO IR LED BOARD AND 7U43 1 PNX SPI SDI KEYBOARD CONTROL 59 9S ANDPY WES L RXD UP 26 RESET STBYn PNx85500 STANDBY CONTROLLER BN i DETECT2 7820 RESET SYSTEM NCP303LSN28G 1 3 E RESET STBYn AV1 STATUS ee LCD PWR ON ENABLE 3V3 5V 3V3 STANDBY ENABLE 1V8 TO PIN ENABLE 3V3n ipog 13 PCEC HDMI CEC HDMI SEL HDMI ARC 1M99 SII9187ACNU LAMP ON BACKLIGHT our m ARX HOTPLUG RESET ETHERNETn BACKLIGHT BOOST 5 BRX HOTPLUG POWER OK SUPPLY 4 1P02 19 CONNECTOR 1p05 19 5 POWER i 6000 Serie mux SIL9187 non Instaport SUPPLY 8000 Serie mux SIL9287 Instaport 18990 404 100331 eps mee Z Z s e T a p r 100331 p back to 2010 02 rele Block Diagrams Q552 1A LA 9 LIN 9 5 Block Diagr
128. FU50 C1 1044 2054 2 FU51 C1 3U41 2055 F3 FU52 C3 optionally 1 99 is a 9 pin connector 10K RES 2U68 E1 FU53 C2 e 2U71 D5 FU54 C2 BC847BW 2072 D1 FU55 C1 2041 RES IAT 3070 LED1 3U41 B5 FU56 D1 d BC847BW 304203 FU57D1 00 3043 FU58 E1 120 3044 59 E1 T 3U45 C3 FU60 E1 1956 ES 1 ae 3059 B6 FU63 1 C lt 3U60 1 F5 FU64F1 FU52 g 1064 FUSS 3042 lt lt BACKLIGHT PWM BL VS 3060 2 F4 FU65F1 e 3064 100R lt BACKLIGHT BOOST 7048 1 i FUN __BACKLIGHT PWM ANA DISP 43083 45 85785 01 EE E oof 100K 3062 1 F4 FU72 ipa iD 2 5 c 1041 577 858 Yas P 3U62 2E3 FU73E5 e 3 9 E 33 10K is S 3U62 3 E4 2074 01 1 1085 E 3062 4 1040 E5 5 a gt POWER OK D 3U63 F5 1041 05 d 3U66 ee 3U64 C2 1043 B5 RES 1008 3067 3065 02 1144 FU57 BL SPI CSn 3V3 STANDBY 3U66 D2 1045 4 or 100R REg BL SPI CLK 3067 02 1047 B4 1008 RES 3U71 2 3068 B3 1048 4 2068 100R BC857BS COL 9920 1049 3070 B4 1050 F4 10 15 BC847BPN COL 3071 03 IU51 s aa 4 or af 3U72F3 1052 5 ux ion z 3U73 F3 1055 D3 40 3 3074 A4 1156 5 x 3 6 e 772 ENABLE 1V8 3U75 A4 1057 F6 3 A S 847 E SEN s lt 3076
129. G17 3 3 SPI CLOCK Se 100R 7001 LTW 008RGB 7002 LTW 008RGB SPI CLOCK BYF 10 3V3 7003 LTW 008RGB 11 12 3V3 3B39 2 FB40 1K5 1 3B39 3 3V3 1K5 196 13 14 3B34 100K RES D 3V3 Y 7B30 3B11 10n 3004 10K RES 2B09 FB41 7005 LTW 008RGB 1K5 196 0 4 LMV331IDCK 3835 2708 3836 2708 4 gt 3837 68R 4 AR 3 3B13 3 6 10K 5 3813 4 4 10K FB32 PWM G1 7B25 BC847BW 3 001 002 007 2010 02 back to div table 10 11 12 13 1 3B03 1 1K5 2 3803 2 gt 1K5 3803 3 6 1K5 4 3B03 4 5 1K5 AL 2K10 LiteOn 15 LED Common 1M83 C1 2800 E8 2B01 F8 2802 E9 2803 114 2804 1 7 2B04 2 B6 2B04 3 B8 2B04 4 B7 2808 E12 2809 E12 2B10 F9 2B11 A9 2B17 D8 2B20 D4 3004 E12 3B00 1 3B00 2 B6 3800 3 B6 3B00 4 B6 3B01 1 E7 3B01 2 D7 3B02 1 3B02 2 E5 3803 1 H14 3B03 2 H14 3803 3 H14 3803 4 H14 3B07 1 F3 3807 2 G3 3B07 3 H3 3B07 4 G3 3B11 E12 3B13 3 H3 3B13 4 3B18 A8 3B21 B7 3B22 B8 3B30 1 09 3B30 4 E9 3831 B10 3834 013 3B35 G14 3B36 G14 3B37 G14 3B39 1 E13 3B39 2 D12 3B39 3 D13 7000 G5 7001 G7 7002 G8 7003 G10 7004 G11 7005 G13 7B06 D3 7B07 D4 7B20 1 D8 7 20 2
130. IA RXC 1 02 OW CRX24 2 ____ HDMIA RX0 V25 CRX2 71 et HDMIA RXO V26 CRX14 69 HDMIA RX1 U25 CRX1 68 HDMIA RX1 U26 CRXO 66 HDMIA RX2 T25 CRXO 65 HDMIA RX2 T26 63 HDMI 1 CRXC 62 3S0W CONNECTOR 7800 PNX85507EB PNX85500 51171810 CLASS D VIDEO STREAM AUDIO LM324P 12 7805 gt STANDBY 7 PE ANALOG VIDEO 2145 CONROL R26 licet R25 USB DP FLASH FLASH 7F20 NANDO2GW3B2DN6F XIO D 00 07 NANDO4GW3B2DN6F 12 37 6000 Serie 256MB 8000 Serie 512MB 211421 MEMORY 7800 EDE1116AGBG EDE1108AGBG RXC B RXC B P RXO B B P RX1 BN RX1 BP RX2 BN RX2 BP A2 V1 DDR2 VREF CTRL2 DDR2 VREF CTRL3 E back to 2010 Apr 02 div table gt TPA6111A2DGN 5D07 2 24V AUDIO POWER 5D08 10 12 1735 LEFT SPEAKER ig RIGHT SPEAKER G n 108 ad SUBWOOFER ES N 2 TEMP SENSOR 1328 I OUT 3 5mm 6000 Serie 256MB s p lt lt a mO m sn Ot n n nnm Mr E
131. K _ RESET SYSTEMn RESET SYSTEMn gt UK AV2 BLK s AV1 BLK 3819 Kamon KEYBOARD 1 BERE LIGHT SENSOR lt lt AV1 STATUS gt JE AV2 STATUS 2 serpaoa A spl Pros x PNX SPI WPn 2 100 gt 0 IS3B o9 2813 2 907 9 310 N n DS50 2S4G m 10 A 5 7800 9 S lt is lt PNX85500 9 2S4F i 10p 3V3 STANDBY gt lt lt Y a 8 gt lt RESET STBYn IS3F 3S44 STANDBY lt EAT EA lt M ALE 10K 3543 lt ALE lt PSEN Z PSEN 1530 40k 3942 10K 3S2F 100R lt SDA UP MIPS sDA UP MIPS RES 3S6V 3526 1008 SCL UP MIPS SCL UP MIPS 4K7 3S6W 4 RES 3S2H 100R LED1 LED1 lt RES 3 1 4K7 3S2K 100R S LED2 LED2 lt 10K 3841 10K PNX SPI SDO lt PNX SPI SDI PNX SPI CLK S PNX SPI CSBn IS2V CTRL DISP 7 CTRL DISP lt RES 3S2L IS2Z RESET DVBS RESET DVBS lt 10K RES 3546 S RESET USBn RESET USBn Eee 10K Ro 3V3 STANDBY _ RESET ETHERNETn RESET ETHERNETn lt 10K RES 3547 S SEL HDMI ARC SEL HDMI ARC lt 3S2S 10 l s RESET AVPIP RESET AVPIP lt 10K RES 3S2M S RESET AUDIO RESET AUDIO 3S3W 10K RES s AUDIO MUTE UP AUDIO MUTE UP lt 4K7 3S49 ag 3V3 STANDBY 3V3 STANDBY gt 5 9 9 2807 7820 RESET STBYn NCP303LSN28 7 gt FS45 1 IS2U 1 a t amp m 2 8
132. ROM RSDS R TXT SAM S C SCART SCL SCL F SD SDA SDA F SDI SDRAM SECAM SIF SMPS SoC SOG SOPS SPI S PDIF SRAM SRP SSB SSC STB STBY SVGA 2010 Apr 02 Q552 1A LA 3 575612 MHz and PAL N 3 582056 MHz Printed Circuit Board same as PWB Pulse Code Modulation Plasma Display Panel Power Factor Corrector or Pre conditioner Picture In Picture Phase Locked Loop Used for e g FST tuning systems The customer can give directly the desired frequency Point Of Deployment a removable CAM module implementing the CA system for a host e g a TV set Power On Reset signal to reset the uP Power Supply for Direct view LED backlight with 2D dimming Power Supply with integrated LED drivers Power Supply with integrated LED drivers with added Scanning functionality Positive Temperature Coefficient non linear resistor Printed Wiring Board same as PCB Pulse Width Modulation Quasi Resonant Converter Quality Temporal Noise Reduction Quality Video Composition Processor Random Access Memory Red Green and Blue The primary color signals for TV By mixing levels of R G and B all colors Y C are reproduced Remote Control Signal protocol from the remote control receiver signal Read Only Memory Reduced Swing Differential Signalling data interface Hed TeleteXT Service Alignment Mode Short Circuit Syndicat des Constructeurs d Appareils Radior cepteurs et T l viseurs Se
133. S DVBS DATA IF27 IF28 43V3 BRA FLT We 40 lprMB B gt IF AGC 8 18K S INFO N 3FE6 10K 1 51 41 Jh 42 3FE7 10K IF29 e 7 6 _ 3FG2 lt RESET SYSTEMn E 11 5 10K 3FG22 10 SCL SSB lt 3FE8 100R 1 49 _ 45 12 3FG4 2 SDA SSB gt 9 100R 46 1 467 ac 24 43V3 BRA FLT T TIO CO N SE LO LO CO AGND AGND 2010 Apr 02 backto div table 10 3V v Y Y 5V Y Y Y 10 SFE7 11 12 13 30R 5FE9 7FE3 LD3985M25 30R 5FGO 30R 5FG2 AGND 30R 11 48 p gt 3V3 BRA p gt 2V5 BRA Es e 12 13 TUNER HDMI amp CI 8204 000 8994 1 0 C2 2FEO 2FE3 2 4 2FE5 A6 2FE6 B3 2FE8 2FF0 2FF1 A7 2FF2 B6 2FF3 B6 2FF4 B6 2FF5 B6 2FF6 B7 2FF7 C6 2FF8 C6 2FF9 C7 2FG0 C6 2FG1 C7 2FG2 C1 2FG3 C2 2FG4 03 2FG6 D3 2FG7 E3 2FG8 2769 2FH2 011 2 012 2FH4 012 2FH5 06 2FH6 2FH7 E7 E7 3FE6 F3 3FE7 F3 3FE9 3FG2 1 F6 3FG2 2 F7 3FG4 1 F7 3FG4 2 F6 3FG6 2 E7 3FG6 3 E7 3FG6 4 D7 3FG7 E7 5FEO A3 5FE3 5FE4 B7 5FE5 B3 5FE7 C11 C7 5FE9 C11 E11 5FG2 E11 7FEO D4 7FES C11 9F27 1 EB 9F27 2 D8 9F27 4 D8 9F28 E8 BFE1 E4 BFE2 E4 BFES E4 4 4 BFE5 4 DFE6 06 DFE7 06 DFE8 0
134. S Non DVBS 8204 000 8957 L To o O 18770_565_100125 eps 100218 E back to 2010 Apr 02 div table Circuit Diagrams PWB Layouts Q552 1A LA 10 8 Video Out LVDS Video Out LVDS 9 10 125005 FG1CD4 1051011 FG1D D4 1X05 G1 FG1E E4 2G24C10 FG1F E4 2025 C11 1 4 2G26 C11 1 4 2627 C11 FG1J E4 2028 11 1 4 2029 11 FGILE4 2075 10 FG1M E4 s 2076 C10 FG1N E4 2677 C10 FG1PF4 2678 C10 FG1QF4 g i 2G79C10 us T M 2G7AC10 FG1SF9 IRR 2692 C4 9 C 1221 sz gesl 2093 4 FGIUF9 2 888 L 209404 FG1VF9 T CPSP gt on o 2G95 D4 FG1W F9 AER MER 209604 FG1YD9 Ica MEN s eem 269704 FG1ZD9 s 2696 cmos 2098 D4 2220 09 D omens 0R T mrs y 209904 FG21D9 100 2096 pu I F 3G2W C8 FG22 E9 LA 2807 xis 3G2Y C8 FG23E9 gt NE e rio nie 302708 FG24E9 rion gt ELE 3G30 D9 FG25 E9 er pin 303108 626 E9
135. Set is still operating Yes Y Connect U SB stick to the set go to SAM and save the current TV settings via Upload to USB Start up the set Set behaviour this for visual feedback No picture displayed 1 Start up the TV set equiped with the Service SSB and enable the UART logging on the PC Y 2 The TV set will start up automatically in the download application if main TV software is not loaded Y 3 Plug the prepared USB stick into the TV set Follow the instructions in the UART log file press Right cursor key to enter the list Navigate to the autorun upg file in the UART logging printout via the cursor keys on the remote control When the correct file is selected press Ok Y 4 Press Down cursor and Ok to start flashing the main TV software Printouts like L 1 100 V 1 100 and P 1 100 should be visible now in the UART logging Y 5 Wait until the message Operation successful is logged in the UART log and remove all inserted media Restart the TV set Picture displayed Set is starting up with software v 1 Plug the USB stick into the TV set and select the autorun upg file in the displayed browser 2 Now the main software will be loaded automatically supported by a progress bar 3 Wait until the message Operation successful is displayed an
136. Sharp DirectLED board applicable to xxPFL76xx sets LGD side view edge LED with scanning PSLS power board not applicable to this chassis direct view LED with OD dimming PSL power board applicable to xxPFL56xx sets ASIC direct view LED with 2D dimming PSDL power board not applicable to this chassis Refer to section 7 2 2 Diversity for an in depth explanation of the different power boards that are used BacklightB oost PNX Jg BacklightP WM 85500 Z lamp ON 18770 242 100203 eps 100208 Figure 7 10 Backlight xxPFL54xx xxPFL56xx xxPFL76xx sets application 7 8 Ambilight In this chassis only 2 sided Ambilight is implemented Refer to figure 7 11 Ambilight architecture MTK or PNX85500 18770 209 100202 5 100202 Figure 7 11 Ambilight architecture For an overview of the LED grouping per board refer to figure 7 12 LED grouping per board back to 2010 Apr 02 div table GUE Q552 1A LA Circuit Descriptions 6 x 6 L E D 18770 210 100126 eps 100126 Figure 7 12 LED grouping per board The communication between PNX85500 Complex Programmable Logic Device CPLD and the Ambilight module uses the SPI protocol refer to figure 7 13 Communication protocol outside LED board Between the CPLD and the LED driver as extra line is mentioned e Non SPI signals that are required for the LED driver e Temperature sensor line 18770 211 10012
137. V TUN PIN p gt 10 m N 7275 e UPC3221GV E1 AF72 T 1275 2 74 173 2 75 F76 3F79 1 e 5 2 7 IF74 1 ral 10n 10n 220R IF16 x c 2F78 Ja 6 178 ur Q m S 2F79 35794 9 adus AF71 TUN IF N S IF81 10 1 o B FF74 FF76 e 9 TUN IF P 10n 220R AF73 6 Te B TUN P1 e FF00 7251 4 AGC CONTROL tO 2 9F04 IF AGC 36 17 a 0 E oN E i i ger FF75 u 3 E RE i i PNXCIF N IF82 3F77 TUN P6 e PNX IF AGC yg 3 80 F 2 2 63 IF13 FF01 E 10n S o 572 5v TUN PIN E 66 gt Se x TV 9 3F72 Lo s 220R 10n C gt N e m LO IF86 2F90 Us IF87 SCL TUNER 1 10 E 15 47R 3 5873 2 lt X gt TUN P6 TUN IF N Se 5 2 86 e 47 SSDA TUNER N TUN IF P i 1 6 C n d 15p 47R ATB2012 2F91 gt TUN P7 10n RES D IF89 D 9 s IF90 SELECT SAW 7F70 L PDTC114EU Ob HETS 9F71 E 5F72 E 5V TUN n 5V TUN PIN 30R RES 2 LN 1 2 3 4 5 6 7 8 9 10 2009 10 22 8204 000 8994 Pt ____ LS 18770_505_100118 eps 100118 TUNER HDMI amp Cl
138. V543 platform are New power architecture for LED backlight PSL PSLS PSDL e Boost signal is now PWM signal continuous variable The control signals are e Standby Lamp on off DIM PWM not for PSDL Boost PWM except for IPB e Power OK indicates that the main converter is functioning feedback signal to the SSB In this manual no detailed information is available because of design protection issues The output voltages to the chassis are e 3V3 STANDBY standby mode only 12V on mode e Vsnd 24V audio power e 24V bolt on power back to div table 7 2 2 e Output to the display in case of IPB High voltage to the LCD panel PSL and PSLS LED driver outputs PSDL high frequent AC current Diversity The diversity in power supply units is mainly determined by the diversity in displays Table 7 1 Supply diversity lists the different types of displays with its associated PSUs Table 7 1 Supply diversity 42PFL8605D 93 PLDF P975A 42PFL8605 98 LGIT PLDJ P977A 46PFL8605D 93 LGIT PLDF P975A The following displays can be distinguished e CCFL EEFL backlight power board is conventional IPB e LED backlight side view LED without scanning PSL power board side view LED with scanning PSLS power board direct view LED without 2D dimming PSL power board direct view LED with 2D dimming PSDL power board
139. am 2 PC contro Re rs 000 7500 85507 3 SCL PNX85500 CONTROL 1 SDA 7F52 SCL UP MIPS DEBUG ini ONLY SES PNX85500 STANDBY CONTROLER _ CONNECTOR3 6 PNX SPI CLK AF24 03 _ 3V3 STANDBY 3 PNX SPFWPn AE22 5 STANDBY 33 BRX DDC SDA 1 SST arza ne ___ gt 5 PNX SPI SDO 722 34 BRX DDC SCL 2 PNX SPI SDI AF25 a5 CIN 5V STANDBY ae RES RES CONNECTOR 2 Mc 1P02 _ NI 39 CRX DDC SDA MAIN NVM SW CRX DDC SCL FLASH 1F51 7F20 p CONNECTOR 1 NANDO2GW3B2DN6F E EE UC ds NAND04GW3B2DN6F USEONLV DRX DDC SDA HDMI L 4 DRX DDC SCL Y25 DDCA SDA Y26 DDCA SCL 222 XIO D 00 07 DDC_A_SCL 3V3 2 HDMI_DV 2117191 ETHERNET SERVICE 5V EDID 5V VGA pe 9 1E06 Y23 RXD1 MIPS 3 53 4 3 533 6000 Serie 256MB UART 47 VGA SDA EDID HDMI 8000 Serie 512MB Y24 SERVIC 9FC3 CONNECTOR 8 VGA SCL EDID HDMI nea anacogvinceo e o
140. ansition diagram back to div table 2010 Apr 02 16 EM Q552 1A LA service Modes Error Codes and Fault Finding 2010 Apr 02 Stand by or Protection Standby Supply starts running standby supply voltages become available st by resets Initialise I O pins of the st by pP Switch reset AVC LOW reset state Switch reset system LOW reset state Switch reset Ethernet LOW reset state If the protection state was left by short circuiting the SDM pins detection of a protection condition during startup will stall the startup Protection conditions in a playing set will be ignored The protection mode will Switch reset USB LOW reset state not be entered Switch reset DVBs LOW reset state keep Audio reset and Audio Mute Up HIGH Switch Audio Reset high start keyboard scanning RC detection Wake up reasons are It is low in the standby mode if the standby off mode lasted longer than 10s Switch ON Platform and display supply by switching LOW the Standby line 12V 24Vs AL and Bolt on power is switched on followed by the 1V2 DCDC converter Detect2 high received within 2 seconds Detect2 is moved to an interrupt To be checked if the detection on interrupt base is feasible or not or if we should stick to the standard 40ms interval 12V error No Layer 3 Layer2 16 Yes Enter protection Enable the DCDC converters ENABLE 3V3n LOW Enable
141. bled like Sleep timer Child parental lock Picture mute blue mute or black mute Automatic volume levelling AVL Skip blank of non favourite pre sets How to Activate SDM For this chassis there are two kinds of SDM an analogue SDM and a digital SDM Tuning will happen according Table 5 1 Analogue SDM use the standard RC transmitter and key in the code 062596 directly followed by the MENU or HOME button Note It is possible that together with the SDM the main menu will appear To switch it off push the MENU or HOME button again Digital SDM use the standard RC transmitter and key in the code 062593 directly followed by the MENU or HOME button Note It is possible that together with the SDM the main menu will appear To switch it off push the MENU or HOME button again Analogue SDM can also be activated by grounding for a moment the solder path on the SSB with the indication SDM see figure Service mode Z j 77 v 5 18770 249 100215 5 100215 Figure 5 1 Service mode pad After activating this mode SDM will appear in the upper right corner of the screen when a picture is available How to Navigate When the MENU or HOME button is pressed on the RC transmitter the TV set will toggle between the SDM and the normal user menu Ho
142. cord record selection that follows main picture and sound 1280 x 768 15 9 Quartz crystal 1024 x 768 4 3 Luminance signal Luminance Y and Chrominance C signal Component video Luminance and scaled color difference signals B Y and R Y Component video Mechanical Instructions Da 4 Mechanical Instructions Index of this chapter 4 1 Cable Dressing Matisse styling 4 2 Service Positions 4 3 Assy Panel Removal Matisse Styling 4 4 Set Re assembly 41 Cable Dressing Matisse styling Notes e Figures below can deviate slightly from the actual situation Note pictures are taken from the European equivalent with due to the different set executions SCART connector 18990_100_100401 eps 100401 Figure 4 1 Cable dressing 42 8000 series back to _ _ div table 2010 Apr 02 Da Q552 1A LA Mechanical Instructions 18990 101 100401 eps 100401 Figure 4 2 Cable dressing 46 8000 series back to 2010 Apr 02 div table 4 2 4 3 4 4 Mechanical Instructions Q552 1A LA D LUN Service Positions For easy servicing of a TV set the set should be put face down on a soft flat surface foam buffers or other specific workshop tools Ensure that a stable situation is created to perform measurements and alignments When using foam bars take care that these always support the cabinet and never only the display Caution Failure to follow these guidelines can seriously damage the display En
143. cted and error code 37 is the last detected error Note that no protection errors can be logged in the error buffer 5 5 3 5 5 4 Service Modes Error Codes and Fault Finding Q552 1A LA GEN e the blinking LED procedure See section 5 5 3 How content as this history can give significant information This to Clear the Error Buffer ensure that old error codes are no longer present Via ComPair If possible check the entire contents of the error buffer In some situations an error code is only the result of another error How to Clear the Error Buffer code and not the actual cause e g a fault in the protection detection circuitry can also lead to a protection Use one of the following methods There are several mechanisms of error detection By activation of the ERROR BUFFER command s IUBE si in the SAM menu polling on I O pins going to the stand by processor e Via sensing of analogue values on the stand by processor or the PNX85500 Via a not acknowledge of an IC communication the content of the error buffer has not changed for 50 hours it resets automatically Error Buffer Take notice that some errors need several minutes before they start blinking or before they will be logged So in case of problems wait 2 minutes from start up onwards and then check if the front LED is blinking or if an error is logged In case of non intermittent faul
144. ctivate the CSM in order to identify the status of the set Now the Service technician can judge the severity of the complaint In many cases he can advise the customer how to solve the problem or he can decide if it is necessary to visit the customer The CSM is a read only mode therefore modifications in this mode are not possible When in this chassis CSM is activated a testpattern will be displayed during 5 seconds 1 second Blue 1 second Green and 1 second Red then again 1 second Blue and 1 second Green This test pattern is generated by the 51 0 So if this test pattern is shown it could be determined that the back end video chain PNX51X0 LVDS and display of the SSB is working For TV sets without the PNX51 XO inside every menu from CSM will be used as check for the back end video chain When CSM is activated and there is a USB stick connected to the TV set the software will dump the complete CSM content to the USB stick The file Csm txt will be saved in the root of the USB stick This info can be handy if no information is displayed To have fast feedback from the field a flashdump can be requested While in CSM push the red button dial serial digits 2679 same keys to form the word COPY with a cellphone A file Dump settype serienumber bin will be written on the connected USB device This can take 1 2 minute depending on the quantity of data that needs to be dumped Also when CSM is activated t
145. ctly you must set both option number lines You can find the correct option numbers on a sticker inside the TV set and in Table 6 7 Option and display code overview Example The options sticker gives the following option numbers 08192 00133 01387 45160 12232 04256 00164 00000 2010 Apr 02 6 Q552 1A LA Alignments 6 4 5 6 5 6 5 1 2010 Apr 02 The first line group 1 indicates hardware options 1 to 4 the second line group 2 indicate software options 5 to 8 Every 5 digit number represents 16 bits so the maximum value will be 65536 if all options are set When all the correct options are set the sum of the decimal values of each Option Byte OB will give the option number See Table 6 7 Option and display code overview for the options Diversity Not all sets with the same Commercial Type Number CTN necessarily have the same option code Use of Alternative an alternative number usually indicates the use of an alternative display or power supply This results in another display code thus in another Option code Refer to Chapter 2 Technical Specifications Diversity and Connections Option Code Overview Table 6 7 Option and display code overview CTN Options Group 1 Options Group 2 Disp Alt BOM code 42PFL8605D 93 02060 12803 23359 40647 33552 34310 00000 00000 6 6 42PFL8605 98 102060 12803 23359 39363 00016 34304 00000 00000 AGPFL8605D 93 02060 1
146. cuit Diagrams and PWB Layouts Q552 1A LA ES LIN FF46 40 FF45 3V3 o 3 3 50 064 gt 3V3 IF47 3F44 2 oy SDIO DAT3 SDIO DAT3 2 7 e 47K 1008 F43 2 34136 spio cmp 8010 gt 2 cM 47K 100R C 2 43V3 SD k 3F44 1 3F45 RES spi0 cLK SDIO CLK gt 1 8 e C 5 10K 100R a F43 7 SDIO DAT0 5010 lt gt 3 706 47K _ 1008 F43 1 lt 9 4344145 splo DAT1 SDIO DAT1 5 314 47K F44 3 1008 porc SDIO DAT2 SDIO DAT2 2 3 6 e 47K 100R 1 09 2 27 527 SDIO CDn NSDIO CDn x e C 47K C n IF46 M2 91123 6 SDIO WP SDIO WP e 1939115 1 47K 2010 Apr 02 backio div table 1P09 1 C4 1P09 2 D4 2F40 A2 3F40 A2 3F41 1 C1 3F41 2 C1 3F41 3 C1 3F41 4 C1 3F42 1 C1 3F42 2 D1 3F42 3 D1 3F43 1 C3 3F43 2 C3 3F43 3 C3 3F44 1 C3 3F44 2 C3 3F44 3 C3 3F45 C1 FF41 FF42 C3 FF43 C3 FF44 D3 FF45 A2 FF46 C4 FF47 C3 FF48 C3 FF49 C3 FF50 D3 IF46 D1 IF47 8204 000 8994 18770 503 100118 5 100118 Circuit Diagrams PWB Layouts Q552 1A LA ES LIN PNX85500 Control 1 2 3 4 9 6 8 9 1F51 F8 1F52 D8 2F52 B1 2F53 D6
147. d remove all inserted media Restart the TV set Set the correct Display code via 062598 HOME where is the digit display panel code see sticker on the side 4 or bottom of the cabinet v After entering the Display Option code the set is going to Standby validation of code v Restart the set Y Connect PC via the ComPair interface to Service connector Start mode DVD OSD Open ComPair browser Q54x Saved settings on USB stick Yes Y Picture displayed Set is starting up without software upgrade menu appearing on screen upgrade menu appearing on screen Program set type number serial number and display 12 NC Program E DFU if needed Go to SAM and reload settings via Download from USB function In case of settings reloaded from USB the set type serial number display 12 NC are automatically stored when entering display options If not already done m Check latest software on Service website Update main and Stand by software via USB Attention point for Net TV If the set type and serial number are not filled the Net TV functionality will not work It will not be possible to connect to the internet Check and perform alignments
148. dby pP to 60h start comm protocol Timing needs to be updated if more mature info is available Flash to Ram image transfer succeeded within 30s Code Layer1 2 Layer2 15 Yes Timing needs to be updated if more mature info is available Code Switch AVC PNX85500 in Layari No reset active low SW initialization succeeded within 20s Disable all supply related protections and switch off the 3V3 5V DC DC converter Layer2 58 Enable Alive check mechanism MIPS reads the wake up reason Wait until AVC starts to from standby communicate Startup screen shall only be visible when there is a coldboot to an active state end situation The startup screen shall not be visible when waking up for reboot reasons or waking up to semi standby conditions or waking up to enter Hibernate mode Wake up reason coldboot amp not semi standby switch off the remaining DC DC converters Switch Standby line high and wait 4 seconds Yes yes The first time after the option turn on of the startup screen or when the set is virgin the cfg file is not present and hence the startup screen will not be shown Startup screen cfg file present yes Blink Code as error code No Enter protection 85500 sends out startup screen 85500 starts up the display Toon 2 up ine Startup screen visible 85500 requests Lamp on
149. e 3063208 FO27EO PX3D NES n nd 3G33 C9 FG28 9 gt Sem zm Oron 3G34 B9 FG29 E9 Pes 3035 FG2AE9 e pan 303608 FG2B E9 EE 2 s TUR 3037 09 FG2C 9 nen ES 9000 11 FG2D F9 23 4 FG2E D9 PX4D 2 EN 9GOK 2 C4 FG2F D9 N e rio je 9G0K 3C4 FG2G C9 zd i VDISP q FG2N 9G0K 4 C4 FG2H C9 408 FG2JD5 FG11E4 FG2K 09 FG12 F4 FG2L D10 FG13 F4 FG2M D10 FG14 F4 FG2N G11 FG15 F4 FG2P F11 FG16 F4 FG2R D11 FG17 F4 FG30 D5 FG18 F4 FG31 D5 FG19 F4 FG32 D5 FG1AF4 FG33D5 FG1BF4 FG34C11 1 2 3 4 5 6 7 8 9 10 11 12 13 LVDS Non DVBS 8204 000 8957 ____ 18770 566 100125 5 100125 E 2010 02 div table AmbiLight CPLD Circuit Diagrams and PWB Layouts Q552 1A LA 10 BO6C AmbiLight CPLD 1G35 G2 2610 1636 G2 2611 1637 B13 2612 2813 F7 2516 F8 26019 F9 2GA2 B4 2GAb5 B3 3G10 3 E6 2614 F8 2G17 F8 2GAO0 2 3G10 1 E6 3G10 4 E7 2815 F8 2618 F9 2GA1 B4 2GA4 G3 3G10 2 E7 3G11 1 E6 5GA0 FGA0 3V3 e p VINT 30R lt 515916 Sr 686 8 N N TN 5 1 FGA1 3V3 p gt e gt
150. e CSM is used for communication between the call centre and the customer This chassis also offers the option of using ComPair a hardware interface between a computer and the TV chassis It offers the abilities of structured troubleshooting error code reading and software version read out for all chassis see also section 5 4 1 ComPair Note For the new model range a new remote control RC is used with some renamed buttons This has an impact on the activation of the Service modes For instance the old MENU button is now called HOME or is indicated by a house icon Service Default Mode SDM Purpose e Tocreate a pre defined setting to get the same measurement results as given in this manual override SW protections detected by stand by processor and make the TV start up to the step just before protection a sort of automatic stepwise start up See section 5 3 Stepwise Start up e To start the blinking LED procedure where only LAYER 2 errors are displayed See also section 5 5 Error Codes Specifications Table 5 1 SDM default settings Default Region Freq MHz system Europe AP PAL Multi 475 25 PAL B G 546 00 PID Video 06 PID PCR 06 PID Audio 0B 07 Europe AP DVB T All picture settings at 50 brightness colour contrast Sound volume at 25 2010 Apr 02 back to div table e All service unfriendly modes if present are disa
151. e a DDR AD25 d VGA SDA EDID 9FC2 VGA_EDID_SDA 2 mS VGA SCL EDID 9FC4 VGA_EDID_SCL Lo o 7B00 i i RES EDE1116AEBG 7B01 L RES EDE1108AGBG EDE1108AGBG ANALOGUE P GAMMA amp VCOM amp FLASH SHARP AEYN TCON CONTROL VIDEO DF a eae E SHARP SDI 2515 VGA SDA EDID TCON TS 9514 VGA SCL EDID TCON E DDRZ A 0 13 _ RES DDR2 D 0 31 SDA TCON 7B02 EDE1116AEBG EDE1108AGBG 7803 EDE1108AGBG 7E10 LAN8710A EZK 3V3 ETHERNET CONNECTOR RJ45 3S81 RXD2 MIPS TXD2 MIPS Hrweeecweo TEMP SENSOR SDA SSB AIN 5V 1P04 ARX DDC SDA SDA UP MIPS 3F63 3F75 SDA TUNER TUN P7 TUN P6 7KQB M25P32 Q Oo Only for SHARP display with SSB Only for SHARP display with TCON on SSB mu _ 1651 SDA SET B Luc SDA DISP 3G2W LVDS SCLSET ____ ScLOISP i e connector e x NON DVBS CONNECTOR BOARD connectors SHARP 1F53 1F53 3K84 2D 2D
152. e assumption here is that a fast toggle 2s can only happen during ON gt SEMI gt In these states the AVC is still active and can provide the 2s delay A transition ON gt SEMI gt STBY gt SEMI gt ON cannot be made in less than 2s because the standby state will be maintained for at least 4s CPipe already generates a valid output clock in the semi standby state display startup can start immediately when leaving the semi standby state Switch on the display power by The exact timings to switching LCD PWR ON low switch on the delay lamp delay Wait x ms are defined in the Initialize audio and video display file Switch on LVDS output in the 85500 processing IC s and functions according needed use case Delay Lamp on with the sum of the LVDS delay and the Lamp delay indicated in the display file Switch off the dimming backlight feature set the BOOST control to nominal and make sure PWM output is set to maximum allowed PWM Switch on LCD backlight Lamp ON Start POK line Wait until valid and stable audio and video corresponding to the detection algorithm requested output is delivered by the AVC AND the backlight has been switched on for at least the time which is indicated in the display file as time return Switch Audio Reset low and wait 5ms Release audio mute and wait 100ms before any other audio handling is done e g volume change Restore dim
153. e of TCON alignment is to obtain equal voltages for both positive and negative LC polarity This is to avoid flicker and image sticking For alignment see 6 3 3 TCON Alignment back 2010 Apr 02 div table LINIEN IC Data Sheets 8 IC Data Sheets This chapter shows the internal block diagrams and pin electrical diagrams with the exception of memory and logic configurations of ICs that are drawn as black boxes in the ICs 8 1 Diagram USB Hub 01 USB2513B IC 7225 Block diagram To EEPROM or To Upstream Upstream 24 MHz SMBus Master USB Data Crystal SDA SCL Bus Serial Power Upstream Regulator Interface Detect PHY Vyus Pulse Serial Repeater Interface Controller Engine Lcd TT TT Regulator 1 Hx Controller CRFILT Routing amp Port Re Ordering Logic m Port 1 Port x OC Sense OC Sense Switch Driver Switch Driver LED Drivers LED Drivers 3 3 V USB Data OC Port USB Data OC Port Downstream Sense Power Downstream Sense Power Switch Switch LED LED Drivers Drivers The x indicates the number of available downstream ports 2 3 4 or 7 Note The LED port indicators only apply to USB2513i Pinning information HS IND CFG SEI 1
154. e to save the customer s TV settings and to store them into another SSB Download to USB To download several settings from the USB stick to the TV same way of working needs to be followed as with uploading To make sure that the download of the channel list from USB to the TV is executed properly it is necessary to restart the TV and tune to a valid preset if necessary NVM editor For NET TV the set type must be installed Also the production code can be entered via the RC transmitter How to Navigate e In SAM the menu items can be selected with the CURSOR UP DOWN key on the RC transmitter The selected item will be highlighted When not all menu items fit on the screen move the CURSOR UP DOWN key to display the next previous menu items e With the CURSOR LEFT RIGHT keys it is possible to De activate the selected menu item De activate the selected sub menu 2010 Apr 02 GLE EH Q552 1A LA service Modes Error Codes and Fault Finding 5 2 3 e With the OK key it is possible to activate the selected action How to Exit SAM Use one of the following methods Switch the TV set to STAND BY via the RC transmitter e Via a standard RC transmitter key in 00 sequence or select the BACK key Customer Service Mode CSM Purpose When a customer is having problems with his TV set he can call his dealer or the Customer Helpdesk The Service technician can then ask the customer to a
155. eck mechanism E g since the protection detections are done by means of software failing of the software will have to initiate a protection mode since safety cannot be guaranteed any more Remark on the Supply Errors The detection of a supply dip or supply loss during the normal playing of the set does not lead to a protection but to a cold reboot of the set If the supply is still missing after the reboot the TV will go to protection Protections during Start up During TV start up some voltages and IC observers are actively monitored to be able to optimise the start up speed and to assure good operation of all components If these monitors do not respond in a defined way this indicates a malfunction of the system and leads to a protection As the observers are only used during start up they are described in the start up flow in detail see section 5 3 Stepwise Start up Hardware Protections The only real hardware protection in this chassis appears in case of an audio problem e g DC voltage on the speakers This protection will only affect the Class D audio amplifier item 7010 see diagram and puts the amplifier in a continuous burst mode cyclus approximately 2 seconds Repair Tip There still will be a picture available but no sound While the Class D amplifier tries to start up again the cone of the loudspeakers will move slowly in one or the other direction until the initial failure shuts the amplifier d
156. ed mode converter is 350 kHz item no 7T03 and V LNB lines e the output signal on the V LNB line goes to the LNBH23Q item no 7T50 e the LNBH23Q item no 7T50 sends a feedback signal via the VO CNTRL line e the switching frequency of the 5V DVBS to 1 DVBS switched mode converter is 900 kHz item no 7T00 e adelay line for the 2V5 DVBS and 1V DVBS lines is created with item 3T03 R 10k and 2706 C 100n e a3 3V to 2 5V linear stabiliser is built around item no 7101 e a5V to 3 3V linear stabiliser is built around item no 7 2 Front End Analogue and DVB T DVB C ISDB T reception European China region The Front End for the European China region consist of the following key components Hybrid Tuner e Switchable SAW filter 7 8 MHz Eur or single SAW filter 8 MHz China e Bandpass filter e Amplifier 85500 SoC TV processor with integrated DVB T and DVB C channel decoder and analogue demodulator Below find a block diagram of the front end application for this region SELECT Sw SAW 18770_235_100127 eps 100219 Figure 7 6 Front End block diagram European China region 7 4 2 Brazil region The Front End for the Brazil region consist of the following key components Hybrid Tuner with integrated SAW filter and amplifier e External ISDB T channel decoder covering the Brazilian digital terrestrial TV standard Bandpass filter e Amplifier
157. emperature Normal All White point values to 127 In case you have a colour analyser e Measure with a calibrated contactless colour analyser Minolta CA 210 or Minolta CS 200 in the centre of the screen Consequently the measurement needs to be done in a dark environment e Adjust the correct x y coordinates while holding one of the White point registers R G or B on 127 by means of decreasing the value of one or two other white points to the Correct x y coordinates see Table 6 1 White D alignment values CCFL backlight panels 6 2 White D alignment values LED backlight panels colour analyser Minolta CA 210 or 6 3 White D alignment values LED backlight panels colour analyser Minolta CS 200 Tolerance dx 0 002 dy 0 002 e Repeat this step for the other colour temperatures that need to be aligned e When finished press OK on the RC and then press STORE in the SAM root menu to store the aligned values to the NVM Restore the initial picture settings after the alignments Table 6 1 White D alignment values CCFL backlight panels Cool 11000K Normal 9000K Warm 6500K 0 276 0 287 0 313 0 282 0 296 0 329 6 3 2 Alignments Q552 1A LA LUE Table 6 2 White D alignment values LED backlight panels 6 3 3 colour analyser Minolta CA 210 Cool 9420K Normal 8120K Warm 6080K 0 282 0 292 0 320 L 0 298 0 311 0 345 Table 6 3 White D alignment values LED
158. eps 100219 Figure 7 2 Architecture of TV550 platform TCON integrated on SSB xxPFL6xxx back to _ _ div table 2010 Apr 02 Q552 1A LA Circuit Descriptions 7 1 3 SSB Cell Layout m 1M36 DDR2 DDR2 LVDS OUT 20 00 DDR2 ejo HDMI 1 3 H HDMI 1 3H HDMI 1 3 gern 18990 200 100401 5 100401 Figure 7 3 SSB layout cells top view TCON integrated in display xxPFL8xxx FPGA DDR2 CA PNX85500 M1 27x27 20 00 IHE ung DDR2 SH SPDIF AUD DDR2 qu 2 HDMI 1 3 HDMI 13 q 18990 201 100401 eps 100401 Figure 7 4 SSB layout cells top view TCON integrated on SSB xxPFL6xxx back 2010 02 div table 7 2 7 2 1 Power Architecture Refer to figure Figure 7 5 for the power architecture of this platform Circuit Descriptions Q552 1A LA LEM LI 1 18770 234 100127 5 100127 Figure 7 5 Power Architecture TV550 platform Power Supply Unit All power supplies are a black box for Service When defective a new board must be ordered and the defective one must be returned unless the main fuse of the board is broken Always replace a defective fuse with one with the correct specifications This part is available in the regular market Consult the Philips Service web portal for the order codes of the boards Important delta s with the T
159. he LAYER 1 erroris displayed via blinking LED Only the latest error is displayed see also section 5 5 Error Codes How to Activate CSM Key in the code 123654 via the standard RC transmitter Note Activation of the CSM is only possible if there is no user menu on the screen How to Navigate By means of the CURSOR DOWN UP knob on the RC transmitter can be navigated through the menus Contents of CSM The contents are reduced to 3 pages General Software versions and Quality items The group names itself are not shown anywhere in the CSM menu General Set Type This information is very helpful for a helpdesk workshop as reference for further diagnosis In this way it is not necessary for the customer to look at the rear of the TV set Note that if an NVM is replaced is initialized after corruption this set type has to be re written to NVM This can be done in SAM via the NVM editor or ComPair Production Code Displays the production code the serial number of the TV Note that if an NVM is replaced or is initialized after corruption this production code has to be re written to NVM This can be done in SAM via the NVM editor or via ComPair 2010 Apr 02 back to div table Installed date Indicates the date of the first installation of the TV This date is acquired via time extraction Options 1 Gives the option codes of option group 1 as set in SAM Service Alignment Mode
160. he USA and used e g in LATAM and AP NTSC countries Blue TeleteXT Centre channel audio Consumer Electronics Control bus remote control bus on HDMI connections Constant Level audio output to connect with an external amplifier Component Level Repair Computer aided rePair Connected Planet Copy Protection Customer Service Mode Color Transient Improvement manipulates steepness of chroma transients Composite Video Blanking and Synchronization Digital to Analogue Converter Dynamic Bass Enhancement extra low frequency amplification Data Communication Module Also referred to as System Card or Smartcard for iTV See E DDC Monochrome TV system Sound carrier distance is 6 5 MHz Dynamic Frame Insertion DFU DMR DMSD DNM DNR DRAM DRM DSP DST DTCP DVB C DVB T DVD DVI d E DDC EDID EEPROM EMI EPG EPLD EU EXT FDS FDW FLASH FM FPGA FTV Gb s G TXT H HD HDD HDCP HDMI HP 2 26 IR IRQ ITU 656 Precautions Notes and Abbreviation List Q552 1A LA EM Directions For Use owner s manual Digital Media Reader card reader Digital Multi Standard Decoding Digital Natural Motion Digital Noise Reduction noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool special remote control designed for service technicians Digital Transmission Content Protection A protocol for protecting dig
161. he USB stick 2 Rename the autorun upg to something else e g to software upg Do not use long or complicated names keep it simple Make sure that AUTORUN UPG is no longer present in the root of the USB stick Copy the renamed upg file into this directory Insert USB stick into the TV 5 The renamed file will be visible and selectable in the upgrade application P back to div table Back up Software Upgrade Application If the default software upgrade application does not start could be due to a corrupted boot sector via the above described method try activating the back up software upgrade application How to start the back up software upgrade application manually 1 Disconnect the TV from the Mains AC Power 2 Press the CURSOR DOWN button on a Philips TV remote control while reconnecting the TV to the Mains AC Power 3 The back up software upgrade application will start Stand by Software Upgrade via USB In this chassis it is possible to upgrade the Stand by software via a USB stick The method is similar to upgrading the main software via USB Use the following steps 1 Create a directory UPGRADES on the USB stick 2 Copy Stand by software part of the one zip file e g StandbySW CFT72 88 0 0 0 upg into this directory 3 Insert the USB stick into the TV 4 Startthe download application manually see section Manual Software Upgrade 5 Select
162. he prior permission of Philips Published by ER TY 1063 BU TV Consumer Care the Netherlands Subject to modification EN 3122 785 18990 2010 Apr 02 PHILIPS EE El AEAN Revision List 1 Revision List Manual xxxx xxx 0 e First release 2 Technical Specifications Diversity and Connections Index of this chapter 2 1 Technical Specifications 2 1 Technical Specifications 2 7 For on line product support please use the CTN links Table 2 1 Here is product information available as well as getting 2 5 started user manuals frequently asked questions and software amp drivers Notes e Figures can deviate due to the different set executions e Specifications are indicative subject to change Table 2 1 Described Model Numbers and Diversity pese 42PFL8605D 93 Matisse 63643 2 3 s 7 4 1 Em 1 MOSI 11 1 0 16 42PFL8605 98 Matisse 63643 2 3 4 1 4 3 t b d 7 2 7 4 1 E 1 11 1 10 16 46PFL8605D 93 Matisse 3643 2 3 t b d 10 1 10 3 11 1 0 16 2 2 Directions for Use B01 Tuner 802 PNX85500 Additional LiteOn B06 non DVBS LVDS Common Everlight Additional Everlight DC DC Class D ___ Supp 809 non DVBS conn B11 TCON LGD B13 Ambilight B14 TCON SHP 5 LI ae efe Poson eie pie EE 1 io
163. ia and Hypermedia Experts Group It is commonly used as a language to describe interactive television services Microprocessor without Interlocked Pipeline Stages A RISC based microprocessor Matrix Output Processor Metal Oxide Silicon Field Effect Transistor switching device Motion Pictures Experts Group Multi Platform InterFace MUTE Line Mainstream TV TV mode with Consumer TV features enabled iTV Not Connected Near Instantaneous Compounded Audio Multiplexing This is a digital sound system mainly used in Europe Negative Temperature Coefficient non linear resistor National Television Standard Committee Color system mainly used in North America and Japan Color carrier NTSC 3 579545 MHz NTSC 4 43 4 433619 MHz this is a VCR norm it is not transmitted off air Non Volatile Memory IC containing TV related data such as alignments Open Circuit On Screen Display Over the Air Download Method of software upgrade via RF transmission Upgrade software is broadcasted in TS with TV channels On screen display Teletext and Control also called Artistic SAA5800 Project 50 communication protocol between TV and peripherals Phase Alternating Line Color system mainly used in West Europe color carrier 4 433619 MHz and South America color carrier PAL M 2010 Apr 02 PCM PDP PFC PIP PLL POD POR PSDL PSL PSLS PTC PWB PWM QRC QTNR QVCP RGB RC RC5 RC6 RESET
164. ight Common LiteOn LED Common 1 AL1 A LiteOn 15 LED Common A FH12 25S 0 5SH 55 O QI OQ N 3V3 FB12 gt e PWM CLOCK SPI DATA RETURN 15 SPI DATA IN FB16 SPI CLOCK 2 SPI DATA IN BUF gt SPI CLOCK BUF gt 3V3 7B06 74LVC1G32GW SPI CS gt 1 DATA SWITCH 2 SPI DATA RETURN 8 3 BLANK 3B00 1 1 8 3V3 2B11 100n 7826 1 TLC5946RHB PWM CLOCK BUF 150R PWM R1 PROG 4 3800 4 5 PWM G1 PWM B1 PWM G3 SPI CLOCK BUF 150R PWM R3 SPI DATA IN BUF SPI DATA IN 3 SPI DATA OUT 3B00 50R PWM R2 PWM G2 PWM B2 OO N O LATCH 2 9B00 2 7 lt FB20 3 130 PWM BS3 PWM G4 3B02 2 3V3 3B02 1 10K 24 8 3807 1 1 10K 7B23 1 BC847BS QOL 2 2 3B07 2 7 10K PWM B1 FB30 4 t 4 5 3B07 4 10K 7B23 2 BC847BS COL 5 es 3B07 3 6 10K PWM R1 FB31 E 3V3 2 7000 LTW 008RGB 150R 100p 2 2B04 2 7 PWM CLOCK 2 a PWM R4 PWM B4 PWM B5 PWM G5 PWM R5 DATA SWITCH 100R 1 3801 1 8 1 3830 1 8 3831 PWM CLO K BUF 7B20 2 74LVC2
165. in SAM according to the Service Manual Option codes colour temperature etc v Final check of all menus in CSM Special attention for HDMI Keys and Mac address Check if E D F U is present l Cm D Figure 5 11 SSB replacement flowchart back to div table Check if correct display option code is programmed Verify option codes according to sticker inside the set Default settings for white drive see Service Manual Q54x E SSB Board swap VDS Updated 22 03 2010 H 16771 007 100402 2010 Apr 02 GEJ EM Q552 1A LA service Modes Error Codes and Fault Finding Set is starting up in Factory mode oet is starting up in Factory mode Noisy picture with bands lines is visible and the is displayed and the HDMI 1 HED LED is continuous on input is displayed Press the volume minus button on the TVs local keyboard for 5 10 seconds Press the SOURCE button for 10 seconds until the disappears from the screen or the noise on the screen is replaced by blue mute The noise on the screen is replaced with the blue mute or the is disappeared Unplug the mains cord to verify the correct disabling of the Factory mode Program display option code 062598 MENU followed by the 3 digits code of the display this code can be found on a sticker on or inside the set After entering display option code the set is going in
166. in software and the default software upgrade application can be upgraded with the AUTORUN UPG FUS part of the one zip file e g 3104 337 05661 FUS _Q555X_ commercial zip This can also be done by the consumers themselves but they will have to get their software from the commercial Philips website or via the Software Update Assistant in the user menu see eUM The autorun upg file must be placed in the root of the USB stick How to upgrade 1 Copy AUTORUN UPG to the root of the USB stick 2 Insert USB stick in the set while the set is operational The set will restart and the upgrading will start automatically As soon as the programming is finished a message is shown to remove the USB stick and restart the set Manual Software Upgrade In case that the software upgrade application does not start automatically it can also be started manually How to start the software upgrade application manually 1 Disconnect the TV from the Mains AC Power 5 9 5 2 Press the OK button on a Philips TV remote control or a Philips DVD RC 6 remote control it is also possible to use a TV remote in DVD mode Keep the OK button pressed while reconnecting the TV to the Mains AC Power 3 The software upgrade application will start Attention In case the download application has been started manually the autorun upg will maybe not be recognized What to do in this case 1 Create a directory UPGRADES t
167. isplay option code in SAM even when picture is available Performance with the incorrect display option code can lead to unwanted side effects for certain conditions New in this chassis While the download application start up in TV mode button pressed the display option code can be changed via 062598 HOME XXX special SAM command XXX display option in 3 digits back 2010 02 div table Service Modes Error Codes and Fault Finding Q552 1A LA 5 5 8 11 SSB Replacement Follow the instructions in the flowchart in case a SSB has to be exchanged See figure SSB replacement flowchart Before starting prepare a USB memory stick with the latest software download the latest Main Software Fus from www p4c philips com unzip this file create a folder upgrades in the root of a USB stick size gt 50 and save the autorun upg file in this upgrades folder Note it is possible to rename this file e g Q54x SW version upg this in case there are more than one autorun upg files on the USB stick Due to a possible wrong display option code in the received Service SSB NVM it s possible that no picture is displayed Due to this the download application will not be shown either This tree enables you toload the main software step by step via the UART logging on the PC Instruction note SSB replacement Q543 x Q548 x Q549 x and Q55x x START
168. isplay panel code see sticker on the side bottom of the cabinet When no picture is available Due to a possible wrong display option code in the received Service SSB NVM no picture can be available at start up and thus no download application will be visible Here you can proceed and finalize step by step to load the main TV software via the UART logging on the PC for visual feedback 1 Start up the TV set equipped with the Service SSB and enable the UART logging on the PC see for settings 5 8 Fault Finding and Repair Tips 5 8 6 Logging 2 he TV set will start up automatically in the download application if main TV software is not loaded 3 Plug the prepared USB stick into the TV set press cursor Right to enter the list and navigate to the file in the UART logging printout via the cursor keys on the remote control When the correct file is selected press OK 4 Press cursor Down and to start the flashing of the main TV software Printouts like L 1 100 V 1 100 and P 1 100 should be visible now in the UART logging 5 Waituntil the message Operation successful is displayed and remove all inserted media Restart the TV set 6 correct display code via 062598 where is the 3 digit display panel code see sticker on the side bottom of the cabinet 6 7 Total Overview SAM modes Table 6 8 SAM mode overview Alignments Q552
169. it 4 refers to the Service version change code digits 5 and 6 refer to the production year and digits 7 and 8 refer to production week in example below it is 2006 week 17 The 6 last digits contain the serial number MADE IN BELGIUM 220 240V 50 60Hz PHILIPS 128W VHF S H UHF 10000 024 090121 5 100105 MODEL 32PF9968 10 PROD NO AG 1A0617 000001 Figure 3 1 Serial number example Board Level Repair BLR or Component Level Repair CLR If a board is defective consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level If your repair procedure says the board should be exchanged completely do not solder on the defective board Otherwise it cannot be returned to the O E M supplier for back charging Practical Service Precautions makes sense to avoid exposure to electrical shock While some sources are expected to have a possible dangerous impact others of quite high potential are of limited current and are sometimes held in less regard Always respect voltages While some may be dangerous in themselves they can cause unexpected reactions that are best avoided Before reaching into a powered TV set itis bestto test the high voltage insulation It is easy to do and is a good service precaution 2010 Apr 02 back to div table Precautions Notes and Abbreviation List Abbreviation List 0 6 12 AARA ACI ADC AFC
170. ital audio video content that is traversing a high speed serial bus such as IEEE 1394 Digital Video Broadcast Cable Digital Video Broadcast Terrestrial Digital Versatile Disc Digital Visual Interface d digital only Enhanced Display Data Channel VESA standard for communication channel and display Using E DDC the video source can read the EDID information form the display Extended Display Identification Data VESA standard Electrically Erasable and Programmable Read Only Memory Electro Magnetic Interference Electronic Program Guide Erasable Programmable Logic Device Europe EXTernal source entering the set by SCART or by cinches jacks Full Dual Screen Same as FDW Full Dual Window same as FDS FLASH memory Field Memory or Frequency Modulation Field Programmable Gate Array Flat TeleVision Giga bits per second Green TeleteXT H sync to the module High Definition Hard Disk Drive High bandwidth Digital Content Protection A key encoded into the HDMI DVI signal that prevents video data piracy If a source is HDCP coded and connected via HDMI DVI without the proper HDCP decoding the picture is put into a snow vision mode or changed to a low resolution For normal content distribution the source and the display device must be enabled for HDCP software key decoding High Definition Multimedia Interface HeadPhone Monochrome TV system Sound carrier distance is 6 0 MHz Inter IC bus Inter IC Da
171. ltage 1 15V nominal for the core voltage of PNX85500 stabilised close to the point of load SENSE 1V1 signal provides the DC DC converter the needed feedback to achieve this 1V8 supply voltage for the DDR2 memories and DDR2 interface of PNX85500 3V3 supply voltage 3 30V nominal overall 3 3 V for onboard 10 5 for non 5000 series SSB diversities only e 5V 5 15V nominal for USB WIFI and Conditional Access Module and 5V5 TUN for 5V TUN tuner stabiliser The linear stabilisers are providing 1V2 supply voltage 1 2V nominal stabilised close to PNX85500 device for various other internal blocks of PNX85500 SENSE 1V2 signal provides the needed feedback to achieve this 2 5 supply voltage 2 5V nominal for LVDS interface and various other internal blocks of PNX85500 for 5000 series SSB diversities the stabiliser is 7002 while for the other diversities 7UCO is used 3V3 supply voltage 3V3 nominal for 5000 series SSB diversities provided by 7003 in this case the 12V to 3V3 DC DC converter is not present e 5V TUN supply voltage BV nominal for tuner and IF amplifier 3V3 STANDY 3V3 nominal is the permanent voltage supplying the standby microprocessor inside PNX85500 Supply voltage 1 1 is started immediately when 12V voltage becomes available 12 is enabled by STANDBY signal when Supply voltages 3V3 2V5 1V8 1 2 and 5V TUN are switched by signal ENABLE
172. ming backlight feature PWM and BOOST output and unblank the video Switch on the Ambilight functionality according the last status settings Startup screen Option and Installation setting Photoscreen ON A Display cfg file present and up to date according correct display option Prepare Start screen Display config file and copy to Flash Active Figure 5 6 Semi Stand by to Active flowchart EEFL or LED backlight 50 100 Hz only A LED set does not normally need a preheat time The preheat remains present but is set to zero in the display file The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video Yes 18770 253 100216 eps 100216 back 2010 02 div table Service Modes Error Codes Fault Finding Q552 1A LA 5 LUN Semi Standby Wait until previous on state is left more than 2 seconds ago to prevent LCD display problems Assert RGB video blanking and audio mute There is no need to define the Backlight already on display timings since the timing splash screen gt implementation is part of the Yes The assumption here is that a fast toggle 2s can only happen during ON gt SEMI gt ON In these states the AVC is still active and can provide the 2s delay If the transitio
173. n DDR2 D18 s P3 DDR2 DQS3_N P DDR2 D22 S N1 s DDR2 DQS3 P 0082 023 U1 DDR2 D20 P1 DDR2 CAS 3560 DDR2 D21 Se T1 Se DDR2 CKE DDR2 CKE DDR2 D24 Se V4 gt DDR2 CS 10K DDR2 D30 Se R5 Se DDR2 ODT NN DDR2 D26 05 DDR2 D25 5 gt DDR2 RAS DDR2 ODT y vut DDR2 D28 Se N3 DDR2 WE 10K E DDR2 D31 Ss V3 DDR2 D27 4 DDR2 VREF CTRL2 0082 029 s V5 4 DDR2 VREF CTRL3 1188 15515818 9 98 wn 2 tt T dp N 6 2009 12 07 8204 000 8950 ____ 18770 512 100118 eps 100118 PNX85500 back to 2010 02 table PNX Digital Video In zl ple PNX Digital Video In 1 2 7800 6 PNX85500 HDMIA RX2 gt HDMIA RX2 E HDMIA RX1 gt HDMIA RX1 gt HDMIA RX0 gt HDMIA RX0 gt HDMIA RXC gt HDMIA RXC gt 3S0W 12K LLI RES 9I Circuit Diagrams PWB Layouts Q552 1A LA ES LIN DV A RX1 A Y26 DDCA SCL SCL DDC A SDA Y25 lt 1510 RX2_A HOT_PLUG_A i E 2010 02 div table 10 10 11 11 12 12 13 14 252 F5 3S0W E5 7900 6 06 1501 1510 7 13 14 DEM PNX85500 8204 000 8950 18770 513 100118 eps 100118 Circuit Diagrams PWB Layouts Q552 1A LA 10 LIN PNX Audio 802 D PNX Audio 1 2 3 4 5 6 7 8 9 10 11 12 13 BO2D 151 G7 IS1K H9 IS
174. n ON gt SEMI gt STBY gt SEMI gt ON can be made in less than 2s we have to delay the semi stby transition until the requirement is met No Initialize audio and video processing IC s and functions according needed use case Request Tcon to Switch on the backlight in a direct LED or set Lamp on line in case of a side LED Start POK line detection algorithm Wait until valid and stable audio and video corresponding to the requested output is delivered by the AVC Switch Audio Reset low and wait 5ms Release audio mute and wait 100ms before any other audio handling is done e g volume change The higher level requirement is that audio and video should be demuted without transient effects and that the audio should be demuted maximum 1s before or at the same time as the unblanking of the video unblank the video Switch on the Ambilight functionality according the last status settings Startup screen Option and Installation setting Photoscreen ON Yes j Display cfg file present and up to date according correct display option Prepare Start screen Display config file and copy to Flash Active 0 j 2 Yes 18770 254 100216 eps 100216 Figure 5 7 Semi Stand by to Active flowchart LED backlight 200 Hz back to _ _ div table 2010 Apr 02 LEM EM Q552 1A LA service Modes Error Codes and Fault Finding Active Mute all sound output
175. n initial tactory SSB back to div table mi U SIOdRAS Rui af LL Model WMP G15 PUN 482206241036 from 8 N 1162V291000037 Made In China F e gt k e ee 4 gt FH SMS PISA 50890242 5310432410121 131443 ALPHA 18310 221 090318 eps 090319 Figure 6 1 SSB identification Service SSB delivered without main software loaded Due to a changed manufacturing process new Service SSB s can be delivered to the warehouse without main TV software loaded Below you find the steps to follow when such an SSB is received When a picture is available 1 Mount the Service SSB into the TV set After start up normally the download application will appear on the Screen 2 Download the latest main software FUS from the www p4c philips com website 3 Create a folder upgrades in the root of a USB stick size gt 50 MB and save the autorun upg file in this upgrades folder Note it is possible to rename this file e g 0555 SW version upg this in case there are more than one autorun upg files on your USB stick 4 Plugthe prepared USB stick into the TV set and select the autorun file in the displayed browser on the screen 5 Now the main TV software will be loaded automatically supported by a progress bar 6 correct display code via 062598 where is the 3 digit d
176. n is for development purposes sions Acoustics parameters ACSTS 0 39 6 16 UL C Pos Poles POF Fiedsotings AmbighparmeesPREAMSO24 OOO O Development 2 file version 12NC zip software Display information is for development purposes mamans FTempcomfleversionnone Upload to USB To upload several settings from the to an USB encina LS Download from USB To download several settings from the USB stick to __ kr sentation data LS NVM editor editor re type number and production back to _ _ div table 2010 Apr 02 LEM Q552 1A LA Circuit Descriptions 7 Circuit Descriptions Index of this chapter 7 1 Introduction 7 2 Power Architecture 7 3 DC DC Converters 7 4 Front End Analogue and DVB T DVB C ISDB T reception 7 5 HDMI 7 6 Video and Audio Processing PNX85500 7 Back End 7 8 Ambilight 7 9 TCON Notes Only new circuits circuits that are not published recently are described e Figures can deviate slightly from the actual situation due to different set executions e For a good understanding of the following circuit descriptions please use the wiring block see chapter 9 Block Diagrams and circuit diagrams see chapte
177. nal 1 2V reg disabled MODE 0 0 MODE 1 0 MODE 2 0 INTERRUPT FUNCTION DISABLED ON nINT TXER TXD4 SIGNAL PHYADD 0 0 PHYADD 1 0 PHYADD 2 0 MII mode selected Internal 1 2V reg enabled MODE 0 1 MODE 1 1 MODE 2 1 INTERRUPT FUNCTION ENABLED ON nINT TXER TXD4 SIGNAL 2010 Apr 02 back to div table 11 12 14 ANALOG 9E42 D5 9E43 C3 G BE00 G6 BE01 G6 BE02 G6 BE03 H6 FE27 G6 FE28 G6 FE29 G6 FE30 G6 FE31 H6 H FE32 5 FE33 I5 FE34 H6 FE56 A11 FE57 A11 FE58 A11 IEO6 B4 IEO7 A3 IE26 C2 IE32 B3 IE33 B3 IE38 B4 IE39 D5 IE49 A10 IE50 AQ IE63 C6 IE64 C6 8204 000 8952 2009 10 22 18770 530 100118 eps 100118 Circuit Diagrams PWB Layouts Q552 1A LA 10 10 11 12 13 B04D 1P02 E2 5EC0 A8 1P03 C2 5EC2 F7 nga 2ECOA9 6EC1 H3 MICOM VCC33 5119187 OxB2 2 1 7202 G3 HDMI CONNECTOR 3 3V3 5
178. nalogue Externals B B04B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1E03 B3 1204 C3 1E07 A12 1E08 1 B3 1 08 2 E3 1E08 3 D3 1E09 F3 1E28 B4 A 1E29 D4 1E37 F4 SPDIF out 1E38 G4 YPBPR 1E39 C4 1 07 1 42 4 15 5E06 YKC21 5598 P od EU 9E29 ot SG AV3 Y SPDIF OUT jus CON JACK 1E43 B4 i 1E44 B10 2 m YPBPR1 SYNCIN1 Sm lt 2 YKB11 0946V 1E75 5 1 YELLOW Su E AP 9E04 3E88 IE73 e 1E76 15 il 1ECB 14 2220 4 MTJ 032 21B 41 NI FE EU 9E57 IE 4 E89 sd gt AV3 PB 2E21 14 E YPBPR1 PB 2E22 BY 1 2227 B4 2E35 F6 2E36 F4 2237 G4 AV3 PR 2E38 G6 w C 2E39 D4 2E40 E4 2 67 B4 2E68 C4 2 71 2E72 D5 YPBPR AUDIO 3E14 H6 3E15 H6 5 AUDIO IN3 R D x a a 3E87 B6 2TA 3E88 B6 3E89 B6 3E90 C6 YKC21 5598 gt rre E AUDIO IN3 L 3E96 E5 1E08 2 3E97 D5 me gle 5E06 B9 6E06 D5 E 6E15 H5 6E16 15 6E19 F5 6E20 G5 VGA OR DVI AUDIO 6 8 E5 6E40 B5 6E46 B11 1E09 E i 2 wv Se AUDIO IN4 L 6E51 B4 6E52 C4 218 F 9E04 B5 7 9E29 B5 9E57 B5 gt 9E58 C5 BE20 H6 wen es AUDIO IN4 R FEO1 F4 FEQ F5 G G5 FE41 B12 FE42 C4 FE43 D4 SVHS IN FE45 H5 FE44 BE20 3E14 46 4 2 188 FE48 C4 FE49 E4 H FE50 D4 FE51 B4 FE 0 1 3E15 dre e e gt Y SvHS FE59 B10 27R IE09 F6 IE10 G6 IE15 B9 IE29 E6 IE31 06 IE71 B6 IE72 B7 IE73 B7 IE74 B
179. nd H 264 supports new TV experiences with IPTV and VOD On top of that optional support is available for 2D dimming in combination with LED backlights for optimum contrast and power savings up to 50 For a functional diagram of the PNX85500 refer to Figure 7 9 2010 Apr 02 EN 42 Q552 1A LA Circuit Descriptions PNX85500x MEMORY CONTROLLER TS input MPEG SYSTEM LVDS for TS out in for PROCESSOR PRIMARY flat panel display PCMCIA VIDEO single dual or OUTPUT quad channel DVB T C channel decoder AV PIP SUB PICTURE VIDEO DECODER SD RGB SECONDARY VIDEO ENCODER analog CVBS OUTPUT DIGITAL IF MPEG H 264 VIDEO Motion accurate DECODER pixel processing SCALER T AUDIO DEMOD DE INTERLACE DECODE AND NOISE REDUCTION AUDIO DACS analog audio AUDIO IN AUDIO DSP 25 AUDIO OUT SPDIF 450 MHz RECEIVER AV DSP SYSTEM 560 MHz DRAWING CONTROLLER MIPS32 ENGINE 8051 24KEf CPU DMA BLOCK GPIO IR ADC SPI UART GPIO Flash USB2 0 SD Ethernet x8 Memory MAC Card 18770 241 100201 eps 100219 Figure 7 9 PNX85500 functional diagram back to 2010 Apr 02 div table Circuit Descriptions Q552 1A LA LIN 7 7 The following backlight types be distinguished Inte grated BackLight e CCFL EEFL backlight applicable to the xxPFL54xx sets Tcon CCFL LED backlight 50 100Hz SideLED side view edge LED without scanning PSL power
180. own this cyclus starts over and over again The headphone amplifier will also behaves similar 5 8 5 8 1 5 8 2 5 8 3 5 8 4 Service Modes Error Codes Fault Finding Q552 1A LA ES Fault Finding and Repair Tips Read also section 75 5 Error Codes 5 5 4 Error Buffer Extra Info Ambilight Due to degeneration process of the LED s fitted on the ambi module there can be a difference in the colour and or light output of the spare ambilight modules in comparison with the originals ones contained in the TV set Via SAM alignments gt ambilight the spare module can be adjusted Audio Amplifier The Class D IC 7D10 has a powerpad for cooling When the IC is replaced it must be ensured that the powerpad is very well pushed to the PWB while the solder is still liquid This is needed to insure that the cooling is guaranteed otherwise the Class D IC could break down in short time CSM When CSM is activated and there is a USB stick connected to the TV the software will dump the complete CSM content to the USB stick The file Csm txt will be saved in the root of the USB stick If this mechanism works it can be concluded that a large part of the operating system is already working MIPS USB DC DC Converter Description basic board The basic board power supply consists of 4 DC DC converters and 5 linear stabilisers All DC DC converters have 12 input voltage and deliver e 1V1 supply vo
181. peaker Interface bracket 32 Not displayed For screen size 32 only Front Cabinet Locking Bracket 40 Not displayed For screen size 40 only Stand Remote Control Not displayed Keyboard assy Loudspeaker assy left amp right FOR ELECTRICAL PARTS SEE WIRING DIAGRAM CHAPTER 9 18770_803_100216 eps 100401 E Z back to 2010 Apr 02 div table
182. r 10 Circuit Diagrams and PWB Layouts Where necessary you will find a separate drawing for clarification TV550 Basic Hybrid Tunes 85500 Noise ANALOGUE ae Del 7 1 7 1 1 Introduction The Q552 1A LA chassis is part of the TV550 platform and comes with the following stylings Da Vinci series xxPFL6xxx and Matisse series xxPFL8xx The TV550 platform is the successor of the TV543 platform Implementation Key components of this chassis are e 85500 System On Chip SOC TV Processor e TX31XX Hybrid Tuner DVB T C analogue e SII9x87 HDMI Switch e TPA312xD2PWP Class D Power Amplifier e LAN8710 Dual Port Gigabit Ethernet media access controller TV550 Architecture Overview For details about the chassis block diagrams refer to chapter 9 Block Diagrams An overview of the TV550 architecture can be found in Figure 7 1 Matrix d HDNM Ambilight Cpipe Ethernet 1251 Pixelated Ambi FHD 100p 18770_244_100203 eps 100219 Figure 7 1 Architecture TV550 platform TCON integrated in display xxPFL8xxx back to div table 2010 Apr 02 Circuit Descriptions Q552 1A LA 37 Hybrid Tuner Saw DDR II 52 3 85500 ANALOGUE Noise Dei 2 VCAR HDNM Ambilight Cpipe MAC B Ethernet HDMI LB LII 18770 245 100203
183. red when pressing cursor right or the OK button and then the SW Maintenance SW Events Not useful for Service purposes In case of specific software problems the development department can ask for this info HW Events Not useful for Service purposes In case of specific software problems the development department can ask for this info Test settings For development purposes only Development file versions Not useful for Service purposes this information is only used by the development department Upload to USB To upload several settings from the TV to an USB stick which is connected to the SSB The items are Channel list Personal settings Option codes Display related alignments Identification data and History list First a directory repair V has be created in the root of the USB stick To upload the settings select each item separately press cursor right or the OK button confirm with OK and wait until Done appears In case the download to the USB stick was not successful Failure will appear In this case check if the USB stick is connected properly and if the directory repair is present in the root of the USB stick Now the settings are stored onto the USB stick and can be used to download onto another TV or other SSB Uploading is of course only possible if the software is running and if a picture is available This method is created to be abl
184. rent situation when this error occurs the TV procedure when SDM is switched Remark this only will constantly reboot due to the blocked bus The best way works for TV sets with an 2 controlled screen included for further diagnosis here is to use ComPair Error 28 Channel dec DVB S When there is no Error 15 PNX8550 doesn t boot Indicates that the main communication towards the DVB S channel decoder processor was not able to read his bootscript This error will LAYER 2 error 28 will be logged and displayed via the point to a hardware problem around the PNX8550 blinking LED procedure if SDM is switched on supplies not OK PNX 8550 completely dead link Error 31 Lnb controller When there is no IC between PNX and Stand by Processor broken etc communication towards this device LAYER 2 error 31 When error 15 occurs it is also possible that 221 bus is back to _ _ div table 2010 Apr 02 GEN EH Q552 1A LA service Modes Error Codes and Fault Finding will be logged and displayed via the blinking LED procedure if SDM is activated Error 34 Tuner When there is no communication 5 6 2 towards the tuner during start up LAYER 2 error 34 will be logged and displayed via the blinking LED procedure when SDM is switched Error 35 main NVM When there is no communication towards the main NVM during start up LAYER 2 error 35 will be displayed via the blinking LE
185. resh this creates a more stable condition when switching off the power Switch AVC system in reset state reset system and reset AVC lines Switch reset USB Reset Ethernet and Reset DVBs LOW Wait 10ms Disable all supply related protections and switch off the DC DC converters ENABLE 3V3n Switch OFF all supplies by switching HIGH the Standby line entering Also here the standby state has to be maintained for at least 4s before starting Stand by 18770 256 100216 eps 100216 Figure 5 9 Semi Stand by to Stand by flowchart back to _ _ div table 2010 Apr 02 5 0552 1 LA service Modes Error Codes and Fault Finding 5 4 5 4 1 2010 Apr 02 Service Tools 5 5 ComPair 5 5 1 Introduction ComPair Computer Aided Repair is a Service tool for Philips Consumer Electronics products and offers the following 1 ComPair helps to quickly get an understanding on how to repair the chassis in a short and effective way 2 ComPair allows very detailed diagnostics is therefore capable of accurately indicating problem areas No knowledge UART commands is necessary because ComPair takes care of this 3 ComPair speeds up the repair time since it can automatically communicate with the chassis when the uP is working and all repair information is directly available 4 ComPair features TV software up possibilities Specifications ComPair consists of a Windows
186. ress MENU or HOME Back key on the RC transmitter 5 3 Service Modes Error Codes and Fault Finding Q552 1A LA 5 LU Stepwise Start up When the TV is in a protection state due to an error detected by stand by software error blinking is displayed and SDM is activated via shortcutting the SDM solder path on the SSB the TV starts up until it reaches the situation just before protection So this is a kind of automatic stepwise start up In combination with the start up diagrams below you can see which supplies are present at a certain moment Caution in case the start up in this mode with a faulty FET 7UOX is done you can destroy all IC s supplied by the 1V8 and 1v1 due to overvoltage 12V on XVX line It is recommended to measure first the FET WakeUp requested Acquisition needed Tact switch pushed stby requested and no data Acquisition required Tact switch pushed Tact switch pushed ast status is hibernate after mains ON Hibernate 7UOX or others FET s on shortcircuit before activating SDM via the service pads The abbreviations SP and MP in the figures stand for protection or error detected by the Stand by Processor protection or error detected by the MIPS Main Processor WakeUp requested St by requested tact SW pushed WakeUp requested SDM GoToProtection GoToProtection Protection 18770_250_100216 eps 100402 Figure 5 3 Tr
187. rial Clock CLock Signal Fast 2 bus Standard Definition Serial Data DAta Signal on Fast 2 bus Serial Digital Interface see ITU 656 Synchronous DRAM SEequence Couleur Avec M moire Color system mainly used in France and East Europe Color carriers 4 406250 MHz and 4 250000 MHz Sound Intermediate Frequency Switched Mode Power Supply System on Chip Sync On Green Self Oscillating Power Supply Serial Peripheral Interface bus a 4 wire synchronous serial data link standard Sony Philips Digital InterFace Static RAM Service Reference Protocol Small Signal Board Spread Spectrum Clocking used to reduce the effects of EMI Set Top Box STand BY 800 x 600 4 3 back to div table Precautions Notes and Abbreviation List SVHS SW SWAN SXGA TFT THD TMDS TS TXT TXT DW Ul uP UXGA V VESA VGA VL VSB WYSIWYR WXGA XTAL XGA Y Y C YPbPr YUV Super Video Home System Software Spatial temporal Weighted Averaging Noise reduction 1280 x 1024 Thin Film Transistor Total Harmonic Distortion Transmission Minimized Differential Signalling Transport Stream TeleteXT Dual Window with TeleteXT User Interface Microprocessor 1600 x 1200 4 3 V sync to the module Video Electronics Standards Association 640 x 480 4 3 Variable Level out processed audio output toward external amplifier Vestigial Side Band modulation method What You See Is What You Re
188. rvice Modes Error Codes and Fault Finding The SAM menu will now appear on the screen Select ALIGNMENTS and go to one of the sub menus The alignments are explained below The following items can be aligned White point e Ambilight e TCON Alignment Reset TCON Alignment To store the data e Press OK on the RC before the cursor is moved to the left e In main menu select Store and press OK on the RC e Switch the set to stand by mode 2010 Apr 02 back to div table For the next alignments supply the following test signals via a video generator to the RF input e EU AP PAL models a PAL B G TV signal with a signal strength of at least 1 mV and a frequency of 475 25 MHz e US AP NTSC models an NTSC M N TV signal with signal strength of at least 1 mV and a frequency of 61 25 MHz channel 3 e models NTSC M TV signal with a signal strength of at least 1 mV and a frequency of 61 25 MHz channel 3 White Point Choose TV menu Setup More TV Settings and then Picture and set picture settings as follows Picture Setting Brightness 9 e n menu Picture choose Pixel Plus HD and set picture settings as follows Picture Setting Dynamic Backlight e Go to the SAM and select Alignments gt White point White point alignment LCD screens Use a 90 white screen to the HDMI input and set the following values Colour t
189. s via softmute Wait 100ms Set main amplifier mute audio mute Force ext audio outputs to ground audio reset And wait 5ms switch off Ambilight Wait until Ambilight has faded out Output power Observer should be zero Switch off POK line detection algorithm switch off LCD backlight or Mute all video outputs Yes lt Wait x ms display file Instruct 200Hz The exact timings to switch off the display LVDS delay lamp delay are defined in the display file Tcon to turn off the display Switch off LVDS output in 85500 Wait x ms Switch off the display power by switching LCD PWR ON high Semi Standby Figure 5 8 Active to Semi Stand by flowchart 18770_255_100216 eps 100216 back 2010 02 div table Important remarks release reset audio 10 sec after standby to save power another state transition Service Modes Error Codes and Fault Finding Q552 1A LA EHI Semi Stand by If ambientlight functionality was used in semi standby lampadaire mode switch off ambient light see CHS ambilight Delay transition until ramping down of ambient light is 7 If this is not performed and the set is finished switched to standby when the switch off of the ambilights is still ongoing the lights will switch off abruptly when the supply is cut transfer Wake up reasons to the Stand by uP Switch Memories to self ref
190. ssibility for diagnosis e g when Development asks for this Initialize the NVM Note When the NVM is corrupted or replaced there is a high possibility that no picture appears because the display code is not correct So before initializing the NVM via the SAM a picture is necessary and therefore the correct display option has to be entered Refer to Chapter 6 Alignments for details To adapt this option it s advised to use ComPair the correct values for the options can be found in Chapter 6 Alignments or a method via a standard RC described below Changing the display option via a standard RC Key in the code 062598 directly followed by the MENU or HOME back to div table button and XXX where XXX is the 3 digit decimal display code as mentioned in Table 6 7 Make sure to key in all three digits also the leading zero s If the above action is successful the front LED will go out as an indication that the RC sequence was correct After the display option is changed in the NVM the TV will go to the Stand by mode If the NVM was corrupted or empty before this action it will be initialized first loaded with default values This initializing can take up to 20 seconds Display Option Code PHILIPS MODEL 32PF9968 10 PROD SERIAL NO AG 1A0620 000001 E 06532 038 eps 240108 Figure 5 2 Location of Display Option Code sticker e Store go right All options and alignments are sto
191. stand by mode validation of code Restart the set Figure 5 12 SSB replacement flowchart Factory mode H_16771_007b eps 100322 back to 2010 Apr 02 div table 5 9 5 9 1 5 9 2 Service Modes Error Codes Fault Finding Q552 1A LA ES GEJ Software Upgrading Introduction The set software and security keys are stored in a NAND Flash which is connected to the PNX85500 It is possible for the user to upgrade the main software via the USB port This allows replacement of a software image in a stand alone set without the need of an E JTAG debugger A description on how to upgrade the main software can be found in the electronic User Manual 5 9 3 Important When the NAND Flash must be replaced a new SSB must be ordered due to the presence of the security keys CI MAC address Perform the following actions after SSB replacement 1 Setthe correct option codes see sticker inside the TV 2 Update the TV software see the eUM electronic User Manual for instructions 3 Perform the alignments as described in chapter 6 section 6 5 Reset of Repaired SSB 4 Check CSM if the CI key MAC address are valid For the correct order number of a new SSB always refer to the Spare Parts list Main Software Upgrade 5 9 4 e The UpgradeAll upg file is only used in the factory Automatic Software Upgrade In normal conditions so when there is no major problem with the TV the ma
192. sure that ESD safe measures are taken Assy Panel Removal Matisse Styling No detailed information is available at time of publishing Set Re assembly Tore assemble the whole set execute all processes in reverse order Notes While re assembling make sure that all cables placed and connected in their original position e special attention not to damage the EMC foams in the set Ensure that EMC foams are mounted correctly back to _ _ div table 2010 Apr 02 5 0552 1 LA Service Modes Error Codes and Fault Finding Service Modes Error Codes and Fault Finding 5 5 1 5 2 5 2 1 Index of this chapter 5 1 Test Points 5 2 Service Modes 5 3 Stepwise Start up 5 4 Service Tools 5 5 Error Codes 5 6 The Blinking LED Procedure 5 7 Protections 5 8 Fault Finding and Repair Tips 5 9 Software Upgrading Test Points As most signals are digital it will be difficult to measure waveforms with a standard oscilloscope However several key ICs are capable of generating test patterns which can be controlled via ComPair In this way it is possible to determine which part is defective Perform measurements under the following conditions e Service Default Mode e Video Colour bar signal Audio 3 kHz left 1 kHz right Service Modes Service Default mode SDM and Service Alignment Mode SAM offers several features for the Service technician while the Customer Service Mod
193. t Bk Coaxial 0 4 0 6Vpp 75 ohm gt 12 HDMI 2 amp 3 optional Digital Video Digital Audio In See 3 HDMI Digital Video Digital Audio In 13 HDMI 1 Digital Video In Digital Audio with ARC In Out 19 1 Waco e 10000 017 090121 eps 090428 Figure 2 5 HDMI type connector 1 02 Data channel 2 Shield Gnd 3 02 Data channel 4 D1 Data channel 5 Shield Gnd 6 01 Data channel 7 00 Data channel 8 Shield Gnd 9 DO Data channel 10 CLK Data channel 2 4 Chassis Overview Refer to chapter Block Diagrams for PWB CBA locations 2010 Apr 02 back to div table 11 Shield Gnd 12 CLK Data channel 13 Easylink CEC Control channel 14 ARC Audio Return Channel 15 DDC SCL DDC clock 16 DDC SDA DDC data 17 Ground Gnd 18 5V 19 HPD Hot Plug Detect 20 Ground Gnd 14 Cinch Audio In VGA DVI Rd Audio 0 5 Vrms 10 kohm Wh Audio L 0 5 10 kohm 15 Aerial In EC type EU Coax 75 ohm 16 VGA Video RGB In 5 OOOOO Q 29999 O15 10000 002 090121 eps 090127 Figure 2 6 VGA Connector 1 Video Red 0 7 Vpp 75 ohm 2 Video Green 0 7 Vpp 75 ohm 3 Video Blue 0 7 Vpp 75 ohm 4 n c 5 Ground Gnd 6 Ground Red Gnd 7 Ground Green Gnd 8 Ground Blue Gnd 9 5Vpc 5 V 10 Ground Sync Gnd 11 n c 12 DDC SDA DDC data 13 H sync 0 5V 14 V sync 0 5V 15 DDC SCL DDC clock
194. t CVBS LR ENS SIDE Off On Select SIDE I O On Off Off On Select HDMI 3 On Off Miscellaneous Region Select Region country muere E _ back to 2010 Apr 02 div table Alignments Q552 1A LA LUE C 227 2 71 E 771 17 277770 Option numbers e g 00008 01793 15421 08192 DEBE The first line group 1 indicates hardware options 1 to 4 e g 44013 34315 00000 00000 LE The second line group 2 indicates software options 5108 Store Select Store in the SAM root menu after making any changes Operation hours display In case the display must be swapped for repair you can reset the Display operation hours to 0 So this one does keeps up the lifetime of the display it self mainly to compensate the degeneration behav iour Software maintenance Software events bo Display information is for development purposes E ra Hardware events Display Display information is for development purposes modulation None Display information is for development purposes w r Tanqa emen oo POP Installation Digital only Select Digital only or Digital Analogue before instal Development file ver Development 1 file version Display parameters DISPT6 0 9 8 Display informatio
195. t Diagrams PWB Layouts Q552 1A LA 10 Ethernet Service BO 4 Ethernet Service 1 2 3 4 5 6 7 8 9 10 11 12 13 14 B04C 1E06 A13 1E70 B3 1E85 A11 1E86 A11 1N00 G7 3V3 ET ANA 20825 2 49 5 _ 3659 2 3E53 1 i A 2E52 B3 5E08 07 3 3 s s 30R 2E62 10u 2E63 100n 2E66 100n 47R 47R 1 06 1850 3E53 3 FES7 UART 2E53 B4 RXD1 MIPS 6 3 e 2 ES 3V3 ET ANA 3V3 47R 47 I SERVICE 2E54 B3 21 5157 CONNECTOR 2E55 FE58 6E43 gt BZX384 C5V1 6 44 221 BZX384 C5V1 1E85 1E86 Y Y 2E56 H2 2E57 H2 2E58 H3 1M0 2E59 H4 3V3 2 2 60 5 L B 2E62 A3 25M 2E63 A3 2E66 A3 3E22 1 F2 3E22 2 F3 ETH EXP 3E22 3 F2 3E22 4 F2 CEA 3E26 F5 ETH TXCLK x ETH RXDV 3 34 06 5 06 1264 RES Mens E 3565 IOK ETH RXCLK ON 3E53 1 A10 gt 53 2 A9 ETH INTSEL 3E53 3 A10 129 S672 S895 avs D 3E53 4 A9 ES gt ETH CRS 3E64 C6 3E65 D6 3E66 B2 3E67 B2 3E68 D6 3E69 C2 3E70 C1 3E71 C3 E 3E72 D6 3E95 1 F3 95 2 3E95 3 F4 3E95 4 F4 3E98 F5 5E08 A3 ey GE43 A9 6 44 A10 1 z 6E47 G2 6E48 G3 6E49 G4 CONFIGURATION RESISTOR SETTINGS 6E50 G5 7E10 1 B4 7E10 2 E4 IE32 IE38 IE06 0 33 2 52 100 2E5
196. ta bus Inter IC Sound bus Intermediate Frequency Infra Red Interrupt Request The ITU Radio communication Sector ITU R is a standards body subcommittee of the International Telecommunication Union relating to radio communication ITU 656 a k a back to div table ITV LS LATAM LCD LED L L LPL LS LVDS Mbps M N MHEG MIPS MOP MOSFET MPEG MPIF MUTE MTV NC NICAM NTC NTSC NVM O C OSD OAD OTC P50 PAL 01 is a digitized video format used for broadcast grade video Uncompressed digital component or digital composite signals can be used The SDI signal is self synchronizing uses 8 bit or 10 bit data words and has a maximum data rate of 270 Mbit s with a minimum bandwidth of 135 MHz Institutional TeleVision TV sets for hotels hospitals etc Last Status The settings last chosen by the customer and read and stored in RAM or in the NVM They are called at start up of the set to configure it according to the customer s preferences Latin America Liquid Crystal Display Light Emitting Diode Monochrome TV system Sound carrier distance is 6 5 MHz L is Band L is all bands except for Band LG Philips LCD supplier Loudspeaker Low Voltage Differential Signalling Mega bits per second Monochrome TV system Sound carrier distance is 4 5 MHz Part of a set of international standards related to the presentation of multimedia information standardised by the Multimed
197. the appropriate file and press the OK button to upgrade Content and Usage of the One Zip Software File Below the content of the One Zip file is explained and instructions on how and when to use it e FUS 05551 commercial zip Contains the autorun upg which is needed to upgrade the TV main software and the software download application StandbySW CFTxx x x x x commercial zip Contains the Stand by software in upg and hex format The StandbySW_xxxxx_prod upg file can be used to upgrade the Stand by software via USB The StandbySW_xxxxx hex file can be used to upgrade the Stand by software via ComPair The files StandbySW xxxxx exhex hex and StandbySW xxxxx dev upg may not be used by Service technicians only for development purposes UpgradeAll_Q555X_x x x x_commercial zip Only for production purposes not to be used by Service technicians ProcessNVM Q55XX x x x x zip Default NVM content Must be programmed via ComPair or can be loaded via USB be aware that all alignments stored in NVM are overwritten here UART logging 2K10 see section 5 8 Fault Finding and Repair Tips 5 8 6 Logging 2010 Apr 02 LUE EM Q552 1A LA Alignments 6 Alignments Index of this chapter 6 1 General Alignment Conditions 6 2 Hardware Alignments 6 3 Software Alignments 6 4 Option Settings 6 5 Reset of Repaired SSB 6 6 Service SSB delivered without main software loaded
198. the supply detection algorithm Set 2 slave address of Standby uP to AOh Detect EJTAG debug probe pulling pin of the probe interface to An EJTAG probe e g WindPower ICE probe can be ground by inserting EJTAG probe connected for Linux Kernel debugging purposes JTAG probe Yes connected No No No Cold boot Yes Release AVC system reset Release AVC system reset Release AVC system reset Feed warm boot script Feed cold boot script Feed initializing boot script disable alive mechanism 18770 251 100216 eps Figure 5 4 to Semi Stand by flowchart part 1 back to div table 100216 Service Modes Error Codes and Fault Finding Q552 1A LA 5 Reset system is switched HIGH by the Reset system is switched HIGH by the AVC at the end of the bootscript AVC at the end of the bootscript No AVC releases Reset Ethernet Reset USB and AVC releases Reset Ethernet Reset USB and This cannot be done through the bootscript Reset DVBs when the end of the AVC boot Reset DVBs when the end of the AVC boot the I O is on the standby pP script is detected script is detected Reset Audio and Audio Mute Up are Reset Audio and Audio Mute Up are switched by MIPS code later on in the Switched by MIPS code later on in the Timing need to be updated if startup process startup process more mature info is available Bootscript ready No in 1250 ms Yes Set slave address of Stan
199. ts clear the error buffer before starting to repair before clearing the buffer write down the Table 5 2 Error code overview Monitored Error Buffer Description Layer 1 Layer 2 Prot Blinking LED Device Defective Board LIEB PNX aoesrrt boot HW cause 2 i5 P eL wo e p B jm HDMI mux 2 p 510 87 2 switch 2 PCA9540 Channel dec DVB S 2 mrs STV0903 Lnb controller 2 a mrs LNBH23 Tue ________ MS DTT 71300 mrs STM24C64 Tuner DVB S 21 mrs T sensor SSB set 2 mrs LM 78 T sensor LED driver Tcon 7 42 MIPS LM 78 PNX doesn t boot SW cause PNXe550 Display MIPS BL EB Altera Display Extra Info blocked NVM 2 1 can be indicated in the schematics as Rebooting When a TV is constantly rebooting due to follows SCL UP MIPS SDA UP MIPS internal problems most of the time no errors will be logged Other root causes for this error can be due to hardware or blinked This rebooting can be recognized via a ComPair problems regarding the DDR s and the bootscript reading interface and Hyperterminal for Hyperterminal settings from the PNX8550 see section 5 8 Fault Finding and Repair Tips 5 8 6 e Error 16 12V This voltage is made in the power supply Logging It s shown that the loggings which are generated and results in protection LAYER 1 error 3 in case of by the main soft
200. use the correct temperature profile Where applicable and available this profile is added to the IC Data Sheet information section in this manual Lead free Soldering Due to lead free technology some rules have to be respected by the workshop during a repair Use only lead free soldering tin If lead free solder paste is required please contact the manufacturer of your soldering equipment In general use of solder paste within workshops should be avoided because paste is not easy to store and to handle e Use only adequate solder tools applicable for lead free soldering tin The solder tool must be able Toreach a solder tip temperature of at least 400 C stabilize the adjusted temperature at the solder tip exchange solder tips for different applications e Adjust your solder tool so that a temperature of around 360 380 is reached and stabilized at the solder joint Heating time of the solder joint should not exceed 4 sec Avoid temperatures above 400 C otherwise wear out of tips will increase drastically and flux fluid will be destroyed To avoid wear out of tips switch off unused equipment or reduce heat e Mix of lead free soldering tin parts with leaded soldering tin parts is possible but PHILIPS recommends strongly to avoid mixed regimes If this cannot be avoided carefully clear the solder joint from old tin and re solder with new tin 2010 Apr 02 3 3 6 3 3 7 3 3 8 Q552 1A
201. voltage for DVB S2 channel decoder e 1V DVBS core voltage for DVB S2 channel decoder 12 V under voltage detector see diagram BO3C enables the 12V to 3 3 and 12V to 5V DC DC converters via the ENABLE 3V3 5V line and the 12V to 1 8V DC DC converter via the ENABLE 1V8 line DETECT2 is the signal going to the standby microcontroller ENABLE 3V3n is the signal coming from the standby microcontroller Diagram contains the following linear stabilisers e 42V5 stabiliser built around item no 7UCO e 5V TUN stabiliser built around items no 7UA6 7UA7 e 1V2 stabiliser built around items no 7UA3 and 7UAA Diagram BO8A contains the DVB S2 related DC DC converters and stabilisers e 24 under voltage detection circuitry is built around item no 7TO4 2010 Apr 02 Table 7 2 Connector overview Connector Come me uos wi 46 wes wes mos Jimer Descr mains mains to SSB to Amb Tcon Pi ow ona ons 2v 2 jr fiwa snay av jew fonni onor GND1 BL ON GND1 _ LN E e GND_ SND bh n c back to div table 7 4 7 4 1 e the switching frequency of the 24 to 14 20V switch
202. w to Exit SDM Use one of the following methods Switch the set to STAND BY via the RC transmitter e Via standard customer RC transmitter key in 00 sequence 5 2 2 Service Modes Error Codes Fault Finding Q552 1A LA ES LEN Service Alignment Mode SAM Purpose To perform software alignments Tochange option settings To easily identify the used software version e To view operation hours To display or clear the error code buffer How to Activate SAM Via a standard RC transmitter Key in the code 062596 directly followed by the INFO HOME button After activating SAM with this method a service warning will appear on the screen continue by pressing the OK button on the RC Contents of SAM see also Table 6 8 Hardware Info A SW Version Displays the software version of the main software example Q555X 1 2 3 4 AAAAB X Y W Z e AAAA the chassis name e B the SW branch version This is a sequential number this is no longer the region indication as the software is now multi region e X Y W Z the software version where X is the main version number different numbers are not compatible with one another and Y W Z is the sub version number a higher number is always compatible with a lower number B STBY PROC Version Displays the software version of the stand by processor C Production Code Displays the production code of the TV this
203. ware keep continuing In this case absence When SDM is activated we see blinking LED diagnose has to be done via ComPair LAYER 2 error 16 Error 13 FC bus 3 558 bus blocked At the time of Error 17 Invertor or Display Supply Here the status of release of this manual this error was not working as the Power is checked by software no protection will expected Current situation when this error occurs the TV occur during failure of the invertor or display supply no will constantly reboot due to the blocked bus The best way picture only error logging LED blinking of LAYER 1 for further diagnosis here is to use ComPair error in CSM in this gives LAYER 2 error 17 Error 14 FC bus 2 TV set bus blocked At the time of Error 23 HDMI When there is no IC communication release of this manual this error was not working as towards the after start up LAYER 2 error 23 expected Current situation when this error occurs the TV will be logged and displayed via the blinking LED will constantly reboot due to the blocked bus The best way procedure if SDM is switched on for further diagnosis here is to use ComPair Error 24 I2C switch When there is IC Error 18 bus 4 Tuner bus blocked At the time of communication towards the switch LAYER 2 release of this manual this error was not working as error 24 will be logged and displayed via the blinking LED expected Cur
204. with a large number of IC ICs in the set To ensure good communication and to make digital diagnosis possible the microprocessor has to know which ICs to address The presence absence of these PNX51XX ICs back end advanced video picture improvement IC which offers motion estimation and compensation features commercially called HDNM plus integrated Ambilight control is made known by the option codes Notes e After changing the option s save them by pressing the OK button on the RC before the cursor is moved to the left select STORE in the SAM root menu and press OK on the RC e new option setting is only active after the TV is switched off stand by and again with the mains switch the NVM is then read again Dealer Options For dealer options in SAM select Dealer options See Table 6 8 SAM mode overview Service Options Select the sub menu s to set the initialisation codes options of the model number via text menus See Table 6 8 SAM mode overview Opt No Option numbers Select this sub menu to set all options at once expressed in two long strings of numbers An option number or option byte represents a number of different options When you change these numbers directly you can set all options very quickly All options are controlled via eight option numbers When the NVM is replaced all options will require resetting To be certain that the factory settings are reproduced exa

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