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Microcontroller Prototyping System - Using Cortex-M3

1. 0x9000 0000 Reserved Ox1F00 1000 0x2000 0000 Ox1F00 6000 Ox1F00 OFEC 0x8000 0000 Ox1F00 0000 Config Regs Config Regs Ox1F00 5000 PLO11 3 Ox1EFF_0000 RAM FPGA 64k RAM FPGA 64k 0x1F00_4000 PLO22 TouchScrn Reserved 0x7000_0000 NOx1F00_3000 12C DVI i Reserved A 0xiC00 0000 OxlE00 2000 Reserved SMC OxlF00 0014 0x6000 0000 Reserved 0x1F00 1000 Reserved SMC 0x1F00_0010 TS Status Flash 64M alias 0x1F00_0 000 CPU Sys Regs 0x1F00_000C CPU LEDs 0x5000_0000 0x1800_0000 0x1F00_0008 CPU Switches 0x F00_0004 Remap Alias Reserved Reserved 0x4000_0000 9x1080_0000 Ox1F00 0000 System ID 0x1040 0000 RAM B 4M RAM B 4M 0x3000 0000 0x1000 0000 RAM A 4M RAM A 4M ALIAS 1 ALIAS 0 0x2000_0000 01000 0000 Int ROM Exec i ns 0x1000 0000 li Int ROM Exec Reserved Reserved 0x0000 0000 0x0400 0000 SS Flash 60M 0x00 0000 Flash 64M 0x0000 0000 RAM A 4M MPB M3 Processor FPGA REMAP 1 REMAP 0 Figure 9 CPU FPGA memory map 16 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Programmer s model 5 1 2 DUT FPGA M3 memory area function OxF000_0000 0xE010_0000 0x10000_0000 0xC000 0000 0xA400 0000 OxEO00 0000 OxA3FF 0000 Jf xA400 0000 7 di 0xA000 0000 OxD000 0000 0xC000 0000 0xA002 0000 0xA00 0 0000 0xB000 0000 0x5000_0000 0xA000_0000 Ox4FFF_0000 Ox4EF 0000 0x9000 0000 O XAFF
2. Figure 7 MPB M3 Clock and Reset Architecture 3 2 1 Clock Routing Name CLK100M CLKO CLK1 EXT CLK5p CLK15p CLK1p CLK10p CLK4p CLK13p DUT_PLL_T1_CLKOUT3 DUT_PLL_B1_CLKOUT3 DUT_PLL_R2_CLKOUTO CPU PLL L2 CLKOUTO CPU PLL R2 CLKOUTO CPU PLL B2 CLKOUTS3 CPU PLL T2 CLKOUT3 L14 CPUCLK Diff L14 DUTCLK Diff Table 1 Clock Routing Application Note 218 ARM DAI0218A Freq Hz Source Destination Note 100M Osc CF DUT CPU Buffered output to DUT and CPU BB CF Oscillator module on Baseboard BB CF Oscillator module on Baseboard BB CF External SMB clock input on Baseboard CF CPU Direct connection to CPU only CF CPU Direct connection to CPU only HCLK CF CPU DUT Buffered match lengths to DUT amp CPU HCLK 25M CF CPU DUT Buffered match lengths to DUT amp CPU CLK25MHz CF DUT Direct connection to DUT only CF DUT Direct connection to DUT only 25 175M DUT CF CPU MCBO Buffered FPGA output from internal PLL 12 288M DUT CF CPU MCBO Buffered FPGA output from internal PLL 25M DUT CF Direct FPGA output from internal PLL 50M CPU CF Direct FPGA output from internal PLL 25M CPU CF Direct FPGA output from internal PLL OM CPU CF Direct FPGA output from internal PLL OM CPU CF Direct FPGA output from internal PLL OM CPU DUT Direct FPGA differential output for L14 interface OM DUT CPU Direct FPGA differential output for L14 interface Copyright 2009 ARM Limited All rights reserved 11 Architecture 3 2 2
3. A9 RO fw FPGAbud S Name Bs Reseved Big dT SCC USB FORCE SLOW RW bo Forces the USB interface io operate slowly USB HC WAKE RO b Status of USB Host Controller Wake Suspend signal USB DC WAKE E We p ou Status of USB Device Controller Wake Suspend signal Reseved B RO Reseved k RW bo 1 Reserved p pw bo Application Note 218 Copyright 2009 ARM Limited All rights reserved 19 ARM DAI0218A Programmer s model Reserved 2 RO OO WPROT RO b0 Status of MCI WPROT bit 1 write protected CARDIN o RO bo Status of MCI card Present 1 card inserted The HUMI Mode bits define how the scheduler selects the different display components on the system This can be used for system debug Mode Bitvaue Nos OO Scheduler Jooo Round robin schedule to all HUMI devices Character LCD HUMI character LCD only output Reserved Do Not Use 5 3 1 3 Switches SYS SW Reserved Qt8 J 0 e USER BUT 3 0 7 4 JRO h Always returns value of user buttons USER SW 3 0 3 0 JRO h Always returns value of user switches 5 3 1 4 LED s SYS LED Reserved Biese Returns value in register 118 LED on OLED of 5 3 1 5 20 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Programmer s model 5 3 1 6 Display output SYS 7SEG N
4. Character LCD the scheduler drives DUT HUMI SEGn to 4 b1110 and DUT HUMI LEDn high and enables the DUT LCD interface control lines Should any operation be in progress when the scheduler wishes to switch back to the LED then change is halted whilst the operation completes and any new operation is prevented from starting the CharLCD driver appears busy to the processor Signal Direction Width Comments BUTTON input 4 DUT DSW input 4 DUT HUMI An bi dir DUT HUMI Bn bi dir DUT HUMI Cn bi dir DUT HUMI Dn bi dir DUT HUMI En bi dir DUT HUMI Fn bi dir DUT HUMI Gn bi dir DUT HUMI DPn bi dir DUT HUMI SEGn output 4 DUT HUMI LEDn output DUT LCD REGSEL output DUT LCD RW output DUT LCD ENABLE output 10 1 2 3 FPGA Configuration connections These connector is not used by the design but for FPGA configuration only Signal Direction Width Comments DUTFCP CLK input DUTFCP DATA input DUTFCP PLTXT RDY input 10 1 2 4 SEMULATOR connections The SEmulator connector is not used by this design For further details please refer to the MPB User Guide 1 Signal Direction Width Comments SEDUT L4 RXN input 4 SEDUT L4 RXP input 4 SEDUT L4 RXCLKN
5. 10 1 2 1 Clocks and Resets see section 3 2 Signal Direction Width Comments ee ee i USER RESETn input HPE RESETn input DUT CLKI input AHB system clock input DUT CLK4 input Video Pixel Clock input DUT CLKI10 input Peripheral reference clock input DUT_CLK13 input AACI bit clock input DUT_CLK100M input Reference 100MHz input DUT PLL B1 CLKOUT3 output 25MHz reference clock from FPGA PLL DUT PLL R2 CLKOUTO output AACI 24 576MHz bit clock x2 from FPGA PLL DUT PLL T1 CLKOUT3 output Video Pixel Clock from FPGA PLL 10 1 2 2 LED and switch connections Please refer to section 5 3 for details on driving this interface The buttons and switches can be read via the register SYS SW see section 5 3 1 3 The values held in the SYS LED and SYS 7SEG registers see sections 5 3 1 4 and 5 3 1 5 are driven onto this interface based upon the value held in the HUMI MODE field in the SYS PERCFG register see section 5 3 1 2 The scheduler runs at a preset rate of 500Hz and selects a new driver for the data lines DUT_HUMI_ A G DP n every 2 ms if the HUMI MODE field is set to Scheduler 8 b000 The order of the cycle is LEDs selected the scheduler drives DUT HUMI LEDn low Segment 0 the scheduler drives DUT HUMI SEGn to 4 b1110 Segment 1 the scheduler drives DUT HUMI SEGn to 4 b1101 Segment 2 the scheduler drives DUT HUMI SEGn to 4 b1011 Segment 3 the scheduler drives DUT HUMI SEGn to 4 b0111 ARM DAI0218A Signal assignments
6. List commands Performs a read modify write of memory at address combining in with value which will be masked with masks The size of the transfer can be optionally specified it can be BYTE HALFWORD or WORD defaults to WORD Alias for EXIT Starts a timer which is stopped with the STOP TIMER command Application Note 218 ARM DAI0218A STOP TIMER Example software Stop a timer pervious started with the START TIMER command and displays elapsed time 9 1 4 Boot Monitor NOR Flash Submenu Commands Command Format DISPLAY IMAGE lt name gt ERASE IMAGE lt name gt ERASE RANGE start address lt end_address gt EXIT HELP LIST AREAS LIST IMAGES LOAD lt name gt QUIT RESERVE SPACE lt address gt lt size gt RUN lt name gt UNRESERVE SPACE lt address gt WRITE BINARY lt file gt NAME lt name gt FLASH_ADDRESS lt address gt LOAD_ADDRESS lt address gt ENTRY_POINT lt address gt Application Note 218 ARM DAI0218A Note Display details of image lt name gt Erases image or binary file from flash It is only possible to erase entire blocks of flash Therefore the entire block of flash that contains lt start_address gt the block that contains lt end_address gt and all intervening blocks will be erased This may mean that data before lt start_address gt or after lt end_address gt will be erased if they are not on block boundaries If the optional lt end_addr
7. CAN STB 10 1 2 12 Flexray Interface This interface is not driven in the example design supplied Signal Direction Width Comments FLEX BGE bi dir FLEX EN bi dir FLEX ERRn bi dir FLEX RXD bi dir FLEX RXEN bi dir FLEX STBn bi dir FLEX TXD bi dir FLEX TXEN bi dir 50 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Signal assignments FLEX WAKE bi dir 10 1 2 13 LIN Interface This interface is not driven in the example design supplied Signal Direction Width Comments LIN RXD bi dir LIN TXD bi dir LIN SLPn bi dir LIN ACTIVE bi dir 10 1 2 14 RS232 connections These interfaces are driven by the Primecell PLO11 see section 5 3 10 There are three UARTs in the example system connected to the DUT FPGA Interface RSO connects to UART 1 UARTS 2 and 3 are connected to the UART ports RS232 1 and RS232 2 on the baseboard respectively RSO_xxx_MIDI and RS1 xxx MIDI Signal Direction Width Comments RSO RXD LVTTL input RSO TXD LVTTL output RSO CTS LVTTL input RSO RTS LVTTL output RSO RXD MIDI input RSO TXD MIDI output RSI RXD MIDI input RSI TXD MIDI output Application Note 218 Copyright 2009 ARM Limited All rights reserved 51 ARM DAI0218A
8. RTL All of the RTL for this design is provided as Verilog or precompiled netlists Example files are provided to allow the system to be rebuilt with the Altera Quartus Il tools The readme files provided with the application note show the version of the tools used to build the design Directory structure fpga cpu peripherals Figure 13 Top Level Directory Structure The application note has several directories e docs Contains related documents including this document e fpga_cpu Contains a precompiled encrypted image for the processor FPGA in the design which contains the processor and the local peripherals e fpga dut Contains the verilog RTL files which describe the structure and design of the example system e software Example software and utilities specific to the application note e peripherals Contains the verilog RTL or precompiled images of the peripherals used in the fpga_dut design Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A RTL 6 2 The fpga dut Directory fpga dut scripts Figure 14 Directory Structure within fpgu dut Directory The fpga_ dut directory contains the Verilog required for top level of the example customer system This is in the directory logical verilog and includes e The top level of the system which contains the IO instantiations and clock reset sources This is also a wrapper for the main top level logic module Th
9. 0 by nSDAOUTEN going to MH 10 1 2 9 DDR17 Interface This interface is not driven in the example design supplied Application Note 218 Copyright 2009 ARM Limited All rights reserved 49 ARM DAI0218A Signal assignments Signal Direction Width Comments MEM DDR2 ADDR output 15 0 MEM DDR2 BA output 2 0 MEM DDR2 CASn output MEM DDR2 RASn output MEM DDR2 WEn output MEM DDR2 CSn output 1 0 MEM DDR2 ODT output 1 0 MEM DDR2 CKE output 1 0 MEM DDR2 CLKP output 1 0 MEM DDR2 CLKN output 1 0 MEM DDR2 DM output 3 0 MEM DDR2 DQSN bi dir 3 0 MEM DDR2 DQSP bi dir 3 0 MEM DDR2 DQ bi dir 31 0 MEM VAR bi dir 23 0 Not connected in this design 10 1 2 10 Ethernet Phy Interface This interface is not driven in the example design supplied Signal Direction Width Comments ETH COL bi dir ETH CRS bi dir ETH MDC bi dir ETH MDINTRn bi dir ETH RESETn bi dir ETH RXCLK bi dir ETH RXD bi dir 3 0 ETH RXDV bi dir ETH RXER bi dir ETH TXCLK bi dir ETH TXD bi dir 3 0 ETH TXEN bi dir ETH TXER bi dir 10 1 2 11 CAN Interface This interface is not driven in the example design supplied Signal Direction Width Comments CAN RXD CAN TXD
10. 8 RESP READY RESETn NTO NT1 T jae bong Gong gord Go nd paed Kaet EE rasa Fasi Faea Paea Fasa Fad Faod Faod PAU un m mm zzz EN z 1 ELLE ed ed LI El LE NYA OI IN oo z r9 r10 r11 Lr12 r13 r14 r1i5 r16 r17 r18 r19 zz zzz q N NT22 23 z s DEOCLK DEOO DEO1 1 DEO2 1 DEO3 1 DEO4 1 DEO5 1 DEO6 1 DEO7 1 CLK SISISIS UO S g iab Direction PGA IC 91 DATA12 PGA IC 98 DATA19 S gt M M gt S UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc UT gt Proc Tes U Proc OIOIOIOIOIIOIO OJICIOIZIOIZIZIZIZIZI2IZI2ZIZIZIZI 2I 7o OI UO UO These signals are driven by DDR registers clocked by VIDEOCLK and are arranged in the same way as the signals are driven off the CPU FPGA 40 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Signal assignments 8 9 10 11 12 PGA 58 d L14 DUTO L14 DUTO L14 DUTO L14 DUTO L14 D L14 CP L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C L14 C C d i H H C d C d U u u u u C o C Gi H O x U C C Uju c
11. Limited All rights reserved 27 RTL a ds700 charlcd JA verilog Ch h a gt D Q Q Q sch g TQ pl011 uart pl022 ssp pl031 rtc peripherals sp804 timer sp805 watchdog verilog verilog verilog pl041 aaci il J Figure 15 Directory Structure within peripherals Directory 6 4 Building the application note Building the Application Note requires the running of a single batch script This script invokes the Altera Quartus tools to perform both synthesis and place and route functions Once this script has completed the sof can be download into the DUT FPGA The script for creating the new image is found in the MPS directory fpga_dut physical mpb_dut altera scripts build bat This will recreate the existing DUT FPGA design The resulting sof file will be in fpga_dut physical mpb_dut altera netlist foga_dut sof This is the file to be programmed into the FPGA by the Hpe _desk application See the Hpe _desk user Guide for details on downloading and configuring Note you require the Altera Quartus Il 8 0sp1 Web Edition or later to rebuild this image for the FPGA 28 Copyright O 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Functional testing 7 Functional testing 7 1 Self test 7 1 1 Functionality The selftest code allows the user to confirm the functionality of their Microcontroller Prototyping System and provides a starting point for writing end code to make us
12. N AEA EEA N EENAA Enana aasa 32 9 1 Boot Monitor User Interface ccccssssssssscsscsssescssssssscsssnessssssscesssssnscsssnsssssnescessossossossnessssncssesscssossossnessssnessesooss 32 92 Peripheral Support cccissisiczecssoccesecseceessastesebde M 36 9 3 Hardware Requirements sssenseenenneenennenenenenenenenenenenesnnnensensensnessensesse 38 94 To ET TA M 38 9 5 M ltiprocessing rss ennesnnmerenstsnsnnen riens sses o osos ossi eos sns sosio sssr soosoo ossetere sran eosto eies otso isS 39 o P ES A L E E A T EAEE E EEE TTA R EEES 39 9 7 Platform Library Initialization ss ssssssssnsssssssssssssesssesnsnsenenenenenensenennsesesneeeenenssessnsesse 39 9 8 Memory Management amp Caches sessssesorsesesecccoesoroesesecceeesorsesesecoeoeserecoeeororoeserecoeeororsesesoeresoroeserecoeseeoeeororseseseseesoroesee 39 9 9 Building the Firmware 4 eeeeeee eese eee een enses ense teo eP noS ta sons Eserin ooa Oue sone ta sns tasses suse tosta sees sos Eee eta COENE Seat 39 10 SIGNAL ASSIGNMENTS 3222735525 rir inn orn so inn oan n Enn ore Soon naa Eain 40 10 1 Interface between the CPU and DUT FPGAS e eeeeeeeeeee eee ee eene enata enses suse ta sone ta sens tastes sosta sse tassa senses enses ens 40 Application Note 218 Copyright 2006 ARM Limited All rights reserved V ARM DAI 0125A Introduction 1 Introduction 1 1 Purpose of this
13. On Pixel Clock Falling Edge Red CLD 7 0 Green MSBs CLD 23 20 10 1 1 7 SEMULATOR Connector Signal Direction Width Comments SECPU LA RXI input Not Connected SECPU L4 RX2 input Not Connected SECPU L4 RX3 input Not Connected SECPU L4 RXCLK input Not Connected SECPU LA TXI input Not Connected SECPU L4 TX2 input Not Connected SECPU L4 TX3 input Not Connected SECPU L4 TXCLK input Not Connected SECPU RESETn input Not Connected 10 1 1 8 Human Interface Switches and LEDs Signal Direction Width Comments CPU DSW input 7 0 Read via System register SYS SW CPU LED output 7 0 Set via System Register SYS LED 10 1 1 9 CPUFCP Interface Signal Direction Width Comments CPUFCP CLK input Not Connected CPUFCP DATA input Not Connected CPUFCP PLTXT RDY input Not Connected 10 1 1 10 JTAG Connector CPU Signal Direction Width Comments Application Note 218 Copyright 2009 ARM Limited All rights reserved 43 ARM DAI0218A Signal assignments FTSH_GNDDET bi dir Connector Detect Weak pull up on FPGA which is pulled low by the connector to indicate a connection FTSH_TMS bi dir Input to SWDIOTMS on processor Also used as Data Out for Serial Wire Debug FTSH_TCK bi dir JTAG Clock to processor FTSH TDO bi dir JTAG Data Out from processor FTSH TDI bi dir JTAG Data In to
14. Overview of the hardware platform eee eee eee eee eese enses tn sins tn stato sees tn seta reoni seta sse seeto eieo suse ta sene eias sereis 1 2 GETING STARTED 53 giri en RIS E UU Rav s DURAN RI NEU Ee DC MER QUI AON DUNS dune ensuite 3 MEME giri EC 3 2 0 Software download to MPS eee ee eee esee esses thats enses tuse ta sn sn seta sse ta sens tasses ioannis ieas eeso rasiko ose avoas 3 2 3 FPGA Image download to MPS eee eee esee esee ee eese en testes tuse ta sns ta sens tn ses tosta sees tosta sse ta sense tasse ta irises tissosa 3 ZA Clock control of MBS i ssc csccsssscessectectesesessvasscsaccacstssescsossescesisvessssaisesssseisscnasasdasendacastaodcssesessesuebs oscdtacsedudseivadcscesssapiestoedses 4 2 5 Rebuilding the DUT FPGA 4 3 ARCHITECTURE nn nn idu ibtd biet Dhu nl tn li ne dll dis aaae 5 3 1 Block Dia Sra sesiis isss eicere dete eo it eeu cocaenststusaobsaseasietessaactsaseokshssesesabseseshsepachoactucsedunteessoacsaasccsstsesvassesasosaseenteedens 5 MEE Geist Suaia 10 X EB irirawuihiscivenirceriiu rc 13 SA Debug architecture C 13 3 5 Processor Implementation Architecture ssssssssssseseneeneneenenenenerenesenensenesenenensese 13 4 HARDWARE DESCRIPTION anna rte niet eaaa
15. TOUCH SPI DIN input Connects to TS DIN TOUCH SPI DOUT output Driven by TS DOUT TOUCH SPI IRQ input Connects to TS INTn 10 1 1 6 VGA DVI Controller Signal Direction Width Comments VIDEO CLK output Driven by Pixel Clock from Video PL111 from DUT VIDEO D output 11 0 Driven by DDR registers see table below VIDEO DATA EN output Driven from Video PL111 CLAC Data Enable VIDEO HPINT input Not Connected Hot Plug Interrupt VIDEO HSYNC output Driven from Video PL111 CLLP Horizontal Sync signal VIDEO DC SCL output Clock driven by DS702 peripheral in CPU FPGA Figure 16 VIDEO DC SDA bi dir Data driven by to DS702 peripheral in CPU FPGA Figure 16 VIDEO MODE input Not Connected Video mode VIDEO RESET output Driven by reset synchronized to Pixel Clock VIDEO SPARE output Not Connected VIDEO VSYNC output Driven from Video PL111 CLFP Vertical Sync signal 42 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A SDA SCL VIDEO_I2C_SCL Driver nSDAOUTEN 1 b0 VIDEO I2C SDA Tri stated driver Figure 16 Video I C Connections Signal assignments 10 1 1 6 1 Video DDR Assignment 11 8 7 0 On Pixel Clock Rising Edge Green LSBs CLD 19 16 Blue CLD 15 8 11 413 0
16. application note This application note covers the operation of the Hpe amp midiv2 with the HM ALC AS3 from Gleichmann Electronics Research It describes the contents of the FPGAs on the HMALC AS3 52 the system interconnect the clock structure and specifics of the programmer s model relevant to Customer FPGA s operation After reading this Application Note the user should be in a position to make changes to the customer FPGA design provided or introduce their own AHB based peripherals 1 2 Overview of the hardware platform Application Note 218 ARM DAI0218A This application note is designed to work on the Microcontroller Prototyping System as shown in Figure 1 fitted with the ARM Hpe amp module as shown in Figure 2 This application note is intended for the processor FPGA to be installed with the ARM Cortex M3 image For further details on this system please see 1 ru HPE rs Microcontroller Prototyping System ARM Power FPGA Config 9 LIES E PA xb Figure 1 Microcontroller Prototyping System Copyright 2009 ARM Limited All rights reserved 1 Introduction Figure 2 ARM HPE Module 2 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A 2 2 1 sw1 ON OFF X X X X 2 2 2 3 Application Note 218 Getting started Getting started The system comes pre configured with an example design installed on the customer FPGA The processor FPGA is con
17. auto detection of semihosting or UART port3 for console interface SW3 Function Note X Normal boot Use this as default X Run boot Script This needs to be pre configured from the boot monitor command line ON Auto Select between UART port3 Detects semihosting supported debugger and Semihosting for Console OFF Force UART port3 for Console Always use UART port3 regardless of semihosting support ON Reserved Do not use undefined behaviour OFF Reserved Do not use undefined behaviour Software download to MPS The MPS comes with a Keil ULINK2 USB JTAG adaptor to allow download and programming of the Flash memory from Vision The ULINK2 plugs into the 20way IDC connector at the back of the unit Example software and projects are supplied for p Vision See the Vision documentation for details about how to compile and program the flash If you do not use the JTAG download it is possible to transfer files and write them into flash using bootmonitor and the SD card slot It is possible to fit a SDCard or MMC into the SD Card slot in the back and access it as a standard FAT16 8 3 filename device long filenames are not supported and the maximum usable card size is 2GB FPGA Image download to MPS ARM DAI0218A The HPE Desk application Windows based from Gleichmann allows you to download new FPGA images for the DUT FPGA and updates from ARM for the CPU FPGA when available Please see the Hpe amp desk documentation for details on how to do th
18. for example Function Direction TAO HWDATA4 DAT HWDATA5 M z 2 eta E ATA6 M a 1 N mim Le 1 w E p EN is C 4 i C 4 i Jg Z Interface between the CPU and DUT FPGAs Bus Function PGA 90 ltd afaa X PGA 93 sd he Xl ajajaja aja Ij PGA 104 PGA 106 PGA 109 PGA IT PGA 113 PGA LT PGA 120 PGA 122 125 aja 201 39 3 ILLIS x zi 1 1 F3 F3 Kel od ez rz rz r3 P f Qj ojajararmnrmnanajjnujaeuealmnuenuoJn TA A 2 alalalalala zj Q D Cyc Be rem CIO Cic il 11H OjO GIc il 11H UJU zz E p e gio i is Z C E ejeje NESES UO C j 4 O O C UO a zzz UO C E 4 O C 3 a Z E p P is C 4 i 4 i Jg Z E p eS is i C i Jg Z E C E E e D UO UO C 1 4 j j O O C UO UO 2 2 blblhlololslalul wlnlH e U Ie E p e is C 4 i C 4 i E p e is a 4 i C 4 E p e is 4 i 4 i E p e is C 4 i C 4 Ae Lm H H DS DS is C 4 3 4 4 O C C 3 3 j El O O O O O GIO OIAa UJ UJ U UJ U UJ UI L U C C i SJIAIUIH wWINIHIo U U C C i HRDATA11 T mimimim eil T DATA2
19. input SEDUT L4 RXCLKP input SEDUT L4 TXN input 4 SEDUT L4 TXP input 4 SEDUT L4 TXCLKN input SEDUT L4 TXCLKP input SEDUT RESETn input Application Note 218 Copyright 2009 ARM Limited All rights reserved 47 ARM DAI0218A Signal assignments 10 1 2 5 USB Interface This interface is driven by a dedicated interface driver which is designed to drive the NXP ISP1761 USB controller 14 The interface driver is not configurable and is transparent to the rest of the system Signal Direction Width Comments USB A output 17 USB CSn output USB_RDn USB_WRn USB_D USB DC DACK Not connected in this design USB DC DREQ Not connected in this design USB DC IRQ Used as input only See interrupt table USB DC WAKEUPn Not connected in this design USB HC DACK Not connected in this design USB HC DREQ Not connected in this design USB HC IRQ Used as input only See interrupt table USB HC WAKEUPn bi dir Not connected in this design 10 1 2 6 Multi Media SD Card Interface This interface is driven by the Primecell PL181 see section 5 3 12 Signal Direction Width Comments SD SCLK output Driven by MCICLKOUT SD CD input See Figure 17 SD WRP input See Figure 17 SD CT output Pulled low to enable SD CD and SD WRP inputs SD IRQ bi dir See Figure 17 SD CSn bi dir See Figure 17 SD DAT bi dir See Figure 17 SD DI bi d
20. low signal SSRAMI CKEn output Clock enable signal Active low signal SSRAMI OEn output Output enable Active low signal SSRAMI LBOn output Burst Mode Control Active low signal Tied to 0 SSRAMI ADV output Address Advance Tied to 0 SSRAMI ZZ output Sleep request Tied to 0 10 1 1 17 FLASH connections This port is driven by a dedicated interface control block which is not configurable and is transparent to the system This block is responsible for controlling the multiplexing of the shared data and address lines for these devices Application Note 218 Copyright 2009 ARM Limited All rights reserved 45 ARM DAI0218A Signal assignments Signal Direction Width Comments FLASH WEn output Write enable Active low signal FLASH RESETn output Memory reset Active low signal FLASH CEn output Chip select Active low signal FLASH OEn output Output enable Active low signal FLASH WPn ACC output Not Write Protect Access signal Tied to 1 No write protection 1s available on this interface FLASH RD BYn input Ready Not Busy input Not connected 10 1 1 18 RS232 connection These interface is driven by the Primecell PLO11 see section 5 3 10 There is one UART in the example system connected to the CPU FPGA Interface RS1 connects to UART 0 Direction Width RS TXD LVTTL output 10 1 2 Other DUT FPGA interfaces
21. processor FTSH TRST bi dir JTAG Reset This is an active low signal 10 1 1 11 JTAG Connector Shared Signal Direction Width Comments INTCPU TDI input JTAG Data In to processor INTCPU TDO bi dir JTAG Data Out from processor INTCPU TCK input JTAG Clock to processor INTCPU TMS input Input to TMS on processor This is not connected to the Serial Wire Debug Data Out INTCPU TRSTn input JTAG Reset This is an active low signal INTCPU SRSTn input Factored into CPU reset INTCPU RTCK output Not connected INTCPU DBGRQ input Not connected INTCPU DBGACK output Not connected 10 1 1 12 MICTOR Connections Signal Comments o MICTOR PIPESTATO output Tied to 0 MICTOR PIPESTATI output Tied to 0 MICTOR PIPESTAT2 output Tied to 0 MICTOR EXTTRIG output Tied to 0 MICTOR_TRACEPKT output 15 0 Bits 3 0 carry the TRACEDATA port from the processor Bits 15 4 are tied to 0 MICTOR TRACESYNC output Not connected MICTOR TRACECLK output Connects to processor TRACECLK port 10 1 1 13 SSRAM Shared Connections Signal Direction Width Comments SSRAM CLK output Driven by processor bus clock 10 1 1 14 SSRAM 0 Connections This port is driven by a dedicated interface control block which is not configurable and is transparent to the system Signal Direction Width Comments SSRAMO A output 19 0 Addres
22. shared between these devices are controlled by a multiplexer which is controlled by the interface controller for the FLASH RAM Signal Direction Width Comments SSRAMFLASH A output 23 0 Address to SSRAM FLASH SSRAMFLASH DQA bi dir 7 0 Data lines 7 0 Byte lane 0 SSRAMFLASH DQB bi dir 7 0 Data lines 15 8 Byte lane 1 SSRAMFLASH DQC bi dir 7 0 Data lines 23 16 Byte lane 2 SSRAMFLASH DQD bi dir 7 0 Data lines 31 24 Byte lane 3 10 1 1 16 SSRAM1 Connections This port is driven by a dedicated interface control block which is not configurable and is transparent to the system Signal Direction Width Comments SSRAMI BWAn output Write byte lane 0 Active low signal SSRAMI BWBn output Write byte lane 1 Active low signal SSRAMI BWCn output Write byte lane 2 Active low signal SSRAMI BWDn output Write byte lane 3 Active low signal SSRAMI DQPA bi dir Byte lane 0 parity signal SSRAMI DQPB bi dir Byte lane 1 parity signal SSRAMI DQPC bi dir Byte lane 2 parity signal SSRAMI DQPD bi dir Byte lane 3 parity signal SSRAMI CSIn output Chip select 1 Active low signal SSRAMI CS2 output Chip select 2 Active high signal SSRAMI CS3n output Chip select 3 Active low signal SSRAMI WEn output Write enable Active
23. 009 ARM Limited All rights reserved Change history Issuer Gleichmann Industries Gleichmann Industries Altera Corporation ARM Ltd by Joseph Yiu ARM Lid ARM Ltd Chrontel ARM Ltd ARM Ltd ARM Ltd ARM Ltd ARM Ltd ARM Ltd ST NXP Wireless Application Note 218 ARM DAI0218A Proprietary notice ARM the ARM Powered logo Thumb and StrongARM are registered trademarks of ARM Limited The ARM logo AMBA Angel ARMulator EmbeddedICE ModelGen Multi ICE ARM7TDMI ARM9TDMI TDMI and STRONG are trademarks of ARM Limited All other products or services mentioned herein may be trademarks of their respective owners Confidentiality status This document is Open Access This document has no restriction on distribution Feedback on this Application Note If you have any comments on this Application Note please send email to errata arm com giving e the document title e the document number e the page number s to which your comments refer e an explanation of your comments General suggestions for additions and improvements are also welcome ARM web address http www arm com Application Note 218 Copyright 2006 ARM Limited All rights reserved ARM DAI 0125A Table of Contents 1 INTRODUCTION pa N 1 11 Purpose of this application note 4 eee eee eerte eee enses tn seen tn setatis tasa tn stesso seta sone ta sensn sesso sees bs ossoss soss senatu sensn ess 1 12
24. 1 4 o UART 0 MCIb o o E co MCIa Timer 3 2 o RI Timer 1 0 o a RTC Wat chDog WatchDog Figure 8 Interrupt Allocation Table This interrupt structure is in addition to the 16 internal CPU interrupts on the Cortex M3 3 4 3 5 Application Note 218 ARM DAI0218A Debug architecture The example design provided with this Application Note is based on a simple JTAG debug architecture For the JTAG chain routing please refer to the Module User Guide 1 The Cortex M3 implementation contains an ETM which is connected directly to the trace MICTOR connector on the FPGA Module Processor Implementation Architecture The Cortex M3 processor has been implemented with the following functionality Function Implemented Details MPU Yes Interrupts yes 32 external IRQ s Error Bookmark not Copyright 2009 ARM Limited All rights reserved 13 Architecture defined Priority Yes 3 bits 8 levels Trace yes Full debug including data matching JTAG amp SWD Yes Both JTAG and Single wire debug present Clock gating No No architectural clock gating implemented in design All registers reset No Not all registers are reset after system reset Internal observability No No internal observability implemented WIC No No WIC implemented SYSTICK Yes 100kHz reference clock implemented with divider to 10ms Pow
25. ART 1 UART 0 SD MMC Timer 3 2 Timer 1 0 RTC WatchDog VORADS is 0x6000 0000 Ox9FFF FFFF cashes VOPADS EEREEEE 52155 OxAO3F FFFF Switches LEDs config Figure 6 Bus Architecture of Customer DUT FPGA Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A 3 1 3 CPU FPGA functionality Bus Infrastructure components 32 bit AHB 2x1 Bus Mux AHB Decoder AHB Data Mux AHB to APB Bridge Memor ZBT RAM Controller Flash RAM Controller Peripherals Serial Bus I F Sync Serial Port System Regs UART 3 3 1 4 Customer DUT FPGA functionality Bus Infrastructure components Application Note 218 ARM DAI0218A AHB Decoder AHB Data Mux AHB to APB Bridge APB Decoder Architecture Provides the bulk of the interconnect structure It handles the contention between the Instruction and Data AHB busses of the processor when they access the local memory and peripherals This block implements the memory map for the CPU FPGA bus structure This block connects the Bus matrix to the AHB and APB peripherals It handles the returning data and responses from the peripherals The bridge contains the muxing and decoding scheme for the bus allowing the APB peripherals to be connected Controller for a ZBT zero bus turnaround RAM Allows the CPU access to the local fast RAM Controller for Samsung Flash NOR RAM Allows CPU ac
26. Application Note 218 Using the Cortex M3 on the Microcontroller Prototyping System Document number ARM DAI0218A Issued February 2009 Copyright ARM Limited 2009 Application Note 218 Using the Cortex M3 on the Microcontroller Prototyping System Copyright 2009 ARM Limited All rights reserved Release information The following changes have been made to this Application Note Date Issue Change February 2009 A First release Version controlled by Domino Doc DS158 GENC 009371 2 3 References Document 1 User Manual for HMALC AS3 52 2 HPE_Desk Basic Online Help 3 Altera Double Data Rate I O Megafunctions User Guide 4 The Definitive Guide to the ARM Cortex M3 ISBN 978 0 7506 8534 4 5 PrimeCell Synchronous Serial Port PLO22 Technical Reference Manual 6 Cortex M3 User Guide ARM DUI 0450A 7 CH7303 HDTV DVI Transmitter CH7303 Data Sheet 8 ARM Dual Timer Module SP804 Technical Reference Manual 9 PrimeCell Real Time Clock PLO31 Technical Reference Manual 10 ARM Watchdog Module SP805 Technical Reference Manual 11 PrimeCell UART PLO11 Technical Reference Manual Revision r1p5 12 PrimeCell Advanced Audio CODES Interface PLO41 Technical Reference Manual 13 ARM PrimeCell Multimedia Card Interface PL181 Technical Reference Manual 14 ISP1761 Hi Speed Universal Serial Bus On The Go controller Rev 05 13 March 2008 Product data sheet ii Copyright 2
27. D 0000 Ox4FFC 0000 0x8000 0000 Ox4FFB 0000 Ox4FFA 0000 0x7000 0000 Ox4FF0 0000 0x6000 0000 16x 64kB AHB peripherals 0x4000 F000 0x5000 0000 0x4000 E000 0x4000 D000 0x4000 0000 0x4000 C000 16x 4kB APB peripherals 0x4000 B000 0x4000 5000 0x3000 0000 0x4000 A000 0x4060 401C 4000 4018 0x4000 9000 0x2000 0000 0x4000 8000 0x4000 7000 0x4000_4014 Int ROM Exec 0x1000 0000 0x4000 6000 0x4000 4010 0x4000 5000 0x4000 400C Int ROM Exec 0x0000 0000 0x4000 4000 0x4000 4008 0x4000 3000 0x4000 4004 0x4000 4000 0x4000 2000 0x4009 1000 0x4000 0000 MPB M3 DUT FPGA Figure 10 DUT FPGA memory map 5 2 CPU FPGA specific registers 5 2 1 System Registers The system registers are based at address 0x1F00 0000 Register Offset Access Reset Note 5 oO SYS D hooo RO hi0230b BoardandFPGAidenWier SYS SW R0008 RO RO00000 Indicates user switch settings SYSTS hooro AO h00000000 TouchScreen register 5 2 1 1 ID register SYS ID Name Bis Access Reset Note O REV pra RO hi BoadRevsonB O O BOARD 27 46 RO ha HBlBoadnumer VARIANT 15 12 RO ho Build Variant of board ARCH 11 8 RO h4 Bus Architecture 4 AHB 5 AXI BUILD 7o RO J m FPGA build Application Note 218 Copyright 2009 ARM Limited All rights reserved 17 ARM DAI0218A Pr
28. I controller Copyright 2009 ARM Limited All rights reserved 37 Example software 9 3 Hardware Requirements The firmware depends on various hardware facilities to be available to be able to provide its functionality 9 3 1 Platform Library The following items are basic requirements of the platform library without which a complete implementation would be difficult e UART The default output for the C libraries standard I O will normally be the first UART in the system This UART is also use to output error messages when it is not possible to output them to the selected standard output device e 100Hz Counter This is used to provide the clock function in the C library having this counter removes the need to use a general purpose timer and allows a basic library to function without the need for interrupts e PrimeCell Real Time Clock RTC This is used to provide the time function in the C library e The RTC during system initialization will be set to zero e 25MHz Counter This is used to implement a general purpose delay routine which is used by a number of components within the firmware The following items enhance the functionality of the platform library but are not requirements in fact in the case of the LCD and keyboard the platform library can be built without this support e LEDs The firmware cycles the CPU LED s when running standalone to show that the board is running correctly e The followin
29. INT lt address gt name as the specified binary file but with the exe file extension COPY lt file1 gt lt file2 gt Copies file lt file1 gt to lt file2 gt 32 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A CREATE lt file gt DEBUG DELETE lt file gt DIRECTORY lt directory gt DISPLAY BOOTSCRIPT ECHO lt text gt EXIT FLASH HELP lt command gt LOAD lt image gt MKDIR lt directory path gt QUIT RMDIR lt directory path gt RENAME lt file1 gt lt file2 gt RUN lt image gt SDCARD SET BOOTSCRIPT lt script gt TYPE lt file gt Application Note 218 ARM DAI0218A Example software Create a file lt file gt Enter Debug Submenu Delete a file lt file gt List files in lt directory gt Display the current boot script Prints string lt text gt Exits the application or submenu Enter Flash Submenu Provides help information on command If command is not specified then all available commands are listed Loads image image into memory Creates a new directory at the end of the given path Alias for EXIT Removes a directory at the end of the given path Renames file lt file1 gt to lt file2 gt Load image image into memory and run it Enter SDCard Submenu Set the current boot script This script will be run at system reset if the run boot script switch is set Displays file lt file gt Copyright 2009 ARM Limited All ri
30. Oupubis 5 2 2 1 SB Status register SB CONTROL Name Bis Access Rest Noe Reewed i2 SBSDA JO b LewioSDAsgm sss p Ro Jo level of SCL signal 5 2 2 2 SB Set register SB CONTROLS Sets SDA line when 1 Sets SCL line when 1 18 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Programmer s model SB nSDAOUTEN w bo Clears SDA line when 1 SB SCLOUT o gt W bo Clears SCL line when 1 5 2 2 4 Basic Timing The basic I2C timing diagram is shown below The ACK is a returned value from the target device responding to a data burst being received CB SDA MSB Y Y X LSB ACK j o CB_SCL Start Stop Figure 11 12C Timing Diagram 5 2 3 Touchscreen The Primecell PLO22 is used to drive the touchscreen interface This interface has a base address of Ox1F00 4000 5 5 3 Customer DUT FPGA Specific Registers 5 3 1 System Registers The DUT specific registers are mapped to a 16KB area at 0x4000 4000 The addresses in this section are all relative to this base address Register jOfiset Access Rest Note SYS ID h0000 h102304xx Board and FPGA identifier SYS PERCFG h0004 RW h00000000 Peripheral control signals SYS_ Indi i i S RW RW h00000000 Sets LED outputs Free running counter incrementing at 100Hz No ARCH fs RO fm JBusArhiecue 4AHB O BUILD
31. Reset Routing Name PWR_RESET USER_RESET HPE_RESET Table 2 Reset Routing Source Destination Note BB CF O D output from supply monitor internal use All CF CPU DUT Push button on Processor board O D CF BB DUT Driven by USER_RESET and PWR_RESET Notes BB BaseBoard CF Clock Factory CPU CPU FPGA DUT DUT FPGA OSC Crystal Oscillator module The System only uses the USER_RESET signal and this drives all internal resets nPOR nHRESET etc The design ignores PWR_RESET and HPE_RESET The CPU FPGA drives the nHRESET signal between the CPU and DUT FPGA to create a synchronous reset with respect to HCLK in the DUT FPGA The DUT FPGA uses this to resynchronise resets to all other clock domains within the FPGA 3 2 3 Clock and Reset Destinations Device CPU AHB APB infrastructure SMC ZBT amp NOR UART SPI 12C VIDEO AC97 SD MMC Character LCD 7SEG Display Timer Real Time Clock Watch Dog USB Static Memory Clock Freq Clock ref Reset ref Note HCLK CLKip HRESETn HCLK CLK1p HRESETn Runs as CPU frequency HCLK CLK1p HRESETn CPU FPGA memory controllers and I F to USB IC 25MHz CLK10p HRESETn PLO11 25MHz CLK10p HRESETn PLO22 HCLK CLK1p HRESETn DS702 23 75MHz CLK4p HRESETn Video LCD controller pixel clock 12 288MHz CLK13p HRESETn PL041 25MHz CLK10p HRESETn PL181 HCLK CLKip HRESETn DS700 HCLK CLKip HRESETn TBD 1MHz CLK10p HRESETn SP804 1Hz CLK10p HRESETn PLO31 1Hz CLK10p HRESETn
32. SP805 HCLK CLKip HRESETn External IC ISP1761 HCLK CLK1p HRESETn Memory controller on DUT FPGA Table 3 Clock and Reset Destinations All the peripherals that have an AHB or APB interface have that interface running at CLK1p CLK100M is used to derive all peripheral clocks where appropriate since this is a non variable clock and ideal for timers watchdogs etc The Reset column refers to the reset signal that is re synchronised to the respective clock domain Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A 3 3 PLO22 PLO11 3 Reserved Reserved MPB M3 Interrupt Reserved Architecture Interrupt architecture The interrupt controller for the Cortex M3 implementation is integrated into the processor but the mapping of peripheral to interrupt is irrespective of the controller implementation Figure 8 describes which interrupt is driven by each peripheral Cortex M3 has an NMI input so INT 0 from the following interrupt table driven by the watchdog timer peripheral is also routed to NMI on the Cortex M3 processor SPI touchscreen UART 3 o Es Ext touchscreen n Qo I2C DVI v w PON c c c w w Ba D 3 oo I2C ADC DAC co Qo LIN co M CAN co f Flexray co o Reserved Reserved Character LCD o USB HC d co USB DC Ethernet CLCD combined Int AACI AC97 d UART 2 UART
33. ame Es Access Reset Note DisPs 5124 RW hoo Segmenisordisplay 3 DISP2 23 16 RW h00 Segments for display 2 DISP1 15 8 RW hoo Segments for display 1 DISPO Segments for display 0 Disp3 Disp2 Disp1 DispO GOT Figure 12 7 Segment Display Segment Identification 5 3 1 6 1 The bit relationship to segment Name Ne DP p ris Deomal Ponton Ois Decimal Ponto G be iissegmeton0isegmetof D 3 X tissegmenton 0 is segment off C 2 tis segment on 0 is segment off B ft tissegmenton 0 is segment off A 0 tis segment on 0 is segment off 5 3 1 7 25MHz Counter SYS_CNT25MHz Count25MHz h00000000 Free running counter from 25MHz clock 5 3 1 8 100Hz Counter SYS CNT100Hz Name Access Reset Count100Hz 31 0 RO J h00000000 Free running counter from 100Hz clock 5 3 2 ADC DAC I2C The DS702 peripheral is used for the interface and implements a bit banging method for the I2C interface The base address for this peripheral is 0x4000 B000 Please see section 5 2 2 for details of registers Application Note 218 Copyright 2009 ARM Limited All rights reserved 21 ARM DAI0218A Programmer s model 5 3 3 Character LCD The Character display component is the DS700 and interfaces to the industry standard Hitachi HD44780 controller It uses 11 signals 8 data 1 strobe E read write RnW and Register data select RS N
34. ary which handles the initial system initialization therefore any application that is built with the platform library or handles it own initialization could replace the boot monitor It supports the following functions General file operations Programming images into flash Loading and running another application Board configuration e Asemihost server that with handle standard ARM semihosting SWI s e Flash Support The code that is used by the boot monitor and NFU to program flash can be incorporated into a user application and is supplied in source form e MMC FAT support 9 1 Boot Monitor User Interface The Boot Monitor command interpreter accepts user commands from the debugger console window or an attached terminal and carries out actions to complete the commands 9 1 1 Boot Monitor Main Menu Commands Command Format Note ALIAS alias command string Create an alias command alias for the string of commands in command string CD directory path Change directory to the one specified in directory path CLEAR BOOTSCRIPT Clear the current boot script If no boot script is set then the boot monitor will always prompt for input no matter what the state of the run boot script switch CONFIGURE Enter Configure Submenu CONVERT BINARY lt binary file gt Adds information required by the RUN command to execute LOAD ADDRESS address a binary file The command will produce a file with the same ENTRY PO
35. cess to the local Flash RAM Controls the detection and configuration of the DVI transmitter IC ARM Primecell PLO22 Synchronous Serial Port Used to interface to a touch screen controller Set of registers for configuration and control of the CPU FPGA For a complete list of the functionality of these registers refer to section 5 2 1 of this application note ARM PrimeCell PLO11 Universal Asynchronous Receiver Transmitter interfaces RS 232 serial Used by the Boot Monitor as default This block implements the memory map for the DUT FPGA bus structure This block connects the Bus matrix to the AHB peripherals and the APB bridge It handles the returning data and responses from the peripherals The bridge contains the muxing and decoding scheme for the bus allowing the APB peripherals to be connected This block implements the memory map for the DUT FPGA APB bus structure This decoder assumes that the AHB Copyright 2009 ARM Limited All rights reserved 9 Architecture 3 2 Peripherals Serial Bus I F AACI Character LCD MCI Real Time Clock System Regs Timers 0 1 UARTs 0 2 Watchdog Clock architecture decoder has selected the APB region of the memory map Used as an ADC DAC interface ARM Primecell PLO41 Advanced Audio Codec Interface Controller for the Character LCD Provides a memory mapped register interface to the display ARM Primecell PL181 Multimedia Card Interface ARM Primec
36. ck diagram of the system consisting of a CPU FPGA a Customer DUT FPGA peripherals and a Human Interface Block Human Interface LCD connector Q 0 0 EN E EI HE 12V Power Supply Customer DUT CPU Stratix3 Stratix3 Reset EP3SL50 C2 EP3SL50 C2 To PC ALTERA USB Blaster Clock Factory FLASH Handler Common Conf FLASH 780 pin fpBGA Hpe_child Connector DDR possible Figure 3 MPB System Block Diagram Application Note 218 ARM DAI0218A Copyright 2009 ARM Limited All rights reserved Hpe module Connector Hpe module Connector 780 pin fpBGA JTAG SEmulator 10 pin flat ribbon FLASH 128 Mb 32 MICTOR Architecture m M plemente d e e e e e Not Implemented e e e BaseBoard UART Switches LEDs Switches LEDs 7SEG Processorboard Trace Debug Ethernet C N Flexray Lin CPU FPGA Video oooooB2b552occc B SMB UARTS AC97 SD MMC 12C SPI MPB M3 Block Diagram I O Figure 4 Block diagram of the ARM Microcontroller Prototyping System Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Architecture Bus architecture 3 1 1 Bus Architecture of CPU FPGA The CPU FPGA implements an AHB bus infrastructure The bus matrix is used to give the processor access to the local FLASH a
37. cludes the Colour LCD and Video controller block user supplied Without this define the pixel clock is not driven and the data and control lines are tied to 0 Which means that the video bus will not drive any data or clock at all define VGA Implement the VGA Pattern Generator 640x480 if no CLCD present define SVGA Implement the VGA Pattern Generator 800x600 if no CLCD present define XVGA Implement the VGA Pattern Generator 1024x768 if no CLCD present define INCLUDE AACI This includes the Primecell PLO41 Audio Codec interface define INCLUDE MCI This includes the Primecell PL181 MMC SD interface define INCLUDE DMC This includes the DDR memory interface user supplied If these components are not included then the video and LCD controller does not have any route to memory so the address out of the video and LCD controller block is connected to the read data bus giving a static image on any screen attached to that interface Table 5 System Configuration Application Note 218 Copyright 2009 ARM Limited All rights reserved 15 ARM DAI0218A Programmer s model 5 Programmer s model 5 1 Memory map 5 1 1 CPU FPGA M3 memory area function 0x10000 0000 OxF000 0000 OxEO10 0000 OxEO00 0000 CPU FPGA OxD000 0000 0xC000 0000 0xB000 0000 0xAO000 0000 0x2000 0000
38. e name for example t images boot_monitor axf will be called boot_monitor and this can be overridden by using the option NAME argument You can specify where in flash the image is written by using the optional FLASH ADDRESS argument Note if the image is linked to run from flash then this address will be used and the FLASH ADDRESS argument will be ignored 9 1 5 Boot Monitor SDCard Submenu Commands Command Format Note FORMAT QUICK Formats the SDCard MMC as FAT16 with 8 3 filenames VOLUME lt label gt QUICK performs a quick format with only the FAT and bootsector updated VOLUME label will add a Volume label to the disk as specified in the field label INFORM Display details SD MMC Card INITIALISE If the card has been changed use this command to re initialise it to determine it s features before using any other commands EXIT Exit HELP List commands 9 2 Peripheral Support 9 2 1 NVIC Support for the Cortex M3 Nested Vectored Interrupt Controller is provided by the following functions in the platform library irq enable nVIC interrupt enable routine irq disable nVIC interrupt disable routine 9 2 2 DMC No support is provided for the Dynamic Memory controller 9 23 SMC Initialisation of static memory controller is provided in the initial boot code with no additional functions provided 9 2 4 Video LCD No support is provided for the video LCD controller 36 Copyright 2009 ARM Li
39. e of the MPB peripherals Selftest is a piece of diagnostic code for testing the following peripherals AACI MMCI USB UARTs character LCD LEDs switches SRAM memory RTC and system clocks interrupts Selftest is designed to run on the Keil Software Development System that is delivered with the Microcontroller Prototyping System The user can interact with the software operation via the debugger s console window The user interface displays a menu and prompts the user on how to operate each test For more information on exactly how each test is working refer to the provided code source and readme files 7 1 2 Compilation notes 7 1 3 Description A MicroVision project file is shipped as part of the selftest suite This project file can be used to rebuild the code with MicroVision A makefile is also provided so that automated builds can be run The selftest directory contains a suite of register level software tests for testing each of the MPB peripherals The code fragments used may also prove useful in developing demonstration code or OS driver ports The project and executable files for these tests can be found under the selftest build Build_Keil directory To complete the tests it is necessary to connect a number of loopback cables to the board see note below After connecting the test harness and loading the program image into the debugger selftest_mpb axf each of the MPB peripherals may be tested individually or alt
40. ell PLO31 Real Time Clock module Real time refers to total time from an event and not actual real world time Set of registers for configuration and control of the DUT FPGA For a complete list of the functionality of these registers refer to section 5 3 1 of this application note ARM ADK component SP804 ARM PrimeCell PLO11 Universal Asynchronous Receiver Transmitter interfaces RS 232 serial ARM ADK component SP805 is the watchdog controller It allows for the generation of an interrupt or reset after a defined time to prevent against system lockup failure The clock factory is a Gleichmann specific implementation and is treated as a blackbox with configuration performed by their software application 2 and the Altera Quartus II tools Figure 7 shows the clock and reset architecture for the system Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Architecture BaseBoard Processorboard A CPU_PLL_R2 L2_CLKOUTO MCBO B58 PWR RESET MCBO B60 USER RESET MCBO B62 HPE RESET amp MCBO 1 33 65 66 CLKO 1 Ex MOD DUT PLL R2 CLKOUTO Lo on TENAN CLK5p 15p CLK4p 13p CLK100M CLK1p 10p matched lengths DUT PLL T1 B1 CLKOUT3 CPU FPGA I L14 DUTCLK Diff USER RESET amp HPE_RESET L14 CPUCLK Diff MCBO B34 B2
41. er Management No The Sleep modes do not perform any clock stopping but will allow the WFI type functionality Multiprocessor No No support for multiprocessor communication Communication is implemented Table 4 Cortex M3 Configuration 14 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Hardware description 4 Hardware description 4 1 Top Level The top level of the DUT FGPA is foga_dut v This top level e Handles all the static tie offs e Maps the internal design signals to the board connections e Includes calls the header file which contains the configuration information for the example system e Instances any special IO cells the design requires e g the DDR registers for the Video connections The top level module instantiates the dut logic v module which in turn instances all the blocks in the example system and defines the interconnect between them 4 1 4 Configuring the Example System As an example of how to prototype a system too large for the Customer System FPGA the definitions file fpga dut defs v contains four defines which allow the system to be built without significant portions of the design to reduce size or improve performance By default the audio codec and MMC SD card interfaces are included but by un commenting or commenting out the following lines the system configuration can be altered Define Effect define INCLUDE CLCD This in
42. ess gt parameter is not specified then only the single block of flash that contains lt start_address gt will be erased Exit List commands List areas of flash where an area is one or more contiguous blocks that are of the same size and use the same programming algorithms List images in flash Load image lt name gt from flash Alias for EXIT Reserves space in flash for user applications that the boot monitor will not use Load image name from flash and run it Unreserves pervious reserved space in flash Writes a binary file to flash The image will be identified in flash by a name derived from the filename for example t images boot_monitor bin will be called boot monitor and this can be overridden by using the option NAME argument You can specify where in flash the image is written by using the optional FLASH ADDRESS argument Note if both FLASH ADDRESS and LOAD ADDRESS are specified and LOAD ADDRESS is located in flash then LOAD ADDRESS will be used and the FLASH ADDRESS argument will be ignored The optional LOAD ADDRESS and ENTRY POINT arguments allow you to specify these parameters if ENTRY POINT is not specified then to defaults to the load address Copyright 2009 ARM Limited All rights reserved 35 Example software WRITE IMAGE lt file gt Writes an ELF image file to flash NAME lt name gt The image will be identified in flash by a name derived from FLASH_ADDRESS lt address gt the fil
43. figured and ready for use and the bootmonitor software is loaded into the system memory Connect a serial cable to RS232 4 UART port3 above the power connector and use a terminal emulation program e g HyperTerminal configured as 38 400 baud 8bit data no parity 1 stop bit and no flow control to talk to the MPS Insert the power cable and turn on the PWR switch at the back This will bring up the system and the bootmonitor will start execution The character display will show the Firmware F W and Hardware H W versions of the system This is also output to the serial port for display on the terminal if connected The CPU LEDs 0 to 7 will cycle a lighted bit to show the bootmonitor is running The three blue LEDs on the right will be lit to indicate that the system and FPGAs are configured with valid images The four green Power LEDs will light to show all power supplies are functioning properly and within tolerance If a FAN LED lights then the corresponding FPGA temperature is above the pre defined limit if fans are fitted then the fan for that FPGA will become operational Pressing the recessed reset button on the front panel will perform a hardware reset and the system will restart as if it had been power cycled Switch settings ON ON OFF OFF The bootmonitor reads the processor switches 1 3 on power up and uses these to select the boot option On delivery all the switches are set to ON and defaults to no boot script with
44. g items are only used by the platform library as a means to an end therefore support is only required if needed e 2C not used or implemented e Although not used by the platform library drivers are provided for the following e Character LCD Support is provided for outputting messages to the character LCD using standard C library functions e Additional UARTs Any additional UART can be accessed using C library standard functions 9 3 2 Boot Monitor The boot monitor requires the following hardware support e FAT file system The boot monitor has several file related commands to copy load run etc It also supports the use of script files which are stored in a FAT file system e Switches The boot monitor uses one switch to select whether it will run a script when the system boots or not This is user switch 1 e Configuration and Informational The boot monitor obtain information such as hardware revisions directly from the hardware register The boot monitor can also configure system clocks by via hardware registers 9 4 Endianness The platform will only supports Little Endian LE 38 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Example software 9 5 Multiprocessing The platform library will not support multiprocessing and therefore any image that is built with the platform library will only run on a single core 9 6 System Boot There are bootable device
45. ghts reserved 33 Example software 9 1 2 Boot Monitor Configure Submenu Commands Command Format DISPLAY DATE DISPLAY HARDWARE DISPLAY TIME EXIT HELP lt command gt QUIT RESET IF REQUIRED SET BAUD port gt rate SET DATE lt dd mm yy gt SET TIME lt hh mm ss gt Note Displays the current system date Display hardware information Displays the current system time Exits the application or submenu List commands Alias for EXIT Resets this system If the optional IF REQUIRED qualifier is specified the system will only be reset if there has been a configuration change made that requires a reset Sets UART port gt to the specified rate e g SET BAUD 0 9600 available ports 0 4 Sets system date in the form dd mm yy Sets system time in the form hh mm ss 9 1 3 Boot Monitor Debug Submenu Commands Command Format DEPOSIT lt address gt lt value gt size DISABLE MESSAGES ENABLE MESSAGES EXAMINE address lt size gt EXIT GO lt address gt HELP lt command gt MODIFY lt address gt lt value gt lt mask gt size QUIT START TIMER 34 Copyright 2009 ARM Limited All rights reserved Note Deposit value lt value gt to memory at lt address gt optionally specifying the size it can be BYTE HALFWORD or WORD defaults to WORD Disables debug messages Enables debug messages Examine memory at address for size number of bytes Exit Run code at address
46. ic c jilald U C C i iH HIH HIHIHIHI HIHIHIHIHIHIH HIHIHI HIH H HIHIHIH Z C u u clc Gic U C U C C aalaga lalalalalala lalalalalalala lalala Z C U C C C O OJ O O C Uju cic aic VIDEOVSYNC VIDEOHSYNC VIDEODE D D D D D c OUT D OUT D OUT D OUT D OUT D D D D D D D D Utd tot ttt tol toto uu tye U C C NI Io U U Gic Gic Jg au J clc OJ OJ OJO O cic UO a U U Gic Gic JI au 1 0 0 0 REEF 1 J clc O O O O clc UO a U C C J z U O o o O O C 4 e m ime ojo o o 5 o w D o o m m wv o o0 o o N o U C O C a Z NIHIo U C O C Iw Z Table 7 FPGA Interconnect Signal Assignments 1 These signals are driven by DDR registers clocked by VIDEOCLK and are arranged in the same way as the signals are driven off the CPU FPGA 10 1 1 Other CPU FPGA Interfaces 10 1 1 1 Resets Signal Direction Width Comments CPU_PORSEL input Power on reset USER RESETn input User reset 10 1 1 2 Clocks from Clock Factory Signal Direction Width Comments CPU CLKI input AHB system clock input CPU CLK5 input Not used CPU CLKIO input Peripheral reference clock input CPU CLK15 input Not used CPU CLK100M input 100MHz reference clock 10 1 1 3 Clocks to Cl
47. ior and RVCT v3 1 Application Note 218 Copyright 2009 ARM Limited All rights reserved 39 ARM DAI0218A Signal assignments 10 10 1 11 Od n Q al kal zi yoj pe ala pp aja bol Q tz keai kai zd bel y Q Q D D ajajaja o lalu wInir o bol Q tz Q D jj ajajaja T bel Q D m o tz F1 keal keal kal Az tg ro Q Qo D HiHlblblh UHR WIDE tz bel Q m OY lal U Q D m oo tz bel Q D m o aai beni r1 r1 d 3 j ol el ed Wek ek Le Q1Q Q1Q 1Q a Dess alalalalalal ala alalalala NDININININ IN Uil o N m Io tz Q D N OY tz Q D tz Q D N N C C C C C C tz r1 kani beat rz ey Rol Mel el ek Wel QI QI Q Q Q aQ pese Go FU co FU Co G2 SO UPB oo to O Lo tz fe f Pri d rz ra a ee n bel Q Qa alalalalalalalalalalalalalala gs s is s s o9 fu UHR co N i Oo tvo oo 1 tz bel Q D OY U UJ U alam Due alalalalal a Ajaja vo oo 1 j ps Q D Ui o tj d Q D ul E tz i U a D afalala uu WIN tz bel Q D Ui ES rj ps Q D ain Ui Ui lt U Q D a vifu o Signal assignments This section shows the interfaces available on the Customer DUT FPGA The direction of the signals is shown from the point of view of the DUT FPGA so an O signal goes from the DUT FPGA to the CPU FPGA
48. ir See Figure 17 SD DO bi dir See Figure 17 48 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Signal assignments Tri stated driver nMCIDATEN MCIDATOUT 3 0 SD_CSn SD_DAT SD_IRQ SD_DO MCIDATIN 3 0 AY Tri stated driver SD CT Pulled low nMCICMDEN MCICMDOUT gt SD_DI MCICMDIN lt Open Collector Drain driver MCICLKOUT ba SD_CLK MCIFBCLK 1 MCIPWR SD Voc Power FET driver to smart Card PullUp Pulled down when card MCICARDIN SD CD present MCIWPROT SD WRP PullUp Pulled down when Write protected Figure 17 MCI interface connections The nCARDIN and WPROT signals are feed to the peripheral system registers for use as setting interrupts and detecting the status of the signals 10 1 2 7 Audio AC97 Interface This interface is driven by the Primecell PLO41 see section 5 3 11 Signal Direction Width Comments AC BITCLK Not connected AC EAPD Tied to 1 AC EXT CLK Not used Tied to 0 AC SDATAIN Drives AACISDATAIN AC SDATAOUT output Driven by AACISDATAOUT AC RESETn output Driven by AACIRESET AC SYNC bi dir Driven by AACISYNC used as an output 10 1 2 8 A D amp D A Interface This interface is driven by the serial interface block DS702 see section 5 3 2 Signal Direction Width Comments ADDA CLK bi dir Driven by SCL ADDA DATA bi dir Drives SDAin and is driven to
49. is Copyright 2009 ARM Limited All rights reserved 3 Getting started 2 4 Clock control of MPS HPE_Desk allows you to select which clock sources are routed to which clock inputs of the FPGAs clock factory so you can change the operation frequency of both the CPU and DUT FPGAs The Clocks to the clock factory are driven from the DUT and CPU FPGAs the CPU FPGA clocks are fixed by the design and not alterable by the customer The DUT FPGA clocks are alterable by the user by reconfiguring the PLL used to generate them Refer to the Altera Stratix Ill documentation for details on configuration of the PLL 2 5 Rebuilding the DUT FPGA To rebuild the DUT FPGA and configuring the MPS please see section 6 4 4 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Architecture 3 Architecture This application note implements an AHB AMBA 2 0 based system on the Microcontroller Prototyping System This board contains two FPGAs on which the system is implemented e The CPU FPGA One instance of the ARM Cortex M 3 processor with ETM two memory controllers to operate interfaces to the noBLRAM and FLASH NOR RAM on the board Touchscreen and IC peripherals and a configuration register block This FPGA has a dedicated interface to e The DUT FPGA Containing an example system including timers display drivers an audio interface and an MCI SD card interface 3 1 Block Diagram Figure 3 shows a conceptual blo
50. is block is called fpga_dut v and is the module called from the synthesis scripts e The logic module called dut_logic v which describes the structure of the top level logic and instances the AHB peripherals and the APB sub system e The associated AHB and APB peripherals which are specific to the Customer DUT FPGA e g an AHB decoder an AHB to APB bridge an AHB Lite Slave to Master Multiplexer etc e The system registers and their default settings are in this directory e The main defines which control what parts of the system are included in the build Also within this directory is the script for building the bit file to download to the FPGA The synthesis script is in physical mpb dut altera scripts and produces a routed placed design in the physical mpb dut altera netlist directory See the HPE Desk manuals for downloading this image to the FPGA 2 6 3 The peripherals Directory Application Note 218 ARM DAI0218A The peripherals directory contains verilog required for most of the ARM peripherals in the example customer system with some blocks as pre built vqm files in peripherals physical lt peripheral_name gt synplify netlist to be read in by the build script The function of each block is shown in section 3 Each Primecell or other large IP block has its own directory e g pl011_uart The netlists in these directories are pulled into the design by the scripts in the fpga dut directory Copyright 2009 ARM
51. mited All rights reserved Application Note 218 ARM DAI0218A 9 2 5 UART Example software Support for the PLO11 UART is provided by the following functions in the platform library platform uart entry Handles all channel operations for the UART channels reading characters writing characters and opening the channel 9 2 6 Character LCD Support for the character display is provided by the following functions in the platform library platform charlcd entry Handles all channel operations for the debug lcd channel writing characters and opening the channel 9 2 7 Timer Support for the SP804 timer is provided by the following functions in the platform library Enables a timer with a given period and mode timer disable Disables the defined timer timer interrupt clear Clears the timer interrupt 9 2 8 RTC Support for the real time clock is provided by the command line interface commands SET DATE SET TIME and by the following functions in the platform library time Reads the current time from the Real Time Clock 9 2 9 Ethernet 9 2 10 SSP 9 2 11 MMCI 9 2 12 USB 9 2 13 AACI Application Note 218 ARM DAI0218A No support is provided for the Ethernet controller No support is provided for the SSP controller Support for FAT16 file system 8 3 filenames 2GB max card size No support is provided for the USB controller No support is provided for the AAC
52. mmunication to the ISP1761 USB device 14 Configuration and use of this is outside the scope of this Application Note 5 3 10 UARTs The PLO11 PrimeCell is used as the UART See the TRM for details about its functionality 11 The clock source is divided down and is derived from the 100MHz clock 5 3 11 Audio AACI AC97 The PLO41 PrimeCell is used as the AACI See the TRM for details about its functionality 12 The AACI is a modification of the PrimeCell with increased FIFO depth to help improve transfer performance in FPGA The clock source is derived from the baseboard and drives a clock input of the DUT FPGA CLK13p The FPGA can also drive the AC EXT CLK to set the clock but this option is not implemented 5 3 12 MMC SD MMCI The PL181 PrimeCell is used as the MMC SD card controller See the TRM for details about its functionality 13 The MMCI uses the bits in the system registers to identify the write protection and card inserted status see section 5 3 1 for details 5 4 Boot operation This system should normally boot from the board NOR Flash the default configuration switches in the up position The NOR Flash is preprogrammed with the boot monitor The user can also program custom boot software in NOR Flash but note that any software configurable devices such as the UARTs etc will not work until properly configured Application Note 218 Copyright 2009 ARM Limited All rights reserved 25 ARM DAI0218A RTL 6 1 26
53. nd ZBT memory An APB bus is used to connect PrimeCell APB peripherals A separate AHB interconnect exists for access to the peripherals on the Customer DUT FPGA l D S AHB Lite mux 0x0000_0000 Ox08FF_FFFF 0x1040_0000 0x2000 0000 T OxDFFF_FFFF 0x1F00_0000 0x1000_0000 Ox1EFF_0000 ver ME OxEO10 0000 Ox1F00_FFFF Ox103F FFFF OxIEFF FFFF e OxFFFF FFFF AHB to APB APB Config registers VOPADS PLOM 3 SMC1 RAM FPGA SMCO ep PLO22 0 i 12C 0 l eh he ESS I VOPADS VORADS VOPADS bee 1 Hebei saan None LOADS 1 AHB Interface to DUT FPGA 0x1040_0000 Ox107F FFFF 0x1000 0000 OxiOSF FFFF And remaped to 0x0000 0000 O0x0000 0000 And aliased to OxOSFF FFFF 0x1800 0000 MPB M3 Processor FPGA Figure 5 Bus Architecture of CPU FPGA 3 1 2 Bus Architecture of Customer DUT FPGA An additional AHB Lite matrix is implemented in the DUT FPGA to give the processor access to all the AHB peripherals within the FPGA An AHB to APB bridge gives access to the APB peripherals in the system Application Note 218 Copyright 2009 ARM Limited All rights reserved 7 ARM DAI0218A Architecture 0x2000_0000 OxDFFF_FFFF OxEO10 0000 OxFFFF FFFF 1 0 PADS AHB Interface from CPU FPGA CPU FPGA Video Ethernet LIN CAN Flexray DDR I II SRAM NOR Character LCD I2C AACI AC97 UART 2 U
54. nectors on either end with connections as follows Pin Connector A Connector B 1 N C N C 2 RX TX 3 TX RX 4 DTR DSR 5 GND GND 6 DSR DTR 7 RTS CTS 8 CTS RTS 9 N C N C Connect one cable between the top two UART connectors and another between the bottom two UART connectors on the MPB back panel 7 1 4 3 USB OTG and USB Host cable The external interconnect is not tested as part of self test so no cable is required Selftest only ensures the registers can be read and written 30 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Clock frequency settings 8 Clock frequency settings Please see section 3 2 for the intended clock frequencies of the design Please use the online help of the HPE Desk software for details on programming the clocks 2 Application Note 218 Copyright 2009 ARM Limited All rights reserved 31 ARM DAI0218A Example software 9 Example software The example software components of the firmware are e Platform Library This handles the system initialization and retargets the C Library To achieve this it provides a basic I O subsystem that supports simple device drivers Included with the platform library there is a simple terminal driver UART PS 2 keyboard and LCD drivers and support for semihosting I O e Boot Monitor This is the normal application that runs when the system is booted It is built with the platform library and it is the platform libr
55. ock Factory Signal Direction Width Comments CPU PLL L2 CLKOUTO AHB and Processor frequency from FPGA PLL CPU PLL R2 CLKOUTO Peripheral reference clock from FPGA PLL CPU PLL B1 CLKOUT3 Not used DUT PLL T1 CLKOUT3 CPU Not used DUT PLL B1 CLKOUT3 CPU Not used Application Note 218 Copyright 2009 ARM Limited All rights reserved 41 ARM DAI0218A Signal assignments 10 1 1 4 LCD Signal Direction Width Comments LCD BLON output Tied to 1 LCD R HSYNC output Driven from Video controller CLLP Horizontal Sync signal LCD R M DE output Driven from Video controller CLAC Data Enable LCD R SHFCLK output Driven from Video controller Pixel Clock CLCP Pixel Clock LCD_R_VSYNC output Driven from Video controller CLFP Vertical Sync signal LCD_SPARE output Not Connected LCD_TTL_B Driven from Video controller CLD 7 2 Red Data MSBs LCD TTL G Driven from Video controller CLD 15 10 Green Data MSBs LCD TTL R Driven from Video controller CLD 32 18 Blue Data MSBs LCD VDON output Tied to 1 10 1 1 5 Touch Screen Interface Signal Direction Width Comments TOUCH SPI BUSY input Connects to TS BUSY TOUCH SPI CS output Driven by TS FSSOUT TOUCH SPI DCLK output Driven by TS CLK
56. ogether using Run all tests The tests perform register level and basic functional tests on the MPB hardware reporting any errors found The source code for the tests are brought together in a single project file build Build_Keil selftest_mpb Uv2 The source code for each peripheral test is split into separate directories for example apaaci contains apaaci c and apaaci h for testing the AACI peripheral The main folder contains main c and common c which provide the user menu and functions that are common to all peripheral tests Note If the default install directory is not used then the project will have to be rebuilt in order for the debugger to display the source code automatically 7 1 4 Selftest test harness Application Note 218 ARM DAI0218A The MPB test code requires three separate cable assemblies to be connected to the board for complete testing Note these cables are not supplied with the MPB but details of their connections are given here Copyright 2009 ARM Limited All rights reserved 29 Functional testing 7 1 4 1 The AACI cable The AACI test performs a loopback test from Line Level Out to Line Level In This requires two 3 5mm stereo jack plugs which must all be wired as follows Connector A Connector B Tip Tip Ring Ring Screen Screen Connect the cable between the line in and line out sockets on the MPB back panel 7 1 4 2 UART loopback cable The two UART cables have female 9 pin D sub con
57. ogrammer s model 5 2 1 2 Memory Configuration SYS MEMCFG Power On Reset Reserved 1313 RW e SWDPEN 2 Single Wire Debug Port Enable 1 is SWD 0 t FO PP LE Not used in Cortex M3 implementation as this autodetects serial or JTAG REMAP fo RW bo Remap SSRAM 1 is Remap on0 Remap off Default memory mapping is Flash Aliased and SSRAM not remapped The register is reset at power on to this state but any debug reset or system reset will not change the values stored This allows the SRAM to be programmed placed and address 0x0000_0000 and execute after generating a system reset 5 2 1 3 Switches SYS SW Reseed sie USER SWITCH 7 0 JRO fh Always returns value of user switches 5 2 1 4 LEDs SYS LED Reseved iste OCOCSCSCSCSSCCCCCC C Returns value in register 1 is LED on OLED of 5 2 1 5 TouchScreen SYS TS Resened Ba E TS INT RO b External Interrupt from Touchscreen TS BUSY o JRO fb External Busy signal from Touchscreen 5 2 2 Video I2C for DVI The DS702 peripheral is used for the interface and implements a bit banging method for the I2C interface The base address for this interface is 0x1F00_3000 Register Ofset Access Reset Note SB CONTROL Jno000 A eo Status Register of VOsignals SB_CONTROLS hoo00 w boo SetOuiputbis SB CONTROLC hood WO boo Oear
58. ote the interface can be a 4 bit or 8 bit interface For this application it is in 8 bit mode Note When the display is used with a 4 bit interface an 8 bit value has to be written read as two consecutive nibbles writing reading bits 7 4 first into register bits 7 4 then writing reading bits 3 0 into register bits 7 4 Register Offset Access Reset Note CHAR_COM h0000 RW h00000000 JA write will write to the display controller command register read will initiate a status register access returns value later in CHAR RD CHAR DAT h0004 h00000000 JA write will write to the display controller data register read will initiate a data register access returns value later in CHAR RD me ai co 10 CHAR DAT read when CHAR RAWIS i is set Writing 0 to bit 8 clears bit us pum e pasas Eds aree completes ner nc per CHAR MASK 22 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Programmer s model 5 3 3 1 Character Command Register CHAR COM Reset Note Been e mE Y E COMMAND 0 RW h00000000 JA write will write to the display controller command register A read will initiate a status register access returns value later in CHAR RAW and CHAR RD 5 3 3 2 Character Data Register CHAR DAT Rest Note esee prd a DATA 7 0 RW h00000000 JA write will write to the display controller data register A read
59. r configuration this is implemented in the CPU FPGA see section 5 2 2 for details of registers The Datasheet 7 covers the data format and process for configuration The example clock source for the video pixel clock is derived from the PLL in the DUT FPGA and drives a clock input of the DUT FPGA CLK4p via the clock factory The clock source isset by the HPE Desk application on the PC and the frequency is determined by the PLL implemented in the DUT FPGA Note though the interface to the Video and LCD displays is driven by the processor FPGA the peripheral is in the Customer DUT FPGA and the video LCD signals are driven across the interconnect between the two FPGAs see section 10 1 The signals from the CLCD are mapped to the video signals as follows Note Pixel Clock CLPOWER 7 NotUsed CUP ICO A HSYNC VIDEOHSYNC Horizontal Sync Verical Sync Data Enable CLE Not Use ICLD 19 16 VIDEO 11 8 Green Data DDR encoded rising edge ICLD 15 8 VIDEO 7 0 Blue Data DDR encoded rising edge CLD 7 0 J VIDEO ff 4 Red Data DDR encoded falling edge ICLD 23 20 VIDEO 30 Green Data DDR encoded falling edge ICLD 23 0 VIDEO I1 0 RGB colour Data DDR encoded falling edge cra OD TTLRES Red Data MSB s CLD ISH0 LoD TL Giso Green Data MSB CLD 23 18 LCD TTL B 50 Blue Data MSB s VIDEORESET Reset synchronised to pixel clock MEF INT Hot Plug inter
60. raaa FeNSa a aa Ea EEEa 14 AT Top a E EE E TE TS S E S E T TA 15 5 PROGRAMMER S MODEL svciaritecacnuscavecavinacacavaranecaucnevscayicauscbedaauceavigaveubusvaudcausaavdunusaatendi 16 E Mou 16 5 2 CPU FPGA specific registers eere eese esee eene eee ee etn tn sento seta sosta stesso seta coapse seriden ta senses tosta sse ta sens tn sensns eae 17 5 3 Customer DUT FPGA Specific Registers ceci eee essen eene enses tnnt n enata tuse ta sine ta sens en sesto s eta sse ta sens en sesto sena 19 5 4 lt Boot operation EE 25 cs n HOC EEE ETET TT 26 6 1 Directory structure AREENA SEO E OEE EAE AEA OEE 26 6 2 The fpga dut Directory eee eese etes eerte entente notans thats enses sosta sone ta sens enses suse to sone oS Seo Se Sanss eaea ostes siesti ienn 27 6 3 The peripherals Directory eeeeeee esee eene teens oeo snes Sae oies So seta riiete Oeri toss SAES sone ta ses senses ense tasse taste ET ai 27 dvo Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A 6 4 Building the application note ss sssssesesssenessenenensneenenesenenennsnennenneseensneesseneeneeseneesssnseese 28 7 FUNCIIONAE TES ENG nn nn nn EE GE SER net dt DECRE UE kasaad aa DUREE 29 AI MEE iare Msn sn tetes ses EE er ces se ATAOE AE TTT 29 8 CLOCK FREQUENCY SETTINGG ccccccccccccccecceeeseseesesesesssssesesceccseesesessessesesesesecsesesssses 31 9 EXAMPLE SOFTWARE pscing nissana a EAA ESA E
61. rupt Not Used VIDEOMODE Video Mode GPIO pin of video chip Not Used MEE NR VIDEO I2C SC Video Chip configuration bus L BEEN ERE VIDEO I2C SD Video Chip configuration bus A LCD BLON Back Light On output tied to 1 7 LCD VDON LCD Power On output tied to 1 Table 6 Video and LCD Connections For further data on the video encoding see the Datasheet for Chrontel CH7303A device 7 5 3 5 Timer The SP804 ADK component is used for the timers See the TRM for details about its functionality 8 The Timer clock is set at 1MHz and is derived from the 100MHz clock The combined interrupt is used so each SP804 implementation only has 1 interrupt output see section 3 3 24 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Programmer s model 5 3 6 RTC The PLO31 PrimeCell is used as the RTC See the TRM for details about its functionality 9 The RTC clock is feed from the RTCCLK signal and is 1Hz and is derived from the 100MHz clock 5 3 7 WatchDog The SP805 ADK component is used for the watchdog See the TRM for details about its functionality 10 The clock is set at 1Hz and is derived from the 100MHZ clock 5 3 8 Dynamic Memory Controller This is a user Supplied component with basic interfaces brought into the DUT FPGA to enable implementation 5 3 9 Static Memory Controller The Static memory interface implemented in the design is specifically to allow co
62. s on the board NOR Flash or SSRAM 9 6 1 Boot from Flash When the system boots the first instructions executed will be from memory at address 0 This memory is read only If the code within this memory requires read write memory it is expected that it will initialize and use SSRAM The type of memory visible at address 0 on system boot is determined by the configuration register settings the default setting is to boot from flash At system boot this memory will be visible in two locations at address zero and at a fixed location in the memory map It is expected that the code within this memory will branch to the copy at the fixed location The code will detect if the core is a secondary master and if so enter a safe mode Only the primary master will continue initialization and copy the code to SSRAM before performing a remap operation to remove the copy at address zero 9 7 Platform Library Initialization The implementation is very similar to the existing ARM hardware platforms therefore the initialization of the platform library will be basically the same The differences are handled with different include files and conditional compilation 9 8 Memory Management amp Caches No cache or memory management is implemented in the processor so no additional support is required 9 9 Building the Firmware 9 9 1 Development Environment Currently only a Windows development environment is supported The firmware can be built using CodeWarr
63. s to SSRAM SSRAMO DQA bi dir 7 0 Data lines 7 0 Byte lane 0 SSRAMO DQB bi dir 7 0 Data lines 15 8 Byte lane 1 SSRAMO DQC bi dir 7 0 Data lines 23 16 Byte lane 2 SSRAMO DQD bi dir 7 0 Data lines 31 24 Byte lane 3 SSRAMO BWAn output Write byte lane 0 Active low signal SSRAMO BWBn output Write byte lane 1 Active low signal SSRAMO BWCn output Write byte lane 2 Active low signal 44 Copyright 2009 ARM Limited All rights reserved Application Note 218 ARM DAI0218A Signal assignments SSRAMO BWDn output Write byte lane 3 Active low signal SSRAMO DQPA bi dir Byte lane 0 parity signal SSRAMO DQPB bi dir Byte lane 1 parity signal SSRAMO DQPC bi dir Byte lane 2 parity signal SSRAMO DQPD bi dir Byte lane 3 parity signal SSRAMO CSIn output Chip select 1 Active low signal SSRAMO CS2 output Chip select 2 Active high signal SSRAMO CS3n output Chip select 3 Active low signal SSRAMO WEn output Write enable Active low signal SSRAMO CKEn output Clock enable signal Active low signal SSRAMO OEn output Output enable Active low signal SSRAMO LBOn output Burst Mode Control Active low signal Tied to 0 SSRAMO ADV output Address Advance Tied to 0 SSRAMO ZZ output Sleep request Tied to 0 10 1 1 15 Common SSRAM1 and FLASH Connections The lines
64. will initiate a data register access returns value later in CHAR RAW and CHAR RD 5 3 3 3 Character RD Register CHAR RD P O a Reseved lte AO 00000000 READ 0 h00000000 SET ST CHAE data from last CHAR_COM or CHAR_DAT read when DONE is set 5 3 3 4 Character Command Register CHAR_RAW Memes es ess ee oe Reserved 3t9 RW h0000000 DONE RW Reading indicates AUGE AUR access is complete Writing 0 clears bit Reserved 70 RW ho Note If a transaction is attempted before DONE is asserted CHAR RAW register by the controller then it maybe ignored and the command data transfer could be lost Once DONE is asserted it can be cleared and a transaction started 5 3 3 5 Character Interrupt Mask Register CHAR MASK Besa Noe O S Git RW moo MASKINT RW Set to 1 will generate interrupt when access completes CHAR DONE set 5 3 3 6 Character Status Register CHAR STAT Bits Access Reset Application Note 218 Copyright 2009 ARM Limited All rights reserved 23 ARM DAI0218A Programmer s model STATINT RW Returns status of CHAR DONE ANDed with CHAR MASKINT 5 3 4 Video This is a user supplied component with basic interfaces brought into the DUT FPGA to enable implementation The DVI I controller device 7 includes an I2C DS702 serial bus fo

Microcontroller Prototyping System - Using Cortex-M3

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