VIP, VIP-8 Versatile ISDN Port PEB 20590 Version 2.1 PEB 20591
Contents
1. 15 Table 7 JTAG Boundary Scan Test Interface IEEE 1149 1 15 Table 8 Control Bits in S T Mode on DR 31 Table 9 Control Bits in S T Mode on DX 31 Table 10 TAP Controller Instruction Codes Overview 34 Table 11 DC 5 39 Table 12 Capacitances except line interfaces and clocks 41 Table 13 Recommended Crystal 41 Table 14 IOM 2000 Interface Timing 43 Table 15 JTAG Boundary Scan Timing Values 45 Data Sheet 2001 03 01 ga Infineon PER 20390 technologies PEB 20591 Preface This document provides reference information on VIP Versatile ISDN Port Organization of this Document This Data Sheet is divided into 9 chapters It is organized as follows Chapter 1 Introduction Gives a general description of the VIP lists the key features and presents some typical applications Chapter 2 Pin Description Lists pin locations with associated signals categorizes signals according to function and describes signals Chapter 3 Interface Description Describes the VIP external interfaces Chapter 4 Operational Description Describes the VIP operations reset initialization analog test loops and the monitoring o2. 25 3 3 3 Receive Clock Recovery 25 3 3 3 1 LT S MOUS Red 26 3 3 3 2 ETAT aed 27 3 3 4 Reference Clock Selection in LT T Mode 28 3 3 5 Receive Signal Oversampling 29 3 3 6 Elastic BUCY Pr cT 29 3 4 IOM 2000 Interface Overview 30 3 4 1 IOM 2000 Frame Structure 31 3 4 1 1 Data Interface uu vdd dele eae ee y secs RE kee 31 3 5 JTAG Boundary Scan Test Interface 34 3 5 1 TAP C ntroller siss s sa arret e e OEE E OA 34 4 Operational Description 36 4 1 General epp 36 4 2 uui us Vas Uude ches 36 4 3 ANZ AON DTE 36 4 4 Analog Test 5 37 4 5 Monitoring of Code Violations 37 5 Electrical Characteristics 38 5 1 Absolute Maximum Ratings 38 5 2 Operating Range 38 5 3 DC Characteristics 39 5 4 e 41 5 5 Recommended 15 36 MHz Crystal Parameters 41 Data Sheet 2001 03 01
3. 2096 S T interface compatible to QUAT S 2084 OM 2000 interface to DELIC supporting up to three VIPs 24 channels Transceiver initialization and configuration Control of layer 1 activation deactivation Exchange of command and status information e Signaling control for all VIP channels by dedicated HDLC controllers DELIC Single 3 3 V power supply JTAG IEEE1149 1 compliant test interface with dedicated reset input Note Up refers to a version of the Up interface meeting the ZVEI standard with a reduced loop length of up to 1 3 km depending on the type of cable 1 Infineon Technologies OCTAT P 2096 Octal Transceiver for Upy Interfaces 2 Infineon Technologies QUAT S 2084 Quadruple Transceiver for S T Interface Type Package PEB 20590 PEB 20591 P MQFP 80 1 Data Sheet 5 2001 03 01 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Introduction 1 3 Logic Symbol Diagrams Power Supply Analog Digital Reset i 24 S T and Up Line Interface 7 VIP lt gt 2000 Interface PEB 20590 Dedicated 6 gt Pins A A af 54 V V Clock JTAG Signals Test Interface vip 0003 logic symbol Figure 2 Logic Symbol PEB 20590 72 of 80 Pins used Power Supply Analog Digital Reset 27 1 32 S T and Uy Line Interface 7 VIP 8 lt gt 2000 PEB 20591 Dedicated _ A Fi sH
4. Infineon PEB 20590 technologies PEB 20591 Table of Contents Page 5 6 Characteristics 22 ciues nesese menan 2 5 ee ee eed dod Rode wba 42 5 7 Pe grace opa E ROSEO 42 5 8 Upn Interface ome a Gis as Sate dee Ae 42 5 9 IOM 2000 Interface 43 5 10 JTAG Boundary Scan Test Interface 44 5 11 Transmitter Performance 45 5 12 S T Transmitter Performance 45 6 Application Hints 0 00002 es 46 6 1 VIP External 46 6 1 1 Recommended Line Transformers 46 6 1 2 Interface External 47 6 1 3 S T Interface External Circuitry 47 6 2 Wiring Configurations in LT S Mode 49 6 3 LOOP MOdES cn ec oe We Bhd Ble dod a 50 7 Package 51 8 Glossary 52 9 eee ee 5 Data Sheet 2001 03 01 Infineon technologies List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12
5. PRELIMINARY Application Hints 6 2 Wiring Configurations in LT S Mode 1000 m Point to Point SCOUT S TR TR VIP Configurations TE1 ds lt 100 200 m Short Passive Bus lt 10m LT S SCOUT S SCOUT S TE1 8 500 lt 25 50 j mw H Vip Extended Passive Bus lt 10m LT S y SCOUT S SCOUT S TE1 TE8 TR Terminating Resistor see ITU 1 430 Figure 32 Wiring Configurations in User Premises LT S Mode Data Sheet 49 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Application Hints 6 3 Loop Modes The following figure shows the different loops that can be closed in the VIP Loops are programmed by the DELIC using the command bits LOOP EXLP and TX EN External VIP Circuitry Internal analog loop Analog Analog TX 4 Line Transmitter 4 lt a Driver EN Ed LOOP IOM 2000 eC o EXLP 1 Analog 0 Receiver m gt DR MUX Figure 33 Internal and External Loop Back Modes Data Sheet 50 2001 03 01 07 _ Infineon technologies PEB 20591 Package Outlines 7 Package Outlines P MQFP 80 1 Plastic Metric Quad Flat Package
6. P NET 17 2 8 Index Marking a 8 3 gt 1 Does not Include plastic or metal protrusion of 0 25 max per side t Sorts of Packing Package outlines for tubes trays etc are contained in our Data Book Package Information SMD Surface Mounted Device Dimensions in mm Data Sheet 51 2001 03 01 infinson PEB 20590 20591 PRELIMINARY Glossary 8 Glossary AMI Alternate Mark Inversion ANSI American National Standardization Institute CMOS Complementary Metal Oxide Semiconductor CO Central Office DC Direct Current DECT Digital European Cordless Telecommunication DELIC DSP Embedded Line and Port Interface Controller PEB 20570 PEB 20571 EMC ElectroMagnetic Compatibility ETSI European Telephone Standards Institute HDLC High level Data Link Control IEEE Institute of Electrical and Electronic Engineers INFO U and S interface signal as specified by ANSI ETSI Input Output IOM 2 ISDN Oriented Modular 2nd generation IOM 2000 Proprietary ISDN inferface for connection of VIP to DELIC ISDN Integrated services Digital Network ITU International Telecommunications Union OCTAT P Transceiver for U Interfaces 2096 LT S Line Termination Subscriber LT T Line Termination Trunk PLL Phase Locked Loop PBX Private Branch Exchange QUAT S QUAdrupleTransceiver for S T Interface 2084 S T Two wire pair interface TAP Test Access P
7. 3 5 JTAG Boundary Scan Test Interface The VIP provides IEEE 1149 1 compatible boundary scan support to allow cost effective board testing It consists of e Complete boundary scan test Test access port TAP controller Five dedicated pins TCK TMS TDI TDO according to JTAG and an additional TRST pin to enable asynchronous resets to the TAP controller e One 32 bit IDCODE register e Specific functions for the analog line interface pins b and SXna b 3 5 1 TAP Controller The TAP controller implements the state machine defined in the JTAG standard IEEE 1149 1 Transitions on the pin TMS cause the TAP controller to perform a state change The TAP controller supports 7 instructions e 5 standard instructions 2 additional user specific instructions for transmitting continuous pulses at the line interfaces 60 kHz and SXna b 120 kHz Table 10 TAP Controller Instruction Codes Overview Code Instruction Function 0000 EXTEST External testing 0001 INTEST Internal testing 0010 SAMPLE PRELOAD Snap shot testing 0011 IDCODE Reading ID code register 1111 BYPASS Bypass operation 1000 User specific Continuous pulses on and 1001 User specific Continuous pulses on SXna and SXnb TAP Controller Instructions EXTEST EXTEST is used to verify the board interconnections When controller is in the state update all output pins are updated with t
8. 5 DIR DiRection of Transfer Upy Line Interface Indicates the direction of the data transfer Tx or Rx in Upy ping pong mode required for driving electronic transformers SCAN ENable If driven to 1 during device tests a full scan of the VIP is enabled 60 SCANEN Data Sheet 14 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY Pin Description Table 6 Power Supply and Reset Pin Symbol I During Function No Out O Reset 11 24 VppA Power Supply 3 3 V Analog 29 38 Used for VIP analog logic 49 63 67 72 77 6 14 Vppp Power Supply 3 3 V Digital 45 53 Used for VIP digital logic 10 23 VssA Reference Ground 0 Analog 30 37 50 64 68 71 78 7 15 Vssp Reference Ground 0 V Digital 46 54 44 RESET low System Reset VIP is forced to go into reset state Table 7 JTAG Boundary Scan Test Interface IEEE 1149 1 Pin Symbol In During Function No Out O Reset 58 TCK Test ClocK Provides a clock for JTAG test logic 57 TMS Test Mode Select internal pull up A O 1 transition on this pin is required to step through the TAP controller state machine 56 TDI Test Data Input internal pull up In the appropriate TAP controller state test data or a instruction is shifted in via this line 59 TDO O O Test Data Outp
9. ITAC IWE MUSAC A OCTAT P QUAT S SICAT SICOFI SICOFI 2 SICOFI 4 SICOFI 4uC SLICOFI are registered trademarks of Infineon Technologies AG ACE ASM ASP POTSWIRE QuadFALC SCOUT are trademarks of Infineon Technologies AG Infineon PEB 20590 technologies PEB 20591 Table of Contents Page 1 Introduction ne OA Oe Oe ee Ow oil Bed Bed and 3 1 1 atin in ee Oe eR ewe ee mane 3 1 2 Logic Symbol lt 6 1 3 Typical Applications 7 2 Pin Description 2232293272315 923 9 2 1 aper Pie WD 9 2 2 Pin DescHpMlOPIS s sce eU ER tubes ra e e n 11 3 Interface Description 16 3 1 Overview of Interfaces 16 3 2 Upy Line Interface 16 3 2 1 Frame 16 3 2 2 Du Transceiver 20 3 2 3 Receive PLL oo aea E aa b d SERRE 21 3 2 4 Receive Signal Oversampling 21 3 3 ese odo cen 22 3 3 1 Frame a e dee Rede ur dt e ede eed 23 3 3 2 SVT Transceiver ccc sone cased d Dx E ae
10. Phase adjustment The RxPLL performs tracking after detecting phase shifts of the same polarity in four consecutive pulses A phase adjustment is done by adding or subtracting 65 ns or 32 5 ns one oscillator period programmable by the DELIC command bit PLLS default TICCMR PLLS 0 to or from the 384 kHz receive data clock 3 2 4 Receive Signal Oversampling In order to further reduce the bit error rate in severe conditions the VIP performs oversampling of the received signal and uses majority decision logic The process of receive signal oversampling is illustrated in Figure 13 Each received bit is sampled 6 times at 15 36 MHz clock intervals inside the estimated bit window The samples obtained are compared to a threshold of 50 with respect to the signal stored by the peak detector If at least n samples have an amplitude exceeding the 50 threshold a logical 1 is detected otherwise a logical 0 no signal is assumed The parameter n is programmed in steps of 2 in bits OWIN 2 0 of IOM 2000 register Note The recommended setting for signal oversampling is TICCMR OWIN 011 For detailed description please refer to DELIC LC PB Data Sheet Data Sheet 21 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description A Ku Vibl 100 50 P dl Se Bit No 401234 18 19 20 21 22 23 40 384 kH
11. 01 PEB 20590 Infineon technologies PEB 20591 PRELIMINARY Pin Description top view P MQFP 80 1 2 Q 2 3 Ins i m 5 9998 599 8 gt gt 90 gt gt 0 gt gt AOA AA th SR5b LI5b SR3b LI3b SR5a Li5a Vopa Vopa SSA SSA SX5b SX3b SX5a Sx3a VIP ADD1 Hs VIP ADDO SX6a SX2a SX6b VIP 8 SX2b 20591 DDA DDA SR6a LI6a SR2a Ll2a SR6b LI6b SR2b LI2b SR7b LI7b SR1b LI1b SR7a LI7a 1 Vopa Vopa SSA SSA SX7b SX1b SX7a SX1a ca Q a lt a ao lt 200 9 J e C6Ep sz S 2sdz22890 amp 8 M co O nn a vip_0005_vip8_pinout Figure 8 Pin Diagram PEB 20591 Data Sheet 10 2001 03 01 20590 Infineon PEB 20591 PRELIMINARY Pin Description 2 2 Pin Descriptions Table 2 20590 Upy and S T Line Interface Pin Symbol In 1 During Function No Out O Reset 25 SR1a Ll1a I VO I S T Receive Channel 1 3 5 7 26 SR1b LI1b Transmit Receive Channel 1 3 5 7 39 SR3a LI3a 40 SR3b LI3b 62 SR5a LI5a 61 SR5b LI5b 76 SR7a LI7a 75 SR7b LI7b 12 LlOa Transmit Receive Channel 0 2 4 6 13 1106 28 Ll2a 27 LI2b 48 Ll4a 47 1145 73 Ll6a 74 LI6b 21 SX1a O O S T Transmit Channel 1 3 5 7 22 SX1b
12. Device Code Manufacturer Code Output 0010 0000 0000 0100 1111 0000 1000 001 1 gt TDO Note In the state test logic reset the code 0011 is loaded into the instruction code register BYPASS A bit entering TDI is shifted to TDO after one TCK clock cycle e g to skip testing of selected ICs on a printed circuit board User Specific Instructions Symmetric continuous pulses can be generated at pins 60 kHz and SXna b 120 kHz to test the analog line interfaces Note A 15 36 MHz crystal or an external 15 36 MHz clock signal on CLK15 1 is required for test pulse generation Data Sheet 35 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Operational Description 4 Operational Description After some general remarks on the operation of the DELIC amp VIP chipset the reset and the initialization procedure are described The operation of analog test loops as well as the monitoring of illegal code violations are also part of this chapter 4 1 General The DELIC amp VIP chipset provides all functionality required for data transmission over the Up and the S T interface e g initialization and configuration activation and deactivation frame and multiframe synchronization The Upy and S T layer 1 state machines run on DELIC s DSP performing activation deactivation switching of loops and transmission of test pulse patterns Such actions can be initiated by INF
13. Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Data Sheet PEB 20590 PEB 20591 Page Top Level Block Diagram of the 4 Logic Symbol 20590 72 of 80 Pins 6 Logic Symbol 20591 6 VIP in Mixed S T and Upy Line Cards e g 8 S T and 16 Upy 7 VIP in a Small PBX Solution 7 DELIC PB and VIP in a Card for 8 16 S T Interfaces 8 Pin Diagram PEB 20590 9 Pin Diagram 20591 10 Upy Interface Frame Structure 17 AMI Coding the Upy Interface in VIP 19 Transceiver Functional 20 Eduallzer sue ated Tote E dE E E 20 Receive Signal Oversampling on Upy Interface 22 Frame Structure at Reference Points S and T ITU T 1 430 23 S T Interface Line Code without Code Violation 24 Receiver Functional 5 25 Clock Recovery in LT T 27 LT T Reference Clock Channel Selection for Cascaded VIPs 28 Recei
14. hold time after tescu 70 ns not shown in DCL_2000 falling edge Figure 25 DX setup time before toxs 10 ns DCL_2000 falling edge DX hold time after toxH 10 ns DCL_2000 falling edge 5 10 JTAG Boundary Scan Test Interface 100 X ITD05401 Figure 26 JTAG Timing Data Sheet 44 2001 03 01 07 Infineon technologies PEB 20591 PRELIMINARY Electrical Characteristics Table 15 JTAG Boundary Scan Timing Values Parameter Symbol Limit Values Unit min max Test clock period a 100 ns Test clock period low Lon 50 5 Test clock period high Bei 50 5 TMS setup time to TCK luss 10 ns TMS hold time from TCK 10 ns TDI setup time to TCK ic 10 ns TDI hold time from TCK 10 5 valid delay from 30 5 5 11 Upy Transmitter Performance The VIP fulfills the electrical requirements of the Up interface for loop lengths depending on the cable quality Adaptive Equalizer Switching is Enabled AAC 1 0 and FIL 1 in DELIC IOM 2000 Command Register Cable Loop Length J Y ST Y 2x2xO0 6 up to 1 km AWG 26 up to 1 3 km 5 12 S T Transmitter Performance Cable 0 6 mm 120 nF km Distance TE TE Distance TE LT 200 2000 kHz 950 100 mVpp Roundtrip lt 2 us 200 2000 kHz 120m 550m 100 mVpp Configuration Point to point Data Sheet 45 2001 0
15. in the circuit description are fulfilled Data Sheet 38 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY 5 3 DC Characteristics 3 3 V 0 17 V T 0 to 70 C Table 11 DC Characteristics Electrical Characteristics Parameter Symbol Limit Values min max Unit Test Condition All digital pins except LIna b SXna b SRna b CLK15 1 O L input voltage 0 8 V H input voltage V 2 0 0 3 IV L output voltage Vou 0 45 V lout 2mA H output voltage Von 2 4 V lout 2 mA Input leakage current L 1 lt lt not specified for pins DIR and REFCLK TDI TMS TRST Input leakage current 1 Vy Voo high Input leakage current d 10 300 Vy 0 V internal low pull up resistor Lina b Transmitter output Vy 2 24 3 08 V U Transmitter amplitude output amplitude Receiver input 10 Receiver input impedance impedance transmitter inactive SXna b Absolute value of 1 05 1 16 V 500 output pulse amplitude 1 05 1 23 V 400 Q Voxna Data Sheet 39 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY Electrical Characteristics Table 11 DC Characteristics cont d Parameter Symbo
16. 03 01 07 Infineon dici technologies PEB 20591 PRELIMINARY Application Hints 6 1 2 Interface External Circuitry A transformer external resistors and two capacitors 100 nF and 0 33 uF are connected externally to the line interface pins Llna b Voltage overload protection is achieved by adding clamping diodes see Figure 28 Upn Transceiver 100 Figure 28 External Transceiver Circuitry of the Mode Note The resistor values in Figure 28 are optimized for an ideal transformer 0 The 0 33 pF capacitance will be verified during system tests 6 1 3 S T Interface External Circuitry The VIP needs some external circuitry to achieve impedance matching overvoltage protection and ElectroMagnetic Compatibility EMC for its connection to the 4 wire S T interface The configuration is shown in Figure 29 26 8 mA Spec S T External External S T Transmitter Circuitry Circuitry 0 75 Receiver Figure 29 Overview of External Circuitry of the VIP in S T Mode Note The actual values of the external resistors depend on the transformer selected The resistor values are optimal for an ideal transformer 0 Line termination R is usually applied to the NT and last wall outlet on the S bus only Data Sheet 47 2001 03 01 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Application Hints Transmitter Dedic
17. 3 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Application Hints 6 Application Hints This chapter provides some additional information on how to use the VIP The first section describes some external circuitry Recommended line transformers resistors and capacitors Different wiring configurations in user premises are depicted for the LT S mode and the different loops that can be closed in the VIP via the DELIC are also presented in the following sections 6 1 VIP External Circuitry 6 1 1 Recommended Line Transformers The VIP is connected to the Up or S T lines 1 1 transformers The line side primary side of the transformer could be center tapped for the phantom power supply Reference model parameters of the transformers are shown below Up Transformer Primary to secondary transformer ratio 1 1 Primary total DC resistance lt 4 80 Primary inductance Ly gt 2 1 mH 20 Primary inductance with secondary short circuited Lp lt 22 uH Coupling capacitance C lt 150 pF S T Transformer Primary to secondary transformer ratio 1 1 Primary total DC resistance lt 2 0 Primary inductance Ly gt 30 MH Primary inductance with secondary short circuited L lt 6 uH Coupling capacitance C 80 pF Lp R Line Side 1 1 Ideal Transformer vip trafo model vsd Figure 27 1 1 Transformer Model Data Sheet 46 2001
18. 35 SX3a 36 SX3b 66 SX5a 65 SX5b 80 SX7a 79 SX7b 8 9 not connected 31 32 51 52 69 70 Data Sheet 11 2001 03 01 20590 Infineon PEB 20591 PRELIMINARY Pin Description Table 3 20591 Upy and S T Line Interface Pin Symbol In 1 During Function No Out O Reset 12 SROa LIOa I VO S T Receive Channel 13 SROb LIOb Upy Transmit Receive Channel 25 SH1a Llta 26 SR1b Ll1b 27 SR2a Ll2a 28 SR2b LI2b 39 SR3a LI3a 40 SR3b LI3b 48 SR4a Ll4a 47 SR4b LI4b 62 SR5a Ll5a 61 SR5b LI5b 73 SRe6a Ll6a 74 SR6b LI6b 76 SR7a LI7a 75 SR7b LI7b 8 SX0a S T Transmit Channel 9 SXOb 21 SX1a 22 SX1b 32 SX2a 31 SX2b 35 SX3a 36 SX3b 52 SX4a 51 SX4b 66 SX5a 65 SX5b 69 SX6a 70 SX6b 80 SX7a 79 SX7b Data Sheet 12 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY Pin Description Table 4 IOM 2000 Interface Pin Symbol In 1 During Function No Out O Reset 18 FSC IOM 2000 Frame SynChronization 8 kHz signal for IOM 2000 frames 19 DCL 2000 IOM 2000 Data CLock Data Clock from DELIC 3 072 6 144 or 12 288 MHz in case of 1 2 or 3 VIPs 1 DR O IOM 2000 Data Receive Data received on the line interface is sent to the DELIC 20 DX IOM 2000 Data Transmit Data to be transmitted on the line interface is received from the DEL
19. 90 technologies PEB 20591 PRELIMINARY Interface Description 3 3 3 1 LT S Mode In the LT S mode the DELIC is the clock master to all terminals connected to the VIP In receive direction two cases are distinguished depending on the bus configuration Point to point or extended passive bus Short passive bus Point to Point or Extended Passive Bus e Programmed by DELIC IOM 2000 Command bits MOSEL 1 0 00 MODE 2 0 011 The 192 kHz receive bit clock is recovered via PLL from the receive data stream on the S interface Shift between receive and transmit frame According to ITU T 1 430 the receive frame may be shifted by 2 to 8 bits with respect to the transmit frame VIP supports also other frame shifts including O Note The recommended setting for point to point and extended passive bus in LT S mode is TICCMR OWIN 101 and TICCMR PD 0 For detailed description please refer to VIP channel config command in the DELIC LC PB SW User s Manual Short Passive Bus e Programmed by DELIC IOM 2000 Command bits MOSEL 1 0 00 MODE 2 0 111 e The 192 kHz receive bit clock is identical to the transmit bit clock generated by division of the incoming IOM 2000 data clock Shift between receive and transmit frame The sampling instant for the receive bits is shifted by 4 6 us with respect to the transmit bit clock According to ITU T 1 430 the receive frame must be shifted delayed by two bits wi
20. Data Sheet 054 March 2001 2 0590 Version 2 1 i N 20594 Version 2e X Wired Communications Never stop thinking Edition 2001 03 01 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 M nchen Germany Infineon Technologies AG 2001 Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness o
21. IC 2 CMD IOM 2000 ComManD Receives the commands from the DELIC 3 STAT IOM 2000 STATus Transmits the VIP status information to the DELIC 4 REFCLK IOM 2000 REFerence CLocK Provides a 1 536 MHz reference clock e g derived from Central Office in LT T applications to the DELIC Data Sheet 2001 03 01 20590 Infineon PEB 20591 PRELIMINARY Pin Description Table 5 Clock Signals and Dedicated Pins Pin Symbol In 1 During Function No Out O Reset 42 CLK15 I 15 36 MHz External Crystal Input 43 CLK15 O JO 15 36 MHz External Crystal Output 17 INCLK External Reference CLocK 1 Reference clock from VIP or Central Office 33 VIP_ADDO VIP ADDress Pins 34 VIP_ADD1 Determines the sequential order of up to 3 VIPs in the IOM 2000 frame for the 12 MHz case VIP_ADD 1 0 00 VIP in 1st quarter of IOM 2000 frame 01 VIP in 2nd quarter of IOM 2000 frame 10 VIP in 3rd quarter of IOM 2000 frame 11 Reserved for future connection of VIP in 4th quarter of IOM 2000 frame Currently only the lower addresses are available refer to IOM 2000 description in DELIC LC PB Data Sheet IDDQ Test Mode Forces the Line Interface Unit into power down mode for IDDQ testing 16 IDDQ Oscillator POWer DowN Switches the internal oscillator into power down mode in case that 15 36 MHz input clock is provided by the DELIC 41 POWDN
22. LIC is able to enable or disable this feature via the DELIC BBC command bit Upy Coding The coding technique used in the VIP transceiver is half bauded AMI code with a 50 96 pulse width refer to Figure 10 Binary Value AMI Code with 50 Pulse Width Logical 0 Neutral level Logical 1 Alternate positive and negative pulses A Code Violation CV is caused by two successive pulses with the same polarity Data Sheet 18 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 0 1 0 0 1 1 0 1 1 0 Binary Values Line Signal e g Bits M Bit with Code Violation ITD05393 Figure 10 Coding on the Uy Interface in VIP Scrambling Descrambling B channel data on the Up interface is scrambled to ensure that the receiver at the subscriber terminal gets enough pulses for a reliable clock extraction flat continuous power density spectrum and to avoid periodical patterns on the line The scrambler descrambler polynomial implemented in DELIC complies with ITU T V 27 and OCTAT P Data Sheet 19 2001 03 01 Infineon dicit technologies PEB 20591 PRELIMINARY Interface Description 3 2 2 Up Transceiver The receiver input stages consist of an amplifier equalizer followed by a peak detector adaptively controlling the thresholds of the comparators and a digital oversampling unit Receive Re
23. O signals on the Up and S T lines or by codes sent by the uP to DELIC and transferred to VIP via the IOM 2000 Command and Status interface All options and register settings are described in the DELIC Data Sheet 4 2 Reset At power up a reset pulse RESET low active of at least 1 us must be applied to reset the line interfaces of the VIP The source of the reset can be either the microprocessor or the DELIC RESIND pin which is a delayed reset signal This assures that the VIP is always reset simultaneously with the DELIC and receives stable clock signals by the DELIC after reset 4 3 Initialization After hardware reset each VIP must be initialized and configured by IOM 2000 commands The following steps are required to initialize the VIP 1 DELIC Hardware Reset to synchronize the state machines counters etc 2 VIP Hardware Reset 3 Release resets 4 Read version register from VIP CMD register optional available from VIP version V2 1 and higher Program the VIP if required e g LT T clock source DELIC Program VIP channel mode Upy LT S or LT T closing test loops 7 DELIC Configure each VIP receiver if required e g oversampling D channel handling Data Sheet 36 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Operational Description 4 4 Analog Test Loops Different analog test loops may be switched in the VIP near to the S T or Up line interfaces No
24. P in a Small PBX Solution Data Sheet 7 2001 03 01 Infineon technologies PEB 20591 PRELIMINARY Introduction 8 H PCM H 110 20591 a SWITI optional optional 20571 20591 10 2000 Central Office 2XT r So yP Memory Infineon C166 0008 pc card Figure 6 DELIC PB and VIP in a PC Card for 8 16 S T Interfaces Data Sheet 8 2001 03 01 Infineon technologies PEB 20590 PEB 20591 Pin Description PRELIMINARY 2 Pin Description The VIP is available in an 80 pin Plastic Metric Quad Flat Package P MQFP 80 1 This chapter presents a simple layout of the 80 pin MQFP package with pin and signal callouts and a table of signal definitions 2 1 Pin Configuration top view P MQFP 80 1 SR5b LI5b SR3b LI3b 15 SR8a LI3a Vopa Vopa SSA SSA SX5b SX3b SX5a SX3a VIP ADD1 VIP_ADDO n c n c n c VIP n c Vasa PEB 20590 Vesa DDA DDA 2 1165 125 SR7b LI7b SR1b LI1b SR7a LI7a Vopa SSA SSA SX7b SX1b SX7a angg lt 10a lt 7 0 ao m 5 7715258008 LL 4 a vip 0001 pinout Figure 7 Pin Diagram PEB 20590 Data Sheet 9 2001 03
25. S T channels Ux 8 7 16 5 4 3 2 ST 0 1 2 4 4 4 4 BA VIP 8 20591 All eight channels are programmable to either S T or Up mode Maximum Number of Up and S T channels Upn 8 7 6 5 4 3 2 1 0 S T 0 1 2 3 4 5 6 7 8 S T or Analog Line and S T 1 2000 VOM 2009 Usi Interface Transceiver Interface S 0002 block diagram Figure 1 Top Level Block Diagram of the VIP Data Sheet 4 2001 03 01 Infineon technologies PRELIMINARY Versatile ISDN Port VIP VIP 8 Version 2 1 1 2 VIP Key Features VIP is a universal ISDN transceiver IC for different interface modes S T or Up e Eight 2B D line interfaces with full duplex transceivers S T interfaces at 192 kbit s with line transceivers according to ITU T 1 430 ETSI 300 012 and ANSI T1 605 PEB 20590 PEB 20591 CMOS P MQFP 80 1 interfaces at 384 kbit s with line transceivers according to ZVEI standard Receive timing recovery Conversion between pseudo ternary and binary codes Conversion between Up or S T frames and IOM 2000 frame structures Execution of test loops Frame alignment in trunk applications with maximum wander correction of 25 us Upy interface compatible to
26. V V Clock JTAG Signals Test Interface vip 0006 8logic symbol Figure 3 Logic Symbol PEB 20591 Data Sheet 6 2001 03 01 097 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Introduction 1 4 Typical Applications Typical VIP applications are PBX line cards S T or mixed and small PBXs The following figures illustrate sample configurations in which the VIP shows its flexibility upto 4 ST VIP f N 1 ax 20590 f PCM 1 8E 4 32 18 DELIC d N upto 20570 4 20571 ST 4x 8 20590 ios N Signaling LI 2 048 Mbit s fe if Se i PN 20590 LL Cr Infineon C166 vip_0004_line_card Figure 4 VIP in Mixed S T and Up Line Cards e g 8 S T and 16 Upy amp 2 IOM 2 HV SLIC POM 32 x tir up to 32 TS HV SLIC SLICOFI 2 HV SLIC DELIC PB 4x PEB 20571 2 5 gt 20590 E 2xT Cp qp 3 2 Mbit s Office m for service U d P HP Infineon Supply C166 vip 0007 pbx Figure 5 VI
27. ated external resistors 10 12 5 are required for the transmitter in order to e Adjust the output voltage to the pulse mask nominal 750 mV according to ITU T 1 430 e Meet the output impedance of a minimum of 20 Q transmission of a binary O according to ITU T 1 430 10 12 50 TM C3 S T Overvoltage S Interface Transmitter Protection Connector o 10 12 5 Mla sla sain Diodes 1N4151 or similar Figure 30 External S T Transmitter Circuitry Receiver At the receiver 8 kQ overall resistance is needed in each receive path It is recommended to use two resistors per line as shown in Figure 31 This makes it possible to place a high resistance between the transformer and the diode protection circuit required to pass 96 kHz input impedance test of ITU T 1 430 The remaining resistor protects the VIP receiver from input current peaks o a Overvoltage S Interface pose Protection Connector Diodes 1N4151 BE B or similar L Up to 47 pF for additional noise reduction if required Figure 31 External S T Receiver Circuitry Data Sheet 48 2001 03 01 Infineon technologies PEB 20590 PEB 20591
28. ceive Data Clock CLK15 I RxPLL and Oversampling Comparators Detector Transmit Data Figure 11 Transceiver Functional Blocks Amplitude Equalizer Frequency equi up vsd Figure 12 Equalizer Effect The equalizer compensates the loss of Amplitude of higher frequencies see Figure 12 In order to reach the best performance and range of the Up transceiver it is recommended to use the equalizer with automatic adaptation Data Sheet 20 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description To enable the filter of equalizer inside the VIP set bit TICCMR FIL to 1 please refer to VIP channel config description in DELIC LC PB SW Users Manual The adaptive amplifier control of the equalizer should be set to automatic Set bit TICCMR AAC 1 0 to 00 please refer to VIP channel config description in DELIC LC PB SW Users Manual 3 2 3 Receive PLL The receive PLL RxPLL recovers bit timing from a comparator output signal Note The recommended setting for the receive PLL is integral behaviour This is enabled by setting bit TICCMR PLLINT 1 please refer to VIP channel config description in DELIC LC PB SW User s Manual Comparator threshold The comparator has a threshold of 80 with respect to the signal stored by the peak detector
29. ceiver Receiver Characteristics The receiver input stages consist of a differential amplifier followed by a peak detector and a set of comparators Additional noise immunity is achieved by digital oversampling after the comparators meaning that the sampling of the received bit is controlled digitally and dependent on the mode Command Register The peak detector requires at most 2 us to reach the peak value while storing the peak level for at least 250 us The data detection thresholds are set to 35 of the peak voltage to increase the performance in extended passive bus configurations However they are never lower than 85 mV with respect to the line signal level in order to increase noise immunity The level detector monitors the line input signals to detect whether an INFO signal is present It is possible to indicate an incoming signal during activated analog loop Level Detect Data High Peak Detector Data Low ITS05456 Figure 16 Receiver Functional Blocks 3 3 3 Receive Clock Recovery The VIP generates the internal clocks with a PLL that receives a 15 36 MHz signal via an on chip oscillator either from an external crystal or from the DELIC VIP Operating Mode Clocks Synchronized to LT S or Up mode IOM 2000 interface data clock provided by the DELIC on DCL 2000 pin LT T mode Data clock provided by the Central Office Data Sheet 25 2001 03 01 07 Infineon PEB 205
30. e Structure Data Rates Within a burst the Up data rate is 384 kbit s using a 38 bit frame structure During the 250 us burst repetition period 4 D bits 16 B1 bits and 16 B2 bits are transferred in each direction resulting in a full duplex user data rate of 144 kbit s Data Sheet 17 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description Control and Maintenance Bits Bit Description LF Framing Bit Always logical 1 M M Bit Final bit of the frame Four successive M bits compose a superframe Three signals are carried in this superframe CV Code Violation Bit First bit of the superframe Used for superframe synchronization S Service Bit Third bit of the superframe Accessible via DELIC s command status interface Conveys test loop control information from the PBX to the TE and reports transmission errors from the TE to the PBX far end code violation T T Bit 2nd and 4th bit of the superframe Accessible via DELIC s command status interface Carries the D channel available blocked information for the terminal and the DECT synchronization information DC DC Balancing Bit May be added to the burst to decrease DC offset voltage on the line after transmission of a CV in the M bit position VIP issues this DC balancing bit when transmitting INFO 4 line activated and synchronized and when line characteristics indicate a potential decrease in performance DE
31. e operated in LT T mode only one trunk line may be selected to deliver the reference clock The selection of this trunk line is programmed by the DELIC via IOM 2000 Command bits REFSEL 2 0 and EXREF Note In LT T mode the transmit clock is identical to the recovered receive clock Note The recommended setting for short passive bus in LT T mode is TICCMR OWIN 101 and TICCMR PD 1 For detailed description please refer to VIP channel config command in the DELIC LC PB SW User s Manual 15 36 MHz 15 36 MHz DELIC 192 kHz REFCLK 1 536 MHz e up to 4 or 8 ch VIP LTT Ref vsd Figure 17 Clock Recovery in LT T Mode Data Sheet 27 2001 03 01 07 Infineon technologies PEB 20591 PRELIMINARY Interface Description Jitter Requirements In LT T mode ITU T 1 430 specifies a maximum jitter in transmit direction of 7 to 7 resulting in 730 ns peak to peak This specification will be met by the VIP provided that the master clock source is accurate within 100 ppm 3 3 4 Reference Clock Selection in LT T Mode In LT T configurations the DELIC receives the CO reference clock via the XCLK input pin which is connected to VIP s REFCLK output The VIP reference clock channel is programmed by the DELIC The source may be either one of the 8 VIP channels operated in LT T mode or VIP s INCLK pin when s
32. eas CMD and STAT bits transfer always starts with LSB bit O of any register 2 All registers follow the Intel structure LSB 2 MSB 2 3 Unused bits are don t care x 4 The order of reception or transmission of each VIP channel is always channel 0 to channel 7 A freely programmable channel assignment of multiple VIPs on IOM 2000 e g chO of VIP 0 ch1 of VIP_O chO of VIP 1 ch2 of VIP 0 is not possible Data Sheet 32 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY Interface Description FSC 125 us 12 288 MHz F bit Ch23 Ch24 bitO not used don t care DX DR Ch31 vol bit1 Ch293 Ch24 E not used don t care Ch31 bit1 l Ch bit37 example for 24 channels in U5 mode PN Ch23 bit37 Ch24 bit37 not used Ch31 bit37 Figure 22 IOM 2000 Data Order 3 VIPs with 24 Channels Receive Data Channel Shift In receive direction DR data of all IOM 2000 channels 7 if one VIP is used chO ch23 if three VIPs are used is shifted by 2 channels with respect to the transmitted data channels DX assuming a start of transmission of chO bitO with the FSC signal DELIC is transmitting chO while receiving ch2 via DR the same time etc Data Sheet 33 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description
33. eon technologies PEB 20591 PRELIMINARY Electrical Characteristics 5 Electrical Characteristics This chapter contains the DC and AC specifications as far as available and timing diagrams 5 1 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Storage temperature Ta 65 to 150 IC supply voltage 0 3 to 4 6 V DC input voltage except I Os 7 0 3 to 6 0 V DC output voltage including I Os Vo 0 3to Vp O 3 V output in high or low state DC output voltage including I Os Vo 0 3 to 6 0 V output in tri state ESD robustness 2000 V HBM 1 5 100 pF According to MIL Std 883D method 3015 7 and ESD Ass Standard EOS ESD 5 1 1993 The SX pins are not protected against voltage stress gt 1500 V versus or GND Note Stresses above those listed here may cause permanent damage to the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability Maximum ratings are absolute ratings exceeding only one of these values may cause irreversible damage to the integrated circuit 5 2 Operating Range Parameter Symbol Limit Values Unit min max Power supply voltage 5 3 13 3 47 V Ground Vss 0 oV Voltage applied to input pins Vin 0 0 3 V Operating temperature 0 70 Note In the operating range the functions given
34. everal VIP s are connected to the IOM 2000 interface see Figure 18 Ch 0 REFCLK CH 7 Ch 0 Reference Clock Trunk LT T Ch 7 REFCLK Ch 0 Ch 7 INCLK Figure 18 LT T Reference Clock Channel Selection for Cascaded VIPs Data Sheet 28 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 3 3 5 Receive Signal Oversampling The receive signal is oversampled within the receive clock period and a majority logic is used to reduce the bit error rate in severe conditions As illustrated in Figure 19 each received bit is sampled 29 times at 7 68 MHz clock intervals inside the estimated bit window The samples obtained are compared against a threshold of 35 with respect to the signal stored by the peak detector If at least a number of n samples have an amplitude exceeding the threshold a logical 0 is detected otherwise a logical 1 no signal is assumed The parameter n is programmed by the OWIN command bits A Veni or TRI OV nmm 1121314 15 16 17 18 19 20 2122 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 erived 192 kHz Receive Bit Period c ITD02361 Figure 19 Receive Signal Oversampling in S T Receiver 3 3 6 Elastic Buffer A buffer in the VIP is designed as a wander tolerant system required in LT T and LT S modes In LT T mode the VIP is clock slave
35. external Up or S T interface circuitry is required to close these loops Transparent analog loop data forward path enabled e Non transparent analog loop data forward path blocked External transparent analog loop for board testing Initialization of Test Loops Unlike the LT T state machine the LT S and Up state machines in the DELIC do support loops Consequently neither the C I commands nor indications are provided by the mailbox protocol A loop can be programmed by setting bits TICCMR LOOP and TICCMR EXLP for the respective channel Note For detailed description please refer also to the Application Note Test loops in the In Upy or LT S mode the user may output the loop back data also transparently onto the line interface The selection is performed via IOM 2000 TX command External analog loops are activated by EXLP Command bit refer to Chapter 6 3 Note In order to guaranty that the loop is closed TX must be set to one for the Interface 4 5 Monitoring of Code Violations Any code violation on the S T interface according to ANSI T1 605 or code violations at positions other than the F bit or M bit in the Upy frame result in VIP Status bit FECV being sent to DELIC The check is performed once in every multiframe every 20th 4 kHz S T frame To synchronize the checking DELIC must issue the SH_FSC bit every 40th IOM frame Data Sheet 37 2001 03 01 07 Infin
36. f illegal code violations Chapter 5 Electrical Characteristics Contains the DC and AC specification and timing diagrams Chapter 6 Application Hints Provides information on external line interface circuitry in Upy and S T mode such as transformers and line protection Chapter 7 Package Outlines Chapter 8 Glossary Chapter 9 Index 1 Throughout this document the name VIP will be used to refer to both chip versions PEB 20590 and PEB 20591 Data Sheet 1 2001 03 01 C Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Your Comments We welcome your comments on this document We are continuously trying to improve our documentation Please send your remarks and suggestions by e mail to sc docu comments Q infineon com Please provide in the subject of your e mail device name VIP device number PEB 20590 device version Version 2 1 and in the body of your e mail document type Data Sheet issue date 2001 03 01 and document revision number DS4 Related Documentation Data Sheet for DELIC Version 2 3 or higher PEB 20570 PEB 20571 Data Sheet 2 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Introduction 1 Introduction This chapter gives a general overview of the VIP including a top level block diagram and the logic symbol diagram it lists the key features and presents some typical applications 1 1 Overview VIP Versatile ISDN Port is a highly i
37. f that device or system Life support devices or systems are intended to be implanted in the human or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Data Sheet 054 March 2001 VIP VIP 8 Versatile ISDN Port PEB 20590 Version 2 1 PEB 20591 Version 2 1 Wired Communications _ Infineon technologies Never stop thinking 20590 20591 PRELIMINARY Revision History 2001 03 01 DS4 Previous Version 01 00 Page Subjects major changes since last revision Page 15 Pull ups for the signals TMS TDI TRST Page 34 ID Code for TAP controller Page 29 Maximum wander tolerance Page 35 VIP version register Page 46 Primary inductance for recommended S T transformer Page 46 External S T Receiver Circuitry Page 38 Electrical Characteristics Page 45 Note This revision history is not 100 complete For questions on technology delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide see our webpage at http www infineon com AOP ARCOFI ARCOFI BA ARCOFI SP DigiTape EPIC 1 EPIC S ELIC FALC954 FALC 56 FALC E1 FALC LH IDEC IOM IOM 1 2 IPAT 2 ISAC P ISAC S ISAC S TE ISAC P TE
38. he falling edge of TCK When it has entered state capture DR the levels of all input pins are latched with the rising edge of TCK The in out shifting of the scan vectors is typically done using the instruction SAMPLE PRELOAD Data Sheet 34 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description INTEST INTEST supports internal chip testing When TAP controller is in the state update all inputs are updated internally with the falling edge of TCK When it has entered state capture DR the levels of all outputs are latched with the rising edge of TCK The in out shifting of the scan vectors is typically done using the instruction SAMPLE PRELOAD Note 0011 IDCODE is the default value of the instruction register SAMPLE PRELOAD SAMPLE PRELOAD provides a snap shot of the pin level during normal operation or is used to either preload TDI or shift out TDO the boundary scan test vector Both activities are transparent to the system functionality Note The input pin CLK15 I should not be evaluated The input frequency 15 36 MHz is not synchronous with TCK 6 25 MHZ this may cause unpredictable snap shots on the pin CLK15 I IDCODE The 32 bit identification register is read out serially via TDO It contains the version number 4 bits the device code 16 bits and the manufacturer code 11 bits The LSB is fixed to 1 The code for VIP version 2 1 is 0010 Version
39. ible to OCTAT P PEB 2096 1 1 transformers are required 3 2 1 Frame Structure The Upy interface uses a ping pong technique for 2B D data transmission over the line Upy is always point to point The frame structure of the data transfer between the exchange PBX LT and the terminal TE is depicted in Figure 9 e The PBX starts a transmission every 250 us burst repetition period frame transmitted by the exchange PBX is received by the terminal TE after a given propagation delay t The terminal waits a minimum guard time 1 5 2 us while the line clears Then a frame is transmitted from the terminal to the PBX Data Sheet 16 2001 03 01 Infineon dicit technologies PEB 20591 PRELIMINARY Interface Description The time between the end of reception of a frame from the TE and the beginning of transmission of the next frame by the LT must be greater than the minimum guard time The guard time in TE is always defined with respect to the M bit TE PT LF Framing Bit M Channel Superframe 17000823 CV Code Violation for Superframe synchronization T Transparent Channel 2 kbit s 5 Service Channel 1 kbit s 2 DC balancing bit only sent after a code violation in the M bit position and in special configurations Timings t burst repetition period 250 us ine delay 20 8 us maximum t guard time 5 2 us minimum Figure 9 Interface Fram
40. ion Table 8 Control Bits in S T Mode on DR Line ctrl bit1 data Function 0 0 Logical 0 received on line interface Logical 1 received on line interface 0 1 1 0 Received E bit inverted transmitted D bit LT T only 1 1 F bit Framing received indicates the start of the S frame Table 9 Control Bits in S T Mode on DX Line ctrl bit1 data Function 0 0 Logical 0 transmitted on line interface 0 1 Logical 1 transmitted on line interface 1 0 not used 1 1 F bit Framing transmitted indicates the start of the S frame Note data is always transmitted prior to ctrl via DX DR lines refer to Figure 21 Data Sheet 31 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description FSC 125 DCL 3 072 MHz F bit 1 data ctrl Cho bitO LT S mode B II Ch1 bito data mode Ch2 bitO data DX DR Ch7 bito data Ch0 bit1 ES Ch1 bitO ctrl Ch2 bit1 Chr bito ctrl ChO bit2 Ch1 data Ch2 bit2 Ch1 3 5 7 in S mode LT S Ch0 2 4 6 in Up mode Ch7 data last bit of Up Ch6 bit37 last bit of LT S frame Ch7 bit 23 ctrl Figure 21 IOM 2000 Data Sequence 1 VIP with 8 Channels Note 1 Data transfer IOM 2000 interface always starts with the MSB related to B channels wher
41. l Limit Values Unit Test Condition min max Transmitter output 1 21 0 mA current 26 8 25640 Transmitter output Ly acc to Inactive or during impedance ITU T binary one 1 430 OV lt lt Vy 0 Q during binary zero 1 Nominal value determined by fuses 2 Absolute current limit resulting from the S interface specification CLK15 I H input voltage Via 1 2 V 0 3 IV L input voltage Vi 0 4 V CLK15 O H output voltage Vou 2 4 V 20 L output voltage Vor 0 45 V f 0 Supply Current Operational supply 30 mA supply current current Peak value Vbo 3 3 V 27 5 number of S T m x 47 5 interfaces activated m number of Upy interfaces activated Operational supply Teg 18 mA Mean supply current current Mean typical V 3 3 V value 8 5 number of S T mx6 5 interfaces activated m number of Upy interfaces activated Data Sheet 40 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Electrical Characteristics 5 4 Capacitances 25 Vg 3 3 V 0 17 V Vs 0 V 1 MHz unmeasured pins grounded Table 12 Capacitances except line interfaces and clocks Parameter Symbol Limit Values Unit Test Condition min max Pin capacitance 7 5 5 Recommended 15 36 MHz Crystal Parameters The user has two options to supply the VIP 15 36 MHz input clock via a standard 15 36 MHz crysta
42. l or e via an external source e g connecting the DELIC output pin L1 CLK duty cycle of 40 60 or better is required The on chip oscillator must be powered down via pin POWDN Note It is recommended to supply the VIP 15 36 MHz input clock via the DELIC In case a crystal serial resonance is connected it should meet the requirements shown in Table 13 Table 13 Recommended Crystal Parameters Parameter Symbol Typical Unit Test Condition Values Motional Capacitance C 20 fF Shunt Capacitance 7 pF External Load Capacitance C 30 pF Resonance Resistance R lt 65 Q Frequency Calibration Tolerance lt 100 ppm External CLK 151 Oscillator CLK 151 Signal 15 36 MH m 100 bb Cip CLK 150 NC CLK 150 Crystal Oscillator Mode Driving from External Source Cip 2 2 CL ITS11110 Figure 23 Recommended Oscillator Circuit Data Sheet 41 2001 03 01 07 Infineon technologies PEB 20591 PRELIMINARY Electrical Characteristics 5 6 AC Characteristics T 0 to 70 C V 3 3 V 0 17 V Note Timing measurements are made at 2 0 V for a logical 1 and at 0 8 V for a logical 0 0 5 2 0 Test Points 0 8 750 pF CMOS Input Level l TTL Output Level 1507329 0 5V Figure 24 Input Output Wave Form for AC Tests 5 7 REFCLK Parameter Symbol Limit Values Unit Comment
43. ling 29 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Index S T transceiver 25 Receive clock recovery 25 Receiver characteristics 25 S T transformer 46 S T transmitter performance 45 Short passive bus 26 System integration 7 T controller 34 U Upy coding 18 Upy line interface 16 Control and maintenance bits 18 External circuitry 47 Frame structure 16 scrambling descrambling 19 Up transceiver 20 Receive PLL 21 Receive signal oversampling 21 Up transformer 46 Upy transmitter performance 45 W Wiring configurations in LT S mode 49 Data Sheet 54 2001 03 01 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG o This datasheet has been downloaded from www EEworld com cn Free Download Daily Updated Database 100 Free Datasheet Search Site 100 Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www EEworld com cn Datasheets Cannot Be Modified Witho
44. min max High phase of clock Lus 40 ns Delay of falling edge after falling edge of INCLK Low phase of clock fwi 40 ns Delay of rising edge after rising edge of INCLK Clock period T 651 ns During PLL adjustment this value could change 5 8 Interface Parameter Symbol Limit Values Unit Comment min max DIR delay from DCL 2000 fp 60 ns rising edge Data Sheet 42 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY Electrical Characteristics 5 9 IOM 2000 Interface FSC FSCS DCL_2000 DX DR CMD 22 WN 2 222 STAT 2222 2 lt IOM 2000 vsd Figure 25 IOM 2000 Timing Table 14 IOM 2000 Interface Timing Parameter Symbol Limit Values Unit Notes min typ max DR delay from tor 38 ns DCL_2000 rising edge STAT delay from lerAT 38 ns DCL 2000 rising edge setup time to tcmps 10 ns DCL_2000 falling edge CMD hold time to 10 ns DCL_2000 falling edge Data Sheet 43 2001 03 01 Infineon technologies PEB 20590 PEB 20591 PRELIMINARY Table 14 IOM 2000 Interface Timing Electrical Characteristics Parameter Symbol Limit Values Unit Notes min max FSC setup time before trgcg 2 10 ns DCL_2000 rising edge FSC
45. ntegrated multiple layer 1 transceiver IC connecting to e Up subscriber line interfaces 2 wire and e S T subscriber or trunk line interfaces 4 wire VIP integrates the complete analog line interface circuitry as well as the transceiver logic required for eight full duplex channels Typical VIP applications include PBX line cards S T or mixed and small PBXs VIP must be operated in combination with DELIC which is required for configuration and control activation of VIP s layer 1 transceivers The communication path between the DELIC and the VIP is the serial IOM 2000 interface with a data rate of up to 12 288 Mbit s DELIC also processes the signaling information of each VIP channel by providing a dedicated HDLC controller per subscriber For more information on DELIC and the IOM 2000 interface please refer to the DELIC LC PB Data Sheet Infineon Technologies DELIC DSP Embedded Line and Port Interface Controller The DELIC is available in two versions PEB 20570 and PEB 20571 Data Sheet 3 2001 03 01 07 Infineon technologies PEB 20591 PRELIMINARY Introduction The VIP is available in two different versions which differ in the possible interface combinations Table 1 VIP Product Family Device Available Interfaces VIP 20590 Four channels are programmable to either S T or Up mode and the other four channels can be operated in Up mode only Maximum Number of Up and
46. ort Upn Two wire interface Zentralverband Elektrotechnik und Elektroindustrie e V Data Sheet 52 2001 03 01 e Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Index 9 Index 42 A L AC characteristics 42 Logic symbol Analog test loops 37 PEB 20590 6 Application hints 46 20591 6 Applications 7 50 O Block diagram 4 Operating modes 25 Operating range 38 Operational description 36 Capacitances 41 Clock synchronization 25 Crystal parameters 41 D DC characteristics 39 E Extended passive bus 26 External circuitry 46 F Features VIP 5 Initialization 36 Interface IOM 2000 interface 30 JTAG boundary scan test inter face 34 Overview 16 S T line interface 22 line interface 16 IOM 2000 Frame Structure 31 IOM 2000 interface 30 J Jitter requirements 28 JTAG boundary scan test interface 34 JTAG boundary scan test interface timing Data Sheet Oscillator circuit 41 51 Pin descriptions 9 Clock signals and dedicated pins 14 IOM 2000 interface 13 JTAG boundary scan test inter face 15 Power supply andreset 15 UPN and S T line interface 12 and S T line interface 11 Pin diagram PEB 20590 9 20591 10 P MQFP 80 1 51 Product family VIP 4 R Reference clock selection 28 Reset 36 5 S T coding 24 S T line interface 22 Data rates 24 Elastic buffer 29 External circuitry 47 Frame structure 23 Receive signal oversamp
47. th respect to the transmit frame Note If one VIP has channels working in LT S and Up mode then the F bits appear the S interface 6 Up clocks nominal case later than the F bits on the Upy lines within the same sync frame Note The recommended setting for short passive bus in LT S mode is TICCMR OWIN 001 and TICCMR PD 0 For detailed description please refer to VIP channel config command in the DELIC LC PB SW User s Manual Data Sheet 26 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 3 3 3 2 LT T Mode Programmed by DELIC IOM 2000 Command bits MOSEL 1 0 00 MODE 2 0 001 In LT T applications the VIP DELIC system operates as slave to the central office clock The 192 kHz receive bit timing is recovered via RxPLL from the receive data stream on the trunk line interface that was selected as clock source The RxPLL also provides a 1 536 MHz clock synchronous to the Central Office clock adaptive timing recovery which in LT T applications is used to synchronize the DELIC clock generator via the IOM 2000 REFCLK line refer to Figure 17 The RxPLL tracks every 250 us after detecting the phase between the framing bit transition F L bit in S T frame of the receive signal and the recovered clock A phase adjustment is done by adding or subtracting 65 ns or 130 ns to or from the 15 36 MHz clock depending on PLLS If several VIP or several S T lines ar
48. to the CO and the data clocks of the S T interface and the IOM 2000 interface have a time dependent phase relationship The buffer compensates a maximum phase wander of 20 us A slip detector indicates when this limit is exceeded The SLIP bit in VIP Status Register issues a warning to the DELIC when a slip of 20 us in either direction was detected The VIP buffers are reset to their default positions automatically Note In case of frame slip the phase relationship between the IOM 2000 interface and the S T interface is arbitrary A re alignment of the wander buffer after a slip may result in loss of data Data Sheet 29 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 3 4 IOM 2000 Interface Overview The IOM 2000 interface connects up to three VIPs to DELIC DELIC as the communication controller performs parts of the layer 1 protocol which enables flexible and efficient operation of the VIP Note For detailed description of IOM 2000 including the command and data interface please refer to the DELIC Data Sheet IOM 2000 Description Frame synchronization IOM 2000 uses an 8 kHz FSC Data interface Data is transmitted via DX line from DELIC to VIP with DCL 2000 rising edge Data is received via DR line from VIP to DELIC sampled with DCL 2000 falling edge Command Status Configuration and control information of VIP s layer 1 interface transceivers is exchanged
49. ut In the appropriate TAP controller state test data or a instruction is shifted out via this line 55 TRST Test ReSeT internal pull up Provides an asynchronous reset to the TAP controller state machine Data Sheet 15 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 3 Interface Description The VIP provides four types of external interfaces Up line interfaces S T line interfaces an IOM 2000 interface and a JTAG boundary scan test interface These interfaces are described in the following sections 3 1 Overview of Interfaces The VIP provides the following system interfaces Upy line interfaces The VIP provides up to 8 independent Up line interfaces for connection of ISDN terminals or DECT base stations S T line interfaces The PEB 20590 provides up to 4 independent S T line interfaces up to 8 for PEB 20591 They can be operated in subscriber mode LT S or trunk mode LT T e 10 2000 interface Up to three VIPs can be connected to one DELIC IOM 2000 interface VIP s transceivers are initialized and controlled by the DELIC JTAG boundary scan test interface The VIP provides a standard test interface according to IEEE 1149 1 User specific instructions are implemented to generate periodic test patterns on the line The TAP controller has an own reset input 3 2 Line Interface The functionality is compat
50. ut Permission Copyright O Each Manufacturing Company
51. ve Signal Oversampling in S T Receiver 29 Overview of IOM 2000 Interface Structure Example with One VIP 30 IOM 2000 Data Sequence 1 VIP with 8 Channels 32 IOM 2000 Data Order 3 VIPs with 24 Channels 33 Recommended Oscillator 41 Input Output Wave Form for AC 42 IOM 2000 43 gen cee 44 1 1 Transformer 46 External Transceiver Circuitry of the VIP in Upy Mode 47 Overview of External Circuitry of the VIP in S T Mode 47 External S T Transmitter 48 External S T Receiver 48 Wiring Configurations in User Premises LT S Mode 49 Internal and External Loop Back Modes 50 2001 03 01 Infineon PEB 20590 technologies PEB 20591 List of Tables Page Table 1 VIP Product Family gt eee he ee eee oe RR RUE he Redde rik ak Rede 4 Table 2 20590 Upy and S T Line Interface 11 Table 3 20591 Upy and S T Line Interface 12 Table 4 IOM 2000 Interface 13 Table 5 Clock Signals and Dedicated 14 Table 6 Power Supply and
52. via CMD and STAT lines Data Command Clock Data and commands for one VIP are transmitted at 3 072 MHz When DELIC drives 2 or 3 VIPs the transmission rate is increased Reference clock In LT T mode the VIP provides a reference clock synchronized to the exchange In LT S or Up mode DELIC is always the clock master to VIP S T bit 1 Data Transmit Receive in S T mode dat trl 3 i DX DR ata ctr f 3 072 MHz 2 x 8 x 192 kbit s Usi bit O Data Transmit Receive for Up mode data f23 072 MHz 8 x 384 kbit s FSC VIP DELIC DR gt STAT E Channel 7 4 Figure 20 Overview of IOM 2000 Interface Structure Example with One VIP Data Sheet 30 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 3 4 1 IOM 2000 Frame Structure 3 4 1 1 Data Interface On the ISDN line side of the VIP data is ternary coded Since the VIP contains logic to detect the level of the signal only the data value is transferred via IOM 2000 to DELIC Up Mode In Up mode only data is sent via the IOM 2000 data interface S T Mode In S T mode data and control information is sent via IOM 2000 data interface Every data bit has a control bit associated with it Thus for each S T line signal 2 bits are transferred via DX and DR BitO is assigned to the user data and bit1 carries control informat
53. write ONEs F Auxiliary Framing Bit See section 6 3 in ITU 1 430 N N F B1 B1 Channel Data User data B2 B2 Channel Data User data Data Sheet 23 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description Bit Description A Activation Bit 0b gt INFO 2 transmitted A 1b gt INFO 4 transmitted S S Channel Data Bit 1 and S2 channel data M Multiframing Bit M 1b gt Start of new multi frame Data Rates The S T transmission rate is 192 kbit s 36 bits user data and 12 bits control and maintenance Frames are transmitted with a 2 bit offset in TE LT T LT S direction S T Coding The coding technique used on the S T interface is a full bauded AMI code with 100 pulse width refer to Figure 15 Binary Value AMI Code with 100 Pulse Width Logical 0 Alternate positive and negative pulses There are two exceptions The first binary 0 following the first DC balancing bit is of the same polarity as the DC bit The F bit is always at positive level required code violations Logical 1 No line signal 0 V Binary Values 0 1001 1000 1 1 M Line Signal OV Nocna 1000322 Figure 15 S T Interface Line Code without Code Violation Data Sheet 24 2001 03 01 07 Infineon PEB 20590 technologies PEB 20591 PRELIMINARY Interface Description 3 3 2 S T Trans
54. z Receive Bit Period 1007407 Figure 13 Receive Signal Oversampling on Up Interface 3 3 S T Line Interface The functionality is compatible with that of QUAT S PEB 2084 External protection circuitry is reduced and 1 1 transformers are required Data Sheet 22 2001 03 01 07 Infineon technologies PEB 20591 PRELIMINARY Interface Description 3 3 1 Frame Structure The S T interface uses two pairs of copper wires dedicated to transmit and receive for 2B D data transfer It builds a direct link between the VIP and connected subscriber terminals or the Central Office It supports point to point or point to multipoint modes Data and maintenance information is accessible by DELIC the IOM 2000 interface 48 Bits in 250 DL F Lj E D A f B2 E D D 5 B2 E DL F L Bits Offset DL F Lj D L B2 L D B1 L 0 B2 1L DL F L 17003993 Figure 14 Frame Structure at Reference Points 5 and T ITU T 1 430 Bit Description F Framing Bit 0b code violation identifies a new frame always positive pulse L DC Balancing Bit L 0b gt number of binary ZEROs sent after the previous L bit was odd D D Channel Data Signaling data specified by user E D Channel Echo Bit _ E D if D channel is not blocked otherwise ZEROs always over
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