NCPCI-PMC_manual
Contents
1. Table 4 Table 9 Status Register 1 Bit Read Write Reset Status Information Number Value Bit 7 R 0 notused Bit 6 R 0 notused Bit 5 R 0 notused Bit4 R 0 cPCI geographical address bit GA4 Bit 3 R 0 cPCI geographical address bit Bit 2 R 0 cPCI geographical address bit GA2 Bit 1 R 0 cPCI geographical address bit GAI Bit 0 R 0 cPCI geographical address bit GAO 5 8 6 Status Register 2 Status Register 2 is accessed with address offset 0x5 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 10 Status Register 2 Bit Read Write Reset Status Information Number Value Bit 7 R 0 used Bit 6 R 0 notused Bit 5 R 0 not used Bit 4 R 0 _ auxiliaury geographical address bit SGA4 Bit 3 R 0 __ auxiliaury geographical address bit SGA3 Bit 2 R 0 _ auxiliaury geographical address bit SGA2 Bit 1 R 0 cPCIauxiliaury geographical address bit SGA1 Bit 0 R 0 cPCIauxiliaury geographical address bit SGAO Version 2 2 N A T GmbH 23 NcPCI PMC Technical Reference Manual 5 8 7 Status Register 3 Status Register 3 is accessed with address offset 0x6 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 11 St2. see chapter 7 on known bugs SGND is the protective GND of the board case and shielding connected also to the front panel Version 2 2 O N A T GmbH 44 NcPCI PMC Technical Reference Manual 7 NcPCI PMC Programming Notes 7 1 Programming the PCI Bridges 7 1 1 Intel 21555 Bridge Programming The Intel 21555 Bridge which bridges between the Compact PCI bus and the internal PCI bus is initialized by two ways Power Up configuration and EEPROM load of setup information on various Reset conditions 7 1 1 1 Intel 21555 Power Up Configuration Power Up configuration is done by pulling the data pins of the ROM interface to specific logic levels during Power Up Reset Details are found in the table below Table 35 Intel 21555 Power Up Configuration internal PCI bus central functions enabled PCI arbiter internal PCI bus enabled S CLK O disabled Sync Mode asynchronous Primary Lockout Reset Value no lockout none pulled high cPCI bus 64 bit enable not used 7 1 1 2 Intel 21555 Configuration by EEPROM Load When reset the 121555 loads several registers from EEPROM if available On the NcPCI PMC a 93LC66A serial EEPROM is connected to the serial ROM interface of the 121555 The following data is loaded please consult the 121555 User s Manual for a detailed description Table 36 121555 EEPROM Configuration Serial ROM Hex Value Address 0x0 80 00 00 00 00 80 06 00 00 02 06 00 00 00 80 06 Data bytes 0x0 0x42
3. 5 25 Version 2 2 O N A T GmbH 4 NcPCI PMC Technical Reference Manual 5 8 8 3 TDM Bus Routing Switch Configuration Pin eese 25 3 8 9 Control Status Register Insira usate epa Pe e e RA P oun 26 5 6 10 Lattice Revision Status Register te tet eee tense herbe rte ERER 27 5 6 11 Board Hardware Revision Status Register eese 27 5 9 PORT PIN ASSIGNMENT OF THE PERIPHERAL 28 5 9 1 Port Pins of the 18110 H 110 TSI Controller esee 26 6 CONNECTORS pt 29 6 1 CONNECTOR AND JUMPER OVERVIEW 29 6 2 CONNECTOR JP2 FRONT PANEL EJECTOR SWITCH 30 6 3 CONNECTOR JTAG CHAIN OF ONBOARD 8 2 0 000000000000000000000 000000000 30 6 4 CONNECTOR JP4 CPLD PROGRAMMING PORT 30 6 5 PMG SLOT T CONNECTORS n rre titre pei olere lieto EN 31 6 5 1 Slot 1 Connector P11 3l 6 5 2 PMCSlot Connector Pl2 essaie iret iei esas deed ee idee edv sedis 32 6 5 3 Slot 1 Connector 33 6 5 4 Slot 1 Connector P14 PMC 1 34 6 5 5 Slot 2 Connector P21 35 6 5 6 Slot 2 Connector P22 36 6 5 7
4. Figure 1 NcPCI PMC cPCI Intelligent Carrier Board for PMC Modules Backplane Connectors H 110 PCI gt PCI TSI Bridge PMC Module PMC Module e g e g NPMC 8266 OC3 NPMC 8280 4E1 T1 J1 Back View Back View N 21 kil The NePCI PMC has the following major features Intel 21555 PCI PCI bridge cPCI bus gt internal PCI bus 1 64 bit 66 MHz cPCI hot swap capable cPCI 64 bit 66 MHz PCI Rev 2 2 2 PMC slots 64 bit 66 MHz PCI Rev 2 2 P1386 1 Draft 2 4a Agere T8110 TSI controller with H 110 SCSA bus interface Version 2 2 N A T GmbH 9 NcPCI PMC Technical Reference Manual Figure2 NcPCI PMC Block Diagram cPCI P1 PMC Slot 1 PCI to PCI bridge Mrs P2 P4 2 H 110 T8110 SCSA 4 ay H 110 P4 TSI PMC Slot 2 1 1 Board Features e Interfaces cPCI The NcPCI PMC includes a 32 64 bit 33 66 MHz Compact PCI bus interface This is implemented by an Intel 121555 PCI gt PCI bridge The cPCI interface supports hot swap int PCI The NcPCI PMC implements a 64 bit 66 MHz PCI bus which connects the 121555 PCI PCI bridge to the 2 PMC slots implemented according to IEEE P1386 1 Draft 2 4a int TDM The NcPCI PMC implements 2 internal TDM interfaces one each for every PMC I O connector The
5. Table 7 Interrupt Mask Control Status Register 1 Bit Read Write Reset Status Information Control Setting Number Value Bit 7 R W 0 slot 2 signal mask bit Bit 6 R W 0 slot 2 INTC signal mask bit Bit 5 R W 0 PMC slot 2 signal mask bit Bit 4 R W 0 PMC slot 2 INTA signal mask bit Bit 3 R W 0 PMC slot 1 INTD signal mask bit Bit 2 R W 0 slot 1 INTC signal mask bit Bit 1 R W 0 PMC slot 1 INTB signal mask bit Bit 0 R W 0 PMC slot 1 INTA signal mask bit 5 8 4 Interrupt Mask Control Status Register 2 Interrupt Mask Control Status Register 2 is accessed with address offset 0x3 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 8 Interrupt Control Status Register 2 Bit Read Write Reset Status Information Control Setting Number Value Bit 7 R 0 not used Bit 6 R 0 not used Bit 5 R 0 not used Bit 4 R 0 not used Bit 3 R 0 not used Bit 2 R 0 not used Bit 1 R W 0 T8110 CLKERR signal mask bit Bit 0 R W 0 T8110 SYSERR signal mask bit Version 2 2 O N A T GmbH 22 NcPCI PMC Technical Reference Manual 5 8 5 Status Register 1 Status Register 1 is accessed with address offset 0x4 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in
6. and the TDM routing is compatible to NcPCI PMC version 1 4 and older Routing between the local TDM buses of the PMC s and the T8110 TSI can be programmed as follows by programming OE D16 31 Table 13 local TDM Bus routing D16 31 PMC 1 local PMC11ocal 2 local PMC 2 local TDM 00 15 TDM D16 31 D0 15 D16 31 lt gt T8110 lt gt T8110 T8110 T8110 TDM 0 00 15 D16 31 D16 31 D16 31 Kg D0 15 bused D16 31 bused D0 15 bused D16 31 bused N A T GmbH 23 NcPCI PMC Technical Reference Manual OE D16 31 0 is intended to be used with PMCs which connect to the T8110 TSI with 16 TDM data lines each like in a classical SCSA application The N A T 4 1 is such a module In order to make use of all 32 TDM data lines of the T8110 for these modules also the TDM data lines DO 15 of PMC2 are swapped onto the TDM data lines D16 31 For OE D16 31 1 all 32 TDM data lines of the PMCs are connected to the T8110 TSI but they are bused By setting this feature the user may not only distribute the number of TDM data lines from each PMC to the TSI freely but may also specify a routing between the 2 PMC modules without interference of the T8110 Hence for all applications NOT needing the compatibility mode to older NcPCI PMC versions the setting 016 31 1 is preferable 5 8 9 Control Status Register 5 Control Status Register 5 is accessed with addres
7. 9 ____ 52 14 35 4 33 T Version 2 2 O N A T GmbH 41 NcPCI PMC Technical Reference Manual Table 32 Compact PCI Backplane Connector J2 Rows D F Pin No Row D Row E Row F 4 0 5 CIBE4 0 6 GND 7 ADS8 ____ 8 GND 9 gt _____ 5 _ mo paa a 12 GND u GND Version 2 2 O N A T GmbH 42 NcPCI PMC Technical Reference Manual 6 6 3 Compact PCI Backplane Connector J4 Compact PCI backplane connector J4 carries the H 110 bus signals Table 33 Compact PCI Backplane Connector J4 Rows A C Pin No Row A Row C Version 2 2 818151513 e o 8513 GA3 SGA3 nc ___ SGA3 O N A T GmbH SGA2 43 NcPCI PMC Technical Reference Manual Table 34 Compact PCI Backplane Connector J4 Rows D F Pin No RowD Row E Row F Signal Signal CT D2 cT D3 GND Jen 4 33V GND 5 NETRE2 GND 6 4 CT NETREF GND 7 EL i m FSYNC lobo ae FRAMEA i qus CT_FRAMEB Key Area nc nc nc n nc n nc n nc n nc SGND n nc SGND nc nc SGND GAI SGND SGAI SGAO SGND
8. CE sign can ce found on the PCB 2 3 4 Product Safety The board complies to EN60950 and UL1950 Version 2 2 N A T GmbH 15 NcPCI PMC Technical Reference Manual 3 Location Overview The Figure 3 Location diagram of the NePCI PMC shows the position of the important components Depending on the board type it might be that the board does not include all components named in the location diagram Figure 3 Location Diagram of NCPCI PMC LEDs T8110 H 110 i21555 TSA 64 Bit PCI PCI PMC Slot 1 PMC Slot 2 connectors Version 2 2 O N A T GmbH 16 NcPCI PMC Technical Reference Manual 4 TDM Bus and H 110 Bus Controller Signal routing and data flow between the T8110 TSI device and the PMC slot I O connectors is shown in Figure 4 below Figure4 Local TDM Bus Organisation and Synchronisation The TDM data are routed through the T8110 TSI device Hence any timeslot switching between H 110 bus and the local TDM buses is possible The TSI device derives its time base from one of the SREF 8K or signals coming from the PMC modules or from the H 110 bus From this input it generates FSYNC and SCLK for the local SCbuses to synchronize to For detailed information please refer to the Agere T8110 User s Manual Version 2 2 N A T GmbH 17 NcPCI PMC Technical Reference
9. H 110 signal NETREF1 to T8110 LREF2 input module 2 drives H 110 signal 1 B to T8110 LREF3 input Figure 7 shows the local TDM bus and SCbus routing between T8110 and the PMC modules Figure7 T8110 local TDM bus to shared SCbus Routing SREF 8K SCbus DO 31 T8110 TSI SCbus DO 31 SCLK SCLKX2 FSYNC SCbus DO 31 SREF_8K Version 2 2 N A T GmbH 48 NcPCI PMC Technical Reference Manual 8 Known Bugs and Restrictions In hardware versions Rev 1 0 Rev 1 2 of the NcPCI PMC the H 110 bus signals FRAME and FRAME B are swapped As a software workaround enable both A and B signals on the clock master device then the T8110 on the NcPCI PMC will always lock correctly no matter whether it synchronizes to A or B clocks Fixed in Rev 1 3 and higher The Board Hardware Revision Status Register as described in chapter 5 8 11 is available in Rev 1 3 and higher The Lattice Revision Status Register as described in chapter5 8 10 is available in Rev 2 0 and higher PMC module Slot ID programming as described in chapter 5 8 9 Control Status Register 5 is available in Rev 2 0 and higher TDM bus routing as described in chapter 5 8 8 3 TDM Bus Routing Switch Configuration Pin is available in Rev 2 0 and higher Version 2 2 N A T GmbH 49 NcPCI PMC Technical Reference Manual Appendix A Reference Documentation 1 Intel Corp 21555 Non Transpare
10. Manual 5 Hardware 5 1 Memory Map PCI All addresses on the internal PCI bus are set up by programming the corresponding address registers of the PCI devices and may be chosen by the user The following correspondence applies for PCI ADxx lines and IDSEL routing Table 3 IDSEL Routing for internal PCI Bus IDSEL 121555 programmable PCI arbiter PMC slot 1 AD31 programmable PMC expansion slot PMC slot 2 AD30 programmable PMC expansion slot 5 2 Memory Map local Addresses on the internal local bus minibridge of the 121555 are to be seen as offset to the minibridge base address programmed for the 121555 PCI bridge device The following correspondence applies Table 4 local Memory Map T8110 0x00 0000 H 110 TSI device Status Control 0x10 0000 Status Control registers registers see below 5 3 Interrupt Structure The different PCI PMC interrupts are generated by a logical Wired Or of the interrupt sources of the respective PCI buses The interrupt sources are readable by status registers Every interrupt source on the NcPCI PMC is maskable by software The status of these mask registers is also readable Refer to chapter 5 8 for a detailed description Version 2 2 N A T GmbH 18 NcPCI PMC Technical Reference Manual 5 4 5 5 5 6 5 6 1 5 6 2 Hot Swap Capability The NePCI PMC is assembled with the hot swap feature enabled and PCI signals are precharged to 1V during boa
11. Slot 2 Connector P23 isses itineri 37 6 5 8 Slot 2 Connector P24 2 iccccccsscccsssccssssessceessssessceessesssseeesseseneeecsaeseseeeesaecnseeeesaees 38 6 6 COMPACT PCI BACKPLANE CONNECTORS 39 6 6 1 Compact PCI Backplane Connector 39 6 6 2 Compact PCI Backplane Connector 2 41 6 6 3 Compact PCI Backplane Connector 4 43 7 NCPCI PMC PROGRAMMING 8 1 1 1 45 74 PROGRAMMING THE PCT BRIDGES OPEP US 45 7 1 1 Intel 21555 Bridge Programming 45 7 1 1 1 Intel 21555 Power Up Configuration 45 7 1 1 2 Intel 21555 Configuration by EEPROM Load essere ennt 45 7 2 PROGRAMMING THE H 110 TSI 46 72 1 18110 Configuration by EEPROM Load esee 46 7 2 2 T8110 local TDM bus Programming Examples eese eee eene 46 7 2 2 1 T8110 connected to 2 PMCs with private 5 5 5 46 7 2 2 2 T8110 connected to 2 PMCs with a shared 5 5 48 8 KNOWN BUGS AND 5 8 49 APPENDIX REFE
12. T GmbH 30 NcPCI PMC Technical Reference Manual 6 5 PMC Slot 1 Connectors 6 5 1 PMC Slot 1 Connector P11 Table 21 PMC Slot 1 Connector P11 PCI Signal PCI Signal 5 INTBPMCI INTCPMCI 16 O 7 BUSMODEIPMCI 5V 8 9 INTDPMCI PCLRSVI GND 5 12 13 CLKPMCI GND 4 k 59 AD2 ADU 60 Pin 3 3Vaux is not connected to the PMC slot PCI signals SDONE and SBO are not connected to other components just pulled high JTAG signal TCK is pulled low V I O pins are connected to 3 3V Version 2 2 N A T GmbH 31 NcPCI PMC Technical Reference Manual 6 5 2 PMC Slot 1 Connector P12 Table 22 PMC Slot 1 Connector P12 PCI Signal PCI Signal 1 12V TRST 2 5 ___ 7 8 9 PCLRSV PCIRSVA 0 59 GND PCIRESV 60 JTAG signals TMS TDI and TDO are not connected to the PMC slot JTAG signal TRST is pulled low Signals labelled xxx PMCx are private for this PMC slot signals without this attachment are bused to both PMC slots Version 2 2 N A T GmbH 32 NcPCI PMC Technical Reference Manual 6 5 3 PMC Slot 1 Connector P13 Table 23 PMC Slot 1 Connector P13 1 PCL 5 6 8 46 7 ____ 0 8 9 4 10 59 PCIRESV PCI RESV 60 V I O pins are connected to 3 3V Version 2 2 O N A T GmbH 33 NcPCI PM
13. Table 29 Compact PCI Backplane Connector JI Rows 39 Table 30 Compact PCI Backplane Connector JI Rows D 40 Table 31 Compact PCI Backplane Connector J2 Rows 4 Table 32 Compact PCI Backplane Connector J2 Rows D 42 Table 33 Compact PCI Backplane Connector J4 Rows A 43 Table 34 Compact PCI Backplane Connector J4 Rows D 44 Table 35 Intel 21555 Power Up Con guma Nana 45 Table 36 121555 EEPROM Configuration 45 Version 2 2 O N A T GmbH 7 NcPCI PMC Technical Reference Manual Conventions If not otherwise specified addresses and memory maps are written in hexadecimal notation identified by Ox Table 1 gives a list of the abbreviations used in this document Table 1 List of used abbreviations Abbreviation Description Bitbinay Bo Jl K M mega factor 10 0000 in hex factor 1 048 576 in MHz 000 MHz ______ 1 000 000 Herz SCbus Time Slot Interchange Bus of the SCSA subset of H 110 bus Version 2 2 O N A T GmbH 8 NcPCI PMC Technical Reference Manual 1 Introduction The NcPCI PMC is a high performance PCI Mezzanine Card carrier board especially suited for Telecom and networking applications
14. aeos stereo re sees esta Petr tir td dta cei Ah 23 Table 107 Status Register 25 a mahasa eas 23 Table Status Register dla aed 24 Table 12 Control Status Register 24 Table 13 gt local TDM B s routing rn R nG Ti qup ties 25 Table 14 Control Status Register NN BIBE 26 Table 15 Board Hardware Revision Status Register sss 27 Table 16 Board Hardware Revision Status 27 Table 17 Port Pins of T8110 TSI Controller 02 0200000 00000 0 000000000000 28 Table 18 Front Panel Ejector naa 30 Table 19 JTAG Chain of onboard Devices kpa NG Dues ren NAAN 30 Table 20 Lattice programming Ort yeh dt qe er Dee desse Y SUE aes 30 Table 212 Slot I Connector PW arta ttd ttp 31 lable22 PMC Slot Connector E eaa e E 32 Table 23 PMC Slot 1 Connector P13 MM AN NG 33 Table 24 Slot l Connector Paa uice e oet Vou incest aks 34 Table 25 PMC Slet2 Connector 35 Table 20 PMC Slot 36 Table 277 a PMC Slot 2 Connector P23 oec cei etc entier 37 Table 28 PMC Slot 2 eu Ne Lan 38
15. are loaded into the 121555 as register setup Data bytes from 0x44 up are N A T coding of board parameters Version 2 2 N A T GmbH 45 NcPCI PMC Technical Reference Manual 7 2 Programming the H 110 TSI Controller 7 2 1 7 2 2 The T8110 H 110 Timeslot Interchange Controller is located on the parallel ROM interface of the i21555 PCI bridge Some setup information also resides in an EEPROM which is loaded on Reset T8110 Configuration by EEPROM Load The EEPROM connected to the T8110 is delivered empty default i e it reads OxFF in all cells This results in the T8110 ignoring it Hence all initialisation has to be done by external software The user may program the EEPROM according to his needs T8110 local TDM bus Programming Examples There are many different applications to which the bidirectional TDM bus between the T8110 TSI and the PMC modules may be adapted In the following paragraphs two possible and common applications are described and the settings necessary for them The first example describes the connection to classical SCSA modules i e with a SC4000 TSI device with 16 TDM data lines Transmit and Receive data paths are set to be 8 bits wide each The second example describes the connection to modules with H 110 interface i e with a CT812 TSI device with 32 TDM data lines Due to compatibility reasons SCbus protocol and control signal set is used but the data bus is extended to 32 bits in order
16. numbers given above are the maximum values if both PMC slots are populated and each module draws the maximum current allowed from one supply The overall maximum power allowed to be drawn by both modules together is 15W according to the PMC spec The power supply of the NcPCI PMC supports PPMC modules with up to 30W in total for both slots In order to prevent excessive loading of the 3 3V supply of the NcPCI PMC the 3 3V supply for the PMC modules is derived from the 5V supply of the NePCI PMC by onboard switching regulators Automatic Power Up In the following situations the PMC will automatically be reset and proceed with a normal power up The voltage sensor generates a reset e when any of the voltages supervised fall out of 5 tolerance supervised voltages are 5V 3 3V e when the system slot board signals a PCI Reset Version 2 2 N A T GmbH 13 NcPCI PMC Technical Reference Manual 2 3 Statement on Environmental Protection 2 3 1 2 3 2 Compliance to RoHS Directive Directive 2002 95 EC of the European Comission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS predicts that all electrical and electronic equipment being put on the European market after June 30th 2006 must contain lead mercury hexavalent chromium polybrominated biphenyls PBB and polybrominated diphenyl ethers PBDE and cadmium in maximum concentration values of 0 1
17. C Technical Reference Manual 6 5 4 Slot 1 Connector P14 PMC 1 I O Table 24 PMC Slot 1 Connector P14 CC TDI _ s Wo _ vo 162 GND 1 CI DI 7 or wo Cro ___ 9 PN SERI ew 5 19 wo 32 9 Co C30 SS b ho ho 2 INC 3 ING 185 ho ___ _ NC NC NC NC GND NC NC NC NC NC NC NC INC 9 o __ 60 NC NC Version 2 2 N A T GmbH 34 NcPCI PMC Technical Reference Manual 6 5 5 PMC Slot 2 Connector P21 Table 25 PMC Slot 2 Connector P21 PCI Signal PCI Signal a No 02 T 5 2 6 PMC2 9 INTDPMC2 PCLRSVI 0 59 2 GO Pin 3 3Vaux is not connected to the PMC slot The same applies to PCI signals SDONE and SBO JTAG signal TCK is pulled low V I O pins are connected to 3 3V Version 2 2 O N A T GmbH 35 NcPCI PMC Technical Reference Manual 6 5 6 PMC Slot 2 Connector P22 Table 26 PMC Slot 2 Connector P22 PCI Signal PCI Signal 1 12V TRST 2 5 GD __ 6 7 GND 8 9 PCLRSV PCIRSVA 0 59 GND PCIRESV 60 JTAG signals TMS TDI and TDO are not connected to the PMC slot JTAG signal TRST is pulled low Signals labelled xxx PMCx are private for this PMC slot signals w
18. Front Panel Led yellow LED1 2 Front Panel Led orange GPO LEDI 1 Front Panel Led red A bit value of 0 logic low level turns a LED on a bit value of 1 logic high level turns it off See also Figure 5 for LED locations Version 2 2 N A T GmbH 28 NcPCI PMC Technical Reference Manual 6 Connectors 6 1 Connector and Jumper Overview Figure 5 Connectors and Jumpers of the NCPCI PMC Please refer to the following tables to look up the pin assignment of the PMC Version 2 2 N A T GmbH 29 NcPCI PMC Technical Reference Manual 6 2 Connector JP2 Front Panel Ejector Switch Table 18 Front Panel Ejector Switch Switch Contact The switch contact of the front panel ejector switch closes to GND when pressed Default position is open 6 3 Connector JP3 JTAG chain of onboard Devices Connector JP3 connects the onboard devices 121555 PCI bridge and T8110 TSI to a TDI TDO daisy chain JTAG chain The device order in the chain is as described above Table 19 JTAG Chain of onboard Devices 5214 de Zo mo GND 8 9 RST 0 6 4 Connector JP4 CPLD Programming Port Connector JP4 connects the JTAG or programming port of the Lattice CPLD devices The CPLD devices are connected to a TDI TDO daisy chain Table 20 Lattice programming port 5 TD 33V e 7 9 5 0 Version 2 2 N A
19. Lattice CPLD revision Bit 4 R Lattice CPLD revision Bit 3 R Lattice CPLD revision Bit 2 R Lattice CPLD revision R Lattice CPLD revision Bit 0 R Lattice CPLD revision 5 8 11 Board Hardware Revision Status Register The Board Hardware Revision Status Register is accessed with address offset OxF to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 16 Board Hardware Revision Status Register Bit Read Write Status Information Number Bit 7 R hardware PCB layout revision Bit 6 R hardware PCB layout revision Bit 5 R hardware PCB layout revision Bit 4 R hardware PCB layout revision Bit 3 R hardware PCB layout revision Bit 2 R hardware PCB layout revision Bit 1 R hardware PCB layout revision Bit 0 R hardware PCB layout revision Version 2 2 N A T GmbH 27 NcPCI PMC Technical Reference Manual 5 9 Port Pin Assignment of the Peripheral Devices 5 9 1 Port Pins of the T8110 H 110 TSI Controller The T8110 H 110 Controller supplies an 8 bit parallel port which is wired to the following control signals Table 17 Port Pins of the T8110 TSI Controller Port Pin Signal Description GP7 LED2 4 Front Panel Led green GP6 LED2 3 Front Panel Led yellow GP5 LED2 2 Front Panel Led orange GP4 LED2 1 Front Panel Led red GP3 LEDI 4 Front Panel Led green GP2 LEDI 3
20. NcPCI PMC Technical Reference Manual NcPCI PMC cPCI Carrier for 2 PMC Modules for Telecom Applications Technical Reference Manual V2 2 Hardware Revision V2 0 NcPCI PMC Technical Reference Manual The NcPCI PMC has been designed by N A T GmbH Kamillenweg 22 D 53757 Sankt Augustin Phone 49 2241 3989 0 Fax 49 2241 3989 10 E Mail support nateurope com Internet http www nateurope com Version 2 2 O N A T GmbH 2 NcPCI PMC Technical Reference Manual Disclaimer The following documentation compiled by N A T GmbH henceforth called N A T repre sents the current status of the product s development The documentation is updated on a regular basis Any changes which might ensue including those necessitated by updated speci fications are considered in the latest version of this documentation N A T is under no obli gation to notify any person organization or institution of such changes or to make these changes public in any other way We must caution you that this publication could include technical inaccuracies or typographi cal errors N A T offers no warranty either expressed or implied for the contents of this documentation or for the product described therein including but not limited to the warranties of merchant ability or the fitness of the product for any specific purpose In no event will N A T be liable for any loss of data or for errors in data utilization or processing r
21. RENCE 2 21 1 tons 50 APPENDIX B DOCUMENT S 8 11 setate 51 Version 2 2 O N A T GmbH 5 NcPCI PMC Technical Reference Manual List of Figures Figure 1 NcPCI PMC cPCI Intelligent Carrier Board for PMC Modules Figure 2 NcPCI PMC Block Diagram Figure3 Location Diagram of the NcPCI PMC Figure 4 Local TDM Bus Organisation and Synchronisation Figure 5 Connectors and Jumpers of the PMC Figure T8110 local TDM bus to private SCbus Routing Figure 7 T8110 local TDM bus to shared SCbus Routing Version 2 2 N A T GmbH NcPCI PMC Technical Reference Manual List of Tables Table 1 List of used abbreviations oe trt tede 8 INCPCT PMC beide negar DOE 11 Table 3 IDSEE Routing for internal PCI Bus NANANA Gas 18 Toca Memory NA 18 Table 5 Interrupt Status Register aqua 2 Table 6 Interrupt Status Register 222220509 eerie ttr ts KAYA NA 21 Table 7 Interrupt Mask Control Status Register 1 sese 22 Table 8 Interrupt Control Status Register eco ee RE 22 Table 514105 Regis tet T i
22. Reference Manual 5 8 8 1 H 110 Clock Frame Enable Configuration Pins CTC8B EN CTC8A EN Two bits of Control Status Register 4 are used to select the 33Q serial line termination of the C8 clock and frame If the H 110 controller is clock sync slave the serial lines have to be terminated according to the H 110 specification If the H 110 controller is clock sync master the serial lines must not be terminated The termination of the clock frame signal groups A and B that connect T8110 and H 110 bus can be set separately for group A and group B Setting the respective bit to I selects the 33 Q serial line termination T8110 is clock sync slave default setting Setting the respective bit to 0 shorts the 33 Q serial line termination T81 10 is clock sync master 5 8 8 2 PMC Module BUSMODEx Configuration Pins BUSMODE0 4 Five bits of Control Status Register 4 are used to manage the PMC BUSMODEx signals By this register the BUSMODE2 4 pins on PMC modules can be set and the status of all BUSMODE signals of both slots is readable BUSMODE 4 are bused 5 8 8 3 TDM Bus Routing Switch Configuration Pin DI6 31 Version 2 2 This bit sets the way the local TDM buses of the PMC modules are routed to the T8110 TSI controller s local bus interface The TDM switching element which is controlled by OE D16 31 was introduced due to compatibility reasons to older versions of the NcPCI PMC By default this bit is cleared
23. Y MAP LOCAL eie e eee e eret eiae ede dee tes id de Eee 18 3 3 INTERRUPT STRUCTURE AURI VC ERROR cay AUR DRE ORE ER TR IRURE CI 18 5 4 HOT SWAP CAPABILITY eter e RR te eae dts E COR RU ae OT eae ee nere 19 3 5 CLOCKING dish AN i E REG 19 5 6 RESET STRATEGY 305 sede RT ERREUR OUR ER ORO E O 19 5 6 lt NGA TANGAN 19 2 0 2 Reset of the PCT Buses e oot eru e RE RR Qe E e 19 9 7 MINIBRIDGES dr HR EC REOR BT NRI 20 5 71 Minibridge of the 121555 PCI 20 5 72 Minibridge of the T8110 H 110 TSI Controller esee eene eene ener 20 5 8 CONTROE STATUS REGISTERS pneri Hee reet aired ee e Ue tee rate etate 21 DOL Interrupt Status Register 1 E 21 3 002 Interrupt Status Register 2 osa NAG RANA 21 5 6 3 Interrupt Mask Control Status Register 1 essent 22 5 6 4 Interrupt Mask Control Status Register 2 22 5 60 Register NANG eoe De eee p uei 23 5 6 6 Status REGIMET iuo eed DO web V Dre Peu tgo NANANA NAN 23 38 7 24 3 8 8 Control Status Register 4 sies eee ege ee aio ia Pee Sie Hades 24 5 8 8 1 H 110 Clock Frame Enable Configuration Pins 25 5 8 8 2 PMC Module BUSMODEx Configuration
24. atus Register 3 Bit Read Write Reset Status Information Number Value Bit 7 R 0 notused Bit 6 R 0 notused Bit 5 R 0 notused Bit 4 R 0 geographical address bit GA4 on cPCI Connector J4 Bit 3 R 0 geographical address bit on cPCI Connector J4 Bit 2 R 0 geographical address bit GA2 on cPCI Connector J4 Bit 1 R 0 geographical address bit GAI on cPCI Connector J4 Bit 0 R 0 geographical address bit GAO on cPCI Connector J4 5 8 8 Control Status Register 4 Control Status Register 4 is accessed with address offset 0x7 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 The register initializes to 0x73 after a power on reset if no PMC module is installed Otherwise the status of bits 3 2 depend on the module installed Table 12 Control Status Register 4 Bit Read Write Reset Status Information Control Setting Number Value Bit 7 R W 0 OE 016 31 TDM Bus routing switch Bit 6 R W 1 BUSMODE 4 signal Bit 5 R W 1 BUSMODE 3 signal Bit 4 R W 1 BUSMODE 2 signal Bit 3 R 0 BUSMOPE signal of PMC slot 2 Bit 2 R 0 BUSMODE 1 signal of PMC slot 1 Bit 1 R W 1 CTC8B 110 clock frame Term Enable Bit 0 R W 1 EN 110 clock frame Term Enable Version 2 2 N A T GmbH 24 NcPCI PMC Technical
25. bridges 5 7 1 5 7 2 Minibridge of the 121555 PCI Bridge The Minibridge of the i21555 PCI bridge is used as such Thus it has to be programmed for support of the 8 bit peripheral devices connected to it The connected circuitry serves also for serial load support of EEPROM configuration data and Reset configuration defined by logic pin levels during Reset Minibridge of the T8110 H 110 TSI Controller The Minibridge of the T8110 TSI controller is not used as such It is used as microprocessor interface instead and connects to the 121555 minibridge In order to write data to the microprocessor interface of the T8110 through the 121555 minibridge it is necessary to obey to a special software handshake specified for writing to the parallel ROM interface of the 121555 Please refer to the 121555 User s Manual for further details or ask N A T for sample code Version 2 2 N A T GmbH 20 NcPCI PMC Technical Reference Manual 5 8 Control Status Registers The address range of the Control Status registers decoded by hardware is 16 bytes Larger address ranges mirror every 16 bytes 5 8 1 Interrupt Status Register 1 Interrupt Status Register 1 is accessed with address offset 0x0 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 5 Interrupt Status Register 1 Bit Read Write Reset Status Informatio
26. drives H 110 signal 1 to T8110 LREF2 input module 2 drives H 110 signal 1 B to T8110 LREF3 input Figure 6 shows the local TDM bus and SCbus routing between T8110 and the PMC modules Figure 6 78110 local TDM bus to private SCbus Routing SREF 8K SCbus DO 7 SCbus D8 15 T8110 TSI SCbus DO 7 SCbus D8 15 lt SREF_8K Version 2 2 N A T GmbH 47 NcPCI PMC Technical Reference Manual 7 2 2 2 T8110 connected to 2 PMCs with a shared SCbus The local TDM bus of the T8110 TSI has to be programmed to behave as an SCbus with clock master functionality both PMC modules are supposed to be SCbus clock slaves in order to achieve synchronisation The routing of TDM data is not restricted Please take into account that the bus is shared by the 2 PMC slots 18110 local clock output LSCO drives SCbus signal SCLK to PMC module 1 T8110 local clock output LSC1 drives SCbus signal SCLKx2 to PMC module 1 T8110 local sync output FGO drives SCbus signal FSYNC to PMC module 1 T8110 local clock output LSC2 drives SCbus signal SCLK to PMC module 2 T8110 local clock output LSC3 drives SCbus signal SCLKx2 to PMC module 2 T8110 local sync output FG1 drives SCbus signal FSYNC to PMC module 2 module 1 drives SCbus signal SREF 8K to T8110 LREFO input module 2 drives SCbus signal SREF 8K to T8110 LREFI input module 1 drives
27. esulting from the use of this product or the documentation In particular N A T will not be responsible for any direct or indirect damages including lost profits lost savings delays or interruptions in the flow of business activities including but not limited to special incidental consequential or other similar damages arising out of the use of or inability to use this product or the associated documentation even if N A T or any authorized N A T representative has been advised of the possibility of such damages The use of registered names trademarks etc in this publication does not imply even in the absence of a specific statement that such names are exempt from the relevant protective laws and regulations patent laws trade mark laws etc and therefore free for general use In no case does N A T guarantee that the information given in this documentation is free of such third party rights Neither this documentation nor any part thereof may be copied translated or reduced to any electronic medium or machine form without the prior written consent from N A T GmbH This product and the associated documentation is governed by the N A T General Conditions and Terms of Delivery and Payment Note The release of the Hardware Manual is related to a certain HW board revision given in the document title For HW revisions earlier than the one given in the document title please contact N A T for the corresponding older Hardwa
28. he directive also affects business to business relationships The directive is quite restrictive on how such waste of private persons and households has to be handled by the supplier manufacturer however it allows a greater flexibility in business to business relationships This pays tribute to the fact with industrial use electrical and electronical products are commonly intergrated into larger and more complex envionments or systems that cannot easily be split up again when it comes to their disposal at the end of their life cycles Version 2 2 O N A T GmbH 14 NcPCI PMC Technical Reference Manual As N A T products are solely sold to industrial customers by special arrangement at time of purchase the customer agreed to take the responsibility for a WEEE compliant disposal of the used N A T product Moreover all N A T products are marked according to the directive with a crossed out bin to indicate that these products within the European Community must not be disposed with regular waste If you have any questions on the policy of N A T regarding the Directive 2002 95 EC of the European Comission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS or the Directive 2002 95 EC of the European Comission on Waste Electrical and Electronic Equipment WEEE please contact N A T by phone or e mail 2 3 3 Compliance to CE Directive Compliance to the CE directive is declared A
29. ithout this attachment are bussed to both PMC slots Version 2 2 O N A T GmbH 36 NcPCI PMC Technical Reference Manual 6 5 7 PMC Slot 2 Connector P23 Table 27 PMC Slot 2 Connector P23 1 PCL 5 6 8 46 7 ____ 0 8 9 4 10 59 PCIRESV PCI RESV 60 V I O pins are connected to 3 3V Version 2 2 O N A T GmbH 24 NcPCI PMC Technical Reference Manual 6 5 8 Slot 2 Connector P24 PMC 2 I O Table 28 PMC Slot 2 Connector P24 o aa 6 1 2 7 jv 106 CT D25 9 0 5 2 9 0 83 2 b ho boi INC 3 jv me ho o 56 NC NC NC NC GND NC NC NC NC NC NC NC INC 9 0 60 NC NC Version 2 2 N A T GmbH 38 NcPCI PMC Technical Reference Manual 6 6 Compact PCI Backplane Connectors The Compact PCI backplane connectors 5 6 row connectors JI A F to F On the NcPCI PMC J3 and J5 are not populated The 7 row Z does not connect to pins but is just for shielding and completely connected to GND 6 6 1 Compact PCI Backplane Connector J1 Table 29 Compact PCI Backplane Connector J1 Rows A C Pin No RowA Row B Row PCI Signal PCI Signal PCI Signal Ve 2 Stn 3 4 J HEALTHY Sone
30. n JRST 6 REQ 33VL 7 AD30 ADO ADB 26 C BE3 IDSEL D23 AD GND 133 18 Dis Key Area 337 FRAME J RDY 16 DEVSE GND 17 33V Je no 18 33V po 1580 PADIS TAD IAS _ 20 ADI2 GND 21 33V 0 AD8 22 AD7 BBV 23 33V 24 ADI ___ 25 5V E ES 12 13 d4 15 Version 2 2 O N A T GmbH 39 NcPCI PMC Technical Reference Manual Table 30 Compact PCI Backplane Connector J1 Rows D Pin No RowD Row E Row F PCI Signal PCI Signal re Siena ____ GN s 4 BING GND 5 ____ 6 ADI 7 ____ GND 8 ADS 4 ____ o ____ 650 m Key Area s moss Ty Nb 16 STO GND 17 ___ ___ GND 18 PAR J C BI ____ _ bribe ba apo en 25 ____ GND Version 2 2 N A T GmbH 40 NcPCI PMC Technical Reference Manual 6 6 2 Compact PCI Backplane Connector J2 Table 31 Compact PCI Backplane Connector J2 Rows A C Va ne 6 ____ 8 56 5 404
31. n Number Value Bit 7 R 0 slot 2 INTD signal Bit 6 R 0 PMC slot 2 INTC signal Bit 5 R 0 slot 2 INTB signal Bit 4 R 0 slot 2 INTA signal Bit 3 R 0 slot 1 INTD signal Bit 2 R 0 PMC slot 1 INTC signal Bit 1 R 0 PMC slot 1 INTB signal R 0 PMC slot 1 INTA signal 5 8 2 Interrupt Status Register 2 Interrupt Status Register 2 is accessed with address offset 0 1 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 6 Interrupt Status Register 2 Bit Read Write Reset Status Information Number Value Bit 7 R 0 not used Bit 6 R 0 not used Bit 5 R 0 not used Bit 4 R 0 not used Bit 3 R 0 not used Bit 2 R 0 Compact PCI bus INTA signal Bit 1 R 0 CLKERRTSI T8110 Bit 0 R 0 SYSERRTSI T8110 Version 2 2 O N A T GmbH 21 NcPCI PMC Technical Reference Manual 5 8 3 Interrupt Mask Control Status Register 1 Every interrupt source on the NePCI PMC is maskable by software The status of these mask registers is readable anytime The registers initialize to 0 0 after a reset of the PCI bus Set a bit to enable an interrupt clear a bit to mask disable an interrupt Interrupt Mask Control Status Register 1 is accessed with address offset 0x2 to the base address programmed in the i21555 Mini Bridge Base Address Register plus the address value given in Table 4
32. nstalling the NePCI PMC read this installation section e Before installing or uninstalling the NePCI PMC in a rack Check all installed boards and modules for steps that you have to take before turning on or off the power Take those steps Finally turn on or off the power e Before touching integrated circuits ensure to take all require precautions for handling electrostatic devices e Ensure that the NePCI PMC is connected to the backplane via all cPCI connectors and that the power is available on all cPCI connectors GND 5V 3 3V 12V 12V e When operating the board in areas of strong electromagnetic radiation ensure that the module is firmly screwed to the rack and shielded by closed housing Version 2 2 O N A T GmbH 12 NcPCI PMC Technical Reference Manual 2 2 Installation Prerequisites and Requirements IMPORTANT 2 2 1 2 2 2 2 2 3 Before powering up e check this section for installation prerequisites and requirements Requirements The installation requires only e acarrier board for connecting the NCPCI PMC e power supply Power supply The power supply for the NcPCI PMC must meet the following specifications e required for the board 3 3 0 5A typical 5 typical e required for optionally mounted PMC modules 5 6 0A max 12V 1 0A max 12V 1 0A max Refer to User s Manuals of the PMC modules for information on their power consumption The
33. nt PCI to PCI Bridge User Manual July 2001 2 Agere Systems Ambassador T8110 PCI based H 100 H 110 Switch and Packet Payload Engine April 2001 Version 2 2 O N A T GmbH 50 NcPCI PMC Technical Reference Manual Appendix B Document s History mu eee 06 01 2003 initial version o ga ga ga ga ga table 24 TDM signals corrected 15 12 2003 H 110 FRAME bug description added ga ga ga ga ga ga ga 1 5 2 2 06 06 2007 chapter2 3 3 and 2 3 4 added Version 2 2 N A T GmbH 51
34. rd insertion The hot swap capability of the NePCI PMC according to PICMG 2 1 R2 0 complies to Full Hot Swap For High Availability applications contact N A T for support Clocking The NcPCI PMC is capable of supporting 33 MHz and 66 MHz PCI busses also in a mixed environment Which bus frequency is actually selected for either side of the bridge depends on the status of the respective M66EN signal lines If all PCI devices on the bus support 66 MHz M66EN will be high Any device not supporting 66 MHz drives M66EN low thus forcing the bus to operate at 33 MHz bus speed Reset Strategy Reset Sources There are 3 Reset sources that influence the PMC Power On Reset failure of one or more of the power supplies PCIRST signal of the cPCI bus Reset of the PCI Bus The 121555 PCI Bridge which interfaces between the internal PCI bus of the NcPCI PMC and the Compact PCI bus has 3 Reset pins which carry special functionalities P RST and S RST IN are inputs S RST is an output P RST and S RST IN put the device into a well defined Reset Mode and are functionally identical wire ored within the chip S RST IN is not used on the NePCI PMC P RST connected to PCIRST of internal PCI bus is generated by a CPLD if one of the reset sources described in the above chapter becomes active and if an external cPCI PCIRST is received Version 2 2 N A T GmbH 19 NcPCI PMC Technical Reference Manual 5 7 Mini
35. re Manual release Version 2 2 N A T GmbH 3 NcPCI PMC Technical Reference Manual Table of Contents TABLE OF CONTENTS 4 LIST OFFIGURES 6 LIST OF TABLES 7 CONVENTIONS Rt 8 1 INTRODUCTION 9 1 1 BOARD FEATURES eet eee ien ete teet tem i ete Pe thee 10 1 2 BOARD SPECIFICATION heces eap teneam ete baee ire tee n ene 11 2 INS TATA TION fpe 12 2 1 SAFETY NOTE eodeni ate ae RONG Sa eR A Ee aed RAT 12 22 INSTALLATION PREREQUISITES AND REQUIREMENTS 2 eee e een 13 2 2 Requirements osa mn ad eee Ren eed Ree 13 2 2 2 Supply sac to eer eive tet er e ee Yee Qro ue eed que 13 2 2 3 Automatic Power Up i eee ea rene eee ue 13 2 3 STATEMENT ON ENVIRONMENTAL 14 2 3 1 Complidnce to RoHS Directive seii ed a cet e tete eee tape E NABANG 14 2 3 2 Compliance to WEEE Directive epe cree 14 23 3 Compliance to CE Directive eaa eee ri a eroe ee ret he e 15 2 3 4 Product Safety odere 15 3 EOCUA UT LLL 16 4 TDM BUS AND H 110 BUS CONTROLLER eee sees eene eene sesso 17 5 cU 18 5 1 MEMORY MAP eere ede RE Ree E Ue 18 5 2 MEMOR
36. respective 0 01 by weight in homogenous materials only As these harzadous substances are currently used with semiconductors plastics i e semiconductor packages connectors and soldering tin any hardware product is affected by the RoHS directive if it does not belong to one of the groups of products exempted from the RoHS directive Although many of hardware products of N A T are exempted from the RoHS directive it is a declared policy of N A T to provide all products fully compliant to the RoHS directive as soon as possible For this purpose since January 31st 2005 N A T is requesting RoHS compliant deliveries from its suppliers Special attention and care has been payed to the production cycle so that whereever and whenever possible RoHS components are used with N A T hardware products already Compliance to WEEE Directive Directive 2002 95 EC of the European Comission on Waste Electrical and Electronic Equipment WEEE predicts that every manufacturer of electrical and electronical equipment which is put on the European market has to contribute to the reuse recycling and other forms of recovery of such waste so as to reduce disposal Moreover this directive refers to the Directive 2002 95 EC of the European Comission on the Restriction of the use of certain Hazardous Substances in Electrical and Electronic Equipment RoHS Having its main focus on private persons and households using such electrical and electronic equipment t
37. s offset Ox8 to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 14 Control Status Register 4 Bit Read Write Reset Status Information Control Setting Number Value Bit 7 R 0 notused Bit 6 R 0 notused Bit 5 R W Slot ID 4 signal of both PMC slots Bit 4 R W GA2 Slot ID 3 signal of both PMC slots Bit 3 R W Slot ID 2 signal of both PMC slots Bit 2 R W GAO Slot ID 1 signal of both PMC slots Bit 1 R W 0 Slot ID 0 signal of PMC slot 2 Bit 0 R W 1 Slot ID 0 signal of PMC slot 1 This register allows the user to program a unique ID for each PMC module in the system The ID definition complies to the Slot ID definition of the SCSA bus spec By default the upper 4 bits of the PMC ID is copied from the lower 4 bits of the cPCI Slot ID GAO GA3 refer to chapter 5 8 5 Status Register 1 Version 2 2 O N A T GmbH 26 NcPCI PMC Technical Reference Manual 5 8 10 Lattice Revision Status Register The Lattice Hardware Revision Status Register is accessed with address offset OxE to the base address programmed in the 121555 Mini Bridge Base Address Register plus the address value given in Table 4 Table 15 Board Hardware Revision Status Register Bit Read Write Status Information Number Bit 7 R Lattice CPLD revision Bit 6 R Lattice CPLD revision Bit 5 R
38. se interfaces have 32 bit TDM data path and comply to H 110 as well as SCSA timing constraints H 110 The NcPCI PMC implements a 32 bit H 110 interface according to PICMG 2 5 R1 0 This is implemented by an Agere T8110 TSI device This device also sets the interface characteristics for the 2 internal TDM interfaces Version 2 2 N A T GmbH 10 NcPCI PMC Technical Reference Manual 1 2 Board Specification Table 2 NcPCI PMC Features Board Format standard 6U Compact PCI board PCI to cPCI bridge 121555 cPCI functions 64 Bit 66 MHz PCI hot swap with H 110 extension PMC 2 PMC slots 64 Bit 66 MHz Firmware OKI VxWorks BSP on request 3 3V 0 5A typ P ti BE re typ PMC module supply note the 3 3V supply of the PMC s is derived from the 5V of the carrier Temperature operating 0 C to 60 C with forced cooling Temperature storage 40 C to 85 C Humidity 10 Yo to 90 Yo rh noncondensing Environmental conditions Standards compliance PCI Rev 2 2 PICMG 2 5 R1 0 IEEE P1386 1 Draft 2 4a Version 2 2 O N A T GmbH 11 NcPCI PMC Technical Reference Manual 2 Installation 2 1 Safety Note To ensure proper functioning of NePCI PMC during its usual lifetime take the following precautions before handling the board CAUTION Electrostatic discharge and incorrect board installation and uninstallation can damage circuits or shorten their lifetime e Before installing or uni
39. to support H 110 standards Transmit and Receive data paths are not restricted in use and may be specified according to the user s needs 7 2 2 1 T8110 connected to 2 PMCs with private SCbuses The local TDM bus of the T8110 TSI has to be programmed to behave as an SCbus with clock master functionality both PMC modules are supposed to be SCbus clock slaves in order to achieve synchronisation This is achieved by the following routing of T8110 local TDM signals to the SCbuses of the 2 PMC slots Version 2 2 N A T GmbH 46 NcPCI PMC Technical Reference Manual T8110 TDM_D0 7 writes timeslot data to SCbus D0 7 of PMC module 1 T8110 TDM D16 23 writes timeslot data to SCbus D0 7 of PMC module 2 module 1 SCbus 08 15 writes timeslot data to T8110 8 15 module 2 SCbus 08 15 writes timeslot data to T8110 D24 31 T8110 local clock output LSCO drives SCbus signal SCLK to PMC module 1 T8110 local clock output LSC1 drives SCbus signal SCLKx2 to PMC module 1 T8110 local sync output FGO drives SCbus signal FSYNC to PMC module 1 T8110 local clock output LSC2 drives SCbus signal SCLK to PMC module 2 T8110 local clock output LSC3 drives SCbus signal SCLKx2 to PMC module 2 T8110 local sync output drives SCbus signal FSYNC to PMC module 2 module 1 drives SCbus signal SREF 8K to T8110 LREFO input module 2 drives SCbus signal SREF 8K to T8110 LREFI input module 1
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