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STM8S903K3
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1. Table 12 General hardware register map continued Address Block Register label Register name Reset status 00 530COx TIM5_CNTRH TIM5 counter high 0x00 0x00 530D TIM5_CNTRL TIM5 counter low 0x00 0x00 530E TIM5_PSCR TIM5 prescaler register 0x00 0x00 530F TIM5_ARRH TIM5 auto reload register high OxFF 0x00 5310 TIM5_ARRL TIM5 auto reload register low OxFF 0x00 5311 Eus TIM5 CCR1H TIM5 capture compare register 1 high 0x00 0x00 5312 TIM5 CCR1L TIM5 capture compare register 1 low 0x00 0x00 5313 TIM5 CCR2H TIM5 capture compare register 2 high 0x00 0x00 5314 TIM5 CCR2L TIM5 capture compare register 2 low 0x00 0x00 5315 TIM5_CCR3H_ TIM5 capture compare register 3 high 0x00 0x00 5316 TIM5 CCR3L TIM5 capture compare register 3 low 0x00 0x00 5317 to Reserved area 43 bytes 0x00 533F 0x00 5340 TIM6_CR1 TIM6 control register 1 0x00 0x00 5341 TIM6_CR2 TIM6 control register 2 0x00 0x00 5342 TIM6_SMCR TIM6 slave mode control register 0x00 0x00 5343 TIM6 IER TIM6 interrupt enable register 0x00 0x00 5344 TIM6 TIM6_SR TIM6 status register 0x00 0x00 5345 TIM6_EGR TIM6 event generation register 0x00 0x00 5346 TIM6_CNTR TIM6 counter 0x00 0x00 5347 TIM6_PSCR TIM6 prescaler register 0x00 0x00 5348 TIM6_ARR TIM6 auto reload register OxFF 0x00 5349 to Reserved area 153 bytes 0x00 53DF 0x00 53E0 to ADC1 ADC DBxR ADC da
2. Table 13 CPU SWIM debug module interrupt controller registers Address Block Register label Register name dee 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 0x00 7FOB to 0x00 Reserved area 85 bytes 7F5F 0x00 7F60 CPU CFG_GCR Global configuration register 0x00 0x00 7F70 ITC_SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 i ITC SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt software priority register 8 OxFF 0x00 7F78 to Reserved area 2 bytes 0x00 7F79 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 bytes 0x00 7F8F G Doc ID 15590 Rev
3. Table 25 Total current consumption in halt mode at Vpp 5 V Symbol Parameter Conditions Typ Mis Pus n Unit Flash in operating mode HSI clock after wakeup 63 75 105 Supply current in A DD H halt mode Flash in power down mode HSI clock after 6 0 15 35 H wakeup K 1 Data based on characterization results not tested in production Table 26 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Ed Pus Ac Unit i Supply current in Flash in operating mode HSI clock after wakeup 60 75 100 F DD H halt mode Flash in power down mode HSI clock after wakeup 4 5 12 30 1 Data based on characterization results not tested in production Low power mode wakeup times Table 27 Wakeup times Symbol Parameter Conditions Typ Max Unit See t Wakeup time from wait note WU WF mode to run mode fopu fuAsrER 16 MHz 0 56 Flash in operating 4 6 mode MVR voltage 4 regulator on Flash in power 3 6 5 i Wakeup time active halt down mode HSI us WU AH mode to run model Flash in operating after wakeup 430 5 MVR voltage mode 4 regulator off Flash in power 50 down mode 9 Wakeup time from halt Flash in operating mode 9 52 WU H 3 VI mode to run mode Flash in power down mode 54 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 6 X 1 fcpu 3 Measu
4. Table 11 I O port hardware register map Address Block Register label Register name Weer 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0x00 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0x00 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0x00 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0x00 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register 0x00 0x00 5016 Port E PE_DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018
5. Table 41 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 8 i SCK SPI clock frequency S MHz Losch Slave mode 0 TBD ec SPI clock rise and fall time Capacitive load C 30 pF 25 hsc tsuNss NSS setup time Slave mode 4 X tMASTER thuss NSS hold time Slave mode 70 3 W SCKH SCK high and low time Master mode tsck 2 15 tgc 2 15 tw SCKL t 3 Master mode 5 sum 3 Data input setup time tsu S1 Slave mode 5 t 3 Master mode 7 ns n Ml Data input hold time this Slave mode 10 taso V Data output access time Slave mode 3 X MASTER tasso 9 Data output disable time Slave mode 25 Leo Data output valid time Slave mode after enable edge TBD tymoy Data output valid time Master mode after enable edge 30 tho Slave mode after enable edge 270 Data output hold time thamioy Master mode after enable edge 110 1 Parameters are given by selecting 10 MHz UO output frequency 2 Data characterization in progress 3 Values based on design simulation and or characterization results and not tested in production 4 Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 5 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 68 88 Doc ID 15590 Rev 1 D
6. Table 37 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 100 VoL Output low level with 8 pins sunk o 10 mA Vpp 5V 2 Output high level with 4 pins sourced lig 4 mA Vpp 3 3 V 2 10 M To Output high level with 8 pins sourced lip 10 mA Vpp 2 5 V 2 8 1 Data based on characterization results not tested in production Table 38 Output driving current true open drain ports Symbol Parameter Conditions Min Max Unit lio 10 MA Vpp 3 3 V 1 57 Vo Output low level with 2 pins sunk lio 10 mA Vpp 5 V 1 V lio 20 mA Vpp 5V 2 1 Data based on characterization results not tested in production Table 39 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 4 pins sunk lio 10 mA Vpp 3 3 V 100 VoL Output low level with 8 pins sunk lio 10 mA Vpp 5 V 0 8 Output low level with 4 pins sunk lio 20 mA Vpp DM 1 50 7 Output high level with 4 pins sourced lio 10 mA Vpp 3 3 V 2 1 Vou Output high level with 8 pins sourced lio 10 mA Vpp 5 V 4 0 Output high level with 4 pins sourced lio 20 mA Vpp 5 V 3 30 1 Data based on characterization results not tested in production Figure 23 Typ Vo Vpp 3 3 V standard ports 15 40 C 25 C 125 85 C 125 C 62 88 Doc ID 15590 Rev 1 Lyr www bdtic com ST S
7. Voo VoH V lo mA Figure 32 Typ Vpp Von 9 Vpp 5 V high sink ports 40 C 25 C 85 C 1 5 125 C Voo 6x V 25 Doc ID 15590 Rev 1 65 88 www bdtic com ST Electrical characteristics STM8S903K3 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 40 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit Vit nrst NRST Input low level voltage 1 0 3 V 0 3 x Vpp y 1 0 7 x Von Vin wrst NRST Input high level voltage 7 ger 0 3 V Vor NRsT NRST Output low level voltage 1 logi 2 mA 0 5 Reuwrst NRST Pull up resistor 30 40 60 kQ Hepupen NRST Input filtered pulse 9 75 ns tinrp nrst NRST Input not filtered pulse 3 500 ns toP NRST NRST output pulse 3 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 33 Typical NRST Vj and Vj vs Vpp 4 temperatures 40 C 6 25 C 5 85 C 125 C 4 z 33 E a 2 1 o i i 25 3 3 5 45 5 55 6 Voo V Figure 34 Typica
8. Symbol Ratings Max Unit Jupp Total current into Vpp power lines source 100 lyss Total current out of Vss ground lines sink 80 is Output current sunk by any I O and control pin 20 Output current source by any I Os and control pin 20 ni Injected current on NRST pin 4 Inem 24 Injected current on OSCIN pin 4 Injected current on any other pin 4 Zus Total injected current sum of all I O and control pins 20 1 Data based on characterization results not tested in production All power Vpp and ground Vss pins must always be connected to the external supply 3 Iw must never be exceeded This is implicitly insured if Viy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the lj j piyy value A positive injection is induced by Viz Vpp while a negative injection is induced by Viy Vss For true open drain pads there is no positive injection current and the corresponding Vu maximum must always be respected 4 Negative injection disturbs the analog performance of the device See note in Section 9 3 10 10 bit ADC characteristics on page 72 5 When several inputs are submitted to a current injection the maximum Aly pi is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with Hm up maximum current injection on four I O port pins of the device Table 16 Thermal c
9. Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 14 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage D 0 3 6 5 Input voltage on true open drain pins Vss 0 3 6 5 V Vin Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vppl Variations between different power pins 50 IVssx Vss Variations between all the different ground pins 50 see Absolute maximum Vesp Electrostatic discharge voltage ratings electrical sensitivity on page 76 1 All power Vpp and ground Vss pins must always be connected to the external power supply liNJ piN must never be exceeded This is implicitly insured if Vjy maximum is respected If Viy maximum cannot be respected the injection current must be limited externally to the lup value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vas For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected Doc ID 15590 Rev 1 D www bdtic com ST STM8S903K3 Electrical characteristics Table 15 Current characteristics
10. 7 N o m Pol A e oH PD7 PC7 HS SPI_MISO TIM1_CH2 PC6 HS SPI MOSI TIM1_CH1 PCS HS SPI_SCK TIM5_CH1 PC4 HS TIM1_CH4 CLK_CCO AIN2 TIM1_CH2N PC3 HS TIM1 CH3 TLI TIM1_CH1N PC2 HS TIM1_CH2 TIM1_CH3N PC1 HS TIM1_CH1 UART1_CK TIM1_CH2N PE5 SPI_NSS TIM1 CH1N NN N Go N A allg N O OO o ar ab k N Ha Hu Ha HR Ha or ri Ho PB7 Clo PB6 HS PB3 HS PB2 HS PB1 HS PBO TIM1_CH3N AIN2 TIM1_CH2N AIN1 TIM1 CH1N AINO TIM1_ETR AIN3 TIM1_BKIN 12C_SDA T PB5 O ADC_ETR l2C_SCL T PB4 HS high sink capability 2 T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 20 88 Doc ID 15590 Rev 1 D www bdtic com ST STM8S903K3 Pinout and pin description Table 4 Legend abbreviations Type l Input O Output S Power supply Level Input CM CMOS Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset O4 Fast slow programmability with fast as default state after reset configuration Port and control Input float floating wou weak pull u
11. 28 28 7 3 7 21 8K 6400 1K independent WDG ADC PWM timer TIM5 8 bit timer TIM6 1 Including 21 high sink outputs 2 Noread while write RWW capability ky Doc ID 15590 Rev 1 9 88 www bdtic com ST Block diagram STM8S903K3 3 Block diagram Figure 1 Block diagram Reset block XTAL 1 16 MHz Kc Clock controller Reset Reset RC int 16 MHz Detector POR BOR 4 RC int 128 kHz Clock to peripherals and core lt gt Window WDG STMB core lt gt lt gt Independent WDG Single wire debug interf GE Debug SWIM 5 gt 8 Kbytes L 5 gt program Flash 640 bytes 5 gt data EEPROM lt gt 1 Kbytes RAM 400 Kbit s 4 Pc lt gt 8 Mbits lt T gt LIN master SPI emul LD UARTI Se X Up to 4 CAPCOM lt gt 16 bit advanced control channels timer TIM1 an 3 complementary outputs 16 bit general purpose K gt Up to Timer TIM5 3 CAPCOM channels Address and data bus lt gt 8 bit basic timer Up to 7 gt ADC1 lt gt TIM6 channels Gen keiz Beeper 5 gt lt gt AWU timer D 10 88 Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Product overview 4 4 1 Product overview The following section in
12. ky STM8S903K3 16 MHz STM8S 8 bit MCU up to 8 Kbytes Flash 1 Kbyte RAM 640 bytes EEPROM 10 bit ADC 2 timers UART SPI IC Features Core m 16 MHz advanced STMB8 core with Harvard architecture and 3 stage pipeline m Extended instruction set Memories m Program memory 8 Kbytes Flash data retention 20 years at 55 C after 10 kcycles m Data memory 640 bytes true data EEPROM endurance 300 kcycles m RAM 1 Kbytes Clock reset and supply management m 2 95 to 5 5 V operating voltage m Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC m Clock security system with clock monitor m Power management Low power modes wait active halt halt Switch off peripheral clocks individually m Permanently active low consumption power on and power down reset Interrupt management m Nested interrupt controller with 32 interrupts m Up to 28 external interrupts on 7 vectors Timers m Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization April 2009 Preliminary data LQFP32 7x7 VFQFPN32 5x5 m 16 bit general purpose timer with 3 CAPCOM channels IC OC or PWM m 8 bit basic timer with 8 bit prescaler m Auto wake up timer m 2 watchdog timers Window watchdog and indepe
13. www bdtic com ST STM8S903K3 Electrical characteristics Table 20 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 8 fcpu MASTER 16 MHz HSE user ext clock 16 MHz 2 2 3 HSI RC osc 16 MHz 1 5 2 Supply m fopy fmastep 128 125 HSE user ext clock 16 MHz 0 81 kHz maouted HSI RC osc 16 MHz 0 7 0 87 from RAM fcpu fmaster 128 15 625 kHz HSI RC osc 16 MHz 8 0 46 0 58 fcpu MASTER 128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN HSE crystal osc 16 MHz 4 mA fcpu MASTER 16 MHz HSE user ext clock 16 MHz 3 9 4 7 HSI RC osc 16 MHz 3 7 4 5 Supply fopu MASTER HSI RC osc 16 MHz 8 2 0 84 1 05 current in run 2 MHz mode code H 7 executed foru fmaster 128 125 ist RC osc 16 MHZ 072 09 kHz from Flash fopu fuasrEn 128 HSI RC osc 16 MHz 8 0 46 0 58 15 625 kHz 5 j fcpu MASTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off ky Doc ID 15590 Rev 1 47 88 www bdtic com ST Electrical characteristics STM8S903K3 Total current consumption in wait mode Table 21 Total current consumptio
14. 18 85 C 125 C 16 t 45 C 14 T bg 12 W a L EE T L z 0 8 a Q 0 6 0 4 0 2 0 T 2 25 3 35 4 45 5 55 6 Voo V Figure 13 Typ Ipp wri VS fcpu HSE user external clock Vpp 5 V 25 C 18 85 C 125 C 1 6 45 C 14 T 12 1 I E 0 8 1 8 0 6 04 0 2 0 2 4 6 8 10 12 14 16 18 Feru MHz ky Doc ID 15590 Rev 1 53 88 www bdtic com ST Electrical characteristics STM8S903K3 54 88 Figure 14 Typ Ipp wF vs Vpp HSI RC osc fcpu 16 MHz HSI mA IDD WEI H 25 C 85 C 125 C 45 C 3 3 5 4 45 Fepu MHz Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Electrical characteristics 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and T4 Table 30 HSE user external clock characteristics Symbol Parameter Conditions Min Max Unit fius aat See clock source 0 16 MHz Vasen oes input pin high level 0 7 xVpp Vpp 0 3 V Vasel mech input pin low level Vss 0 3 x Vpp ILEAK_HSE OSCIN input leakage current Vss lt Vin lt Vpp 1 1 UA 1 Data based on characterization results not tested in production Figure 15 HSE external clock source VHsEH L Vusg L External clock Source Lol L
15. Do te OSCIN gt STM8 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Doc ID 15590 Rev 1 55 88 www bdtic com ST Electrical characteristics STM8S903K3 Table 31 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Ges External high speed oscillator 1 16 MHz frequency Rr Feedback resistor 220 kQ CU Recommended load capacitance 2 20 pF C 20 pF ci fosc 16 MHz stabilized Ipp Hsg HSE oscillator power consumption mA C 10 pF 6 potus fosc 16 MHz stabilized 9 Om Oscillator transconductance 5 mA V tutus Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details Data base
16. 1 39 88 www bdtic com ST Memory and register map STM8S903K3 Table 13 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name bean Ox007F90 DM BKIRE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BKA2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF 0x00 7F9B to Reserved area 5 bytes 0x00 7F9F 1 Accessible by debug module only 40 88 Doc ID 15590 Rev 1 eo www bdtic com ST STM8S903K3 Electrical characteristics 9 9 1 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production
17. 7 0 FFh 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 00h function ox4go4 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR LSI IWDG WWDG WWDG 0x4805h OPT3 Reserved HSITRIM 00h Miscellaneous EN HW HW HALT option d NLSI 0x4806 NOPT3 Reserved RESI S De NWWDG NWWG FFh TRIM _EN W HW _HALT EXT CKAWU PRS PRS 0x4807 OPT4 Reserved 00h CLK SEL C1 CO Clock option NEXT NCKAWUS NPR NPR 0x4808 NOPT4 Reserved FFh CLK EL SCH SCH 0x4809 HSE clock OPTS HSECNT 7 0 00h Ox480A Startup NOPT5 NHSECNT 7 0 FFh 26 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Option bytes d Table 8 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page 0 defined as UBC memory write protected 0x02 Pages 0 to 1 defined as UBC memory write protected Page 0 and 1 contain the interrupt vectors Ox7F Pages 0 to 126 defined as UBC memory write protected Other values Pages 0 to 127 defined as UBC memory write protected Note Refer to the family reference manual RM0016 section on Flash write protection for more details OPT2 AFR 7 0 Refer to Table 9 an
18. EEEE EEEE EEE EEEIEE EEEE r 44 External capacitor CEXT a 45 Typ Ipp Ruw VS Von HSE user external clock fcpj 16 MHZ ee eee eee 52 Typ Ipp Ruw VS fepu HSE user external clock Vpp DN 52 Typ IDD RUN VS Vbpp HSI RC OSC fcpu 16 MHZ ise e a a Re Directe dar 53 Typ Ipp wri VS Vpp HSE user external clock fopy 16 MHz eee eee eee 53 Typ Ipp wri VS fcpy HSE user external clock Vpp 5 V 222222 lala akka kaa 53 Typ IDD WFI VS V nn HSI RC OSC fcpu 216MHZ seen 54 HSE external clock source 55 HSE oscillator circuit diagram lille ren 56 Typical HSI accuracy at Vpp 5 V vs 5 temperatures 1 1 2 2 22 ana 57 Typical HSI frequency variation vs Vpp 4 temperatures a saaa ananena 58 Typical LSI frequency variation vs Vpp 4 temperatures 58 Typical Vu and Vj vs Vpp 4 temperatures eee 61 Typical pull up resistance vs Vpp 4 temperatures n n cece eee eee 61 Typical pull up current vs Vpp 4 temperatures 61 Typ Vor Vpp 3 3 V standard porte 62 Typ Vor 9 Vpp 5 V standard ports e 63 Typ VoL Vpp 3 3 V true open drain porte 63 Typ VoL 9 Vpp 5 V true open drain porte 63 Typ Vor 9 Vpp 3 3 V high sink porte 64 Typ Vor 9 Vpp 5 V high sink porte 64 Typ Vpp Vou 9 Vpp 3 3 V standard porte 64 Typ Vpp Vou 9 Vpop 5 V standard porte 65 Typ Vpp Vou 9 Vpop 3 3 V high sink
19. Ee DC interrupt Yes Yes 0x00 8054 20 Reserved 0x00 8058 21 Reserved 0x00 805C JEN MEE 0x00 8060 23 TIM6 TIM6 update overflow trigger 0x00 8064 24 Flash EOP WR_PG_DIS 0x00 8068 EENS 0x00 806C to 0x00 807C 1 Except PA1 ky Doc ID 15590 Rev 1 25 88 www bdtic com ST Option bytes STM8S903K3 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 7 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 7 Option bytes Option tion bit Factor Option p Option bits actory Addr hane byte default no 7 6 5 4 3 2 1 0 setting Read out 0x4800 protection OPTO ROP 7 0 00h ROP 0x4801 User boot OPT1 UBC 7 0 00h ox4802 code UBC NopTi NUBC
20. PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 Doc ID 15590 Rev 1 31 88 www bdtic com ST Memory and register map STM8S903K3 Table 12 General hardware register map Address Block Register label Register name nesel status 0x00 501E to Reserved area 60 bytes 0x00 5059 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Blac COMPANY conte OxFF register 2 0x00 505D Flash FLASH _FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection OxFF register 0x00 505F FLASH IAPSR Flash in application programming Ox00 status register 0x00 5060 to Reserved area 2 bytes 0x00 5061 0x00 5062 Flash FLASH_pukr_ Flash program memory unprotection yygg register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to Reserved area 59 bytes 0x00 509F 0x00 50A0 i EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to Reserved ar
21. Ta 25 C 30 MHz to 130 MHz 10 10 dBuV Sc LQFP32 package 130 MHz to 1 GHz 5 7 Conforming to SAE J 1752 3 SAE EMI level SAE EMI level 2 5 2 5 1 Data based on characterization results not tested in production 76 88 Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU and DLU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin One model can be simulated Human body model This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 48 ESD absolute maximum ratings Symbol Ratings Conditions Class mn Unit value V Electrostatic discharge voltage TA 25 C conforming to A 4000 ESD HBM Human body model JESD22 A114 H V Electrostatic discharge voltage TAE QFP32 package VESD CDM Charge device model 25 C conforming to IV 1000 SD22 C101 1 Data based on characterization results not tested in production Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Electrical characteri
22. available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you 84 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 STM8 development tools 12 12 1 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STM8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module SWIM
23. based on a differential lnn measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production conversions Not tested in production Doc ID 15590 Rev 1 Data based on a differential Ipp measurement between reset configuration and continuous A D 51 88 www bdtic com ST Electrical characteristics STM8S903K3 52 88 Current consumption curves Figure 9to Figure 14 show typical current consumption measured with code executing in RAM Figure 9 Typ Ipp RuN VS Vpp HSE user external clock fcpy 16 MHz 2 05 IDD run HSE mA 25 C 85 C 125 C 45 C Voo V 45 55 Figure 10 Typ Ipp nuw VS fcpu HSE user external clock Vpp 5 V mA IDD run HSE 25C 85 C 125 C 4 45 C Fcru MHz Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Electrical characteristics Figure 11 Typ Ipp RUN vs Vpp HSI RC OSC fepy 16 MHz 25 C 2 85 C 125 C 45 C to a eo rl a wo eo IDD run HSI mA gt 8 ia t t i tn a u N 25 3 35 4 45 5 55 6 Von V Figure 12 Typ Ipp wri VS Vpp HSE user external clock fcpy 16 MHz 25 C
24. cC v 3r no il SI S lala 5 function remap ZI ZS 5 c O sz option 9 2 bit ui Analog input 2 PCA TIM1 CHA Timer 1 channel 4 AFR2 21 CLK CCO AIN2 UO X X X HS O3 X X Port C4 configurable clock Timer 1 TIM1_CH2N output inverted channel 2 AFR7 Timer 5 22 SE 1 O X X X HS O3 X X Port C5 SPI clock channel 1 m AFRO PC6 SPI_MOSI SPI master out er 23 TIM1 CH1 1 O X X X HS O3 X X Port C6 slave in channel 1 E AFRO PC7 SPI_MISO SPI masterin Timer 1 24 TIM1 CH2 UO X X X HS O3 X X Port C7 slave dut channel 2 AFRO Con figurable gg DO TINH BRIN vo x x x HsS o3s x x pan pp Timert break doce CLK CCO input output AFR5 26 PD1 SWIM vo x x x HS O4 X X part D1 SWIM data interface Analog input 3 AFR2 27 PD2 AIN3 TIM5_CH3 1 O X X X HS OS3 X X Port D2 Timer 5 channel 3 AFR1 Analog input 4 PD3 AIN4 TIM5_CH2 Timer 5 channel 28 ADC KTR 1 O X X X HS O3 X X Port D3 2 ADC external trigger UART PD4 TIM5_CH1 BEEP Timer 5 channel 29 a 1 O X X X HS O3 X X Port D4 clock UART1_CK 1 BEEP output AFR2 Analog input 5 30 PD5 AIN5 UART1_TX 1 O X X X HS O3 X X Port D5 UARTI data transmit ky Doc ID 15590 Rev 1 23 88 www bdtic com ST Pinout and pin description STM8S903K3 Table 5 VFQFPN32 LQFP32 pin description continued
25. calculate the temperature range needed for a given application Assuming the following application conditions e Maximum ambient temperature Tanav 75 C measured according to JESD51 2 e IpDmax 8 mA Vpp 25V e Maximum 20 l Os used at the same time in output at low level with lot 8 mA VoL 0 4V PiNTmax 8 mA x 5 V 400 mW Piomax 20 X 8 MA x 0 4 V 64 mW This gives Pintmax 400 mW and Piomax 64 mW PDmax 2 400 mW 64 mW Thus Ppmax 464 mW Using the values obtained in Table 52 Thermal characteristics on page 82 T ymax is calculated as follows for LQFP32 59 C W TJmax 75 C 59 C W x 464 mW 75 C 27 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 Doc ID 15590 Rev 1 83 88 www bdtic com ST Ordering information STM8S903K3 11 Ordering information Figure 46 STM8S903K3 ordering information scheme Example STM8 S 903 K 3 T 6 C TR E Product class STM8 microcontroller Family type S Standard Sub family type 903 903 sub family Pin count K 32 pins Program memory size 3 8 Kbytes Package type T LQFP U VFQFPN Temperature range 3 40 C to 125 C 6 40 C to 85 C Package pitch No character 0 5 mm C 2 0 8 mm Packing No character Tray or tube TR Tape and reel 1 Fora list of
26. com ST Electrical characteristics STM8S903K3 Figure 40 ADC accuracy characteristics A i EP 1028 ect OS eben oet As pateat qut m 1022 VbDA ssa pa 1LSB 7 7 1021 _ IDEAL 1024 2 p P up 1 Ld X oF K Er B K 7 1 CE e 3 1 6 i T 7 1 1 4 uc Eo oy SH d 44 5 1 3 127 T EE d Ep i 2 3A 1 VE oe 1 LSBipEAL 1 l pit J ijiet 0 1 2 6 7 1021102210231024 Vssa Von 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Er Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 41 Typical application with ADC Von STM8 V R ZN 0 8V AIN AINx R 10 bit A D Vain NNNNN T oN conversion C V ZNosv On Caoc D 74 88 Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Electrical characteristics 9 3 11 EMC characteris
27. porte 65 Typ Vpp Vou 9 Vpop 5 V high sink ports een 65 Typical NRST Vj and Vu vs Vpp 4 temperatures alana 66 Typical NRST pull up resistance vs Von 4 temperatures 66 Typical NRST pull up current vs Vpp 4 temperatures 2 2 2 ee 67 Recommended reset pin protection 1 ssk akak akak aaa 67 SPI timing diagram slave mode and CPHA 0 1211122222 lakka aaa 69 SPI timing diagram slave mode and CPHA 1 69 SPI timing diagram master mode MUCH 70 ADC accuracy characteristics 2 74 Typical application with ADC 74 32 pin low profile quad flat package xv 79 32 lead very thin fine pitch quad flat no lead package 5 x 5 nanunua 80 Recommended footprint for on board emulation 81 Recommended footprint without on board emulation eee eee eee 81 STM8S903K3 ordering information scheme cece eee eee 84 Doc ID 15590 Rev 1 7 88 www bdtic com ST Introduction STM8S903K3 8 88 Introduction This datasheet contains the description of the STM8S903K3 features pinout electrical characteristics mechanical data and ordering information e Forcomplete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e Eor information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manu
28. to control the timer with external signals or to synchronize with TIM1 or TIM6 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Product overview 4 12 TIM6 8 bit basic timer e 8 bitautoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update e Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM5 Table 3 TIM timer features Timer Timer Counter Prescaler Counting CAPCOM Complem EH synchronization size bits mode channels outputs trigger Ges chaining Any integer from TIM1 1 to 65536 Up down 4 3 Yes Any power of 2 from 1 TIM5 to 32768 Up 3 0 No Yes Any power of 2 from 1 TIM6 to 128 Up 0 0 No 4 13 Analog to digital converter ADC1 STM8S903K3 products contain a 10 bit successive approximation A D converter ADC1 with up to 7 external and 1 internal multiplexed input channels and the following main features e Input voltage range 0 to Vpp e Conversion time 14 clock cycles e Single and continuous and buffered continuous conversion modes e Buffer size n x 10 bits where x number of input channels e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Internal reference voltage on channel AINT This internal reference is constant and can be used for example to
29. which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 Doc ID 15590 Rev 1 85 88 www bdtic com ST STM8 development tools STM8S903K3 12 2 12 2 1 12 2 2 12 3 86 88 Software tools STMB8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raison
30. 1 Reserved PCKEN14 TIM6 PCKEN10 FC PCKEN24 Reserved PCKEN20 Reserved Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Product overview 4 6 4 7 Power management For efficent power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is bas
31. 3 3 33 bytes terase Erase time for 1 block 64 bytes 3 3 33 i 2 Erase write cycles T 85 C 10k Naw program memory cycles Erase write cycles data memory Ta 125 C 300k 1M Data retention program and data memory after 10k erase write cycles Tret 55 C 20 at Ta 55 C RET years Data retention data memory after 300k erase write cycles Tret 85 C 1 at Ta 125 C Supply current Flash programming or 2 M DD erasing for 1 to 128 bytes 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte ky Doc ID 15590 Rev 1 59 88 www bdtic com ST Electrical characteristics STM8S903K3 9 3 6 I O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 36 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 V 0 3 x Von V Input high level Vpp 5V Vum voltage 0 7x Von Vpp 0 3 V V Vhys Hysteresis 700 mV Rpu Pull up resistor Vpp 5 V Vin Vss 30 45 60 kQ Fast I Os 20 ns E Rise and fall time Load 50 pF R F 10 90 Stand
32. 55 9 3 4 Internal clock sources and timing characteristics 57 9 3 5 Memory characteristics 59 9 3 6 I O port pin characteristics 0 0 0 0 eee 60 9 3 7 Reset pin characteristics 66 9 3 8 SPI serial peripheral interface 68 9 3 9 DC interface characteristics 0 0 0 0 000 c cece ee 71 9 3 10 10 bit ADC characteristics 0 00000 ccc eee 72 9 3 11 EMC characteristics 0 0000 75 Package characteristics leeeese 78 10 4 Package mechanical data 79 10 1 1 LQFP package mechanical data 0002 eee eee 79 10 1 2 VFQFPN package mechanical data iss 80 10 2 Thermal characteristics m Rr EN 82 10 2 1 Reference document 82 10 2 2 Selecting the product temperature range saaana aaraa 83 Ordering information llle 84 STM8 development tools luleees 85 12 1 Emulation and in circuit debugging tools 85 Doc ID 15590 Rev 1 3 88 www bdtic com ST Contents STM8S903K3 12 2 Software EE EE 86 12 2 1 STMB8toolset 0 0 cee eee k k kd n 86 12 2 2 Candassemblytoolchains 86 12 3 Programming tools Ee RE RR RE RR EGER aka RR NEE AN 86 13 REVISION history 2a s aei 9 ado d Wr e e s 8 RN 87 4 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10
33. ANE X 76 ESD absolute maximum ratings llli res 76 Doc ID 15590 Rev 1 5 88 www bdtic com ST List of tables STM8S903K3 Table 49 Table 50 Table 51 Table 52 Table 53 6 88 Electrical sensitivities 77 32 pin low profile quad flat package mechanical dats 79 32 lead very thin fine pitch quad flat no lead package mechanical data 80 Thermal characteristics 82 Document revision history 87 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 ky Block diagrams SEELEN pee hia EE e yep E AS ee d dux Rated dd NEEN dE wand 10 Flash memory organisation 13 STM8S903K3 VFQFPN32 LQFP32 pinout 0 aaaea 20 Memory map sx pees Sheed Sieg al Pel ee ae oe ee ais REGE Se RUN A 30 Pin loading conditions 0 0 RI N ba 41 Pin input voltage vua uses eee eee 42 foPUmax VEFSUS VDD uiado eaaa EEEE EEEE EEEE EEEE
34. G_KR IWDG key register 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to Reserved area 13 bytes 0x00 50EF 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer Ox3F register 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to Reserved area 12 bytes 0x00 50FF Doc ID 15590 Rev 1 33 88 www bdtic com ST Memory and register map STM8S903K3 Table 12 General hardware register map continued Address Block Register label Register name iea 0x00 5200 SPI CR1 SPI control register 1 0x00 0x00 5201 SPI CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 ER SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF 0x00 5208 to Reserved area 8 bytes 0x00 520F 0x00 5210 GC CR1 DC control register 1 0x00 0x00 5211 I2C_CR2 DC control register 2 0x00 0x00 5212 IOC FREQR Ic frequency register 0x00 0x00 5213 IOC OARL DC Own address register low 0x00 0x00 5214 12C_OARH DC Own address re
35. IAP and communication routines Figure 2 Flash memory organisation Data Data memory area 640 bytes EEPROM memory Option bytes Programmable area from 64 bytes UBC area 1 page up to 8 Kbytes Remains write protected during IAP in 1 page steps Low density Flash program memory 8 Kbytes Program memory area Write access possible for IAP Doc ID 15590 Rev 1 13 88 www bdtic com ST Product overview STM8S903K3 4 5 14 88 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller Clock controller The clock controller distributes the system clock fuAsrER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safeclock switching Clock sources can be changed safely on the fly in run mode through a configurati
36. IMR register for given Vop and TA conditions 44 Accuracy of HSI oscillator factory calibrated Vpp 5 V Ta 25 C 2 5 1 3 K Vpp lt 5 V 25 C T4 85 C 2 5 2 3 2 95 lt Vpp lt 5 5 V 40 C lt T lt 125 C A SIS 3 2 3 tsu HSI HSI oscillator wakeup time including calibration 10 us Ipp HSI HSI oscillator power consumption 170 250 pA ZS mm cz Refer to application note Data based on characterization results not tested in production Subject to further characterization to give better results Guaranteeed by design not tested in production Figure 17 Typical HSI accuracy at Vpp 5 V vs 5 temperatures 3 00 1 2 00 1 1 00 4 0 00 4 1 00 4 2 00 1 3 00 4 00 4 ee max min 5 00 40 125 d Doc ID 15590 Rev 1 57 88 www bdtic com ST Electrical characteristics STM8S903K3 Figure 18 Typical HSI frequency variation vs Vpp 4 temperatures 25 C 85 C 10 M r 12 C 45 C 0 50 0 00 0 50 i c a a e a i 1 00 1 50 2 00 T T T T i 25 3 3 5 4 45 5 55 6 Von V Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and T4 Table 33 LSI oscillator characteristics Symbol Parameter Conditions Mi
37. Input Output co Alternate B S8 function 2 oo Pin l a 5 1 co Default alternate after Pin name Sle ct cC v 3r no ESI I BI SI a 202 function remap S SI El E 8 2 s option o Z z bit ui Analog input 6 31 PDe AING UART1 HX 1 O X X X HS O3 X X Port D6 UART1 data receive Timer 1 32 PD7 TLI TIM1_CH4 UO X X X HS O3 X X Port D7 Top level interrupt channel 4 AFR6 1 I O pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Table 15 Current characteristics 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain UO P buffer and protection diode to Vpp are not implemented 5 1 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 7 Option bytes When the remapping option is active the default alternate funct
38. Maxat85 Maxat Symbol Parameter Main voltage Flash Clock Typ soi 125 sen Unit regulator model source MvR HSE crystal osc 1030 Operating 16 MHz mode LSI RC osc 128 kHz 200 260 300 On Supply HSE crystal osc 970 current in Power down 16 MHz A DD H active halt mode LSI RC osc i mode 128 kHz 150 200 230 Operating 66 85 110 mode LSI RC osc of 128 kHz Power down 10 20 40 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 24 Total current consumption in active halt mode at Vun 3 3 V Conditions i Max at Maxat Symbol Parameter Main voltage Flash Clock Typ 85 c 125 oc Unit regulary model source MVR HSE crystal osc 550 Operating 16 MHz mode LSI RC osc 128 kHz 200 260 290 On Supply HSE crystal osc 970 current in Power down 16 MHz A DD H active halt mode LSI RC osc g mode 128 kHz 150 200 230 parann 66 80 105 mode LSI RC osc G Power down 128 kHz 10 18 35 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register ky Doc ID 15590 Rev 1 49 88 www bdtic com ST Electrical characteristics STM8S903K3 Total current consumption in halt mode
39. R ERREUR RR REP EE AERA AEN A 15 48 Auto wakeup counter 0000 sss saak aaa ee 16 4 9 Se WEE 16 4 10 TIM1 16 bit advanced control timer 16 4 11 TIM5 16 bit general purpose timer aaa a 16 4 12 TIM6 8 bitbasictimer 0 es 17 4 13 Analog to digital converter DCH 17 4 14 Communication interfaces 17 AAG WARD wisi ste di died pede ee da we Oke ah coh wae a oe 18 EC 18 SCIAS c HE 19 5 Pinout and pin description 20 5 1 Alternate function remapping 22 2 ssn saka ee 24 6 Interrupt vector Mapping 25 7 ub eta TT 26 8 Memory and register map eee 30 2 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Contents 10 11 12 8 1 uunc ano TP LAT 30 8 2 EECHER cheese a ask AV e E Ee Ee a EN Electrical characteristics na 41 9 1 Parameter conditions 41 9 1 1 Minimum and maximum values 41 9 1 2 Typical values 212211 03 a na snak R Ra RR R e en 41 9 1 3 Typical CuUIVeS osha dE pex rS a Peewee EG RAE RE 41 9 1 4 Loading capacitor aR 6 rk N 0 9 9 0 8 a ECR N RRR H RR dada sanak 41 9 1 5 Pin input voltage ssseseeeeee RII 42 9 2 Absolute maximum ratings 42 9 3 Operating conditions 33x sexes ES teehee REP EC RERES arka Ra 44 9 3 1 VCAP external capacitor 45 9 3 2 Supply current characteristics 121222222a naan a 46 9 3 3 External clock sources and timing characteristics
40. RODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 88 88 Doc ID 15590 Rev 1 ky www bdtic com ST
41. S levels 0 3Vpp and 0 7 Vpp 70 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Electrical characteristics 9 3 9 PC interface characteristics Table 42 C characteristics Standard mode DC Fast mode CH Symbol Parameter Unit MinO Max Min Max twscLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsuspa SDA setup time 250 100 tsp SDA data hold time o 9 o9 9009 SDA SDA and SCL rise time 1000 300 ns tscL SDA SDA and SCL fall time 300 300 lici ty stay START condition hold time 4 0 0 6 us tsustay Repeated START condition setup time 4 7 0 6 lsusro STOP condition setup time 4 0 0 6 US STOP to START condition time bus tw STO STA free 4 7 1 3 US Cp Capacitive load for each bus line 400 400 pF 1 fwaster must be at least 8 MHz to achieve max fast DC speed 400kHz Data based on standard DC protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL d Doc ID 15590 Rev 1 71 88 www bdtic com ST Electrical characteristics STM8S903K3 9 3 10 10 bit ADC characteristics Subject to general operating conditions for Vpp faster and TA unless oth
42. TM8S903K3 Electrical characteristics Figure 24 Typ Vo Vpp 5 V standard ports 40C m 25 C 125 85 C 125 C lo mA Figure 25 Typ Vo Vpp 3 3 V true open drain ports lg mA Figure 26 Typ Vo 8 Vpp 5 V true open drain ports 40 C a 25 C 85 C 154 125 C Doc ID 15590 Rev 1 63 88 www bdtic com ST Electrical characteristics STM8S903K3 64 88 Figure 27 Typ Vo Vpp 3 3 V high sink ports 40C m 25 C 1 25 85 C 125 C 15 1 lo mA Figure 28 Typ Vo Vpp 5 V high sink ports 25 lo mA Figure 29 Typ Vpp Vou 9 Vpp 3 3 V standard ports 40C a 25 C 85 C 125 C d Voo Mall Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Electrical characteristics Figure 30 Typ Vpp Von Vpp 5 V standard ports 40 C 25 C 85 C 2 1 5 7 125 C Voo WH V lo MA Figure 31 Typ Vpp Von Vpp 3 3 V high sink ports
43. Table 10 STM8S903K3 alternate function remapping bits 1 0 AFR1 option bit value AFRO option bit value HO port Alternate function mapping AFR1 and AFRO remapping options inactive o 0 Default alternate functions PC5 TIM5_CH1 0 1 PC6 TIM1_CH1 PC7 TIM1_CH2 PA3 SPI NSS i M PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5 CH1 PC6 TIM1 CH1 PC7 TIM1 CH2 1 1 PC2 TIM1_CH3N PC1 TIM1_CH2N PE5 TIM1_CH1N PA3 UART1_TX PF4 UART1_RX 1 Refer to pinout description Doc ID 15590 Rev 1 29 88 www bdtic com ST Memory and register map STM8S903K3 8 8 1 30 88 Memory and register map Memory map Figure 4 Memory map 0x00 0000 0x00 O3FF 0x00 4000 0x00 427F 0x00 4280 0x00 47FF 0x00 4800 0x00 480A 0x00 480B 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 9FFF 0x00 A000 0x02 7FFF RAM 1 Kbyte Reserved 640 bytes data EEPROM Reserved Option bytes Reserved GPIO and periph reg see Table 11 and Reserved CPU SWIM debug ITC registers see Table 13 d 32 interrupt vectors Flash program memory 8 Kbytes Reserved Doc ID 15590 Rev 1 D www bdtic com ST STM8S903K3 Memory and register map 8 2 d Register map
44. Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 ky STM8S903K3 access line features 9 Peripheral clock gating bit assignments in CLK_PCKENR 1 2 registers 14 TIM timer features 17 Legend abbreviations 0 000 eee 21 VFQFPN32 LQFP32 pin description 21 Interrupt mapping 6 RR IRR HI K RR b aa i 25 Option Dytes 2 14 issus rase ber seeded Eden debts APR R EE ud tea Pa eb pg es 26 Option byte description 27 STM8S903K3 alternate function remapping bits 7 2 lisse 28 STM8S903K3 alternate function remapping bits 1 0 llle 29 I O port hardware register map 31 General hardware register map 32 CPU SWIM debug module interrupt controller registers 39 Voltage characteristics se a e R x x e e R R RRR RRR RRR Ren 42 Current characteristics unaua aaue 43 Thermal characteristics e x e R e e e K RRR en 43 General operating conditions 44 Operating conditions at power up power down 45 Total current consumption with code execution in run mode at Vpp 5 V 46 Total current consumption with code exe
45. V np fopu MHz FUNCTIONALITY NOT GUARANTEED IN THIS AREA GUARANTEED T4 40 to 125 4 SUPPLY VOLTAGE V d Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Electrical characteristics Table 18 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 2 oo typp o us V Vpp fall time rate 2 oo Reset release ils ttemp delay Vpp rising 1 7 ms Power on reset Vr ec 2 6 2 7 2 85 v Brown out reset Vm ies 2 5 2 65 2 8 Brown out reset VHYS BOR hysteresis Td mv 1 Reset is always generated after a treyp delay The application must ensure that Vpp is still above the minimum ooperating voltage Vpp min when the trgyp delay has elapsed 9 3 1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cer to the Vcap pin Cgxz is specified in Table 17 Care should be taken to limit the series inductance to less than 15 nH Figure 8 External capacitor Cer ESR e Rleak 565 ESL 1 ESR is the equivalent series resistance and ESL is the equivalent inductance d Doc ID 15590 Rev 1 45 88 www bdtic com ST Electrical characteristics STM8S903K3 9 3 2 Supply current characteristics The current consumption is measured as described in Figure 6 on pag
46. a 21 bytes 0x00 523F 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 SE mode register 0x00 TIM1 0x00 5259 TIM1_CCMR2 TIM1 POPE mode register 0x00 0x00 525A TIM1 CCMR3 TIM1 EE mode register 0x00 0x00 525B TIM1_CCMR4 TIM1 PER mode register 0x00 0x00 525C TIM1_CCER1 TIM1 SE enable register 0x00 0x00 525D TIM1 CCER2 TIM1 EE enable register 0x00 0x00 525E TIM1_CNTRH TIM1 counter high 0x00 ky Doc ID 15590 Rev 1 35 88 www bdtic com ST Memory and register map STM8S903K3 Table 12 General hardware register map continued Address Block Register label Register name iea 0x00 525F TIM1 CNTRL TIM1 counter low 0x00 0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1_RCR TIM1 repetiti
47. al PMO051 e Forinformation on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e Forinformation on the STMB core please refer to the STM8 CPU programming manual PM0044 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Description 2 Description The STM8S908K3 8 bit microcontroller offers 8 Kbytes Flash program memory plus integrated true data EEPROM The STM8S microcontroller family reference manual RM0016 refers to devices in this family as low density They provide the following benefits Reduced system cost Integrated true data EEPROM for up to 300 k write erase cycles A High system integration level with internal clock oscillators watchdog and brown out reset Performance and robustness 16 MHz CPU clock frequency Robust I O independent watchdogs with separate clock source Clock security system Full documentation and a wide choice of development tools Advanced core and peripherals made in a state of the art technology Table 1 STM8S903K3 access line features 2 o o v 2 2 2 4 a 2 E 3 8 2 2 G E l lt l El o 5 gt z E 258528 Fe 29 age 55385 x PET s Device IER E 8 E E m S r 2 Peripheral set 2 S o s E 2205 887 H S SP BER 5 a o Q L G ER S Multipurpose timer TIM1 SPI DC UART window WDG STM8S903K3 32
48. ance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code STM8 toolset STMB8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST visual develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com e Haisonance C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more info
49. ard and high sink I Os 125 ne Load 50 pF Digital input leakage likg current 9 Vss lt ViN lt Vpp 1 UA Analog input likg ana Kette Geer Vss Vin S Voo 290 Leakage current in Iniecti ATA 1 Ikg inj adjacent I O njection current 4 m 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 60 88 Doc ID 15590 Rev 1 D www bdtic com ST STM8S903K3 Electrical characteristics Figure 20 Typical Vu and Vu vs Vpp 4 temperatures 40 C 6 25 C 5 85 C 1250 A 2 I gt 3 E gt 2 1 0 25 3 85 4 45 5 55 6 Voo V Figure 21 Typical pull up resistance vs Von 4 temperatures 40 C 60 25 C 85 C 55 125C g 50 8 H 8 B8 K a 45 a i 4 3 a 35 30 T T T T T 25 3 35 4 45 5 55 6 Vo VI Figure 22 Typical pull up current vs Vpp 4 temperatures 140 R Ss 2 e E4 B 80 g 60 ae i wer 25 C 40 85 C d 1257 20 E Pal 125 C pd nk 0 1 2 3 4 5 6 Voo V d Doc ID 15590 Rev 1 61 88 www bdtic com ST Electrical characteristics STM8S903K3
50. cution in run mode at Vpp 3 8V 47 Total current consumption in wait mode at Vpp2 DN 48 Total current consumption in wait mode at Vpp 2 N lesen 48 Total current consumption in active halt mode at Vpp 5 V 21 eee eee u 49 Total current consumption in active halt mode at Vpp 233N 222 49 Total current consumption in halt mode at Von B VY 2222 kkk kkk aaa a 50 Total current consumption in halt mode at Von 32N lakka a 50 Wakeup mes iussus aum orm REI eIGXGa du RR RR iu d r 50 Total current consumption and timing in forced reset state nuuanu uaaa 51 Peripheral current consumption re 51 HSE user external clock characteristics liliis 55 HSE oscillator characteristics llle 56 HSI oscillator characteristics llle ren 57 LSI oscillator characteristics 2 1s sa sasa sasaran 58 RAM and hardware registers skaka aaa aaa skara 59 Flash program memory data EEPROM memory 59 UO static characteristics 2s n 60 Output driving current standard ports 00 cece eee ee 62 Output driving current true open drain porte 62 Output driving current high sink porte 62 NRST pin characteristics 66 SPI characteristics 68 best EE EE 71 ADC characteristics 72 ADC accuracy with Rain lt 10kQ Vpp zb Loue ee ee 73 ADC accuracy with Rain lt 10 kQ RAIN Vbpp 2g Mese ave l auo acr b Edd s 73 EMS E EE 75 EMI dala 220
51. d Table 10 for alternate function remapping decriptions of bits 7 2 and 1 0 respectively OPT3 HSITRIM High speed internal clock trimming register size 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active Doc ID 15590 Rev 1 27 88 www bdtic com ST Option bytes STM8S903K3 28 88 Table 8 Option byte description continued Option byte no OPT4 Description EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilizati
52. d on characterization results not tested in production SU HSE is the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 16 HSE oscillator circuit diagram l R I jm Cot Lm Dos fuse to core gt STM8 Rr C OSCIN e mee E L e Im Resonator Consumption Lal control Resonator HE 2 OSCOUT Ci 56 88 HSE oscillator critical g formula Jmorit 2x IIx HSE x R 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 1 C 2 C Grounded external capacitance Hm gt gt Imcrit Doc ID 15590 Rev 1 d www bdtic com ST STM8S903K3 Electrical characteristics 9 3 4 Subject to general operating conditions for Vpp and T4 High speed internal RC oscillator HSI Table 32 HSI oscillator characteristics Internal clock sources and timing characteristics Symbol fusi Parameter Frequency Conditions Min Typ 16 Max Unit MHz ACCusi Accuracy of HSI oscillator User trimmed with CLK HSITR
53. data input AFR4 ADC PB4 l2C_SCL 3 2 external 12 ADC_ETR UO X X X O1 T X Port B4 FC clock trigger AFR4 Analog input 3 13 PB3 AIN3 TIM1_ETR 1 O X X X HS O3 X X Port B3 Timer 1 external trigger Analog input 2 14 PB2 AIN2 TIM1_CH3N 1 O X X X HS O3 X X Port B2 Timer 1 inverted channel 3 Analog input 1 15 PB1 AIN1 TIM1 CH2N UO X X X HS O3 X X Port B1 Timer 1 inverted channel 2 Analog input 0 16 PBO AINO TIM1 CH1N 1 O X X X HS O3 X X Port BO Timer 1 inverted channel 1 Timer 1 PE5 SPI_LNSS SPI master slave inverted 17 ln CH1N VO KX LOS URS CIR X ae Port ES Jeepen channel 1 AFR1 0 PCI TIM1_CH1 Timer 1 channel 1 res 18 UART1_CK 1 O X X X HS O3 X X Port C1 h TIM1_CH2N UART1 clock channel 2 AFR1 0 Timer 1 PC2 TIM1_CH2 inverted 19 TIM1_CH3N 1 O X X X HS O3 X X Port C2 Timer 1 channel 2 channel 3 AFR1 0 Top level interrupt AFR3 20 PESTIMT CAs T I UO X X X HS O3 X X Port C3 Timer 1 channel 3 Timer 1 TIM1_CHI1N inverted channel 1 AFR7 22 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Pinout and pin description Table 5 VFQFPN32 LQFP32 pin description continued Input Output C Alternate S8 function e o oo Pin Sioa 5 1 co Default alternate after Pin name Sle E
54. e 42 Total current consumption in run mode The MCU is placed under the following conditions e AN UO pins in input mode with a static value at Vpp or Vas no load e Al peripherals are disabled clock stopped by peripheral clock gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and T Table 19 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 3 fopu MASTER 16 MHz HSE user ext clock 16 MHz 2 2 35 HSI RC osc 16 MHz 1 7 2 Supply current in run fopy fmastep 128 HSE user ext clock 16 MHz 0 86 mage coe 125 ME HSI RC osc 16 MHz 0 7 0 87 executed from RAM fopu fuaster 128 fcpu fMAsTER 128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN HSE crystal osc 16 MHz 4 5 mA CPU MASTER 16 MHz HSE user ext clock 16 MHz 4 3 4 75 HSI RC osc 16 MHz 3 7 4 5 knee dd CPU MASTER HSI RC osc 16 MHz 8 2 0 84 1 05 current in run 2 MHz mode code f f 128 executed from CPU MASTER 77 HSI RC osc 16 MHz 0 72 0 9 125 kHz Flash foru fuaster 128 fopu MASTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d 46 88 Doc ID 15590 Rev 1
55. ea 17 bytes 0x00 50B2 0x00 50B3 RST RST_SR Reset status register XX 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50C0 sie CLK_ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 32 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Memory and register map d Table 12 General hardware register map continued Address Block Register label Register name deelt Status 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register EE 0x00 50C6 CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CLK_CSSR Clock security system register 0x00 0x00 50C9 CLK_CCOR Configurable clock control register 0x00 0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB CLK CANCCR CAN clock control register 0x00 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register XX 0x00 50CD CLK_SWIMCCR SWIM clock control register x0 0x00 50CE to Reserved area 3 bytes 0x00 50D0 0x00 50D1 WWDG_CR WWDG control register Ox7F WWDG 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to Reserved area 13 bytes 00 50DF 0x00 50E0 IWD
56. ed on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Doc ID 15590 Rev 1 15 88 www bdtic com ST Product overview STM8S903K3 4 8 4 9 4 10 4 11 16 88 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt
57. erwise specified Table 43 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 2 95 to 5 5 V 1 4 fanc ADC clock frequency MHz Von 4 5 to 5 5 V 1 6 Van Conversion voltage range l Vas Vpp V Internal bandgap reference 8 VBGREF voltage Vpp 2 95t0 5 5 V 1 19 1 22 1 25 V Internal sample and hold Cape capacitor 3 pF fap 4 MHz 0 75 tg Minimum sampling time E us fADC 6 MHz 0 5 terap Wake up time from standby 7 US Minimum total conversion time Tano 4 Mhz dm Hs tcony including sampling time 10 bit fanc 6 MHz 2 33 US resolution 14 TR 1 During the sample time the input capacitance Cam 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming D 72 88 Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Electrical characteristics Unit LSB Table 44 ADC accuracy with Ran lt 10 kQ Vpp 5 V Symbol Parameter Conditions Typ Max fapc 2 MHz 1 6 TBD EA Total unadjusted error fApc 4 MHz 2 2 TBD fapc 6 MHz 24 TBD fapc 2 MHz 1 1 TBD IEg Offset error fA
58. gister high 0x00 0x00 5215 Reserved 0x00 5216 GC DR DC data register 0x00 0x00 5217 DC DC SR1 DC status register 1 0x00 0x00 5218 I2C_SR2 DC status register 2 0x00 0x00 5219 I2C_SR3 DC status register 3 OxOx 0x00 521A I2C ITH lc interrupt control register 0x00 0x00 521B I2C CCRL DC Clock control register low 0x00 0x00 521C I2C CCRH DC Clock control register high 0x00 0x00 521D I2C_TRISER DC TRISE register 0x02 0x00 521E Il2C PECH DC packet error checking register 0x00 0x00 521F to Reserved area 17 bytes 0x00 522F 34 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Memory and register map Table 12 General hardware register map continued Address Block Register label Register name i 0x00 5230 UART1 SR UART1 status register COh 0x00 5231 UART1 DR UART1 data register xxh 0x00 5232 UART1_BRR1 UART1 baud rate register 1 00h 0x00 5233 UART1 BRR2 UART1 baud rate register 2 00h 0x00 5234 UART1_CR1 UART1 control register 1 00h 0x00 5235 UART1 UART1_CR2 UART1 control register 2 00h 0x00 5236 UART1_CR3 UART1 control register 3 00h 0x00 5237 UART1_CR4 UART1 control register 4 00h 0x00 5238 UART1_CR5 UART1 control register 5 00h 0x00 5239 UART1_GTR UART1 guard time register 00h 0x00 523A UART1_PSCR UART1 prescaler register 00h 0x00 523B to Reserved are
59. haracteristics Symbol Ratings Value Unit TstG Storage temperature range 65 to 150 Ty Maximum junction temperature 150 ky Doc ID 15590 Rev 1 43 88 www bdtic com ST Electrical characteristics STM8S903K3 9 3 44 88 Operating conditions Table 17 General operating conditions Symbol Parameter Conditions Min Max Unit fopy Internal CPU clock frequency 0 16 MHz Vpp Standard operating voltage 2 95 5 5 V lt lt Cext VCAP external capacitor m Seet 470 3300 nF Power dissipation at LQFP32 330 TA 85 C for suffix 6 VFQFPN32 550 Pp mW Power dissipation at LQFP32 83 TA 125 C for suffix 3 VFQFPN32 110 Ambient temperature YLE Maximum power dissipation 40 85 suffix version TA ATHE temperature SES Maximum power dissipation 40 125 C suffix version 6 suffix version 40 105 Ty Junction temperature range 3 suffix version 40 130 9 1 Care should be taken when selecting the capacitor due to its tolerance as well as its dependency on temperature DC bias and frequency in addition to other factors 2 To calculate Pp TA use the formula Pomax T mas TAGA see Section 10 2 Thermal characteristics with the value for Tjmax given in Table 17 and the value for Oj4 given in Table 52 Thermal characteristics 3 T lman is given by the test limit Above this value the product behavior is not guaranteed Figure 7 fcpumax Versus
60. ile quad flat package 7 x 7 D1 D3 24 32 Pin 1 identification 1 CN ccc C ES E1 E 4 gt ON Ce DV ME Table 50 32 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 C 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits Doc ID 15590 Rev 1 79 88 www bdtic com ST Package characteristics STM8S903K3 10 1 2 80 88 VFQFPN package mechanical data Figure 43 32 lead very thin fine pitch quad flat no lead package 5 x 5 Seating plane C E2 Bottom view 42 ME Table 51 32 lead very thin fine pitch quad flat no lead package mechanica
61. ion is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 D 24 88 Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Interrupt vector mapping 6 Interrupt vector mapping Table 6 Interrupt mapping Description aem OTT Vector address RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level Interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes Yes 1 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 EXTI5 Port F interrupt Yes Yes 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIMI a cd 0x00 8034 12 TIM1 TIM1 capture compare 0x00 8038 18 TIM5 TIM5 update overflow trigger 0x00 803C 14 TIM5 TIM5 capture compare 0x00 8040 15 Reserved 0x00 8044 16 Reserved 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19
62. k frame Reception Detects 11 bit break frame Maximum speed 8 Mbit s fuAsrER 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Product overview 4 14 3 ISC master features Clock generation Start and stop generation ISC slave features Programmable DC address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz Doc ID 15590 Rev 1 19 88 www bdtic com ST Pinout and pin description STM8S903K3 5 Figure 3 Pinout and pin description NRST OSCIN PA1 OSCOUT PA2 Vss VCAP Von UART1_TX SPI_NSS TIM5_CH3 HS PA3 UART1_RX PF4 STM8S903K3 VFQFPN32 LQFP32 pinout S O x EH G Z o 20 9 xxr e xXx ISI d 1859 2 GEW z BEER GZ ZE St m SE E L E St zez G910uX9z JZZUZSZE E ESSnssgQr DHHDHHHDHA fa es is wea aga Opes gen sy PD6 PD5 PD4 PD3 PD2 PD1 PDO co JO om E GM w a w 0 N e D o N
63. l NRST pull up resistance vs Vpp 4 temperatures 40 C 60 25 C 85 C e 125C s 45 a gg eg m 40 35 30 F s 25 3 3 5 4 5 5 55 6 Voo V 66 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Electrical characteristics Figure 35 Typical NRST pull up current vs Vpp 4 temperatures 140 120 100 NRESET Pull Up current 60 40 C 40 t isa 85 C li 125 C oe r 0 1 2 3 4 5 6 WO The reset network shown in Figure 36 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu max level specified in Table 36 Otherwise the reset is not taken into account internally Figure 36 Recommended reset pin protection Vpp STM8 Rpu External NRST Internal reset reset e Filter circuit 0 01 pF optional Doc ID 15590 Rev 1 67 88 www bdtic com ST Electrical characteristics STM8S903K3 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 41 are derived from tests performed under ambient temperature fmasTter frequency and Vpp supply voltage conditions tyaster l fuAsTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO
64. l data mm inches Dim Min Typ Max Min Typ Max A 0 80 0 90 1 00 0 0315 0 0354 0 0394 A1 0 0 02 0 05 0 0008 0 0020 A3 0 20 0 0079 b 0 18 0 25 0 30 0 0071 0 0098 0 0118 D 4 85 5 00 5 15 0 1909 0 1969 0 2028 D2 3 20 3 45 3 70 0 1260 0 1457 E 4 85 5 00 5 15 0 1909 0 1969 0 2028 E2 3 20 3 45 3 70 0 1260 0 1358 0 1457 e 0 50 0 0197 L 0 30 0 40 0 50 0 0118 0 0157 0 0197 ddd 0 08 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Doc ID 15590 Rev 1 D www bdtic com ST STM8S903K3 Package characteristics Figure 44 Recommended footprint for on board emulation date Ve 0 8mm 0 032 4mm 0 157 Fn 0 5mm i 1 65mm 0 065 HL 0 9mm 0 035 0 3mm 0 012 4mm 0 157 ai15319 Bottom view 1 Drawing is not to scale Figure 45 Recommended footprint without on board emulation prs De rin mu spese 3 30 1 280 num 258 a e Lr SR re I 3 30 4 1 Drawing is not to scale 2 Dimensions are in millimeters Doc ID 15590 Rev 1 81 88 www bdtic com ST Package characteristics STM8S903K3 10 2 Thermal characteristics The maximum chip junction temperature T imas must never exceed the values given in Table 17 General operating conditions on page 44 The maximum chip juncti
65. lash memory e 640 bytes true data EEPROM User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 The size of the UBC is programmable through the UBC option byte Table 8 in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory Up to 8 Kbytes minus UBC e User specific boot code UBC Configurable up to 8 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the
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67. mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals or to synchronize with TIM5 or TIM6 Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM5 16 bit general purpose timer 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 3 individually configurable capture compare channels PWM mode Interrupt sources 3 x input capture output compare 1 x overflow update Synchronization module
68. monitor Vpp It is independent of variations in Vpp and ambient temperature T4 e Analog watchdog interrupt e External trigger input e Trigger from TIM1 TRGO e Endofconversion EOC interrupt 4 14 Communication interfaces The following communication interfaces are implemented e UART 1 Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode single wire mode LIN2 1 master capability e SPI Full and half duplex 8 Mbit s e BC Up to 400 Kbit s ky Doc ID 15590 Rev 1 17 88 www bdtic com ST Product overview STM8S903K3 4 14 1 UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fepy 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fcpu 16 LIN master mode 4 14 2 SPI 18 88 Emission Generates 13 bit synch brea
69. n Typ Max Unit figi Frequency 110 128 150 kHz Luten LSI oscillator wake up time 7 Hs Ibos LSI oscillator power consumption 5 UA Figure 19 Typical LSI frequency variation vs Vpp 4 temperatures 25 C 85 C 5 00 F r T 125 C 4 00 45C 3 00 At t 2 00 S 1009 2 S 0 00 X EH 1 00 2 00 3 00 4 00 5 00 2 25 3 3 5 4 45 5 55 6 Voo V 58 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Electrical characteristics 9 3 5 Memory characteristics RAM and hardware registers Table 34 RAM and hardware registers Symbol VRM Parameter Conditions Min Data retention mode Halt mode or reset 2 8 V Typ Max Unit 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Referto Table 18 on page 45 for the value of Vit max Flash program memory data EEPROM memory Table 35 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage Von all modes execution write erase fcpu 16 MHz ees 9 Y Standard programming time including erase for byte word block 6 6 6 ion 1 byte 4 bytes 64 bytes Fast programming time for 1 block 64 ES
70. n in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 6 fcpu MASTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply fepy f 128 lppqwri current in o HSI RC osc 16 MHz 0 7 0 88 mA wait mode foru fuasrER 128 2 15 625 kHz HSI RC osc 16 MHz 8 0 45 0 57 fcpu fuAsTER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 22 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 1 fcpu MASTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply fopu f 128 IpDwrn current in EE HSI RC osc 16 MHz 0 7 0 88 mA wait mode fopu fuAsrER 128 2 15 625 kHz HSI RC osc 16 MHz 8 0 45 0 57 fcpu fMAsTER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 48 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Electrical characteristics Total current consumption in active halt mode Table 23 Total current consumption in active halt mode at Vpp 5 V Conditions 1
71. ndent watchdog Communications interfaces m UART with clock output for synchronous operation Smartcard IrDA LIN master mode m SPlinterface up to 8 Mbit s m DC interface up to 400 Kbit s Analog to digital converter ADC m 10 bit 1 LSB ADC with up to 7 multiplexed channels 1 internal channel scan mode and analog watchdog I Os m Up to 28 I Os on a 32 pin package including 21 high sink outputs m Highly robust I O design immune against current injection m Development support Embedded single wire interface module SWIM for fast on chip programming and non intrusive debugging Doc ID 15590 Rev 1 1 88 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to change without notice www st com www bdtic com ST Contents STM8S903K3 Contents 1 Introd ction EE 8 2 D esCHDpHOD ou uui dmm epee E RRR RRR Ka Kyn EROR KR Ota eee 9 3 Block diagram ss his eu 63 2372 E eat oae eu 678 0879 93 oa hai 10 4 Product overview ue aucun D n e NENT RR t Re i 11 4 1 Central processing unit GTM 11 4 2 Single wire interface module SWIM and debug module DM 12 4 3 Interrupt controller ag 5 00 s n EROR ERR x ERG ehe me RR cae 12 4 4 Flash program and data EEPROM memory 13 45 Clock controller a nn EEN Ae r teases EET EE E P ER 14 4 6 Power management 0 000 eee aaa aaa aaa 15 4 7 Watchdogtimers iue RR R
72. on 100 of the devices with an ambient temperature at T4 25 C and T4 Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 X Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 X Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 5 Figure 5 Pin loading conditions STM8 PIN 50PF Doc ID 15590 Rev 1 41 88 www bdtic com ST Electrical characteristics STM8S903K3 9 1 5 9 2 42 88 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 6 Figure 6 Pin input voltage STM8 PIN
73. on counter register 0x00 0x00 5265 TIM1 CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 Mu TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1_CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1_CCR3H_ TIM1 capture compare register 3 high 0x00 0x00 526A TIM1_CCR8L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1_CCR4H_ TIM1 capture compare register 4 high 0x00 0x00 526C TIM1 CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1 BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 0x00 5270 to Reserved area 147 bytes 0x00 52FF 0x00 5300 TIM5 CR1 TIM5 control register 1 0x00 0x00 5301 TIM5_CR2 TIM5 control register 2 0x00 0x00 5302 TIM5 SMCR TIM5 slave mode control register 0x00 0x00 5303 TIM5 IER TIMB interrupt enable register 0x00 0x00 5304 TIM5_SR1 TIM5 status register 1 0x00 0x00 5305 TIM5_SR2 TIMS status register 2 0x00 0x00 5306 TIM5_EGR TIM5 event generation register 0x00 0x00 5307 TIM5 TIM5 CCMR1 TIM5 EE mode register 0x00 0x00 5308 TIM5 CCMR2 TIM5 EE mode register 0x00 0x00 5309 TIM5 CCMR3 TIM5 SE mode register 0x00 0x00 530A TIM5_CCER1 TIM5 EE enable register 0x00 0x00 530B TIM5 CCER2 TIM5 SE enable register 0x00 36 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Memory and register map
74. on register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources Four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN2
75. on temperature T max in degrees Celsius may be calculated using the following equation TJmax Tamax Ppmax X ja Where Tanav is the maximum ambient temperature in C Oy is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pi Omax PDmax Pintmax Promax e Pintmax IS the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pi omax represents the maximum power dissipation on output pins Where Pyomax No lol Z Vpp Von Ton taking into account the actual Vo Jo and Vou log of the I Os at low and high level in the application Table 52 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient a LQFP 32 7 x 7 mm ii did Thermal resistance junction ambient P Dan VFQFPN32 5x5mm SS cM 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment 10 2 1 Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org 82 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Package characteristics 10 2 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 11 Ordering information on page 84 The following example shows how to
76. on time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles Table 9 STM8S903K3 alternate function remapping bits 7 2 Option byte no OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate functions 1 Port C3 alternate function TIM1 CH1N port C4 alternate function TIM1 CH2N AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate function 1 Port D7 alternate function TIM1 CHA AFRB5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate function 1 Port DO alternate function CLK CCO AFRA Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions 1 Port B4 alternate function ADC ETH port P5 alternate function TIM1_BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive Default alternate functions 1 Port C4 alternate function AIN2 port D2 alternate function AIN3 port D4 alternate function UART1_CK 1 Do not use more than one remapping option in the same port 2 Refer to pinout description D Doc ID 15590 Rev 1 www bdtic com ST STM8S903K3 Option bytes
77. p Output T True open drain OD Open drain PP Push pull Reset state is shown in bold Table 5 VFQFPN32 LQFP32 pin description input Output go Alternate Ss function Pin o SE e o Default alternate after Pin name a2 E eis 3t e no GIS z3 olg gjalla 5 function remap 635 2c 2 ojej E iJ option 2 bit OI 1 NRST IO X Reset 2 PA1 OSCINO vo x x x O1 X X Port A1 ES 3 PA2 OSCOUT Vo X X X oul X X Port A2 r 4 Vss Digital ground 5 VCAP 1 8 V regulator capacitor 6 Vpp S Digital power supply SPI master slave select PA3 TIM5_CH3 l 7 SPI NSS UART1 TX 1 O X X X HS O3 X X Port A3 Timer 5 channel 3 AFR1 UART1 data transmit AFR1 0 UART1 data 8 PFA UART1 RX UO X X O1 X X Port F4 receive AFR1 0 9 PB7 yo O1 Port B7 10 PB6 O X X O1 X X Port B6 ky Doc ID 15590 Rev 1 21 88 www bdtic com ST Pinout and pin description STM8S903K3 Table 5 VFQFPN32 LQFP32 pin description continued Input Output cl Alternate m 23 function E DIS o 0 Pin Sioa 5 1 co Default alternate after Pin name Sle ctt a 3r no EIS 3252 a ZS function remap S SI E5 z g29 st option gl 2 bit x I l Timer 1 PB5 I2C SDA 3 2 break 11 TIM1_BKIN UO X X X O1 T X Port B5 FC
78. pc 4 MHz 1 5 TBD fapc 6 MHz 1 8 TBD fapc 2 MHz 1 5 TBD lEg Gain error fApc 4 MHz 2 1 TBD fapc 6 MHz 2 2 TBD fapc 2 MHz 0 7 TBD lEpl Differential linearity error fapc 4 MHz 0 7 TBD fapc 6 MHz 0 7 TBD fapc 2 MHz 0 6 TBD IE Integral linearity error 2 fapc 4 MHz 0 8 TBD fapc 6 MHz 0 8 TBD 1 Data characterization in progress 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for In up and Zlins Piny IN Section 9 3 6 does not affect the ADC accuracy Table 45 ADC accuracy with Rain lt 10 kQ RAIN Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fADC 2 MHz 1 6 TBD IE Total unadjusted error fapc 4 MHz 1 9 TBD fapc 2 MHz 1 TBD lEol Offset error E fADC 4 MHz 1 5 TBD fapc 2 MHz 1 3 TBD IEg Gain error E LSB fADC 4 MHz 2 TBD fapc 2 MHz 0 7 TBD lEpl Differential linearity error E fADC 4 MHz 0 7 TBD fapc 2 MHz 0 6 TBD IE I Integral linearity error E fADC 4 MHz 0 8 TBD 1 Data characterization in progress ky Doc ID 15590 Rev 1 73 88 www bdtic
79. red from interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK ICKR register 5 Configured by the AHALT bit in the FLASH_CR1 register 6 Plus 1 LSI clock depending on synchronization 50 88 Doc ID 15590 Rev 1 D www bdtic com ST STM8S903K3 Electrical characteristics d Total current consumption and timing in forced reset state Table 28 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state SE UA Vpp 3 8 V 300 tRESETBL Reset pin release to vector fetch 150 US 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vas Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T HSI internal RC fcpy fuAsrER 16 MHz Vpp 5 V Table 29 Peripheral current consumption Symbol Parameter Typ Unit Ippqim1 TIM1 supply current 210 Ippcrims TIM5 supply current 130 IDD TIM6 TIM6 timer supply current 50 Ipo uanri UART1 supply current 120 UA Ippse SPI supply current 45 Ipp i c CC supply current 65 IDD ADC1 ADC1 supply current when converting 1000 1 Data based on a differential lnn measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no UO pads toggling Not tested in production Data
80. rmation see www raisonance com e STMS8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Revision history 13 Revision history Table 53 Document revision history Date 30 Apr 2009 Revision 1 Changes Initial revision Doc ID 15590 Rev 1 87 88 www bdtic com ST STM8S903K3 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsib
81. stics Static latch up Two complementary static tests are required on six parts to assess the latch up performance e A supply overvoltage applied to each power supply pin A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 49 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class Ta 85 C A Ta 125 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard Doc ID 15590 Rev 1 77 88 www bdtic com ST Package characteristics STM8S903K3 10 Package characteristics To meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 78 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Package characteristics 10 1 10 1 1 d Package mechanical data LQFP package mechanical data Figure 42 32 pin low prof
82. ta buffer registers 0x00 0x00 53F3 0x00 53F4 to Reserved area 12 bytes 0x00 53FF ky Doc ID 15590 Rev 1 37 88 www bdtic com ST Memory and register map STM8S903K3 Table 12 General hardware register map continued Address Block Register label Register name Pose status 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC_CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high 0x00 0x00 5405 ADC_DRL ADC data register low 0x00 0x00 5406 ADC TDRH ADC Schmitt n disable register 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register 0x00 ADC1 low 0x00 5408 contd ADG HTRH ADC high threshold register high 0x03 0x00 5409 ADC HTRL ADC high threshold register low OxFF 0x00 540A ADC_LTRH ADC low threshold register high 0x00 0x00 540B ADC LTRL ADC low threshold register low 0x00 0x00 540C ARG AWSRH ADC analog n status register 0x00 0x00 540D ADC ONERE ADC analog KEE status register 0x00 0x00 540E ADG Zeie ADC analog ST control register 0x00 0x00 540F ADC1 RER ADC analog watchdog control register 0x00 contd low 0x00 5410 to 0x00 57FF Reserved area 1008 bytes 38 88 Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Memory and register map
83. tends to give an overview of the basic features of the STM8S903K3 functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accum
84. ter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 46 EMS data Symbol Parameter Conditions Level class Vpp 3 3 V Ta 25 C fMASTER 16 MHz HSI clock 2 B conforming to IEC 1000 4 2 Voltage limits to be applied on any I O pin VFESD to induce a functional disturbance Fast transient voltage burst limits to be Vpp 3 3 V Ta 25 C Verte applied through 100 pF on Vpp and Vss fuasrEn 16 MHz HSI clock 4 A pins to induce a functional disturbance conforming to IEC 1000 4 4 Doc ID 15590 Rev 1 75 88 www bdtic com ST Electrical characteristics STM8S903K3 Electromagnetic interference EMl Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm SAE J 1752 3 which specifies the board and the loading of each pin Table 47 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit General conditions frequency band 16 MHz 16 MHz 8 MHz 16 MHz 0 1MHz to 30 MHz 2 3 Vpp 5 V E Peak level
85. tics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 1000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program coun
86. ulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers Doc ID 15590 Rev 1 11 88 www bdtic com ST Product overview STM8S903K3 4 2 4 3 12 88 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 28 external interrupts on 7 vectors including TLI Trap and reset interrupts Doc ID 15590 Rev 1 ky www bdtic com ST STM8S903K3 Product overview 4 4 Flash program and data EEPROM memory e 8 Kbytes of Flash program single voltage F
87. www bdtic com ST STM8S903K3 Electrical characteristics Figure 37 SPI timing diagram slave mode and CPHA 0 NSS input lt lt ISU NSS gt lt te SCK h NSS CPHA O ft CPOL 0 SCK Input OO 32 it o L 72 o A es 1 T 1 t ta S0 n ee th SO lt gt she Son tdis SO 4 MISO V Leon OUTPUT MSBOUT OUT BIT our Boom sid OUT isu SI gt INPUT E E ths ai14134 Figure 38 SPI timing diagram slave mode and CPHA 1 NSS input A fi SU NSS 4 gt Ia lc SCK i th Nss s CPHA 1 o if Xo X4 X amp CPOL 0 i M x opu w SGKH 4 gt d i D d CPOL 1 El Ic NEN Lei Jos SCK i g t th SO lt gt dis SO e MISO OUTPUT w our wsBour BIT6 OUT Bou OUT me Sl Ss SI INPUT ai14135 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Vpp d Doc ID 15590 Rev 1 69 88 www bdtic com ST Electrical characteristics STM8S903K3 Figure 39 SPI timing diagram master mode SCK Input SCK Input High NSS input i SCK CPHA 0 CPOL 0 f ALL CPHA 0 3 Y CPHA 1 CPOL 0 T CPHA 1 d rit MISO f SCK C FY MoS MSBOUT T i BITI O T aour T OUTUT TLA UT U V MO zap th MO gt ai14136 1 Measurement points are done at CMO
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