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Processor Local Bus Functional Model Toolkit User`s Manual

1. M az Las na Y 2 3 EE 1 pasji ea AA 0000 Y D A1X 0000Y D A3K 0000 0000 ME 0000 Y 0000 X ija NE MA Figure 13 Back to Back Read Write Read Write Set device path plb complex plb masterO device type plb master mem init mem init addr 00000000 data 00010203 addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init addr 0000000c data 0c0d0e0f read addr 00000000 size 0000 be 1111 write addr 00000004 size 0000 be 1111 read addr 00000008 size 0000 be 1111 56 Processor Local Bus Functional Model Toolkit Version 4 3 write addr 0000000c size 0000 be 1111 send level 0 Set device path pib complex pilb slave0 device type plb slave Initialize device 0 mem init addr 00000000 data 00010203 addr 00000004 data 04050607 mem_init addr 00000008 data 08090a0b mem_init addr 0000000c data 0c0d0e0f read_response aack_delay 0 dack_delay 0 mem_init write_response aack_delay 0 dack_delay 0 read_response aack_delay 0 dack_delay 0 write_response aack_delay 0 dack_delay 0 mem_check level 0 addr 00000000 data 00010203 mem_check level 0 addr 00000004 data 04050607 mem_check level 0 addr 00000008 data 08090a0b mem_check level 0 addr 0000000c data 0c0d0e0f Version 4 3 PLB Bus Timing 57 7 7 Four word Line Read Tra
2. As shown in Figure 1 the on chip bus structure provides a link between the processor core and other peripherals which consist of PLB and OPB master and slave devices The processor local bus PLB is the high performance bus used to access memory through the bus interface units The two bus interface units shown above external peripheral controller and memory controller are the PLB slaves The processor core has two PLB master connections one for instruction cache and one for data cache Attached to the PLB is also the direct memory access DMA controller which is a PLB master device used in data intensive applications to improve data transfer performance Lower performance peripherals such as OPB master slave and other internal peripherals are attached to the on chip peripheral bus OPB A bridge is provided between the PLB and OPB to enable data transfer by PLB masters to and from OPB slaves In the above example we have two Version 4 3 PLB Toolkit Overview 1 bridges a PLB to OPB bridge which is a slave on the PLB and a master on the OPB and an OPB to PLB bridge which is a slave on the OPB and a master on the PLB OPB peripherals may also comprise DMA peripherals The device control register DCR bus is used primarily for accessing status and control registers within the various PLB and OPB masters and slaves It is meant to off load the PLB from the lower performance status and control read and write transfers The DCR bus arch
3. 22 Version 4 3 Contents Gommand Modes stat aid dd a A as no Lts ARA 22 Internal Slave Data Memory Structure and Look Up Algorithms 23 Ordered Write Cycles PLB ordered 24 Internal Slave Memory Checking 25 Burst MOdes See OA E ee es BER O A ale Se OE SNE EN 25 Conversion Cycles with Different PLB Device Sizes 25 Pipeline Modes e Bina AN teal O RA eren a Re an Ga 26 PLB Monitor ost ean ieee a4 en he ee ee a 26 Chapter 6 PLB Bus Functional Language 28 BFM Device Configuration Commands 28 Set Device Command ii 28 PEB Allas Commands s nie a a NA MENU UE A WE SE Ban 28 Set Alias Command coco WWW 29 PLB Master Commands in 29 Configure Command o 29 BFL Mode Configuration Parameters 29 Automatic Command Mode Configuration Parameters 29 Automatic Data Mode Configuration Parameters 31 Mein nt O Command eo rr Da eee had Dee RENA Ra Da 31 Reg_Init Command sie AA eke te ama eee bbe adda ee ee ee ee 32 Read and Write Bus Cycle Commands 32 Mem Update Command ii 34 Reg Update Command inn 34 Send Command si si
4. 7 4 Back to Back Read Transfers Figure 11 shows the operation of several back to back single read transfers on the PLB Cycle SYS_pIbCik Transfer Qualifiers Mn_request Mn_priority 0 1 Mn_busLock Mn_RNW Mn BE 0 3 Mn size 0 3 Mn type 0 2 Mn abort Mn_ABus 0 31 PLB PAValid SI wait SI AddrAck Write Data Bus Mn wrDBus 0 31 SI wrDAck SI wrComp Mn wrBurst Read Data Bus SI rdDBus 0 31 SI rdWdAddr 0 3 SI rdDAck Si rdComp Mn rdBurst l EEES naanmanaaan Ber cw TS TE ZNE NE Kv ia va aX va aX Ta ay 0000 A D ATA D A2 DIA3 DAA 0000 0000 E oo i i i NA i i i Figure 11 Back to Back Read Transfers set device path plb complex plb master0 device type plb master mem init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init addr 0000000c data 0c0d0e0f read addr 00000000 size 0000 be 1111 read addr 00000004 size 0000 be 1111 read addr 00000008 size 0000 be 1111 read addr 0000000c size 0000 be 1111 52 Processor Local Bus Functional Model Toolkit Version 4 3 send level 0 set device path plb_complex plb_slave0 device_type plb_slave Initialize device 0 mem_init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init ad
5. Error 2 32 3 An error message is issued when PLB wrBurst is re asserted before the last Sin wrDAck of a burst transfer is received Error 2 32 4 An error message is issued when PLB_wrBurst is active the cycle after SIn_wrBTerm e Error 2 32 5 An error message is issued when PLB wrBurst is active and SYS_plbReset is active Error 2 32 6 An error message is issued when PLB_wrBurst is active during a non burst write cycle Error 2 32 7 An error message is issued when the PLB changes this transfer qualifier from when a primary request to transfer is made until the addressed slave asserts its Sln_addrAck or the transfer is terminated via Mn_abort or PLB_MnRearbitrate or Timeout 8 7 31 PLB rdPrim The following error messages are issued for this signal Error 2 33 1 An error message is issued if this signal is asserted without the last read cycle Sln_AddrAck being a secondary acknowledge with PLB_SAValid 8 7 32 PLB_wrPrim The following error messages are issued for this signal e Error 2 34 1 An error message is issued if this signal is asserted without SIn wrComp e Error 2 34 2 An error message is issued if this signal is asserted without a secondary pipelined write transaction acknowledged 8 7 33 PLB Abort The following error messages are issued for this signal e Error 2 35 1 Version 4 3 PLB Compliance Checks 85 An error message is issued if this transfer qualifier does not match Mn_Abort when PLB MnAdarAck
6. Read Transfers set device path plb complex plb master0 device type plb master mem init addr 00000000 data 00010203 read addr 00000000 size 0000 be 1111 48 Processor Local Bus Functional Model Toolkit Version 4 3 send level 0 set device path plb complex plb slave0 device type plb slave mem init addr 00000000 data 00010203 read response aack delay 3 dack delay 1 mem_check level 0 addr 00000000 data 00010203 Version 4 3 Initialize device O PLB Bus Timing 49 7 2 Write Transfers Figure 9 shows the operation of a single write data transfer on the PLB Cycle cma any a es a a ee sys pick LEL LILI LILI Li Transfer Qualifiers Mn_request Mn priority 0 1 Mn busLock Mn RNW Mn BE 0 3 Mn size 0 3 Mn type 0 2 Mn abort Mn ABus 0 31 Iyo PLB PAvalid i i Next Rd Avalid Ne Wr Avalid Sl wait a ee ee SI AddrAck Write Data Bus Mn wrDBus 0 31 Y DAO SI wrDAck SI wrComp Mn wrBurst Read Data Bus SI rdDBus 0 31 i i 0000 SI_rdWdAdar 0 3 i i i i 0000 SI rdDAck SI rdComp Mn rdBurst Figure 9 Write Transfers set device path plb complex plb master0 device type plb master mem init addr 00000000 data 00010203 write addr 00000000 size 0000 be 1111 send level 0 set device path plb_complex plb_slave0
7. The following error messages are issued for this signal e Error 1 13 1 A warning message is issued if Mn_abort is asserted without a Mn_Request 8 6 12 Mn_wrDBus 0 PLB DATA BUS WIDTH The following error messages are issued for this signal e Error 1 14 1 An error message is issued when a master changes this transfer qualifier from when a write request to transfer is made until the addressed slave asserts its Sln_addrAck or the transfer is terminated via Mn_abort PLB_MnRearbitrate or Mn_Timeout Error 1 14 2 Version 4 3 PLB Compliance Checks 71 An error message is issued when the first word of data on Mn_wrDBus does not remain constant from the assertion of PLB MnaddrAck to the first PLB MnWrDAck in the case when wrDAck is delayed This check is also performed on words following the first of multi word transfers in which case the word of data on Mn_wrDBus must remain constant from PLB_MnWrDAck through the next PLB MnWrDAck Error 1 14 3 An warning message is issued when a master changes this transfer qualifier from when a read reguest to transfer is made until the addressed slave asserts its Sln addrAck or the transfer is terminated via Mn abort or PLB MnRearbitrate Error 1 14 4 An error message is issued if the Mn wrDbus is not properly mirrored as indicated in the architecture specification for smaller masters connected to larger width PLB Arbiters 8 6 13 Mn rdBurst The following error messages are iss
8. The following is an example of how to specify a 32 bit single read transaction read addr 00001000 size 0000 be 1111 Command mode is the default mode for the master model and the user is not required to specify a BFL configuration parameter for this mode Auto Mode This mode enables PLB read write bus cycles to be generated automatically without the need for read write master commands in the bfl In this mode the PLB master model will generate PLB cycles automatically based on an internal random number generator and pre programmed minimum and maximum delays of the available parameters The random number generator selects a new delay value between the minimum and maximum using a uniform distribution function The minimum and maximum range may be initialized by the user through a configuration command The PLB master model will use auto mode when a configuration command enables it such as configure master_auto_mode true 5 2 5 Burst Operations The PLB master model supports the PLB burst protocol The model accesses the internal master memory during the initial bus request and also during each data phases of the burst transfer The PLB master model terminates a burst transfer when the user specified number of data transfers has occurred or when a slave terminates the burst transfer with a burst terminate signal The PLB master model supports a burst_continue_mode where the PLB master will request the bus again if a slave terminate sign
9. instructions It provides a mechanism for testing and branching The bits of the Condition Register are grouped into eight 4 bit fields named CR Field 0 CRO CR Field 7 CR7 Instructions are provided to perform logical operations on individual CR bits and to test individual CR bits The bits of the CR fields are interpreted as follows bit 0 Negative LT The result is negative bit 1 Positive GT The result is positive bit 2 Zero EQ The result is zero bit 3 undefined The synchronization register latches the Synch_in input It can subsequently be referenced or reset using an ALU or move instruction 5 28 ALU Instructions The following instructions are available for arithmetic operations a detailed description is provided in PLB Master Commands on page 29 Add Sub And Or Shift_Left Shift_Right Compare Version 4 3 PLB Bus Models 19 5 2 9 Branch Instructions The PLB master model contains a branch instruction so that users can implement loops and forward jumps The branch instruction uses the condition register to determine whether a jump is taken Any one of the Condition Register Fields CRO CR7 may be used in a branch instruction Branching between devices is not supported 20 Processor Local Bus Functional Model Toolkit Version 4 3 5 3 PLB Slave Model PLB slaves respond to cycles based on requests generated from the PLB core and they maintain an internal m
10. is complete last rddack received or rdbterm asserted Error 2 17 6 An error message is issued when this signal is asserted before the last rddack of the transaction is received 8 7 18 Sin rdBTerm The following error messages are issued for this signal 80 Processor Local Bus Functional Model Toolkit Version 4 3 Error 2 18 1 An error message is issued if SIn_rdBTerm is active outside of allowed window that is from the cycle after slave asserts its Sln addrAck or arbiter asserts rdprim to the cycle it asserts its Sin rdComp Note 2 18 2 An note message is issued if Sin rdBTerm is not asserted for a fixed length burst transfer or the last SI rdDAck was not asserted with the SI rdBTerm Warning 2 18 3 A warning message is issued if SIn rdBTerm is not asserted for a guarded burst transfer which crosses a 1k address boundary 8 7 19 Sin MBusy 0 15 The following errors are issued to this signal Error 2 19 1 An error message is issued when a slave does not assert and hold active the corresponding bit of its Sin MBusy bus from the time the slave asserts it SIn_addrAck until the read transfer is complete Error 2 19 2 An error message is issued when a slave does not assert and hold active the corresponding bit of its Sin MBusy bus from the time the slave asserts it Sin addrAck until the write transfer is complete 8 7 20 Sin Mrd wrErr 0 15 The following error messages are issued for this signal Error 2
11. 2 7 1 An error message is issued when the PLB changes this transfer qualifier from the time when a request to transfer is made until the addressed slave asserts its Sln addrAck or the transfer is terminated through Mn abort PLB MnRearbitrate or PLB MnTimeout Error 2 7 2 An error message is issued when the PLB is locked Mn busLock Mn Reguest and PLB MnaddrAck were sampled active and PLB masterID does not equal the locked master s id Error 2 7 3 An error message is issued if in the cycle following a rearbitrate with PLB busLock inactive PLB PAValid is active and the current PLB masteriD is the same as in the previous cycle when rearbitrate was asserted 8 7 8 PLB rd wrpendPri 0 1 There are currently no protocol checks for this signal Version 4 3 PLB Compliance Checks 77 8 7 9 PLB regPri 0 1 The following error messages are issued for this signal e Error 2 9 2 An error message is issued when this bus does not equal the Mn priority winner of primary and secondary reguests when PLB MnAddrAck is asserted 8 7 10 PLB wrDBus The following error messages are issued for this signal e 2101 An error message is issued when the PLB wrDBus does not remain constant from the slaves assertion of SIn addrAck to Sin wrDAck and also between Sin wrDAck assertions in multi data transfers e 2 10 2 An error message is issued when the PLB changes the write data bus from the time when a primary request to transfer is made unt
12. PLB slave design under test connect the PLB signals in the test bench to the new device and remove a PLB slave model instantiation Ensure that the PLB slave address map has non overlapping slave address space The PLB slave model instantiation generics parameters have a default slave address mapping as follows Device 0 00000000 0003FFFF Device 1 00040000 0007FFFF Device 2 00080000 000BFFFF Device 3 000C0000 000FFFFF The PLB slave model has parameters for the address decode in the HDL file These may be updated by the user to re program the default slave address space for a single PLB slave instantiation When multiple slave models are connected to a single PLB core the user must ensure that the slave decode maps are mutually exclusive within a test bench This can be accomplished through the BFL configure command generic statements in the VHDL instantiations or Verilog parameters in the model HDL files 3 3 Instantiating PLB Master Designs Under Test When instantiating a PLB master design under test connect the master to the PLB master interface of the PLB core arbiter Each master will have an independent PLB interface as defined in the PLB architecture specification Each toolkit model uses intercommunication signals called Synch in 0 to 31 and Synch_out 0 to 31 to synchronize events in the test environment The Synch_in 0 to 31 is the logical OR of all the Synch out outputs of each instantiated models in the simulation environment w
13. See ok een Stee CSE ee oe Saje 78 Sine WIDACK a testes tote Rn aan bo ga tented dee eens ite nce es gate eu ote Se 78 SINE WIGOMP ie ee th ee ede dena eee RR ae ae dad JE ed as 79 SIEM we AS Be Rep op A NE Gian Sean aa ara 79 SIMO D BUS ei E A MIB a e a A E AE e da o GIN 79 SinzrdWdAdar 013 ah nia abaratar e ath Ina 79 Sine rdDACK data Z eti Bea Sa dana ARA DAA de pl oe 80 SINE TAC OMP tacts ote tats ote Sectoid An Oa wale iaa ei 80 SIA rd TEN Aye o Nee IE Ene de te di 80 Sli MBUSYy OH9 4 2 2 2 ia cade eed e aban doa Mae et aje 81 Sin Mrd WrErr 0115 25 Ses eee ee aed A Ey ae ea eee eee A 81 PRB RNW so cdse cies eo di te ein Ged A di he welt ko E 81 PEB BES a dea O 82 REBESIZO O JANA NAN LAGE ne O NA LA is A A A A 82 PEB pE cit A es BO a SRN odi dod ie kN 83 PLB TAttribute osos aras a SE ta hele dt ta tara ale pl e 83 PLBEOCK EPs sario tad to e ceded te SAS a act 83 PEBABUS PLBLUADUS 3 do dedo Nea 83 PLEB DUSLOCK S12 806 A A E ah PD oje PE 84 PEB ABUSI O ita Mol cd dt ne ACA UI an Ne ald dt 84 PLB lt WIBurSt uso o ddr da Ba he eae 85 PEB TAM aa ta an tas A a di 85 REB WrP1IMe23200 000tLocmis hee do ALO Dd as a EA 85 REBSADO Ee ee a o o a Tio 85 RUB lt STADBUS EN E a A a oe OAR Pa aa 86 Time Out Handshake Checks For 3 x PLB 86 PEB MAWrBTEerMY ias arma a a at a Sire k 86 PEBo2MARdaB Er ena a a da de aa IIs 86 PEB MNE ei nana EA SAMA BA A a AN SS 86 Index na ni NN 87 viii Pro
14. can be programmed to a different number of beats than that specified on the byte enables When the BURST_COUNT parameter is less than the BE data beat count the burst signal will be pre maturely de asserted When the BURST_COUNT is greater than the BE data beat count the master will continue bursting IF a slave burst terminate signal was not asserted to the master IT IS STRONGLY RECOMMENDED THAT LOGIC DESIGNS WHICH SUPPORT BURST AND FIXED LENGTH BURST BE TESTED THOROUGHLY WITH ALL COMBINATIONS OF BYTE ENABLES MASTER BURST ABORTS AND SLAVE BURST TERMINATES TO MAXIMIZE CORE COMPATIBILITY AND COMPLIANCE burst deassert delay integer Version 4 3 PLB Bus Functional Language 33 This parameter specifies the wait period for number of clocks before de asserting the burst signal When this parameter is used instead of the burst count parameter the PLB master model asserts its M_wr rdBurst signal and deasserts it after the number of clocks have been specified by this parameter The master model waits for a final data acknowledge with its burst signal low and continues to the next instruction When this parameter is used together with the burst_count parameter the master will wait the specified number of clocks after the next to last rd wrDAck is sampled active to deassert the Mn_rd wrBurst signal abort delay integer This parameter specifies the number of clocks to wait before Mn_abort is asserted with respect to the assertion of
15. defined in the PLB architecture The memory array is declared as a linear array of 64 bit address control and 128 bit data for each array entry PLB_Master_Addr_Array 0 to 63 bits O to 61 address field bit 62 dirty bit bit 63 valid bit PLB_Master_Data_Array 0 to 127 4 word data field The valid bit is set during model initialization for each memory entry used and when a memory entry is allocated in the case of a read memory access miss When a read command reloads a memory entry with bus data the dirty bit is set This may be used with test environments to check if bus commands have executed and caused a master memory update in addition to data miscompares The default size of the master memory array is 64k bytes This may be increased or decreased by updating the PLB_Master_Mem_Size in the declaration HDL file of the toolkit 5 2 4 Command Modes This section discusses the possible modes that are available for a PLB master device PLB masters may be configured to act in either Command mode or Auto mode A description of these modes are Command Mode Version 4 3 PLB Bus Models 17 This mode enables the user to generate PLB read write bus transactions and perform other operations using commands which are decoded and executed from within the PLB master model These commands are parsed by the BFC loaded into the PLB master model at simulation time 0 and decoded from an internal command array after PLB reset is de asserted
16. device_type plb_slave Initialize device 0 mem_init addr 00000000 data 00010203 write_response aack_delay 3 dack_delay 3 mem_check level 0 addr 00000000 data 00010203 50 Processor Local Bus Functional Model Toolkit Version 4 3 7 3 Transfer Abort Figure 10 shows a transfer aborted by the master in the same clock cycle the request was being acknowledged by the slave Cycle 0 alp 9 SYS plbCik Transfer Qualifiers Mn_request Mn priority 0 1 Mn busLock 1 Mn RNW Mn BE 0 3 Mn size 0 3 Mn type 0 2 Mn abort Mn ABus 0 31 PLB PAValid SI wait SI AddrAck Write Data Bus La i 4 Next Wr Rd Avalid Mn_wrDBus 0 31 SI_wrDAck SiwComp _ _ Mn_wrBurst Read Data Bus SI rdDBus 0 31 SI rdWdAdar 0 3 SI rdDAck SI rdComp Mn rdBurst set device path plb complex plb master0 device type plb master mem init addr 00000000 data 00010203 write addr 00000000 size 0000 be 1111 abort 3 send level 0 Figure 10 Transfer Abort set device path plb complex plb slave0 device type pib slave mem init addr 00000000 data 00010203 write response aack delay 3 dack delay 0 mem_check level 0 addr 00000000 data 00010203 Version 4 3 Initialize device O PLB Bus Timing 51
17. or information about IBM products machines and programs programming or services that are not announced in your country Such references or information must not be construed to mean that IBM intends to announce such IBM products programming or services in your country Any reference to an IBM licensed program in this publication is not intended to state or imply that you can use only IBM s licensed program You can use any functionally equivalent program instead No part of this publication may be reproduced or distributed in any form or by any means or stored in a data base or retrieval system without the written permission of IBM Requests for copies of this publication and for technical information about IBM products should be made to your IBM Authorized Dealer or your IBM Marketing Representative Address comments about this publication to IBM Corporation Department YM5A P O Box 12195 Research Triangle Park NC 27709 IBM may use or distribute whatever information you supply in any way it believes appropriate without incurring any obligation to you O Copyright International Business Machines Corporation 1996 2000 All rights reserved 4321 Notice to U S Government Users Documentation Related to Restricted Rights Use duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corporation Patents and Trademarks IBM may have patents or pending patent applications coverin
18. within the toolkit 5 3 5 Ordered Write Cycles PLB_ordered When the slave model acknowledges a write cycle when PLB TAttribute 8 signal is active the PLB slave model will delay all subsequent internal data accesses until the previous write cycle is internally complete The PLB slave model however may acknowledge additional cycles assert SI addrAck during ordered writes 24 Processor Local Bus Functional Model Toolkit Version 4 3 5 3 6 Internal Slave Memory Checking Mem_check slave commands allow automatic slave data memory lookup and compares without performing PLB bus operations Error messages will be generated when data miscompares occur with the mem check commands When the slave is programmed with mem check commands it waits to receive a synchronization signal and then performs the data memory lookup The order in which the mem check commands appear in a BFL file are independent of the slave read response write response and mem init commands Slave check addr array 0 to 31 bits Oto 29 address bits 30 31 are unused Slave check data array 0 to 31 4 byte data field The default size of the slave check memory array is also 128 entries This may be increased or decreased by updating the slave check array size in the declaration HDL file of the toolkit 5 3 7 Burst Modes The PLB slave model supports the PLB burst protocol The model accesses the internal slave memory during the initial bus reguest and also dur
19. 0c0d0e0f read_response aack_delay 0 dack_delay 0 rdword_mode 1 mem_check level 0 addr 00000000 data 00010203 mem_check level 0 addr 00000004 data 04050607 mem_check level 0 addr 00000008 data 08090a0b mem_check level 0 addr 0000000c data 0c0d0e0f Version 4 3 PLB Bus Timing 59 7 8 Four word Line Write Transfers Figure 15 shows the operation of a single four word line write to a slave device which is capable of latching data every clock cycle from the PLB Cycle OA A AA AS SYS pibCik NENA Transfer Qualifiers Mn_request Mn priority 0 1 Mn busLock Mn RNW Mn_BE 0 3 Mn_size 0 3 Mn type 0 2 Mn abort Mn_ABus 0 31 PLB PAValid SI AddrAck SI wait Write Data Bus E Mn_wrDBus 0 31 SI wrDAck SI wrComp Mn wrBurst i Read Data Bus V poor XL 900 ma Mao Y ext Rd Avalid Next Wr Avalid Next Rd AddrAck t Wr AddrAck SI rdDBus 0 31 SI_rdWdAddr 0 3 0000 Si rdDAck SI_rdComp Mn_rdBurst Figure 15 Four Word Line Write set device path plb complex plb master0 device type plb master mem init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init addr lt 0000000c data 0c0d0e0f write addr lt 00000000 size 0001 be 1111 send level 0 60 Processor Local Bus Functional Model Toolkit Version 4 3 set device path plb_complex plb_sl
20. 2 bit master addr HI x 32 bit These parameters are used in master_auto_mode and they override the default generic address parameters for the PLB master models The user may provide up to two non contiguous address ranges for the same master by changing the x from Oto 1 reg delay min max integer default 0 20 These parameters specify the range for reg delay when master auto mode is true The model automatically assigns a random value to the reg delay between and including the minimum and maximum values abort_probability integer default 5 This parameter specifies the probability that M_abort will be asserted when master auto mode is true For example the probability that M abort will be asserted is approximately 1 out of every 5 default value master reguests when master auto mode is enabled abort delay min max integer default 0 17 These parameters specify the range for abort delay when master auto mode is true The model automatically assigns a random value to the abort delay between and including the minimum and maximum values This parameter is generated for approximately 1 out of every abort probability cycles when master auto mode is enabled lock probability integer default 5 This parameter specifies the probability that M busLock will be asserted when master auto mode is true For example the probability that M busLock will be asserted is approximately 1 out of every 5 default value maste
21. 20 1 An error message is issued when a slave asserts its SI Mrd wrErr signal to master n without the corresponding SI MBusy SI Mrddack or SI Mwrdack signal asserted 8 7 21 PLB RNW The following error messages are issued for this signal Error 2 21 1 An error message is issued when the PLB changes this transfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated through Mn abort or PLB MnRearbitrate or timeout Error 2 21 2 An error message is issued if this transfer gualifier does not match Mn RNW of the reguesting master when PLB MnAddrAck is active Version 4 3 PLB Compliance Checks 81 8 7 22 PLB_BE The following error messages are issued for this signal Error 2 22 1 An error message is issued when the PLB changes this transfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated via Mn_abort or PLB MnRearbitrate or timeout Error 2 22 2 An error message is issued if this transfer qualifier has no enabled bytes all zeroes for a non line non burst transfer Error 2 22 3 An error message is issued if the replication of the byte enables is not correct when a device is connected to a PLB of a larger size 8 7 23 PLB_size 0 3 The following error messages are issued for this signal 82 Error 2 23 1 An error message is issued when the PLB cha
22. 3x vhd plb_slave3x v This HDL file is a compatibility mode wrapper for the PLB slave component which is instantiated in this file Users should instantiate this entity in test fixtures which include the PLB model toolkit slave model being used with 3 x PLB Architecture arbiter designs plb monitor3x vhd plb monitor3x v This HDL file is a compatibility mode wrapper for the PLB monitor component which is instantiated in this file Users should instantiate this entity in test fixtures which include the PLB model toolkit monitor model being used with 3 x PLB Architecture arbiter designs It is recommended that all simulations use the PLB monitor to ensure PLB compliance plb complex vhd plb complex v This HDL file is the PLB test bench Designs under test may be instantiated in the test bench and simulated with the PLB behavioral models Version 4 3 PLB Toolkit Environment 7 Chapter 3 PLB Toolkit Test Bench Figure 3 shows the default configuration of the PLB toolkit test bench environment It contains instantiations of a PLB master model PLB slave model PLB core and a PLB monitor model It also contains the distributed multiplexers and logic to implement the PLB bus using AND OR HDL statements Note Default configuration instantiates four masters and four slaves The current PLB implementation supports up to eight masters Designs under test may be instantiated in the toolkit test bench HDL which replace the default configura
23. 6 3 11 Compare Command The compare command enables the user to compare two values and store the results in the condition register Each compare instruction executes in one PLB clock cycle SRC two are required This parameter specifies the internal register value to be used as a source of the compare instruction Each compare instruction requires two SRC parameters Valid values are SR RO 31 DST This parameter specifies the condition register destination of the compare instruction Valid values are CRO 7 Example compare RO R1 CR1 36 Processor Local Bus Functional Model Toolkit Version 4 3 6 3 12 Add Command The add command updates an internal master register with the result of an addition between an internal register and an immediate value Each add command executes in one PLB clock cycle DST hex value up to 4 bytes These two parameters specify the 32 bit internal destination register to be updated and the immediate hexadecimal value to be added to the destination register The DST must be RO 31 SR or CR Example add R0 01 6 3 13 Sub Command The sub command updates an internal master register with the result of a subtraction between an internal register and an immediate value Each sub command executes in one PLB clock cycle DST hex value up to 4 bytes These two parameters specify the 32 bit internal destination register to be updated and the immediate hexadecimal value to be subtract
24. 6 3 4 Read and Write Bus Cycle Commands The read write bus cycle commands initiate read or write cycles on the PLB bus by causing the bus master to assert the M reguest signal These commands are executed sequentially therefore the completion of the cycles on the PLB bus influence the simulation time at which the commands are decoded The following is a list of possible read write parameters e addr 4 8 byte This parameter specifies the 32 bit or 64 bit address e BE 4 8 16 bit This parameter specifies the Mn_BE byte enable signals of the PLB The valid byte enable combinations are listed in the PLB architecture specifications under transfer qualifier signals This parameter is required for all nonburst and non line transfers size 4 bit This parameter specifies the Mn_size signals of the PLB The valid size combinations are listed in the PLB architecture specifications under transfer qualifier signals Msize 2 bit This parameter specifies the Mn_MSize signals of the PLB The valid size combinations are listed in the PLB architecture specifications under transfer qualifier signals Note that this parameter will be ignored if MSize was previously defined as a configuration parameter e reg delay integer This parameter specifies the number of clock cycles for the master to wait before it asserts its M_request signal for the corresponding read or write cycle e lock 1 bit default 0 This para
25. Ana E Ban NE A EN EN ea Ba 35 Waitr Gommand cartare cara ropas Se ane ane baddies ble AeA ah 35 Branch Command er heed aes tan AE hee eee EN ale NG 35 Move Command va z said AN RA E ERA KEKE SDN thew RE 36 Compare Command Lc 36 Add Command io ba heed dew eee bea ma eee bebas eee eden 37 Sub COMMANG iii a aa eo ee ee Ee aw A ba ar dae 37 AND Command iee don nan book ena ee cee ad Manan naa 37 OR COMMAND A eee wi a SAE a a Meee 37 Shift left Command sitni a naa a aaa A EN ede OES ey leli 38 Shift right Command ii 38 PLB Slave Gommand viii ss hn ba A ES 38 Configure Command LLLL eee 38 BFL Mode Configuration Parameters 38 Automatic Command Mode Configuration Parameters 40 Automatic Data Mode Configuration Parameters 41 Mein nt Command Maceo e A A A a a 42 Read Response Write Response Commands 42 Mem Check Command ii 43 PLB Monitor Commands a e aA E ee ee eee ee eee eee 44 Configure Command ii 44 Configuration Parameters 44 vi Processor Local Bus Functional Model Toolkit Version 4 3 Read Write Commands tees 45 Sample Monitor Read Write BFL 46 Chapter 7 PLB Bus Timing ccoo bros
26. B secondary to primary read reguest indicator PLB regPri 0 1 Arbiter PLB current reguest priority PLB RNW Arbiter PLB read not write PLB size 0 3 Arbiter PLB transfer size PLB type 0 2 Arbiter PLB transfer type PLB wrBurst Arbiter PLB burst write transfer indicator PLB wrPrim Arbiter PLB secondary to primary write reguest indicator SI addrAck Slave Slave address acknowledge SI_MBusy 0 3 Slave Slave busy indicator SI rdBTerm Slave terminate read burst transfer SI rdComp Slave read transfer complete indicator SI rdDAck Slave read data acknowledge SI rdWdaAddr 0 3 Slave read word address SI rearbitrate Slave rearbitrate bus indicator SI wait Slave wait indicator SI wrComp Slave Slave write transfer complete indicator 79 SI wrDAck Slave Slave write data acknowledge 78 Processor Local Bus Functional Model Toolkit Version 4 3 Table 1 Summary of PLB Signals Continued Signal Name Source Synch out Description Page 8 6 Master Interface Checks This section describes the PLB master interface checks performed during simulation 8 6 1 Mn reguest The following error messages are issued for this signal Error 1 1 1 An error message is issued when a master deasserts its Mn reguest without any of the following events that is if any one of the following events occur then no error is flagged PLB MnAddrAck is asserted Mn abort is asserted PLB MnRearbitrate is asserted MnTimeout is ass
27. B slave model operation section discusses the slave bus commands and modes internal slave data memory structure and look up algorithms ordered write cycles PLB_ordered internal slave memory checking burst modes conversion cycles with different PLB device sizes and pipeline modes 5 3 2 Slave Bus Commands and Modes The PLB slave model responds to PLB memory cycles PLB_type 000 when there is a valid request on the PLB bus and the PLB address is within the PLB slave s configured address space Separate read_response and write_ response commands allow programmable overlapped read and write data phases The slave model stores the read and write response parameters in separate command arrays which allows independent and parallel control of the data buses Although address phases occur sequentially it is possible for a slave to perform out of order memory access relative to the address phases depending on how the master cycles are generated and how the slave model is programmed to respond to the bus cycles The PLB slave model memory uses the SI rdDAck and SI wrDAck signals to perform internal memory accesses needed to satisfy PLB read and write bus cycle reguesis In the PLB slave model memory access for reads always occurs one clock before the SI rdDAck assertion and the memory access for writes always occurs in the clock that SI wrDAck is asserted Also writes have precedence in the memory access logic of the PLB slave memory model If SI r
28. Configuration Parameters master auto data boolean default false This parameter specifies whether the PLB master behavior should automatically generate data When the master model is configured for automatic data mode there is no need to initialize internal memory data since it is generated and checked using the BFM data generation function described in PLB Bus Functional Compiler on page 11 data seed integer default 1 This parameter specifies the seed to be used for the auto data feature of the model The slave model forms a seed using this root_seed and the byte address The user may change the initial seed to meet the random number sequences which are generated which in turn will produce various slave data 6 3 2 Mem Init Command The mem init command initializes the internal master memory and is only executed at simulation time addr 4 byte This parameter specifies a master 32 bit address for data array initialization data 4 byte This parameter specifies the master memory data to initialize in the corresponding PLB device Example mem init addr 00001000 data 01020304 Version 4 3 PLB Bus Functional Language 31 6 3 3 Reg Init Command The reg_init command initializes an internal master register and is only executed at simulation time 0 DST z 4 byte This parameter specifies the master 32 bit register to initialize DST may be CR SR or RO 31 Example reg init R0 01020304
29. DR LO 0 4 byte SLAVE1 ADDR HI O 4 byte SLAVE1 ADDR LO 1 4 byte SLAVE1 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 1 SLAVE2 ADDR LO 0 4 byte SLAVE2 ADDR HI O 4 byte SLAVE2 ADDR LO 1 4 byte SLAVE2 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 2 lt SLAVE3 ADDR LO 0 4 byte SLAVE3 ADDR HI O 4 byte SLAVE3 ADDR LO 1 4 byte SLAVE3 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 3 SLAVE4 ADDR LO 0 4 byte SLAVE4 ADDR HI O 4 byte SLAVE4 ADDR LO 1 4 byte SLAVE4 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 4 SLAVE5 ADDR LO 0 4 byte SLAVE5 ADDR HI 0 4 byte SLAVE5 ADDR LO 1 4 byte SLAVE5 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 5 44 Processor Local Bus Functional Model Toolkit Version 4 3 SLAVE6 ADDR LO 0 4 byte SLAVE6_ADDR_HI_0 4 byte SLAVE6_ADDR_LO_1 4 byte SLAVE6 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 6 SLAVE7 ADDR LO 0 4 byte SLAVE7 ADDR HI O 4 byte SLAVE7 ADDR LO 1 4 byte SLAVE7 ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 7 Example set device path plb complex mon device type plb monitor configure SLAVEO ADDR LO 0 00000000 slave O range configure SLAVEO ADDR HI 0 0003FFFF configure SLAVEO ADDR LO 1 FFFF0000 slave 0 range hi SLAVEO ADDR HI 1 FFFFF
30. Err PLB_MnWrDAck PLB_MnWrBTerm PLB MnRdDBus 0 31 gt PLB MnRdWdAddr 0 3 PLB MnRdDAck gt PLB MnRdBterm PLB PAValid PLB SAValid PLB rdPrim PB wPim PLB busLock PLB RNW PLB BE 0 3 PLB size 0 3 PLB type 0 2 PLB compress PLB guarded PLB ordered Pr PLB lockError PLB ABus 0 31 PLB abort e PLB wrDBus 0 31 PLB wrBurst PLB rdBurst PLB pendReg PLB_reqPri 0 1 PLB pendPri 0 1 PLB masteriD 0 3 vv i y v il yy PLB SladdrAck PLB SiRearbitrate PLB SlwrComp PLB SiWait PLB SiwrDAck PLB SlrdComp PLB_SIrdDAck SI wait AA s Sl rdComp SI rearbitrate Sl addrAck SI rdDAck SI rdBTerm SI rdDBus 0 31 ll SI rdWdAddr 0 3 A SI_wrDAck 4 Sl_wrBTerm SI wrComp SI MBusy AA SI_MErr Figure 7 PLB Monitor Interface Version 4 3 PLB Monitor Interface From 1 to x sets of these master to PLB signals From 1 to x sets of these PLB to master signals PLB signals Or ed slave outputs to PLB core From 1 to y of these slave to PLB signals PLB Bus Models 27 Chapter 6 PLB Bus Functional Language The bus functional models in the PLB model toolkit can be controlled through command files which contain information on how to in
31. FFF SLAVE1 ADDR LO 0 00040000 slave 1 range ebiu configure SLAVE1 ADDR HI 0 0007FFFF configure SLAVE2 ADDR LO 0 00080000 configure SLAVE2 ADDR HI 0 000BFFFF configure SLAVE3 ADDR LO 0 000C0000 slave 3 range configure SLAVE3 ADDR HI 0 000FFFFF ssize 2 bit configure configure slave 2 range msize 2 bit 6 5 2 Read Write Commands The following set of parameters can be used to create expect values for transactions that occur on the bus If a value is specified but mismatches when checked against the actual transaction that occurred on the bus then the monitor will generate an error message addr 4 8 byte Specifies the expected address value for a bus transaction be 4 8 16 bit Specifies the expected byte enable value for a bus transaction size 4 bit Specifies the expected size value for a bus transaction aack_delay integer Specifies the expected aack_delay value for a bus transaction abort_delay integer Specifies the expected abort_delay value for a bus transaction dack_delay integer Version 4 3 PLB Bus Functional Language 45 Specifies the expected dack_delay for a bus transaction 6 5 2 1 Sample Monitor Read Write BFL The following example shows bfl for a master slave and monitor device The master will perform four writes followed by four reads The slave will respond to each with the specified aack and dack delays The mon
32. Mn_Compress signal for the duration of the master request phase guarded 1 bit default 0 This parameter enables the assertion of the Mn_Guarded signal for the duration of the master request phase ordered 1 bit default 0 This parameter enables the assertion of the Mn_Ordered signal for the duration of the master request phase e lockErr 1 bit default 0 This parameter enables the assertion of the Mn_lockErr signal or the duration of the master request phase burst count integer This parameter specifies the total number of data transfers when a burst cycle is used with the size parameter The master will continue to execute cycles until an internal transfer counter equals the burst_count parameter Note that this parameter is only used when a burst cycle is specified with the size parameter For a burst of one data transfer the rd wr_burst signals will not be asserted and the burst_count parameter should be set to 1 or simply omitted from the command Note For fixed length bursts the PLB Architecture allows the pre mature de assertion of the M_rd wrburst signal before the number of data beat transfers specified by the byte enables The PLB Architecture also allows Masters to continue bursting beyond the fixed length burst beat count if a slave burst terminate signal is NOT received during a fixed length burst transfer To allow verification of this architectural flexibility the BURST COUNT parameter
33. Mn_request If the parameter is not specified Mn_abort is not asserted If PLB_MAddrAck is sampled active before the abort signal is asserted the data phase is processed as it would be without the abort priority 2 bit default 00 This parameter specifies the Mn_priority signals of the PLB e rdWord mode 1 bit O seguential 1 target word first This parameter specifies the address intermediation order for automatically checking the PLB_Mn_rdWdAdar signals during line transfers The valid modes are sequential and target word first An error message will be generated if a comparison error occurs Example read req_delay 3 addr 00001000 size 0000 be 1111 e data ALU Register When this optional parameter is used data is loaded into the specified PLB master register directly instead of being loaded into the internal PLB master model memory Also no data comparison checking is performed with the data received from the PLB bus 6 3 5 Mem Update Command The mem_update command updates master memory during the decode and execution of master bus commands It is a serializing instruction meaning that all outstanding bus cycles complete before the internal memory array is updated addr 4 byte This parameter specifies the 32 bit address of the internal memory data value to be updated data 4 byte or CRx Rx SR This parameter specifies the data which will be used to update the PLB master internal memory An imme
34. Processor Local Bus Functional Model Toolkit User s Manual Version 4 3 CoreConnect The system on a chip bus standard SA 14 2542 02 First Edition May 2001 This edition of Processor Local Bus Functional Model Toolkit User s Manual applies to the IBM PLB toolkit until otherwise indicated in new versions or application notes The following paragraph does not apply to the United Kingdom or any country where such provisions are inconsistent with local law INTERNATIONAL BUSINESS MACHINES CORPORATION PROVIDES THIS MANUAL AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Some states do not allow disclaimer of express or implied warranties in certain transactions therefore this statement may not apply to you IBM does not warrant that the products in this publication whether individually or as one or more groups will meet your requirements or that the publication or the accompanying product descriptions are error free This publication could contain technical inaccuracies or typographical errors Changes are periodically made to the information herein these changes will be incorporated in new editions of the publication IBM may make improvements and or changes in the product s and or program s described in this publication at any time It is possible that this publication may contain references to
35. R BURST ABORTS AND SLAVE BURST TERMINATES TO MAXIMIZE CORE COMPATIBILITY AND COMPLIANCE 18 Processor Local Bus Functional Model Toolkit Version 4 3 5 2 6 Conversion Cycles with Different PLB Device Sizes The PLB master model can be configured to be a 32 bit 64 bit or 128 bit device When the PLB master model receives a PLB MnSSize with PLB MnAddrAck which represents a slave that is smaller than the configured PLB master size Mn_Msize 0 1 the PLB master will automatically generate additional cycles to complete the original requested transaction These additional cycles can be referred to as conversion cycles For example a 64 bit PLB master will always generate one additional cycle when a 32 bit slave responds to a single transfer M_Size 0000 read or write cycle For line transfers the PLB master completes the request when the appropriate number of words have been transferred as determined by the transaction width MSize SSize and the transfer size M_Size See PLB architecture specifications for details on different device widths 5 2 7 General Purpose and Branch Processor Registers The PLB master model contains 32 general purpose registers RO 31 a 32 bit synchronization register SR and a 32 bit condition register CR These registers can be used by the programmer to implement algorithms or conditions which affect the way in which the PLB master executes commands The condition register is updated during compare
36. Values Continued Mn_size 0 3 Definition Burst Transfer Words Length determined by master Burst Transfer Double words Length determined by master Burst Transfer Quad words Length determined by master Burst Transfer Octal words Length determined by master Reserved 1111 Reserved Error 1 6 3 An error message is issued When master has a double word burst size and Mn MSize indicates a 32 bit master When master has a quad word burst size and Mn MSize indicates a 32 bit master When master has a quad word burst size and Mn_MSize indicates a 64 bit master When master has a octal word burst size and Mn MSize indicates a 32 bit master Master has a octal word burst size and Mn MSize indicates a 64 bit master Master has a octal word burst size and Mn MSize indicates a 128 bit master 8 6 7 Mn type 0 2 The following error messages are issued for this signal e Error 1 7 1 An error message is issued when a master changes this transfer qualifier from when a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated via Mn_abort PLB MnRearbitrate or Mn_Timeout 8 6 8 Mn TAttribute The following error messages are issued for this signal e Error 1 10 1 An error message is issued when a master changes this transfer qualifier from when a request to transfer is made until the addressed slave asserts its Sin addrAck or the tra
37. _device command are used to initialize the specified device Additional set_device commands are used to specify the initialization of other devices e Device Type String The device_type string specifies the type of model being initialized The valid strings for this toolkit are PLB_master PLB_slave or PLB_monitor Any mismatch in the device_type parameter and the model being initialized will cause an initialization error Example set device path plb complex m0 device type plb master 6 2 PLB Alias Commands This section discusses set alias and name value alias commands 28 Processor Local Bus Functional Model Toolkit Version 4 3 6 2 1 Set Alias Command The set_alias is an optional command which sets up an alias to be used for string substitution in the bus functional command parameters The aliases must be set up before they are used Multiple aliases may be set up It is possible to have alias files separate from BFL command files by invoking the BFC with multiple BFL files The syntax for the set_alias command is set_alias target_name string_name When an alias is established the BFC automatically substitutes the string_name for every occurrence of the target_name Example set_alias TARGET_REG 01020304 In this example the BFC automatically replaces every occurrence of the string TARGET_REG with string 01020304 6 3 PLB Master Commands The PLB master command types include configuration bus cy
38. age is issued if atime out occurs and the arbiter fails to assert the corresponding PLB MnErr signal in any read write DAck cycle for non line line or burst transfer requests 86 Processor Local Bus Functional Model Toolkit Version 4 3 Index A about this book xiii address map setup error 64 alu intructions 19 B back to back read transfers 52 back to back read write read write transfers 56 BFM device configuration commands 28 branch intructions 20 branch processor register 19 burst modes 25 burst operations 18 bus functional compiler PLB model toolkit 11 bus functional compiler files 5 bus model toolkits PLB toolkit 1 bus models 13 C command modes 17 22 conversion cycles with different PLB device sizes 19 25 D declarations file access 11 decode unit 16 E example test case file 6 F four word line read followed by four word line write transfers 62 fourword line read transfers 58 fourword line write transfers 60 G general purpose register PLB bus models branch processor register 19 ieee packages 9 initializing bus functional models 12 internal master data memory 17 internal slave data memory structure 23 internal slave memory checking 25 invoking bus functional compiler 12 Version 4 3 master inferface checks 67 master model operation 16 monitor model 64 O operations 22 ordered write cycles 24 P pipeline modes 26 PLB alias commands 28 PLB bus functional compiler declarations fi
39. al is received and the PLB master has more data to transfer To configure the PLB master model for burst_continue_mode use the following configuration statement configure burst_continue_mode true The PLB master model also supports the PLB fixed length burst protocol The master model will automatically de assert the M_rd wrBurst signal when the BE parameter is non zero the size parameter indicates a burst cycle the corresponding number of data transfers takes place Note For fixed length bursts the PLB architecture allows the pre mature de assertion of the M_rd wrburst signal before the number of data beat transfers specified by the byte enables The PLB architecture also allows masters to continue bursting beyond the fixed length burst beat count if a slave burst terminate signal is NOT received during a fixed length burst transfer To allow verification of this architectural flexibility the BURST_COUNT parameter can be programmed to a different number of beats than that specified on the byte enables When the BURST COUNT parameter is less than the BE data beat count the burst signal will be pre maturely de asserted When the BURST COUNT is greater than the BE data beat count the master will continue bursting IF a slave burst terminate signal was not asserted to the master IT IS STRONGLY RECOMMENDED THAT LOGIC DESIGNS WHICH SUPPORT BURST AND FIXED LENGTH BURST BE TESTED THOROUGHLY WITH ALL COMBINATIONS OF BYTE ENABLES MASTE
40. ave0 device_type plb_slave Initialize device 0 mem_init addr 00000000 data 00010203 mem_init addr 00000004 data 04050607 mem_init addr 00000008 data 08090a0b mem_init addr 0000000c data 0c0d0e0f write_response aack_delay 0 dack_delay 0 mem_check level 0 addr 00000000 data 00010203 mem_check level 0 addr 00000004 data 04050607 mem_check level 0 addr 00000008 data 08090a0b mem_check level 0 addr 0000000c data 0c0d0e0f Version 4 3 PLB Bus Timing 61 7 9 Four word Line Read Followed By Four word Line Write Transfers Figure 16 shows the operation of a four word line read followed immediately by a four word line write on the PLB AA AAA AAA SYS_pIbCik Transfer Qualifiers Mn_request Mn_priority 0 1 1 I Mn busLock Mn RNW 7 J Mn_BE 0 3 O wees Mn size 0 3 A door 00 Mn_type o 2 Y ooo 000 Mn abort LA Mn ABus 0 31 me NO PLB_PAValid Next Read AValidA Next Write AValid SI wrComp SI addrAck ij k EASE Write Data Bus w A Dp az Mn wrBurst Mn wrDBus 0 31 A D1 A J SA Read Data Bus SI wrDAck SI rdDBus 0 31 0000 X wo X w1 4 W2 Y w3 0000 SI rdWdAddr 0 3 0000 X 0000 0001 0019X 0011 0000 SI rdDAck AANA SI_rdComp Mn rdBurst Figure 16 Four Word Line Read followed by Four Word Line Write set device path plb complex plb master0 device t
41. ay between and including the minimum and maximum values s write wait min max integer default 12 15 These parameters specify the range for wait delay during write cycles when slave auto mode is true The model automatically assigns a random delay to the wait delay between and including the minimum and maximum values e read DAck min max integer default 0 15 These parameters specify the range for DAck delay during read cycles when slave auto mode is true The model automatically assigns a random delay to the DAck delay between and including the minimum and maximum values write DAck min max integer default 0 15 These parameters specify the range for DAck delay during write cycles when slave auto mode is true The model automatically assigns a random delay to the DAck delay between and including the minimum and maximum values e read comp min max integer default 0 2 These parameters specify the range for comp delay during read cycles when slave auto mode is true The model automatically assigns a random delay to the comp delay between and including the min and max values write comp min max integer default 0 2 These parameters specify the range for comp delay during write cycles when slave auto mode is true The model automatically assigns a random delay to the comp delay between and including the minimum and maximum values read burst term min max z integer default 7 10 These
42. bed in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons The information contained in this document does not affect or change IBM s product specifications or warranties Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties All information contained in this document was obtained in specific environments and is presented as illustration The results obtained in other operating environments may vary THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN AS IS BASIS In no event will IBM be liable for any damages arising directly or indirectly from any use of the information contained in this document IBM Microelectronics Division 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 6531 The IBM home page can be found at http www ibm com The IBM Microelectronics Division home page can be found at http www chips ibm com Document No SA 14 2542 02
43. cessor Local Bus Functional Model Toolkit Version 4 3 Figures Figure 1 Processor Local Bus Interconnection Figure 2 Physical Implementation of the PLB Figure 3 PLB Toolkit Testbench plb complex vhd v Figure 4 PLB Master Interface Figure 5 PLB Master Model Figure 6 PLB Slave Interface Figure 7 PLB Monitor Interface Figure 8 Read Transfers Figure 9 Write Transfers Figure 10 Transfer Abort Figure 11 Back to Back Read Transfers Figure 12 Back to Back Write Transfers Figure 13 Back to Back Read Write Read Write Figure 14 Four Word Line Read Figure 15 Four Word Line Write Figure 16 Four Word Line Read followed by Four Word Line Write Version 4 3 Figures Processor Local Bus Functional Model Toolkit Version 4 3 Tables Table 1 Summary of PLB Signals 65 Table 2 Mn type Values ii 69 Table 3 Mn Size Valles rres sa tan dan obj ah dee bs Swear aden noire bb ble bs we 69 Table 4 PLB type Values Version 4 3 Tables xi xii Processor Local Bus Functional Model Toolkit Version4 3 About This Book This book begins with an overview followed by detailed information on Processor Local Bus Functional Model Toolkit environment testbench bus functional compiler models and language used in simulation The Processor Local Bus Functional Model Toolkit features e Unit and subsystem level simulation of logic designs which comply with PLB a
44. cid coded See bak ee Bore nes 48 FREAGMIFANSTORS fa ict oh A e A A Sap Sg estan Senet EEE NE Na Na 48 Write TransierS osito dia rota nt ete abet aan 50 Transter ADOFrE Wen a a a ta tt a da 51 Back to Back Read Transfers eee teenies 52 Back to Back Write Transfers Wa 54 Back to Back Read Write Read Write Transfers 56 Four word Line Read Transfers 0 0 ccc eee ee tenet eens 58 Four word Line Write Transfers eee eens 60 Four word Line Read Followed By Four word Line Write Transfers 62 Chapter 8 PLB Compliance Checks 64 Monitor Model iia at does he eked Ane each BY ween Se aise 64 Terminology tits A hand dated A Wits wae Baoan ied Satie 64 Address Map Set up Error ii 64 Slave Interface PLB Core OR Logic Error 64 Signal Summary Table ion 65 Master Interface Checks Wa 67 Min request Hn a aa a ata bi RA BN ee na 67 MM priority ON ne or bee em bahkan shee eae eee ora DER NN eee eae En 67 Mn bUSLock hinted ele rea a aa Po an an ea ana 67 MA RNW ood ente at be ket kiddo abra bad Gia RE 68 Mi BED dede Malah e td et alo als hdc SN tete zo Mladen 68 Mnesize 0 3 ns oe en Ma Pa A eee Si NEE ee a 69 Mitype 0 2 capi SE DI REG E be ak ESRB ads bee eee eG 70 Mine Att UTS z ne ple za cee eet DP ie wate a AN ea PD
45. cifies the 32 bit address data 4 byte This parameter specifies the slave memory data to initialize in the corresponding PLB device 6 4 3 Read Response Write Response Commands These commands specify attributes for a slave cycle read or write response when an address decode is true Read_response commands are used to initialize the PLB slave response aack delay integer default 0 This parameter specifies the number of clocks to wait before asserting SI addrAck from the time PLB_PAValid or PLB_SAValid is active For example an aack_delay value of O will assert SI addrAck together with PLB PAValid and an aack_delay of 1 will assert SI addrAck one clock after PLB_PAValid is recognized rearb_delay integer default 0 This parameter specifies the number of clocks to wait before asserting the SI rearbitrate signal from the clock that PLB PAValid was previously asserted No SI addrAck is asserted if the rearb_delay parameter is used DAck delay integer default 0 This parameter specifies the number of clocks to wait before asserting the first data acknowledge control signal for a read response or write_response This parameter is relative to the earliest legal assertion of SI rdDAck and SI wrDAck For example a DAck delay value of O for a read_response causes the SI rdDAck signal to be asserted 2 clocks after SI addrAck is asserted which is the earliest legal PLB slave data response time for the first SI
46. cle and internal memory access commands 6 3 1 Configure Command The configure command allows the user to configure different PLB model attributes One or more parameters can be used with a single configure command and multiple configure commands may be used in a single test case It is important to note that the configure commands are only executed at time 0 in simulation 6 3 1 1 BFL Mode Configuration Parameters msize 2 bit This parameter specifies the Mn_Msize signals of the PLB The valid size combinations are listed in the PLB architecture specifications under transfer qualifier signals This parameter may also be used in each read write master command However when this parameter is used in a configuration statement it is retained throughout the simulation as a master configuration parameter Example configure msize 01 burst continue mode boolean default false When this parameter is set to true and a burst transfer is terminated early the master will automatically issue additional reguests to satisfy the burst count Otherwise the master command which was terminated early by a slave or other cycle terminating condition such as master abort or rearbitrate will be considered complete e msg disable bit default 0 This parameter disables all message generation of the PLB master model including read data error message generation 6 3 1 2 Automatic Command Mode Configuration Paramete
47. configure read addr pipeline disable 1 disable address pipelining for read cycles by ignoring PLB SAValid during read cycles Note Although address pipelining can be disabled in the PLB slave model by user configuration commands and also by simply not connecting the PLB_SAValid signal at the slave interfaces it is important to test pipelining conditions whenever a target system or follow on systems includes pipelining slaves Therefore complete and thorough verification with pipelining enabled and multiple slave devices is recommended for most functional verification efforts 5 4 PLB Monitor The PLB monitor is a model which samples all PLB signals in every clock cycle It checks for violations of the PLB architectural specification during simulation When a warning or error condition occurs by the PLB arbiter master or slave device the model assigns an error register and reports the corresponding condition to the user with a display message Figure 7 demonstrates all PLB monitor interface input output signals See PLB architecture specifications for detailed functional description of the signals 26 Processor Local Bus Functional Model Toolkit Version 4 3 PLB Bus Mn_request Mn_priority 0 1 Mn_busLock Mn_RNW Mn BE 0 3 Mn size 0 3 Mn type 0 2 Mn compress Mn guarded Mn ordered Mn lockError Mn_ABus 0 31 Mn_abort Mn_wrDBus 0 31 Mn_wrBurst Mn_rdBurst PLB_MnAddrAck PLB_MnRearbitrate PLB_MnBusy PLB_Mn
48. cts Each branch instruction executes in one PLB clock cycle SRC This parameter specifies the condition register to determine whether the branch is taken A condition register is used in this comparison Version 4 3 PLB Bus Functional Language 35 OP This parameter specifies the comparison operator to compare the condition register The valid conditions are LT less than GT greater than EQ equal NL not less than NG not greater than NE not equal Label This parameter specifies the BFL destination of the branch if the condition register matches the operator parameter The label must be defined in the test case using the label command attribute Example branch CR3 LT Label1 6 3 10 Move Command The move command enables the user to move a 32 bit internal register or internal memory value to an internal register Register to Register Move instructions execute in one clock cycle Internal memory to register Move instructions are decoded in one clock and the register update occurs in the next clock Note Register data is always available in the next clock for following instructions e DST SRC The SRC parameter specifies the internal register or 32 bit internal memory value to be used as the source of the move instruction The DST parameter specifies the internal register which is updated with the SRC parameter value The DST may be CR SR or R0 31 Example move CR RO Example move CR addr 12345678
49. d extension is simply added to the end of the filename It is possible to invoke the BFC with multiple command files by specifying each file as an argument input parameter to the BFC When multiple files are used in a single BFC call the command file which is generated will be named using the first input file name To invoke the bus functional compiler type BFC filename1 bfl filename2 bfl Note If the message perl not found or other system error is encountered when invoking the BFC ensure that the path for the Perl executable is correct on the first line of the BFC source program as required by the Perl interpreter specification To locate the Perl executable try using the UNIX command which perl 4 4 Initializing the Bus Functional Models The command files which are generated by the bus functional compiler should be executed at simulation time 0 For the VHDL toolkit this is accomplished with an include or do type command after the model is loaded by the simulator For the Verilog toolkit the BFC generates a Verilog initialization command file which should be included when the simulation model is compiled 12 Processor Local Bus Functional Model Toolkit Version 4 3 Chapter 5 PLB Bus Models The toolkit contains bus functional models for PLB master PLB slave and PLB monitor The PLB master and slave models are controlled through a bus functional command interface which is defined in PLB Bu
50. dDAck is asserted in a cycle after a wrDAck then the read data always reflects the new data written If a rdDAck is asserted in a cycle before or during a wrDAck then the read data always reflects the old data Since the PLB architecture allows out of order rd wrDAcks with respect to addrAck from the same slave it is the responsibility of the system designer to resolve data coherency issues when simultaneous write read cycles occur Slave memory and configuration parameters are initialized at simulation time O with the command file generated by the PLB bus functional compiler The slave response commands are initialized in the slave command array at simulation time 0 but they are executed sequentially during simulation Separate read and write internal command pointers advance when bus transfers complete a rearbitrate occurs or a master abort occurs Intermediate data checking during simulation can be done by using memory check commands which are executed when an intercommunication signal is received by the slave These memory check commands are independent of the slave response command flow The default size of the bus command array is 256 entries This may be increased or decreased by updating the PLB slave CMD array size parameter in the PLB DCL declaration HDL file of the toolkit 5 3 3 Command Modes This section discusses the possible modes that are available for a PLB slave device PLB slaves may be configured to act in either Configuratio
51. del attaches to the PLB bus and generates informational architectural compliance messages during simulation The model is passive in that it does not participate in any bus protocol signal assertions but it samples PLB signals in every clock to keep track of the state of the PLB bus and inform the user of any detectable PLB compliance problems Messages are generated to the simulator console which also may be re directed to file systems in most simulation environments 8 2 Terminology The following terminology is used in the specification of the PLB monitor compliance checks e Active refers to the situation when a signal is at its true state a logical 1 e Asserted refers to the situation when a signal transitions from inactive to its active state e Inactive refers to the situation when a signal is at its false state a logical 0 e Deasserted refers to the situation when a signal transitions from active to its inactive state e Time out refers to the event which occurs when there have been 16 cycles of non response from a slave or Mn_abort since the assertion of PLB_PAValid The 16 cycle count may be interrupted by the slave response of Sln_wait active And the count will remain interrupted for as long as the wait is active The count will be terminated by slave asserting Sin rearbitrate or Sn_addrAck The count may also be terminated by the master asserting Mn_abort given no Sn_addrAck has been received If the count reaches 16 and
52. del toolkit The user should also be familiar with UNIX type operating systems basic digital logic design and simulation and the simulator which is used for the verification process Related Publications The following publications contain related information Processor Local Bus Architecture Specifications On Chip Peripheral Bus Architecture Specifications Device Control Register Bus Architecture Specifications Processor Local Bus Toolkit User s Manual On Chip Peripheral Bus Toolkit User s Manual Version 4 3 About This Book xiii Device Control Register Bus Toolkit User s Manual Processor Local Bus Arbiter Core User s Manual On Chip Peripheral Bus Arbiter Core User s Manual PLB to OPB Bridge Core User s Manual OPB to PLB Bridge Core User s Manual How This Book is Organized This book is organized as follows Chapter 1 PLB Toolkit Overview Chapter 2 PLB Toolkit Environment Chapter 3 PLB Toolkit Test Bench Chapter 4 PLB Bus Functional Compiler Chapter 5 PLB Bus Models Chapter 6 PLB Bus Functional Language Chapter 7 PLB Bus Timing Chapter 8 PLB Compliance Checks To help readers find material in these chapters the book contains e Contents on page v e Figures on page ix e Tables on page xi e Index on page 87 Xiv Processor Local Bus Functional Model Toolkit Version 4 3 Chapter 1 PLB Toolkit Overview Processor local bus PLB functi
53. der Test 9 VHDL Signal Types ui e td A a hie ete a 9 IEEE Packages iii a EA A oad AE ERA 9 Chapter 4 PLB Bus Functional Compiler 11 Simulator GONTIQUIAI N sacra iaa ari a ara 11 Declarations File Access 11 Invoking the Bus Functional Compiler 12 Initializing the Bus Functional Models 12 Chapter 5 PLB Bus Models 13 Running the 4X Bus Models in 3X Mode 13 PLB Master Model 4 5 lt del ai 15 Master Model Operation a pe aa DSE 16 Decode Unit ana tenan Saw ee naa maa Wina eke ebook da Rn Wah 16 Internal Master Data Memory ii 17 Command Modest ama mana Hara been ba bea aa ia ts 17 Burst Operations ciao sbb alan MN ama ban bee bb el heel eee eas 18 Conversion Cycles with Different PLB Device Sizes 19 General Purpose and Branch Processor Registers 19 ALU INStrUCIONS vito PE BA eee hth PERSE EN aS ewes 19 Branch Instructions es oe Wad Rete At ae BA eee on eid letela 20 PLB slave Model ic vs tai ena ees AA ee WN tate NUR Pn ant 21 Slave Model Operation na 22 Slave Bus Commands and Modes
54. diate 4 byte data value or an internal register may be used Example mem update addr 00001000 data 05060708 6 3 6 Reg Update Command The reg update command updates an internal master register during the decode and execution of master bus commands Each reg update command executes in one PLB clock cycle DST z 4 byte This parameter specifies the 32 bit destination register of the internal register to be updated 34 Processor Local Bus Functional Model Toolkit Version 4 3 Example reg update R0 05060708 6 3 7 Send Command The send command causes a vectored intercommunication signal to be asserted at the corresponding level parameter and does not directly cause PLB bus activity The synch Out signal is asserted for one clock per send instruction and may be used to communicate between multiple model instantiations in order to coordinate bus activity The send is executed seguentially along with the read write commands and is a serializing instruction meaning that the model waits for all previously issued bus cycles to complete on the bus before sending its intercommunication signal level integer range 0 to 31 The level parameter allows for one or more send signals to be asserted on the synch_Out bus Multiple levels may be used in the same clock by listing more than one level Note that it is possible for a user to use the same intercommunication level with multiple masters however the assertion of the same level
55. dr 0000000c data 0c0d0e0f read response aack delay 0 dack delay 0 read response aack delay 0 dack delay 0 read response aack delay 0 dack delay 0 read response aack delay 0 dack delay 0 mem_check level 0 addr 00000000 data 00010203 mem_check level 0 addr 00000004 data 04050607 mem_check level 0 addr 00000008 data 08090a0b mem_check level 0 addr 0000000c data 0c0d0e0f Version 4 3 PLB Bus Timing 53 7 5 Back to Back Write Transfers Figure 12 shows the operation of several back to back single write transfers on the PLB c ME oa SYS pibcik m Mi m PL IH Transfer Gualifiers 2 A N3 Mn reguest Na 4 Mn priority 0 1 X validY validX validX validY Mn busLock Mn_ANW n s i se ee ele Mn_type 0 2 y Y T 000 Mn abort AAA Mn ABus 0 31 ar X we yas Xa X PLB_PAValid ORT AN ZN ad a Si wait i 4 4 ZME SI AddrAck AMI NY 4 Write Data Bus Mn wrDBus 0 31 X D A1X DAN DAN DAA Si wrDAck NAVA VAERVA E SI wrComp 4 2 3 4 Mn_wrBurst Read Data Bus SI rdDBus 0 31 0000 SI rdWdAdar 0 3 l 0000 Sl_rdDAck l Sl_rdComp Mn_rdBurst Figure 12 Back to Back Write Transfers set device path plb_complex plb_master0 device_type plb_master mem init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem in
56. e during the data phase of a burst write transfer e Error 2 12 2 An error message is issued when SIn_wrComp is active outside of allowed window i e from the assertion of Sln_addrAck to the assertion of Sln_wrComp e Error 2 12 3 An error message is issued when more than one slave asserts Sin wrComp in the same clock 8 7 13 Sin wrBTerm The following error messages are issued for this signal e Error 2 13 1 An error message is issued when SIn_wrBTerm is active outside of allowed window from the assertion of Sln_addrAck to the assertion of Sln_wrComp e Warning 2 13 2 A warning message is issued when Sin wrBTerm is not asserted during a guarded burst transfer that crosses a 1k address boundary e Note 2 13 3 A note message is issued if this signal is asserted pre maturely during a fixed length burst transfer This means the wrbterm is asserted when there is more than one dack required to meet the number of expected dacks 8 7 14 Sin rdDBus The following error messages are issued for this signal e Error 2 14 1 An error message is issued when a slave drives data other than zeroes on its Sin rdDBus 0 31 when not selected for a read transfer 8 7 15 Sin rdWdAddr 0 3 The following error messages are issued for this signal e Error 2 15 1 An error message is issued when a slave drives data other than zeroes on its Sin rdWdAddr 0 3 when not selected for a read transfer Version 4 3 PLB Compliance Checks 79 Err
57. e to automatically assert the SI rd wrBterm signal when a fixed length burst cycle is in progress and the corresponding number of data transfer has occurred on the bus wait disable 1 bit Ozenabled 1 disabled default 0 This parameter specifies if the SI wait signal can be asserted When this parameter is used in the configuration statement of the slave the wait_disable will be constant for the entire simulation session wait mode z 1 bit Ozassert on address 1 delay mode default 0 This parameter specifies how the SI wait signal is asserted When assert on address mode is used the slave will assert SI wait whenever the PLB_Abus is within the slave address range When delay mode is used SI wait will be asserted based on both an address match and the wait parameter of the read write response commands read addr pipeline disable 1 bit O lt SAValid recognized 1 SAValid ignored default 0 This parameter specifies whether the PLB core secondary address valid control signal is recognized by the PLB slave model during secondary read requests When programmed to recognize PLB_SAValid the PLB slave model asserts addrAck during PLB_SAValid and queues secondary read requests which are processed after primary requests are complete The PLB_rdPrim and PLB wrPrim signals are used to switch secondary requests to primary status within the model When this parameter is used in the configuration statement of the slave the read_addr_pipeline_mod
58. e will be constant for the entire simulation session write addr pipeline disable 1 bit 0 SAValid recognized 1 SAValid ignored default 0 This parameter specifies whether the PLB core secondary address valid control signal is recognized by the PLB slave model during secondary write reguests When programmed to recognize PLB SAValid the PLB slave model asserts addrAck during PLB SAValid and queues secondary write reguests which are processed after primary reguests are complete The PLB rdPrim and PLB wrPrim signals are used to switch secondary reguests to primary status within the model When this parameter is used in the configuration statement of the slave the write addr pipeline mode will be constant for the entire simulation session data pipeline mode 1 bit O overlapped DAck mode 1 seguential DAck mode default 0 Version 4 3 PLB Bus Functional Language 39 This parameter specifies whether the PLB slave model may assert read and write data acknowledge signals simultaneously When programmed for sequential DAck mode the slave model will not assert read and write DAcks in the same clock When this parameter is used in the configuration statement of the slave the data_pipeline_mode will be constant for the entire simulation session e msg disable bit default 0 This parameter disables all message generation of the PLB slave model including data error message generation 6 4 1 2 Automatic Command Mode Configuration Pa
59. easserted for a secondary read cycle without a valid termination of the request by either Sin_addrAck or Mn abort SI rdComp or SI rearbitrate Error 2 2 2 An error message will be issued if PLB_SAValid is deasserted for a secondary write cycle without a valid termination of the request by either SIn_addrAck or Mn abort SI wrComp or SI rearbitrate Error 2 2 3 An error message will be issued when a secondary request is not converted into a primary request This occurs when PLB_SAValid is deasserted because of a SIn_rd wrComp assertion without overlapped SI addrAck PLB abort and PLB_PAValid is not active in the next clock Error 2 2 4 An error message is issued if PLB SAValid and PLB PAValid are active in the same clock Error 2 2 5 An error message is issued if PLB SAValid is active and PLB rd wrpendReg is inactive Error 2 2 6 An error message is issued when PLB SAValid is active and SYS plbReset is active 8 7 3 Sin addrAck The following error messages are issued for this signal Error 2 3 1 An error message is issued when SIn_addrAck is asserted and PLB PAValid or PLB SAValid is inactive Error 2 3 2 An error message is issued when SIn addrAck is active while the slave is not selected This check depends on user defined address map Error 2 3 3 An error message is issued when more than one slave asserts Sin addrAck in the same clock 8 7 4 Sin wait The following error messages are issued for this signal Er
60. ed from the destination register The DST must be RO 31 SR or CR Example sub R0 01 6 3 14 AND Command The AND command updates an internal master register with the result of a bit wise AND operation between an internal register and an immediate value Each AND command executes in one PLB clock cycle DST hex value up to 4 bytes These two parameters specify the 32 bit internal destination register to be updated and the immediate hexadecimal value to be AND d with the destination register The DST must be RO 31 SR or CR Example and RO FFFFFFFO 6 3 15 OR Command The OR command updates an internal master register with the result of a bit wise OR operation between an internal register and an immediate value Each AND command executes in one PLB clock cycle DST hex value up to 4 bytes These two parameters specify the 32 bit internal destination register to be updated and the immediate hexadecimal value to be OR d with the destination register The DST must be RO 31 SR or CR Example or R0 01 Version 4 3 PLB Bus Functional Language 37 6 3 16 Shift_left Command The Shift_left command updates an internal master register with the result of a bit wise Shift_left operation between an internal register and an immediate value Each Shift_left command executes in one PLB clock cycle DST integer value These two parameters specify the 32 bit internal destination register to be updated and im
61. emory which can be initialized through the bus functional language This memory may be dynamically checked during simulation or when all bus transactions have completed Figure 6 demonstrates all PLB slave interface input output signals See PLB architecture specifications for detailed functional description of the signals Version 4 3 PLB Bus Synch in p PLB PAValid gt PLB busLock gt PLB_masterlD 0 3 PLB RNW PP PLB BE 0 3 PLB_size 0 3 gt PLB_type 0 2 gt PLB_MSize 0 1 PLB guarded gt PLB ordered gt PLB lockErr gt PLB abort PP PLB_ABus 0 31 P 4 Synch out SI addrAck SI wait 4 Sl_SSize 0 1 4 SI rearbitrate SI_MBusy 0 15 H SI MErr 0 15 PLB SAValid bi PLB rdPrim gt PLB wrPrim PLB_wrDBus 0 31 PLB wrBurst gt SI wrDAck 4 Sl_wrComp Sl wrBTerm PLB rdBurst Pp 4 SI rdDBus 0 31 4 sli rdWdaAddr 0 3 4 Sl rdDAck 4 SI rdComp ia Sl rdBTerm Slave Interface Transfer Qualifiers Address Pipelining Write Data Bus Read Data Bus Figure 6 PLB Slave Interface PLB Bus Models 21 5 3 1 Slave Model Operation The PL
62. enable command mode The user is not required to specify a BFL configuration parameter to use this mode Auto Mode This response mode enables various cycle responses without using pre programmed read write slave response commands In this mode the PLB slave model generates address and data phase completion signals automatically based on an internal random number generator and pre programmed minimum and maximum delays The random number generator selects a new delay value between the minimum and maximum using a uniform distribution function The minimum and maximum range may be initialized by the user using a configuration command The PLB slave model requires a configuration command for enabling auto mode The following configure statement is an example configure slave_auto_mode true 5 3 4 Internal Slave Data Memory Structure and Look Up Algorithms The PLB slave model contains an internal memory array which can be initialized by the user with mem init bus functional commands Each entry of the memory array represents a 64 bit address and 128 bit data PLB slave addr array 0 to 63 bits 0 to 61 address bit 62 dirty bit bit 63 valid bit PLB slave data array 0 to 127 4 word data field PLB slave dirty array 0 to 15 bytes written half word field Bits 62 and 630f the PLB slave addr array are not used for addressing bytes within the PLB slave model memory but they are used by the internal slave model memory in
63. environment in which they may initialize the toolkit models and simulate with the ability to detect error conditions in PLB bus protocol and also in data consistency Test cases are written using a bus functional language which is described in PLB Bus Functional Language on page 28 Note All user verification procedures and regressions should include a released and qualified PLB core from the IBM Core ASIC library which will be included in the target product silicon 2 1 Bus Functional Compiler and ReadMe Files The following files represent the bus functional compiler and a readme file BFC This Perl program parses the test cases written in the bus functional language and generates command files which are used to control the bus functional models README This file provides information about the toolkit release including functional support level and any known errata UPDATE LOG This file provides information about changes in the toolkit release relative to the previous release 2 2 VSS Script Files The following files are example VSS script files for model compilation invoking simulation signal tracing and a BFL test case e analyze VSS analyze MTI These example script files compile the VHDL version of the toolkit for VSS and MTI into the work library teb This Perl program invokes the bus functional compiler with a BFL file as a program argument It then invokes the VSS simulator with the command file wh
64. ers can be used with a single configure command and multiple configure commands may be used in a single test case It is important to note that the configure commands are only executed at time 0 in simulation 6 4 1 1 BFL Mode Configuration Parameters e SSize 2 bit This parameter specifies the SIn SSize signals of the PLB The valid size combinations are listed in the PLB architecture specifications This parameter may also be used in each read write slave response command However when this parameter is used in a configuration statement it is retained throughout the simulation as a slave configuration parameter 38 Processor Local Bus Functional Model Toolkit Version 4 3 Example configure ssize 01 burst_term_mode enumerated type default cycle This parameter specifies whether the PLB slave behavior should terminate burst cycles based on the number of data transfers which have occurred or the number of clocks from the time the burst transaction starts The valid types are cycle or clk rdWord mode 1 bit O seguential 1 target word first This parameter specifies the address incrementation order for the slave during line transfers The valid modes are sequential and target word first When this parameter is used in the configuration statement of the slave the rdWord mode will be constant for the entire simulation session fixed burst mode 1 bit O disabled 1 enabled This parameter configures the slav
65. erted Error 1 1 2 An error message is issued when Mn reguest is active and SYS plbReset is active Warning1 1 3 A warning message of possible deadlock is issued when Mn reguest is not inactive for 2 clock cycles after PLB MnRearbitrate Mn reguest and Mn busLock are sampled active with PLB Mnaddrack inactive Error 1 1 4 Requesting master which has the bus locked did not deassert Mn Reguest for two clocks after a rearbitrated request 8 6 2 Mn priority 0 1 No protocol checks 8 6 3 Mn busLock The following error messages are issued for this signal Error 1 3 1 An error message is issued when a master s Mn busLock is active without its Mn reguest being active unless the bus is already locked by the reguesting master Error 1 3 2 Version 4 3 PLB Compliance Checks 67 A warning message of possible deadlock is issued when Master n has the bus locked and Mn_busLock is not inactive for 2 clock cycles after PLB_MnRearbitrate Mn_Request and Mn_busLock are sampled active with PLB MnAdarAck inactive Error 1 3 3 An error message is issued when Mn_busLock is active and SYS_plbReset is active Warning1 3 4 A warning message is issued when Mn_busLock is de asserted during a master request phase before PLB_MnaddrAck Mn_abort MnTimeout or PLB MnRearbitrate is asserted Error 1 3 5 Requesting master did not deassert Mn_busLock for two cycles after a rearbitrated request ERROR 1 3 6 An error message is issued when Mn_busLock
66. espond to a single cycle If both address parameters are equal they are not used as a valid address decode e read aack min max integer default 0 15 These parameters specify the range for aack_delay during read cycles when slave_auto_mode is true The model automatically assigns a random delay to the aack_delay between and including the minimum and maximum values e write aack min max z integer default 0 15 These parameters specify the range for aack_delay during write cycles when slave_auto_mode is true The model automatically assigns a random delay to the aack_delay between and including the minimum and maximum values e read_rearb_min max integer default 12 15 These parameters specify the range for rearb_delay during read cycles when slave_auto_mode is true The model automatically assigns a random delay to the rearb_delay between and including the minimum and maximum values write rearb min max integer default 12 15 40 Processor Local Bus Functional Model Toolkit Version 4 3 These parameters specify the range for rearb_delay during write cycles when slave_auto_mode is true The model automatically assigns a random delay to the rearb_delay between and including the minimum and maximum values e read wait min max integer default 12 15 These parameters specify the range for wait delay during read cycles when slave auto mode is true The model automatically assigns a random delay to the wait del
67. essage is issued when this signal is active and the PLB_masterlD identifies a different master as granted Error 1 17 3 An error message is issued if arbiter does not assert this signal when a time out occurs This check is not performed for PLB 4 x Error 1 17 4 An error message is issued if PLB asserts PLB_MnAddrAck when a different master has locked the PLB Error 1 17 5 An error message is issued if PLB asserts more than one PLB MnAddrAck in the same clock 8 6 16 PLB MnRearbitrate The following error messages are issued for this signal Error 1 18 1 An error message is issued when this signal is active and the PLB masterlD identifies a different master as granted Error 1 18 2 An error message is issued when this signal is active and the corresponding Mn reguest is inactive Error 1 18 3 An error message is issued when this signal is asserted by PLB during a secondary request This check is not performed for PLB 4 x 8 6 17 PLB_MnWrDAck The following error messages are issued for this signal Error 1 19 1 An error message is issued if PLB MnWrDAck is asserted outside of window from assertion of PLB_MnAddrAck to assertion of SIn wrComp Version 4 3 PLB Compliance Checks 73 8 6 18 PLB_MnRdDAck The following error messages are issued for this signal e Error 1 20 1 An error message is issued if PLB MnRdDAck is asserted outside of the window defined from 2 clocks after the assertion of PLB MnAddrAck t
68. essages are issued for this signal Error 2 30 1 An error message is issued if this arbitration gualifier does not match Mn busLock when PLB MnAdarAck is active Error 2 30 2 An error message is issued if PLB busLock and PLB SAValid are active at the same time Error 2 30 3 An error message is issued when PLB busLock is active and SYS plbReset is active Error 2 30 4 An error message is issued if this arbitration gualifier does not match Mn busLock when the bus is already locked Error 2 30 5 An error message is issued if this signal is asserted with no PLB PAValid or PLB SAValid and the bus is not locked 8 7 29 PLB rdBurst The following error messages are issued for this signal 84 Error 2 31 1 PLB rdBurst and PLB RESET are active at the same time Error 2 31 2 PLB asserted PLB rdBurst without a primary or secondary read burst transfer acknowledged Error 2 31 3 PLB rdBurst does not match M rdBurst during a read burst transfer Error 2 31 4 PLB reasserted PLB rdBurst before the current burst transfer received its last dAck Error 2 31 5 PLB failed to deassert PLB rdBurst after bTerm was received for the current burst transfer Processor Local Bus Functional Model Toolkit Version 4 3 8 7 30 PLB_wrBurst The following error messages are issued for this signal e Error 2 32 1 An error message is issued if this transfer qualifier does not match Mn_wrBurst during a primary request with PLB_PAValid active
69. g the subject matter in this publication The furnishing of this publication does not give you any license to these patents You can send license inquiries in writing to the IBM Director of Licensing IBM Corporation 208 Harbor Drive Stamford CT 06904 United States of America The following terms are trademarks of IBM Corporation IBM CoreConnect Other terms which are trademarks are the property of their respective owners Contents eo ee rr A ERE A ix Tables eiriaa ad ded bid Sid eth et edd ee wc AAA dentate eee xi ABOUT This BOOK i is da a as ATRAER At A AE e tends teja ie xiii Chapter 1 PLB Toolkit Overview 1 PLB Toolkit Features cs Suede pa en amankan A baa Sa pan eee Talk 2 PLB Features Giaa e PAN Ui Pena DEL A NAN eb aje tadej E 2 PLB Implementation pita an che SEN LEE SNN BOLA eR 4 Chapter 2 PLB Toolkit Environment 5 Bus Functional Compiler and ReadMe Files 5 VSS ScriptEiles24 sec kewego d ebi laa era nee 5 Example Test Case File soon niki diva rd cee bbe dL a pe aa ees 6 VHDE VeErilog FIlSS ija sponte RA NN i NE Be a 6 Chapter 3 PLB Toolkit Test Bench 8 Programmable PLB Data Bus Width and Automatic Replication 8 Instantiating PLB Slave Designs Under Test 9 Instantiating PLB Master Designs Un
70. he user through direct register access and message generation 5 1 Running the 4X Bus Models in 3X Mode As discussed previously the 4X toolkit may be configured to run in 3X mode This allows the user to have access to all of the functionality and signals from the 3X toolkit with additional checks from the Version 4 3 PLB Bus Models 13 monitor and improvements to the toolkit itself In order to run in 3X mode the user must do the following Change the PLB ARCHITECTURE VERSION in the plb_dcl to 3 e Change the PLB DATA BUS WIDTH in the plb_dcl to 64 e Change the PLB READ PIPELINE DEPTH in the plb dcl to 2 A larger value can be used when using the arbiter model e Instantiate devices using the 3X wrappers i e use plb master3x plb slave3x titles for instantiation e Connect the byte enable signals for a 64 bit bus byte enables are 8 bits for a 64 bit bus as opposed to 4 bits for a 32 bit bus and 16 bits for a128 bit bus e Note that ordered guarded and compressed are separate in 3X but are part of the t attribute in 4X Note that merr in 3X is separated into mrderr and mwrerr in 4X Note that mirq does not exist in 3X 14 Processor Local Bus Functional Model Toolkit Version 4 3 5 2 PLB Master Model The PLB master model contains logic to automatically request the bus when it has read write commands to execute It performs an operation based on the bus functional command which was initialized in the internal mas
71. hich uses the intercommunication bus When instantiating toolkit models which need to support the send wait commands as described in PLB Bus Functional Language on page 28 ensure that the intercommunication logic within the test bench is updated to reflect the additional model instantiations 3 4 VHDL Signal Types The signal interface for the VHDL bus functional model wrappers and test bench are declared as IEEE std logic and std logic vector signal types If the bus functional models are integrated with a test bench environment which uses bit and bit vector types the wrappers may be eliminated so that type conversions do not have to be included in the model interfaces When the wrappers are not used please note that the I O for each PLB toolkit model component contains primary inputs for configuration signals rather than the VHDL generic declarations which are in each wrapper 3 5 IEEE Packages The VHDL version of the PLB core RTL is translated from Verilog to VHDL with a source level language translator The translated VHDL calls out some IEEE packages such as Version 4 3 PLB Toolkit Test Bench 9 ieee std logic 1164 all ieee std logic arith all ieee std logic unsigned all Some VHDL compilers and analyzers may reguire the use of compiler directive switches to resolve overloaded relational operators 10 Processor Local Bus Functional Model Toolkit Version 4 3 Chapter 4 PLB Bus Functional Compiler Test cases written i
72. ich was generated by the bus functional compiler e tec This Perl program invokes the VSS simulator with a previously generated command file from the bus functional compiler The command files from the bus functional compiler have a cmd file extension plbbus Version 4 3 PLB Toolkit Environment 5 This is an example VSS command file which contains trace commands for the PLB bus 2 3 Example Test Case File sample bfl This file is an example PLB BFL file Note the path in the set_device command may be updated for user simulator hierarchical structure specifications alu bfl This example BFL file contains ALU and branch commands to illustrate a looping condition mon_init bfl This example BFL file contains monitor initialization statements for slave address range initialization used in PLB Monitor checking code 2 4 VHDL Verilog Files The following list of files comprise the models and test bench of the PLB toolkit The files should be compiled in the order specified pib pkg vhd pib pkg inc This HDL file is used by the PLB behavioral models to implement internal functions such as type conversion and other general procedures plb_dcl vhd plb_dcl inc This HDL file contains the component and constant declarations for the toolkit behavioral models plb_master_comp vhd plb_master_comp v This HDL file represents a PLB master device It contains decode execute and bus logic to interface with the PLB b
73. il the addressed slave asserts its Sin addrAck or the transfer is terminated through Mn_abort PLB_MnRearbitrate or PLB_MnTimeout 8 7 11 Sin wrDAck The following error messages are issued for this signal e Error 2 11 1 An error message is issued when a slave asserts its SIn_wrDAck before asserting its Sln_addrAck or after asserting its Sln wrComp e Error 2 11 2 An error message is issued when on a non burst write transfer the slave fails to give expected number of wrDAcks Error 2 11 3 An error message is issued when this signal is asserted during a DMA transfer type1 4 5 7 from the assertion of Sin addrack to the assertion of Sln wrComp e Error 2 11 4 An error message is issued when a slave asserts is SIn wrDAck after it has already been asserted for the last write data transfer of a burst write e Error 2 11 5 An error message is issued if more than one SI wrDAck is asserted during the same clock cycle Error 2 11 6 An error message is asserted when this signal is asserted for a transfer that is outside of the slave s assigned address space e Error 2 11 7 78 Processor Local Bus Functional Model Toolkit Version 4 3 An error message is asserted when wrcomp is asserted for a burst transfer before the last wrdack of the burst is received 8 7 12 Sin wrComp The following error messages are issued for this signal e Error 2 12 1 An error message is issued when SIn_wrComp is asserted and PLB_wrBurst is activ
74. in the same clock by multiple masters will not be distinguished on the intercommunication send vector e reg delay integer This parameter specifies how many clock cycles the PLB master needs to wait before it asserts the synch signal for the corresponding send instruction The counter starts when all cycles on the bus are complete since the send instruction is a serializing instruction Example send level 1 6 3 8 Wait Command The wait command causes the bus master to suspend instruction decode until an intercommunication signal is received The wait instruction is a serializing instruction and is executed sequentially along with the read write commands In addition all previously issued bus cycles need to complete on the bus before the intercommunication signal on the synch In bus is recognized level integer range 0 to 31 The level parameter specifies the synch In signal to be sampled before instruction execution continues Example wait level 1 6 3 9 Branch Command The branch command enables the user to re direct the command decode location within the PLB master decode unit internal command array lt also enables looping and jumping Branch targets are established by specifying label attributes with a PLB master command such as Ti read reg delay 3 addr 00001000 size 0000 be 1111 establish a branch target called T1 Note The between the label and master command delineates the two BFL constru
75. ing each data phases of the burst transfer The PLB Slave model supports two types of counting mechanisms for asserting sl rd wrBterm It can count by the number of clocks from the start of the data phase of the transaction or by the number of sl rd wrDack assertions from the start of the transaction The PLB slave will assert the burst terminate signal when burst_term parameter is used and the corresponding count parameter has expired The PLB slave model also supports the PLB fixed length burst protocol The slave model will automatically assert the SI rd wrBterm signal when the fixed burst mode is enabled the PLB BE signal is non zero the PLB size signal indicates a burst cycle and the corresponding number of data transfers has occurred To enable fixed length burst in the slave model use the following slave configuration statement configure fixed burst mode 1 Default is 0 disabled Note The PLB Architecture allows slave designs to assert sl rdBterm anywhere from one clock after sl AddrAck or PLB rdPrim to sl rdComp for read transactions and together with sl AddrAck or one clock after PLB wrPrim to sl wrComp for write transactions It is common for PLB Slave designs to assert sl rd wrBterm together with the second to last sl rd wrDack assertions However in order to achieve 100 percent functional verification of a PLB master design the Burst Term Mode Clk should be used to assert the sl rd wrbTerm signals in every po
76. is active 8 7 34 PLB SrdDbus The following error messages are issued for this signal e Error 2 36 1 An error message is issued if the PLB_sRdDbus is not properly replicated as indicated in the architecture specification for smaller slaves connected to larger width PLB Arbiters 8 8 Time Out Handshake Checks For 3 x PLB The following checks relate specifically to the event of time out as described in the beginning of this document Furthermore these checks are implemented based on two implementation assumptions 1 The arbiter will respond with required handshaking to the master within two cycles of time out 2 All required handshaking to complete the timed out request is done in a minimal number of cycles For example in the event of a 4 word line read transfer that timed out then 4 successive PLB rdDAcks are to be issued with accompanying PLB_MErr with no wait cycles between these 8 8 1 PLB MnWrBTerm The following error messages are issued for this signal Error 3 1 1 An error message is issued when a write burst transfer has timed out and the arbiter does not assert this signal to the corresponding master who s request timed out 8 8 2 PLB MnRdBTerm The following error messages are issued for this signal Error 3 2 1 An error message is issued when a read burst transfer has timed out and the arbiter does not assert this signal to the corresponding master who s request timed out 8 8 3 PLB MnErr An error mess
77. is asserted for a requesting master after a new request was started and before PLB_MnAddrAck Mn_abort PLB_MnRearbitrate or MnTimeout 8 6 4 Mn RNW The following error messages are issued for this signal Error 1 4 1 An error message is issued when a master changes this transfer gualifier from when a reguest to transfer is made until PLB MnAddrAck Mn abort PLB MnRearbitrate or Mn Timeout is asserted 8 6 5 Mn BE 0 3 The following error messages are issued for this signal 68 Error 1 5 1 An error message is issued when a master changes this transfer gualifier from when a reguest to transfer is made until PLB MnAddrAck Mn abort PLB MnRearbitrate or Mn Timeout is asserted Error 1 5 2 An error message is issued if there are no enabled bytes on Mn BE when Mn reguest is active and Mn size indicate a non line non burst transfer Error 1 5 3 An error message is issued if Mn BE contains non contiguous enabled bytes when Mn reguest is active and Mn size indicate a non line non burst transfer memory transfer Error 1 5 4 An error message is issued if the Mn BE bit corresponding to the LSB bits of Mn ABus encode is not active for a non line non burst transfer For example On a non line non burst transfer reguest with Mn ABus 30 31 11 Mn BE 0 3 must be 0001 Error 1 5 5 Processor Local Bus Functional Model Toolkit Version 4 3 8 6 6 Mn size 0 3 An error message is issued if the Mn BE signal is
78. it addr 00000008 data 08090a0b mem init addr 0000000c data 0c0d0e0f write addr 00000000 size 0000 be 1111 write addr 00000004 size 0000 be 1111 write addr 00000008 size 0000 be 1111 54 Processor Local Bus Functional Model Toolkit Version 4 3 write addr 0000000c size 0000 be 1111 send level 0 set device path plb_complex plb_slave0 device_type plb_slave Initialize device 0 mem init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init addr 0000000c data 0c0d0e0f write response aack delay 0 dack delay 0 write response aack delay 0 dack delay 0 write response aack delay 0 dack delay 0 write response aack delay 0 dack delay 0 mem_check level 0 addr 00000000 data 00010203 mem_check level 0 addr 00000004 data 04050607 mem_check level 0 addr 00000008 data 08090a0b mem_check level 0 addr 0000000c data 0c0d0e0f Version 4 3 PLB Bus Timing 55 7 6 Back to Back Read Write Read Write Transfers Figure 13 shows the operation of several back to back single read and write transfers on the PLB Cycle SYS plbCik Transfer Qualifiers Mn_request Mn_priority 0 1 Mn_busLock Mn_RNW Mn_BE 0 3 Mn_size 0 3 Mn_type 0 2 Mn_abort Mn_ABus 0 31 PLB_PAValid SI AddrAck SI wait Write Data Bus Mn wrDBus 0 31 SI wrDAck SI wrComp Mn wrBurst Read Data Bus SI rdDBus 0 31 SI rdWdAddr 0 3 SI rdDAck SI rdComp Mn rdBurst Ema AA EAN
79. itecture allows data transfers among OPB peripherals to occur independently from and concurrent with data transfers between the processor and memory or among other PLB devices The toolkit allows users to initiate PLB master cycles and provide PLB slave responses through a bus functional language which is parameterized according to the architectural specification Data checking and bus protocol monitoring also provide a way for users to automate the verification of PLB designs under development Source files in ASCII format are distributed with the toolkit which include behavioral models programs and documentation 1 1 PLB Toolkit Features PLB toolkit features e Unit and subsystem level simulation of logic designs which comply with PLB architecture specifications e VHDL and verilog source model solutions with simulator independence e Bus functional command definition which generates and responds to different transaction types with varying delays e Bus functional compiler which generates model initialization files from bus functional commands e Bus protocol checking through the use of general purpose bus monitors Read and write data checking in masters and slaves e Model inter communication bus for event and transaction synchronization e Enables peripheral developers to verify and debug designs to assure bus compliance e Faster simulation run times than PPC BFM or FFM to generate bus traffic Allows what if simu
80. itiate and respond to bus cycles The command files also contain model configuration information The general form of a bus functional language command is specified as follows command parameters Parameters define attributes for bus cycles and configurations A bus command may have more than one parameter and have the following format parameter value A parameter value may be either a scalar or enumerated type that is a string Note 1 Bus functional language BFL comments are delineated using the or string All characters after the comment delineator are ignored by the BFL parser An end of line character terminates a comment Note 2 Bus functional language is case insensitive Note 3 A denotes an optional parameter otherwise the parameter is required Note 4 There is no restriction on the order in which parameters may be specified within a command Note 5 If multiple parameters are specified for the same command they must be separated by commas 6 1 BFM Device Configuration Commands This section discusses set_device path string and device_type string configuration commands 6 1 1 Set_Device Command The set_device command selects a model to initialize Within a BFL file test case there may be only one set_device command used per model initialization e Path String The path string specifies the path of the model within the test bench hierarchy The commands following the set
81. itor will check that each transaction completes with the expected values that are provided by the monitor bfl PLB Master 0 set device path plb complex m0 device type plb master configure msize 00 mem_init addr 00021000 data 001 12233 mem_init addr 00021004 data 44556677 mem_init addr 00021008 data AABBCCDD mem_init addr 0002100C data AABBCCDD write addr 00021000 size 0000 be 1111 write addr 00021004 size 0000 be 1111 write addr 00021008 size 0000 be 1111 write addr 0002100C size 0000 be 1111 read addr 00021000 size 0000 be 1111 read addr 00021004 size 0000 be 1111 read addr 00021008 size 0000 be 1111 read addr 0002100C size 0000 be 1111 PLB Slave 0 set device path plb complex s0 device type plb slave Initialize device 0 configure ssize 00 mem_init addr 00021000 data AABBCCDD mem init addr 00021004 data AABBCCDD mem init addr 00021008 data AABBCCDD mem init addr 0002100C data AABBCCDD write response aack delay 4 dack delay 3 write response aack delay 3 dack delay 3 write response aack delay 2 dack delay 3 46 Processor Local Bus Functional Model Toolkit Version 4 3 write_response aack_delay 1 dack_delay 3 read_response aack_delay 4 dack_delay 2 read_response aack_delay 3 dack_delay 2 read_response aack_delay 2 dack_delay 2 read response aack delay 1 dack delay 2 PLB Monitor BFL set device path plb complex mon device type plb monitor configure msize 00 ssize 00 wri
82. lation scenarios using different master and slave configurations Flexible and user friendly bus functional language BFL for quick generation of a variety of bus transactions e Hierarchical solution to verification 1 2 PLB Features The PLB model toolkit enables the user to simulate the following PLB features e Separate address bus read data bus and write data bus for each bus master Shared address bus read data bus and write data bus for all bus slaves 2 Processor Local Bus Functional Model Toolkit Version 4 3 Separate read data bus and write data bus transfer qualifiers allow overlap of read and write transfers Maximum bandwidth of the bus is two transfers per cycle when a read and write operation is overlapped Read operations may be pipelined allowing continuous bus utilization when a master is performing back to back read operations For continuous back to back read or write transfers the maximum bandwidth of the bus is one transfer per cycle Byte enables specify bytes within a word allowing for byte halfword and word transfers as well as unaligned halfword transfers and 3 byte transfers Packing and unpacking of data is performed within each PLB slave All masters and slaves attach to the PLB as 128 bit 64 bit and 32 bit devices Slaves may support 8 bit and 16 bit bus widths if required PLB protocol does not include support for halfword or byte devices All transfer requests for bytes within an aligned word wi
83. le access 11 initializing bus functional models 12 invoking bus functional compiler 12 simulator configuration 11 PLB bus functional language 28 BFM device configuration commands 28 PLB alias commands 28 PLB master commands 29 PLB monitor commands 44 PLB slave commands 38 PLB bus models PLB monitor 26 running 4x bus models in 3x mode 13 PLB bus timing back to back read transfers 52 back to back read write transfers 56 back to back write transfers 54 four word line read followed by four word line write transfers 62 fourword line read transfers 58 fourword line write transfers 60 read transfers 48 transfer abort 51 write transfers 50 PLB compliance checks 64 address map setup error 64 master inferface checks 67 monitor model 64 slave interface checks 75 slave interface PLB core OR logic error 64 timeout handshake checks 86 PLB implementation 4 PLB master commands 29 PLB master designs undertest 9 read write Index 87 PLB master mode 15 PLB master models alu intructions 19 branch intructions 20 burst operations 18 command modes 17 conversion cycles with different PLB device sizes 19 decode unit 16 general purpose register 19 internal master data memory 17 master model operation 16 PLB master mode 15 PLB model toolkit 1 bus functional compiler 11 bus functional language 28 bus models 13 compliance checks 64 features 2 timing 48 PLB model toolkit environment 5 PLB model toolkit testbench 8 PLB monitor 26 PLB slave co
84. ll be transferred on the PLB in one data transfer cycle A PLB master may request a16 byte 32 byte or 64 byte line of data These requests will result in data being transferred to the master in 4 8 or 16 word transfers on the PLB For non line transfers transfer width will match the width of the requested data as indicated by the byte enables PLB slaves provide a read word address SI rdWdAdar allowing bus slaves to fetch line data in any order that is target word first or sequentially All masters are required to sample the word address for line read operations and steer the word to the appropriate location within the line based on the word address from the slave See PLB Architecture specification for more information Sequential burst protocol provides a mechanism for a master to request a burst of word halfword or byte transfers to from any slave Abort signal provides the master the capability to abort a request late in the cycle Guarded and unguarded memory transfers allow a slave device to enable or disable the prefetching of instructions or data Four levels of request priority for each master allow PLB implementations with various arbitration schemes Master may lock bus arbitration allowing for atomic operations Slaves provide error reporting and busy acknowledge to each master on the PLB Version 4 3 PLB Toolkit Overview 3 1 3 PLB Implementation The PLB implementation consists of a PLB core to which all masters and
85. mediate integer value to indicate the number of bit positions to shift the specified register The DST must be RO 31 SR or CR Example shift left R0 1 6 3 17 Shift right Command The Shift right command updates an internal master register with the result of a bit wise Shift right operation between an internal register and an immediate value Each Shift right command executes in one PLB clock cycle DST integer value These two parameters specify the 32 bit internal destination register to be updated and immediate integer value to indicate the number of bit positions to shift the specified register The DST must be RO 31 SR or CR Example shift right RO 1 6 4 PLB Slave Commands The PLB slave commands are categorized into model configuration memory initialization commands bus response commands and memory comparison check commands The model configuration commands are used to characterize the slave model by controlling the way in which it responds to PLB cycles The memory initialization commands are used to set up the slave memory before simulation starts The memory comparison check commands can be used to compare expected data with slave memory data during simulation The bus response commands are used to change the slave bus response parameters such as wait states and termination types 6 4 1 Configure Command The configure command allows the user to configure different PLB model attributes One or more paramet
86. meter specifies whether to assert Mn_busLock with Mn_request If the parameter is not specified then lock is not asserted The PLB will be locked when a valid PLB_MnaddrAck is asserted When using the lock parameter an unlock parameter is required in the same instruction The lock signal is automatically deasserted if a rearbitrate occurs unlock mode enumerated type default cycle This parameter specifies the mode in which lock is deasserted This may be specified as clock mode or cycle mode Clock mode specifies the deassertion of lock as the number of clocks from when lock was previously asserted Cycle mode specifies the number of cycles to expire before lock is deasserted In cycle mode lock is deasserted when Mn_request is deasserted during the last locked cycle e unlock delay integer range 1 to 255 32 Processor Local Bus Functional Model Toolkit Version 4 3 This parameter specifies the number of clocks to deassert lock after it was previously asserted or the number of cycles to elapse before it is deasserted The mode for the deassertion of lock is specified with the previous unlock_mode parameter type 3 bit default 000 This parameter specifies the Mn_type signals of the PLB The valid size combinations are listed in the PLB architecture specifications under transfer qualifier signals The default value is a memory transfer compress 1 bit default 0 This parameter enables the assertion of the
87. mmands 38 PLB slave designs under test 9 PLB slave models burst modes 25 command modes 22 conversion cycles with different PLB device sizes 25 internal slave data memory structure 23 internal slave memory checking 25 operations 22 ordered write cycles 24 pipeline modes 26 PLB slave 21 slave bus command modes 22 PLB toolkit environment bus functional compiler files 5 example test case file 6 read me files 5 verilog files 6 vhdl files 6 vss script files 5 PLB toolkit testbench ieee packages 9 PLB master designs under test 9 PLB slave designs under test 9 programmable PLB data bus width and auto matic replication 8 vhdl signal types 9 processor local bus 88 Processor Local Bus Functional Model Toolkit signals 65 programmable PLB data bus width and automat ic replication 8 R read me files 5 read transfers 48 running 4x bus models in 3x mode 13 S signals processor local bus 65 simulator configuration 11 slave bus command modes 22 slave interface checks 75 slave interface PLB core OR logic error 64 T timeout handshake checks 86 transfer abort 51 V verilog files 6 vhdl files 6 vhdl signal types 9 vss script files 5 Ww write transfers 50 Version 4 3 Version 4 3 International Business Machines Corporation 1996 2000 Printed in the United States of America 5 16 01 All Rights Reserved The information contained in this document is subject to change without notice The products descri
88. n mode Command mode or Auto mode A description of these modes are e Configuration Mode 22 Processor Local Bus Functional Model Toolkit Version 4 3 This response mode allows the user to change the slave read write response on a test case basis For each PLB master cycle that is received the PLB slave model uses an internal configuration register to respond to all PLB read or write memory cycles which are active within its address space This mode is the default configuration of the PLB slave model The configuration delay values can be initialized using configuration commands such as configure read_aack_delay 2 read_dack_delay 2 1 1 1 write_aack_delay 1 write_dack_delay 1 1 1 1 This mode is the default mode of the PLB Slave model and the user is not required to specify a BFL configuration parameter for this mode Command Mode This response mode enables the user to change the slave read write response on a transaction basis For each PLB master cycle that is received the PLB slave model uses a response command from an internal read or write command array when a PLB read or write memory cycle is active within its address space The PLB slave model uses command mode instead of configuration mode when read write response commands are programmed in a test case such as read_response aack_delay 2 dack_delay 3 When the BFC parses response commands it automatically initializes the appropriate internal slave model register to
89. n the PLB bus functional languages are parsed by the toolkit bus functional compiler For VHDL simulators it generates simulator interface commands to initialize the PLB models within the toolkit test bench For Verilog simulators the BFC generates a Verilog initialization file which contains Verilog statements to initialize the bus functional models These command files are used to load the bus functional model command and data arrays after the test bench is loaded into the simulator Multiple bus functional model command sections may be written within the same BFL file or individual BFL files may be used to initialize each master slave device The bus functional compiler will generate a single command file for each BFL file which it processes If more than one BFL file is used for a single test case the user should include each command file generated by the BFC when initializing the bus functional models within the test bench The bus functional compiler is implemented in Perl which is an interpreted language distributed under the GNU public license It is available at no cost and runs on nearly all UNIX or UNIX like operating systems 4 1 Simulator Configuration Since the output of the bus functional compiler is a simulator specific command initialization file the user should indicate the target simulator being used This can be done by changing the default simulator command output parameter at the header of the bus functional compiler Perl p
90. n transfer size Mn_type 0 2 Master n Master n transfer type Mn_wrBurst Master n Master n burst write transfer indicator Mn_wrDBus 0 31 Master n write data bus PLB_abort Arbiter PLB abort bus request indicator PLB_ABus 0 31 Arbiter PLB address bus PLB_BE 0 3 Arbiter PLB byte enables PLB busLock PLB bus lock PLB guarded Arbiter PLB guarded transfer indicator PLB lockErr Arbiter PLB lock error indicator PLB masterID 0 1 Arbiter PLB current master identifier PLB Mn Busy PLB master n slave busy indicator PLB Mn Err Mastern PLB master n slave error indicator PLB Mn WrBTerm Mastern PLB master n terminate write burst indicator PLB Mn WrDAck Mastern PLB master n write data acknowledge PLB MnAddrAck PLB master n address acknowledge Version 4 3 PLB Compliance Checks 65 66 Table 1 Summary of PLB Signals Continued Signal Name Source Description PLB MnRdBTerm PLB master n terminate read burst indicator PLB MnRdDAck Master n PLB master n read data acknowledge Page PLB MnRdDBus 0 31 Master n PLB master n read data bus PLB MnRdWdAdar 0 3 Master n PLB master n read word address PLB MnRearbitrate PLB master n bus rearbitrate indicator PLB PAValid Arbiter PLB primary address valid indicator PLB pendPri 0 1 Arbiter PLB pending reguest priority PLB pendReg Arbiter PLB pending bus reguest indicator PLB rdPrim Arbiter PL
91. nerated and the corresponding error detection bit is set in the PLB device level integer This parameter specifies which synchronization signal to wait for before checking the slave memory data addr 4 byte Version 4 3 PLB Bus Functional Language 43 This parameter specifies the 32 bit address data 4 byte This parameter specifies the slave memory data to check in the corresponding PLB device 6 5 PLB Monitor Commands The PLB Monitor contains registers for address mapping of slave instantiations Some of the monitor protocol checks use the address map to provide accurate messaging and perform the actual protocol checks It is required for the user to set up the Monitor register initializations for the slave address map 6 5 1 Configure Command The configure command allows the user to configure different PLB model attributes One or more parameters can be used with a single configure command and multiple configure commands may be used in a single test case It is important to note that the configure commands are only executed at time 0 in simulation 6 5 1 1 Configuration Parameters enable timeout report This parameter enables the monitor to give an error message specifying that a timeout occurred on the bus SLAVEO ADDR LO 0 4 byte SLAVEO ADDR HI O 4 byte SLAVEO ADDR LO 1 14 byte SLAVEO ADDR HI 1 4 byte Address map range 0 1 for slave instantiation 0 SLAVE1 AD
92. nges this transfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated through Mn_abort or PLB_MnRearbitrate or timeout Error 2 23 2 An error message is issued if this transfer qualifier does not match Mn size when PLB_MnAddrAck is active Error 2 23 3 When PLB_PAValid or PLB_SAValid is active an error message is issued for the following combination of PLB_type and PLB_size values as shown in Table 4 Table 4 PLB_type Values Any of the reserved size codes Any of the reserved size codes or any line size code 010 Codes other than 0000 Codes other than 0000 100 Codes other than 0000 101 Codes other than 0000 110 Any of the reserved size codes 111 Codes other than 0000 Processor Local Bus Functional Model Toolkit Version 4 3 8 7 24 PLB_type The following error messages are issued for this signal Error 2 24 1 An error message is issued when the PLB changes this transfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated through Mn_abort or PLB_MnRearbitrate or timeout Error 2 24 2 An error message is issued if this transfer gualifier does not match Mn type when PLB MnAdarAck is active 8 7 25 PLB TAttribute The following error messages are issued for this signal Error 2 27 1 An error message is issued when the PLB changes this t
93. none of the terminating responses from master or slave have been asserted then a time out has occurred 8 3 Address Map Set up Error An error message is issued when PLB_reset is de asserted and the PLB monitor slave address map has not been initialized 8 4 Slave Interface PLB Core OR Logic Error An error message is issued when the OR ed value of all the PLB slave control outputs does not equal the output of the system OR gates which are inputs to the PLB arbiter 64 Processor Local Bus Functional Model Toolkit Version 4 3 8 5 Signal Summary Table Table 1 provides a summary of all PLB input output signals in alphabetical order which includes the source a brief description and page reference for bus functional compliance checks See PLB architecture specifications for detailed signal description Table 1 Summary of PLB Signals Signal Name Source Description Page Mn_abort Master n Master n abort bus request indicator Mn_ABus 0 31 Master n Master n address bus Mn_BE 0 3 Master n byte enables Mn_busLock Master n Master n bus lock Mn_TAttribute Master n Master n storage attributes Mn_guarded Master n Master n guarded transfer indicator Mn_lockErr Master n lock error indicator Mn_priority 0 1 Master n Master n bus request priority Mn_rdBurst Master n Master n burst read transfer indicator Mn_request Mastern Master n bus request Mn_RNW Master n read write Mn_size 0 3 Master n Master
94. not properly replicated as indicated in the architecture specification for smaller masters connected to larger width PLB Arbiters The following error messages are issued for this signal Error 1 6 1 An error message is issued when a master changes this transfer gualifier from when a reguest to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated via Mn abort PLB MnRearbitrate or Mn Timeout Error 1 6 2 When Mn reguest is active an error message is issued for the following combination of Mn type values as shown in Table 2 and Mn size values as shown in Table 3 Table 2 Mn type Values Mn type Mn size 000 Any of the reserved size codes 001 Any of the reserved size codes or any line size code 010 Codes other than 0000 011 Codes other than 0000 100 Codes other than 0000 101 Codes other than 0000 110 Any of the reserved size codes Table 3 Mn_size Values Mn_size 0 3 Definition 0000 Transfer one to four bytes of a word starting at the target address Transfer the 4 word line containing the target word Transfer the 8 word line containing the target word Transfer the 16 word line containing the target word Reserved Reserved Reserved Reserved Burst Transfer Bytes Length determined by master 1001 Burst Transfer Halfwords Length determined by master Version 4 3 PLB Compliance Checks 69 Table 3 Mn_size
95. ns of PLB master model are shown in Figure 5 Bus Functional Language File CLK Reset Decode Unit Bus Unit Bus Functional Compiler Cycle Info Cycle Queue Queue Info Request Command File Bus Interface Logic Decode Logic Memory Logic Processor Local Bus Timing Filter y O D o E o Memory Address Figure 5 PLB Master Model 5 2 2 Decode Unit The PLB master model executes bus commands from internal command arrays which are loaded from the command file The command file is the file generated by the bus functional compiler When invoking the simulator the command file should be included so that the command arrays are initialized when the simulation model is loaded This is accomplished by using an include file parameter The master commands are executed sequentially during simulation The decode unit is designed to decode and queue external bus requests every PLB clock until the bus unit cycle queue is full 16 Processor Local Bus Functional Model Toolkit Version 4 3 When the decode unit issues a bus request it continues decoding and executing additional instructions from the command memory as long as it is not waiting on an external event An example of an external event would be a synchronization signal In addition a request delay parameter may suspend
96. nsfer is terminated via Mn_abort PLB_MnRearbitrate or Mn_Timeout 8 6 9 Mn lockErr The following error messages are issued for this signal e Error 1 11 1 70 Processor Local Bus Functional Model Toolkit Version 4 3 An error message is issued when a master changes this transfer qualifier from when a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated via Mn_abort PLB MnRearbitrate or Mn_Timeout 8 6 10 Mn ABus Mn UABus The following error messages are issued for this signal e Error 1 12 1 An error message is issued when a master changes these transfer qualifiers from when a request to transfer is made until the addressed slave asserts its Sln_addrAck or the transfer is terminated via Mn_abort PLB_MnRearbitrate or Mn_Timeout e Error 1 12 2 An error message is issued when the Mn_Abus word address is non zero during a line write transfer Error 1 12 3 An error message is issued when the master has a non aligned half word burst address for half word burst transfers when the master has a non aligned word burst address for word burst transfers when the master has a non aligned double word burst address for double word burst transfers when the master has a non aligned quad word burst address for quad word burst transfers e Note1 12 4 An note message is issued when the Mn_Abus word address is non zero during a line write transfer 8 6 11 Mn_abort
97. nsfers Figure 14 shows the operation of a single four word line read from a slave device which is capable of providing data in a single clock cycle Cycle GH an Re ee a aaron SYS plbCik _ Transfer Qualifiers Mn_request Mn_priority 0 1 Mn_busLock Mn_RNW Mn BE 0 3 Mn size 0 3 Mn type 0 2 Mn abort Mn ABus 0 31 ALA2 J PLB PAValid NS Next Wr Avalid Next Rd Avalid SladdrAck Saf NextWrAddrAok Next Rd AdtirAck SI wait q Write Data Bus Mn_wrDBus 0 31 SI wrDAck SI wrComp Mn wrBurst Read Data Bus SI_rdDBus 0 31 0000 Xwz Xx w3 X wol 0000 SI rdWdAdar 0 3 0000 1 0010X 0011 X 0000 4 0001 0000 SI rdDAck SI rdComp Mn rdBurst 7 Figure 14 Four Word Line Read Set device path plb_complex plb_master0 device_type plb_master addr 00000000 data 00010203 addr 00000004 data 04050607 mem_init addr 00000008 data 08090a0b mem_init addr 0000000c data 0c0d0e0f read addr 00000008 size 0001 be 1111 send level 0 mem_init mem_init Set device path plb_complex plb_slave0 device_type plb_slave Initialize device 0 58 Processor Local Bus Functional Model Toolkit Version 4 3 mem_init addr 00000000 data 00010203 mem_init addr 00000004 data 04050607 mem_init addr 00000008 data 08090a0b mem_init addr 0000000c data
98. o the clock after SIn rdComp e Error 1 20 2 An error message is issued if PLB_MnRdDack is asserted during a DMA transfer which requires no rdDAcks 8 6 19 PLB_MnRdWdAdadr 0 3 The following error messages are issued for this signal e Error 1 21 1 An error message is issued when master does not own the read data bus and PLB MnRdWdAddr 0 3 contains non zero data e Error 1 21 2 An error message is issued when PLB MnRdWdAddr 0 3 does not match SI rdWdAdar 0 3 e Error 1 21 3 An error message is issued when PLB MnRdWdAdar 0 3 does not cover all the necessary read word addresses in a line transfer 8 6 20 PLB_MnBusy The following error messages are issued for this signal Error 1 22 1 An error message is issued when PLB MnBusy is not active during a read transaction with slave Error 1 22 2 An error message is issued when PLB_MnBusy is not active during a write transaction with slave 8 6 21 PLB MRdErr PLB MWrErr Error 1 23 1 An error message is issued when these signals are asserted without a PLB_Mrd wrDack or without a busy signal 8 6 22 PLB MSSize Error 1 24 1 An error message is issued when PLB Arbiter core did not propagate SI Ssize to master when SI addrAck was asserted 74 Processor Local Bus Functional Model Toolkit Version 4 3 8 6 23 PLB_MnTimeout The following error messages are issued for this signal Error 1 25 1 An error message is issued when this signal is active and the PLB_mas
99. onal model toolkit provides unit and system level simulation and verification of ASICs and logic designs which comply with PLB architecture specifications The toolkit enables the designer to accelerate the design cycle time by identifying and addressing possible problems at an earlier stage of the design cycle The processor local bus PLB is designed to interface directly with the processor cores The primary goal of the PLB is to provide a standard interface between the processor cores and integrated bus controllers such that a library of processor cores and bus controllers can be developed for use in the Core ASIC development The PLB model toolkit facilitates unit and subsystem level simulation of logic designs which comply with the PLB architecture See the PLB architecture specifications for more information Figure 1 demonstrates how the processor local bus is inter connected for the purpose of Core ASIC development or system on a chip design OPB Arbiter Data Instruction DMA PLB to OPB OPB to PLB Cache Unit Cache Unit Controller Bridge Bridge Processor Core DCR Bus OPB Master DCR Bus Processor Local Bus On Chip Peripheral Bus Internal Peripheral DCR Bus External Peripheral Controller Memory Controller SRAM External External SDRAM ROM Peripheral Bus Master Controller Figure 1 Processor Local Bus Interconnection
100. or 2 15 2 An error message is issued when SIn_rdWdAddr 0 3 is not aligned for line transfer 8 7 16 Sin rdDAck The following error messages are issued for this signal Error 2 16 1 An error message is issued when SIn_rdDAck is asserted outside of the window from two clocks after the assertion of Sin addrAck to one clock after the assertion of SIn rdComp Error 2 16 2 An error message is issued when on a non burst read transfer the slave fails to give the expected number of rdDAcks Error 2 16 3 An error message is issued when this signal is asserted during a DMA type 1 4 5 7 cycle from two clocks after Sin addrack until one clock after Sin rdComp is asserted Error 2 16 4 An error message is issued when this signal is asserted for a transfer that is outside of the slave s assigned address space Error 2 16 5 An error message is issued when this signal is asserted more than once after the rdburst signal has been deasserted for a read burst transfer 8 7 17 Sin rdComp The following error messages are issued for this signal Error 2 17 1 An error message is issued when Sin rdComp is active outside of allowed window from the cycle after slave asserts its Sln addrAck to the cycle it asserts its Sin rdComp Error 2 17 4 An error message is issued when more than one slave asserts Sin rdComp in the same clock Error 2 17 5 An error message is issued when this signal is asserted before a variable length burst transaction
101. parameter specifies the address incrementation order for the slave during line transfers The valid modes are sequential and target word first If this parameter is used in the configuration statement of the slave the rdWord mode response parameter will be ignored burst term 32 bits or integer default 0 This parameter specifies the internal burst address or data acknowledge cycle to assert SI rdBTerm or SI wrBTerm signal If the slave is configured in burst address terminate mode a 32 bit address should be specified otherwise the cycle integer should be specified MErr integer default 0 This parameter specifies the data transfer to assert the SI MErr signal If 0 SI MErr is not asserted Note that only one MErr assertion per response including line burst transfers command is possible MErr delay integer default 0 This parameter specifies the number of clocks to wait before asserting the SI MErr signal after the slave data acknowledge signal is asserted e SSize 2 bit This parameter specifies the SIn SSize signals of the PLB The valid size combinations are listed in the PLB architecture specifications Note that this parameter will be ignored if the SSize parameter was previously defined as a configuration parameter 6 4 4 Mem Check Command The mem_check command automatically compares slave memory with the specified comparison data If there is a data comparison error an error message is ge
102. parameters specify the range for burst term delay during read cycles when slave auto mode is true The model automatically assigns a random delay to the burst term delay between and including the minimum and maximum values e write burst term min max integer default 7 10 These parameters specify the range for burst term delay during write cycles when slave auto mode is true The model automatically assigns a random delay to the burst term delay between and including the minimum and maximum values 6 4 1 3 Automatic Data Mode Configuration Parameters slave auto data boolean default false Version 4 3 PLB Bus Functional Language 41 This parameter specifies whether the PLB slave behavior should automatically generate data When the slave model is configured for automatic data mode there is no need to initialize internal memory data since it is generated and checked using the BFM data generation function described in PLB Bus Functional Compiler on page 11 root seed integer default 1 This parameter specifies the seed to be used for the auto data feature of the model The slave model forms a seed using this root_seed and the byte address The user may change the initial seed to change the random number sequences which are generated which in turn will produce varying slave data 6 4 2 Mem Init Command The mem init command initializes slave memory at simulation time 0 addr 4 byte This parameter spe
103. r reguests when master auto mode is enabled unlock delay min max integer default 1 50 Processor Local Bus Functional Model Toolkit Version 4 3 These parameters specify the range for unlock_delay when master_auto_mode is true The model automatically assigns a random value to the unlock_delay between and including the minimum and maximum values when the lock delay parameter is selected This parameter is generated for approximately 1 out of every five cycles when master_auto_mode is enabled Msize_min max integer default 0 1 These parameters specify the range for Msize when master_auto_mode is true The model automatically assigns a random value to the Msize between and including the minimum and maximum values If the Msize parameter is also specified in a configure statement for the same master the minimum and maximum values will not be used even if the master is configured for auto_mode size_min max integer default 0 6 These parameters specify the range for size when master auto mode is true The model automatically assigns a random value to size between and including the minimum and maximum values burst_count_min max integer default 1 32 These parameters specify the range for burst_count when master_auto_mode is true and the size equals a burst transfer The model automatically assigns a random value to burst_count between and including the minimum and maximum values 6 3 1 3 Automatic Data Mode
104. rameters slave auto mode boolean default false This parameter specifies whether the PLB slave behavior should automatically respond to bus cycles with varied acknowledge delays and termination types The valid parameter types are true and false When the slave model is configured for automatic mode there is no need to initialize read write response commands since they are ignored while auto mode is enabled seed integer default 1 This parameter specifies the seed to be used for the random features of the model The slave model currently uses a uniform distribution function implemented with exclusive or algorithms to produce random values for parameters which are varied by the model when configured in automatic mode The user may change the initial seed to change the random number sequences which are generated which in turn will produce varying slave response sequences by the model e slave_addr_LO_x 32 bit slave addr HI x 32 bit These parameters allow a user to override the default generic address decode parameters for the PLB device slaves The user may provide up to two non contiguous address ranges for the same slave by changing the x from 0 to 1 If more non contiguous slaves address ranges are necessary the user may instantiate additional PLB device models in the test bench It is important that there are no overlapping memory address areas between multiple slaves since both slaves would attempt to r
105. ransfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated via Mn_abort PLB MnRearbitrate or PLB MnTimeout Error 2 27 2 An error message is issued if this transfer qualifier does not match Mn_TAttribute when PLB_MnAddrAck is active 8 7 26 PLB_lockErr The following error messages are issued for this signal Error 2 28 1 An error message is issued when the PLB changes this transfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated through Mn_abort or PLB MnRearbitrate or Timeout Error 2 28 2 An error message is issued if this transfer qualifier does not match Mn_lockError when PLB MnAdarAck is active 8 7 27 PLB ABus PLB UAbus The following error messages are issued for this signal Error 2 29 1 An error message is issued when the PLB changes this transfer qualifier from the time a request to transfer is made until the addressed slave asserts its Sin addrAck or the transfer is terminated through Mn_abort or PLB_MnRearbitrate or timeout Error 2 29 2 Version 4 3 PLB Compliance Checks 83 An error message is issued if this transfer qualifier does not match Mn_ABus when PLB MnAdarAck is active Error 2 29 3 An error message is issued when the PLB Abus word address is non zero during a line write transfer 8 7 28 PLB busLock The following error m
106. rchitecture specifications e VHDL and verilog source model solutions with simulator independence e Bus functional command definition which generates and responds to different transaction types with varying delays e Bus functional compiler which generates model initialization files from bus functional commands e Bus protocol checking through the use of general purpose bus monitors Read and write data checking in masters and slaves e Model inter communication bus for event and transaction synchronization Enables peripheral developers to verify and debug designs to assure bus compliance e Faster simulation run times than PPC BFM or FFM to generate bus traffic e Allows what if simulation scenarios using different master and slave configurations e Flexible and user friendly bus functional language BFL for quick generation of a variety of bus transactions e Hierarchical solution to verification Who Should Use This Book This book is for hardware software and application developers who need to understand Core ASIC development and system on a chip SOC designs The audience should understand embedded system design operating systems and the principles of computer organization Since the PLB model toolkit is designed to comply with the architectural specification toolkit users need to have a working level understanding of the architectural specification to be able to develop test cases and simulate using the bus mo
107. rdDAck A DAck delay value of 0 for a write response causes the SI wrDAck signal to be asserted together with the SI addrAck assertion which is the earliest legal PLB slave data response time for the first SI wrDAck comp delay integer default 0 42 Processor Local Bus Functional Model Toolkit Version 4 3 This parameter specifies the number of clocks to wait before asserting the SI rdComp or SI wrComp signals relative to the last SI rdDAck or SI wrDAck For reads a value of 0 will cause SI rdComp to be asserted 1 clock before the last SI rdDAck For writes a value of O will cause SI wrComp to be asserted together with the last SI wrDAck A non zero value will cause a per clock assertion delay relative to the fastest possible assertion time s wait delay z integer range 0 to 255 This parameter specifies the number of clocks to wait before SI wait is asserted with respect to the assertion of PLB PAValid or PLB SAValid If the parameter is not specified and wait disable is 0 SI wait is asserted whenever the PLB_ABus is within the slave address range unwait z integer default 0 This parameter specifies the number of clocks to wait before deasserting the SI wait signal from the clock that SI wait was previously asserted The SI wait signal is automatically deasserted if an abort or rearbitrate occurs or ifthe PLB_ABus is outside the slave address range e rdWord mode 1 bit O seguential 1 target word first This
108. rent memory look up algorithms used to access the internal memory arrays fully associative and direct mapped Each of these is described below Fully associative linear search look up mode The default mode for the PLB slave model is linear search mode This algorithm provides the flexibility to initialize the slave model with many non contiguous data patterns within an entire 64 bit address range In the linear look up mode each array element status is maintained by the slave Initialization with mem_init commands causes the valid bit to be set Any bus cycles which have an address that matches a valid entry in the memory array will use the memory array for the bus functional command operation For write cycles the internal master data memory will be updated when SI wrDAck is asserted For read cycles data from the internal slave memory is loaded into a buffer one clock before SI rdDAck assertion Direct mapped mode When the PLB slave model is programmed in direct mapped mode a subfield of the address PLB_Abus is used to directly reference the PLB slave internal memory The direct mapped mode is useful when simulations contain many contiguous slave address as the lookup algorithm is more efficient than the linear search mode Note The internal slave address subfield is automatically calculated by the model as the slave memory configuration parameters are set in the plb_dcl vhd file The user is not required to configure these indices
109. rogram The name of this variable is target_simulator Note The BFC will not compile a bfl file if it is not configured properly 4 2 Declarations File Access The PLB slave model provided with this toolkit supports more than one internal memory lookup algorithm In addition the model memory sizes can be configured by updating the declarations file plb_dcl vhd v This is described in more detail in Master Model Operation on page 16 and Slave Model Operation on page 22 Since the memory initialization statements are generated from the BFC when parsing the bus functional language memory initialization constructs the BFC needs to know the memory configuration parameters before it generates the simulator specific initialization files Therefore the BFC reads the plb_dcl vhd v file before it processes a test case to determine the memory configuration parameters Note If the BFC file is not executed from the same directory where the plb dcl vhd v file resides the user must update the plb dcl path at the header of the BFC file An error message is generated if the declarations file is not found Version 4 3 PLB Bus Functional Compiler 11 4 3 Invoking the Bus Functional Compiler The bus functional compiler operates on files with the extension bfI and it generates a file with the same name but with a cmd or do or v extension depending on the target simulator If the bfl extension is omitted the cm
110. ror 2 4 1 An error message is issued when Sin wait is active while the slave is not selected This check depends on user defined address map Error 2 4 2 An error message is issued when more than one slave asserts Sin wait in the same clock 8 7 5 Sin rearbitrate The following error messages are issued for this signal 76 Processor Local Bus Functional Model Toolkit Version 4 3 Error 2 5 1 An error message is issued when Sin rearbitrate is asserted and both PLB_PAValid and PLB SAValid are inactive Error 2 5 2 An error message is issued when Sin_rearbitrate is active while the slave is not selected This check depends on user defined address map Error 2 5 3 A warning message is issued when Sin rearbitrate is asserted and PLB SAValid is active Not applicable to PLB 4 x Error 2 5 4 An error message is issued when more than one slave asserts Sin rearbitrate in the same clock 8 7 6 PLB rd wrpendReg The following error messages are issued for this signal Error 2 6 1 3 An error message is issued when the PLB changes this transfer gualifier from the time when a reguest to transfer is made until the addressed slave asserts its Sln addrAck or the transfer is terminated through Mn abort PLB MnRearbitrate or PLB MnTimeout Error 2 6 2 4 An error message is issued if this signal is active when there is no Mn_request 8 7 7 PLB_MasterlD 0 3 The following error messages are issued for this signal Error
111. rs master auto mode boolean default false Version 4 3 PLB Bus Functional Language 29 This parameter specifies whether the PLB master behavior should automatically generate random bus requests When the master model is configured for automatic mode there is no need to initialize read write commands since they are ignored while the bus cycle generation is enabled auto_max_cycle integer default 0 This parameter specifies the maximum number of cycles that will be generated automatically and complete on the bus If the default value of 0 is used cycles will be produced until the simulation is interrupted stopped auto_synch_level integer default none This parameter specifies the level on the synch bus that will be asserted when the maximum number of automatically generated cycles on the bus have completed The maximum number of automatically generated cycles is determined by the auto_max_cycle value seed integer default 1 This parameter specifies the seed to be used for the random features of the model The master model currently uses uniform distribution functions implemented with exclusive or algorithms to produce random values for parameters which are changed by the model when configured to automatic mode The user may change the initial seed to meet the random number sequences which are generated which in turn will produce various master read and write sequences by the model master_addr_LO_x 3
112. s Functional Language on page 28 The master model has the ability to issue requests for the bus and generate cycles and the slave model can be initialized to decode PLB bus cycles and respond to PLB master requests Both the master and slave models may be initialized to perform different PLB cycles with programmable signal delays The master and slave models support multiple modes of data operation The default mode for the models is to source data from internal data memories which are initialized at model load time The initialization data is specified through the BFM user interface The user has the ability to modify the internal memory contents during simulation through the use of bus functional commands described in PLB Bus Functional Language on page 28 Another data mode which is provided in the PLB toolkit is auto data When the master and or slave models are configured for this mode data is automatically generated and checked as bus transactions are processed in simulation When the master and slave models are ready to drive data on the PLB bus they call a pseudo random number generator to form the necessary data patterns When data is received by the master and slave models they call the same pseudo random number generator to create expect data which is used to compare with the data received from the bus The source and receive data is synchronized through the formation of a deterministic seed produced with a root seed and the addres
113. s of each byte of data To produce the source and expect data the models use an addition function for the root seed and address which produces a unique seed for each byte of data The root_seed is typically varied by the user on a test case basis The PLB Bus Model can be configured to run with a 64 bit and a 128 bit data bus width It is important to note that the 4X version of the toolkit will not work with a 32 bit data bus width configuration For applications requiring a 32 bit data bus width there are two options PLB3X can be used and configured for 32 bits or PLB4X can be used with manipulated assignments to all unused portions of the 64 bit data connection and 8 bit byte enable connection Another option provided by the 4X toolkit is the ability to run in 3X mode This means that the toolkit will run with the functionality and signals from 3X but will have the additional monitor checks and toolkit enhancements that have been added to the 4X version This configuration is possible through the use of 3X wrappers These wrappers allow the user to instantiate 3X devices using the 4X toolkit without having to connect all of the additional 4X signals Please see the section titled Running in 4X Bus Models in 3X Mode for more configuration information The PLB monitor model receives all PLB core signals in the PLB test bench environment It performs bus protocol checking for arbitration and data transfers Error detection is reported to t
114. slaves are attached The logic within the PLB core consists of a central bus arbiter and the necessary bus control and gating logic The PLB architecture supports up to sixteen master devices However PLB core implementations supporting less than sixteen masters are allowed The PLB architecture also supports any number of slave devices However it should be noted that the number of masters and slaves attached to a PLB core in a particular system will directly affect the performance of the PLB core in that system Figure 2 shows an example of the PLB connections for a system with three masters and three slaves me y Central Bus Arbiter y Arbitration BLE Slaves Address Address amp Transfer amp Transfer 1 Qualifiers Qualifiers 1 i i pa Bus ke es a Control Saja S 4 us amp Gating US a Logic Di GI o Control Control Tm o gt Read J Data lt a Read Bus o 4 Data ore PLB i Bus M asters Status amp Status amp Control Contro B Processor Local Bus Functional Model Toolkit Figure 2 Physical Implementation of the PLB Version 4 3 Chapter 2 PLB Toolkit Environment The PLB toolkit consists of a test bench bus functional models and a bus functional compiler The test bench instantiates the bus models a reference PLB core and design s under test The toolkit is intended to provide users with an
115. ssible combination of assertions for the entire set of burst transactions 5 3 8 Conversion Cycles with Different PLB Device Sizes The PLB slave model can be configured to be a 32 bit 64 bit or 128 bit device When the PLB slave model asserts Sln AddrAck with a PLB MSize which represents a master that is smaller than the configured PLB slave size Sin SSize 0 1 the PLB slave will automatically adjust the data bus access and internal memory access to correspond to the transaction size as indicated by the PLB MSize and SI SSize values during the SI addrAck assertion For example if a 32 bit PLB master initiates a 4 word read line transfer to a 64 bit slave the slave will drive 4 SI rdDack signals and drive bits 0 31 of the SI rdDBus However if a 64 bit PLB master initiates a 4 word read line transfer to a 64 bit slave the slave will drive 2 SI rdDAck signals and drive bits 0 63 of the SI rdDBus To configure data bus size of the PLB slave model use the following command configure SSize xx Version 4 3 PLB Bus Models 25 where xx is 00 for a 32 bit device 01 for a 64 bit device or 10 for a 128 bit device 5 3 9 Pipeline Modes The PLB slave model samples PLB_SAValid to detect the occurrence of pipelined address cycles on the PLB From a test case the user may selectively disable read or write address pipelining in the PLB slave model by setting the read write_addr_pipeline_mode parameters For example
116. te addr 00021000 size 0000 be 1111 aack_delay 4 dack_delay 3 write addr 00021004 size 0000 be 1111 aack_delay 3 dack delay 3 write addr 00021008 size 0000 be 1111 aack_delay 2 dack delay 3 write addr 0002100C size 0000 be 1111 aack delay 1 dack delay 3 read addr 00021000 size 0000 be 1111 aack_delay 4 dack delay 2 read addr 00021004 size 0000 be 1111 aack_delay 3 dack delay 2 read addr 00021008 size 0000 be 1111 aack_delay 2 dack delay 2 read addr 0002100C size 0000 be 1111 aack_delay 1 dack delay 2 Version 4 3 PLB Bus Functional Language 47 Chapter 7 PLB Bus Timing This section on PLB timing provides various examples with timing diagrams consistent with PLB architecture specifications 7 1 Read Transfers Figure 8 shows the operation of a single read data transfer on the PLB Cycle Ha Ke ENE NU A Transfer Qualifiers Mn reguest ij Mn priority 0 1 valid Y Mn_busLock Mn RNW NE 1 Mn BE 0 3 1111 Mn_size 0 3 Mn type 0 2 000 Mn abort Bz Mn_ABus 0 31 h PLB PAValid m Next Wi Avalidi Next Rd Avalid SI wait To SI AddrAck Write Data Bus Mn wrDBus 0 31 SI wrDAck SI wrComp Mn_wrBurst Read Data Bus SI_rdDBus 0 31 0000 X D AO 0000 SI rdWdAddr 0 3 0000 OE 00 SI rdDAck E SI rdComp Mn rdBurst Figure 8
117. ter model command array The PLB arbiter determines which master bus cycle to issue on the slave side of the PLB bus Figure 4 demonstrates all PLB master interface input output signals See PLB architecture specifications for detailed functional description of the signals PLB Bus Master Interface Synch in gt PLB_MnAddrAck PLB_MnRearbitrate PLB MnSSize 0 1 PLB MnBusy gt PLB_MnErr gt Synch out Mn reguest Mn_priority 0 1 4 Mn busLock Mn RNW Request Qualifiers Mn BE 0 3 bi Mn size 0 3 Mn type 0 2 Mn MSize 01 w Mn compress Mn guarded Mn ordered lt 4 Mn_lockErr Mn_abort Mn ABus 0 31 PLB_MnWrDAck gt PLB MnWrBTerm 4 Mn wrBurst Write Data Bus 4 Mn wrDBus 0 31 Mn wrDBus 32 63 PLB MnRdAck PLB MnRdBTerm PLB MnRdWdAddr 0 3 Read Data Bus PLB MnRdDBus 0 31 gt Mn rdBurst Figure 4 PLB Master Interface Version 4 3 PLB Bus Models 15 5 2 1 Master Model Operation The PLB master model operation section discusses the decode unit internal master data memory command modes burst modes conversion cycles with different PLB device sizes general purpose registers and ALU instructions and branch instructions The operatio
118. terface logic to maintain the status of memory array elements The valid bit is set during model initialization for each memory entry used and also during simulation when a memory entry is allocated in the case of a write memory access miss When a write command reloads a memory entry with bus data the dirty bit is set This Version 4 3 PLB Bus Models 23 may be used with test environments to check that bus commands are executed and master memory is updated in addition to data miscompares For each byte that is written to the slave memory array during simulation of PLB write cycles to the slave the PLB_slave_dirty_array is updated to indicate that the corresponding byte has been updated This feature can be used in simulation environments which need to detect or count exactly which bytes were written to in the slave so that a more comprehensive checking algorithm may be implemented In addition there are two integer variables within the slave memory process which accumulate the total number of bytes which have been read from the slave memory array and also the total number of bytes which have been written to the array These two variables are called slave mem total bytes written slave mem total bytes read The default size of the slave memory array is 64k bytes This may be increased or decreased by updating the PLB slave mem array size parameter in the PLB DCL declaration HDL file of the toolkit The PLB slave model supports two diffe
119. terlD identifies a different master as granted Error 1 25 2 An error message is issued when this signal is active and the corresponding Mn_request is inactive Error 1 25 3 An error message is issued when this signal is asserted by PLB during a secondary request Error 1 25 4 An error message is issued when this signal is asserted in the same clock as PLB MnAddrAck Error 1 25 5 An error message is generated if the PLB Arbiter asserts address acknowledge during a secondary request Error 1 25 6 If enable_timeout_report is true then an error message will be issued whenever a timeout is received This error can be turned on through monitor bfl but it defaults to being turned off 8 7 Slave Interface Checks This section describes the PLB slave interface checks performed during simulation 8 7 1 PLB PAValid The following error messages are issued for this signal Error 2 1 1 An error message will be issued if PLB PAValid is deasserted without a valid termination of the request by either Sin addrAck Sin rearbitrate Mn abort or PLB MnTimeout Error 2 1 2 An error message is issued if PLB PAValid is active and PLB rd wrpendReg is inactive Error 2 1 3 An error message is issued when PLB PAValid is active and SYS plbReset is active 8 7 2 PLB SAValid The following error messages are issued for this signal Error 2 2 1 Version 4 3 PLB Compliance Checks 75 An error message will be issued if PLB_SAValid is d
120. the decode unit issuance of commands to the bus unit until an internal command delay counter has expired The default size of the bus command array is 1024 entries This may be increased or decreased by updating the PLB_Master_CMD_Array_Size constant in the declarations HDL file of the toolkit 5 2 3 Internal Master Data Memory The PLB master model contains an internal memory array which can be initialized by the user with mem_init bus functional commands Each entry of the memory array is maintained by the master model during simulation During this initialization with mem_init commands a valid bit is set for each address entry Any bus functional commands which specify an address that matches a valid entry in the memory array will use the memory array for the bus functional command operation The data used in mem_init statements provides the expect data that is used for the read data comparison checks within the master model It also provides the data used during a write transfer to a memory address For write cycles the internal master data memory will be used as source data when the bus functional command address matches the command array For read cycles the data which is received from the PLB bus will automatically be compared with the internal master data memory Error messages will be generated when data miscompares occur Only the valid bytes for a particular command will be checked The valid bytes are determined by the transfer size as
121. tion Also the bus functional models may be instantiated in other test bench environments which include designs under test PLB Monitor Processor Local Bus Core Figure 3 PLB Toolkit Testbench pib complex vhd v 3 1 Programmable PLB Data Bus Width and Automatic Replication The PLB toolkit test bench uses a constant called PLB_DATA_BUS_WIDTH in declaring the actual PLB arbiter data bus signals This constant defaults to 128 for the PLB 4 x toolkit but may be changed to be 64 or 32 for other PLB arbiter implementations The toolkit will automatically scale the model I O s and bus operations based on the PLB DATA BUS WIDTH constant In addition to programmable arbiter data bus widths the PLB Test Bench contains logic to automatically perform the necessary Byte Enable BE and Data Bus replication as described by the PLB 4 x Bus Architecture specification This replication is performed when necessary as smaller PLB masters and Slaves are connected to a wider data path PLB Arbiter The master BE s and write data bus wrDbus are replicated to the arbiter and the slave read data bus rdDbus is also replicated to the arbiter when necessary The test bench uses the msize ssize signals from the masters and slave together with other bus control signals to automatically generate a mirror signal 8 Processor Local Bus Functional Model Toolkit Version 4 3 3 2 Instantiating PLB Slave Designs Under Test When instantiating a
122. ued for this signal Error 1 15 1 Mn RdBurst and PLB RESET are active at the same time ERROR 1 15 2 Master asserted Mn rdBurst before AddrAck was received Error 1 15 3 Master failed to deassert its Mn rdBurst after receiving PLB MnRdBTerm Error 1 15 4 Master reasserted Mn rdBurst before the current burst transfer received it last DAck Error 1 15 5 An error message is issued if a master terminates a read burst transfer by deasserting its Mn rdBurst and then reasserts its Mn rdBurst signal before the last rdDAck for a multi burst read transfer is terminated 8 6 14 Mn wrBurst The following error messages are issued for this signal 72 Error 1 16 1 An error message is issued when a master terminates a write burst transfer by deasserting its Mn wrBurst and re asserts its Mn wrBurst before receiving the last wrDAck Error 1 16 2 An error message is issued if Mn WrBurst is active in the cycle after PLB MWrBTerm is asserted Error 1 16 3 An error message is issued if Mn WrBurst is asserted without a valid burst reguest as indicated by Mn size Processor Local Bus Functional Model Toolkit Version 4 3 Error 1 16 4 An error message is issued when Mn_WrBurst is active and SYS plbReset is active 8 6 15 PLB_MnAddrAck The following error messages are issued for this signal Error 1 17 1 An error message is issued when this signal is active and the corresponding Mn_request is inactive Error 1 17 2 An error m
123. us lt also contains an internal master memory plb_slave_comp vhd plb_slave_comp v This HDL file represents a PLB slave device lt contains interface with the PLB bus and also an internal memory plb monitor comp vhd plb_monitor_comp v This HDL file performs PLB cycle monitoring and protocol checking plb master vhd plb_master v This HDL file is a wrapper for the PLB master component which is instantiated in this file Users should instantiate this entity in test fixtures which include the PLB model toolkit master model plb_slave vhd plb_slave v This HDL file is a wrapper for the PLB slave component which is instantiated in this file Users should instantiate this entity in test fixtures which include the PLB model toolkit slave model plb_monitor vhd plb_monitor v 6 Processor Local Bus Functional Model Toolkit Version 4 3 This HDL file is a wrapper for the PLB monitor component which is instantiated in this file Users should instantiate this entity in test fixtures which include the PLB model toolkit monitor model It is recommended that all simulations use the PLB monitor to ensure PLB compliance plb_master3x vhd plb_master3x v This HDL file is a compatibility mode wrapper for the PLB master component which is instantiated in this file Users should instantiate this entity in test fixtures which include the PLB model toolkit master model being used with 3 x PLB Architecture arbiter designs plb_slave
124. vie lentes 70 MRS IOCKE M rinne at a ad ty ale a ira ash Mares Bata MAJE dea 70 Mn ABuUS Mn UABUS sec 2 cd o s acted tot 71 Min abo zni sise cee Poa Deeb Goeth GE AE NE lah lei hea ees k 71 Mn_wrDBus 0 PLB DATA BUS WIDTH 0 0 00 71 MneTdBUFSt sis titis adiante bedded eke kel ed a needs 72 Min WIBUISU tie eS ei beat ba catenin tbl ede ee tanda ma KAN NN o 72 PEB MnAGGrAck 28 8 tes a e an AA E Uk Be e ae e Ce a 73 PLB MnRearbitrates lt 25 ceca A EA A DRA BAS els ES 73 PLBMOWIDAEK 003400 ANA tt A mes ne oa ENE OO E A 73 PEB MARADACK aaite a al paa o hbo es 74 PLB MA RAWAAdAHO 3 sevi dd a tada 74 PEB MABUSY coa pan a al aa na REE pad Bea Te aa eee een 74 PLB MRdErr PLB_MWrEtr 0 00 ee ee ee eee eee 74 PLB MSSiZ6 concibe ao dde ge elites fade 74 PEB MATIMSOUL 2 23 ee eae A A et ee el x Aes Se 75 Slave Interface Checks anna 75 Version 4 3 Contents vii PLB PAValld S Siter bana opie hdd sa nan Kanaan ba is 75 PEB SAV ali d2 it Sela a na HN SNN ANA Sean Sao al Scheel ate lad eS 75 Sinsadd Aek Me ia ae eas aan Oe aa ana an sate nang gn tht Les 76 SI MA na Sp a O O A nana USA eases 76 Sin re arbitrales PA a ed A A BRA NN AAN Sana 76 PLB rd wrpend Rege bhi rodar coral rap o 77 PLB MasterID 03 Ab haere haa Re RN BB ema ka Nata RAN NG 77 PLB rd wrpendPri O 1 22 22a desk eke a iaa E a vee pad eee bee eee ee 77 PEB reg P O rere e RA BAN A Ban DNA 78 PEB WrDBUS sa i 05 ot rt nd pe Peed
125. ype plb master mem init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init addr 0000000c data 0c0d0e0f mem init addr lt 00000010 data 10111213 mem init addr lt 00000014 data 14151617 mem init addr lt 00000018 data 18191a1b 62 Processor Local Bus Functional Model Toolkit Version 4 3 mem_init addr 0000001c data 1c1d1e1f read addr 00000000 size 0001 be 1111 write addr 00000010 size 0001 be 1111 send level 0 set device path plb_complex plb_slave0 device_type plb_slave mem init addr 00000000 data 00010203 mem init addr 00000004 data 04050607 mem init addr 00000008 data 08090a0b mem init addr 0000000c data 0c0d0e0f mem init addr lt 00000010 data 10111213 mem init addr 00000014 data 14151617 mem init addr lt 00000018 data 18191a1b mem init addr lt 0000001c data 1c1d1e1f write response aack delay 0 dack delay 0 read response aack delay 0 dack delay 0 mem_check level 0 addr 00000000 data 00010203 mem_check level 0 addr 00000004 data 04050607 mem_check level 0 addr 00000008 data 08090a0b mem_check level 0 addr 0000000c data 0c0d0e0f mem_check level 0 addr 00000010 data 10111213 mem_check level 0 addr 00000014 data 14151 617 mem_check level 0 addr 00000018 data 18191a1b mem_check level 0 addr 0000001c data 1c1d1e1f Version 4 3 Initialize device O PLB Bus Timing 63 Chapter 8 PLB Compliance Checks 8 1 Monitor Model The PLB monitor mo

Processor Local Bus Functional Model Toolkit User`s Manual

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