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PCI-6202

1. ST Figure 4 3 FIFO Data In Out Structure DMA transfers data according to channel order Figure 4 4 shows DA channel 0 to channel 3 data while channel 2 is dis abled DA Channel 0 DA Channel 1 DA Channel 2 DA Channel 3 Figure 4 4 Waveform Generation for Three Channels Update With hardware based waveform generation D A conversions are updated automatically by the FPGA rather than by the application software Compare with the conventional software based waveform generation the precise hardware timing con trol guarantees non distorted waveform generation even when the host CPU is under heavy loading NOTE When using waveform generation mode all four DACs must be configured in a single mode However any indi vidual DAC can be disabled Output Switch There is an onboard output switch between the DACs and DUC device under control Each DAC has an output switch When DUC is ready but the controller PC is not or in start up process the PCI 6202 is in unknown status and the DAC output may not be stable The DUC may malfunction or get damaged when it receives an unknown signal In order to prevent this the output switch isolates the DUC from the DAC signals Operation Theory 19 ADLINK PN Photo MOS switch The default switch setting is OFF but this can be programmed via the software application Using the Multiplying Characteristic of DACs The PCI 6202 supports a maximum 10V voltage outpu
2. ADLINK PN Basic Timer Counter Functions Each timer counter has three inputs that can be controlled via hardware or software applications They are clock input GPTC CLK gate input GPTC GATE and up down control input GPTC UD The GPTC_CLK input provides a clock source input to the timer counter Active edges on the GPTC_CLK input make the counter increment or decrement The GPTC UD input controls the counter to count up or down high count up low count down while the GPTC GATE input is a control signal which acts as a counter enable or a counter trigger signal under different applications The GPTC_OUT will then generate a pulse signal based on which timer counter mode you have set All input output signals polarities can be programmed by soft ware application For brevity all GPTC CLK GPTC GATE and GPTC OUT in the following illustrations are assumed to be active high or rising edge triggered General Purpose Timer Counter modes Ten programmable timer counter modes are provided All modes start operating following a software start signal that is set by the software The GPTC software reset initializes the status of the counter and reloads the initial value to the counter The operation remains halted until the software start is executed again The operating theories under different modes are described in the following sections Mode1 Simple Edge Counting In this mode the counter counts the number of pulses on th
3. 1 Figure 4 18 Mode 7 Operation Mode 8 Continuous Gated Pulse Generation This mode generates periodic pulses with programmable pulse interval and pulse width following the software start GPTC GATE is use to enable disable counting When GPTC GATE is inactive the counter halts the current count value Figure 4 19 illustrates the generation of two pulses with a pulse delay of four and a pulse width of three Software start me Lu GEK PULL Count value 4 1 1 2 1 0 3 1 0 2 3 1 0 9 11 0 um E a A ee See Figure 4 19 Mode 8 Operation Operation Theory A ADLINK BA OGY INC Mode 9 Edge Separation Measurement Measures the time differentiation between two different pulse signals The first pulse signal is connected to GPTC_GATE and the second signal is connected to GPTC AUX It counts the clocks that pass by between the rising edge signal of two different pulses through the 40MHz internal clock or external clock You can calculate the time period via the known clock frequency The maximum counting width is 32 bit Figure 4 20 illustrates how the counter value decreases in Edge Separation Measurement mode Software start Gate i i 1 AUX CLK 1 Count value ha 1 13 11 10 9 E 7 1 3 1 2 4 TE EG 4 1 Figure 4 20 Mode 9 Operation Mode 10 PWM Output Aside from the 4 CH dedicated PWM outputs the card s pow erful timer counter can also simulate a PWM Pulse Width Modulation output By setting varying numb
4. 34 68 Table 4 6 Encoder Pins in CN2 Operation Theory A ADLINK Encoder Isolation Input Module Figure 4 22 illustrates the encoder isolation phase A phase B and phase Z inputs module with 2500 Vrms protection Internal logic Power Encoder phase A phase B phase Z Input Y 470 ohm Resistor Internal Signal to FPGA Encoder phase A phase B phase Z Input p Internal Ground Figure 4 22 Encoder Isolation Input Module The Encoder OGRx input is different from the encoder phase input since you need to add an external 24V power to drive the photo couple Figure 4 23 shows the OGRx input External 24V power Internal logic Power 4 7K Resistor Internal Signal to FPGA gt Encoder ORGx Internal Ground Figure 4 23 Encoder OGRx Input Operation Theory 39 ADLINK PN CW CCW Encoder Mode When GPTC is set to CW CCW encoder mode and when the input EAx is connected to CW source signal and EBx is con nected to CCW source signal pulses from EAx will cause the counter to counter up and spin the motor clockwise Otherwise pulses from EBx will cause the counter to counter down and spin the motor counterclockwise Figure 4 24 shows the increase decrease of counter value in CW or CCW encoder mode CW CCW EAO EA1 EBO EB1 Cou
5. ADLINK JN PCI 6202 16 bit High Resolution Voltage Output Card User s Manual Manual Rev 2 00 Revision Date March 17 2008 Part No 50 11235 1000 Recycled Paper Advance Technologies Automate the World A ADLINK TECHNOLOGY ING Copyright 2008 ADLINK TECHNOLOGY INC All Rights Reserved The information in this document is subject to change without prior notice in order to improve reliability design and function and does not represent a commitment on the part of the manufacturer In no event will the manufacturer be liable for direct indirect spe cial incidental or consequential damages arising out of the use or inability to use the product or documentation even if advised of the possibility of such damages This document contains proprietary information protected by copy right All rights are reserved No part of this manual may be repro duced by any mechanical electronic or other means in any form without prior written permission of the manufacturer Trademarks NuDAQ NulPC DAQBench are registered trademarks of ADLINK TECHNOLOGY INC Product names mentioned herein are used for identification pur poses only and may be trademarks and or registered trademarks of their respective companies ADLINK Getting service Customer satisfaction is our top priority Contact us should you require any service or assistance ADLINK TECHNOLOGY INC Web Site Sales amp Service Telephone N
6. a gt 4 I I l I e a l I l Period width HV LV Figure 4 11 PWM Output Parameters The period width time value is shown in this formula Period time value ms 80 MHz HV and LV can also set the PWM duty cycle HV High level d f 2 igh tevel _ dutycycie HV LV iV L level d le ow _ievei _dutycycie HV Ly 30 Operation Theory General Purpose Timer Counter ADLINK PCI 6202 comes with three general purpose timer counter sets featuring gt gt Count up down controlled by hardware or software Programmable counter clock source internal clock up to 80MHz external clock up to 10MHz Programmable gate selection hardware or software control Programmable input and output signal polarities high active or low active Initial Count can be loaded from a software application Current count value can be read back by software without affecting circuit operation Definition Pin Definition 1 35 GPTC_OUTO 2 36 GPTC GATEO 3 37 GPTC UDO 4 38 GPTC_AUX0 5 39 GPTC_CLKO 6 40 GPTC_OUT1 7 41 GPTC GATE1 8 42 GPTC UD1 DGND 9 43 GPTC AUX1 DGND 10 44 GPTC CLK1 11 45 DGND 12 46 DGND 13 47 DGND 14 48 DGND 15 49 DGND 16 50 DGND 17 51 DGND 18 52 DGND DGND 19 53 DGND 20 54 DGND 21 55 DGND 22 56 DGND 23 57 34 68 Table 4 5 Timer Counter Mode Pins in CN1 Operation Theory 31
7. EAO 11 45 EAT EAO 12 46 EA1 EBO 13 47 EBT EBO 14 48 EB1 EZ0 15 49 Ezt EZ0 16 50 EZ1 EORGO 17 51 EORG1 EA2 18 52 EZ2 EA2 19 53 EZ2 EB2 20 54 EORG2 EB2 21 55 Ext 24V Ext GND 22 56 Ext 24V IGND 23 57 Ext GND IGND 24 58 IGND VDD 25 59 IGND VDD 26 60 ISO5V DO 0 27 61 IDO 8 DO 1 28 62 IDO 9 IDO 2 29 63 IDO 10 IDO 3 30 64 IDO 11 IDO 4 31 65 IDO 12 IDO 5 32 66 IDO 13 IDO 6 33 67 1DO 14 IDO 7 34 68 IDO 15 Table 2 2 CN2 Pin Assignment Hardware Information 13 ADLINK PN Signal Descriptions Below is the PCI 6202 I O signal descriptions Signal Name Reference Direction Description AO_CH lt 0 3 gt AGND Output AO channel lt 0 3 gt AGND Analog ground for AO DI lt 0 7 gt DGND Input Digital Input lt 0 7 gt DO lt 0 7 gt DGND Output Digital Output lt 0 7 gt EA lt Q 1 2 gt Ext GND Input Encoder A Phase EB lt Q 1 2 gt Ext GND Input Encoder B Phase EZ lt 0 1 2 gt Ext GND Input Encoder Z Phase ORG lt 0 2 gt Ext GND Input Encoder Original Signal Ext 24V Ext GND Input Encoder voltage input pin GPTC_CLK lt 1 gt DGND Input Clock source of GPTC lt O 1 gt GPTC_GATE lt 0 1 gt DGND Input Gate
8. VB Delphi BCB etc DAQBench DAQPilot 2 s Library PCIS D2K WD OCX ActiveX Control amp System Mar ActiveX Control NET Assembly IPCIS IWD DAQPilot Drivers Driver D2K PCI SEIS Task oriented Operating System Windows 98 NT 2K XP Vista x86 Windows XP x64 Server 2003 x64 Vista x64 ADLINK DAQ Cards General Purpose DAQ Digital I O Analog Output Performance DAQ PXI High Speed Digital I O Digitizer Figure 1 1 ADLINK Software Support Overview Introduction ADLINK BA Driver Support for Windows DAQPilot DAQPilot is a driver and SDK with a graphics driven interface for various application development environments DAQPilot comes as ADLINK s commitment to provide full support to its comprehensive line of data acquisition products and is designed for the novice to the most experienced programmer ANALOG INPUT ANALOG OUTPUT DIGITAL INPUT DIGITAL OUTPUT TIMER CTR Figure 1 2 DAQPilot Main Interface As a task oriented DAQ driver SDK and wizard for Windows systems DAQPilot helps you shorten the development time while accelerating your learning curve for data acquisition pro gramming You can download and install DAQPilot at http Awww adlinktech com TM DAQPilot html Introduction 7 ADLINK DAQMaster The ADLINK DAQMaster is a smart device manager that opens up access to ADLINK data acquisition and test and mea surement products DAQMaster deliver
9. 3 Installation This part describes the PCI 6202 installation and configuration Chapter 4 Operation Theory The operation theory of the PCI 6202 functions including D A conversion isolation DIO and application function I O are discussed in this chapter Chapter 5 Calibration The chapter offers information on how to calibrate the PC1 6202 for accurate data acquisition and out put Warranty Policy This presents the ADLINK Warranty Policy terms and coverages ADLINK PN 1 3 Conventions Take note of the following conventions used throughout the man ual to make sure that you perform certain tasks and instructions properly NOTE Additional information aids and tips that help you per form particular tasks IMPORTANT Critical information and instructions that you MUST perform to complete a task WARNING Information that prevents physical injury data loss mod ule damage program corruption and others when trying to complete a particular task A ADLINK BA OGY INC List OF Table eccisisiccdveieveviieivspevscesiessceesepavtenvsverseusesalBeceberteetes iii List of Figures uuuaanumunanneansenjmaanosinanievasinisktkn iv 1 Introduction issnin osanna annia enana aiaa aoaaa aai 1 VA Features irian ia n aaia aE EA aS 2 1 2 Applications rrnnrnnrnnrrrrvrnrrnrrrrnrrnrn rann nnnennrnnrertnrrnrnnnnnnnnnn 2 1 3 Speomcationssuauansedduesekddeeedalnntdeg 3 1 4 Unpacking Checklist errrnnnrrnnnronnnrrnnnronnnrr
10. 5885 8666 86 10 5885 8625 Room 801 Building E Yingchuangdongli Plaza No 1 Shangdidonglu Haidian District Beijing China ADLINK TECHNOLOGY SHANGHAI Sales amp Service Telephone No Fax No Mailing Address market adlinkchina com cn 86 21 6495 5210 86 21 5450 0414 Floor 4 Bldg 39 Caoheting Science and Technology Park No 333 Qinjiang Road Shanghai China ADLINK TECHNOLOGY SHENZHEN Sales amp Service Telephone No Fax No Mailing Address market adlinkchina com cn 86 755 2643 4858 86 755 2664 6353 C Block 2nd Floor Building A1 Cyber tech Zone Gaoxin Ave 7 S High tech Industrial Park S Nanshan District Shenzhen Guangdong Province China A ADLINK BA OGY INC Using this manual 1 1 Audience and scope This manual guides you when using ADLINK multi function data acquisition PCI card The card s hardware signal connections and calibration information are provided for faster application building This manual is intended for computer programmers and hardware engineers with advanced knowledge of data acquisition and high level programming 1 2 How this manual is organized This manual is organized as follows Chapter 1 Introduction This chapter intoduces the ADLINK PCI 6202 card including its features specifications software support information and package contents Chapter 2 Hardware Information This chapter presents the card s layout and connector pin definition Chapter
11. 9 p i 3 gt 1 Figure 4 27 X4 Encoder Mode Phase Z Each encoder mode may use a third phase phase Z that is also frequently used for the index phase You may decide if the counter needs to be reloaded a specified value when phase Z is at a logic high level with phase A and B at a specific logic condition You must ensure that the logic level of phase Z is high during at least a portion of the phase you specify for reload when you use phase Z Otherwise the counter does not reload In Figure 4 28 the reload phase is when the logic level of phase A is high phase B is low and phase Z is high in X1 Operation Theory 41 ADLINK PN Encoder Mode In addition reloading takes higher priority than increment or decrement of counter value The reload occurs within one maximum CLK period after the reload phase becomes true After the counter value is reloaded the counter continues to count as before Phase A Phase B Phase Z 2 3 3 0 0 Count Value 0 1 1 2 Figure 4 28 Phase Z Original Signal ORGx Original Signal ORGO ORG2 ORG1 is used with phase Z With ORG enabled a high level on phase Z and ORG causes the counter to reload with a specified value in a specified phase of the quadrature cycle When you use ORG signal if it is at a low level and phase Z is at a high level then counter reload is ignored Encoder Position Trigger The PCI 6202 comes with a special encoder function This
12. Digital I O Number of channels 8 CH TTL digital input e 8 CH TTL digital output e 3 CH Application Function Interface AFI Input voltage e Logic low VIL 0 8V max IIL 0 2mA max e Logic high VIH 2 0V min IIH 0 2mA max Output voltage e Logic low VOL 0 5V max IOL 10mA max e Logic high VOH 2 6V min IIH 10mA max Timer Counter Type 2 CH 32 bit general purpose timer counters Clock source Internal or external Maximum source Internal 80 MHz frequency External 10 MHz Encoder Inputs Number of channels 3 Maximum input frequency 4 MHz Encoder count 19 bit data width Photo isolator Photo isolator Encoder modes CW CCW X1 AB phase encoder X2 AB phase encoder X4 AB phase encoder PWM Outputs Number of channels 4 Duty cycle 1 99 Modulation frequency 20 MHZ to 0 005 Hz Isolated 5V Output Driving current 350 mA maximum Introduction ADLINK Physical Power and Operating Environment Dimension 120 mm x 87 mm I O connector 2 x 68 pin SCSI VHDCI connectors Power Requirement e 5 VDC 500 mA typical e 12 VDC 110 mA Operating environment e Ambient temperature 0 C to 45 C e Relative humidity 10 to 90 non condensing Storage environment Ambient temperature 20 C to 80 C e Relative humidity 5 to 95 non condensing Specificat
13. maximum isolated digital input current Operation Theory 43 ADLINK PN 4 7 Trigger Sources The PCI 6202 supports two trigger sources for analog input software trigger and external digital trigger Software Trigger This trigger mode does not need any external trigger source The trigger asserts right after you execute the specified function calls to begin data acquisition External Digital Trigger An external digital trigger occurs when a rising edge or a falling edge is detected on the digital signal connected to the PCI 6202 s function I O You can set any DI line as external trigger pin You may also easily program the trigger polarity via the ADLINK soft ware drivers Take note that the signal level of the external digital trigger signals should be TTL compatible with a minimum 25 ns pulse Positive edge trigger event occurs Negative edge trigger event occurs Figure 4 31 External Digital Trigger 44 Operation Theory A ADLINK BA OGY INC 5 Calibration Before shipment the PCI 6202 is factory calibrated with Agilent 34410 The calibration is done by writing the associated calibration constants of TrimDACs firmware to the onboard EEPROM Trim DACs firmware is the algorithm in the FPGA Loading calibration constants is the process of loading the values of TrimDACs firm ware stored in the onboard EEPROM NOTE A one year re calibration interval is recommended Contact your distributor or ADLINK
14. of GPTC lt 0 1 gt GPTC_OUT lt 0 1 gt DGND Output Output of GPTC lt O 1 gt GPTC UD lt 0 1 gt DGND Input Up Down of GPTC lt 0 1 gt IDI lt 0 15 gt COM Input Isolation digital input lt 0 15 gt IDO lt O 15 gt IGND Output Isolation digital output lt 0 15 gt ISO5V IGND Output Isolation 5V power NC NC NC No connection Table 2 3 I O Signal Description 14 Hardware Information ADLINK 3 Installation 3 1 Before You Proceed The PCI 6202 card has electro static sensitive components that can be easily damaged by static electricity The card must be han dled on a grounded anti static mat The operator must wear an anti static wristband grounded at the same point as the anti static mat Inspect the card module carton for damages Shipping and han dling could cause damage to the module Make sure that the card has no damage before installing it After opening the card package get the module and place it ona grounded anti static surface with component side up then care fully inspect the module for any damage Press down all socketed ICs to make sure that they are properly seated Do this only with the module placed on a firm flat surface WARNING Do not apply power to the card if it is damaged 3 2 Installing the Card IMPORTANT Install the card driver before you install the card into your computer system Refer to section 1 5 for driver support information To install the card 1 Turn o
15. the size of a single waveform is larger than that of the FIFO it needs to be intermittently loaded from the host computer s memory via DMA and will occupy the PCI band width 4 update count 3 iteration count UC counter 4 IC counter 3 DLY2_counter 0 UC Counter 4 Trigger i DAWR l WF in Rrog i ke TL LT A single waveform Figure 4 9 Finite Iterative Waveform Generation with Post trigger In conjunction with different trigger modes and counter setups you can manipulate a single waveform to generate different and more complex waveforms 4 update count iterate infinite UC counter 4 IC counter infinite DLY2_counter 0 f 1 Vg UC Counter 4 Trigger i vawe UII i a gt 1 A single waveform Figure 4 10 Infinite Iterative Waveform Generation with Post trigger 26 Operation Theory A ADLINK DLY2_Counter in Iterative Waveform Generation To expand the flexibility of iterative waveform generation DLY2_counter was implemented to separate consecutive waveform generations The DLY2_counter starts counting down right after a single waveform generation is completed When it reaches zero the next iteration of waveform generation will start as shown in Figure 4 5 If you generate the waveform piece wisely the next piece of waveform will be generated Operation Theory 27 A A ADLINK TECHNOLOGY I
16. 202 is suitable for the following applications gt gt Automotive testing Waveform generation Introduction 1 3 Specifications ADLINK Analog Output AO Number of channels 4 D A converter Onboard converter Maximum update range 1 MS s per channel Resolution 16 bit Data transfers Programmed I O DMA Output range 10 V Settling time 3 us 0 1 of full scale Slew range 20 V uS Rise time 0 67 V S typical Fall time 20V uS Maximum DNL 1 LSB Output coupling DC Output impedance 0 01 Q maximum Output driving 5 mA maximum Stability Any passive load up to 1500 pF Power on state OV Power on glitch 6 25 mV ms maximum Offset error After calibration 0 3 mV typical Gain error After calibration 0 06 mV maximum Isolated Digital Input Number of channels 16 Photo isolator PC3H410 or equivalent Isolation voltage 2500 Vrms Input voltage Up to 24 VDC non polarity Logic low VIL 0 to 3 0 V e Logic high VIH 3 2 V to 2 4 V Input resistance 4 7 KO 0 12 W Introduction A A ADLINK TECHNOLOGY ING Isolated Digital Output Number of channels 16 Photo isolator PC3H7 or equivalent Isolation voltage 2500 Vrms Output type Photo coupler transistors open collector up to 24 VDC Sink current 200 mA for each channel maximum
17. DAQPilot and avoid using legacy DASK drivers For current DASK driv er users or those who do not have Internet access we of fer an installation CD Contact your ADLINK distributor for details Introduction 9 A ADLINK TECHNOLOGY INC 10 PCIS DASK drivers prepare legacy Windows users for Win dows Vista and 64 bit editions of Windows PCIS DASK comes with the following features gt gt gt gt Supports Windows Vista 32 bit or 64 bit editions Supports AMD64 and Intel x86 64 architectures Digitally signed for Windows Vista 64 bit edition Utilizes WOW64 subsystem to ensure that 32 bit applica tions run normally on 64 bit editions of Windows XP Win dows 2003 Server and Windows Vista without modification For more information about Windows Vista support visit http www adlinktech com TM VistaSupport html or view the user s guide included in the ADLINK All in one CD Introduction ADLINK 2 Hardware Information This chapter provides information on the PCI 6202 layout connec tors and pin assignments 2 1 Card Layout Figure 2 1 shows the PCI 6202 board layout and dimensions gt fa EUEUETEUTE LIG as Go P ET Eo cy Figure 2 1 PCI 6202 Layout 2 2 Connector Pin Assignment PCI 6202 c
18. External digital trigger in Used for one of all DA output trigger source External digital trigger out Export a digital trigger based on a software trigger Encoder position trigger This function is combined with out encoder0 input When encoder counts up for a specific value that you have set AFIO will export a digital high signal AFI1 External convert signal out AFI1 can be configured as a DA convert source Digital trigger in Used for one of all DA output trigger source Digital trigger out Export a digital trigger based on software trigger Encoder position trigger This function is combined with out encoder input When encoder counts up for a specific value that you have set AF11 will export a digital high signal AFI2 Encoder position trigger This function is combined with out encoder2 input When encoder counts up for a specific value that you have set AFI2 will export a digital high signal Table 4 4 AFI Functions Operation Theory 29 ADLINK PWM Output The PCI 6202 provides four dedicated PWM outputs each consisting of two parameters high level and low level width These two parameters have a 24 bit count width that can be used The PWM base clock is 80MHz Figure 4 11 shows the high and low level definition of the PWM output HV is high level width count value while LV is low level count value High Level width HV Low Level width LV
19. FAE staff service Qadlinktech com 48 Warranty Policy
20. NG 28 4 3 General Purpose Digital D O The PCI 6202 offers comprehensive support to various digital I O provided by an FPGA chip These digital I O include general pur pose digital input and output PWM Timer Counter and Applica tion Function Interface AFI General Purpose DIO PCI 6202 provides 8 channel DI and 8 channel DO All I O are static TTL compliant You can read write these I O line by soft ware polling In this way the sample and update rate is fully controlled by software timing Definition Pin amp Definition DOO 1 35 DO1 2 36 DO2 3 37 DO3 4 38 DO4 5 39 DO5 6 40 DO6 7 41 DO7 8 42 DGND 9 43 DGND 10 44 DIO 11 45 DGND DI 12 46 DGND DI2 13 47 DGND DI3 14 48 DGND DI4 15 49 DGND DI5 16 50 DGND DI6 17 51 DGND DI7 18 52 DGND DGND 19 53 PWM 0 DGND 20 54 PWM 1 DGND 21 55 PWM 2 DGND 22 56 PWM 3 DGND 23 57 AFIO 24 58 AFI1 25 59 AFI2 26 60 34 68 Table 4 3 TTL DIO Pins in CN1 Operation Theory ADLINK Application Function Interface AFIx The application function interface can be used for special func tions The table below shows the available function for each dedicated AFI pin NOTE When AFIx is configured as one function these pins may not be used for any other function Pin Function Note AFIO External convert signal out Configured as a DA convert source
21. ain Figure 4 16 illustrates the generation of a single pulse with a pulse delay of two and a pulse width of four Software start Gate n ok UML Count value h 2 1 0 3 2 1 0 ur mm Figure 4 16 Mode 5 Operation Mode 6 Re triggered Single Pulse Generation This mode is similar to Mode 5 except that the counter gener ates a pulse following every active edge of GPTC GATE After the software start every active GPTC GATE edge triggers a single pulse with programmable delay and pulse width Any GPTC GATE triggers that occur when the prior pulse is not completed is ignored Figure 4 17 illustrates the generation of two pulses with a pulse delay of two and a pulse width of four Software start Ignored Gate I iM I CLK AUTO nn Count value 2 1032102210321022 art Mooon 177 Figure 4 17 Mode 6 Operation Operation Theory 35 A ADLINK TECHNOLOGY ING Mode 7 Single Triggered Continuous Pulse Generation This mode is similar to Mode 5 except that the counter gener ates continuous periodic pulses with programmable pulse inter val and pulse width following the first active edge of GPTC_GATE When the first GPTC_GATE edge triggers the counter GPTC_GATE makes no effect until the software start is executed again Figure 4 18 illustrates the generation of two pulses with a pulse delay of four and a pulse width of three Software start Gate eh LOLOL Count value 4 FY 23 152181 2 1 8 4 181 3 OUT r 1 r
22. cccceceeeeeeeeeeeeeeseneeeaeeees 33 Mode 2 Operation cccccceeeeeeeeeteeteeesenereaeeees 33 Mode 3 Operation ccccccceeeeeeeeseeteeeseseeeaeeees 34 Mode 4 Operation ccccceeeeeeeeeseeeeeeseneeeaeeees 34 Mode 5 Operation cccccecceeeeeeseeseeeeeneeeaeeees 35 Mode 6 Operation c cccceeeeeeeeeseeeeeeetseeeaeeees 35 Mode 7 Operation cccccecceeeeeeseeseeeseneeeeeeees 36 Mode 8 Operation cccccceceeeeeeeseeteeeeeneeeaeeees 36 Mode 9 Operation cccccceeeeeeeeeseeeeeeseneeeateees 37 Mode 10 Operation rnrrrrrnnrrnnrnnnrnnnrnnrnnnnnrnnnnnnnen 37 Encoder Isolation Input Module rornnrnnnnnnnrnnrr 39 Encoder OGRX Input rerrnnnrnnnernrrrrrrnnnrnnrnnnennnenn 39 CW CCW Encoder Timing 40 X1 Encoder Mode mmrnnnnnnnnnnnnnnnnvnnnnnnnvennnnnrrnnrnnnnnn 40 X2 Encoder Mode viisis diaii adiada 41 X4 Encoder Mode mrrnnnnnnnnnnnnnrnnnnnnnnnvennnnnnrnnrnnnnnn 41 PHASE E A E 42 Isolated Digital Output rrrrannnrrnrnnnnnnrnvrrrnnnnrnnrnnn 43 Isolated Digital Input oornnrarnnnnrnnnnnnnnnnrrrnnrnnnnnnnn 43 External Digital Trigger errrnnvrrnnnnnnnnvrnnnnnvnvrrrnnnen 44 List of Figures ADLINK 1 Introduction The ADLINK PCI 6202 is a 4 channel 16 bit high resolution voltage output card with hardware timed waveform generation It comes with four analog output channe
23. ctly configured Refer to the BIOS documentation that came with the system for details 16 Installation A ADLINK 4 Operation Theory The operation theory of each PCI 6202 function is described in this chapter These functions include D A conversion isolation DIO application function I O and more The operation theory can help you understand how to configure and program the PCI 6202 4 1 Block Diagram There are 4 single ended channels of 16 bit D A output available in the PCI 6202 Every two channels are generated by one DAC chip TI DAC8812 The DAC controller and all timing control log ics are implemented by FPGA Combining FIFO design and syn chronized update control logic the PCI 6202 provides 4 channels simultaneous voltage output with waveform generation functional ity For analog output the PCI 6202 comes with a calibration circuit to provide high accuracy voltage output with low temperature drift The calibration data are saved in the EEPROM The isolated digital I O TTL digital I O encoder and PWM output are controlled directly by the FPGA Refer to Figure 4 1 EEPROM AO DATA FLOW Control l Calibration Data Storage Ta T p gt PCI INTERFACE AFI GPIO GPTC Decorder Calibration Control Figure 4 1 PCI 6202 Block Diagram Operation Theory 17 EN A ADLINK TECHNOLOGY ING 18 4 2 D A Conversion The PCI 6202 supports voltage output in two
24. e GPTC_CLK after the software start Initial count can be loaded from the software application Current count value can be read back by software any time with no effect to the counting GPTC_GATE is used to enable disable counting When GPTC_GATE is inactive the counter halts the current count value Figure 4 12 illustrates the operation with initial count 5 count down mode 32 Operation Theory A ADLINK Software start Gate sr ck Lee Count value 5 5 4 3 2 1 1 0 en Figure 4 12 Mode 1 Operation Mode 2 Single Period Measurement The counter counts the period of the signal on GPTC_GATE in terms of GPTC_CLK Initial count can be loaded from the soft ware application After the software start the counter counts the number of active edges on GPTC_CLK between two active edges of GPTC_GATE After the completion of the period inter val on GPTC_GATE GPTC_OUT outputs high and then cur rent count value can be read back by the software application Figure 4 13 illustrates the operation where initial count 0 count up mode Software start amp 34 Gate PF Lo To ee Count value 0 0 1 2 3 4 5 5 5 Figure 4 13 Mode 2 Operation Mode 3 Single Pulse width Measurement The counter counts the pulse width of the signal on GPTC_GATE in terms of GPTC_CLK Initial count can be loaded from the software application After the software start the counter counts the number of active edges on GPTC_CLK when GPTC_GATE is i
25. eneral Purpose Timer Counter cceceeeeeeeees 31 4 4 Isolation Encoder cccccecceceeeeeeeeeeeeeeecneeeeeeeeeeeeeeeeees 38 4 5 Isolated Digital Output rsrrrnnnrnnnnrrnnnnnnnnrrrnnnrennrrrnnnrennnnn 43 4 6 Isolated Digital Input ssnnrrrnnnnonnnrrnnnnonnnrrnnnnennnrrnnnsenennnr 43 Table of Contents i APLINK PA AT Trigger Sources oenraniccisrieeac add danene 44 Software Tigger secrencecennensniennnaninniorani 44 External Digital Trigger rrrrrnnnnonnrrnnnnennrrrnnnnersrrrenssennr 44 5 Calbratonuuuuawnuvauennmeuncrnanoaaoeskiinijdhumskiven 45 Warranty PONCY uemsansasentuespdanenudosemrsrkkvvicjeinnr 47 ii Table of Contents A ADLINK BA TECHNOLOGY INC List of Tables Table 2 1 CN1 Pin Assignment aiseee 12 Table 2 2 CN2 Pin Assignment ennrrrnnroonnnrrrnnronnnrrrvnnrennrnnen 13 Table 2 3 I O Signal Description rrrrnnnnonnrrrvnnnnonnrrnnnnnennnnne 14 Table 4 1 Bipolar Output Codes rrrnnrnnrrnrrnnrnnnrrrrrrrrnnrnnnnnnn 20 Table 4 2 Summary of Counters for Waveform Generation 21 Table 4 3 TTL DIO Pins in CN1 rrennnrrrrrrrnnrrrrrrrrrnnrrrrrsrrnnrnnen 28 Table 4 4 AFI Functions mmmmrererrrnrrrnrrrrrrnrrnrrenrrrrrrnnrnnrnnnnnnn 29 Table 4 5 Timer Counter Mode Pins in CN1 rrnnnnrnnrrnnnnnnrnn 31 Table 4 6 Encoder Pins in CN2 cccccceeeeeeeeeeeeteeneenee 38 List of Tables iii A A ADLINK TECHNOLOGY INC Figu
26. er of Pulse_initial_cnt and Pulse_length_cnt you can get varying pulse frequency Fpwm and duty cycle Dutypwm Figure 4 21 illustrates the PWM output and the formula showing how to calculate the PWM frequency and duty cycle I I I MA l I 1 Pulse Initial cnt 0x7 1 Pulse length cont 0xB i mar o YO tmerase CLP nnn Figure 4 21 Mode 10 Operation F F Timedase PUM Pulse initial _cnt Pulse length _cnt Pulse length _ ent Duty PEMO Pulse _initial _cnt Pulse _length _cni Operation Theory 37 A A ADLINK TECHNOLOGY ING 38 4 4 Isolation Encoder PCI 6202 features a combination of data acquisition and simple motion control with support for three encoder input sets which pro vide an alternative for step motor or servo motor s position feed back The internal isolation provides easy encoder connection The encoder sets are assigned in CN2 Definition Pin Definition 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 COM 9 43 COM COM 10 44 COM EAO 11 45 EA1 EAO 12 46 EA1 EBO 13 47 EB1 EBO 14 48 EB1 EZ0 15 49 EZ1 EZ0 16 50 EZ1 EORGO 17 51 EORG1 EA2 18 52 EZ2 EA2 19 53 EZ2 EB2 20 54 EORG2 EB2 21 55 Ext 24V Ext GND 22 56 Ext 24V IGND 23 57 Ext GND IGND 24 58 IGND VDD 25 59 IGND VDD 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67
27. ff the system chassis and disconnect the power plug from the power source 2 Remove the system chassis cover 3 Select the PCI slot that you intend to use then remove the bracket opposite the slot if any 4 Align the card connectors golden fingers with the slot then press the card firmly until the card is completely seated on the slot 5 Secure the card to the chassis with a screw Installation 15 ADLINK PN 6 Replace the system chassis cover 7 Connect the power plug to a power source then turn on the system 3 3 Configuring the Card As a plug and play component the card requests an interrupt number through its PCI controller The system BIOS responds with an interrupt assignment based on the card information and on known system parameters These system parameters are deter mined by the installed drivers and the hardware load detected by the system Configuration The card configuration is done on a card by card basis for all PCI cards on your system Because configuration is controlled by the system and the software there is no jumper setting required for base address DMA and interrupt IRQ The configuration is subject to change with every boot of the sys tem as new PCI cards are added or removed Troubleshooting If your system fails to boot or if you experience erratic operation with your PCI card in place this is likely caused by an interrupt conflict such as when the BIOS Setup is incorre
28. function combines the encoder count function digital output and system interrupt When you set the pacer number and enable the encoder position trigger function this function will start to count When the counting number is equal to the multiple of pacer number the position trigger will output high in AFIx pin or gen erate an interrupt for software operation The behavior may be selected by configuring this function The output AFIx pulse width can still be configured as 200us 2ms 20ms and 200ms by the software application 42 Operation Theory A ADLINK 4 5 Isolated Digital Output The isolated digital output circuit offers an open collector type output and an isolation voltage of 2500 Vrms between the iso lated output and the host power signals Refer to Figure 4 29 Internal 3 3V External Isolation Power Isolation 5V Pull up Resistor LOAD Isolation DOx Internal Signal to FPGA Isolator IGND Figure 4 29 Isolated Digital Output 4 6 Isolated Digital Input The isolated digital input circuit is equipped with a current limit resistor and supports an input voltage of up to 24V The isola tion voltage between the isolated input and the host power sig nals is 2500 Vrms as illustreated in Figure 4 30 3 3V Pull up Resistor Isolation DI I 4 7K ohm Resistor 3 Signal to FPGA COM Isolator Ground Figure 4 30 Isolated Digital Input NOTE The 4 7 kQ resistor constrains the
29. hich items you sent on the RMA Request amp Confirmation Form ADLINK is not responsible for items not listed on the RMA Request amp Confirmation Form Warranty Policy 47 A A ADLINK TECHNOLOGY ING 3 Our repair service is not covered by ADLINK s guarantee in the following situations gt gt gt gt Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part dur ing product transportation Damage caused by fire earthquakes floods lightening pollution other acts of God and or incorrect usage of voltage transformers Damage caused by unsuitable storage environments i e high temperatures high humidity or volatile chemi cals Damage caused by leakage of battery fluid during or after change of batteries by customer user Damage from improper repair by unauthorized ADLINK technicians Products with altered and or damaged serial numbers are not entitled to our service This warranty is not transferable or extendible Other categories not protected under our warranty 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company web site http rma adlinktech com policy Damaged products with attached RMA forms receive priority If you have any further questions please email our
30. ions are subject to change without notice 1 4 Unpacking Checklist Before unpacking check the shipping carton for any damage If the shipping carton and or contents are damaged inform your dealer immediately Retain the shipping carton and packing mate rials for inspection Obtain authorization from your dealer before returning any product to ADLINK Check if the following items are included in the package gt PCI 6202 multi function DAQ card gt ADLINK All in One CD gt User s manual If any of the items is damaged or missing contact your dealer immediately CAUTION The card must be protected from static discharge and physical shock Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the product to handle the card Wear a grounded wrist strap when servicing Introduction 5 ADLINK TECHNOLOGY INC 1 5 Software Support ADLINK provides comprehensive software drivers and packages to suit various user approach to building a system Aside from pro gramming libraries such as DLLs for most Windows based sys tems ADLINK also provides drivers for other application environment such as LabVIEW and MATLAB ADLINK also provides ActiveX component ware for measurement and SCADA HMI and breakthrough proprietary software applications All software options are included in the ADLINK All in One CD ADE VB NET C NET VC
31. ls that update simultaneously and support up to 1 MS s update rate per channel Delivering excellent linearity DNL lt 1 LSB the PCI 6202 is suitable for dynamic signal simulation and control applications which require high accuracy through voltage output The PCI 6202 also provides additional I O control lines for system integration including 16 CH isolated digital input and 16 CH isolated output 8 CH TTL DI and 8 CH TTL DO 3 CH encoder inputs and 4 CH PWM outputs These high performance 1 O functionalities combined with a solid voltage output linearity and high accuracy make the PCI 6202 the best single board solution for both equipment manufacturers and laboratory research applications Introduction 1 ADLINK PN 1 1 Features The PCI 6202 comes with the following features Yv v v yy yy V v 1 2 Supports a 32 bit 3 3 V or 5 V PCI bus PCI 2 3 compliant 4 CH single ended analog output 1 MS s with simultaneous update FIFO with 512 samples 8 CH TTL digital input and 8 CH TTL digital output 16 CH isolated digital input and 16 CH isolated digital output 2 CH 32 bit 40 MHz general purpose timer counters 3 CH 4 MHz encoder input supporting AB phase and CW CCW 4 CH PWM output 3 CH digital application function interface with gt Digital input and output gt External digital trigger in and out gt External analog output conversion clock source gt Encoder trigger out Applications The PCI 6
32. n its active state After the completion of the pulse width interval on Operation Theory 33 ADLINK PN GPTC_GATE GPTC_OUT outputs high and then current count value can be read back by the software application Figure 4 14 illustrates the operation where initial count 0 count up mode Software start Gate EE fF M GE oe Jee ae Count value n 0 1 2 3 4 5 5 5 Figure 4 14 Mode 3 Operation Mode 4 Single Gated Pulse Generation This generates a single pulse with programmable delay and programmable pulse width following the software start The two programmable parameters can be specified in terms of periods of the GPTC_CLK input by the software application GPTC_GATE is use to enable disable counting When GPTC_GATE is inactive the counter halts the current count value Figure 4 15 illustrates the generation of a single pulse with a pulse delay of two and a pulse width of four Software start Gate fig e Lee Count value 2 2 1 0 3 2 2 1 0 OUT NE SEE SS __ Figure 4 15 Mode 4 Operation 34 Operation Theory A ADLINK BA OGY INC Mode 5 Single Triggered Pulse Generation This mode generates a single pulse with programmable delay and programmable pulse width following an active GPTC_GATE edge You may specify these programmable parameters in terms of periods of the GPTC_CLK input When the first GPTC_GATE edge triggers the single pulse GPTC_GATE makes no effect until the software start is exe cuted ag
33. nt Value 9 1 2 3 4 5 6 7 aff 8 7 6 5 4 3 Figure 4 24 CW CCW Encoder Timing X1 Encoder Mode In X1 encoder mode if phase A EAO EA1 is advanced of phase B EBO EB1 in a quadrature cycle the increment of counter value will be 1 Otherwise if phase B is advanced of phase A in a quadrature cycle the decrement of counter value will also be 1 Figure 4 25 shows a quadrature cycle and the increment and decrement of counter value in X1 encoder mode When phase A leads phase B the counter value increases on the first rising edge of CLK after phase A goes high When phase B leads phase A the counter value decreases on the first rising edge of CLK after phase A goes low T H i 7 f Phase A i i i oe i l Phase B Count Value 0 1 1 2 2 3 3 2 2 1 Figure 4 25 X1 Encoder Mode 40 Operation Theory A ADLINK BA OGY INC X2 Encoder Mode This mode is similar to X1 Encoder Mode except that the amount of counter value increases or decreases by two Refer to Figure 4 26 UA A Count Value 0 f a P 5 P 3 2 f Figure 4 26 X2 Encoder Mode X4 Encoder Mode This mode is similar to X1 Encoder Mode except that the amount of counter value increases or decreases by four Refer to Figure 4 27 PhaseB pi EE t ggz e AMMAR AU Count Value 0 i n 7 p
34. o Fax No Mailing Address http Www adlinktech com service Qadlinktech com 886 2 8226 5877 886 2 8226 5717 9F No 166 Jian Yi Road Chungho City Taipei Hsien 235 Taiwan ROC ADLINK TECHNOLOGY AMERICA INC Sales amp Service Toll Free Fax No Mailing Address info adlinktech com 1 866 4 ADLINK 235465 1 949 727 2099 8900 Research Drive Irvine CA 92618 USA ADLINK TECHNOLOGY EUROPEAN SALES OFFICE Sales amp Service Toll Free Fax No Mailing Address emea adlinktech com 49 211 4955552 49 211 4955557 Nord Carree 3 40477 Dusseldorf Germany ADLINK TECHNOLOGY SINGAPORE PTE LTD Sales amp Service Telephone No Fax No Mailing Address singapore adlinktech com 65 6844 2261 65 6844 2263 84 Genting Lane 07 02A Cityneon Design Center Singapore 349584 ADLINK TECHNOLOGY INDIA LIAISON OFFICE Sales amp Service Telephone No Fax No Mailing Address india adlinktech com 91 80 57605817 91 80 2667 1806 No 1357 Ground Floor Anupama Aurobindo Marg JP Nagar Ph 1 Bangalore 560078 A A ADLINK TECHNOLOGY ING ADLINK TECHNOLOGY KOREA Sales amp Service Telephone No Fax No Mailing Address korea adlinktech com 82 2 20570565 82 2 20570563 402 Dongsung B D 60 12 Nonhyeon Dong Gangnam gu Seoul 135 010 South Korea ADLINK TECHNOLOGY BEIJING Sales amp Service Telephone No Fax No Mailing Address market adlinkchina com cn 86 10
35. omes with two VHDCI 68 pin SCSI VHDCI connectors The CN1 connector is for digital input output AFI and analog out put while CN2 is for isolated DIO and encoder Hardware Information 11 ADLINK PN CN1 Pin Assignment Definition Pin Definition DOO 1 35 GPTC_OUTO DO1 2 36 GPTC_GATEO DO2 3 37 GPTC_UDO DO3 4 38 GPTC AUXO0 DO4 5 39 GPTC_CLKO DO5 6 40 GPTC_OUT1 DO6 7 41 GPTC_GATE1 DO7 8 42 GPTC UD1 DGND 9 43 GPTC AUX1 DGND 10 44 GPTC CLK1 DIO 11 45 DGND DI1 12 46 DGND DI2 13 47 DGND DI3 14 48 DGND DI4 15 49 DGND DIS 16 50 DGND DI6 17 51 DGND DI7 18 52 DGND DGND 19 53 PWM 0 DGND 20 54 PWM 1 DGND 21 55 PWM 2 DGND 22 56 PWM 3 DGND 23 57 AFIO AGND 24 58 AFI1 AGND 25 59 AFI2 AGND 26 60 AGND AGND 27 61 AGND AGND 28 62 AGND AGND 29 63 AGND AGND 30 64 AGND AO CHO 31 65 AGND AO CH1 32 66 AGND AO CH2 33 67 AGND AO CH3 34 68 AGND Table 2 1 CN1 Pin Assignment 12 Hardware Information ADLINK CN2 Pin Assignment Definition Pin Definition IDI 0 1 35 IDI 8 IDI 1 2 36 IDI 9 IDI 2 3 37 IDI 10 IDI 3 4 38 IDI 11 IDI 4 5 39 IDI 12 IDI 5 6 40 IDI 13 IDI 6 7 41 IDI 14 IDI 7 8 42 IDI 15 COM 9 43 COM COM 10 44 COM
36. r IC counter and is illustrated in Figure 4 6 12 Update Count and I iteration count UC Counter 12 hal Trigger DAWR ILI LILI LIL WF in Rrog ooo oo Wave Figure 4 6 Post Trigger Generation Operation Theory 23 A ADLINK PA Delay Trigger Generation Use delay trigger when you want to delay the waveform gener ation after the trigger signal The delay time is determined by DLY1 counter as illustrated in Figure 4 7 The counter counts down on the rising edges of DLY1_counter clock source after the start trigger signal When the count reaches zero card will start to generate the waveform The DLY1 counter clock source can be selected via software application using the internal 80 MHz timebase 6 update count and I iteration count Delay ere oe UC Counter 6 i ache i i i l Trigger i i j 7 i i i pawe LILL WF in Rrog eee q_ Wave Figure 4 7 Delay Trigger Generation Post Trigger or Delay Trigger with Retrigger Use post trigger or delay trigger with retrigger when you want to generate multiple waveforms with respect to multiple incom ing trigger signals You can set Trig counter to specify the number of acceptable trigger signals Refer to Figure 4 8 In this example two waveforms are generated after the first trigger signal The board then waits for another trigger signal When the next trigger signal is asserted the board generates t
37. re 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 2 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 4 12 Figure 4 13 Figure 4 14 Figure 4 15 Figure 4 16 Figure 4 17 Figure 4 18 Figure 4 19 Figure 4 20 Figure 4 21 Figure 4 22 Figure 4 23 Figure 4 24 Figure 4 25 Figure 4 26 Figure 4 27 Figure 4 28 Figure 4 29 Figure 4 30 Figure 4 31 List of Figures ADLINK Software Support Overview s s s 6 DAQPilot Main Interface rnrnnnnnnnnnnnrnnrrnnnnnnnnnnnnn 7 DAQMaster Device Manager 8 Legacy Software Support Overview rrrnrrrrrrrrrrn 9 PCI 6202 Layout sner aiad a 11 PCI 6202 Block Diagram ranrnnnnrrnnnnnonnnrrnnnnnnnnrnnn 17 Block Diagram of D A Conversion Function 18 FIFO Data In Out Structure eeren 19 Waveform Generation for Three Channels Update 19 Typical D A Timing of Waveform Generation 22 Post Trigger Generation uurannnrrnnnnnonnrrrnnnnnnnnnnnn 23 Delay Trigger Generation uarrnnrrrnnrnnnnnrrnnnnnnnnrnnn 24 Post Trigger with Retrigger Generation 4 25 Finite Iterative Waveform Generation with Post trigger 2 enste dies ddiekvdndenilitdee 26 Infinite Iterative Waveform Generation with Posttrigger ssassn i sviende 26 PWM Output Parameters mrrrrrrrnnrnnrnnrnnrnnnnnnnnn 30 Mode 1 Operation cc
38. rnnrennrrrrnrrennrnne 5 1 5 Software Suppokt uismdveesveriiskananreidine 6 Driver Support for Windows 0 ceecceeeeeeeeeeeteeseees 7 2 Hardware Information rnnvrnnvrnnnrnnvrnvnnnnnnnnnnnnnnnennnnnnnner 11 21 Cand Layoutiuuauisniunsenmnn nintshansgvnned i 11 2 2 Connector Pin Assignment rrrnnrrrnnnnonnrrrnnnrnnnnrrennnnrnnrnen 11 CN1 Pin Assignment osiers 12 CN2 Pin Assignment rsnnnrrrnnnnonnrrrnnnnrnnnrrnnnrrnnnrrensernenr 13 Signal Descriptions errrnrrrnnnnrnvrrrnnnnennnrrnnnrensnrrennrenenr 14 3 Installation ui summmuKn hi ivvecdecdeveuvncsivensdveded covsvecesversssals 15 3 1 Before You Proceed ceseeceeceeeeeeeeeeeeeeetesteensanaeees 15 3 2 Installing the Card sseeeasannnnnnnanonnnvnnannnnnnvnnannnnvnvnnannnnnnnenn 15 3 3 Configuring the Card wm x rrnnanvavvrrnnnnvvnnnrrnnnrvrnnrrennrnennrnen 16 Configuration sssini 16 Troubleshooting 0 00 eee eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeteeeeeeeeeeeenaeees 16 4 Operation Theory ccceeccecceeeceeceeeeceeeeeeeeeeeeeeeeeeeees 17 4 1 Block Diagram avventer bli iaceteevstitendemaiiccriuce 17 4 2 DIA COnverSiOn cccccececeeecceeceeeeeeeeeeeseeeenncnaeeeeeeeeeeetees 18 Software Update c cccccccccceeeeeeeeeeeeeeseeeaeeeeeeeeees 20 Waveform Generation ccccccceeeeeeeeeeeteeteeeenaeees 21 4 3 General Purpose Digital D O rarnrrrrnnnannnrrvnnnnennrrrnnevennrnne 28 G
39. s all in one configura tions and provides you with a full support matrix to properly and conveniently configure ADLINK Test and Measurement prod ucts Gee Ir p Derre Manger 0 Setters manager 9 T remert DA Re dren Masam JG Seiten Mader m Ps seen blade y teense inden tee oder a X z Pract byport Meema Fa Par Paget amp Appts E 0 Device Mansgerfinstalied Drag the relected device Rem to tubfunction butten to launch i m BF RT Catibrates 040 2000 serier moduler Ge 1 gt St FE sy Figure 1 3 DAQMaster Device Manager As a configuration based device manager for ADLINK DAQ cards DAQMaster enables you to manage ADLINK devices and interfaces install and upgrade software applications and manage ADLINK DAQPilot tasks 8 Introduction A ADLINK PCIS DASK Legacy Drivers and Support PCIS DASK is composed of advanced 32 bit kernel drivers for customized DAQ application development PCIS DASK enables you to perform detailed operations and achieve supe rior performance and reliability from your data acquisition sys tem DASK kernel drivers now support the revolutionary Windows Vista OS User Mode Kernel Process Structure DASK Kernel Driver a S c 2 3 e mm u H 2 S e I 3 Configuration Plug and Pay Ane x VB NET ce VO Manager File System rmetiovel Figure 1 4 Legacy Software Support Overview NOTE ADLINK strongly recommends installing
40. t Table 4 1 illustrates the relationship of straight binary coding between the digital codes and output voltages Digital Code Analog Output OxFFFF 20V 65535 65536 10V OxC000 5V 0x8001 20V 32769 65536 10V 0x8000 OV 0x4000 5V 0x0000 10V Table 4 1 Bipolar Output Codes Software Update This method is suitable for applications that need to generate D A output controlled by user programs In this mode the D A con verter generates one output once the software command is issued However it would be difficult to determine the software update rate under a multitask OS such as Windows 20 Operation Theory Waveform Generation ADLINK A BA TECHNOLOGY INC o This method is suitable for applications that need to generate waveforms at a precise and fixed rate Various programmable counters will facilitate the generation of complex waveforms with great flexibility Waveform Generation Timing Six counters interact with the waveform to generate different DAWR timing to form various waveforms These are described in Table 4 2 and illustrated in Figure 4 5 start trigger count when re trigger function is enabled Counter Name Width Description Note Ul_counter 32 bit Update Interval Update Interval Defines the update Ul counter Timebase interval between each data output UC counter 32 bit Update Counts When value in Defines the n
41. to have your card re calibrated Calibration 45 A ADLINK BA NOLOGY ING 46 Calibration ADLINK Warranty Policy Thank you for choosing ADLINK To understand your rights and enjoy all the after sales services we offer please read the follow ing carefully 1 Before using ADLINK s products please read the user man ual and follow the instructions exactly When sending in damaged products for repair please attach an RMA appli cation form which can be downloaded from http rma adlinktech com policy 2 All ADLINK products come with a limited two year war ranty one year for products bought in China The warranty period starts on the day the product is shipped from ADLINK s factory gt Peripherals and third party products not manufactured by ADLINK will be covered by the original manufactur ers warranty For products containing storage devices hard drives flash cards etc please back up your data before send ing them for repair ADLINK is not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ADLINK does not condone the use of pirated software and will not service systems using such software ADLINK will not be held legally responsible for products shipped with unlicensed software installed by the user gt For general repairs please do not include peripheral accessories If peripherals need to be included be cer tain to specify w
42. umber of UC_counter is smaller data in a waveform than the size of waveform patterns the waveform is generated piece wisely IC counter 32 bit Iteration Counts Defines how many times the waveform is generated DLY1_counter 32 bit Defines the delay time Delay Time for waveform generation DLY1 counter Clock after the trigger signal Timebase DLY2_counter 32 bit Defines the delay time Delay Time to separate consecutive DLY2 counter Clock waveform generation Timebase This is applicable only in Iterative Waveform Generation mode Trig_counter 32 bit Defines the acceptable Table 4 2 Summary of Counters for Waveform Generation Timebase 80M Operation Theory 21 ADLINK NOTE The maximum D A update rate is 1 MHz and the mini mum setting of Ul counter is 80 4 Update Count and 3 iteration count UC_Counter 4 i P Trigger UNN NAN NANN ee 2 DAWR es i f Delay until Delay until Delay until Lag DLY2 Counter Reach 0 DLY2 Counter Reach 0 DLY1 Counter Reach 0 DA Update Interval T UT Counter Timebase Figure 4 5 Typical D A Timing of Waveform Generation 22 Operation Theory A ADLINK Trigger Modes Post Trigger Generation Use post trigger generation when you want to generate a waveform right after a trigger signal The number of patterns to be updated after the trigger signal is specified by UC_counte
43. ways software poll ing and DMA mode This allows control of the D A update rate by either software or hardware timer Architecture Figure 4 2 shows the PCI 6202 DAC structure Two 16 bit D A chips each with two digital to analog converters are available in the card The FIFO module and timing control module are implemented in the FPGA The FIFO module stores the D A data that comes from DMA transfer or software polling The D A data is then latched in the DAC internal register and waits for the data load command while the timing control mod ule handles all update time information For example the ana log output updates data based on the update time interval parameter set by the user The timing block counts down to this parameter When the count down reaches zero the timing block sends the update command to DAC to load data FPGA Trigger Signal Figure 4 2 Block Diagram of D A Conversion Function Hardware controlled Waveform Generation FIFO is a hardware first in first out data queue that holds tem porary digital codes for D A conversion When PCI 6202 oper ates in waveform generation mode the waveform patterns are stored in FIFO with 512 samples Operation Theory A ADLINK Waveform patterns larger than 512 samples are also supported using bus mastering DMA transfer via the PCI controller Data format in FIFO is shown in Figure 4 3 512 Samples Data FIFO 16 Bit Hex Data Format Data Out Data In
44. wo more waveforms 24 Operation Theory A ADLINK After two trigger signals as specified in Trig Counter no more triggers signals will be accepted unless trigger reset command is executed For more information on Iterative Waveform Gen eration that is used in this example refer to the next section 3 update counts and 2 iterations UC_count 3 IC count 2 Trig_count 3 DLY1_count disabled DLY2_count disabled Ignored UC_Counter 3 Le Trigger i ow ULL n n WF in Rrog i oe LAA AA a gt A single waveform Figure 4 8 Post Trigger with Retrigger Generation NOTE Start Trigger signals asserted during the waveform gen eration process will be ignored Iterative Waveform Generation You can set the IC counter to generate iterative waveforms no matter which trigger mode is used The IC counter stores the iteration number Examples are shown in Figure 4 9 and Figure 4 10 When IC counter is enabled and set to 0 the waveform generation will not stop until IC counter is disabled An onboard data FIFO is used to buffer the waveform patterns for waveform generation If the size of a single waveform is smaller than that of the FIFO after initially loading the data from the host computer s memory the data in FIFO will be reused when a single waveform generation is completed and will not occupy the PCI bandwidth afterwards Operation Theory 25 ADLINK PN However if

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