Xilinx UG967 Artix-7 FPGA AC701 Evaluation Kit Getting
Contents
1. UG967_13_112712 Figure 13 Voltage Current and Power Monitoring on AC701 Board Supplies www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design Advanced Bring up with Base Targeted Reference Design Introduction Figure 14 depicts the block level overview of the Artix 7 FPGA base Targeted Reference Design TRD which delivers up to 10 Gb s of performance per direction 64 bits at 800 Mb s 1B B sk AXI MIG 512 bits at 100 MHz UCD90120A AXI VFIFO WR RD 512 bits at 512 bits at 100 MHz 100 MHz PCle IP AXIS IC GTP M2 M1 MO Transceiver 128 bits at 125 MHz PCle x4 Gen2 Link PCle Integrated Endpoint Block x4 Gen2 128 bits at 125 MHz ER um 128 bits at 125 MHz 128 bits at 125 MHz AXI ST 128 bits at 125 MHz Control Path Integrated Blocks T xin Party iP ig Software Driver E Custom RTL Figure 14 Artix 7 FPGA Base TRD Block Diagram MM 512 bits at 100 MHz 50 MHz Domain UG967_14_121912 The intent of this design is to demonstrate a high performance data transfer system using the PCI Express x4 GEN2 endpoint with a high performance scatter gather packet DMA controller from NorthWest Logic and DDR3 64 bit SODIMM memory operating at 800 Mb s Artix 7 FPGA2. UG967_08_111412 Figure 8 Serial Port Setup 6 Select the desired tests to run and observe the test results see Figure 9 Artix 7 FPGA Base TRD 12 www xilinx com UG967 v1 0 January 10 2013 XILINX com2 9600baud Tera Term YT d Basic Hardware Bring up with Built In Self Test File Edit Setup Control Window Help r 2 3 Xilinx Artix 7 FPGA 01 Evaluation Kit hoose Feature to Test est LED Test IIC Test TIMER Test ROTARY Test SWITCH Test LCD Test DDR3 External Memory Test BRAM Internal Memory Test ETHERNET Loopback Test BUTTON Test xit UG967 09 111412 Figure 9 BIST Main Menu For more information on the BIST software and additional tutorials including how to restore the default content of the on board non volatile storage see the AC701 Evaluation Kit at www xilinx com ac701 Artix 7 FPGA Base TRD www xilinx com 13 UG967 v1 0 January 10 2013 Chapter 14 XILINX AMS Bring up with the AMS101 Evaluation Card Introduction The Artix 7 XC7A200T 2 FBG676 FPGA features two 1 Mega samples per second MSPS 12 bit Analog to Digital Converters ADCs built into the device for a range of applications including simple analog monitoring to more signal processing intensive tasks such as linearization calibration oversampling and filtering The AC701 Evaluation Kit includes the hardware and software to evaluate the ADC feature The AC701 Eva
3. Hardware Bring up This section details the steps for hardware bring up 1 With the board switched off connect a USB mini B cable into the UART port of the AC701 and the host PC see Figure 4 o o T Ek 5 LAT V 01 1040 00800068058 UG967_04_111412 Figure 4 AC701 Board with UART Digilent JTAG and 12V Adapter Cables Attached 2 Connect the 12V adapter cable 3 Connect the Digilent JTAG cable 4 Switch AC701 Power to ON Artix 7 FPGA Base TRD www xilinx com 9 UG967 v1 0 January 10 2013 Chapter XILINX Install the Silicon Labs UART Device Driver 1 Run the downloaded executable UART USB driver file listed in Hardware Test Setup Requirements see Figure 5 This enables UART USB communications with a host PC Silicon Laboratories 210 YCP Drivers for Windows XP 2003 Server Vista a i xj Welcome to the InstallShield Wizard for Silicon Laboratories CP210x VCP Drivers for Windows XP 2003 Server Vista 7 v6 5 The InstallShield Wizard will copy Silicon Laboratories CP210x VCP Drivers for Windows XP 2003 Server Vista v6 5 onto your computer To continue click Next UG967_05_111412 Figure 5 UART Cable Driver Installation Dialog 2 Set the USB UART connection to a known PORT in the Device Manager a Right click the Computer desktop icon and select Properties b Click Device Manager c Right click the Cypress device in the list and select Properties see F
4. chip included on the AC701 evaluation board o Built in hardware to monitor die temperature by way of a Xilinx Analog to Digital Converter 20 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design Test Setup Requirements The prerequisites for testing the design in hardware are e AC701 evaluation board with XC7A200T 2 FBG676 FPGA Design consisting of e Design source files e Device driver files o FPGA programming files o Documentation e Vivado Design Edition v2012 4 e Micro USB cable Fedora 16 LiveDVD e A PC with PCIe v2 1 compliant slot For a complete list of recommended machines and all known issues refer to the Artix 7 FPGA Base Targeted Reference Design Release Notes and Known Issues Master Answer Record at http www xilinx com support answers 53372 htm Note The PC could also have Fedora 16 Linux OS installed Hardware Demonstration Setup This section details the hardware setup and use of the provided control and monitoring application and GUI to assist in getting started quickly with the hardware Step by step explanations are provided on hardware bring up software bring up and the use of the application GUI Board Setup This section details how to set up the AC701 evaluation board as required for demonstrating the TRD Setting the AC701 jumpers and switches l Verify the switch and jumper settings are as shown in Tab
5. Base TRD www xilinx com 19 UG967 v1 0 January 10 2013 Chapter XILINX The PCIe amp endpoint DMA controller together are responsible for the movement of data between a PC and an FPGA S2C implies data movement from a PC to an FPGA and C2S implies data movement from an FPGA to a PC A DDR3 SDRAM 64 bit 800 Mb s or 400 MHz is used for packet buffering a virtual FIFO layer facilitates the use of DDR3 memory as multiple FIFOs Additionally the design provides power monitoring capability based on a PicoBlaze embedded processor For software the design provides 32 bit Linux drivers targeting the Fedora 16 platform and a graphical user interface GUI which controls the tests and monitors the status Features Base Features This section lists the features of the Targeted Reference Design e PCI Express v2 1 compliant x4 endpoint operating at 5Gb s lane direction o PCIe transaction interface utilization monitor o MSI amp Legacy interrupt support e Bus Mastering Scatter gather DMA oe Multi channel DMA o AXI4 Stream interface for data o 14 interface for register space access o DMA performance monitor gt Full duplex operation Independent transmit and receive channels e Virtual FIFO layer over DDR3 memory o Provides 4 channel design 4 FIFOs in DDR3 SODIMM Application Features e PicoBlaze processor based PVT Monitoring e Built in hardware to monitor power by reading the TI UCD90120A power controller
6. Figure 21 shows the content of the a7_base_trd folder File Edit View Go Bookmarks Help Computer W 9 Q Search Home Documents File System configure_ac701 design doc linux_driver_app Trash Network quickstart sh readme txt Browse Net auickstart sh selected 104 bytes UG967 21 111312 Figure 21 Structure of a7 base trd Directory 5 Double click the quickstart sh script as shown in Figure 22 This script sets the proper permissions and invokes the driver installation GUI Select Run in Terminal File Edit View Go Bookmarks Help lt Q Search Computer lt Home Desktop 4 ES Home Documents 9 File System configure_ac701 design doc linux_driver_app Trash F N Network EJ I amp Browse Net quickstart sh readme txt Y Do you want to run quickstart sh or display its contents quickstart sh is an executable text file Run in Terminal Display Cancel quickstart sh selected 104 bytes a UG967_22_111312 Figure 22 Running the quickstart sh Script Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 28 www xilinx com XILINX Advanced Bring up with Base Targeted Reference Design 6 The GUI showing driver installation options appears as shown in Figure 23 Subsequent steps demonstrate the GUI operation by installing and removing drivers Click Install TRD Setup Artix 7 Base TRD Device Memory contro
7. Header 96 Completion Header 0 Posted Data 432 Non Posted Data 16 Completion Data Temperature UG967_25_111312 Figure 25 Control and Monitoring Interface Table 5 Control and Monitoring Interface Components Callout Component Component Description y Indicates DDR3 calibration information Green on calibration red 1 Led Indicator otherwise 2 Test Option Options to select Loopback HW Generator or HW checker Packet size for the test run with allowed packet size shown as a tool 3 Packet size tip 4 Test start stop control Button to control the start and end of the test 32 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design Table 5 Control and Monitoring Interface Components Cont d Callout Component Component Description Throughput Gbps DMA payload throughput in gigabits per second for transmit and receive controllers DMA Active Time ns The time in nanoseconds that the DMA controller has been active in the last second DMA Wait Time ns The time in nanosecond that the DMA controller waited for the software to provide more descriptors BD Errors Indicates a count of buffer descriptors BD that 5 DMA statistics caused a DMA error as indicated by the error status field in the descriptor update BD Short Errors Indicates a short error in the buffer descriptors in the transmit direction when
8. Installed in a PCle x16 Connector 2 Connectthe 12V ATX power supply 4 pin connector to the board as shown in Figure 17 Note A 6 pin ATX supply cannot be connected directly to the AC701 board A 4 pin adapter is necessary in this instance Artix 7 FPGA Base TRD www xilinx com 23 UG967 v1 0 January 10 2013 Chapter XILINX UG967 17 121412 Figure 17 Power Supply Connection 3 To avoid loose contact issues make sure the connections are secure Turn ON the SW15 switch and then apply power to the system 24 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design 4 Check the status of the design using the AC701 board LEDs The design provides status with the GPIO LEDs located on the upper right portion of the AC701 board When the PC is powered on and the TRD has successfully configured the LED status from left to right indicates o LED position 1 ON if DDR3 is calibrated o LED position 2 Heart beat LED flashes if PCIe user clock is present o LED position 3 ON if the lane width is x4 else flashing o LED position 4 ON if the PCIe link is up Figure 18 shows the location of the status LEDs LED Position 1 2 3 4 UG967_18_121812 Figure 18 GPIO LEDs Indicating TRD Status Linux Driver Installation The following sections describe installing the device drivers for the Artix 7 FPGA base TRD after completion of the prior
9. Revision History The following table shows the revision history for this document Date Version Revision 01 10 13 1 0 Initial Xilinx release 2 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Table of Contents REVISION IIS TOMY s esso att 2 Getting Started with the Artix 7 FPGA AC701 Evaluation Kit IMERODUCTION teeta eat Sie bre ene Sn end wean ee ete eee ace 5 Basic Hardware Bring up with Built In lt 7 AMS Bring up with the AMS101 Evaluation Card 14 Advanced Bring up with Base Targeted Reference 19 Appendix A Additional Resources Resources MC 37 Solution Centers 0050000000000 hona RR AAA ETE RRA AAA 37 Further Resources ocio toes ead ANENE REES AERIENE RNE 37 op aie ter ee ea el aes a eee ere nta 38 Appendix B Warranty Artix 7 FPGA Base TRD www xilinx com 3 UG967 v1 0 January 10 2013 XILINX www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Getting Started with the Artix 7 FPGA AC701 Evaluation Kit Introduction The Artix 7 FPGA AC701 Evaluation Kit see Figure 1 provides a comprehensive high performance development and demonstration platfor
10. steps 1 If the Fedora 16 Linux OS is currently installed on the PC boot as a root privileged user and skip to step 4 2 To boot from the Fedora 16 LiveDVD provided in the kit place the DVD in the PC DVD ROM drive The Fedora 16 Live Media is for Intel compatible PCs The DVD contains a complete bootable 32 bit Fedora 16 environment with the proper packages installed Artix 7 FPGA Base TRD www xilinx com 25 UG967 v1 0 January 10 2013 Chapter 26 XILINX for the TRD demonstration environment The PC boots from the DVD ROM drive and logs into a liveuser account This account has kernel development root privileges required to install and remove device driver modules Note It might be necessary to adjust the PC BIOS boot order settings to ensure that the DVD ROM drive is the first drive in the boot order Refer to the PC user manual for the proper procedure to set the BIOS boot order The PC should boot from the DVD ROM drive The images in Figure 19 are seen on the monitor during startup First Screen Last Boot Screen Boot Complete UG967 19 111212 Figure 19 Fedora 16 LiveDVD Boot Sequence 3 After Fedora boots open a terminal window click Activities Application scroll down and click the Terminal icon To determine if the PCIe integrated block is detected at the terminal command prompt type lspci The 1spci command displays the PCI and PCI Express buses of the PC On the bus corresponding
11. to the PCIe connector holding the AC701 board look for the message Memory controller Xilinx Corporation Device 7042 This message confirms that the design programmed into the AC701 board is detected by the BIOS and the Fedora 16 OS The bus number varies depending on the PC motherboard and slot used www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Figure 20 shows an example of the output from the 1spci command The highlighted region shows that Xilinx device 7042 has been located by the BIOS on bus number 3 03 00 0 bus dev function Advanced Bring up with Base Targeted Reference Design File Liveuser localhost lspci 0 Host bridge Intel Corporation 5520 5500 X58 1 0 Hub to ESI Port rev 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A 00 01 B3 07 10 10 14 14 la la lc 16 10 10 ylfs Lx 14 14 19 1 1 lb Low ld ld liveuser localhost x Edit View Search Terminal Help PCI bridge Intel Corporation 5520 5500 X58 1 0 Hub PCI Express Root Port 1 rev 12 PCI bridge Intel Corporation 5520 5500 X58 1 0 Hub PCI Express Root Port 3 rev 12 PCI bridge Intel Corporation 5520 5500 X58 1 0 Hub PCI Express Root Port 7
12. 0 1750 2000 2250 2500 2750 3000 3250 3500 3750 4000 4250 Samples Clock Divider 4 aa Connection Manager Connect Connected Mean 0 00 Std Dev 0 00 Min 0 Max 0 Channel Config Channel Options 9 Single Input Type Bi Polar 5101 Evaluator GUI Figure 11 AMS Evaluator Tool UG967_11_112712 XILINX AMS101 Evaluator Quit Time Domain Frequency Domain Linearity XADC Registers Sensor Data Power Monitor Debug Collect Data Continuous Amplitude dB me 7130 1 1 1 1 1 1 1 1 0 50000 100000 150000 200000 250000 300000 400000 450000 500000 Frequency Hz E oed SNR 64 76 THD 75 19 SINAD 64 30 SFDR 76 01 ENOB 10 39 Fs 5 3 961 54k 9 4096 Window 9 Rectangle Band Bins 5 Connection Manager Connect Connected 701 W 9 t J Ver 1 00 DAC Control Generate Sinewave m Using DAC Single Ended Vp Offset 00 vn Offset E 0 500 Enable Internal Shorting Decimation Value Resolution 1 f 16Bits XADC Control Desired ADC Sample Rate 961 54 S sec Clock Divider El 4 Channel Config Channel Options Jj Single Input Type 9 Bi Polar UG967_12_112712 Figure 12 Fast Fourier Transform Result Artix 7 FPGA Base
13. AC701 Board Features Cont d Callout Component Description 7 Rotary switch under LCD 8 Status LEDs 9 CPU reset button 10 Prog button 11 Power slide switch 12 12V power connector 13 User DIP switch 14 User LEDs 15 User push buttons For a diagram of all features on the AC701 Board see UG952 AC701 Evaluation Board for the Artix 7 FPGA User Guide Hardware Test Setup Requirements The prerequisites for testing the design in hardware are e AC701 evaluation board with XC7A200T 2 FBG676 FPGA e USB to Mini B cable for UART e USB to Micro B JTAG Digilent cable AC Power Adapter 12 VDC e TeraTerm Pro or other terminal program e USB UART drivers from SiLabs Ref 1 Hardware Test Board Setup This section details the hardware setup and use of the terminal program for running the BIST application It details step by step instructions for board bring up 8 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Basic Hardware Bring up with Built In Self Test AC701 Evaluation Board Setup 1 Set all three of the AC701 board SW1 switches to the OFF position as shown in Figure 3 ON Position 1 M2 M1 MO OFF Position 0 UG967_03_111412 Figure 3 SW1 Switch Settings for JTAG Programming Mode Note For this application the board should be set up as a standalone system powered with the AC adapter provided with the AC701 Evaluation Kit
14. Artix 7 FPGA AC701 Evaluation Kit Vivado Design Suite 2012 4 Getting Started Guide UG967 v1 0 January 10 2013 XILINX 0402936 01 XILINX Notice of Disclaimer The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made available AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials with
15. Endpoint Status Host System s Initial Credits Link State Up Posted Header 96 Link Speed 5 Gbps Non Posted Header 96 Link Width x4 Completion Header 0 Interrupts Legacy Vendor ID 0x10ee Device ID 0x7042 Posted Data MPS bytes 128 Non Posted Data MRRS bytes 512 Completion Data Power in Watt Temperature C Time Interval mVCCint NGTvcc mVCCaux mVCCbram UG967_26_111312 Figure 26 Start Data Traffic from GUI 2 Verify TRD operations through the status information provided by the GUI as shown in Figure 10 Verify PCIe endpoint throughput a b Verify the DMA Channel throughput for Datapath 0 p Verify the DMA Channel throughput for Datapath 1 d Verify that there are no buffer descriptor errors for error free operation www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design Artix 7 Base TRD Control amp Monitoring Interface MONO Performance Plots Transmit S2C Performance 11 349 Receive Receive C2S Performance hroughput Gbps Message Log Artix 7 Base TRD v1 0 Test Started for Data Path 0 Test Started for Data Path 1 UG967 27 121812 Figure 27 Verifying Error free Operation and Performance Plots 3 Click the Performance Plots tab The system to card and card to system performance numbers for a specific packet size are shown The packet size can be adjusted and the resulting perfor
16. IST files RDF0220 can be found at www xilinx com ac701 in the Docs amp Designs tab The tutorials and reference designs available on the AC701 Web page can be used to further explore the capabilities of the AC701 and the Artix 7 FPGA For additional information see the Artix 7 Family FPGAs Product Table For the most up to date information on the tutorial content provided with the AC701 Evaluation Kit see the AC701 Reference Design Web page by visiting www xilinx com ac701 and clicking the Docs amp Designs tab www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Basic Hardware Bring up with Built In Self Test Basic Hardware Bring up with Built In Self Test Introduction The BIST tests many of the features offered by the Artix 7 FPGA AC701 Evaluation Kit The test is an available reference design for the AC701 Evaluation Kit and can be programmed into the FPGA via the JTAG interface Figure 2 and Table 1 provide an overview of the board features utilized by the BIST and the AMS101 evaluation card UG967_02_112712 Figure 2 AC701 Board Detail Table 1 AC701 Board Features Callout Component Description 1 USB UART connector Diligent JTAG connector RJ45 Ethernet connector XADC header DDR3 external memory LCD display BI WwW Artix 7 FPGA Base TRD www xilinx com 7 UG967 v1 0 January 10 2013 Chapter XILINX Table 1
17. Intel Corporation 82801JI ICH10 Family USB2 EHCI Controller 1 PCI bridge Intel Corporation 82801 PCI Bridge rev 90 ISA bridge Intel Corporation 82801JIR ICHIOR LPC Interface Controller IDE interface Intel Corporation 82801JI ICH10 Family 4 port SATA IDE Controller 1 3 SMBus Intel Corporation 8280121 ICH10 Family SMBus Controller 5 IDE interface Intal Corpora on 82801JI Sa Family 2 port SATA IDE Controller 2 GeForce 8400 GS rev al 97 FireWire IEEE 1394 Texas Instruments TSB43AB22A IEEE 1394a 2000 Controller PHY Link iOHCI Lynx 3f 00 0 Host bridge Intel Corporation Xeon 5500 Core i7 QuickPath Architecture Generic Non Core Registers rev 05 3f 00 1 Host bridge Intel Corporation Xeon 5500 Core i7 QuickPath Architecture System Address Decoder rev 05 3f 02 0 Host bridge Intel Corporation Xeon 5500 Core i7 QPI Link 0 rev 05 3f 02 1 Host bridge Intel Corporation Xeon 5500 Core i7 QPI Physical rev 05 v 3f 03 0 Host bridge Intel Corporation Xeon 5500 Core i7 Integrated Memory Controller rev 05 UG967 20 121812 Figure 20 PCI and PCI Express Bus Devices 4 Download the reference design from www xilinx com ac701 and copy the a7 base trd folder to the desktop or a folder of choice Note that this operation requires root privileges Double click the copied a7 base trd folder Artix 7 FPGA Base TRD www xilinx com 27 UG967 v1 0 January 10 2013 XILINX Chapter The screen capture in
18. RD UG967 v1 0 January 10 2013
19. TRD www xilinx com UG967 v1 0 January 10 2013 17 Chapter 18 XILINX Power Monitoring In addition to measuring the analog signals from the AMS101 evaluation card the AC701 also uses the XADC as a system monitoring solution for measuring the voltage load current and calculated power for nine of the AC701 board analog power supplies By offering 12 bits 1 MSPS and up to 17 externally multiplexed inputs the XADC is a good solution for monitoring voltage and current on all Artix 7 FPGA applications Figure 13 shows an example of the AC701 monitoring Vecnt VccBRAM and the 1 5V supply In conjunction with the AMS Evaluator the AC701 AMS reference design also measures the voltages current and power for the 1 8V supply the 3 3V supply MGTAVCC and MGTAVTT Entorno A a E XILINX AMS101 Evaluator vas out Time Domain Frequency Domain Linearity XADC Registers Sensor Data Power Monitor Debug Connection Manager C EX Connect Connected a Voltage Current Adc Power W 701 1 00 19 7 VCCINT VCCINT Y VCCAUX Y v 1 5V SUPPLY VCCO_ADJ VCCAUX 178 179 7 D D D 1 11 0 2 40 60 m 100 12 1 8V SUPPLY 3 3V SUPPLY C MGTAVCC MGTAVIT VCCBRAM ae 0 2 4 60 90 100 12 1 5V SUPPLY AES ESS 0 20 40 60 80 100 124 4 60 30 100 124
20. d the sole liability of Xilinx shall be at the option of Xilinx to replace or repair the affected products or to refund to Customer the price of the affected products The availability of replacement products is subject to product discontinuation policies at Xilinx Customer may not return product without first obtaining a customer return material authorization RMA number from Xilinx THE WARRANTIES SET FORTH HEREIN ARE EXCLUSIVE XILINX DISCLAIMS ALL OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY INCLUDING WITHOUT LIMITATION ANY WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT AND ANY WARRANTY THAT MAY ARISE FROM COURSE OF DEALING COURSE OF PERFORMANCE OR USAGE OF TRADE 2008 10 Do not throw Xilinx products marked with the crossed out wheeled bin in the trash Directive 2002 96 EC on waste electrical and electronic equipment WEEE requires the separate collection of WEEE Your cooperation is essential in ensuring the proper management of WEEE and the protection of the environment and human health from potential effects arising from the presence of hazardous substances in WEEE Return the marked products to Xilinx for proper disposal Further information and instructions for free of charge return available at http www xilinx com ehs weee htm Artix 7 FPGA Base TRD www xilinx com 39 UG967 v1 0 January 10 2013 Appendix B Warranty XILINX 40 www xilinx com Artix 7 FPGA Base T
21. g From here click the Collect Data button in the center to quickly evaluate the analog signals in the time and frequency domain display linearity verify the XADC register settings and measure the internal temperature sensor and supply voltages Figure 12 shows the XADC results in the frequency domain The AMS101 evaluation card provides a dual 16 bit DAC for use as an analog test source External analog signals can also be applied to the card For a more extensive explanation of the AMS101 evaluation card and the various functions in the AMS Evaluator tool refer to UG886 AMS101 Evaluation Card User Guide www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX AMS Bring up with the AMS101 Evaluation Card o AMS101 Evaluator GUI e os X E XILINX AMS101 Evaluator Mi Quit Time Domain Frequency Domain Linearity XADC Registers Sensor Data Debug Collect Data Continuous _Raw Results Results _Raw Results i cow 9 Ver 32860 32850 DAC Control 32840 gt ti fused TE ges red z 32830 J 32820 Vp Offset 0 500 Vn 0000 x gt as 79 32810 A m Enable Internal Shorting 5 32800 Decimation Value Resolution 32790 1 16 Bits 32780 32770 XADC Control Clocking 32760 1 r cud Desired ADC Sample Rate 961 54 ise 0 250 500 750 1000 1250 150
22. igure 6 d Click the Port Settings tab then click the Advanced button e Select an open COM port between COM1 and COM4 see Figure 7 Note Steps and diagrams refer to a Windows host PC 10 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Basic Hardware Bring up with Built In Self Test UG967_06_111412 Figure 6 Selecting the Cypress Driver in the Device Manager Advanced Settings for COM11 v UG967 07 111412 Figure 7 Setting the Port for the Cypress Driver Run the BIST Application 1 Download RDF0220 from the web at www xilinx com ac701 under the Docs amp Designs tab 2 Unzip the design files to the directory 3 Open an ISE Design Suite command prompt and type cd C Nac701 bistNready for download Artix 7 FPGA Base TRD www xilinx com 11 UG967 v1 0 January 10 2013 XILINX Chapter ac701_bist bat 4 Start the installed terminal program 5 Select Setup gt Serial Port and ensure that the settings match those shown in Figure 8 Baud Rate 9600 e Data 8 bit o Parity none e Stop 1 bit Flow control none COM2 9600baud Tera Term VT AHK File Edit Setup Control Window Resize Help Tera Term Serial port setup xi Port com E Baud rate 9600 Data 18 bit Cancel Parity none Stop 1 bit y Help Flow control none Transmit delay 0 msec char msecjline
23. ion related to the AC701 board and its documentation is available on these websites Artix 7 FPGA AC701 Evaluation Kit product page www xilinx com ac701 Artix 7 FPGA AC701 Evaluation Kit Master Answer Record http www xilinx com support answers 51900 htm Artix 7 FPGA Base TRD www xilinx com 37 UG967 v1 0 January 10 2013 Appendix A Additional Resources XILINX Artix 7 FPGA Base Targeted Reference Design Release Notes and Known Issues Master Answer Record http www xilinx com support answers 53372 htm Artix 7 FPGA Product Table www xilinx com publications prod_mktg Artix7 Product Table pdf UG476 Artix 7 FPGA GTP Transceivers User Guide UG586 Artix 7 FPGA Memory Interface Solutions UG477 Artix 7 FPGA Integrated Block for PCI Express PG035 LogiCORE IP AXI4 Stream Interconnect PG038 LogiCORE IP AXI VFIFO Controller UG952 AC701 Evaluation Board for the Artix 7 FPGA User Guide UG886 AMS101 Evaluation Card User Guide Vivado Design Suite www xilinx com products design tools vivado index htm UG626 Synthesis and Simulation Design Guide PicoBlaze Documentation and related programming www xilinx com picoblaze WP350 Understanding Performance of PCI Express Systems White Paper References These websites provide supplemental material useful with this guide 1 38 USB UART drivers from SiLabs http www silabs com Support 20Documents Software CP210x_VCP_Win_XP_S2K3_Vi sta_7 exe Fed
24. le 3 Table 4 and Figure 15 Table 3 AC701 Board Required Jumper Settings Jumper Function Setting J12 PCIe endpoint configuration width 4 lane design 3 4 Artix 7 FPGA Base TRD www xilinx com 21 UG967 v1 0 January 10 2013 Chapter 22 XILINX Table 4 AC701 Board Required Switch Settings Switch Function Type Setting SW15 Board power slide switch off SW2 User GPIO DIP switch 4 off off 2 off 1 off SW1 Positions 1 2 and 3 set configuration mode 3 001 Master SPI on 2 101 JTAG off 1 off UG967 15 121912 Figure 15 AC701 Board Switch and Jumper Locations Hardware Bring up All procedures listed in the following sections require super user access on a Linux PC When using the Fedora 16 LiveDVD provided with the kit super user access is granted by default due to the manner in which the kernel image is built If not using the LiveDVD it is important to ensure that super user access is granted www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design 1 With the host PC powered off insert the AC701 board into the selected PCle x4 or wider edge connector see Figure 16 The PCI Express specification allows for a smaller lane width endpoint to be installed into a larger lane width PCIe connector UG967_03_112712 Figure 16 AC701 Board
25. ller Xilinx Corporation Device 7042 Data Verify UG967 23 121812 Figure 23 Artix 7 FPGA Base TRD Driver Installation GUI After installing the driver the control and monitoring user interface appears as shown in Figure 24 The control view shows control parameters such as test mode loopback generator or checker and packet length The system monitor tab shows system power and temperature The GUI also provides an LED indicator for DDR3 memory calibration Artix 7 FPGA Base TRD www xilinx com 29 UG967 v1 0 January 10 2013 Chapter La XILINX Artix 7 Base TRD Control amp Monitoring Interface System Monitor fPERGFRREETPIGES PCle Endpoint Status Host System s Initial Credits E Loopback Data Path 0 HW Checker Packet Size bytes 32768 Link State Posted Header 96 L HW Generator Link Speed Non Posted Header 96 Link Width Completion Header 0 Transmit S2C0 250 interrupts y Throughput Gbps 0 000 0 000 Vendor ID DMA Active Time ns 1000000000 1000000000 Device ID 704 Posted Data DMA Wait Time ns 1000000000 1000000000 MPS bytes Non Posted Data BD Errors 0 0 MRRS bytes 2 Completion Data BD Short Errors 0 0 SW BDs Power in Watt Temperature C PCle Statistics Transmit writes in Gbps 0 000 Receive reads in Gbps 0 000 Loopback Data Path 1 Hw Checker Packet Size bytes 32768 Start 8 Hw Generator Throughput Gbps 0 000 0 000 DMA Active Ti
26. luation Kit also includes voltage current and power monitoring for nine of the analog power supplies on the board For evaluation of Xilinx Analog Mixed Signal AMS capability the following items in the kit are needed e Access to the AC701 board header see Figure 2 AMS101 evaluation card see Figure 10 and Table 1 Design and software files downloaded from the Docs amp Designs tab at www xilinx com ac701 e FPGA design programming files e USB UART drivers from Silicon Labs www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX AMS Bring up with the AMS101 Evaluation Card UG967_10_112712 Figure 10 AMS101 Evaluation Card Table 2 AMS101 Evaluation Card Features Callout Component Description 1 Jumpers to select DAC or external signal source 2 20 pin connector to the header on the 40701 board 3 Pins for external analog input signals 4 Digital I O level translators 5 16 bit DAC to set analog test voltage 6 Reference buffer for DAC Getting Started 1 Verify the USB UART Silicon Labs drivers are installed as described in Install the Silicon Labs UART Device Driver page 10 2 The AMS101 evaluation card requires a Windows host PC to install the National Instruments LabVIEW run time engine Install the AMS101 Evaluator tool by unzipping the AC701 AMS Evaluator installer files from Example Designs on the Docs and Designs tab at www
27. m based on the XC7A200T 2 FBG676 FPGA for high bandwidth and high performance applications in multiple market segments The built in self test BIST and the Artix 7 FPGA Base Targeted Reference Design TRD are developed on this Kit UG967_01_111412 Figure 1 AC701 Evaluation Kit Artix 7 FPGA Base TRD www xilinx com UG967 v1 0 January 10 2013 Chapter XILINX This Getting Started Guide is divided into two sections e Basic Hardware Bring up Enables hands on operation of all the features in the BIST as well as evaluation of Analog Mixed Signal AMS using the AMS101 evaluation card e Advanced Bring up Enables hands on operation with the base TRD which features PCIe DDR3 memory AXI stream interconnect and AXI virtual FIFO controller IP cores all supported through a custom evaluation graphical user interface GUI AC701 Evaluation Kit Contents e AC701 evaluation board featuring the XC7A200T 2 FBG676 FPGA e AMS101 evaluation board Full seat Vivado Design Suite device locked to the Artix 7 XC7A200T 2 FBG676 FPGA e Board Design Files e Schematics e Board layout files o Bill of Materials Documentation o Hardware User Guide o Getting Started Guide Reference Design User Guide e 12V AC adapter Power Supply e Cables o RJ45 Ethernet Cable HDMI cable gt Digilent USB JTAG Cable USB A to USB mini B cable Software and reference designs demos and documents to quickly get started The B
28. maintains a set of circular arrays to hold second by second sampling points of various statistics which are periodically collected by the performance monitor handler The various GUI indicators and controls are detailed in Figure 25 and Table 5 Artix 7 FPGA Base TRD www xilinx com 31 UG967 v1 0 January 10 2013 Chapter Loopback Data Path 0 HW Checker 8 HW Generator Transmit S2C0 250 Throughput Gbps 0 000 DMA Active Time ns 1000000000 DMA Wait Time ns 1000000000 BD Errors 0 BD Short Errors 0 SW BDs 1999 0 000 PCle Statistics Transmit writes in Gbps Loopback Data Path 1 B HW Checker HW Generator Throughput Gbps DMA Active Time ns DMA Wait Time ns BD Errors BD Short Errors SW BDs 0 000 1000000000 1000000000 Message Log Artix 7 Base TRD v1 0 DDR3 Packet Size bytes Receive reads in Gbps Packet Size bytes Artix 7 Base TRD Control amp Monitoring Interface 2 System Monitor Plots PCle Endpoint Status 32768 Type Value Link State Up Link Speed 5 Gbps Link Width x4 Interrupts Legacy Vendor ID 0 10 Device ID 0x7042 MPS bytes 128 MRRS bytes 512 0 000 1000000000 1000000000 Power in Watt 0 000 32768 Transmit S2C1 Receive C2S1 0 000 1000000000 1000000000 Time Interval mVCCint mGTvcc mVCCaux mVCCbram x XILINX Host System s Initial Credits Posted Header 96 Non Posted
29. mance variation observed 4 Close the GUI This uninstalls the driver and opens the driver installation options screen of the Artix 7 FPGA Base TRD Driver un installation requires the control and monitoring GUI to first be closed This completes system performance evaluation of the Artix 7 FPGA Base TRD using the pre built demonstration bit file The reference design can now be modified The Vivado design suite must be installed before proceeding with custom modifications The design tools do not need to be installed on the same host PC in which the AC701 evaluation board is installed Artix 7 FPGA Base TRD www xilinx com 35 UG967 v1 0 January 10 2013 Chapter XILINX 36 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Appendix A Additional Resources Xilinx Resources For support resources such as Answers Documentation Downloads and Forums see the Xilinx Support website at www xilinx com support For continual updates add the Answer Record to your myAlerts www xilinx com support myalerts For a glossary of technical terms used in Xilinx documentation see www xilinx com company terms htm Solution Centers See the Xilinx Solution Centers for support on devices software tools and intellectual property at all stages of the design cycle Topics include design assistance advisories and troubleshooting tips Further Resources The most up to date informat
30. me ns 1000000000 1000000000 DMA Wait Time ns 1000000000 1000000000 BD Errors 0 BD Short Errors SW BDs 1999 Time Interval Message Log Artix 7 Base TRD v1 0 mVCCint NGTvcc mVCCaux mVCCbram Figure 24 Artix 7 FPGA Base TRD Control and Monitoring Interface UG967 24 111312 Using the Application GUI The transmission and reception of data is configured through the application GUI The GUI displays collected statistics and other status information At startup the GUI displays a launching page which detects the PCIe device for this design Vendor ID Ox10EE and Device ID 0x7042 When the appropriate device is detected driver installation is allowed to proceed An additional option is available which allows the enabling of a data integrity check Upon successful installation of the drivers the control and monitoring interface appears 30 www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Advanced Bring up with Base Targeted Reference Design GUI Control Function These parameters are controlled with the GUI e Packet size for traffic generation Test selection e Loopback e HW checker o HW Generator GUI Monitor Function The driver always maintains information about the hardware status The GUI periodically issues an I O Control ioct1 to read the status information which is comprised of e PCIe link and device status DMA controller status Power status The driver
31. ora Project fedoraproject org Northwest Logic DMA Back End Core www nwlogic com packetdma www xilinx com Artix 7 FPGA Base TRD UG967 v1 0 January 10 2013 XILINX Appendix B Warranty THIS LIMITED WARRANTY applies solely to standard hardware development boards and standard hardware programming cables manufactured by or on behalf of Xilinx Development Systems Subject to the limitations herein Xilinx warrants that Development Systems when delivered by Xilinx or its authorized distributor for ninety 90 days following the delivery date will be free from defects in material and workmanship and will substantially conform to Xilinx publicly available specifications for such products in effect at the time of delivery This limited warranty excludes i engineering samples or beta versions of Development Systems which are provided AS IS without warranty ii design defects or errors known as errata iii Development Systems procured through unauthorized third parties and iv Development Systems that have been subject to misuse mishandling accident alteration neglect unauthorized repair or installation Furthermore this limited warranty shall not apply to the use of covered products in an application or environment that is not within Xilinx specifications or in the event of any act error neglect or default of Customer For any breach by Xilinx of this limited warranty the exclusive remedy of Customer an
32. out prior written consent Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http www xilinx com warranty htm IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL SAFE PERFORMANCE SUCH AS APPLICATIONS RELATED TO I THE DEPLOYMENT OF AIRBAGS II CONTROL OF A VEHICLE UNLESS THERE IS A FAIL SAFE OR REDUNDANCY FEATURE WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR OR III USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS Copyright 2012 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Vivado Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries PCI PCI Express PCle and PCI X are trademarks of PCI SIG All other trademarks are the property of their respective owners
33. rev 12 PIC Intel Corporation 5520 5500 X58 Physical and Link Layer Registers Port 0 rev 12 PIC Intel Corporation 5520 5500 X58 Routing and Protocol Layer Registers Port rev 12 PIC Intel Corporation 5520 5500 X58 1 0 Hub System Management Registers rev 12 PIC Intel Corporation 5520 5500 X58 1 0 Hub GPIO and Scratch Pad Registers rev 12 PIC Intel Corporation 5520 5500 X58 1 0 Hub Control Status and RAS Registers rev 12 PIC Intel Corporation 5520 5500 X58 1 0 Hub Throttle Registers rev 12 Ethernet controller Intel Corporation 82567LM 2 Gigabit Network Connection USB Controller Intel Corporation 82801JI ICH10 Family USB UHCI Controller 4 USB Controller Intel Corporation 8280121 ICH10 Family USB UHCI Controller 5 USB Controller Intel Corporation 8280121 ICH10 Family USB UHCI Controller 6 USB Controller Intel Corporation 8280121 ICH10 Family USB2 EHCI Controller 2 Audio device Intel Corporation 82801JI ICH10 Family HD Audio Controller PCI bridge Intel Corporation 82801JI ICH10 Family PCI Express Root Port 1 PCI bridge Intel Corporation 82801JI ICH10 Family PCI Express Port 2 PCI bridge Intel Corporation 82801JI ICH10 Family PCI Express Root Port 5 USB Controller Intel Corporation 82801JI ICH10 Family USB UHCI Controller 1 USB Controller Intel Corporation 82801JI ICH10 Family USB UHCI Controller 2 USB Controller Intel Corporation 82801JI ICH10 Family USB UHCI Controller 3 USB Controller
34. the entire buffer specified by length in the descriptor could not be fetched Not applicable to the receive direction SW BDs Indicates the total count of buffer descriptors set up in the descriptor ring Reports transmitted endpoint card to host throughput as obtained g PEL nites from the PCle endpoint hardware performance monitor 7 Reports received host to endpoint card throughput as obtained Pele Receive treads I Ops from the PCle endpoint hardware performance monitor 8 Message log Text box showing informational messages warnings or errors Click this tab to plot the PCIe transactions on the AXI4 Stream 9 Performance plots interface and show the payload statistics graph based on the DMA controller performance monitor 10 Close button Click this button to close the GUI Reports the contents of various PCIe endpoint configuration fields ia status as reported the endpoint configuration space Initial flow control credits advertised by the host system after link 12 Host System s Initial Credits training with the endpoint A value of zero implies infinite flow control credits Click this button to show a case block diagram of each mode 13 Block diagram button currently running 14 Power statistics Power in Watt plotted for the VCCINT GTVCC VCCAUX and VCCBRAM rails 15 Temperature Monitors the current die temperature Notes 1 Items 2 thro
35. ugh 5 are duplicated for each of the two data paths The GUI was developed using the JAVA environment The Java Native Interface JNI was used to build the bridge between the driver and the GUI This code can also be used with the Windows operating system with only minor changes Artix 7 FPGA Base TRD www xilinx com 33 UG967 v1 0 January 10 2013 Chapter 34 Evaluating the TRD x XILINX 1 To start the data traffic on the two data paths a Click Start on Datapath 0 as shown in Figure 26 This enables the driver to start generating the data for Datapath 0 b Click Start on Datapath 1 as shown in Figure 26 This enables the driver to start generating the data for Datapath 1 Artix 7 Base TRD Control amp Monitoring Interface FJ Loopback Data Path 0 HW Checker Packet Size bytes 32768 L HW Generator Throughput Gbps 0 000 0 000 DMA Active Time ns 1000000000 1000000000 DMA Wait Time ns 1000000000 1000000000 BD Errors 0 0 BD Short Errors 0 0 SW BDs PCle Statistics Transmit writes in Gbps 0 000 Receive reads in Gbps 0 000 Loopback Data Path 1 BB HW Checker Packet Size bytes 32768 8 Hw Generator Transmit S2C1 Receive C2S1 Throughput Gbps 0 000 0 000 DMA Active Time ns 1000000000 1000000000 DMA Wait Time ns 1000000000 1000000000 BD Errors BD Short Errors SW BDs Message Log Artix 7 Base TRD v1 0 f System Monitor PIBES PCle
36. xilinx com ac701 After opening the zip folder click the setup exe file to begin installing the GUI software When loading the National Instruments LabView Artix 7 FPGA Base TRD www xilinx com 15 UG967 v1 0 January 10 2013 Chapter 16 XILINX run time engine click OK to accept the license agreement Running the setup program loads the AMS101 Evaluator GUI with the red Xilinx logo on the desktop 3 After the AMS Evaluator has successfully installed restart the host PC 4 Unzip the AC701 AMS design files from Example Designs on the Docs and Designs tab at the AC701 support page to access the AMS bitstream xadc_eval_design bit Evaluating AMS 1 Connect and apply power to the hardware a b 0 Connect the AMS101 evaluation card to the AC701 board making sure the notch on the XADC header lines up correctly with the connector on the AMS101 evaluation card 2 Download the design to the Artix 7 XC7A200T 2 FBG676 FPGA from the AC701 AMS design files a Open the ChipScope analyzer in the Vivado Design Suite select Flow gt Launch ChipScope Analyzer Click the Open_cable command Select Device choose Configure and click Select New File Open xadc_eval_design bit from the AC701 board AMS design files folder 3 Open the AMS Evaluator tool a Running the setup program loads the AMS101 Evaluator GUI with the red Xilinx logo on your desktop Figure 11 shows the AMS101 Evaluator after openin
Download Pdf Manuals
Related Search