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digital logic simulation and synthesis using modelsim, precision rtl

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1. end count3 architecture rtl of count3 is signal count std_logic_vector 2 downto 0 begin process clk resetn begin if resetn 0 then count lt others gt 0 elsif clk event and clk 1 then if count en 1 then count lt count 1 end if end if end process sum lt not count invert the outputs for the demo board Since its LEDs are active low cout lt 0 when count 7 and count en 1 else 1 end rtl 2a The brute force DO file Create the following DO file in your DO directory called count3 do This is a comment line in a do file add all signals to the Waveform window add wave apply a reset to the counter force resetn 0 force clk O0 force count en 1 run 2 unassert the reset signal and clock for several cycles force resetn run 2 force clk 1 run 2 force clk 0 run 2 force clk 1 run 2 force clk O0 run 2 force clk 1 run 2 force clk O0 run 2 force clk 1 run 2 force clk O0 run 2 force clk 1 run 2 force clk 0 run 2 force clk 1 run 2 force clk 0 run 2 force clk 1 run 2 force clk 0 run 2 force clk 1 run 2 force clk O0 run 2 force clk 1 run 2 force clk 0 run 2 This simplistic DO file simply asserts a reset pulse then applies 9 clock pulses in repetition Clearly one would not want to adopt such a manner if it were necessary to simulate a de
2. 9 9 9 9 9 5 Configuration Address 6 Vey Configuration Address 7 a B Bg ar NN eoc J wem cce Select Next 9 Select Finish in the System ACE file Generation Summary 45 v ENS ea IEEE You have entered following information File Type System ACE CF file ace Device Density 128 Mbits Reserved Space O Mbits Total Usable Sp 128 Mbits Collection Nam my_add El Click Finish to start adding device files eoc J Enn _cancer_ 10 Select OK in the Now sart assigning device file to Config Address 0 dialog box 11 Select your full adder negated bit file in the Add Device window and select OPEN Look in Gyne t ted SYNOPSYS_2000 xilinx Full_Adder gt lt ck gr s m C3 Full Add C3 ngo C3 projnav Cd xmsgs full adder_negated bit File name full_adder_negated bit All Design Files bit rbt nky isc bsd Cancel 12 Select OK in the Add Virtex II Pro Virtex4 Object file window 46 47 Add Virtex ll Pro Virtex4 Object Files Virtex Il Pro Virtex4 File Virtex II Pro Virtex4 Configuration File full adder negated bit sR BMM File Add Power PC Software Files 13 Answer No to the Would you like to add another design file to Config Address 0 dialog box 14 Select the gt Generate File in the bottom left portion of the main Impact Window eee Pda lew penses M
3. Ons 8 ns Selected Custom From D ns t4 To 37 ns OK Cancel Figure 6 Setting the Print options To print the file to a printer use the Linux command Ipr Pprinter name filename where printer name is the name of the printer you wish to print to To quit the simulator select File gt Quit from the Simulation window This concludes this introductory example Example 2 Simulating a two input and gate using a DO file Entering commands through the simulator prompt can be tedious especially if it necessary to enter the commands a number of times It is possible to store theses commands in a file and have the simulator read and execute these commands from the file This example makes use of the same and2 gate vhd file but uses a DO file to store the commands in Create a subdirectory called DO within your Modelsim directory and within this subdirectory cre ate a text file called and2 do containing the following add wave in 1 add wave in 2 add wave output force in 1 O0 force in_2 0 run 2 force in 1 0 Force cn 2 1 run 2 force in 1 1 force in 2 O0 run 2 Force ane d force in_2 0 run 2 Once can invoke the simulator specifying that it should read and execute the contents of a specific DO file using the following syntax ted deadflowers Code 5 59pm gt vsim do DO and2 do and2 gate amp The do command line option is used to specify the path to the DO file to be read in The is
4. Tip of the Day window Click on the Close button in the Tip of the Day window 4 Select the New Project icon and fill out the New Project form specifying the following Project Name Full_Adder_Test Project Folder nfs home first_letter_of_first_name your_login_name Modelsim FPGA_ADV The information in the Create Impl field will change to what you have entered as the Project Name Full_Adder_Test_impl Refer to Figure 11 for the details Click on the OK button once the form has been filled Full_Adder_Test nfs home t ted SYNOPSYS 2000 FPGA 4 Full A amp dder Test i Figure 11 New Project form 5 The next step is to specify the VHDL files which to be synthesized This is performed by 24 selecting the Add Input Files icon which appears in the left hand pane of the main Precision win dow The specified files will be read into memory and used to build a database used by the syn thesis tool Precision will analyze all of the files together consequently the order in which your VHDL files are specified is immaterial Futhermore the top level entity will be automatically detected Selecting the Add Input Files will result in the Open form appearing Specify the full_adder_negated_outputs vhd file in the File field by using the Up arrow yellow folder icon to navigate in your Code directory and select the specified file Click OK Refer to Figure 12 Look in z 3cowc m amp 3 c 3
5. any generated output files For this example the chosen directory name was called my_scr Copy the edf file generated during the running of the precision shell command into this directory It will also be necessary to create any ucf file if you wish to map input output ports to specific pins of the FPGA device on the development board Create a text file in this directory containing the following lines save it with an appropriate name such as counter 3 bit pretty scr bin csh is the line continuation character source CMC EN VIRONMENT xilinx env ngdbuild intstyle ise dd nfs home t ted S YNOPS YS_2000 Xilinx my_scr _ngo V uc counter 3 bit ucf p xc2vp30 ff896 7 counter 3 bit edf counter 3 bit ngd map intstyle ise p xc2vp30 ff896 7 cm area pr b k 4 c 100 tx off o counter 3 bit map ncd counter 3 bit ngd counter 3 bit pcf par w intstyle ise ol std t 1 counter 3 bit map ncd counter 3 bit ncd counter 3 bit pcf trce intstyle ise e 3 13 s 7 xml counter 3 bit twx counter 3 bit ncd o counter 3 bit twr counter 3 bit pcf netgen intstyle ise s 7 pcf counter 3 bit pcf rpw 100 tpw 0 ar Structure xon true w ofmt vhdl sim counter 3 bit ncd counter 3 bit gate vhd bitgen intstyle ise f counter 3 bit ut counter 3 bit ncd Note that in the line ngdbuild intstyle ise dd nfs home U ted SYNOPSYS 2000 Xilinx my scr ngo you should change the specified path name to reflect your actual path to where you h
6. batch file Make sure that you have source the xilinx env file prior to entering this on the command line The impact batch file is a text file containing a list of commands to the impact program This file is exactly the same as the impact cmd file created when running the Impact program in the GUI mode You may simply edit this file to change the relevant paths to the input bit file and other files The contents of the impact batch file used in this example is setPreference pref UserLevel NOVICE setPreference pref MessageLevel DETAILED setPreference pref ConcurrentMode FALSE setPreference pref UseHighz FALSE setPreference pref ConfigOnFailure STOP setPreference pref StartupCLock AUTO CORRECTION setPreference pref AutoSignature FALSE setPreference pref KeepSVF FALSE setPreference pref svfUseTime FALSE setPreference pref UserLevel NOVICE setPreference pref MessageLevel DETAILED setPreference pref ConcurrentMode FALSE setPreference pref UseHighz FALSE setPreference pref ConfigOnFailure STOP 63 setPreference pref StartupCLock AUTO_CORRECTION setPreference pref AutoSignature FALSE setPreference pref KeepS VF FALSE setPreference pref svfUseTime FALSE setMode cf setMode cf setAttribute configdevice attr path value nfs home t ted SYNOPSYS_2000 Xilinx my scr setMode cf setAttribute configdevice attr size value 134217728 setAttribute configdevice attr reseveSize value 0 setAttribute conf
7. directory i e nfs home t ted Modelsim Xilinx Full_Adder If there are any errors or warnings you should consult the log file to determine their cause Most warnings can be safely ignored others merit futher investigation and removal Incidentally the entire Xilinx ISE implementation flow can be executed using a command line interface rather then the GUI method illustrated in this tutorial One can even create a shell script consisting of the appropriate commands and execute this command in the background This can be useful for large designs which may take up to sev eral hours days to implement Essentially the log file indicates the commands and their agru ments as in ngdbuild intstyle ise dd nfs home t ted Modelsim Xilinx Full Adder ngo uc full adder negated ucf p XC2vp30 ff896 7 full adder negated edf full adder negated ngd edif2ngd quiet full adder negated edf ngo full adder negated ngo CMC tools xilinx 7 1i bin sol map ise nfs home t ted Modelsim Xilinx Full Adder Full Adder ise intstyle ise p xc2vp30 ff896 7 cm area pr b k 4 c 100 tx off o full adder negated map ncd full adder negated ngd full adder negated pcf par w intstyle ise ol std t 1 full adder negated map ncd full adder negated ncd full adder negated pcf The actual details may vary but this should be a sufficient starting point for the UNIX gurus to implement their design using the command line interface The Xili
8. illustrate various aspects of the different tools available Most of the tools are available in command line version and also in graphical user interface mode I Setting up the user environment to run the Modelsim VHDL simulation tools Throughout this tutorial the Linux prompt is indicated by ted brownsugar 11 27am gt Your prompt may appear different depending upon the configuration of your account Note also that the Linux hostname brownsugar in the above example changes from section to section in this tutorial as it was developed while running the various software from several different ECE workstations Prior to running the Modelsim tools it is necessary to set up your Linux computer account Per form the following from your Linux prompt Step 1 ted brownsugar 11 27am gt source CMC ENVIRONMENT modelsim env Alternatively one may copy the file CMC ENVIRONMENT synopsys env to one s home directory and source it from there make sure you have the most recent version of the file ted brownsugar 11 27am gt cd ted brownsugar 11 27am gt cp CMC ENVIRONMENT modelsim env ted brownsugar 11 27am gt source modelsim env It is necessary to source the modelsim env file every time you login in or whenever you open a new terminal window Step 2 We will first create a directory called Modelsim and within this directory a subdirectory called Code will be created The Code subdirectory will be used to contai
9. w ofmt vhdl sim counter 3 bit ncd counter 3 bit gate vhd The command extracts design data from NCD NGA NGC NGD or NGO input file and gener ates a VHDL netlist compatible with supported simulation tool The use of gate level simulation is exlained in another section The last command bitgen is used to create the configuration BIT file based on the contents of a physical implementation file NCD The BIT file defines the behavior of the programmed FPGA bitgen intstyle ise f counter_3_bit ut counter_3_bit ncd The f option is used to specify a command file which is used by the bitgen command This com mand file specifies the use of the JtagClk as the StartUp Clock It is necessary that you have a file called counter_3_bit ut in your directory containing the following W g DebugBitstream No g Binary no g CRC Enable g ConfigRate 4 g CclkPin PullUp g MOPin PullUp g MIPin PullUp g M2Pin PullUp g ProgPin PullUp 62 g DonePin PullUp g TckPin PullUp g TdiPin PullUp g TdoPin PullUp g TmsPin PullUp g UnusedPin PullDown g UserID 0xFFFFFFFF g DCIUpdateMode AsRequired g StartUpClk JtagClk g DONE cycle 4 g GTS cycle 5 g GWE cycle 6 g LCK cycle NoWait g Security None g DonePipe No g DriveDone No g Encrypt No III Running the Xilinx Impact tool from the Command Line The command to run the Xilinx Impact tool to generate the SystemAce ace file is impact batch impact
10. 0 FPGA ADV Full Adder impl 1 full adder negated edf cc TRUE nfs home t ted SYNOPSYS 2000 FPGA ADV Full Adder impl 1 full adder negated ucf cc Figure 25 New Project Information window 7 The Project Navigator window will change to that shown in Figure 26 37 aE e Ep my ExENI _ mui Seurces nProea Full_Adder ise B n xcevp30 711896 eM tul adder negated full adder nel ME full_adder_negated uct Processes for Source xc2vp30 71f896 Add Existing Source Nl Create New Source HEHE Design Utilities Figure 26 8 Select the full_adder_negated edf file the file listed beneath xc2vp30 7ff896 You will now note that the Processes for Source xc2vp30 7ff896 have changed to include the Implement Design as shown in Figure 27 mug Module ipii for Source full adder rn Pn Mew Design Summary ar Design Utilities PO 6 Ee wien Command Line Eee F User Constraints i Create Timing Constr KEEN inn Package Pins H create Area Constrai BBB Edit Constraints T exi rc AMEN implement Design mg Process View Figure 27 Process including Implement Design To start the Implement Design process double click on Implement Design Messages indicating 38 the progress of the process will be displayed in the bottom pane of the Project Navigator These messages are also written to a log file __projnav log in your specified Xilinx Project
11. 8 floating_ports_from_signal vhd ss half subtractor an fredkin vhd a haque shift an an fredkin2 vhd an hazard vhd full adder negated outputs vhd n hazard free vhtc an ground wire from signal vhd hazard2 vhd a ground_wire_from_single_variable vhd ai hazard3 vhd a ground_wire_from_ variable vhd a hu_li v ja half_adder_regular_outputs vhd a hu li register v J EX File name frull_adder_negated_outputs Open Files of type synthesis Files v HD vHDL v HO HDL Cancel Figure 12 Open form 6 Repeat the above procedure to add the half adder regular outputs vhd file You will now see that the files you specified are listed in the Project files pane of the main window as shown in Fig ure 13 25 Project Files Desi ee Project Full_S4dder_Test Impl Full Adder Test_impl_l Qunsaved s Input Files eo full_sadder_neqated_autputs vhd amp half_adder_regular_outputs vhd EA Constraint Files a Script Files wa Macro Files Z s Cutput Files on Log File Figure 13 Project files pane of the main Precision window indicating added files 7 The next step is to specifiy the FPGA device you wish to use This is performed by selecting the Setup Design icon Clicking this icon will open the Project Settings form In this form select Xilinx as the technology as shown in Figure 14 Design Frequency m Technology Gl Actel Current Frequency non
12. DIGITAL LOGIC SIMULATION AND SYNTHESIS USING MODELSIM PRECISION RTL AND XILINX ISE Ted Obuchowicz VLSI CAD Specialist Department of Electrical and Computer Engineering Concordia University July 1998 Revised July 2011 Qu 25x File Edit View Add Format Tools Window E Wave tr Wax 59068 2 leggax ups dt k3xii QARA LENIN I U EEEL E AG Home File Edit View it Source Process Window Help IE inoxa PIE PX Pl Blas 8 ma aa d ERES q y FPGA Design Summary Sources for 3 Flinx Xilinx_counter Add Existing Source 0 xc2vp30 7ff896 Create New Source eas 1 am RIMES x View Design summ New ded Save Print Opti Design Utilities File Project Hu ns to EA ns A e erae amp counter 3 it stand f Clocks x Ports Started Launching Design Summary g Nets Instances Processes for count3 Design Overview A Summary A 10B Properties A Timing Constraint i i Ma PPP Eile Edit B m M Net Properties e M Enable Enhanced De r Design Summary E Console Q Errors Warnings i Tcl Shell ja Find in File S reset 20 aclear EN v tiene BE x Eile Edit View Gomi Simulate Add Structure Tools Layout Window Help D BBO OME S Hep A Scan gi H 10052 E E
13. EREER DIP switch in DOWN position produces a logic 1 UP DOWN
14. II Implementation using Xilinx ISE The end result of the steps performed in the previous section was the creation of a netlist file in a format known as Electronic Design Interchange Format EDIF An EDIF file is a netlist of basic logic gates The Xilinx ISE tools use EDIF as one possible input format The steps involved to arrive at a functioning implementation beginning with an EDIF file are summarized below i the EDIF file is converted into a netlist of Xilinx Logic Cells This step is referred to as tech nology mapping or partitioning The mapping also attempts to perform some optimization either in terms of the number of Logic Cells required or timing requirements ii the next step is to place each of the Logic Cells generated from the mapping phase into a spe cific location within the target FPGA Once the Logic Cells have been placed they must be inter connected using the available wiring resources and switches within the FPGA This is referred to as routing iii once a design has been placed and routed a configuration file is created which is used to pro gram the FPGA The Xilinx CAD tools will create a file with a bit extension This file is then used to generate a configuration file using the Xilinx Impact tool I Setting up the user environment to run the Xilinx ISE program Prior to running the Xilinx tools it is necessary to setup the Linux environment to run the Xilinx tools Type the following from the Linux prom
15. L EI z t 80002906 O X Layout Simulate vil q2 00 ColumnLayout kllcolunns Y A H e x lb Processes Active zm a x Y Instance Design unit Design unit type Visibility Total co Name Type filtered State Order Parerr UZ z M ando gate and2_gate Architecture ACCE lt N Q line_11 and2_gate Process ACC lt h W standard standard Package acceetu Bi etd Inanir 1154 etd Innie 1 Parkana 4anneefit TABLE OF CONTENTS Wis Introductio 3 afta tar tel sae adds cela ritos de pad eat centage codo A aa coda ufa tne essit 1 2 Part I VHDL Simulation using MODELSIM 5 eerie enne eae eate ropa e Repo pene 2 I Setting up the user environment to run the Modelsim VHDL BUI AM ise eH T 2 II Performing VHDL simulation using Modelsim eee 3 3 Part II Logie Synthesis with Precision RTL ibtd idit eeoies 20 I Performing Logic Synthesis isccvsacessisageactasaccovasesveacnsyecaceusdeeedenspavaawebenerecessacaaveadoeeers 20 4 Part III Implementation using Xilinx ISE eseeseeeeeeeeeeeeeeeeeneen enne 32 I Setting up the user environment to run Xilinx ISE eee 32 II Implementing a Design with the Xilinx ISE Project Navigator 32 III Using Xilinx Impact to program a Compact Flash card with a System TE TVG d CC 43 5 Part IV Xilinx FPGA Demonstration Board esee 51 I User LEDs and Switc
16. Linux shorthand notation for the parent of the present working directory Alternatively one may save the DO files in any directory and simply specify the complete pathname to the location of the specific DO file The three windows will appear and the simulation will run to completion Zoom to a Full view in the Wave window and you will oberve the same simulation results as obained earlier in Example 1 An alternative method of reading in a DO file is the first load the design into the simulator ted deadflowers Code 5 59pm vsim and2 gate amp and then from the Simulation Transcript window enter the following command do DO and2 do Example 3 Simulating a design consisting of multiple VHDL source code files This example illustrates the use of DO files and also illustrates the use of a multi level hierarchical design style Three separate VHDL source files will be analyzed and the top level entity will make references to the the lower level files The two bottom level files specify the entity archi tecture pairs for an AND gate and a OR gate respectively The top level entity consists of a com binational logic circuit consisiting of two AND gates and a single OR gate 1 Create a file called tedand vhd save it in your Code directory with the following contents entity ted and is port A B in BIT OUTPUT out BIT end ted and architecture ted_arch of ted_and is begin OUTPUT lt A and B after 5 ns end ted_a
17. P2 LED2 R7 LED3 P4 LED4 T2 LEDS R5 LED6 R3 LED7 V1 LED8 T6 Note that the expansion module s LEDs are active LOW Refer to Figure 31 for the numbering of the 8 switches 8 LEDs and the location of the clock pushbutton switch as well as the operation of the DIP switches 54 clock pushbutton E 534 5525 LEDs ZEPPELIN 4 xe 4 56 8 DIP SWITCH 3 g u switch In up postition logic 0 switch In down postion bgk 1 Figure 31 Expansion IO module switch and LED locations Board Documentation Complete documentation and schematics for the XUP Virtex II Pro development board may be found in the directory CMC Xilinx_Boards KUP_V2PRO_BOARD This directory contains Postscript files for HardWare Reference Manual as well as complete sche matic diagrams for the board 55 PART V Command Line Interface This section explains how to use the Precision RTL synthesis Xilinx ISE and Xilinx Impact soft ware tools from the Linux UNIX command line instead of running the software tools through use of the various graphical user interfaces GUIs provided by the software tools Itis very useful to be able to run the tools from the command line for the following reasons e ease of use the same basic steps are performed in the design flow all that changes is the VHDL source code and perhaps some ucf files Xilinx user constraints file and perhaps the target FPGA device The use of UNIX scripts allows for rapid
18. Precision 2005a 11 2 Info Last compiled on Jul 7 2005 22 09 45 Info 4512 Initializing Info 4522 Root Module work full adder negated structural Pre process ing Info 4506 Module work half adder true outputs Pre processing Info 4508 Module work half adder true outputs Compiling Info 4523 Root Module work full adder negated structural Compiling Info 4842 Compilation successfully completed Info 4835 Total CPU time taken for compilation 0 0 secs Info 4856 Total lines of RTL compiled 59 Info 4513 Overall running time 7 0 secs Info Current working directory nfs home t ted SYNOPSYS 2000 FPGA ADV 9 The next step is to synthesize your design Select the Synthesize icon in the left hand pane Synthesis messages will appear in the middle pane You may read them from the precision log file if any errors occur The following are the messages relevant to the Synthesize command from the log file COMMAND synthesize Full Adder Test temp 1 Info 2 Instances are flattened in hierarchical bloc Wwork full adder negated structural Info Starting a constant propagation on the mapped Info Current working directory nfs home t ted SYNOPSYS 2000 FPGA ADV Optimizing design work full adder negated structural netlist 28 Info Writing file nfs home t ted SYNOPSYS 2000 FPGA ADV Full Adder Test temp 1 full adder negated edf Info Writing file nfs
19. al carryl carry2 std logic signal sum int a std logic signal sum_out carry_out std_logic declare configuration specification for hal ha2 half adder use entity WORK half adder true outputs begin component instantiation hal half adder port map inl gt inputl in2 gt input2 carry gt carryl sum gt sum int ha2 half_adder port map inl gt sum_int in2 gt carry_in carry gt carry2 sum gt sum_out carry_out lt carryl or carry2 negate the internal sum and carry to the external port signals since the XUP Virtex2 Pro demo board has active LOW LED outputs DIP switch in UP position will produce a logic 0 value carry out neg not carry out sum out neg lt not sum out end structural 22 2 The next step is to setup your Linux environment to run the Precision RTL synthesis tool This is done by sourcing the setup file CMC ENVIRONMENT fpga_advantage env as shown below Change into you FPGA ADV directory and then source the file ted deadflowers FPGA ADV 12 43pm gt source CMC ENVIRONMENT fpga advantage env After this command is issued you will be returned back to your Linux prompt As a double check to ensure that your environment is configured properly issue the which precision command ted deadflowers FPGA ADV 12 43pm gt which precision encs pkg Precision 2010aU 1 root Mgc_home bin precision Note that this tutorial has been written using versi
20. and produce messages as it proceeds Let us know examine the various commands contained in the script 60 ngdbuild intstyle ise dd nfs home t ted S YNOPS YS_2000 Xilinx my_scr _ngo uc counter_3_bit ucf p xc2vp30 ff896 7 counter_3_bit edf counter_3_bit ngd The ngdbuild command translates and merges the various source files of a design into a single NGD design database this is a binary format used by the Xilinx tools The various command line options are dd output dir Directory to place intermediate ngo files intstyle ise xflow silent Indicate contextual information when invoking Xilinx applications uc ucf file Use specified User Constraint File p partname Use specified part type to implement the design The two input files to ngdbuild are the counter 3 bit ucf and the counter 3 bit edf file produced by precision The end result of executing ngdbuild is the output file counter 3 bit ngd The map command map intstyle ise p xc2vp30 ff896 7 cm area pr b k 4 c 100 tx off o counter 3 bit map ncd counter 3 bit ngd counter 3 bit pcf is used to map the logic gates of the user s design previously written to an NGD file by NGDBUILD into the CLBs and IOBs of the physical device and writes out this physical design to an NCD file The input to the map command is the counter 3 bit ngd file and the outputs produced are the counter 3 bit map ncd and counter 3 bit pcf The par command par w intstyle is
21. are vol software software encs 742391808 439336384 303055424 60 nfs encs dev sdb1 31202 7080 24122 23 media disk One may copy the rev0 ace any other file to the Compact flash card using the cp command as in ted deadflowers revO 6 08pm gt cp revO ace media disk Use the ls command to veirfy that the file has been copied ted deadflowers revO 6 08pm gt ls al media disk total 2856 drwxr xr x 2 ted root 16384 Jul 21 18 08 drwxr xr x 4 root root 4096 Jul 21 17 59 rwxr xr x 1 ted root 1449797 Jul 21 18 08 revO ace IMPORTANT After having copied the System Ace file to to compact flash card it is necessary to use the sync command to flush to file buffer ted deadflowers revO 6 09pm gt sync After the sync it is now safe to remove the CF card from the reader to program the FPGA board If you don t sync after writing to the card the file size on the CF card will be 0 bytes and there will be a SystemAce Error on the FPGA board 51 PART IV Xilinx FPGA Development Board The Xilinx University Program Virtex II Pro development board contains a Virtex II Pro XC2VP30 FPGA device in an FF896 BGA Ball Grid Array package This FPGA device has the equivalent logic capability of approximately 30 000 000 logic gates It contains 13 969 slices a slice contains a RAM look up table which is used to implement combinational logic a slice also contains dedicated flip flops for sequential logic implement
22. ation 428 Kb kilobits of distributed RAM over 2000 Kb of Block RAM and 136 multipliers 18 bit x 18 bit Figure 30 is a top view photo of the XUP Virtex II Pro development system Three high current power supplies with continuous monitoring Vw es HF ci qe UN HORE CTI TET Platform Power uns y A WB SI i AUN VC Flash for connector T ond TOL Jn acm M storing and switch A EE x m i Ld E i Tu FPGA i FF Ar DES i iie d Vis config aano T pe VONT ttt urations XSGA a Video USB2 port Port for FPGA contig uratons Compact SATA y flash card connectors port for for Gigabit gt FPGA serial VO config and Pa removable for Compact 5 storage es B Flash vO 10 100 TN EH f i ore i Ethernet gt i 4 S he r con i Ors fo T K amp thataiaidl inne A ode x 7 mice MAC PHY i 2 I mee tt We ans ue LEONE Gigabit serial VO EC PSi2 d dern od OF acne arms TT TT E mouse and s VIRTEX ii s SPA keyboard 1 pro Li s E eo zae port Stereo A Py laf Additional O MESE m audio via i i E ESA ivia four 60 pinmai 1 n ACST NTMCLELOLEN S UHEEEHEHEHR headers JH paan High speed expansion connector Buttons switches Low speed expansion connector compatible with Diadient boards and LEDs comoatible with Diailent boards Figure 30 XUP Virtex II Pro development system User LEDS and Switches The XUP Virtex II Pro development board contains four user defined LEDs as well as four DIP switches and
23. attempt to describe the source of the error For example suppose that in the line port in 1 in 2 in bit the word bit was misspelled as bitt ted deadflowers Code 2 25pm vcom and2 vhd Model Technology ModelSim SE vcom 6 6d Compiler 2010 11 Nov 1 2010 Loading package standard Compiling entity and2 gate Error and2 vhd 3 vcom 1136 Unknown identifier bitt Error and2 vhd 5 VHDL Compiler exiting If you encounter syntax errors in your VHDL source code correct them and recompile the code The vcom command will compile the VHDL source code and create some intermediate files in the work directory ted deadflowers Code 2 31pm gt cd work ted deadflowers work 2 31pm gt ls al total 20 drwx 4 ted ted 4096 Jul 20 14 30 drwx 3 ted ted 4096 Jul 20 14 29 drwx 2 ted ted 4096 Jul 20 14 30 and2_gate IW 1 ted ted 361 Jul 20 14 30 _info drwx 2 ted ted 4096 Jul 20 14 30 _temp rW l ted ted 26 Jul 20 14 30 vmake 3 The next step is to simulate the VHDL model This is done with the vsim command From the Linux enter ted deadflowers Code 2 33pm gt vsim and2 gate amp The name following the vsim command refers to the entity name that has been compiled into the work library You will see lines similar to the following 1 28373 ted deadflowers Code 2 41pm gt Reading nfs sw cmc linux 32 tools mentor 201 1 modelsim_6 6d modeltech tcl vsim pref tcl Three windows w
24. ave created your Xilinx my scr directory instead of nfs home t ted S YNOPSYS 2000 It is necessary to add execute permission to this file since it will be run as a Unix shell script This is done with the chmod command chmod u x counter 3 bit pretty scr if you perform a UNIX listing of this file you will now see x in the permission triplet 59 ted brownsugar my scr 12 20pm gt ls al counter_3_bit_pretty scr IWX 1 ted ted 833 May 2 11 46 counter 3 bit pretty scr It is also necessary to have a file called counter 3 bit ut in your directory with the following con tents W g DebugBitstream No g Binary no g CRC Enable g ConfigRate 4 g CclkPin PullUp g MOPin PullUp g MIPin PullUp g M2Pin PullUp g ProgPin PullUp g DonePin PullUp g TckPin PullUp g TdiPin PullUp g TdoPin PullUp g TmsPin PullUp g UnusedPin PullDown g UserID 0xFFFFFFFF g DCIUpdateMode AsRequired g StartUpClk JtagClk g DONE_cycle 4 g GTS_cycle 5 g GWE_cycle 6 g LCK_cycle NoWait g Security None g DonePipe No g DriveDone No g Encrypt No This file is needed by the bitgen command its use is explained in a later section You may now run the shell script The tee command is useful for logging the screen output to a text file which may be reviewed once the script has finished its execution ted brownsugar my_scr 12 21pm gt counter_3_bit_pretty scr tee script logfile The script will start to run
25. cal Constraints File not Physical Graffitti Led Zeppelin album title lists the inputs outputs and the physical pinds they are associated with Recall that the ucf file originally specified these locations ted acmilan Full_Adder 11 23am gt more full_adder_negated pcf KKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKEKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Written by Map H 38 on Tue Jun 27 11 01 08 2006 Ck CK Ck Ck CK CI Ck CK C CK CI Ck CK C CK CI C CK CK CI C CK C CC Ck CK CC CK CI Ck CK C CK CI Ck CK C CI Ck S x x KK KG KG kx ko ko kokok SCHEMATIC START COMP carry out neg LOCATE SITE ACA LEVEL 1 COMP sum out neg LOCATE SITE AC3 LEVEL 1 COMP carry in LOCATE SITE AC11 LEVEL 1 E Es COMP input1 LOCATE SITE AD11 LEVEL 1 COMP input2 LOCATE SITE AF8 LEVEL 1 SCHEMATIC END 9 The next step is to generate a bit file This is a special file which is used to program config ure the FPGA A bit file may be downloaded directly to a FPGA board using a special commu nications cable MultiLinx cable or the bit file may be used to produce a configuration file which may be copied onto a Compact Flash card This tutorial will explain the use of program ming the board using the System Ace Compact Flash method VERY IMPORTANT PAY YOUR ATTENTION READ THIS FIRST Prior to generation of the bit file JTAG clock must be s
26. dder Test Gg Impl Full Adder Test impl 1 unsaved Input Files IT Constraint Files 8 Script Files 9 Macro Files Sq Output Files L Log File Warnings 1 Infos 8 RTL Schematic Technology Schematic R Area Report R Timing Report R Timing Violation Report R RTL Constraints Report ZU Fani 6 i2li1z4 Manned 8 Instances Figure 16 Main window after the Synthesize command To view the RTL schematic diagram of your synthesized hardware double click the RTL Sche matic icon in the left hand pane of the middle pane The schematic diagram will appear in the right hand pane of the middle pane as shown in Figure 17 Tools Window Help la x gae e ee Jes foren amp amp e vo Ixi if full adder negated gd Clocks C3 Ports Nets Instances f l eo 4 EE i ES Transcript Design C AQ RTL Desig Input Directory FPGA_ADY Figure 17 RTL Schematic of synthesized hardware 30 The RTL Schematic window is very useful for analyzing and debugging a design if there are errors For example one may locate any net a net in logic synthesis terminology is basically a wire connecting two terminals by selecting the symbol to the eft of the word Nets in the left hand portion of the pane All the nets within the design will be listed You may choose one of these carryl for example The wire corresponding to this net wi
27. e Altera ay Atmel Set Frequency n oo MHz Lattice Remove Frequency amp Constraints ilinx rO constraints tf Current Delay Input Delay none Output none Set Delay input DEIS ns GOPE SEU ns C Remove Delays amp I O Constraints i Bun Retiming DH Cancel Figure 14 Project Settings Form 26 Selecting the symbol to the left of the word Xilinx will list the available Xilinx devices Scroll through this list and select VIRTEX II Pro as the family XC2VP30ff896 as the Device and 7 as the speed grade Click OK after you have specfied the values This is the FPGA used in the devel opment board the lab is equipped with Refer to Figure 15 for the details of this form Technology 4 Design Frequency GPro VIRTEX E Military a C Current Frequency none QPro VIRTEX II Military QPro VIRTEX II Rad Toler Set Frequency 100 MHz SPARTANZ IC Remove Frequency amp Constraints SPARTANZE 3 SPARTANS KO Constraints SPARTANSE Current Delay j VIRTEX Input Delay none Output none VIRTEX E i Set Delay VIRTEX II VIRTEX II Pro Infor pees fo JE VIRTEX IV x a E all SUTHUT ISETRUS p i Balen C Remove Delays amp O Constraints zvPsomsse Speed Grade T Run Retiming ERN Figure 15 Specifying the Family Device and Speed grade 8 You are now ready to compile t
28. e ol std t 1 counter 3 bit map ncd counter 3 bit ncd counter 3 bit pcf is used to places and route a design s logic components mapped physical logic cells contained within a NCD file based on the layout and timing requirements specified within the Physical Con straints File PCF The input files are counter 3 bit ncd and counter 3 bit pcf the output file produced by map is the counter 3 bit map ncd The command line options are w Overwrite Allows overwrite of an existing file ol Overall effort level high is maximum effort Default std standard t Placer cost table entry Start at this entry Default 1 61 The trce command is used to Creates a Timing Report file TWR derived from static timing analysis of the Physical Design file NCD The analysis is typically based on constraints included in the optional Physical Constraints file PCF trce intstyle ise e 3 1 3 s 7 xml counter 3 bit twx counter_3_bit ncd V o counter 3 bit twr counter 3 bit pcf The two input files to trce are counter 3 bit ncd and counter 3 bit pcf The outputs are specified with the xml and o options o report twr optional report output file default design twr xml xmlfile optional XML report output file can be any extension default 1s twx The netgen command is used to create the gate level VHDL simulation file netgen intstyle ise s 7 pcf counter 3 bit pcf rpw 100 tpw O ar Structure xon true
29. e counter force resetn 0 force clk O0 force count_en 1 run 2 unassert the reset signal and clock for several cycles force resetn run 2 force clk 1 2 r 4 force clk 0 4 r 4 run for 9 clock periods 9 clock periods x 4 timesteps per period 36 timesteps run 36 The two force commands make use of the r option which is used to repeat the action The syntax of this force command is force signal name signal value start time r repeat time Thus the first force command will set the clk signal to a value of 1 at a time equal to 2 time units after the current simulation time and this will be repeated at a time commencing at 4 time units after the current simulation time In a similar manner the second force command will set the clk signal to a value of 0 at a time equal to 4 units after the current simulation time and this will be repeated starting at 4 time units after the current simulation time Note that the two force com mands may be combined into one in the following manner force clk 1 2 O 4 r 4 This command forces the signal called clk to a value of 1 at a time value of 2 units after the cur rent simulation time and then it forces the signal to value 0 at a time equal to 4 units after the cur 1 rent simulation time and this cycle is repeated at time 4 units after the current simulation time This method is the most practical for creating a periodic clock signal over many cycles Fig
30. e full_adder_negated mrp file reports the amount of FPGA resources used to implement the design ted acmilan Full_Adder 11 21am gt more full_adder_negated mrp Release 7 11 Map H 38 Xilinx Mapping Report File for Design full adder negated Design Information Command Line CMC tools xilinx 7 1i bin sol map ise nfs home t ted SYNOPSYS 2000 Xilinx Full Adder Full Adder ise intstyle ise p xc2vp30 ff896 7 cm area pr b k 4 c 100 tx off o full adder negated map ncd full adder negated ngd full adder negated pcf Target Device xc2vp30 Target Package ff896 Target Speed EL Stepping Level 0 Mapper Version virtex2p Revision 1 26 6 3 Mapped Date Tue Jun 27 11 00 56 2006 Design Summary 40 Number of errors 0 Number of warnings 1 Logic Utilization Number of 4 input LUTs 2 out of 27 392 1 Logic Distribution Number of occupied Slices 1 out of 13 696 1 Number of Slices containing only related logic 1 out of 1 100 Number of Slices containing unrelated logic 0 out of I 0 See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs 2 out of 27 392 1 Number of bonded IOBs 5 out of 556 1 Number of PPC405s 0 out of 2 0 Number of GTs 0 out of 8 0 Number of GT10s 0 out of 0 0 Total equivalent gate count for design 12 Additional JTAG gate count for IOBs 240 Peak Memory Usage 166 MB The full_adder_negated pcf Physi
31. ed brownsugar 1 23pm gt cd Modelsim ted brownsugar Modelsim 1 23pm gt mkdir FPGA ADV Example 1 Synthesizing a structural VHDL design This example consists of a full adder circuit constructed from two half adders and an OR gate The port map statement is used to instantiate two instances of a half adder component Note that the top level output ports sum out neg carry out neg have been negated since the FPGA board LED s are active LOW this means the LED is illuminated when it is driven by a logic 0 1 Create the following files in your Code directory i a file called half_adder_regular_outputs vhd with the following contents library ieee use ieee std_logic_1164 all entity half_adder is port inl in2 in std logic carry sum out std logic end half adder architecture true outputs of half adder is begin carry inl and in2 21 sum lt inl xor in2 end true outputs i1 a file called full adder negated outputs vhd with the following contents library ieee use ieee std logic 1164 al1 entity full adder negated is port carry in inputl input2 in std logic sum out neg carry out neg out std logic end full adder negateg architecture structural of full adder negated is declare a half adder component component half adder port inl in2 in std logic carry sum out std logic end component declare internal signals used to hook up components sign
32. elected as the Startup Clock see page 3 3 of Impact User s Guide Failure to specify JTAG CLK as the Startup Clock will result in an error during the download of the configuration file to the board See Impact User s Guide page 5 41 6 NOTE THE SAME STARTUP CLOCK RESTRICTIONS THAT APPLY FOR CONFIGUR ING DEVICES WITH A CABLE ALSO APPLY TO ADDING BITSTREAMS TO THE SYS TEM ACE FILES FOR SYSTEM ACE CF ONLY BITSTREAMS WITH STARTUP CLOCK SETTINGS OF BOUNDARY SCAN JTAG CLOCK ARE ALLOWED To specify JTAG clock as the Startup Clock select Generate Programming File from the Processes for Current Source in the Project Navigator window so that it becomes high lighted as shown below eoe i Source full adder ne M Back annotate Pin L T Genera ate Programming File Next select Process from the Project Navigator this will cause a popup menu to appear listing the following choices Run Rerun RerunAll Properties Select Properties from this list The Process Properties window will appear as shown in Figure 28 Select the Startup Options button located at the top left hand side 42 Options Encryption Options J Figure 28 Process Properties window Next select JTAG clock as the FPGA Startup Clock as shown in Figure 29 and click OK uTAGCiock fi L Default NoM ait Figure 29 Specifying JTAG Clock as the Startup Clock Once this Startup Clock has been specified doub
33. five pushbutton switches Note that none of the switches are debounced The LEDs are active LOW Table provides the connections between these LEDs and switches and the FPGA device Table 1 The 4 DIP switches SW 0 SW 3 in Table 1 produce a logic 0 value when placed in the UP position The 5 momentary contact pushbutton switches produce a logic 0 when they are pressed upon otherwise they produce a logic 1 value Thus they are useful for active low reset inputs The 4 LEDs LED 0 LED 3 are active LOW this means that the LED will light up when driven by a logic 0 signal Expansion LEDs and DIP Switches Due to the limited number of available user LEDs and switches on the XUP Virtex II board an expansion input output module was added to the develoment board by our ECE technical team This expansion module consists of a debounced clock implemented with a 555 timer integrated circuit 8 dual inline pin DIP switches and 8 LEDs Table 2 lists the connections between the expansion IO and the FPGA device User LEDs and Switch Connections Device FPGA Pin LED 0 ACA LED 1 AC3 LED 2 AA6 LED 3 AAS SW 0 ACII SW I ADII SW 2 AF8 SW_3 AF9 PB ENTER AG5 PB UP AH4 PB_DOWN AG3 PB_LEFT AHI PB RIGHT AH2 53 Table 2 Expansion IO Connections Device FPGA Pin 555 timer T4 output clock SW_l N5 SW 2 L4 SW_3 N2 SW_4 R9 SW 5 M3 SW 6 Pl SW_7 P7 SW_8 N3 LED1
34. gt New Project from the list of items located across the top of this window The New Project window will appear Specify the following in the New Project window Project Name Full_Adder Project Location specify the full path to your Xilinx directory for example nfs home t ted Modelsim Xilinx Full Adder Top Level Module select EDIF from the list Select Next gt when you have entered the values Refer to Figure 22 for the details of this form 34 Full Adder hisfhomertited SYNOPSYS_2000 xilinx Full_ T3 Figure 22 New Project window 4 You will need to create a User Constraints File in order for the Xilinx ISE tools to associate input output ports in your design with physical pin numbers on the FPGA chip For the purpose of this tutorial create a text file called full adder negated ucf file in the same directory that the Precision RTL tool generated your edf EDIF netlist file The contents of this full adder ne gated ucf file should be CONFIG STEPPING 0 NET carry in LOC AC11 NET inputi LOC AD11 NET input2 LOC AF8 NET carry_out_neg LOC AC4 NET sum_out_neg LOC AC3 Usually such a constraints file is created before one begins implementation with the ISE tools The ucf file tells the ISE implementationt tools that the carry_in input should be mapped to I O pin AC11 of the FPGA device This pin is connected to a user DIP switch on the board Simi larly the two outputs of the full_adder carr
35. he vhd files You will note that there are now two new icons in the main window Compile synthesize Select the Compile icon As the Compile command executes messages will be displaye din the middle pane of the window Observe these messages for any warnings or error messages These messages are also written to a log file with filename precision log within the FPGA ADV direc tory The following is an excerpt of the contents of this log file COMMAND compile Info Reading file nfs software cmc tools MentorB Mgc_home pkgs psr techlib s xcv2p syn Info vhdlorder Release 2005a 11 Info Files sorted successfully Info hdl analyze Release RTLC Precision 2005a 11 I y Code half adder reg ular outputs vhd H Code full adder neg ated outputs vhd H H nfo Curren Full_Adder_Tes ct ct temp 1 Full Adder Test temp 1 Info Finished compiling design compile 27 4 fa_71 Precision nfo 2502 Analyzing input file nfs home t ted SYNOPSYS_2000 FPGA_ADV nfo 2502 Analyzing input file nfs home t ted SYNOPSYS_2000 FPGA_ADV nfo Top of Design has been set to full_adder_negated working directory nfs home t ted SYNOPSYS 2000 FPGA ADV Info RTLC Driver Release RTLC Precision 2005a 11 Info Last compiled on Jul 5 2005 15 52 47 Info 4512 Initializing Info 4504 Partitioning design Info RTLCompiler Release RTLC
36. hes 225 tics orn ope aoi de a io Qu mea i pet uides 52 II Expansion LEDs and DIP Switches coiere ee ee BA ae Meteo 52 MI Board Documentation 1 0 cose eerie eate oerte ede Ut ot ena lee autre 54 6 Part V t Command Line Interface ede oett eese taire pea deibdee bt Siras 55 I Running Precision RTL from the Command Line eee 55 II Running Xilinx ISE from the Command Line eee 58 III Running the Xilinx Impact tool from the Command Line sess 62 Te REFERENCES 3 31 eee etude as pestilens dic deleted sagen aut 64 REVISION HISTORY Sept 7 2001 T Obuchowicz modifications to Dynatext browser information added information on expansion I O July 25 2002 T Obuchowicz modifications to paths of setup files found in CMC EN VIRON MENT instead of home ted EN VIRONMENT removed Dynatext browwer information since it has been replaced by a Web browser interface June 2006 T Obuchowicz complete revision of Part II and Part III and Part IV Part II rewritten for Using Precision RTL for synthesis since Synopsys Design Compiler no longer supports FPGA synthesis Part III rewritten for use with Xilinx ISE Part IV revised for the new XUP Virtex II Pro XC2VP30 board which replaces the XC4010E boards made obsolete due to vendor Mentor no longer supporting techniology libraries for this device family Added a Reference section July 2007 T Obuchowicz added Part V on
37. home t ted SYNOPSYS 2000 FPGA ADV Full Adder Test temp 1 full adder ngated ucf Info Finished synthesizing design nfs home t ted SYNOPSYS 2000 FPGA ADV Full Adder Test temp 1 precision tech sdc synthesize ted brownsugar FPGA ADV 12 46pm gt 10 The last step is to Save the project From the main Precision window select File Save Project The files which have been written into the Full Adder Test temp 1 directory will be copied into the Full Adder Test impl 1 directory The Full Adder Test temp 1 will still exist until you exit from Precision by selecting File Exit answer Yes when prompted Are you sure you want to exit Once you have exited from Precision the Full Adder Test temp 1 will be deleted The end result of the Synthesize command is the generation of an EDIF netlist This is high lighted in the above messages in boldface font In this example the name of the EDIF file is full adder negated edf This is an ASCII text file You should examine the contents of this file so that you become familiar with its contents look in the Full Adder Test impl 1 directory 11 Upon completion of the Synthesize command the middle pane of the main window will appear as shown in Figure 16 29 Xilinx VIRTEX II Pro 2VP3 ffaS6 7 Frequency 100 MHZ Project Files Design Hierarchy full adder negated structural XR amp Clocks m S Ports Sq Project Full amp
38. igdevice attr name value XCCACE128 I addCollection name imp scri addDesign version 0 name rev0 addDeviceChain index 0 setCurrentDesign version 0 addDevice position 1 file nfs home t ted SYNOPSYS_2000 Xilinx my_scr counter_3_bit bit setAttribute configdevice attr path value nfs home t ted SYNOPSYS_2000 Xilinx my scr setMode cf generate active imp scri setMode pff setMode sm setMode cf setMode cf setMode pff setMode sm setMode cf setMode bs setMode ss setMode sm setMode bsfile setMode dtconfig setMode cf setMode mpm setMode pff setMode cf setMode cf quit File names which need to be modified are indicated in bold font The ace file is created and saved in the imp scr revO directory or whichever directory is specified by the addCollection name command contained in the file REFERENCES 1 Modelsim SE Reference Manual v6 6d p 306 2 Precision RTL Synthesis User s Manual Mentor Graphics p 1 1 3 http www digilentinc com 64 65 APPENDIX 1 SWITCH AND LED OPERATION XUP VIRTEX II PRO BOARD DIP SWITHES AND LEDs VCC 3 3V DIP switch in UP position produces a logic 0 value 130 OHM DOWN Ky LED3 LED2 LED1 LEDO DIP switch in DOWN position produces a logic 1 value 4 ACTIVE LOW LEDs EXPANSION IO BOARD SWITCHES AND LEDs ZEPPELIN DIP switch in UP position produces a logic 0 value 8 ACTIVE LOW LEDs 700004020 WERN
39. ill open as shown in Figure 2 These are the Objects window the main Model sim simulation window and and Wave window The Objects windows shows the names and val ues of data objects in the current main simulation window In this example the Objects windows shows the two input ports in_1 and in 2 and the output port and indicates their mode in or out and that they are of type signal Simulation commands are entered in the Transcript portion bot tom portion of the Simulation window and the results are displayed in thwe Waveform window Before entering and simulation commands it is necessary to add any signals you wish to have dis played in the Waveform window This is done by moving the mouse cursor over the Add choice of the top menu bar of the Objects window and selecting Add gt To Wave gt Signals in Region You will now see listed in the Wave window the three ports of the design Refer to Figure 3 File Edit View Add Tools Window a Objects Wave Tools Layout Window O 2 Fs Help Qi 4 HF 100 n ELMS IX 6 8 output Layout Sinulate v comis out amp 11Columns 242 II EN SN File Edit View Add Format Tools Window F Instance Design unit a and2_gate ande gate Q line 3 and2 gate D standard standard if Transcript No
40. inera Hee un peg AG xxi cr e mol ae Thiarniny deen ke Fen la TTE ke a E IMi iA Cerfin E pnma E micum Pike Pirri ayaiahiy Oprane ar HES FES Erg im Carapani Fash Compact Plan iain Ch 48 15 Select OK in the ACE file Generation Option System Ace CF Active Collection Total Collection Number 1 Active Collection my add The ACE file Generation Successful message will be displayed in the main Impact window Select File gt Save Project and then File gt Exit 16 Examine the contents of the directory you specified in step 7 ted acmilan Full Add 12 56pm gt pwd nfs home t ted S YNOPSYS 2000 Xilinx Full Adder Full Add ted acmilan Full Add 12 56pm gt ls al total 16 drwx 3ted ted 4096 Jun 27 12 26 drwx 2ted ted 4096 Jun 27 12 26 revO IW lted ted 81 Jun 27 12 26 xilinx sys ted acmilan Full Add 12 56pm gt cd revO ted acmilan revO 12 57pm gt ls al total 1428 drwx 2ted ted 4096 Jun 27 12 26 drwx 3ted ted 4096 Jun 27 12 26 TW lted ted 1449797 Jun 27 12 26 revO ace The default name of the SystemAce file that Xilinx creates is revO ace If you wish you may copy it to some other file name such as full adder ace This is the file which is to be used to program the FPGA 17 Copy the revO ace to the Compact Flash card and plug the card into the board The board will configure itself from the compact flash card ensure that the
41. lation of VHDL units require that the two files tedand vhd and tedor vhd be compiled prior to the compilation of the file tedcircuit vhd We would compile these three files in the following order ted deadflowers Code 6 18pm gt vcom tedand vhd Model Technology ModelSim SE vcom 6 6d Compiler 2010 11 Nov 1 2010 Loading package standard Compiling entity ted and Compiling architecture ted arch of ted and ted deadflowers Code 6 18pm vcom tedor vhd Model Technology ModelSim SE vcom 6 6d Compiler 2010 11 Nov 1 2010 Loading package standard Compiling entity ted or Compiling architecture ted arch of ted or ted deadflowers Code 6 18pm gt vcom tedcircuit vhd Model Technology ModelSim SE vcom 6 6d Compiler 2010 11 Nov 1 2010 Loading package standard Compiling entity tedcircuit Compiling architecture ted arch of tedcircuit Loading entity ted and Loading entity ted or ted deadflowers Code 6 18pm gt 5 Create a DO file save it in your DO directory called tedcircuit do which contains the fol lowing add all the signals to the wave window add wave setup some input values and run the simulator force a 0 force b O0 force c 0 force run 2 Q e force force force force run 2 aaa force force force force run 2 aaa force force force force run 2 aaow Note how comments within a DO file are specified using the character as the first character of
42. le click on Generate Programming File to gen erate the full_adder_negated bit file The file size should be similar to ted acmilan Full_Adder 11 30am gt ls al bit IW lted ted 1448824 Jun 27 11 56 full adder negated bit You may now select File gt Save All from the Project Navigator and then Exit the application 43 III Using Xilinx Impact to program a Compact Flash card with a System ACE File The Xilinx Impact software will now be used to generate a System ACE file which can be copied to a Compact Flash card The System ACE file contains all the information needed to program the FPGA device It has the added benefit of being non volatile The default configuration mode of the demonstration boards is such that the FPGA configures itself from the Compact Flash card upon power up 1 Source the CMC ENVIRONMENT xilinx env file if you have not already done so ted deadflowers Xilinx 3 29pm gt source CMC ENVIRONMENT xilinx env 2 Change into your Xilinx Full_adder directory and start the Impact software ted deadflowers Xilinx 2 59pm gt cd Full_Adder ted deadflowers Full_Adder 2 59pm gt impact amp Select OK in the The Project Directory is either not writeable or does not exist iMPACT has changed the Project Directory to the current working directory message window if it appears 3 In the Impact Project window select I want to create a new project ipf default ipf and Select OK se
43. ll be highlighted in red in the schematic area of the window as inidicated in Figure 18 m C3 Inputs E Nets t co Carry out 4 Instances Po Carry C3 Outputs Fo carry in gt inputi Fo input Po sum out nec fo carry out nt Fo Carry gt sum int gt sum out Figure 18 RTL Schematic highlighting a chosen net 12 If your design is hierarchical i e it makes us of components and port map statements you may view the hierarchy within the schematic by moving the cursor to an empty area of the sche matic and right clicking with the mouse button and selecting the Show Hierarchy item You may print your schematic to a Postscript file by selecting the yellow printer icon located top left por tion of the main window 31 In the Print form specify Print to File and select OK as shown in Figure 19 A Print to File form will appear specify location and a filename such as Full_Adder_Schematic and click on the Save button A file called Full_Adder_Schematic prn will be created in the location you speci fied This is a Postscript file which may be printed to a laser printer with the Ipr P printer_name command Figure 20 is the schematic diagram of the full adder circuit showing the design hierar chy Generic PostScript Printer cut aum in out cy in gt carry input input gt Figure 20 RTL Schematic of Full Adder circuit showing hierarchy 32 PART I
44. modification of existing scripts so that a new design may be implemented without having to redo the entire setup procedure with the various GUIs scripts execute much faster this is useful for large designs which may require significant pro cessing time to complete scripts may be executed in the background with the UNIX nohup command long synthesis compiles may be run on a fast server without requiring any intervention from the user back ground processes continue to execute even if you logout from the system which you initiated them on This section that the user is familiar with basic UNIX shell scripting If you lack such experience refer to any UNIX guide or textbook I Running Precision RTL from the Command Line Prior to invoking Precision in command line mode it is necessary to source the fpga_advantage env file to setup up the Linux environment A typical command line to setup the environment is make sure you have ssh into a Linux system ted focus FPGA ADV 12 17pm gt source CMC ENVIRONMENT fpga advantage linux env The Precision RTL tool can now be invoked in non GUI mode by using the command precision shell In this mode you can enter commands in an interactive manner For example ted brownsugar FPGA ADV 12 19pm gt precision shell precision WARNING Executing on unsupported platform SunOS 5 9 precision Setting MGC HOME to nfs software cmc tools MentorB 4 fa 71 Preci sion Mgc home Precision S
45. mx I want to C load most recent project E Load most recent project file when iMPACT starts create a new project ipf Browse OK Cancel 4 Select Prepare a System ACE file and select Next in the Welcome to iMPACT window p Please select an action from the list below Ga wWeicome to IMPACT Configure devices using Boundary Scan UTAG C Prepare a PROM File Prepare a System ACE File c Prepare a Boundary Scan File Configure devices 5 Choose Novice as the Operating Mode and select Next 6 Select System ACE CF Size Size 128 MBits and select Next 7 Specify Collection Name and Location Name Full Add give some nice meaningful name Location it will have the path to your Full Adder directory 44 v Ga eo ee ee oi tibt l an 29 77 47 Ne AAddheAMmoommojgm Name Max 8 Characters my_add Location ntsshomestited SYNOPSYS_2000 Xi linx Full Adder Browse m Collection Narne and Location 8 Assign Configuration Address And Design Name Select the Configuration Address 0 tick box v HELIUM UPUrL UE Assign Configuration Address and Design Name Max 8 Characters dP revo ooo Configuration Address 1 Jess Configuration Address 2 pev a Configuration Address 3 es Configuration Address 4 fea Configuration Address 5 kes BB B B 9
46. n available from the tool vendors This tutorial is not meant as a definitive guide to the tools rather it gently introduces the student to the many facets of the tools It is hoped that after having completed the material contained in this guide that the on line vendor documentation will not appear as foreboding and intimidating The tutorial is divided into five parts Part I deals with VHDL simulation using the Modelsim simulator from Mentor Graphics Corporation Part II focuses on logic synthesis the Precision Synthesis software from Mentor Graphics being the tool of choice Part III concerns itself with implementation using the Xilinx ISE software In this section the netlist file obtained as a result of the synthesis step performed in Part II is converted into physical hardware which hopefully functions correctly Part IV gives details of the Xilinx FPGA demonstration board This is the board which will be used to program and test the field programamble gate array Part V describes the use of the Mentor and Xilinx tools using the command line interface The examples in this tutorial were simulated synthesized and downloaded to the FPGA demon stration board using Modelsim SE version 6 6d Precision RTL Synthesis 2010a from Mentor Graphics and Xilinx ISE 9 21 PART I VHDL Simulation using MODELSIM This section explains the use of the Modelsim tools to perform simulation of source code written in the VHDL langauge Several examples will
47. n the VHDL code to be sim ulated and a directory called work which will be used to hold intermediate files created by the simulation tools The work directory will be created using a special Modelsim command the vlib command Figure illustrates the directory hierarchy which will be created home first letterogin name ModelsIm um a subdirectory name my flle vhd Figure 1 Directory hierarchy for VHDL Simulation using Modelsim Issue the following commands from the UNIX prompt ted brownsugar 11 27am gt cd ted brownsugar 11 27am gt mkdir Modelsim ted brownsugar 11 27am gt cd Modelsim ted brownsugar 11 27am gt mkdir Code ted brownsugar 11 27am gt cd Code This sequence of commands will create the Modelsim directory and the Code subdirectory We will now create the work directory used by the simulator ted deadflowers Code 2 17pm vlib work This command will create a subdirectory called work and will create a file called info contain ing some setup information used by the simulator Do not delete the info file as it is needed by the simulator The above steps need only be performed one time This completes the setup for perfroming VHDL simulation using the Modelsim tools In the next section we will present several examples on how to use Modelsim to perform VHDL simulation II Performing VHDL simulation using Modelsim This section will illustrate the use of the Modelsim tools used to perf
48. nds only a small portion of the total number of commands are listed above Information concerning a particular command may be obtained using help command name Precision 3 help add input file add input file Adds a file s to the input files list usage add input file File name s to be added to the list of input files format lt string gt input format vhdl ver ilog edif lsyn lib tcl xnf xdb sdf Default will automatically detect the for mat work lt string gt specify library where design should be stored Default work exclude Exclude this file from the Compile phase reset Reset th xisting list before adding the spec ified file s insert_before lt integer gt Add this file before file number N If not set append the file to the end of the list insert_after lt integer gt Add this file after file number N If not set append the file to the end of the list 57 replace Replace existing file in list with these new settings search_path lt list gt Set the search path for included files compile_time lt integer gt Set the compile timestamp A more general approach is to use the command line to specify a Tcl Tool command language file which consists of various commands to be executed These commands typically set con straints and compile and synthesize the design The following command line is used to specify which Tcl c
49. nx Project directory also contains a number of useful reports giving the device resource utilization and timing values For example the file full adder negated twr gives the following useful information ted acmilan Full Adder 11 16am gt more full adder negated twr Release 7 1i Trace H 38 Copyright c 1995 2005 Xilinx Inc All rights reserved CMC tools xilinx 7 1i bin sol trce ise nfs home t ted SYNOPSYS 2000 Xilinx Full Adder Full Adder ise intstyle ise e 3 1 3 s 7 xml full adder negated full adder negated ncd o full adder negated twr full adder negated pcf Design file full adder negated ncd Physical constraint file full adder negated pcf Device speed xc2vp30 7 PRODUCTION 1 90 2005 01 22 Report level error report 39 Environment Variable Effect NONI No environment variables were set GI INFO Timing 2698 No timing constraints found doing default enumeration INFO Timing 2752 To get complete path coverage use the unconstrained paths option All paths that are not constrained will be reported in the unconstrained paths section s of the report Data Sheet report All values displayed in nanoseconds ns Pad to Pad Source Pad Destination Pad Delay carry_in carry_out_neg 6 044 carry_in sum_out_neg 5 035 inputl carry_out_neg 5 607 inputl sum_out_neg 5 981 input2 carry_out_neg 5 654 input2 sum_out_neg 5 839 H Th
50. ommand file is to be used precision shell file do file tcl In the above command do_file tcl is the name of a text file which contains the following This is a comment line Ted Obuchowicz Feb 21 2007 sample script file Precision Synthesis interprets the backslash as a Tcl escape character so means the command is continued on the next line de db db db db SHE HE new project name Test Script folder NN nfs home t ted SYNOPSYS 2000 FPGA ADV XN createimpl name Test Script impl add input file Code 3 bit counter vhd setup design frequency 100 setup design manufacturer Xilinx family VIRTEX Pro part 2VP30ff896 speed 7 compile synthesize save impl save project exit The end result of executing the precision shell file do file tcl command is the generation of the EDIF netlist in the directory specified by the createimpl name which in this example is the directory called Test Script impl If you wish to view the schematic of your synthesized circuit you may invoke the GUI version of precision and open the appropriate psp file In this example it is the Test Script psp file The next step is to run the Xilinx tools from the Solaris command line to generate the bit and ace files 58 II Running Xilinx ISE from the Command Line Create a subdirectory in your Xilinx directory which will be used to hold files required as input to the Xilinx tools and to save
51. on 7 1 of Precision RTL This may change as newer versions are installed The actual results returned from the which command may vary from the ones given above 3 Invoke the Precision RTL tool ted brownsugar FPGA_ADV 1 24pm gt precision The following will be displayed and two windows shown in Figures 9 and 10 will appear ted deadflowers FPGA_ADV 2 22pm gt precision Setting MGC_HOME to encs pkg Precision 2010aUl root Mgc home precision Executing on platform Scientific Linux SL release 5 5 Boron 2 6 18 238 12 1 el5 1686 ES Fie Edit view Tools Window Help ler xi c amp amp eel e S rmi amp 5 wi Precision Synthesis 2005 69 Production Relea Project f Copyright c Mentor Graphics Corporation 199 Portions copyright 1991 2004 Compuw UNPUBLISHED LICENSED SOE CONFIDENTIAL AND PROPRIETARY INFORMA PROPERTY OF MENTOR GRAPHICS CORPORATIO New Project Rumning on SunOS ted acmilan ece concordia ca Open Project Start time Thu Jun 22 09 52 58 2006 Logging session transcript to file nfs softwar Ready E linput Directory Not Figure 9 Main window for the Precision RTL synthesis tool 23 Tip Of The Day Tip of the Day Enter report constraint from the command line or double click on RTL or Tech Constraints Report icon to see the current design constraints v Show tips at startup Previous Next aose Figure 10
52. orm VHDL simulation The examples will illustrate various features of the tools Example 1 Simulating a 2 input AND gate using the Graphical User Interface 1 Change into your Modelsim Code directory and create a file called and2 vhd with the following contents entity and2 gate is port in 1 in 2 in bit output out bit end architecture example of and2 gate is begin output lt in 1 and in 2 eng You can use any Linux text editor vi emacs nedit gedit etc to create and save this file The next step is to compile the VHDL source file This is a process similar to compiling source code written in a high level programming language such a C or FORTRAN During compila tion of VHDL code any syntactical errors will be reported The Modelsim tool used to compile VHDL source code is called vcom 2 Analyze the and2 vhd file using vcom ted deadflowers Code 2 23pm vcom and2 vhd Model Technology ModelSim SE vcom 6 6d Compiler 2010 11 Nov 1 2010 Loading package standard Compiling entity and2 gate Compiling architecture example of and2 gate ted deadflowers Code 2 24pm gt A small message giving the version number of the tool will be displayed along with some infor mation pertaining to the VHDL code being compiled and you will be returned to theLinux prompt if your code contains no syntax errors If there are syntactical errors in the source code vcom will report the line number and
53. pt ted acmilan 12 58pm gt source CMC ENVIRONMENT xilinx env Note that the above xilinx env file is actually a symbolic link pointing to CMC ENVIRON MENT xilinx 9 2i env The symbolic link xilinx env points to the currently installed and sup ported version of the Xilinx tools Occasionally there may co exist other versions Graduate student researchers may need to run other versions they should refer to the env files found in the directory CMC ENVIRONMENT and source the appropriate file if it exists II Implementing a Design with the Xilinx ISE Project Navigator 1 create a subdirectory called Xilinx from within your Modelsim diretory This directory will be used to hold the intermediate files produced by the Xilinx tools The bit file created during the configuration step will also be saved within the structure of this directory 2 Place and route is performed with the ISE software To start the ISE software type ise from the Linux prompt the amp symbol after the command name will cause the tool to run in the back ground and you will be returned back to the Linux prompt after the window appears ted deadflowers Xilinx 2 35pm gt ise amp 33 3 The Xilinx Project Navigator window will appear as shown in Figure 21 A Tip of the Day window will also appear select OK in it to close the Tip of the Day guste re s em S ixi ee empty Log Figure 21 Xilinx Project Navigator window Select File
54. rch 2 Create a file called tedor vhd with the following VHDL statements in it entity ted_or is port A B in BIT OUTPUT out BIT end ted_or architecture ted_arch of ted_or is begin OUTPUT lt A or B end ted_arch 3 Create a file called tedcircuit vhd with the following contents this will be our top level entity entity tedcircuit is port A B C D in BIT E out BIT end tedcircuit architecture ted_arch of tedcircuit is declare the components found in our entity component ted_and port A B in BIT OUTPUT out BIT end component component ted or port A B in BIT OUTPUT out bit end component declare signals used to interconnect components signal sl s2 BIT declare configuration specification for Ul U3 ted and use entity WORK ted and ted arch for U2 ted or use entity WORK ted or ted arch begin Ul ted and port map A gt A B gt B OUTPUT gt s1 U2 ted_or port map A gt C B gt D OUTPUT gt s2 U3 ted_and port map A gt sl B gt s2 OUTPUT gt E end ted_arch 4 Note how the entity tedcircuit whose architecture is specified in the file tedcircuit vhd makes references to entities whose architecture is specified in a separate file Specifically the two com ponents ted_and and ted_or are specified in two separate files The rules specifying the order of compi
55. re is only one ace file stored in the card The DONE LED on the development board should light up when the FPGA has been configured If there is an error during the programming of the FPGA device ask your lab instruc tor to verify the postion of the DIP switches on the FPGA board 49 18 Under Linux the filesystem for the removable Compact flash card will be automounted only after the icon representing it on the KDE desktop has been selected 32M Removab Use the mouse to select this icon by double clicking and the filesystem called media disk will be mounted In addition a Media window will open Tools Settings anm Location Edit View Go Bookmarks LA MERO Ge et Location media sdb1 T D Home Folder 313 xlsx 9 D 8STUFF amp AdderGeneratorExe amp C9ADMS ALLEGRO Ams EQJANALOGLIB te ANAL TEST C9ANNUAL REPORT D Apollo 4 Home Folder m m m 3 FEES count3 ace 1 4 MB ACE Archive E31 Window Help The df command may be used to verify that the media disk filesystem has been mounted ted deadflowers 6 04pm gt df Filesystem 1K blocks Used Available Use Mounted on dev sda2 9920624 3820496 5588060 41 dev shm 1782792 12 1782780 1 dev shm filer software vol sw cmc 1717986944 294931136 1423055808 18 nfs sw cmc 50 filer users vol users users unix 1760285184 958833056 801452128 55 nfs home filer softw
56. running tools from the UNIX command line Added Part VI on performing gate level simulation August 2007 T Obuchowicz updated Part IV to include expansion IO module pin mapping information March 7 2011 T Obuchowicz updated Part II to reflect the fact that Precision RTL runs only on Linux and is no longer available on Solaris 10 systems July 21 2011 T Obuchowicz updated Part I to account that Synopsys VSS is no longer available under Linux and that Modelsim is the replacement simulator The Solaris systems in H913 have been replaced with Linux systems Updated Part III to account for slight differences in the Xilinx ISE 9 21 GUI for the Impact software INTRODUCTION This tutorial guide is an introduction to digital logic simulation and synthesis using the Mentor Graphics Modelsim and Precision RTL and Xilinx ISE and Impact tools You should have working knowledge of the Linux operating system using text editors copying files creating directories printing etc Knowledge of the VHDL language is not required to complete this tutorial The VHDL code for every example has been included The examples have been kept simple the focus is on learning the tools rather than learning how to write VHDL code There are many fine books dealing with VHDL there are not so many books dealing with simulation and synthesis tools This tutorial attempts to bridge the gap between the novice users knowledge of such tools and the documentatio
57. sign over hundreds of clock cycles there are far easier ways of doing this as shown in 2 b 2 b A DO file which makes use of another DO file Create the following two DO files called clock do and count3b do respectively clock do toggle to clock between 1 and 0 force clk 1 run 2 force clk 0 run 2 count3b do This do file reads in another do file which toggles the clock signal for 9 cycles add all signals to the Waveform window add wave apply a reset to the counter force resetn 0 force clk O0 force count en 1 run 2 unassert the reset signal and clock for several cycles force resetn run 2 do clock do do clock do do clock do do clock do do clock do do clock do do clock do do clock do do clock do Simulate the design ted deadflowers Code 7 20pm gt vsim do DO count3b do count3 amp The first part of this DO file is similar to the brute force one it differs in that it reads in the clock do file 9 times instead of repeating the force clk 1 run 2 force clk O0 run 2 statements explicitly 9 times This is a slight improvement over the brute force method but still awkward to use if it is necessary to simulate a design over many clock cycles 2 c Using a force command with a repeat Create the following DO file called count3c do This is a comment line in a do file add all signals to the Waveform window add wave apply a reset to th
58. sim fand2_gate Figure 4 Issueing a force command from the Simulation window The force command assigns a signal the specified value The signal keeps this value until a new force command sets it to another value The run command advances simulation time by the spec ified number of timesteps Examine the waveform in the Wave window One may zoom to a full view format by selecting View gt Zoom gt Zoom Full from the Wave window Use the force command to set the inputs to their different possible values force in 10 force in 21 run 2 force in 11 force in 20 run 2 force in 11 force in 1 1 run 2 Figure 5 shows the results of the simulation v Ox Eile Edit View Add Format Tools Window ArT UTE x18 cae ee ram fand2 Base 1 fand2 ESI a gt and2 gate output m J J PESTS j Ons to 8 ns Figure 5 The Wave window containing the simulation results 6 To obtain a printout of the Wave window select File gt Print Postscript In the Write Post script window specify whether to print to a printer or to print to a file One can also specify the time range to print Select OK to generate the file Refer to Figure 6 for the details of setting the various print options x Printer Print command lp d lpi File name and2_gate ps Browse Setup Export EPS File Signal Selection Time Range All signals Full Range D ns 8 ns Current view Current view
59. te Vsim 3812 Design is being optin Loading std standard Loading work and2_gate example 1 anm VSIM 1 Now Ons Delta do 0 ns to 12980 ns Figure 2 Modelsim simulation windows v du C File Edit View Add Format Tools Window fand2_gate in_1 fand2_gate in_2 fand2_gate out Figure 3 Wave window after signals have been added 5 One can manually assign values to signals using the force command This command is issued from the Transcript portion of the Simulation window Enter the following commands from the bottom portion of the Simulation window as shown in Figure 4 force in_1 0 force in_2 0 run wv ModelSim SE 6 6d F x File Edit View Compile Simulate Add Transcript Tools Layout Window Help Oy a Help a eism S E d 4 gt EF 100nsi ELE E S 4 PP BR XX WD X6 0X Layout Simulate wj ColumnLayout fietaule Me de vs as amp uj 4 aj Bo RAR HE amp sim He P X BP rocesses Active z gl xI Instance Design unit Design unittype Visibility Total coverage Name Ty and2_gate and2_gate Architecture acc lt n line_g and2_gate Process acc lt n B standard standard Package acc fu uee E amp Transcript SIM 1 gt force in 1 0 VSIM 2 gt force in 2 0 VSIM 32 run 3 VSIM 4 1 Now 3ns Delta 0
60. the line Instead of explicitly adding all the signals one can use the wildcard character to add all the signals contained in a given entity to the Wave window 6 Load the compiled design into the simulator together with the specified DO file ted deadflowers Code 6 25pm gt vsim do DO tedcircuit do tedcircuit amp Figure 7 shows the simulation results for this example File Edit View Add Format Tools Window 5 2 eG UAH b ue ou kd ee HI M Atedcircuit b ftedcircuit c Atedcircuit d ftedcircuit e fedcircuit s1 Aedcircuit s2 ane EOS Figure 7 Simulation results for Example 3 Example 4 Specifying repeating signals When simulating VHDL designs it is often neccessary to specify a repeating pattern for a certain signal such as a clock input to a synchronous system There are several methods of doing so through a DO file This example will illustrate three methods ranging from a brute force approach to a more consice and refined manner The three methos make use of the following VHDL code which describes a simple 3 bit counter with an asynchronous reset active low and a count enable signal 1 Create the following VHDL code in your Code directory with the filename count3 vhd library ieee use ieee std_logic_1164 all use ieee std logic unsigned all entity count3 is port clk resetn count en in std logic sum out std logic vector 2 downto 0 cout out std logic
61. ure 8 shows the simulation results obtained from using the count3c do file File Edit View Add Format Tools Window E dB XE AM I Bea P Bo df doge o Wi Ons to 42 ns Figure 8 Simulation results obtained with the repeated force command 20 PART II Logic Synthesis with Precision RTL In this section we will use the Mentor Graphics Precision RTL tool to perform logic synthesis In synthesis VHDL code will be translated into an EDIF Electronic Design Interface Format netlist file This netlist file can then be used as input to third party implementation tools In this tutorial we will be using the Xilinx ISE tool suite which will perform the translation from EDIF netlist f into an implemented design downloaded to a FPGA development board I Performing Logic Synthesis This section will explain the use of the Precision RTL Synthesis tool from Mentor Graphics Corporation To quote the User s Manual Precision M RTL is a comprehensive tool suite pro viding design capture in the form of VHDL and Verilog entry advanced register transfer logic logic synthesis constraint based optimization and schematic viewing 2 You will have to create a subdirectory called FPGA_ADV from within your Modelsim directory to hold the files created by the Precision RTL synthesis tool This directory may be created in the following manner ted brownsugar Code 1 23pm gt cd this will return you to your home directory t
62. y_out_neg sum_out_neg are mapped to pins AC4 and AC3 which are connected to LEDs on the download board Once you have selected Next gt the New Project form will change and you will be prompted to enter the Input File and the User Constraint File Specify your full_adder_negated edf file and the 35 full_adder_negated ucf file you have created You may use the buttons to the right of each field to browse and select a particular file from your directory structure Select Next gt when you are done Refer to Figure 23 nfs home t ted SYNOPSYS 2000 FPGA AD nfs home t ted SYNOPSYS 2000 FPGA AD ni Figure 23 Specifying the Input File and the User Constraints File 5 You must now specify whcih device you use to use Refer to Figure 24 and specify the follow ing in the form Device Family Virtex2P Device xc2vp30 Package ff896 Speed Grade 7 Top level Module Type EDIF Simulator Other Select Next 36 ffSb amp O o Z J xc2vpao LEES IIIILLLSIIINILULAUGxeneepAAG DCUM Ga GT Mu n Figure 24 Specifying the Device 6 In the New Project Information window select Finish See Figure 25 Lv Device Family Virtex2P Package ff896 Speed Grade 7 Top Level Module Type EDIF Synthesis Tool N A Simulator Other Generated Simulation Language N A Sources TRUE nfs home t ited SYNOPSYS 200
63. ynthesis 2005a 69 Production Release Fri Jul 15 00 30 14 PDT 2005 Copyright c Mentor Graphics Corporation 1996 2005 All Rights Reserved Portions copyright 1991 2004 Compuware Corporation 56 UNPUBLISHED LICENSED SOFTWARE CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS Running on SunOS ted brownsugar ece concordia ca Generic 118558 34 5 9 sun4u Start time Thu Mar 8 12 22 27 2007 Logging session transcript to file nfs home t ted SYNOPSYS_2000 FPGA_ADV precision log Precision 1l Precision 1 The tool displays some messages then issues the prompt Precision 1 You may enter Precision RTL commands at this prompt A very useful command is the help command Precision 2 help activate impl activate the specified implementation add input file Adds a file s to the input files list add macro file Adds macro s file mdb to the macro files list add placement file Adds a physical database pdb fdb pair to the list of physical databases alias define alternative command for a set of command s all clocks list all clocks all inouts list all the inout bidir ports all inputs list all the input ports all outputs list all the output ports The help command lists all the available comma

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