NI 5782R User Manual and Specifications
Contents
1. F 4 NI 5782 Getting Started PXI 795xR Host vi File Edit View Project Operate Tools Window Help l For instructions select Help gt gt Show Context Help and move the cursor over the VI icon to display help for this VI Resource Configuration _ aj Waveform Graph l Analog Input RIO Resource r 0 4 T RIOO Configured 0 9 0 3 Module Coupling D2 Af Ac 01 g 04 L 4 0 l 3 AI Configuration ________ d 01 AI Channel Trigger Level V 0 2 aro Ii Ifo 03 J 04 k l i i 1 I 1 1 1 1 Record Size Trigger Type 0 5E 7 1E 6 1 5E 6 2E 6 2 5E 6 3E 6 3 5E 6 4E 6 4 5E 6 1 Time 1024 S Software j r x r AO Waveform Graph Analot Output J Software Trigger f j 03 AO Configuration 15 AO Channel Signal Type E r TE 2 i 5 Ao0 2 Sine Wave Ea J i J Z Frequency Hz Sampling Info re 1 00m Fs x IZ 0 3 I 1 I 1 I I 1 I 1 I z 500M 0 1E 7 2 7 3E 7 4E 7 5E 7 6E 7 7E 7 8E 7 9E 7 1E 6 EE V i s l Time J lt 500 Error Out J r Generate State status code source 5 r hko A E STOP Output Update Waweform x NI 5782 Getting Started lvproj My Computer lt Creating a LabVIEW Project and Running a VI on an FPGA Target This section explains how to set up your target and create an FPGA VI and a host VI for data communication This section focuses on proper project con2. eee 175 MHz to 250 MHz ADC part number 2 0 0 0 cccceecseseeeeeeeeeeeeees ADS62P49 14 bit resolution dual ADC AC Coupled Specifications Input range normal operating conditions 10 2 dBm 2 05 Vox pk Absolute maximum input ccccceceeeeseeees 50 O 10 V DC 18 dBm 5 Vpk px AC Bandwidth 1 dB ecccceeessseeeeeeeeeeeeees 1 MHz to 250 MHz Bandwidth 3 dB ssncciele siesta cay 0 1 MHz to 500 MHz Table 5 lists the AC coupled spectral performance measurements All values are measured with a 500 MHz internal Sample Clock Table 5 Analog Input AC Coupled Spectral Performance Signal to noise 70 5 dB 70 0 dB 68 8 dB ratio SNR Signal to noise and 70 5 dB 69 8 dB 68 6 dB distortion ratio SINAD Spurious free dynamic range SFDR Channel to channel isolation EMP Zeer a a E gt 90 dB OO ST M Para E ES 90 dB SOT MHZ inne R 70 dB For additional information on the ADS62P49 refer to the Texas Instruments device data sheet at www ti com NI 5782R User Manual and Specifications National Instruments 17 18 Amplitude dBFS Figure 8 Bandwidth Passband Kb b Lo 5 6 7 8 9 10 O 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 Frequency MHz Figure 9 Terminated Input 0 10 20 30 40 G 50 o cm 60 ze 70 80 90 100 110 0 20 40 60 80 100 120 Frequency MHz nicom NI5782R User Manual and Specifications Fig
3. In the Clock Selections category select 200 MHz Clock from the pull down menu for C1k200 Leave Clk40 configured as the Top Level Clock Click OK ae 1 a Note Configuring these clocks is required for proper CLIP operation Refer to the NI 5782 CLIP topics in the NMI FlexRIO Help for more information about configuring your clocks In the Project Explorer window right click the FPGA target and select New VI to open a blank VI Select Window Show Block Diagram to open the VI block diagram In the Project Explorer window expand the IO Module NI 5782 NI 5782 tree view Drag AI 0 Data N 1 to the block diagram Click and drag the bottom edge of the control node to expose the other signals AI 0 N 1 AI 1N Add a Timed Loop structure around the node Wire indicators to each output terminal of the IO Module AI 0 N 1 AI 1 N Right click the input node of the Timed Loop to wire an FPGA Clock Constant to the node Set this constant to IO Module Data Clock Your block diagram should resemble the block diagram in Figure 6 110 Module Data Clock 14 Figure 6 5782SampleAcg FPGA vi Block Diagram ticks O G FEIO Module AI0 N 1 FEIO Module Al0 N brie J I0 Module Al1 N 1 16 1 10 Module Al1 N ni com NI5782R User Manual and Specifications Q Tip Click the Clean Up Diagram button on the toolbar to cleanly organize the VI 16 17 18 19 20 block diagrams Save the VI as 5782SampleAcq FPGA
4. 4 contains information about the possible NI 5782 clock resources Table 4 NI 5782 Clock Sources Internal Clock 500 MHz The internal voltage controlled oscillator VCO acts PLL Off as a free running clock Internal Clock The internal VCO locks to PXI CLK10 through PLL On IoModSyncClock which is available only through loModSyncClock the backplane of NI PXIe 796xR devices Internal Clock 500 MHz The internal VCO locks to an external Reference PLL On Clock 10 MHz Connect the external Reference CLK IN Clock through the CLK IN front panel connector External Clock 250 MHzto Connect an external Sample Clock through the CLK IN 1 GHz CLK IN front panel connector 10 nicom NI5782R User Manual and Specifications Using Your NI 5782R with a LabVIEW FPGA Example VI Ee Note You must install the software before running this example Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for more information about installing your software The NI FlexRIO Adapter Module Support software includes example projects to help you get started creating your LabVIEW FPGA application This section explains how to use an existing LabVIEW FPGA example project to generate and acquire samples with the NI 5782R This example requires at least one SMA cable to connect signals to your NI 5782R ve Note The examples available for your device depend on the version of the software and driver you are using For more informa
5. Two Tone Spectral Measurement 19 5 and 20 5 MHz 10 dBFS dBFS dB Frequency MHz Analog Output AO 0 and AO 1 General Characteristics Number of channels ccccecssessseceeeeeeeees Two single ended simultaneously sampled CONC CUO Ns cvetecennaepassesi es EER SMA Output impedance cccccscccceccceecesessseessseeees 50 Q per connector Sample rate PLEO oae lt 250 MHz PLE ON eea aSa 250 MHz to 1 GHz DAC part numbe ec cceccceesessseeeeeeeeeeeees DAC5682Z 16 bit resolution dual DAC For additional information on the DAC5682Z refer to the Texas Instruments device data sheet at www ti com 22 nicom NI5782R User Manual and Specifications AC Coupled Specifications Output range normal operating conditions 0 5 dBm 0 6 Vpk pk Bandwidth 3 dB 1 MHz to 225 MHz Table 7 SFDR 70 MHz Out 1 GS s no PLL 77 dBc 61 dBc 72 dBc Channel to channel isolation 1s Lerner tree rrr eee err ero ret 100 dB WOO LME pastes ctete tarot cnr eee seeecesteeeecatcte s 90 dB 2A MI eesin tie terete cerca 90 dB Figure 16 Bandwidth Passband Amplitude dBFS on 0 40 80 120 160 200 240 280 320 360 400 440 480 Frequency MHz Includes DAC sinc response NI 5782R User Manual and Specifications National Instruments 23 24 Figure 17 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm 100 Hz Resolution Bandwidth 100 kHz Bandwidth Amplitude dB
6. connector or IoModSyncClock Internal reference type ccceeessseseeeeeeeeeeeees TCXO Internal reference stability ccccececeeeeeees ppm Internal reference frequency default 10 MHz Internal reference phase noise EKZ OSC braiecs setuct caxieids eaeosiiseake eke 137 dBc Hz tO TET OLS Clic apneni 150 dBc Hz LOO KHZ offset caunn ees eacasie 155 dBc Hz CLK IN General Characteristics Number of channels cccccccccccceesssssesssteeees 1 single ended COMMCCIOR secre eit cie EAE SMA Input impedance ea a neces 50 Q Input COuUpIIh G62 eae A ORR AC External Sample Clock Inpotvoltage range norena 0 63 Vok pk to 2 5 Vok pk Input frequency range cceeeesseeseeeeeeeeeeees 250 MHz to GHz Absolute maximum input ccccceseeeeeeeees 10 V DC 3 1 Vpk pk AC Input power 50 0 cccccss cisvacanastiucdesinaceved cette 0 dBm to 12 dBm External Reference Clock Input voltage range onari LFV eoe to 4 4 Vok pk Input frequency range ccceeessssseeceeeeeeeeees 10 MHz Absolute maximum input cccccceececeeeeees 10 V DC 5 V pk pk AC Input power 600 nec E 7 0 dBm to 16 8 dBm l For additional information about the AD9512 refer to the Analog Devices device data sheet at www analog com 2 ToModSyncClock is available only on NI PXIe 796xR FPGA modules NI 5782R User Manual and Specifications National Instruments 29 TRIG General Chara
7. vi Click the Run button LabVIEW creates a default build specification and begins compiling the VI The Generating Intermediate Files window opens and displays the code generation progress Next the Compilation Status window opens and displays the progress of the compilation The compilation takes several minutes Click Close in the Compilation Status window Save and close the VI Save the project Creating a Host VI l 10 11 12 13 14 15 In the Project Explorer window right click My Computer and select New VI to open a blank VI Select Window Show Block Diagram to open the VI block diagram Add the Open FPGA VI Reference function located on the FPGA Interface palette to the block diagram Drag and drop your 5782SampleAcq FPGA vi into the Open FPGA VI Reference The target name appears under the Open FPGA VI Reference function in the block diagram In the block diagram add a While Loop to the right of the Open FPGA VI Reference function Right click the conditional terminal inside the While Loop and select Create Control to create a STOP button on the VI front panel window Add the Read Write Control function located on the FPGA Interface palette inside the While Loop Wire the FPGA VI Reference Out output terminal of the Open FPGA VI Reference function to the FPGA VI Reference In input terminal of the Read Write Control function Wire the error out terminal of the Open FPGA VI Reference function to
8. G e Translator Analog Front End Analog Front End Analog Front End Analog Front End NI 5782R User Manual and Specifications LabVIEW FPGA CLIP SPI Engine Interfacing with AD9512 ADCs DACs Switches Analog front end FE DA Interface Pa c le pa i DIO Port 0 Rd Data lt 0 3 gt DIO Port 1 Rd Data lt 0 3 gt DIO Port 0 Wr Data lt 0 3 gt DIO Port 1 Wr Data lt 0 3 gt PFI lt 0 3 gt Rd Data PFI lt 0 3 gt Wr Data DIO Port lt 0 1 gt Write Enable PFI lt 0 3 gt Write Enable Trigger Input SPI Read SPI Write SPI Address SPI Write Data SPI Read Data SPI Device Select SPI Idle Initialization Done Reinitialize Configuration Error Sample Clock Select Sample Clock Commit Synthesizer Locked Data Clock Al 0 Data N Al 0 Data N 1 Al 1 Data N Al 1 Data N 1 AO 0 Data N AO 0 Data N 1 AO 0 Data N 2 AO 0 Data N 3 AO 1 Data N AO 1 Data N 1 AO 1 Data N 2 AO 1 Data N 3 IOModSyncClock National Instruments 7 NI 5782 Component Level Intellectual Property CLIP The LabVIEW FPGA Module includes component level intellectual property CLIP for HDL IP integration NI FlexRIO devices support two types of CLIP user defined and socketed e User defined CLIP allows you to insert HDL IP into an FPGA target enabling VHDL code to communicate directly with an FPGA VI e Socketed CLIP provides the same IP integration functionality of the use
9. NI 5782R User Manual and Specifications The NI 5782 is an analog dual input dual ouput intermediate frequency IF transceiver adapter module designed to work with your NI FlexRIO FPGA module The NI 5782 features two analog input AI channels with 14 bit sample rates of up to 250 MS s The NI 5782 also has two analog output AO channels with 16 bit sample rates of up to 500 MS s when using both AO channels or up to 1 GS s when using only one AO channel This document contains signal information and specifications for the NI 5782R which is composed of an NI FlexRIO FPGA module and the NI 5782 adapter module This document also contains tutorial sections that demonstrate how to acquire data using a LabVIEW FPGA example VI and how to create and run your own LabVIEW project with the NI 5782R ve Note NI 5782R refers to the combination of your NI 5782 adapter module and your NI FlexRIO FPGA module NI 5782 refers to your NI 5782 adapter module only N Caution The protection provided by the NI 5782R can be impaired if it is used in a manner not described in this document Contents Electromagnetic Compatibility Guidelines 0 0 0 0 cccccccccesssssssseeeeeeeeccesseeesessseeeeeeeeeeseseeeeees 2 How to Use Your NI FlexRIO Documentation Set eecccsscccceeesssseeeeeeeeseseeeeeeesseeensaeeees 3 Font Panel and Connector PMO US arose E 4 Bock D a ae A I NI 5782 Component Level Intellectual Property CLIP ccccceessessecceeeceeeee
10. Refer to Table 3 for the signal list and a descriptions SRS NI 5782 CLK IN 50 Q single ended SE external Reference or Sample Clock input TRIG Trigger input channel 50 Q SE analog input AJ channel 0 50 Q SE AI channel 1 50 Q SE analog output AO channel 0 16 Bit AO Analog I O YS A NI 5782R User Manual and Specifications National Instruments 5 AUX I O Connector Table 3 NI 5782 AUX I O Connector Pin Assignments AUX I O Connector oe ae eee Signal Description a kanaa digital I O DIO data channel Pe ex T oroni rten tarsiers 6 Pio Peni ites SEDO dua el Pe ex T oroni rfesno torsie o Pio pon ie ies SE IO da chs N Caution The AUX I O connector accepts a standard third party HDMI cable but the AUX I O port is not an HDMI interface Do not connect the AUX I O port on the NI 5782 into the HDMI port of another device NI is not liable for any damage resulting from such signal connections 6 nicom NI5782R User Manual and Specifications Block Diagram Figure 3 shows the NI 5782 block diagram and signal flow to and from the NI 5782 component level intellectual property CLIP by way of the adapter module and the corresponding NI 5782 Multiple Sample CLIP in LabVIEW FPGA Figure 3 NI 5782 Connector Signals and NI 5782 CLIP Signal Block Diagram NI 5782 Adapter Module Bus AUX I O Transceiver Internal Reference Clock Switch Clock Synthesizer Bus TRI
11. compliance for the National Instruments global trade compliance policy and how to obtain relevant HTS codes ECCNs and other import export data 2013 National Instruments All rights reserved 373580A 01 Jan13
12. cteristics Number of channels cccccceeeessseeeeeeeeeeeees 1 single ended COMNGCLOR oira a AE SMA Input 1mpedanCe nsf ee len oie 10k kW TPL COUP ING aea DC Maximum Absolute maximum 1nput cccccccccececeeeeeeees 10 V AUX I O Port 0 DIO lt 0 3 gt Port 1 DIO lt 0 3 gt and PFI lt 0 3 gt General Characteristics Number Of Chante Sissies cwneneasaceumenneaes 12 bidirectional 8 DIO and 4 PFI Connector LY PC sinana SE HDMI Interface standard nrosssaon nnua 3 3 V LVCMOS Interface logic Maximum Vt eeneesevtedutasnteocesietnasametiantan 0 8 V Minimu Vjen ee N 0 3 V Minima V erona 2 0 V Maximum Veg eeoieih ante d celedaven de aii 3 6 V Maxaniuii V 6 cccdccietecceetde eee 0 4V Minimum Voperda in ini aA OV Wirt tin Voy scesadetcteadeaveareeysdetteceucesenurest 22 N Maximum Sy pices sae sielec ish ees ai 3 6 V VEE NIVE REI RAIRE T A AE S 50 Q 20 ar 0G kerariorn an e 2 mA Pull down resistor cccccccccscccessseeeesseceessseeeeeas 150kQ Recommended operating voltage 0 0 3 V to 3 6 V Overvoltage protection cccceeeceeeeessteeees 10 V Maximum toggle frequency ccccccccccceeeeeeees 6 6 MHz 30 nicom NI5782R User Manual and Specifications 5 V maximum POWET ccccceeeessssseceeeeeeeeeees 10 mA 5 V voltage tolerance ccccceeesssseeeeeeeeeeees 4 V to 5 0 V EEPROM Byte Address Field Name Vendor ID Product ID Seria
13. eeessesssseeees 8 55 00 015 6 8 001 2a Cables neneman r EEEE E EEEE EET 10 Coel Neea E E ee eee eer A 10 Using Your NI 5782R with a LabVIEW FPGA Example V1 0 ccccccccccccesessesensseeeeeeeeeees 11 Creating a LabVIEW Project and Running a VI on an FPGA Target ceecececceceeeeseteeeeees 13 Appendix A Speci MCatiOns j2czcecessecscascceczsczcnsesecaes cidsccnecissesenadacescccecdsedendtuaaeadectuestieeieteeieeiaes 16 Appendix B Installing EMI Con ols vec dvecscecececereecanecetcendensaacocecendeecsidecetiecadensaeceevietancuedayee 34 Where to Go for SUPP OU sees desccsernserzecasencntacnataadteatestenccetieniotetaectiaqusesoced2anenidcsactdesese Eia 36 Qy NATIONAL p INSTRUMENTS Figure 1 NI FlexRIO Device NI FlexRIO m NI FlexRIO Adapter Module FPGA Module NI FlexRIO Device Note Before configuring your NI 5782R you must install the appropriate software and hardware Refer to the NI FlexRIO FPGA Module Installation Guide and Specifications for installation instructions Figure 1 shows an example of a properly connected NI FlexRIO device Electromagnetic Compatibility Guidelines This product was tested and complies with the regulatory requirements and limits for electromagnetic compatibility EMC as stated in the product specifications These requirements and limits are designed to provide reasonable protection against harmful interference when the product is operated in its intended operational electromagnetic environmen
14. ence NI 5782R User Manual and Specifications National Instruments 11 10 11 12 13 14 12 c Inthe Configure Open FPGA VI Reference dialog box click the Browse button next to the Bitfile button d Inthe Select Bitfile dialog box that opens select the bitfile for your desired target The bitfile name is based on the adapter module example type and FPGA module e Click the Select button f Click OK in the Configure Open FPGA VI Reference dialog box g Save the VI On the front panel in the RIO Resource pull down menu select an NI 5782R resource that corresponds with the target that you configured in step 6 Select AI 0 in the AI Channel control Set the Trigger Level V and the Record Size controls to the desired values In the Trigger Type box select either Software or Data Edge If you select Software the VI acquires data every time you click the Software Trigger button on the front panel of the VI If you select Data Edge the VI acquires data every time an edge occurs Click the Run button to run the VI Click the Software Trigger button if you selected Software in the Trigger Type control The VI acquires data and displays the captured waveform on the Acquired Waveform graph as shown in Figure 5 Click the STOP button to stop the VI Close the VI nicom NI5782R User Manual and Specifications Figure 5 NI 5782 Getting Started Host VI Front Panel
15. figuration proper CLIP configuration and how to access 5782 AI IO nodes For more detailed information about acquiring data on your NI 5782R refer to the device specific examples available in NI Example Finder Creating a Project Launch LabVIEW If LabVIEW is already running select File Create Project 2 Inthe Create Project dialog box select LabVIEW FPGA Project and click Finish In the Create New LabVIEW FPGA Project dialog box select FlexRIO on My Computer and click Next If your FlexRIO device is connected to your system select Discover Existing System If your device is not connected to your system select Create New System and click Next Select your device and click Next NI 5782R User Manual and Specifications National Instruments 13 6 LabVIEW generates a preview of your project Verify that the project is correct and select Finish The new project opens in the Project Explorer window Creating an FPGA Target VI 1 2 3 4 GN y 9 10 11 12 13 14 15 Right click FPGA Target RIOx PXI 79xxR and select New FPGA Base Clock In the Resource pull down menu select 200 MHz Clock and click OK Right click IO Module 5782 in the Project Explorer window and select Properties In the Clock Selections category select 200 MHz Clock from the pull down menu for C1k200 Leave C1k40 configured as the Top Level Clock Select NI 5782 CLIP in the Name list of the Component Level IP pane
16. from the DUT on AI 0 AI 0 N 1 AI 1 N and AI 1 N 1 Click the STOP button on the front panel and close the VI Appendix A Specifications This section lists the specifications of the NI FlexRIO adapter module NI 5782 Pair these specifications with the specifications listed in the M FlexRIO FPGA Module Installation Guide and Specifications For more information about safety and electromagnetic compatibility refer to the Read Me First Safety and Electromagnetic Compatibility document included in your hardware kit or available at ni com manuals AX Caution To avoid permanent damage to the NI 5782 disconnect all signals connected to the NI 5782 before powering down the module and only connect signals after the module has been powered on by the NI FlexRIO FPGA module Note All numeric specifications are typical unless otherwise noted All graphs illustrate the performance of a representative module Specifications are subject to change without notice For the most recent device specifications visit ni com manuals 16 ni com NI5782R User Manual and Specifications Analog Input Al O and Al 1 General Characteristics Number of channels ccccccccccessesessesssseeees Two single ended simultaneously sampled COMMS COL aca tanta ee tea lela aaa SMA Input impedante maisara eles hae 50 Q per connector Sample rate Internal Sample Clock ccceeeeseeeees 250 MHz External Sample Clock
17. ications Caution To ensure the specified EMC performance the length of all I O cables must be no longer than 30 m 100 ft How to Use Your NI FlexRIO Documentation Set Refer to Figure 2 and Table 1 for information about how to use your NI FlexRIO documentation set Figure 2 How to Use Your NI FlexRIO Documentation Set INSTALL Hardware NI FlexRIO FPGA Module and Software Installation Guide and Specifications CONNECT Signals and Learn About Your Adapter Module NI FlexRIO Adapter Module User Guide and Specifications PROGRAM Your NI FlexRIO System in LabVIEW FPGA Module Are You New to LabVIEW FPGA Module NI FlexRIO Help LEARN About LabVIEW FPGA Module Yes LabVIEW Examples LabVIEW FPGA Module Help NI 5782R User Manual and Specifications National Instruments 3 Table 1 NI FlexRIO Documentation Locations and Descriptions oomen tomon escnt O NI FlexRIO FPGA Available in your FPGA Contains installation instructions for your Module Installation module hardware kit from the NI FlexRIO system and specifications for Guide and Start Menu and at ni com your FPGA module Specifications manuals NI 5782R User Available from the Start Menu Contains signal information examples Manual and and at ni com manuals CLIP details and specifications for your Specifications adapter module this document LabVIEW FPGA Embedded i
18. l Number Reserved User Space Caution Only write to User Space Writing to any other offset may cause the NI 5782 to stop functioning Power Power draw W AC coupled build ecccesesessteeeees 4 59 DC coupled build ececceesseeeees 5 26 DC Power Requirements VCCOA UV CE OD ca cel nonune weauan 2 37 V to 2 60 V VEBR ROM yere N 2 50 V to 5 50 V PS BY scasactalacns hassssaicnescoaap E aCe eens 3 09 V to 3 47 V PIV erR 11 12 V to 12 60 V Physical Dimensions eini a tee beaks 11 4 x 10 2 x 2 00 cm 4 5 x 4 0 x 0 8 in Wela Di eck os esp a A east eacoecces 317 5 g 11 2 oz NI 5782R User Manual and Specifications National Instruments 31 Environmental Operating environment eeeeeeeeeees 0 C to 55 C tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 Relative humidity range ccccsessssceceeeeeeees 10 to 90 noncondensing tested in accordance with IEC 60068 2 56 Maximum altitude ccecccceesessseeeeeeeeeeees 2 000 m at 25 C ambient temperature Polution DG OTE C esseen 2 Indoor use only Storage environment Ambient temperature range 0008 20 C to 70 C tested in accordance with IEC 60068 2 1 and IEC 60068 2 2 Relative humidity range cc ceccceeees 5 to 95 noncondensing tested in accordance with IEC 60068 2 56 Ee Note Clean the device with a soft non metallic brush Make sure that the device is completely dry and free from co
19. m 100 110 69 95 69 96 69 97 69 98 69 99 70 70 01 70 02 70 03 70 04 70 05 Frequency MHz Figure 18 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm 1 kHz Resolution Bandwidth 1 MHz Bandwidth Amplitude dBm 69 5 69 6 69 7 69 8 69 9 70 0 70 1 70 2 70 3 70 4 70 5 Frequency MHz ni com NI5782R User Manual and Specifications Figure 19 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm 1 kHz Resolution Bandwidth 100 MHz Bandwidth Amplitude dBm 20 30 40 50 60 70 80 90 100 110 120 Frequency MHz Figure 20 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm 1 kHz Resolution Bandwidth 500 MHz Bandwidth Amplitude dBm O Ol O 10 150 200 250 300 350 400 450 500 Frequency MHz NI 5782R User Manual and Specifications National Instruments 25 DC Coupled Specifications Output range normal operating conditions 4 dBm 1 0 Vpk pk Bandwidth 3 dB eessen DC to 180 MHz Table 8 SFDR 70 MHz Out 1 GS s no PLL 77 dBc 47 dBc 47 dBc Channel to channel isolation ORs AA ee tenet eee res ee 100 dB TO MR e 100 dB 25 LO ME eao e 87 dB Figure 21 Analog Output Bandwidth Passband Amplitude dBFS on 0 40 80 120 160 200 240 280 320 360 400 440 480 Frequency MHz l Includes DAC sinc response 26 nicom NI5782R User Manual and Specifications Figure 22 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm Ampli
20. me samples per clock on each channel This CLIP provides access to two AI channels two AO channels eight bidirectional DIO channels four bidirectional PFI channels and an input clock selector that can be configured to use one of the following settings Internal Sample Clock Internal Sample Clock locked to an external Reference Clock through the CLK IN connector External Sample Clock through the CLK IN connector Internal Sample Clock locked to an external Reference Clock through IoModSyncClock External Sample Clock through IoModSyncClock This CLIP also contains an engine to program the CLK chip ADCs and DACs either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup The NI 5782 Multiple Sample CLIP is the default CLIP NI 5782 Single Sample CLIP The analog input channels generate one sample per clock cycle and the analog output channels generate two samples per clock cycle The default clock rate for the Multiple Sample CLIP is 250 MHz The Sample Clock rates of AI 250 MHz and AO 500 MHz are the same as Multiple Sample CLIP You can set lower sample rates with the external Sample Clock This CLIP presents the data to the diagram at a clock rate such that the ADC data lands at the same rate as the ADC clock However the DAC data must be presented in two time samples per clock on each channel This CLIP provides access to t
21. n LabVIEW Help Contains information about the basic Module Help and at ni com manuals functionality of the LabVIEW FPGA module NI FlexRIO Help Available from the Start menu Contains FPGA module adapter module and at ni com manuals and CLIP configuration information LabVIEW Examples Available in NI Example Contains examples of how to run FPGA VIs Finder and Host VIs on your device ni com ipnet Contains LabVIEW FPGA functions and intellectual property to share NI FlexRIO ni com flexrio Contains product information and data product page sheets for NI FlexRIO devices Front Panel and Connector Pinouts Table 2 shows the front panel connector and signal descriptions for the NI 5782 Refer to Appendix A Specifications for additional signal information AX Caution To avoid permanent damage to the NI 5782 disconnect all signals connected to the NI 5782 before powering down the module and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module J Caution Connections that exceed any of the maximum ratings of any connector on the NI 5782R can damage the device and the chassis NI is not liable for any damage resulting from such signal connections For the maximum input and output ratings for each signal refer to Appendix A Specifications 4 nicom NI5782R User Manual and Specifications Table 2 NI 5782 Front Panel Connectors Device Front Panel Connector Signal Description AUX I O
22. ns e ICES 001 Class A emissions Ve Note Inthe United States per FCC 47 CFR Class A equipment is intended for use in commercial light industrial and heavy industrial locations In Europe Canada Australia and New Zealand per CISPR 11 Class A equipment is intended for use only in heavy industrial locations ve Note Group 1 equipment per CISPR 11 is any industrial scientific or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection analysis purposes ve Note For EMC declarations and certifications refer to the Online Product Certification section of this document CE Compliance CE This product meets the essential requirements of applicable European Directives as follows e 2006 95 EC Low Voltage Directive safety e 2004 108 EC Electromagnetic Compatibility Directive EMC Online Product Certification To obtain product certifications and the Declaration of Conformity for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column Environmental Management NI is committed to designing and manufacturing products in an environmentally responsible manner NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers For additional environmental information refer to the Minimize Our Environmental Impact
23. ntaminants before returning it to service Shock and Vibration Operational SHOCK ccsssccccececeeeeeeeeeeeeeees 30 g peak half sine 11 ms pulse tested in accordance with IEC 60068 2 27 Test profile developed in accordance with MIL PRF 28800F Random vibration ODENA sect tee 5 Hz to 500 Hz 0 3 gms INGHOPETAUNG moreiras e nena 5 Hz to 500 Hz 2 4 gms tested in accordance with IEC 60068 2 64 Nonoperating test profile exceeds the requirements of MIL PRF 28800F Class 3 Safety This product meets the requirements of the following standards of safety for electrical equipment for measurement control and laboratory use e JEC 61010 1 EN 61010 1 e UL61010 1 CSA 61010 1 For PXI PXI Express chassis configurations that group NI FlexRIO adapter modules in three or more contiguous slots National Instruments recommends limiting the ambient operating temperature to less than 50 C 32 nicom NI5782R User Manual and Specifications 4 Note For UL and other safety certifications refer to the product label or the Online Product Certification section Electromagnetic Compatibility This product meets the requirements of the following EMC standards for electrical equipment for measurement control and laboratory use e EN 61326 1 IEC 61326 1 Class A emissions Basic immunity e EN 55011 CISPR 11 Group 1 Class A emissions e AS NZS CISPR 11 Group 1 Class A emissions e FCC 47 CFR Part 15B Class A emissio
24. on you can obtain the calibration certificate for your product at ni com calibration National Instruments corporate headquarters is located at 11500 North Mopac Expressway Austin Texas 78759 3504 National Instruments also has offices located around the world to help address your support needs For telephone support in the United States create your service request at ni com support and follow the calling instructions or dial 512 795 8248 For telephone support outside the United States visit the Worldwide Offices section of ni com niglobal to access the branch office websites which provide up to date contact information support phone numbers email addresses and current events LabVIEW National Instruments NI ni com the National Instruments corporate logo and the Eagle logo are trademarks of National Instruments Corporation Refer to the Trademark Information at ni com trademarks for other National Instruments trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies For patents covering National Instruments products technology refer to the appropriate location Help Patents in your software the patents txt file on your media or the National Instruments Patents Notice at ni com patents You can find information about end user license agreements EULAs and third party legal notices in the NI 5782 Readme Refer to the Export Compliance Information at ni com legal export
25. part number 778700 01 in your PXI chassis 1 Remove the captive screw covers 2 Install the PXI EMC filler panels by securing the captive mounting screws to the chassis as shown in the figure below Make sure that the EMC gasket is on the right side of the PXI EMC filler panel 34 nicom NI5782R User Manual and Specifications Figure 26 PXI EMC Filler Panels and Chassis 1 Captive Screw Covers 2 Captive Mounting Screws 3 EMC Gasket Note You must populate all slots with a module or a PXI EMC filler panel to ensure proper module cooling Do not over tighten screws 2 5 Ib inch maximum For additional information about the use of PXI EMC filler panels in your PXI system visit ni com info and enter emcpanels NI 5782R User Manual and Specifications National Instruments 35 Where to Go for Support The National Instruments website is your complete resource for technical support At ni com support you have access to everything from troubleshooting and application development self help resources to email and phone assistance from NI Application Engineers A Declaration of Conformity DoC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electromagnetic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification If you product supports calibrati
26. r defined CLIP but also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to communicate directly with both the FPGA VI and the external adapter module connector interface The following figure shows the relationship between an FPGA VI and CLIP Figure 4 CLIP and FPGA VI Relationship NI FlexRIO FPGA Module FPGA User Defined CLIP Adapter Module CLIP Socket i User Defined LabVIEW a CLIP gt FPGA VI Socketed apter i CLIP Module External I O Connector DRAM 0 CLIP Socket Socketed CLIP DRAM 1 CLIP Socket Socketed CLIP 8 nicom NI5782R User Manual and Specifications The NI 5782 ships with socketed CLIP items that add module I O to the LabVIEW project The NI 5782 ships with the following CLIP items l NI 5782 Multiple Sample CLIP The analog input channels generate two samples per clock cycle at a clock rate that is half the sample rate The analog output channels generate four samples per clock cycle at a clock rate that is one quarter of the sample rate The AI default sample rate is 250 MHz and the AO default sample rate is 500 MHz The default clock rate for this CLIP is 125 MHz You can set a lower sample rate by using an external Sample Clock This CLIP presents the data to the diagram in a decelerated format The ADC data lands at half the rate as the ADC clock The DAC data must be presented in four ti
27. t This product is intended for use in industrial locations There is no guarantee that harmful interference will not occur in a particular installation when the product is connected to a test object or if the product is used in residential areas To minimize the potential for the product to cause interference to radio and television reception or to experience unacceptable performance degradation install and use this product in strict accordance with instructions in the product documentation Furthermore any changes or modifications to the product not expressly approved by National Instruments could void your authority to operate it under your local regulatory rules N Caution To ensure the specified EMC performance you must install PXI EMC Filler Panels National Instruments part number 778700 01 in adjacent chassis slots For more information about installing PXI EMC filler panels in your system refer to the Appendix B Installing EMI Controls section of this document N Caution To ensure the specified EMC performance operate this product only with shielded cables and accessories N Caution This product is sensitive to electrostatic discharge ESD To ensure the specified EMC performance follow the programming instructions listed at the end of the Using Your NI 5782R with a LabVIEW FPGA Example VI and Creating a LabVIEW Project and Running a VI on an FPGA Target sections of this document 2 nicom NI5782R User Manual and Specif
28. the error in control of the Read Write Control function Configure the Read Write Control function by clicking the terminal section labeled Unselected and selecting IO Module AI 0 N 1 Click and drag the bottom edge of the control edge to expose the other signals AI 0 N 1 AI 1 N to the Read Write Control function Wire indicators to each output terminal of the IO Module AI 0 N 1 AI 1 N Add the Close FPGA VI Reference function located on the FPGA Interface palette to the right of the While Loop on the block diagram Wire the FPGA VI Reference Out terminal of the Read Write Control function to the FPGA VI Reference In terminal of the Close FPGA VI Reference function Wire the error out terminal of the Read Write Control function to the error in terminal of the Close FPGA VI Reference function NI 5782R User Manual and Specifications National Instruments 15 Your block diagram should resemble the block diagram in Figure 7 Figure 7 5782SampleAcq Host vi Block Diagram D 10 Modulet AILO N 1 IO Module Al0 N aho Module AIO N 10 Modulet AI 1 N 1 Eo Module AI1 N 1 IO Module AIL N 16 Save the VI as 5782SampleAcq Host vi Running the Host VI l 2 3 4 5 Connect one end of an SMA cable to AI 0 on the front panel of the NI 5782 and the other end of the cable to your DUT Open the front panel of 5782SampleAcq Host vi Click the Run button to run the VI The VI acquires data
29. tion about which software versions are compatible with your device visit ni com info and enter rdsoftwareversion in the text field Each NI 5782R example project includes the following components e A LabVIEW FPGA VI that can be compiled and run on the FPGA embedded in the hardware A VI that runs on Windows and interacts with the LabVIEW FPGA VI a Note Inthe LabVIEW FPGA Module software NI FlexRIO adapter modules are referred to as JO Modules Complete the following steps to run an example that acquires a waveform on CH 0 of the NI 5782 1 Connect one end of an SMA cable to AI 0 on the front panel of the NI 5782 and the other end of the cable to your device under test DUT Launch LabVIEW Click Help Find Examples to display the NI Example Finder 4 Inthe NI Example Finder window select Hardware Input and Output FlexRIO IO Modules NI 5782 Select NI 5782 Getting Started Ivproj 6 Inthe Project Explorer window open NI 5782 Getting Started Host vi under My Computer to open the host VI The Open FPGA VI Reference function in this VI uses the NI 7952R as the FPGA target by default If you are using an NI FlexRIO FPGA module other than the NI 7952R complete the following steps to change to the FPGA VI to support your target a Select Window Show Block Diagram to open the VI block diagram b On the block diagram right click the Open FPGA VI Reference PXI 7952R function and select Configure Open FPGA VI Refer
30. tude dBm 100 Hz Resolution Bandwidth 100 kHz Bandwidth 5 0 0 0 10 100 110 69 95 69 96 69 97 69 98 69 99 70 00 70 01 Frequency MHz 70 02 70 03 70 04 70 05 Figure 23 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm Amplitude dBm 1 kHz Resolution Bandwidth 1 MHz Bandwidth 5 0 0 0 10 69 6 69 7 69 8 69 9 70 0 70 1 Frequency MHz 70 2 70 3 70 4 70 5 NI 5782R User Manual and Specifications National Instruments 27 Figure 24 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm 1 kHz Resolution Bandwidth 100 MHz Bandwidth Amplitude dBm 20 30 40 50 60 70 80 90 100 110 120 Frequency MHz Figure 25 Analog Output One Tone Spectral Measurement 70 MHz 0 25 dBm 1 kHz Resolution Bandwidth 500 MHz Bandwidth Amplitude dBm 10 150 200 250 300 350 400 450 500 Frequency MHz O Ql O Internal Sample Clock General Characteristics Oscillator TY PC ices scditcnanesnsnedosensdececaaseendsiueeeseesote Fixed frequency synthesizer Frequency default ccccsssssccceeeeeeceeeeeeens 1 GHz Reference SUS iat ecta ce cate beedeontecdedecciuettnteevessane lt 60 dBc 28 ni ccom NI5782R User Manual and Specifications Phase noise TOT Z Offset ona 95 dBc Hz tOOKHZ Ofset 115 dBc Hz Clock distribution part numbet 008 AD9512 Reference Clock sources eeesseeeeeeeeeetees Internal External through the CLK IN
31. ure 10 Analog Input One Tone Spectral Measurement 70 MHz 1 dBFS dBFS dB 0 0 20 40 60 80 100 120 Frequency MHz Figure 11 Two Tone Spectral Measurement 19 5 and 20 5 MHz 10 dBFS dBFS dB 0 0 20 40 60 80 100 120 Frequency MHz NI 5782R User Manual and Specifications National Instruments 19 DC Coupled Specifications Input range normal operating conditions 4 0 dBm 1 0 Vpk pk Absolute maximum input ccccccesceesseeeeees 50 Q 4 5 V DC 15 dBm 3 6 Vpk pk AC Bandwidth 1 dB cccccceeeesseeeeeeeeeeeeeees DC to 170 MHz Bandwidth 3 dB ceccecseesssseeeeeeeeeeeeeees DC to 330 MHz Table 6 lists the DC coupled spectral performance measurements All values are measured with a 1 GHz internal Sample Clock Table 6 Analog Input DC Coupled Spectral Performance 67 3 dB 66 2 dB 65 5 dB SINAD 67 0 dB 65 4 dB 64 0 dB 80 0 dB 78 0 dB 66 0 dB Figure 12 Analog Input Bandwidth Passband Amplitude dBFS on O 40 80 120 160 200 240 280 320 360 400 440 480 520 560 600 Frequency MHz 20 nicom NI5782R User Manual and Specifications dBFS dB Figure 13 Analog Input Terminated Input 0 20 40 60 80 100 120 Frequency MHz Figure 14 Analog Input One Tone Spectral Measurement 70 MHz 1 dBFS dBFS dB 0 0 20 40 60 80 100 120 Frequency MHz NI 5782R User Manual and Specifications National Instruments 21 Figure 15
32. web page at ni com environment This page contains the environmental regulations and directives NI 5782R User Manual and Specifications National Instruments 33 with which NI complies as well as other environmental information not included in this document Waste Electrical and Electronic Equipment WEEE et EU Customers At the end of the product life cycle all products must be sent to a WEEE recycling center For more information about WEEE recycling centers National Instruments WEEE initiatives and compliance with WEEE Directive 2002 96 EC on Waste and Electronic Equipment visit ni com environment weee ETARA mis hie hl SEAS PE ROHS Ep RAAP Notional Instruments 6 El E TAER A i PRAEH Ee J ta ROHS XF National Instruments FE ROHS APEA E TEESE ni com environment rohs_china For information about China ROHS compliance go TO ni com environment rohs_china Appendix B Installing EMI Controls To ensure specified EMC performance an HDMI cable ferrite and PXI EMC filler panels must be properly installed in your NI FlexRIO system Your kit includes the HDMI cable ferrite but the PXI EMC filler panels National Instruments part number 778700 01 must be purchased separately For more installation information refer to the MI FlexRIO FPGA Module Installation Guide and Specifications Installing PXI EMC Filler Panels Complete the following instructions to install PXI EMC filler panels National Instruments
33. wo AI channels two AO channels eight bidirectional DIO channels four bidirectional PFI channels and an input clock selector that can be configured to use one of the following settings Internal Sample Clock Internal Sample Clock locked to an external Reference Clock through the CLK IN connector External Sample Clock through the CLK IN connector NI 5782R User Manual and Specifications National Instruments 9 Internal Sample Clock locked to an external Reference Clock through IoModSyncClock External Sample Clock through IoModSyncClock This CLIP also contains an engine to program the CLK chip ADCs and DACs either through predetermined settings for an easier instrument setup or through a raw SPI address and data signals for a more advanced setup Refer to the M FlexRIO Help for more information about NI FlexRIO CLIP items how to configure the NI 5782 with a socketed CLIP and for a list of available socketed CLIP signals Connecting Cables e Use any 50 Q SMA cable to connect signals to the connectors on the front panel of your NI 5782 e Use the SHH19 H19 AUX cable NI part number 152629 01 or 152629 02 to connect to the DIO and PFI signals on the AUX I O connector For more information about connecting I O signals on your device refer to the Appendix A Specifications section of this document Clocking The NI 5782 clocks control the sample rate and other timing functions on the device Table
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