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^1 USER MANUAL ^2 Accessory 3E

1. M980 gt X 78421 8 16 word 1 1 16 bit word node2 981 gt 578422 8 16 word 2 27416 bit word node 2 982 gt 578423 8 16 word 3 3 16 bit word node 2 M983 gt X 78425 8 16 word 1 1 16 bit word node 3 984 gt 578426 8 16 word 2 2 16 bit word node 3 M985 gt X 78427 8 16 word 3 3 16 bit word node 3 M1000 gt X 0010F0 8 16 Input mirror word 1 M1001 gt Y S0100F0 8 16 Input mirror word 2 1002 gt 50100 1 8 16 Input mirror word 3 M1003 gt Y S0100F1 8 16 Output mirror word 1 1004 gt 50010 2 8 16 Output mirror word 2 M1005 gt Y S0010F2 8 16 Output mirror word 3 M1010 gt X S0010F3 8 16 Old Image mirror word 1 M1011 gt Y 0010F3 8 16 Old Image mirror word 2 M1012 gt X 0010F4 8 16 Old Image mirror word 3 IO word 1 IO Word 2 IO Word 3 M800 gt X 0010F0 8 M816 gt Y 0010F0 8 M832 gt X 0010F1 8 M801 gt X S0010F0 9 M817 gt Y S0010F0 9 833 gt 50010 1 9 802 gt 50010 0 10 818 gt 50010 0 10 834 gt 50010 1 10 M803 gt X 0010F0 11 819 gt 50010 0 11 835 gt 50010 1 11 804 gt 50010 0 12 820 gt 50010 0 12 836 gt 50010 1 12 M805 gt X 0010F0 13 M829 gt Y S0010F0 13 837 gt 50010 1 13 806 gt 50010 0 14 822 gt 50010 0 14 838 gt 50010 1 14 M807 gt X 0010F0 15 823 gt 50010 0
2. IF M7000 1 and P7000 0 emergancy stop condition CMD A global motion program abort I5111 500 8388608 110 500 msec delay for deceleration WHILE 5111 gt 0 ENDWHILE CMD K kill all axes M7024 0 turn off BUS voltage P7000 1 latch input Endif IF M7000 0 and P7000 1 M7024 1 enable BUS volatge 5111 5000 8388608 110 75000 msec delay for bus voltage WHILE 15111 gt 0 ENDWHILE CMD A close loop for all servos P7000 0 latch input Endif close UMAC Turbo Closed Loop Control Using ACC 3E The ACC 3E data can also be used for closed loop control The encoder conversion table at the UMAC Turbo will have to be modified to use the data for closed loop control Example E2 is jumpered on the ACC 3E to select the I O Gate address Y 078900 Y 78907 Set 18000 F78900 turbo location 3501 process Y 078900 as parallel 3U format I8001 2 018000 turbo location 3502 for 24 bit Y register The user can then set Ix03 and Ix04 to 3502 to use the data for parallel feedback 8 Using Acc 3E with Turbo UMAC Accessory 3E USING ACC 3E WITH UMAC MACRO A fundamental understanding of the MACRO Station I O transfer is needed to set up the MACRO I O family of accessories The MACRO station typically will have up to eight axis nodes 0 1 4 5 8 9 12 and 13 and up to six transfer nodes 2 3 6 7 10 and 11 There are three types of I O transfers allowed to send the information to the Ultralite
3. Description Pin Symbol Function Description Notes 1 I O119 I O I O Bit 119 2 GND Common Return 3 I O118 I O I O Bit 118 4 GND Common Return 5 I O117 I O I O Bit 117 6 GND Common Return 7 I O116 I O I O Bit 116 8 GND Common Return 9 I O115 I O I O Bit 115 10 GND Common Return 11 I O114 I O I O Bit 114 12 GND Common Return 13 I O113 I O Bit 113 14 GND Common Return 15 I O112 I O I O Bit 112 16 GND Common Return 17 I O111 I O I O Bit 111 18 GND Common Return 19 I O110 I O Bit 110 20 GND Common Return 21 1 0109 I O Bit 109 22 GND Common Return 23 I O108 I O Bit 108 24 GND Common Return 25 1 0107 I O Bit 107 26 GND Common Return 27 1 0106 I O Bit 106 28 GND Common Return 29 1 0105 105 144 I O Piggyback Board Header Descriptions 29 30 Accessory 3E 30 GND Common Return 31 1 0104 I O I O Bit 104 32 GND Common Return 33 1 0103 IO I O Bit 103 34 GND Common Return 35 I O102 IO I O Bit 102 36 GND Common Return 37 I O101 I O I O Bit 101 38 GND Common Return 39 I O100 I O I O Bit 100 40 GND Common Return 4 1 099 I O I O Bit 99 42 GND Common Return 43 1 098 I O I O Bit 98 44 GND Common Return 45 1 097 I O I O Bit 97 46 GND Common Return 47 1 096 T O Bit 96 48 GND Common Return 49 45V Output 5 V Supply 50 GND Common Return Default low true i
4. eren 21 Example 2 48 Inputs 48 Outputs Using 1x24 Bit Transfers sess 22 Example 3 36 Inputs 36 Outputs Using 1x72 Bit Transfer nasus 23 144 I O PIGGYBACK BOARD HEADER DESCRIPTIONS 25 J4 50 Pin Header I O Connector Description eene nnne nnne 25 J5 50 Pin Header I O Connector Description aaa 26 J6 50 Pin Header I O Connector Description a eene tenete nennen ener 27 J7 50 Pin Header I O Connector Description eese ener 26 J8 50 Pin Header I O Connector Description eene nnne entente tren tentent nnne nennen 29 J9 50 Pin Header I O Connector Description eese enne tnnt nnne ener enne enne 30 J10 26 Pin Header I O Connector Description eese tnnt ener enne 32 PI 96 Pin Header Option A Required eese eene tnnt trennen nennen 1 33 Table of Contents Accessory 3E Table of Contents Accessory 3E INTRODUCTION The Accessory is a general purpose 1 board to the PMAC2 Ultralite via the MACRO Station ACC 3E provides up to 144 bits lines of digital I O The actual I O Reads are ca
5. w E2 jumpered enable node 2 3 6 and 7 for I O at MACRO Station 50 119 4 sets interrupt period for data transfer MSSAVE0 save to macro station MS 0 macro station to enable OPEN PLC1 CLEAR M1000 M970 new input mirror equal to actual input word 1001 971 new input mirror equal to actual input word IF M1000 M1010 OR M1001 M1011 M1010 M1000 M1011 M1001 if inputs change process outputs old input mirror equal to new input mirror old input mirror equal to new input mirror Set outputs based on inputs or program logic M973 M1002 M974 M1003 Output word equals Output Mirror Word Output word equals Output Mirror Word ENDIF CLOSE 22 Using Acc 3E with Turbo UMAC Accessory 3E Example 3 36 Inputs 36 Outputs Using 1x72 Bit Transfer The 72 bit transfer is unique because it allows the user to transfer both the 3x16 bit and 1x24 bit transfer in one read write transfer This method can only be used with MACRO firmware version 1 112 or higher Using this method we only need to activate one node In this case we will use node 2 For this example the inputs and outputs are sharing the same Node Transfer Address You will notice address has 12 bits of inputs and 4 bits of outputs To properly write to the 4 output bits Delta Tau recommends that the user write the outputs to the entire word Ultralite 8 Axis Turbo Ultralite 8 Axis Description
6. 50010 2 19 943 gt 50010 2 19 912 gt 50010 1 20 928 gt 50010 2 20 944 gt 50010 2 20 913 gt 50010 1 21 129 gt 50010 2 21 945 gt 50010 2 21 914 gt 50010 1 22 M930 X 5 0010F2 22 M946 gt Y SO010F2 22 M915 gt Y S0010F1 23 931 gt 50010 2 23 947 gt 50010 2 23 20 Using with Turbo UMAC Accessory 3E Example 1 48 Inputs 48 Outputs Using 3x16 Bit Transfers For this example the inputs and outputs are not sharing the same Node Transfer Address C0A1 C0A2 C0A3 C0A5 COA6 and COA7 Each of the node transfer addresses can be defined as 16 bit addresses Ultralite 8 Axis Turbo Ultralite 8 Axis Description 1996 0FB33F 1684 1 0FB33F Enable nodes 0 1 2 3 4 5 8 9 12 amp 13 at PMAC Ultralite M980 gt X C0A 1 8 16 M980 gt X 78421 8 16 IO word 1 1st 16 bit word node2 M981 2X C0A2 8 16 981 gt 578422 8 16 IO word 2 2nd 16 bit word node 2 M982 gt X C0A3 8 16 M982 gt X 78423 8 16 10 word 3 3rd 16 bit word node 2 M983 gt X C0A5 8 16 M983 gt X 78425 8 16 IO word 1 1st 16 bit word node 3 M984 gt X C0A6 8 16 M984 gt X 78426 8 16 IO word 2 2nd 16 bit word node 3 M985 gt X C0A7 8 16 M985 gt X 78427 8 16 10 word 3 3rd 16 bit word node 3 M1000 gt X 0770 8 16 M1000 gt X 0010FO0 8 16 Input mirror word 1 M1001
7. 5078802 0 8 I O bits 16 23 port A ICO 2003 gt 5078803 0 8 I O bits 0 7 port B ICO 2004 gt 5078804 0 8 I O bits 8 15 port B ICO 2005 gt 5078805 0 8 I O bits 16 23 port ICO 2006 gt 5078806 0 8 register selected 2007 gt 5078807 0 8 control register 2008 gt 5078800 8 8 I O bits 0 7 port 2009 gt 5078801 8 8 I O bits 8 15 port 2010 gt 5078802 8 8 I O bits 16 23 port 2011 gt 5078803 8 8 I O bits 0 7 port M2012 gt Y 078804 8 8 I O bits 8 15 port 2013 gt 5078805 8 8 I O bits 16 23 port 2014 gt 5078806 8 8 register selected 2015 gt 5078807 8 8 control register 2016 gt 5078800 1 2017 gt 5078801 1 2018 gt 5078802 1 2019 gt 5078803 1 2020 gt 5078804 1 2021 gt 5078805 1 2022 gt 5078806 1 bits 0 7 port IC2 I O bits 8 15 port IC2 I O bits 16 23 port IC2 I O bits 0 7 port B IC2 I O bits 8 15 port IC2 I O bits 16 23 port B IC2 register selected OY N gt gt gt OO OO CO CO CO CO 2023 gt 5078807 1 control register M2007 Y 078C07 0 8 Gontrol word for 78000 0 8 78005 0 8 M2015 Y 078C07 8 8 repontrol word for 79000 9 9 78005 8 8 M2023 Y 078C07 16 8 control word for S78C00 16 8 578 05 16 8 S PLC to in
8. 19 1 038 I O I O Bit 38 20 GND Common Return 21 I O37 I O I O Bit 37 22 GND Common Return 23 1 036 I O I O Bit 36 24 GND Common Return 25 1 035 I O I O Bit 35 26 GND Common Return 27 I O34 I O Bit 34 28 GND Common Return 29 1 033 I O I O Bit 33 30 GND Common Return 31 1 032 I O I O Bit 32 32 GND Common Return 33 I O31 I O I O Bit 31 34 GND Common Return 35 1 030 I O I O Bit 30 36 GND Common Return 37 1 029 I O I O Bit 29 38 GND Common Return 39 1 028 I O I O Bit 28 40 GND Common Return 41 I O27 I O I O Bit 27 ACC 3E 144 I O Piggyback Board Header Descriptions Accessory 3E 42 GND Common Return 43 1 026 I O I O Bit 26 44 GND Common Return 45 1 025 I O I O Bit 25 i 46 GND Common Return 47 I O24 I O I O Bit 24 48 GND Common Return 49 45V Output 5 V supply 50 GND Common Return Default low true inputs and outputs programmable polarity J6 50 Pin Header Connector Description w Pin Symbol Function Description Notes 1 I O71 I O I O Bit 71 2 GND Common Return 3 I O70 I O I O Bit 70 4 GND Common Return 5 1 069 I O I O Bit 69 GND Common Return 7 1 068 I O I O Bit 68 i 8 GND Common Return 9 1 067 I O I O Bit 67 10 GND Common Return 11 I O66 I O I O Bit 66 12 GND Common Ret
9. 1996 0FB337 1684 1 0FB337 Enable nodes 0 1 2 4 5 8 9 12 amp 13 at PMAC Ultralite M970 gt X C0A0 0 24 M970 gt X 78420 0 24 IO word 1 24 bit word node2 M980 gt X C0A1 8 16 M971 gt X 78421 8 16 IO word 1 1st 16 bit word node2 M98 1 gt X C0A2 8 16 972 gt 78422 8 16 word 2 2 16 bit word node 2 M982 gt X C0A3 8 16 973 gt 78423 8 16 word 3 16 bit word node 2 M1000 gt X 0770 0 24 M1000 gt X 0010F0 0 24 Input mirror word 1 M1001 gt Y 0770 8 12 M1001 gt Y 0010F0 8 12 mirror word 2 12 bits inputs only M1002 gt Y 0770 8 16 M1002 Y 0010F0 8 16 Output mirror word 1 12 bits inputs amp 4 bits outputs M1003 gt X 0771 8 16 M1003 gt X 0010F1 8 16 Output mirror word 2 M1004 gt Y 0771 8 16 M1004 gt Y 0010F1 8 16 Output mirror word 3 M1010 gt X 0771 0 24 M1010 gt X 0010F2 0 24 Old Input mirror word 1 M1011 gt Y 0771 8 12 M1011 gt Y 0010F2 8 12 Old Input mirror word 2 MSO MI169 SOOCOAOOOFFC8 sets up macro to transfer data for ACC3E w E2 jumpered MS0 MI975 4 enable node 2 for I O 50 119 4 sets interrupt period for data transfer MSSAVE0 save to macro station 55550 macro station to enable OPEN PLC1 CLEAR M1000 M970 new input mirror equal to actual input word M1001 M981 amp 0FFF IF M1000 M1010 OR M1001 M1011 M1010 M100
10. 6 7 10 and 11 of MI975 should ever be set to 1 MIO975 is used at the power on reset of the Compact MACRO Station in combination with rotary switch SW1 and MI976 to determine which MACRO nodes are to be enabled The net result can be read in Station variable MI996 To get a value of MI975 to take effect the value must be saved MSSAVE node and the Station reset MS node Example Set MI975 to enable nodes 2 and 3 MS0 1975 Set Number MACRO IO nodes to be enabled Bit 15 14 13 12111019 8 71615 4131211410 Value 0 0 0101010101 1010101 101 10 1 1 0 0 2 50 1975 5000 MS0 MI975 2 4 Enable I O Node 2 alone MS0 MI975 C Enable I O Nodes 2 amp 3 50 1 975 54 Enable I O Nodes 2 3 amp 6 MSO M1I975 SCC Enable I O Nodes 2 3 6 amp 7 MSO MI975 S4CC Enable I O Nodes 2 3 6 7 amp 10 MSO MI975 S CCC Enable I O Nodes 2 3 6 7 10 amp 11 54 975 540 Enable Node 6 alone MS4 MI975 C0 Enable Nodes 6 amp 7 MS8 MI975 400 Enable I O Node 10 alone 58 975 5 00 Enable I O Nodes 10 amp 11 Using Acc 3E with Turbo UMAC 11 Accessory 3E MI69 MI70 specify the registers used in 16 bit I O transfers between MACRO node interface registers and I O registers on the MACRO Station I O accessory board They are used only if MI19 is greater than 0 MI69 MI70 48 bit variables represente
11. 6 Control Word Setup Example uiii obest e aa t ee Eie ier ete iso tei pesti beo 6 Accessory I O M Variables for UMAC Turbo n enne rennen enne 7 UMAC Turbo Closed Loop Control Using 02 000044404040 00 entere 8 USING WITH UMAC MACRO QQ sess suse ta 9 MACRO Station I O Node Transfer 5 9 PMAC2 Ultralite I O Node Addresses n n trennen tenere enne entrent nnne 10 PMAC2 Turbo Ultralite I O Node Addresses nn enne ener 10 MACRO W O Software an dci sic nei ga ku upan 11 ACC 3E Setup with MACRO nnne iet edere de abr ed e ipee elect te ete ER bcn 16 Reading and Writing to Node Addresses eseesseseeessseseseeeeeeeee enne enne tenente en nnne 17 ce 17 edo 17 Active Nodes for Compact MACRO I O Station 18 PMAC 2 Ultralite Example M Variable Definitions eese eene enne trennen 19 PMAC2 TURBO Ultralite Example M Variable Definitions nn enne 20 Example 1 48 Inputs 48 Outputs Using 3x16 Bit Transfers
12. X C0B3 10 X C0B4 X C0B5 X C0B6 X C0B7 11 X C0B8 X C0B9 X COBA X C0BB Traditionally the I O words for PMAC accessories are defined by their hardware Example The 34 has an input port and an output port The I O words used to memory map to these locations are fixed For ACC 3E the input and outputs are not defined This accessory board gives the user 144 bits of I O which can be defined to any part of the word 16 Using Acc 3E with Turbo UMAC Accessory 3E Reading and Writing to Node Addresses Delta Tau recommends that the user to read and write to the node address as complete words If the node address is 24 bits wide or 16 bits wide read or write to the M Variable assigned to that address Example Ultralite Turbo Ultralite 970 gt 0 0 0 24 970 gt 78420 0 24 M980 gt X C0A 1 8 16 980 gt 78421 8 16 M98 1 gt X C0A2 8 16 M981 gt X 78422 8 16 M982 gt X C0A3 8 16 M982 gt X 78423 8 16 M1000 gt X 0770 0 24 M1000 gt X 0010F0 0 24 image word M1001 gt X 0771 8 16 M1001 gt X 0010F0 8 16 image word For Outputs M970 F0001 1 sets bits 0 4 20 21 22 amp 23 M980 8101 sets bits 0 8 amp 23 M970 M 1000 sets M970 equal to M1000 M980 M 1001 sets M980 equal to M1001 For Inputs 1000 970 sets 1000 equal to 970 M1001 M980 sets M1001 equal to M980 If using the 48 bit read writ
13. 079436 X 079437 IC2 2 34 X 078420 X 07A421 X 07A422 X 07A423 IC2 3 35 X 07A424 X 07A425 X 07A426 X 07A427 IC2 6 38 X 07A428 X 07A429 X 07A42A X 07A42B IC2 7 39 X 07A42C X 07A42D X 07A42E X 07A42F IC2 10 42 X 07A430 X 07A431 X 07A432 X 07A433 IC2 11 43 X 07A434 X 07A435 X 07A436 X 07A437 2 50 X 07B420 X 07B421 X 07B422 X 07B423 IC3 3 51 X 07B424 X 07B425 X 07B426 X 07B427 IC3 6 54 X 07B428 X 07B429 X 07B42A X 07B42B IC3 7 55 X 07B42C X 07B42D X 07B42E X 07B42F IC3 10 58 X 07B430 X 07B431 X 07B432 X 07B433 IC3 11 59 X 07B434 X 07B435 X 07B436 X 07B437 Example If the user wanted to read the inputs from the MACRO Station of the first 24 bit I O node address of node 2 X C0A0 then he she could point an M variable to the Ultralite or TURBO Ultralite I O node registers to monitor the inputs M980 X 9C0A0 0 24 7000 gt 5078420 0 24 Ultralite node2 address Turbo Ultralite MACRO ICO node 2 address These M variable definitions M980 or M1980 could then be used to monitor the inputs for either the Ultralite or Turbo Ultralite respectively 10 Using Acc 3E with Turbo UMAC Accessory 3E MACRO Software Setings MACRO Station I O can be configured as either an input or an output The hardware connected to the MACRO I O boards determines whether or not the addresses defined are inputs or outputs Each
14. 15 839 gt 50010 1 15 808 gt 50010 0 16 M824 gt Y S0010F0 16 840 gt 50010 1 16 809 gt 50010 0 17 825 gt 50010 0 17 841 gt 50010 1 17 810 gt 50010 0 18 826 gt 50010 0 18 842 gt 50010 1 18 811 gt 50010 0 19 M827 gt Y S0010F0 19 843 gt 50010 1 19 812 gt 50010 0 20 828 gt 50010 0 20 M844 gt X S0010F1 20 813 gt 50010 0 21 829 gt 50010 0 21 845 gt 50010 1 21 M814 gt X 0010F0 22 M830 Y 50010F0 22 846 gt 50010 1 22 M815 gt X 0010F0 23 M831 Y 5 0010F0 23 847 gt 50010 1 23 IO word 4 IO Word 5 IO Word 6 900 gt 50010 1 8 916 gt 50010 2 8 932 gt 50010 2 8 901 gt 50010 1 9 M917 gt X S0010F2 9 M933 gt Y S0010F2 9 M902 gt Y 0010F1 10 918 gt 50010 2 10 934 gt 50010 2 10 903 gt 50010 1 11 919 gt 50010 2 11 M935 gt Y S0010F2 11 M904 gt Y 0010F1 12 920 gt 50010 2 12 936 gt 50010 2 12 M905 gt Y 0010F1 13 129 gt 50010 2 13 937 gt 50010 2 13 906 gt 50010 1 14 922 gt 50010 2 14 938 gt 50010 2 14 907 gt 50010 1 15 923 gt 50010 2 15 939 gt 50010 2 15 908 gt 50010 1 16 924 gt 50010 2 16 940 gt 50010 2 16 909 gt 50010 1 17 925 gt 50010 2 17 941 gt 50010 2 17 910 gt 50010 1 18 926 gt 50010 2 18 M942 gt Y S0010F2 18 M911 gt Y 0010F1 19 927 gt
15. 5078 04 8 8 T O bits 32 397 5078805 8 8 5078905 8 8 Y 078A05 8 8 5078 05 8 8 I O bits 40 47 17 Y 5 078807 8 8 Yirs078907 9 9 Y 5078A07 8 8 Y 078B07 8 8 Control Word 5078800 16 8 5078900 16 8 Y 078A00 16 8 5078 00 16 8 T O bits 0 7 8 5078801 16 8 5078901 16 8 Y 078A01 16 8 Y 078B01 16 8 T O bits 8 15 J8 5078802 16 8 5078902 16 8 Y 078A02 16 8 Y 078B02 16 8 T O bits 16 23 18 5078803 16 8 5078903 16 8 Y 078A03 16 8 Y 078B03 16 8 T O bits 24 31 19 5078804 16 8 5078904 16 8 Y 078A04 16 8 Y 078B04 16 8 T O bits 32 39 J9 5078805 16 8 5078905 16 8 5078 05 16 8 5078 05 16 8 bits 40 47 19 Y 5D78807 16 9 Y SD79907 16 9 5078 07 16 8 Y 5078BU7 16 8 Control Word Because the data processed at these I O Gate Arrays are extremely fast the user were to map the machine I O to the ACC 3E memory locations they could do ao bit wise or using 8 bit words Control Register The control register at address Base 7 permits the configuration of the IOGATE IC to a variety of applications The control register consists of eight write read back bits Bits 0 7 The control register consists of two sections Direction Control and Register Select The direction control allows the user to set his her input bytes to be read only One of the advantages of the IOGATE IC is that we give the user the ability to define the
16. C0A9 X C0AA X C0AB 7 X C0AC X COAD X COAE X C0AF 10 X COBO X COBI X COB2 X COB3 11 4 X C0B5 X C0B6 X C0B7 Using Acc 3E with Turbo UMAC 9 2 Ultralite Node Addresses Accessory 3E Node Node 24 bit Transfer Node 16 bit upper 16 bits Transfer Addresses Addresses 2 X C0A0 X C0A2 X C0A3 3 X C0A4 X C0A5 X C0A6 X C0A7 6 X C0A8 X C0A9 X C0AB 7 X COAC X COAD X COAE X COAF 10 X COBO X COBI X COB2 X COB3 11 X COB4 X COB5 X COB6 X COB7 PMAC2 Turbo Ultralite I O Node Addresses MACR User Node 24 bit Node 16 bit upper 16 bits OIC Node Transfer Transfer Addresses Node Addresses ICO 2 2 X 078420 X 078421 X 078422 X 078423 ICO 3 3 X 078424 X 078425 X 078426 X 078427 ICO 6 6 X 078428 X 078429 X 07842A X 07842B ICO 7 7 X 07842C X 07842D X 07842E X 07842F ICO 10 10 X 078430 X 078431 X 078432 X 078433 ICO 11 11 X 078434 X 078435 X 078436 X 078437 IC1 2 18 X 079420 X 079421 X 079422 X 079423 IC1 3 19 X 079424 X 079425 X 079426 X 079427 IC1 6 22 X 079428 X 079429 X 07942A X 07942B IC1 7 23 X 07942C X 07942D X 07942E X 07942F IC1 10 26 X 079430 X 079431 X 079432 X 079433 IC1 11 27 X 079434 X 079435 X
17. I O node has 72 bits of data to be transferred automatically to the Ultralite As stated previously there are three methods of transfer 3x16 bit 1x24 bit or 72 bit transfer There are several variables at the MACRO Station and PMAC2 Ultralite that enable the I O data transfer Once these variables are set to the appropriate values the user can then process the data like a normal PMAC or PMAC2 The variables to be modified at the MACRO Station are MI19 MI69 MI70 MI71 169 MI170 MI171 MI172 MI173 MI975 MI996 The Ultralite must have 1996 modified to enable the I O nodes used Can only be used with MACRO Station firmware version 1 112 or greater MI19 controls the data transfer period on a Compact MACRO Station between the MACRO node interface registers and the I O registers as specified by station MI variables MI20 through MI71 If MI19 is set to 0 this data transfer is disabled If MI19 is greater than 0 its value sets the period in Phase clock cycles the same as MACRO communications cycles at which the transfer is done MI975 permits the enabling of MACRO I O nodes on the Compact MACRO Station MI975 is a 16 bit value bits 0 to 15 with bit n controlling the enabling of MACRO node n If the bit is set to 0 the node is disabled if the bit is set to 1 the node is enabled The I O nodes on the Compact MACRO Station are nodes 2 3 6 7 10 and 11 which can be enabled by MI975 bits of these numbers Only bits 2 3
18. O Bit 122 44 GND Common Return 45 I O121 I O I O Bit 121 46 GND Common Return 47 I O120 I O Bit 120 48 GND Common Return 49 5V Output 5 V Supply 50 GND Common Return Default low true inputs and outputs programmable polarity ACC 3E 144 I O Piggyback Board Header Descriptions 31 32 Accessory 3E J10 26 Pin Header Connector Description Top View Pin Symbol Function Description Notes 1 OUT120 Output Bit 120 2 21 Output Bit 121 m 3 OUT122 Output Bit 122 i 4 OUT123 Output Bit 123 5 OUT124 Output Bit 124 u 6 OUT125 Output 125 7 OUT126 Output Bit 126 8 OUT127 Output I O Bit 127 9 IN128 Input T O Bit 128 10 1129 Input T O Bit 129 m 11 IN130 Input I O Bit 130 12 Input T O Bit 131 13 IN132 Input I O Bit 132 ii 14 IN133 Input I O Bit 133 T 15 IN134 Input I O Bit 134 16 IN135 Input I O Bit 135 17 IN136 Input T O Bit 136 ii 18 IN137 Input I O Bit 137 m 19 IN138 Input I O Bit 138 20 IN139 Input I O Bit 139 21 1140 Input T O Bit 140 iil 22 IN141 Input I O Bit 141 T 23 IN142 Input I O Bit 142 24 IN143 Input Bit 143 ii 25 OPTO GND Common Return 26 OPTO V Input 12V to 24V Supply Default low true inputs and outputs programmable polarity ACC 3E 144 I O Piggyback Board Header Descrip
19. table explains how these bits select registers Bit 7 Bit 6 Combined Base 0 to Base 5 Base 6 Register Value Register Selected Selected 0 0 0 Data Register Data Register 0 1 1 Setup Register 1 Setup Register 1 0 2 Setup Register 2 n a 1 1 3 Setup Register 3 In a typical application non zero combined values of Bits 6 and 7 are only used for initial configuration of the IC These values are used to access the setup registers at the other addresses After the configuration is finished zeros are written to both Bits 6 and 7 so the data registers at the other registers can be accessed Control Word Setup Example The user will need to setup the control words for the IO card at power up A simple plc could be written to setup the control word properly could accomplish this task For this example we will be setting up one ACC 3E ICO 48in 48out and one ACC4E 24in 24out Control Word for ACC 3E 2007 gt 8078807 0 8 Hex 0 Binary 0 0 1 1 1l 1 4141 Bit 71615 413 211 Bits 0 7 read Bits 8 15 read Bits 16 23 read Register Select Bits 24 31 read only Bits 32 39 read only Bits 40 47 read only 2000 gt 5078800 0 8 1 O bits 0 7 port A ICO 6 Using Acc 3E with Turbo UMAC Accessory 3E M2001 gt Y 078801 0 8 I O bits 8 15 port A ICO 2002 gt
20. the I O piggyback boards to the MACRO node registers I O points move from the least significant bit to the most significant bit I O00 at Node bit 0 Point 5 Option 3 Part Present on Option 4 Matching MACRO X Register I O00 1 015 Sub option A Yes Specified MACRO X Address 1 I O16 1 031 Sub option A Yes Specified MACRO X Address 2 1 032 1 047 Sub option A Yes Specified MACRO X Address 3 I O48 O71 Sub option B No Specified MACRO X Address 0 Examples 69 lt 500 0 000 transfers 72 bit I O between an I O board set at FFCO and MACRO Nodes 2 C0A0 C0A3 1169 00COBOOOFFCS8 transfers 72 bit I O between an I O board set at FFC8 and MACRO Node 10 COBO COB3 MI171 MI172 or MI173 specifies the registers used in 144 bit I O transfers between MACRO I O node interface registers and I O registers on a MACRO station It is used only if MII9 is greater than 0 The transfer utilizes two consecutive 72 bit X memory I O nodes The three 48 bit I O Gates must be the LOWER MIDDLE and UPPER configuration MI171 MI172 or MI173 is a 48 bit variable represented as 12 hexadecimal digits The first 6 digits specify the address of the first 72 bit real time MACRO node register sets to be used of the two The second 6 digits specify the address of 48 bit I O sets on an Option 3 or Option 4 board to be used The individual digits are specified as follows 14 Using Acc 3E w
21. 0 M1011 M1001 use only lower 12 bits if inputs change process outputs old input mirror equal to new input mirror old input mirror equal to new input mirror Set outputs based on inputs or program logic M983 M1001 amp F000 M984 M1002 M985 M1003 Output word equals Output Mirror Word Use Only Upper 4 Bits Output word equals Output Mirror Word Output word equals Output Mirror Word ENDIF CLOSE Using Acc 3E with Turbo UMAC 23 24 Accessory 3E Using Acc 3E with Turbo UMAC Accessory 144 PIGGYBACK BOARD HEADER DESCRIPTIONS J4 50 Pin Header Connector Description Top View Pin Symbol Function Description 1 1 023 I O I O Bit 23 2 GND Common Return 3 22 I O Bit 22 4 GND Common Return 5 I O21 I O I O Bit 21 6 GND Common Return 7 20 I O I O Bit 20 8 GND Common Return 9 I O19 I O Bit 19 10 GND Common Return 11 I O18 T O Bit 18 T 12 GND Common Return 13 I O17 I O I O Bit 17 14 GND Common Return 15 I O16 I O Bit 16 16 GND Common Return 17 I O15 I O Bit 15 18 GND Common Return 19 I O14 I O I O Bit 14 id 20 GND Common Return 21 I O13 13 22 GND Common Return 23 I O12 I O I O Bit 12 24 GND Common Return 25 I O11 I O I O Bit 11 26
22. 0A1 C0A2 COA3 FFCA C0A5 C0A6 COA7 FFCC C0A9 COAA COAB The data in this application will transfer 48 bits of data per node as specified by MI69 These memory locations could be utilized by pointing an M variable to the node locations In your PLC program these M variables would be considered the actual input words and actual output words or a combination of the two 8 inputs 8 outputs for 16 bit read write To efficiently read and write to these memory locations Delta Tau suggests using image input words to read the actual input words and then write to the actual output word if the inputs have changed states The following block diagram shows the typical logic for PMAC s inputs and outputs input mirror input word yes in mirror old in mirror old input mirror input word Y Process Inputs Build Output Word Perform Desired Actions output word out mirror I END bM E 18 Using Acc 3E with Turbo UMAC Accessory 3E For this application we are using six 16 bit data transfers and will use the following M Variable definitions in our application 2 Ultralite Example M Variable Definitions 980 gt 981 gt 982 gt 983 gt 984 gt 985 gt lt 1 lt lt lt 5 lt 1000 gt 1001 Y 1002 X 1003 gt 1004 gt 1005 Y 1010 g
23. 8 gt Y 770 20 M844 gt X 771 20 M813 gt X 770 21 M829 gt Y 770 21 M845 gt X 771 21 M814 gt X 770 22 M830 gt Y 770 22 M846 gt X 771 22 M815 gt X 770 23 M831 gt Y 770 23 M847 gt X 771 23 IO word 4 IO Word 5 IO Word 6 911 gt M912 Y M900 gt Y 771 8 M901 gt Y 771 9 M902 gt Y M903 Y M904 Y M905 Y M906 Y M907 Y M908 Y M909 Y M910 Y 5771 11 a ar dg 771 12 771 13 5531 14 5771 15 771 186 8393 31 771 18 771 19 5771 20 M913 Y M914 Y M915 Y 5971 21 771 22 771 23 916 gt 5772 8 M917 gt X 772 9 772 10 5999 1T 8772 12 5772 13 5979 14 772 15 799 16 8399 17 772 18 M927 X M918 X M919 X M920 X M129 X 922 gt 923 gt 924 gt 925 gt 926 gt 45772 19 928 gt 129 gt 930 gt 931 gt 772 20 5772 21 69222 5772 23 932 gt 5772 8 933 gt 5772 9 M941 Y 942 gt 943 gt 944 gt M934 Y M935 Y M936 Y M937 Y M938 Y M939 Y M940 Y M945 Y M946 Y M947 Y 772 10 5772 11 772 12 772 13 8772 TA S772715 5772 16 5772 17 5772 18 55772 19 5772 20 5772 21 5772 22 5772 23 Using with Turbo UMAC 19 Accessory 3E PMAC2 TURBO Ultralite Example M Variable Definitions
24. 93 I O I O Bit 93 6 GND Common Return 7 1 092 I O I O Bit 92 8 GND Common Return 9 I O91 I O I O Bit 91 10 GND Common Return 11 1 090 I O I O Bit 90 12 GND Common Return 13 1 089 T O Bit 89 14 GND Common Return 15 1 088 I O I O Bit 88 16 GND Common Return 17 I O87 I O I O Bit 87 18 GND Common Return 19 1 086 I O I O Bit 86 20 GND Common Return 21 1 085 T O Bit 85 22 GND Common Return 23 1 084 I O I O Bit 84 24 GND Common Return 25 1 083 I O I O Bit 83 26 GND Common Return 27 I O82 I O I O Bit 82 28 GND Common Return 29 I O81 I O I O Bit 81 30 GND Common Return 31 1 080 I O I O Bit 80 32 GND Common Return 33 1 079 I O I O Bit 79 ACC 3E 144 I O Piggyback Board Header Descriptions Accessory 3E 34 GND Common Return 35 1 078 I O I O Bit 78 36 GND Common Return 37 1 077 I O Bit 77 38 GND Common Return 39 1 076 I O Bit 76 40 GND Common Return 41 I O75 I O I O Bit 75 42 GND Common Return 43 1 074 I O Bit 74 44 GND Common Return 45 1 073 I O I O Bit 73 46 GND Common Return 47 I O72 I O I O Bit 72 48 GND Common Return 49 45V Output 5 V Supply 50 GND Common Return Default low true inputs and outputs programmable polarity J8 50 Header Connector Viri 2
25. CC 3E 144 1 Piggyback Board Header Descriptions 33 Accessory 3E P1 96 Pin Header 555 Option A Required Continued Pin Symbol Function Description Notes 01 5V Supply 5V Supply B02 GND Common Return B03 N C No Connect B04 N C No Connect BOS N C No Connect B06 N C No Connect B07 N C No Connect B08 N C No Connect B09 N C No Connect B10 N C No Connect Bll N C No Connect B12 N C No Connect N C No Connect 14 N C No Connect 15 N C No Connect B16 N C No Connect B17 N C No Connect B18 N C No Connect B19 N C No Connect B20 N C No Connect 21 N C No Connect B22 N C No Connect B23 N C No Connect B24 N C No Connect B25 N C No Connect B26 N C No Connect B27 N C No Connect B28 N C No Connect B29 N C No Connect B30 N C No Connect 31 GND Common Return B32 5V Supply 5V Supply 34 144 I O Piggyback Board Header Descriptions Accessory 3E P1 96 Pin Header 0 Option Required ste Continued Pin Symbol Function Description Notes 01 5V Supply 5V Supply C02 GND Common Return C03 I O00 T O Bit 0 Base 0 bit 0 C04 02 Bit 2 Base 0 bit 2 C05 1 004 T O Bit 4 Base 0
26. GND Common Return 27 I O10 T O Bit 10 28 GND Common Return 29 1 09 T O Bit 9 30 GND Common Return 31 1 8 IO I O Bit 8 32 GND Common Return 33 I O7 I O I O Bit 7 34 GND Common Return 35 1 06 T O Bit 6 36 GND Common Return 37 1 5 I O I O Bit 5 38 GND Common Return 39 1 04 I O Bit 4 n 40 GND Common Return 41 1 03 T O Bit 3 a 42 GND Common Return 43 I O2 I O I O Bit 2 44 GND Common Return 45 1 1 I O I O Bit 1 ACC 3E 144 I O Piggyback Board Header Descriptions 25 26 Accessory 3E 46 GND Common Return 47 1 00 I O I O Bit 0 48 GND Common Return 49 45V Output 5 V Supply 50 GND Common Return Default low true inputs and outputs programmable polarity J5 50 Header Connector Viru 2 Description Pin Symbol Function Description Notes 1 I O47 I O I O Bit 47 2 GND Common Return 3 I O46 I O I O Bit 46 4 GND Common Return 5 1 045 I O I O Bit 45 6 GND Common Return 7 I O44 I O I O Bit 44 8 GND Common Return 9 1 043 I O I O Bit 43 10 GND Common Return 11 1 042 I O Bit 42 12 GND Common Return 13 I O41 I O I O Bit 41 14 GND Common Return 15 I O40 I O I O Bit 40 16 GND Common Return 17 1 039 I O I O Bit 39 18 GND Common Return
27. USER MANUAL Accessory 3E DELTA TAU Data Systems Inc NEW IDEAS IN Single Source Machine Control Power Flexibility Ease of Use 21314 Lassen Street Chatsworth CA 91311 Tel 818 998 2095 Fax 818 998 7807 www deltatau com Copyright Information 2003 Delta Tau Data Systems Inc All rights reserved This document is furnished for the customers of Delta Tau Data Systems Inc Other uses are unauthorized without written permission of Delta Tau Data Systems Inc Information contained in this manual may be updated from time to time due to product improvements etc and may not conform in every respect to former issues To report errors or inconsistencies call or email Delta Tau Data Systems Inc Technical Support Phone 818 717 5656 Fax 818 998 7807 Email support deltatau com Website http www deltatau com Operating Conditions All Delta Tau Data Systems Inc motion controller products accessories and amplifiers contain static sensitive components that can be damaged by incorrect handling When installing or handling Delta Tau Data Systems Inc products avoid contact with highly insulated materials Only qualified personnel should be allowed to handle this equipment In the case of industrial applications we expect our products to be protected from hazardous or conductive materials and or environments that could cause harm to the controller by damaging components or cau
28. bit 4 C06 1 06 T O Bit 6 Base 0 bit 6 C07 I O08 Bit 8 Base 1 bit 0 C08 I O10 T O Bit 10 Base 1 bit 2 C09 I O12 Bit 12 Base 1 bit 4 C10 I O14 I O I O Bit 14 Base 1 bit 6 11 I O16 Bit 17 Base 2 bit 0 C12 1 18 Bit 18 Base 2 bit 2 C13 1 020 T O Bit 20 Base 2 bit 4 C14 1 22 I O Bit 22 Base 2 bit 6 C15 I O24 I O Bit 24 Base 3 bit 0 C16 1 026 I O Bit 26 Base 3 bit 2 C17 1 028 Bit 28 Base 3 bit 4 C18 1 030 I O Bit 30 Base 3 bit 6 C19 1 032 Bit 32 Base 4 bit 0 C20 1 034 I O Bit 34 Base 4 bit 2 C21 1 036 Bit 36 Base 4 bit 4 C22 1 038 Bit 38 Base 4 bit 6 C23 I O40 Bit 40 Base 5 bit 0 C24 42 T O Bit 42 Base 5 bit 2 C25 44 Bit 44 Base 5 bit 4 C26 I O46 I O I O Bit 46 Base 5 bit 6 C27 N C No Connect C28 N C No Connect C29 N C No Connect C30 N C No Connect C31 GND Common Return C32 45V Supply 5V Supply J1 J3 A JEXP C For interboard connection Consult the factory if pinout information is needed ACC 3E 144 I O Piggyback Board Header Descriptions
29. bits as inputs or outputs This control mechanism allows the user to ensure the inputs will always be read properly Our traditional I O accessories always define the inputs and outputs by hardware The register select bits allow the user to define the input or output bytes inversion control or the latching input features Using Acc 3E with Turbo UMAC 5 Accessory 3E Direction Control Bits Bits 0 to 5 of the control register simply control the direction of the I O for the matching numbered data register That is Bit n controls the direction of the I O at Base n A value of 0 in the control bit the default permits a write operation to the data register enabling the output function for each line in the register Enabling the output function does not prevent the use of any or all of the lines as inputs as long as the outputs are off non conducting A value of 1 in the control bit does not permit a write operation to the data register disabling the output reserving the register for inputs For example a value of 1 in Bit 3 disables the write function into the data register at address Base 3 ensuring that lines 024 IO31 can always be used as inputs Register Select Control Bits Bits 6 and 7 of the control register together select which of 4 possible registers can be accessed at each of the addresses Base 0 through Base 5 They also select which of 2 possible registers can be selected at Base 6 The following
30. d as 12 hexadecimal digits The first 6 digits specify the number and address of 48 bit 3 x 16 real time MACRO node register sets to be used The second 6 digits specify the number and address of 16 bit I O sets on the MACRO Station I O accessory board to be used The individual digits are specified as follows Digit Possible Values Description 1 0 1 2 3 Number of MACRO I O nodes to use 0 disables this should also match the number of 48 bit I O sets you intend to use see Digit 7 2 0 Reserved for future use 3 6 COAI1 Node 2 MACRO Station X Address of MACRO I O node first of three 16 bit 5 Node 3 registers COA9 Node 6 COAD Node 7 COB1 Node 10 5 Node 11 7 0 1 2 3 Number of 16 bit I O sets to use 1x16 2x16 3x16 0 disables 0 Reserved for future use 9 12 FFCO FFC8 MACRO Station Y Base Address of I O Board as set by Board Jumper FFDO FFD8 1 4 ACC 3E board or E15 E18 ACC 4E board FFE0 FFE8 MACRO Station Y Base Address of ACC 9E 10 FFF8 12 ACC 13E When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull hig
31. e method it would be ideal if the inputs and outputs were used in multiples of 16 Example 48 inputs 32 inputs 16 outputs 16 inputs 32 outputs or 48 output see Example 1 If the 16 bit word is to be split eight in and eight out then we would read the word at the beginning of the PLC and write the word at the end of the PLC However instead of writing the value of the inputs to the output word you must write zeros to all input bits of this in out word see Example 3 This is because writing a value of 1 toa MACRO I O register makes that I O bit an output only bit Example Setup System Configuration 8 axis PWM System w 96 bit 1 0 48 inputs amp 48 outputs ACC 11E PMAC Ultralite Setup 1996 5 activates nodes 1 2 3 4 5 8 9 12 13 at Ultralite TURBO PMAC Ultralite Setup I6841 FB33F activates nodes 1 2 3 4 5 8 9 12 and 13 at Turbo Ultralite Macro Station Definitions 50 169 520 0 130 0 sets up macro to transfer data for ACC11E MS0 MI975 C enable node 2 and for I O MS0 MI19 4 sets interrupt period for data transfer MSSAVEO save to macro station 55550 macro station to enable Using Acc 3E with Turbo UMAC 17 Accessory 3E Active Nodes for Compact MACRO I O Station Option Node s Gate Addresses Node Transfer Addresses 48 Bit 2 FFC8 C0A1 C0A2 COA3 96 Bit 2 3 FFC8 C0A1 C0A2 COA3 FFCA C0A5 C0A6 COA7 144 Bit 2 3 6 FFC8 C
32. equals Output Mirror Word Output word equals Output Mirror Word Using Acc 3E with Turbo UMAC 21 Accessory 3E Example 2 48 Inputs 48 Outputs Using 1x24 Bit Transfers For this example the inputs and outputs are not sharing the same Node Transfer Address COA0 COA4 COA8 COBO Each of the node transfer addresses can be defined as 24 bit addresses Ultralite 8 Axis I996 0FB3FF Turbo Ultralite 8 Axis 16841 0FB3FF Description Enable nodes 0 1 2 3 4 5 6 7 8 9 12 amp 13 at PMAC Ultralite M970 gt X C0A0 0 24 M970 gt X 78420 0 24 IO word 1 24 bit word node2 M971 gt X C0A4 0 24 971 gt 78424 0 24 word 2 24 bit word node 3 M972 gt X C0A8 0 24 M972 gt X 78428 0 24 10 word 3 24 bit word node 6 M973 gt X COB0 0 24 M973 gt X 7842C 0 24 IO word 1 24 bit word node 7 M1000 gt X 0770 0 24 M1001 gt Y 0770 0 24 1002 gt 0771 0 24 1003 gt 50771 0 24 1010 gt 50772 0 24 1011 gt 50772 0 24 M1000 gt X 0010F0 0 24 M1001 gt Y 0010F0 0 24 M1002 gt X 0010F1 0 24 M1003 gt Y 0010F1 0 24 M1010 gt X 0010F2 0 24 M1011 gt Y 0010F2 0 24 Input mirror word 1 Input mirror word 2 Output mirror word 1 Output mirror word 2 Old Input mirror word 2 Old Input mirror word 3 MS0 MI71 2 20C0A020FFC8 MS0 MI975 CC sets up macro to transfer data for
33. from the MACRO Station 48 bit transfer 24 bit transfer and 72 bit transfer The PMAC2 Ultralite and the MACRO Station enable the user to transfer 72 bits per node For a multi Master system 432 bits 6x72 of data may be transferred for each Master Ultralite in the ring If only one Master is used in the ring node 14 could be used for I O transfer which would give us 504 bits 7x72 of I O transfer data For all MACRO Station I O accessories the information is transferred to or from the accessory I O Gate to the MACRO Station CPU Gate 2B Information from the MACRO Station Gate 2B is then read or written directly to the MACRO IC on the Ultralite Once the information is at the Ultralite it can be used in the users application motion programs or PLC programs Ultralite MACRO IC MACRO Station Gate 2B l O Accessory Gate Each I O board has jumper and software settings to select the I O transfer memory locations at both the I O transfer Gate and the MACRO transfer addresses These jumpers and software settings are discussed in this manual MACRO I O Gate Locations for ACC3E and ACCAE FFCO FFC2 FFC4 FFC8 FFCA FFCC FFDO FFD2 FFD4 FFD8 FFDA FFDC MACRO Station I O Node Transfer Addresses Node s Node 24 bit Transfer Node 16 bit upper 16 bits Transfer Addresses Addresses 2 X C0A0 X C0A2 X C0A3 3 X C0A4 X C0A5 X C0A6 X C0A7 6 X C0A8 X
34. gt Y 0770 8 16 M1001 gt Y 0010F0 8 16 Input mirror word 2 M1002 gt X 0771 8 16 M1002 gt X 0010F1 8 16 Input mirror word 3 1003 gt 50771 8 16 M1003 gt Y 0010F1 8 16 Output mirror word 1 M1004 gt X 0772 8 16 M1004 gt X 0010F2 8 16 Output mirror word 2 M1005 gt Y 0772 8 16 M1005 gt Y 0010F2 8 16 Output mirror word 3 M1010 gt X 0773 8 16 M1010 gt X 0010F3 8 16 Old Image mirror word 1 M1011 gt Y 0773 8 16 M1011 gt Y 0010F3 8 16 Old Image mirror word 2 M1012 gt X 0774 8 16 M1012 gt X 0010F4 8 16 Old Image mirror word 3 MS0 MI975 C 50 119 4 MSSAVEO 55550 OPEN PLC1 CLEAR M1000 M980 1001 981 1002 982 IF 1000 1010 1001 1011 1010 1000 1011 1001 983 1003 984 1004 985 1005 ENDIF CLOSE MS0 MI69 20C0A130FFC8 sets up macro to transfer data for ACC3E w E2 jumpered enable node 2 and 3 for I O sets interrupt period for data transfer save to macro station macro station to enable new input mirror equal to actual input word new input mirror equal to actual input word if inputs change process outputs old input mirror equal to new input mirror old input mirror equal to new input mirror Set outputs based on inputs or program logic Output word equals Output Mirror Word Output word
35. h Writing a 1 to a bit of the I O board enables it as an output and pulls the output low Example 1 48 bit I O transfer using node 2 with jumper E2 of ACC 3E selected MSO MI69 10COA130FFC8 2 2 96 bit I O transfer using nodes 2 amp 3 jumper E2 of ACC 3E 72 inputs 24 outputs MSO 69 520 0 130 8 3 244 bit I O transfer using nodes 2 3 6 7 10 and 11 using two ACC 3Es Jumper E2 on the first ACC3E and E3 jumpered on the second ACC3E MSO 69 530 0 130 8 MSO MI70 30COAD30FFDO 71 specifies the registers used in 24 bit I O transfers between MACRO I O node interface registers and I O registers on the MACRO Station I O accessory board It is used only if MI19 is greater than 0 12 Using Acc 3E with Turbo UMAC Accessory 3E is a 48 bit variable represented as 12 hexadecimal digits The first 6 digits specify the number and address of 48 bit real time MACRO node register sets to be used The second 6 digits specify the number and address of 48 bit I O sets on the MACRO Station I O accessory board to be used The individual digits are specified as follows Digit Possible Values Description 1 0 1 2 3 Number of MACRO I O nodes to use times 2 0 disables this should also match the number of 48 bit I O sets you intend to use see Digit 7 2 0 Reserved for future use 3 6 Node 2 MACRO Station X Address of MACRO I O node first of three 16 b
36. ion table and it s setup is described in the TURBO PMAC Software Reference Manual UMAC Turbo Memory Mapping for ACC 3E The Dalta Tau I O Gate used on the ACC 3E is an 8 bit processor and therefore the memory mapping to the I O bits is processed as 8 bit words at the Turbo UMAC Using this simple scheme the user could process up to 576 1444 bits of data for general purpose I O Jumper E1 Jumper E2 Jumper E3 Jumper E4 Description 5078800 0 8 5078900 0 8 5078400 0 8 Y 078B00 0 8 T O bits 0 7 74 5078801 0 8 5078901 0 8 5078 01 0 8 5078 01 0 8 I O bits 8 15 J4 5078802 0 8 5078902 0 8 Y 5078A02 0 8 5078 02 0 8 bits 16 23 14 5078803 0 8 5078903 0 8 5078 03 0 8 5078 03 0 8 bits 24 31 J5 5078804 0 8 5078904 0 8 Y 078A04 0 8 5078 04 0 8 T O bits 32 39 15 5078805 0 8 5078905 0 8 Y 078A05 0 8 5078 05 0 8 T O bits 40 47 15 Y 5078807 0 8 Y 507890 7 058 5078 07 0 8 078B07 0 8 Control Word 5078800 8 8 5078900 8 8 Y 078A00 8 8 Y 5078B00 8 8 bits 0 7 76 5078801 8 8 5078901 8 8 Y S078A01 8 8 Y 5078B01 8 8 T O bits 8 15 J6 5078802 8 8 5078902 8 8 Y 078A02 8 8 5078 02 8 8 T O bits 16 23 16 5078803 8 8 5078903 8 8 Y 5078A03 8 8 5078 03 8 8 I O bits 24 31 J7 5078804 8 8 5078904 8 8 Y 5078A04 8 8
37. it Node 3 registers COAS Node 6 COAC Node 7 COBO Node 10 COB4 Node 11 7 0 1 2 Number of 24 bit I O sets to use 1x24 2x24 0 disables 0 Reserved for future use 9 12 FFCO FFC8 MACRO Station Y Base Address of I O Board as set by Board Jumper FFDO FFD8 1 4 ACC 3E board or E15 E18 ACC 4E board FFEO FFE8 MACRO Station Y Base Address of ACC 9E ACC 10E ACC 11E FFFO FFF8 ACC 12E and ACC 13E When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low Example 1 Two 24 bit I O transfers using nodes 2 and 3 with jumper E2 selected MSO MI71 2 10C0A020FFC8 2 96 bit I O transfer using nodes 2 3 6 and 7 jumper E2 of ACC 3E MSO MI71 20C0A020FFC8 3 144 bit I O transfer using nodes 2 3 6 7 10 and 11 using two ACC 3Es MSO MI71 30C0A020FFC8 MI169 and MI170 specify the registers used in 72 bit I O transfers between one MACRO node interface register and I O registers on a MACRO station They are used only if MI19 is greater than 0 MI169 and MI170 are 48 bit variables rep
38. ith Turbo UMAC Accessory 3E Digit Possible Values Description 1 0 Reserved for future use 2 0 Reserved for future use 3 6 COAO Nodes 2 3 MACRO Station X Address of MACRO I O first 24 bit COA4 Nodes 3 6 register of the two consecutive nodes COAS Nodes 6 7 COAC Nodes 7 10 COBO Nodes 10 11 COBA Nodes 11 14 7 0 Reserved for future use 8 0 Reserved for future use 9 12 FFCO FFC8 MACRO Station Y Base Address of I O Board as set by FFD0 FFD8 Board Jumper 1 4 board or 15 18 ACC 4E FFE0 FFE8 board FFF0 FFF8 MACRO Station Y Base Address of ACC 9E ACC 10E ACC 11E ACC 12E and ACC 13E When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output pulling the output low The following table shows the mapping of I O points on the I O piggyback boards to the MACRO node registers I O points move from the least significant bit to the most significant bit I O00 at Node bit 0 Point s Option Part Present on Option 4 Matching MACRO X Regi
39. itialize read write I O bits OPEN PLC 1 CLEAR M2007 S3F define bits 0 23 and 24 47 as inputs ACC 3E 2015 500 define bits 0 23 24 47 as outputs 2023 507 define bits 0 23 as inputs and bits 24 47 as outputs ACC 4E DIS CLOSE Accessory M Variables for UMAC Turbo The following is a list of suggested M variables for the default jumper settings is provided You may assign any M variables to these addresses For this example we are assuming 24 inputs and 24 outputs The user may make these M variable definitions and use them as general purpose I O for their PLC s or motion programs 7000 gt 5079 00 0 1 Input 0 7024 gt 5079 03 0 1 Output 0 7001 gt 5079 00 1 1 Input 1 7025 gt 5079 03 1 1 Output 1 7002 gt 5079 00 2 1 Input 2 7026 gt 5079 03 2 1 Output 2 7003 gt 5079 00 3 1 Input 3 7027 gt Y 079C03 3 1 Output 3 7004 gt 5079 00 4 1 Input 4 7028 gt 5079 03 4 1 Output 4 7005 gt 5079 00 5 1 Input 5 7029 gt 5079 03 5 1 Output 5 7006 gt 5079 00 6 1 Input 6 7030 gt 5079 03 6 1 Output 6 7007 gt 5079 00 7 1 Input 7 7031 gt Y 079C03 7 1 Output 7 7008 gt 5079 01 0 1 Input 8 7032 gt 5079 04 0 1 Output 8 7009 gt 5079 01 1 1 Input 9 7033 gt 5079 04 1 1 Output 9 7010 gt 5079 01 2 1 Input 10 7034 gt 5079 04 2 1 Output 10 7011 gt 5079 01 3 1 Input 11 7035 g
40. nputs and outputs programmable polarity J9 50 Header Connector Description ep View 2 Pin Symbol Function Description Notes 1 1 0143 I O Bit 143 2 GND Common Return 3 1 0142 I O Bit 142 4 GND Common Return 5 1 0141 I O Bit 141 6 GND Common Return 7 1 0140 VO I O Bit 140 8 GND Common Return 9 1 0139 T O Bit 139 10 GND Common Return 11 1 0138 I O Bit 138 12 GND Common Return 13 I O137 I O Bit 137 14 GND Common Return 15 1 0136 VO I O Bit 136 16 GND Common Return 17 1 0135 I O Bit 135 18 GND Common Return 19 I O134 IO I O Bit 134 20 GND Common Return 21 1 0133 I O Bit 133 22 GND Common Return 23 1 0132 I O Bit 132 24 GND Common Return 25 I O131 IO I O Bit 131 26 GND Common Return ACC 3E 144 I O Piggyback Board Header Descriptions Accessory 3E 27 1 0130 I O Bit 130 28 GND Common Return 29 I O129 I O I O Bit 129 30 GND Common Return 31 1 0128 I O Bit 128 32 GND Common Return 33 1 0127 I O I O Bit 127 34 GND Common Return 35 I O126 I O I O Bit 126 36 GND Common Return 37 I O125 I O Bit 125 38 GND Common Return 39 I O124 I O Bit 124 40 GND Common Return 41 1 0123 I O I O Bit 123 42 GND Common Return 43 1 0122 T O I
41. resented as 12 hexadecimal digits The first 6 digits specify the address of 72 bit 24 amp 3 x 16 bit real time MACRO node register to be used The second 6 digits specify the address of the LOWER I O Gate on an Option 3 or Option 4 board to be used The individual digits are specified as follows Using Acc 3E with Turbo UMAC 13 Accessory 3E Digit Possible Values Description 1 0 Reserved for future use 2 0 Reserved for future use 3 6 Node 2 MACRO Station X Address of MACRO I O node 24 bit register C0A4 Node 3 C0A8 Node 6 C0AC Node 7 COBO Node 10 C0B4 Node 11 7 0 Reserved for future use 0 Reserved for future use 9 12 FFC0 FFC8 MACRO Station Y Base Address of I O Board as set by Board Jumper FFD0 FFD8 E1 E4 ACC 3E board or E15 E18 ACC 4E board FFE0 FFE8 MACRO Station Y Base Address of ACC 9E 10 SFFF8 ACC 12E and ACC 13E When this function is active the MACRO Station will copy values from the MACRO command input node registers to the I O board addresses it will copy values from the I O board addresses to the MACRO feedback output node registers Writing a 0 to a bit of the I O board enables it as an input letting the output pull high Writing a 1 to a bit of the I O board enables it as an output and pulls the output low The following table shows the mapping of I O points on
42. rried out using M variables like other tradition PMAC products ACC 3E is one of the series of MACRO Stack accessories designed to transfer data to the MACRO Station through its JEXP port pins plugged directly into the stack The other boards in the family of MACRO accessories are 1 2 axis Expansion ACC 2E 4 Axis Expansion Card ACC 3E up to 144 bits TTL level I O ACC 4E 48 bits optically isolated I O ACC 6E 8 16 channels 12 bit A D Converters Introduction Accessory 3E Introduction Accessory 3E HARDWARE SETUP The ACC 3E uses expansion port memory locations defined by the type of PMAC 3U Turbo or MACRO Station it is directly communicating to These memory locations are typically used with other Delta Tau 3U I O accessories such as ACC 4E 24 inputs and 24 outputs low power all optically isolated ACC 6E 16 channels 12 bit ADC All of these accessories have settings which tell them where the information is to be processed at either the PMAC 3U Turbo or the MACRO Station 3U Turbo PMAC MACRO Station Memory Locations Memory Locations 078800 FFCO 078900 FFC8 078A00 FFDO 078B00 FFD8 The ACC 3E has a set of jumers E1 through 4 telling it where to process its data Once the information Is at these locations we can process the binary word in the encoder conversion table to use for servo loop closure Proper setting of
43. sing electrical shorts When our products are used in an industrial environment install them into an industrial electrical cabinet or industrial PC to protect them from excessive or corrosive moisture abnormal ambient temperatures and conductive materials If Delta Tau Data Systems Inc products are directly exposed to hazardous or conductive materials and or environments we cannot guarantee their operation Accessory 3E Table of Contents INTRODUCTION A E AO 1 I EH QUUEVILURI OM UJ Lise 3 Board ete eae ee ie ep b bed tir reel tide ets 3 t i eie d 4 ACC 3E 48 96 144 I O Board 4 EI E4 I O Gate Address Select Jumpers eese 4 EI E4 I O Gate Address Select Jumpers 4 USING ACC 3E WITH TURBO UMAC 5 UMAC Turbo Memory Mapping for ACC 3E 5 Control Revistei uidi aus Pesca s est e epe tube 5 Direction Control 6 Register Select Control Bits tiet taste ti edet esta tiet a bete
44. ster I O00 1 015 Sub option A Yes Specified MACRO X Address 1 1 016 1 031 Sub option A Yes Specified MACRO X Address 2 1 032 1 047 Sub option A Yes Specified MACRO X Address 3 1 048 1 063 Sub option B No Specified MACRO X Address 5 1 064 1 079 Sub option B No Specified MACRO X Address 6 1 080 1 095 Sub option B No Specified MACRO X Address 7 1 096 1 0119 Sub option C No Specified MACRO X Address 0 1 0120 1 0143 Sub option C No Specified MACRO X Address 4 Example 1 Transfer 72 bits I O transfers using nodes 2 and 3 with jumper E2 of ACC 3E MSO MI171 00C0A000FFC8 Using Acc 3E with Turbo UMAC 15 ACC 3E Setup with MACRO Accessory 3E Normally the user will have a PLC to read the input word and write to the output word based on the input logic of the program With the MACRO I O interface this can also be accomplished by either using the 48 bit transfer 24 bit transfer or 72 bit transfer These words would be defined as an input word output word or in out word combination of the two With the MACRO I O Accessories the 72 bit word is split into 3x16 bit transfers 1x24 bit transfers or a combination of the two Node Node 24 bit Transfer Node 16 bit upper 16 bits Transfer Addresses Addresses 2 X COAO X COA2 X C0A3 3 4 X C0A5 X C0A6 X C0A7 6 X C0A8 X C0A9 X C0AA X C0AB 7 X C0B0 X C0B1 X C0B2
45. t 1011 57 1012 gt C0A1 8 16 C0A2 8 16 C0A3 8 16 C0A5 8 16 C0A6 8 16 C0A7 8 16 word 1 1 16 bit word node2 word 2 2 16 bit word node 2 word 3 3 16 bit word node 2 word 1 1 16 bit word node word 2 2 16 bit word node 3 word 3 3 16 bit word node 3 0770 8 16 Input mirror word 1 0770 8 16 Input mirror word 2 0771 8 16 Input mirror word 3 0771 8 16 Output mirror word 1 0772 8 16 Output mirror word 2 0772 8 16 Output mirror word 3 0773 8 16 Old Image mirror word 1 0773 8 16 Old Image mirror word 2 0774 8 16 Old Image mirror word 3 IO word 1 IO Word 2 IO Word 3 800 gt 5770 8 801 gt 5770 9 816 gt 5770 8 817 gt 5770 9 832 gt 5771 8 833 gt 5771 9 802 gt 5770 10 M818 gt Y 770 10 M834 gt X 771 10 M803 gt X 770 11 M819 gt Y 770 11 M835 gt X 771 11 M804 gt X 770 12 M820 gt Y 770 12 M836 gt X 771 12 M805 gt X 770 13 M829 gt Y 770 13 M837 gt X 771 13 M806 gt X 770 14 M822 gt Y 770 14 M838 gt X 771 14 807 gt 5770 15 M823 gt Y 770 15 M839 gt X 771 15 M808 gt X 770 16 M824 gt Y 770 16 840 gt 6771 16 M809 gt X 770 17 M825 gt Y 770 17 M841 gt X 771 17 810 gt 5770 18 M826 gt Y 770 18 M842 gt X 771 18 M811 gt X 770 19 M827 gt Y 770 19 M843 gt X 771 19 M812 gt X 770 20 M82
46. t 5079 04 3 1 Output 11 7012 gt 5079 01 4 1 Input 12 7036 gt 5079 04 4 1 Output 12 7013 gt 5079 01 5 1 Input 13 7037 gt 5079 04 5 1 Output 13 Using with Turbo UMAC Accessory 3E 7014 gt Y S079C01 6 1 Input 14 7038 gt 5079 04 6 1 Output 14 7015 gt 5079 01 7 1 Input 15 7039 gt 5079 04 7 1 Output 15 7016 gt 5079 02 0 1 Input 16 7040 gt 5079 05 0 1 Output 16 7017 gt 5079 02 1 1 Input 17 7041 gt 5079 05 1 1 Output 17 7018 gt 5079 02 2 1 Input 18 7042 gt 5079 05 2 1 Output 18 7019 gt 5079 02 3 1 Input 19 7043 gt 5079 05 3 1 Output 19 7020 gt 5079 02 4 1 Input 20 7044 gt 5079 05 4 1 Output 20 7021 gt 5079 02 5 1 Input 21 7045 gt 5079 05 5 1 Output 21 7022 gt 5079 02 6 1 Input 22 7046 gt 5079 05 6 1 Output 22 7023 gt 5079 02 7 1 Input 23 7047 gt 5079 05 7 1 Output 23 P Sample E Stop PLC This PLC will abort all motion programs and kill the bus voltage to the motors when E stop is depressed When E Stop button in pulled out the motors will servo to actual position ctrl A command after allowing 5 seconds for proper bus voltage 7000 used as Latch variable E M7000 used Emergancy Stop Input M7024 used as Main Contact for main for Bus Voltage I5111 used as count down timer OPEN PLC 5 CLEAR
47. the dip switches ensures all of the JEXP boards used in the application do not interfere with each other ACC 3E Board Layout ind XXX Hardware Setup 3 Accessory 3E Connectors J1 JEXP A 40 pin header for connection to piggyback board s J2 JEXP B 40 pin header for connection to piggyback board s J3 C 28 pin header for connection to piggyback board s 50 pin IDC header for connection of 1 000 to I O23 to Opto 22 G4PB24 or equivalent I O board with straight across connector Option A required J5 50 pin IDC header for connection of I O24 to I O47 to Opto 22 G4PB24 or equivalent I O board with straight across connector Option A required J6 50 pin IDC header for connection of I O48 to I O71 to Opto 22 G4PB24 or equivalent I O board with straight across connector Option B required J7 50 pin IDC header for connection of I O72 to I O95 to Opto 22 G4PB24 or equivalent I O board with straight across connector Option B required J8 50 pin IDC header for connection of I O96 to I O119 to Opto 22 G4PB24 or equivalent I O board with straight across connector Option C required J9 50 pin IDC header for connection of 1 0120 to 1 0143 to Opto 22 G4PB24 or equivalent I O board with straight across connector Option C required J10 26 pin IDC header for connection of optically isolated outputs for I O120 to I O127 and optically isolated inputs for I O128
48. tions Accessory 3E P1 96 Pin Header H Option A Required DOO A Pin Symbol Function Description Notes A01 45V Supply 5V Supply A02 GND Common Return A03 I O01 I O I O Bit 1 Base 0 bit 1 A04 1 003 I O Bit 3 Base 0 bit 3 05 1 O05 I O Bit 5 Base 0 bit 5 A06 1I O07 I O I O Bit 7 Base 0 bit 7 A07 1 O09 I O Bit 9 Base 1 bit 1 A08 I O11 I O Bit 11 Base 1 bit 3 A09 I O13 I O I O Bit 13 Base 1 bit 5 A10 I O15 T O Bit 15 Base 1 bit 7 All I O17 I O I O Bit 17 Base 2 bit 1 A12 I O19 VO T O Bit 19 Base 2 bit 3 A13 I O21 I O I O Bit 21 Base 2 bit 5 14 1 023 T O Bit 23 Base 2 bit 7 15 25 T O Bit 25 Base 3 bit 1 A16 27 Bit 27 Base 3 bit 3 A17 1 029 T O Bit 29 Base 3 bit 5 A18 I O31 T O Bit 31 Base 3 bit 7 A19 1I O33 I O I O Bit 33 Base 4 bit 1 A20 1 035 T O Bit 35 Base 4 bit 3 A21 1 037 T O Bit 37 Base 4 bit 5 A22 1 O39 I O I O Bit 39 Base 4 bit 7 A23 I O41 I O Bit 41 Base 5 bit 1 24 1 043 T O Bit 43 Base 5 bit 3 A25 I O45 I O I O Bit 45 Base 5 bit 5 A26 1 047 I O Bit 47 Base 5 bit 7 27 N C No Connect A28 N C No Connect A29 N C No Connect A30 N C No Connect A31 GND Common Return A32 5V Supply 5V Supply A
49. to I O143 Option C1 or C2 required P1 96 pin DIN connector for connection of I O00 to I O47 Option A required TB1 2 pin terminal block for 5V power supply ACC 3E 48 96 144 Board Jumpers 1 4 Gate Address Select Jumpers Jumper Setting UMAC UMAC e MACRO TURBO 1 1 2 7 078800 078807 2 1 2 8 078900 078907 1 2 FFDO FFD7 078A00 078A07 XY 8 E4 1 2 8 078 00 078 07 Note Only one of E1 to E4 may be ON on any board If more than one of these boards is used in a given UMAC MACRO or UMAC Turbo each must have a different jumper ON E1 E4 I O Gate Address Select Jumpers Jump pins 1 and 2 to latch inputs on the SERVO clock Jump pins 2 and 3 to latch inputs on the PHASE clock default 4 Hardware Setup Accessory 3E USING ACC 3E WITH TURBO UMAC For the UMAC Turbo the ACC 3E can be used for either general purpose I O or as latched inputs for servo loop position or velocity feedback registers used for general I O use 8 bit registers and the user will define three 8 bit registers for each 24 bit I O port To use the ACC 3E for closed loop servo data the user must setup various I variables for the encoder conversion table and power on position The encoder conversion table is setup using variables 18000 through 18192 Each variable is an entry in the convers
50. urn 13 65 I O I O Bit 65 14 GND Common Return 15 I O64 I O I O Bit 64 16 GND Common Return 17 1 063 T O Bit 63 18 GND Common Return 19 1 062 I O I O Bit 62 20 GND Common Return 21 I O61 I O I O Bit 61 22 GND Common Return 23 1 060 I O I O Bit 60 24 GND Common Return 25 1 059 I O Bit 59 26 GND Common Return 27 1 058 I O I O Bit 58 ii 28 GND Common Return 29 1 057 I O I O Bit 57 30 GND Common Return 31 1 056 I O I O Bit 56 32 GND Common Return 33 1055 I O I O Bit 55 ii 34 GND Common Return 35 I O54 I O I O Bit 54 36 GND Common Return 37 1 053 I O I O Bit 53 ACC 3E 144 I O Piggyback Board Header Descriptions 28 Accessory 3E 38 GND Common Return 39 1 052 I O I O Bit 52 40 GND Common Return 41 I O51 T O Bit 51 42 GND Common Return 43 1 050 T O Bit 50 44 GND Common Return 45 1 049 I O I O Bit 49 46 GND Common Return 47 I O48 I O I O Bit 48 48 GND Common Return 49 45V Output 5 V Supply 50 GND Common Return Default low true inputs and outputs programmable polarity J7 50 Pin Header Connector View 2 Description Pin Symbol Function Description Notes 1 1 095 I O I O Bit 95 2 GND Common Return 3 1 094 I O I O Bit 94 4 GND Common Return 5 1 0

^1 USER MANUAL ^2 Accessory 3E

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