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Fall2011 Workshop Handout

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1. ARCHITECTURE logic OF my_memory IS Creates new array data type named mem which has 64 address locations each 8 bits wide TYPE mem IS ARRAY 0 to 63 OF std_logic_vector 7 DOWNTO 0 Creates 2 64x8 bit array to use in design SIGNAL mem_64x8_a mem_64x8_b mem BEGIN mem 64x8 a 12 lt x
2. Devices All ji Pin count 1256 v Be speed gode FE gt Auto device selected by the Fitter Show advanced devices Specific device selected in Available devices list HardCopy compatible only Other nja Let Fitter select part or ni Show advanced devices Choose specific part from list Name Core Voltage slobal Clocks EP3CSF256C6 1 2V EES 5 423936 10 EP3C1OF256C6 1 24 10320 423936 10 EP3C16F256C6 1 2V 15405 516096 20 EPSC25F256C6 1 2V 24624 608256 20 Available devices Companion device HardCopy Limit DSP amp RAM to HardCopy device resources Tcl set global assignment name FAMILY device family name Tcl set global assignment name DEVICE part number 24 8 29 2011 EDA Tool Setting m Choose EDA tools and file formats m Settings can be changed or added later EDA Tool Settings page 4 of 5 Specify the other EDA tools used with the Quartus II software to develop your project EDA tools Tool Type Tool Name Format s Run Tool Automatically Design Entry Synthesis Synplify Pro v EDIF Simulation ModelSim Altera v VHDL p E D Run gate level simulation automatically after compilation Timing Analysis lt None gt v ven HDL Run this tool automatically after compilation Formal Verification None v SystemVerilog HDL Board Level Timing lt None gt E Run this tool automatically to synthesize the current design Symbol lt None gt
3. Sponsored by p National Science Foundation Advanced Technological Education Award No DUE 1003389 VHDL and FPGA Design Workshop Nasser Alaraje PhD Michigan Tech University Associate Professor Program Chair Electrical Engineering Technology E mail alaraje mtu edu Aleksandr Sergeyev PhD Michigan Tech University Assistant Professor Electrical Engineering Technology E mail avsergue mtu edu Fred Scheu College of Lake County Instructor Program Chair Electrical Engineering Technology E mail fscheu clcillinois edu Carl Seidel EET Student Senior Michigan Tech University E mail csseidel mtu edu Sponsored by National Science Foundation Advanced Technological Education Award No DUE 1003389 VHDL and FPGA Design Workshop Nasser Alaraje PhD Michigan Tech University Associate Professor Program Chair Electrical Engineering Technology E mail alaraje mtu edu Aleksandr Sergeyev PhD Michigan Tech University Assistant Professor Electrical Engineering Technology E mail avserque mtu edu Fred Scheu College of Lake County Instructor Program Chair Electrical Engineering Technology E mail fscheu clcillinois edu Carl Seidel EET Student Senior Michigan Tech University E mail csseidel mtu edu Syllabus Day 1 9 00 am Introduction 9 15 am What s an FPGA 9 45 am FPGA Design Techniques 1 00 pm Lab 1 Introduction to Altera s Quartus 2 30 pm Introduction to VHDL 3 30 a
4. time 10 20 30 ns Provide testbench file to simulator Simulator generates waveforms Wecan then check if behavior looks correct Simulator CompToTest And2 PORT MAP x s y S F_s PROCESS BEGIN Test all possible input combinations y s lt 0 x s lt WAIT FOR 10 ns ys lt 0 xs lt WAIT FOR 10 ns ys lt 1 x Ss lt WAIT FOR 10 ns y s lt I t kS lt WAIT END PROCESS END TBarch ieee std logic 1164 ALL ITY Testbench IS END Testbench ARCHITECTURE TBarch OF Testbench IS COMPONENT And2 IS PORT x IN std logic y IN std logic F OUT std logic END COMPONENT SIGNAL x s y S F s std logic BEGIN CompToTest And2 PORT MAP x s y s F s PROCESS BEGIN Test all possible input combinations y_s lt 0 x_s lt 0 WAIT FOR 10 ns y_s lt 0 17 WAIT FOR 10 y_s lt 1 or WAIT FOR 10 y s lt 1 x 17 WAIT END PROCESS END TBarch AND Gate imulation and Testbenche 8 29 2011 80 8 29 2011 Please go to Lab2 Introduction to VHDL inthe Manual Sylabus Day 1 9 00 am Introduction 9 15 am What s an FPGA 9 45 am FPGA Design Techniques 1 00 pm Lab 1 Introduction to Altera s Quartus 2 30 pm Introduction to VHDL 3 30 am Lab 2 Introduction to VHDL Day 2 9 00 am Lab 3 VHDL Testbench Lab 10 00 am Advanced VHDL 11 00 am Lab 4 Advanced VHDL 1 00 pm Final Project using DE2 3 00 pm Support System Softw
5. Critical Warning 1 i M 8i L E es im Er EA a IBI l Dr i Warning 10631 Warning Latch next state S4 148 has unsafe behavior and others are due to unintentional latching conditions caused by not initializing the signals assigned within a case statement Messages Message Oof 30 4 Open the RTL Viewer to see the complex logic that this unintentional latching creates Upon simulation the circuit design may also produce unintended results due to these latches rn 5 Highlight Line 29 in the Lab3b vhd code and click the Uncomment selected text button _ This adds an initialization value at the beginning of the case statement for the next state signal ae State machine PROCESS d B current state next State an BEGIN 29 30 w OLSE current state 31 WHEN 51 gt 6 Save the changes and compile the design Now it can be seen that the only warnings left relate to specifics regarding pin assignments on the physical FPGA device 7 Open the RTL Viewer again to see that now the logic is much simplified and what we intended current state state_data O state _datal 0 Task 4 State Machine Encoding 1 Double clicking the yellow current_state box in the RTL Viewer will open up the State Machine Viewer This graphically shows the state transitions and their associated conditions Alternately the State Machine Viewer can be opened by selecting Tools gt Netlist Viewers g
6. Qu lt 8 N 24 bs gogi nooo Jm pan q J sums annm mE 0010 0110 sels cou s clk Nowy Cursor 1 Task 3 Editing the Test Bench 1 Look at the Adder_Process of the lab4 vhd code here is where the values for the two four bit numbers are assigned as well as where the add subtract selection is made More input combinations can be created to test additional input scenarios To see what output an overflow condition would generate add the following on lines 33 and 34 As lt 1100 Bs lt 0100 Sel s lt 0 WAIT FOR 10 ns The resulting Adder_Process should look similar to the image below ao Adder Process PROCESS 26 BEGIN 21 A oas DDOO I BS MOQO i GEL g e N 20 WAIT FOR 10 ns 23 A Bore MO Ss bog ce T T FELGEN 30 WAIT FOR 10 ns 34 ASS ett UDIUOUI Dog SOOO Se oe ux 34 WAIT FOR 10 ns 3d Aso cm CUYO Dogocm ORO S8ISB8 c r 34 WAIT FOR 10 ns 38 END PROCESS This will cause our adder subtractor to add 12 1100 with 4 0100 which would give us the result of 16 10000 but because of the four bit limit for our sum_s signal an overflow condition will result 4 6 2 Save the changes to Lab4 vhd by clicking the Save button i on the toolbar then select the Project tab and right click Lab4 vhd and select Compile gt Compile Selected fee Project Hi Altera Training Lab4 Lab4 qu ig XI RI m And hd WHOL 0 05 18 11 02 31 09 PM ka Fulladder hd VHDL 1 D5 18 11 03
7. Signal Integrity lt None gt Boundary Scan lt None gt See handbook for Tcl command format New Project Wizard Summary page 5 of 5 When you click Finish the project will be created with the Following settings Project directory Project name Top level design entity Number of Files added Number of user libraries added Device assignments Family name Device EDA tools Design entry synthesis Simulation Timing analysis Operating conditions VCCINT voltage Junction temperature range Cialtera trn Quartus II Software Design Series Foundation QIIF10 0OJEx1 Verilog pipemult pipemult 1 0 Cyclone III EP3CSF256C6 Review results amp click Finish Synplify Pro EDIF ModelSim Altera VHDL Mone lt None gt 25 8 29 2011 Top Level Top level design files file can be schematic HDL Quartus Il design entry or 3 d Party netlist file Text editor Verilog or SystemVerilog 5 g mnm Schematic editor Block Symbol Text Text State Block Diagram File file file file file Machine Text file De file State machine editor e HDL from state machine file el Imported from 3 Generated within Quartus II Party EDA tools Memory editor software e HEX Mir Design Entry 3rd party EDA tools EDIF200 Methods Verilog Quartus Mapping VOM Mixing amp matching design files allowed New Quartus II Project I SOPC Builder System z Des
8. PER Flow Settings Flow Mon DeFaulk Global Settings Flow Status Quartus Yersion Successful Wed May 25 03 06 33 2011 4 1 Build 222 10 21 2009 5J Full Version Hevisian M Lab3 SES Flow Elapsed Time m iis 3 SE Flaw OS SUMAG Top level Entity Mame Labia Flow Log Family Cyclone eh Fitter Timing Models Final Assembler Met timing requirements es an ea Timing Analyzer Total logic elements 1 33215 1 Total combinational functions 1 33215 1 X Dedicated logic registers U S3h 216 0 4 Total registers 0 Total ping ols a Total virtual ping 0 Total memory bits Uy 483 840 0 Embedded Multiplier 3 bit elements Sr 70 7X Total PLL Uz 4 0 x 7 View the Timing Analyzer Summary to see that although fewer components have been utilized the clock speed has been reduced slightly Timing Analyzer Summary m Compilation Report BE Legal Notice Compilation Report Timing Required Actual Bj Fon Suma fee sie fre ne PER Flow Settings 1 worstcasetsu N A None AIEN SE Flow Non Default Global Settings Worst case too M Mone 8 480 ns EES Flow Elapsed Time worst case th M A None 3 E90 22 i ei Clock Setup CLK N A None SE ands Synthesis Total number of Failed paths Fitter mh Assembler EE Timing Analyzer SE Summary hE Settings 3 5 8 Open the RTL Viewer again to see the new schematic diagram for the circuit design Compare this sc
9. y lt a b c z lt b c d Multipliers Answer 4 Multipliers 109 8 29 2011 How Many Multipliers Again Multipliers Again Answer 3 Multipliers This is called sharing common subexpressions Some synthesis tools do this automatically but some don t Parentheses guide synthesis tools If b c is used repeatedly assign to temporary signal 110 8 29 2011 111 8 29 2011 Educational Project Website Materials Available http www tech mtu edu NSFATE Altera University Program website http www altera com education univ unv index html do you really need to start Quratus Software e DE2 FPGA board 112 8 29 2011 SW HW donation Register with Altera website Request DE2 Boards http www altera com education univ materials boards de2 115 unv de2 115 board html workshop We will offer one more free two day workshop Time Summer 2012 Date TBD Location College of Lake County IL 113 8 29 2011 Post Test survey 4 N oer 3 Advanced Technological Education Thanks to National Science Foundation 114 Lab Manual for VHDL and FPGA Design Workshop Software Requirements to complete all exercises Quartus Il software version 9 1 or newer Link to the Quartus II Handbook http www altera com literature hb qts quartusii handbook pdf Link to the project web page to download the related lab files http www tech mtu edu NS
10. 12 Open the RTL Viewer again to see the new schematic diagram Compared to the previous schematic diagrams you can see where the additional registers have been placed huti result 23 D regn Eme suit 23 7 v F JE esu 1 23 0 zF 0 ES w 7 0 Es Task 3 Preventing Latches 1 Create a New File Create a new VHDL file as discussed previously Copy and paste the following code into your new vhdl file and save it as Lab3b vhd Lab 3b Advanced VHDL State Machine Code LIBRARY eee USE ieee std logic 1164 all ENTITY Lab3b IS PORT A B aclr IN std logic CLK IN std logic state data OUT std logic vector 2 DOWNTO 0 END ARCHITECTURE Lab3b arch OF Lab3b IS TYPE State types IS SI TYPE IS One Hot Encoding Minimum Bits Gray Encoding Johnson Encoding Sequential Encoding current state next state State types transitions PROCESS aclr clk IF aclr 1 THEN current state lt SI 3 7 ELSIF rising edge clk THEN Current state lt next state D IF EN END PROCESS state transitions State machine PROCESS A B current state next state BEGIN next state lt current state CASE current state 5 WHEN S1 gt IF A 1 THEN next state lt 52 END IF WHEN 52 gt IF A 0 THEN next state lt SI ELSIF A 1 THEN next state lt 3 END IF WHEN 53 gt IF A 0 THEN next state lt SI ELSIF A 1 AND B 1 THEN next state lt 4 END IF WHE
11. EVENT AND clk 1 CASE filter IS WHEN idle gt IF nw 1 THEN filter lt tapl END IF WHEN tapl gt filter lt tap2 WHEN tap2 gt filter lt tap3 WHEN tap3 gt filter lt tap4 WHEN tap4 gt IF nw 1 THEN filter lt tapl ELSE filter lt idle END IF END CASE END IF END PROCESS out PROCESS filter BEGIN nxt lt 0 first lt 05 select lt 00 CASE filter IS WHEN idle gt WHEN tapl gt first lt 1 WHEN tap2 gt select lt OL WHEN tap3 gt select lt 10 WHEN tap4 gt select lt nxt lt 1 END CASE END PROCESS output END ARCHITECTURE logic 8 29 2011 nxt 0 first 1 select 0 first 0 first 0 select 2 select 1 FSM VHDL Code Next State Logic nxt 0 first 0 select 0 nxt 0 first 1 select 0 first 0 first 0 select 2 select 1 FSM VHDL Code Outputs Using CASE 85 8 29 2011 sing Signal Assignments nxt lt 1 WHEN filter tap4 ELSE 0 first lt 1 WHEN filter tapl ELSE nxt 0 first 1 IN O select 0 WITH filter SELECT select 00 WHEN tapl 0 WHEN tap2 select 2 select 1 10 WHEN tap3 11 WHEN tap4 Conditional 00 WHEN OTHERS signal assignments END ARCHITECTURE logic Selected signal assignments Simulation vs Synthesis e Simulation Code executed in the exact way it is written User has flexibility in writing Initializati
12. The setup instantiates a component representing the entity to be simulated CompToTest The setup uses a process that writes to signals x_s and y_s which are connected to the inputs of CompToTest The process will contain statements that set the signals with the desired test vectors 78 HDL testbench Entity with no ports Declare component to test u Declare signal for each port Instantiate component map signals to ports Set signal values at desired times 8 29 2011 mDTBRARY ieee JSE ieee std_logic_1164 ALL ENTITY Testbench IS END Testbench ARCHITECTURE TBarch OF Testbench IS COMPONENT And2 IS PORT x IN std_logic y IN std_logic F OUT std_logic END COMPONENT SIGNAL x s y S F s std logic BEGIN gt CenmpToTest And2 PORT MAP x S y S F s PROCESS BEGIN Test all possible input combinations WAIT FOR 10 ns T vos 102 zes lt 0 WAIT FOR 10 ns AND OR NOT Gates yes Ue ren Simulation and Testbenches OCess has no sensitivity list Executes immediately WAIT FOR 10 ns Tells simulator to suspend this process move simulation time forward by 10 ns before executing next statement WAIT no time clause Waits forever so process executes only once doesn t repeat Note Process cannot have both a sensitivity list and WAIT statement s AND Gate Simulation and Testbenches Ves lt xs c WAIT FOR 10 ns y s lt
13. Vref Group I O Standard 3 3 V LYTTL default DQS13B DQ 2B DQSn13B DQ7B DQ9B DQ9B PLL6_OUTOp CLK4p Top View Wire Bond Cyclone Il EP2CSF256C6 inex 8 9 0 1 122 13 dH 15 16 eO OA UNA AO x00008 DA XCX0V A9 0090 00 o0 EM VOX AY 200A OO AO Ox x KORK A 000008 9404940 6 C6 0 VES Ma ooet oo pO xxxs UA 22 aM 40 8 29 2011 Back Annotate Assignments Back annotation type Dial A n n ot a t O N Assignments to back annotate Device assignment iz EI Pin cell amp device assignments O Demote cell assignments to LABs Pin cell routing amp device assignments Delay chains Green brown pattern indicates D E tot backannotation Save intermediate synthesis results Save anode level netlist of the entire design into a persistent source file File name LLLI mi Cancel F oe Assignments I O Assignment Analysis Checks legality of all O assignments without full compilation E e Minimal requirements for running fe x O declaration dl Eom E a7 iP HDL port declaration Processing menu A Start gt Start I O Reserved pin Assignment Analysis A or Tasks window Pin related assignments O standard Run from Pin Planner Current stre ngth toolbar Uc Bis gg ml En En Pin location pin bank edge PCI clamping diode Toggle rate 41 8 29 2011 I O Rules Che
14. nction and stored on to the bcd time variable alues are fed out to the four 7 segment displays by using function The first four bits of bcd time correspond next four to digit2 and so on END PROCESS END Lab5 beh 3 Create another New File Create another new VHDL file Copy and paste the following code into your new vhdl file and save it in the project directory as bin_to_7seg vhd make sure the Add file to current project box is checked in the Save As window Lab 5 AVHDL Reaction Timer Reaction Timer Code library IEEE use EEE Std I 0g iG LD67 31 05 USE IEEE std logic unsigned ALL use ieee numeric std all PACKAGE bin to 7seg IS Bin to BCD takes in a 16 bit binary number and returns a 20 bit BCD representation of it This would be the equivalent of a 5 digit integer With 5 groups of 4 bits each representing 1 digit FUNCTI ON Bin to BCD bin std logic vector 15 DOWNTO 0 return std logic vector BCD to 7seg takes a 4 bit BCD value and returns a 7 bit value that represents the desired segments to turn on for a 7 segment display FUNCTI ON BCD to 7seg bcd std logic vector 3 DOWNTO 0 return std logic vector END PACKAGE BODY bin to 7seg IS cc c ee a Binary to BCD Conversion Function FUNCTI ON Bin to BCD bin std logic vector 15 DOWNTO 0 return Std Ogre vector TS variable i integer 0 variable bcd std logic vector 19 downto 0 others gt 0 variable bint
15. 1 countdown countl co 7 unt unti 1 IF countdown countl 655 SZ HD I t moa 2 zo countdown count 2 countdown count1 END IF IF countdown count2 763 THEN countdown done lt 1 own count2 1 countdown count2 0 END IF Turn green LEDS on and begin counting in milliseconds Set countdown done to low WHEN timing gt LEDG lt IF timing_counter 49999 THEN tim ng count timing count 1 tim ng counter 0 ELSE timing counter timing counter 1 END IF el apsed time lt timing count countdown done lt 0 Turn all LEDS on set timing counters to 0 N score gt LEDG lt OTHERS gt 1 LEDR lt OTHERS gt 1 J timing count OTHERS gt 0 timing counter 0 Turn all LEDs off WHEN OTHERS gt LEDG lt OTHERS gt 0 LEDR lt OTHERS gt 0 END CASE END IF END PROCESS Output Process ccc eee eee Ti me Di spl y Process e e ime value on four of the seven S This process displays th m board The functions bin to bcd e pla et segment displays on the DE2 Ab ed from the included bin to 7seg vhd SS elapsed time and bcd to 7seg are call Time Display Process PROCE 20 bit binary variable that holds 5 4 bit BCD values only 4 are used to display on the 4 7 segment displays variable bcd time std logic vector 19 DOWNTO 0 BEGIN 5 4 sed time must be converted from binary to BCD uing the
16. 5 Synthesi S settings Design Entry Synthesis Created on Wednesday May 26 2010 Simulation Based on fractal 2 Fitter settings Timing Analysis Formal Verification e Timi 5 Board uel Timing Analysis settings Analysis amp Synthesis Settings e yo SI lt 2 YHDL Input Power analysis settings En 2 aa Default Paramet SSN Analyzer settings mes Timing Analysis Settings TimeQuest Timing Analyzer Classic Timing Analyzer Settings Classic Timing Analyzer Reporting e l 8 S Assembler Design Assistant SignalTap II Logic Analyzer Logic Analyzer Interface 2 PowerPlay Power Analyzer Settings Dialog Box a Tcl set global assignment name lt assignment_name gt value 34 4 Settings fractal_150 Category General Files Libraries Operating Settings and Conditions Voltage Temperature Early Timing Estimate Incremental Compilation Physical Synthesis Optimizations EDA Tool Settings Design Entry Synthesis Simulation Timing Analysis Formal Yerification Board Level Analysis amp Synthesis Settings VHDL Input Verilog HDL Input Default Parameters Fitter Settings Timing Analysis Settings TimeQuest Timing Analyzer Classic Timing Analyzer Settings Classic Timing Analyzer Reportinc Assembler Design Assistant SignalTap II Logic Analyzer Logic Analyzer Interface PowerPlay Power Analyzer Settings SSN Analyzer Fi Use smart compilation 8 29 2011 ompilation Process Setting E
17. Sequential statements END PROCESS PROCESS BEGIN Sequential statements WAIT ON a b END PROCESS 8 29 2011 65 8 29 2011 Architectures An architecture can have PROCESS 1 multiple process statements Sequential Each process executes in S ipn parallel with other processes Order of process blocks does not matter Within a process the statements are executed sequentially Order of statements Describes the functionality of design within a process does matter Signals Sequential Statement mcc Hom rozs x Functions 1 IBRARY IEEE E USE IEEE STD LOGIC 1164 ALL IEEE STD LOGIC 1164 ALL ENTITY simp prc IS ENTITY simp IS PORT PORT a b IN STD LOGIC a b IN STD LOGIC y OUT STD LOGIC y OUT STD LOGIC gt END ENTITY simp_prc END ENTITY simp Z ARCHITECTURE logic OF simp_prc IS ARCHITECTURE logic OF simp IS SIGNAL c STD_LOGIC SIGNAL c STD_LOGIC BEGIN END ARCHITECTURE logic END PROCESS process1 process2 PROCESS c BEGIN C AND y get executed and updated in EN parallel at the end of the process within END PROCESS process2 one simulation cycle END ARCHITECTURE logic 66 LOGIC 1164 ALL ENTITY simp IS PORT a b IN STD LOGIC y OUT STD LOGIC END ENTITY simp ARCHITECTURE logic OF simp IS SIGNAL c STD LOGIC BEGIN M S we END ARCHITECTURE logic New value of c not available for y until next process execution r
18. THEN xX lt a ELSIF sel 100 THEN ys ELSIF sel 001 THEN Z lt ELSE x lt 0 ys z lt 0 END IF END PROCESS sel 0 sel 1 sel 2 A sel 0 sel 1 sel 2 B sel 0 sel 1 sel 2 C 93 8 29 2011 211X s TCGIVC Latches Removed eparate IF statements and close PROCESS sel a b c PROCESS sel a b c BEGIN BEGIN IF sel O10 THEN x lt Q X lt a 0 ELSE a LOGIC z lt 0 y se x lt O sel 2 IF sel 010 THEN END IF A KEAR IF sel 1007 THEN END IF Eu lt b S LOGIC IF sel 100 THEN 0 sel 2 Aq Un y lt B END IF END IF IF sel 001 THEN IF sel 001 THEN sel 0 Ws AI Z lt C sel 1 s C END PROCESS z lt 0 END IF END PROCESS Case Statements Case statements usually synthesize more efficiently when mutual exclusivity exists Define outputs for all cases Undefined outputs for any given case generate latches VHDL already requires all case conditions be covered Use WHEN OTHERS clause to close undefined cases if any remain 94 8 29 2011 ase Statement Recommendations Initialize all case outputs or ensure outputs assigned in each case Assign initialized or default values to don t cares X for further optimization if logic allows nwanted Latches Case Statements Conditions where output is undetermined outpu
19. Timing 3 Logic Options All A i 7 F sass o M Check All e E H PLL T Comb cell Uncheck All Register cell T Embedded multiplier block Delete All Clack control black Clock delay control black t 3 Double click lt lt new gt gt in the To column and select input0 0 Double click the adjacent cell under Location and type PIN_AF14 Continue to assign the pins as seen in the table below To Location DE2 Board Description 6 ilmputi 1 PINNI 2 SW10 8 inputi PINP2 SW12 9 inpu2 0 PINUS 2 SW14 Note A complete list of pin assignments for the DE2 Development Board can be found here http www terasic com tw attachment archive 30 DE2 Pin Table pd 4 Save the pin assignments by selecting File gt Save from the Menu Bar or by clicking the Save button amp on the toolbar 5 View the Pin Assignments Select Assignments gt Pin Planner to open the Pin Planner window Here you can view which pins have been assigned 1 10 6 Select View gt Pin Legend Window to display the pin legend Close the Pin Planner 7 Export Pin Assignments With the Assignment Editor selected select Assignments gt Export Assignments to create a qsf file containing your pin assignments This qsf file can be used for other projects by selecting Assignments gt Import Assignments when assigning pins Task 4 Using the TimeQuest Timing Analyzer
20. a WHEN 00 BEGIN b WHEN 01 c WHEN 10 d WHEN OTHERS END PROCESS 69 Infinite loop Loops forever While loop Loops until conditional test is false For loop Loops for certain number of Iterations 8 29 2011 Sequential LOOPS Infinite Loop While Loop Note Iteration identifier not required WHILE condition LOOP to be previously declared Additional loop commands each requires loop label NEXT NEXT WHEN Skips to next loop iteration EXIT EXIT WHEN Cancels loop execution Sequential statements END LOOP For Loop FOR lt identifier gt IN range LOOP Sequential statements END LOOP Statements Pauses execution of process until WAIT statement is satisfied Types WAIT ON signal Pauses until signal event occurs WAIT ONa b WAIT UNTIL boolean expression Pauses until boolean expression is true WAIT UNTIL int lt 100 WAIT FOR time expression Pauses until time specified by expression has elapsed WAIT FOR 20 ns Combined WAIT WAIT UNTIL a 1 FORS us Wait statement usage limited in synthesis 140 70 8 29 2011 Jsing WAIT Statements stim PROCESS VARIABLE error BOOLEAN Pause execution of the process WAIT UNTIL clk 0 a lt OTHERS gt 0 b lt OTHERS gt 0 WAIT FOR 40 NS IF sum 0 THEN error TRUE Pause execution of the process END IF unt
21. sync lt 0 counter lt 0 state change lt 0 else sync lt NOT push a if sync 0 the Button not pressed counter lt 0 state change lt 0 elsif sample 1 then Button if counter zPULSE COUNT MAX then state change lt 1 pressed else counter lt counter 1 end if end if end Ti 5 2 end If end process we eee Timer State Machine Process Sets the next state for the state machine The next desired state is stored on the next state signal which is used in the State Transistions process to change the current state Timer State Machine PROCESS cik BEGI N NeXt State lt CUrreEnt state CASE current state IS If the state change flag is set and the push button is pushed then the next desired state is the countdown state WHEN idle gt IF state change 1 AND push button 1 THEN next state lt countdown END IF When the countdown done flag is high the next desired state is the timing state WHEN countdown gt IF countdown done 1 THEN next state timing END IF If the state change flag is high and the push button is pushed then the next desired state is the score state WHEN timing gt IF state change 1 AND push button 1 THEN next State lt score END IF Stay in score state Pressing reset will override this WHEN score gt exl state lt score In case of entering any undefined states next desir
22. y F OUT st END Gate _XOR2 ARCHITECTURE Gate XOR2 beh OF Gate XOR2 IS F lt x XOR y END PROCESS END Gate XOR2 beh This is a basic XOR Gate written using Behavioral style VHDL Similar to the AND gate we created the XOR gate has two inputs x and y which are XORed together and the result of the logic operation is returned on F The Process sensitivity list includes x and y so whenever either of the two change in value the process will execute and generate a new result 5 Create another new VHDL file following the directions in step 1 of task 2 2 7 6 Copy and paste the following code into your new VHDL file then save it by selecting File gt Save Name the file Or3 and click Save in the Save As dialog box This is a three input OR Gate written using Behavioral style VHDL Lab 2 Introduction to VHDL Three Input OR Gate Behavioral VHDL Code LIBRARY eee USE ieee std logic _ 1164 ALL ENTITY Gate OR3 IS PORT x td td td st F END Gate OR3 ARCHITECTURE Gate OR3 beh OF Gate OR3 IS Z F lt x OR y OR z END PROCESS END Gate OR3 beh This is a three input OR Gate written using Behavioral style VHDL Similar to the AND gate and XOR gatewe created the OR gate has three inputs x y and z which are ORed together and the result of the logic operation is returned on F The Process sensitivity list includes x y and z so whenever one changes in value the process will execute and gener
23. 1 Select Assignments gt Settings Click the Timing Analysis Settings and verify that Use TimeQuest Timing Analyzer during compilation is selected for Timing analysis processing Click OK Early Timing Estimate Timing analysis processing Incremental Compilation t Use Timeluest Timing Analyzer during compilation Physical Synthesis Optimizations EDA Tool Settings Analysis amp Synthesis Settings Fitter Settings EXE Timing Analisis Settings Use Classic Timing Analyzer during compilation 2 Synthesize the Design Select the Start Analysis amp Synthesis button from the Toolbar Click OK to continue when the analysis and synthesis is complete 3 Open the TimeQuest Timing Analzyer Select Tools gt TimeQuest Timing Analyzer or use the Toolbar button a Click No when the dialog box pops up asking if you would like to generate an SDC file from the Quartus Settings File 1 11 4 Create a Timing Netlist In the TimeQuest Timing Analyzer window select Netlist gt Create Timing Netlist Set the Input netlist type to Post map and click OK Create Timing Netlist Input netlist Delay model C Post fit f Slow corner Speed grade f Post map Fast cormer if Zero IC delays Tel command create tiring netlist post map model slow zero 1c del Cancel Help 5 Select Constraints gt Create Clock from the Menu Bar 1 12 Type clk for the Clock name and a Period of 20 ns Double Click
24. 1960s 1970s 10 1 000 1980s 1 000 100 000 1990s Millions 2000s Billions 1970s IC behavior documented using combination of schematics diagrams and natural language e g English 1980s Documentation was hundreds of pages for large ICs e Imprecise Need for better documentation dware description languages HDLs Machine readable textual languages for describing hardware Schematic documentation in one HDL description became the precise concise IC documentation Simulator is a tool that automatically generates outputs values of a hardware module for a given sequence of input values VHDL originally defined for simulation of ICs e First IC was designed Then IC was described in HDL for documentation Transistors per IC millio The system has four states When in state Off the system outputs 0 and stays in state Off until the input becomes 1 In that case the system enters state Onl followed by On2 and then On3 in which the system outputs 1 The system then returns to state Off DLs for Simulation CombLogic PROCESS Currstate b BEGIN CASE Currstate IS WHEN S Off gt x lt 0 IF b 0 THEN Nextstate S Off ELSE Nextstate lt S Onl END IF WHEN S On1 gt x lt Ir Nextstate lt S_On2 WHEN S_On2 gt x lt 1 Nextstate lt S_On3 Si WHEN S_On3 gt z lt VI Nextstate lt S_Off END CASE END PROCESS mulation 1020304
25. AF mem 64x8 b 50 lt 11110000 END ARCHITECTURE logic 74 8 29 2011 Recall Structural Modeling Functionality and structure of the circuit Call out the specific hardware lower level components Higher level component Output 7 Lower Level Component2 Lower Level Component1 Outputn Design Hierarchically Multiple Design Files VHDL hierarchical design requires component declarations and component instantiations Top vel BNTITY ARCHITECTURE S OT Component mid a Component mid b Mid_b Vhd ENTI TY ARCHITECTURE mic o Component bottom a Component bottom_b 75 8 29 2011 Declaration and Instantiation Component declaration used to declare the port types and the data types of the ports for a lower level design COMPONENT lt lower level_design_name gt PORT port name port type data type Port name port type data type E END COMPONENT Component instantiation used to map the ports of a lower level design to that of the current level design Instance name lower level design name PORT MAP lower level port name gt current level port name lower level port name gt current level port name ical Circuits Using Entities as Entity can be used as component in a new entity Com pon ents AND entity used as component in compcircuit entity Can continue compcircuit entity can
26. BIT ENTITY y Z OUT BIT ARCHITECTURE END ENTITY cmpl_sig ARCHITECTURE logic OF cmpl sig IS BEGIN simple signal assignment x lt a AND NOT sel OR b AND sel conditional signal assignment y lt a WHEN sel 0 ELSE b selected signal assignment WITH sel SELECT z lt a WHEN 0 b WHEN 1 O WHEN OTHERS END ARCHITECTURE logic Libraries ALIBRARY is a directory that contains a package or a collection of packages Two types of libraries Working library Current project directory Resource libraries STANDARD package EEE developed packages Altera component packages Any LIBRARY of design units that is referenced in a design 54 8 29 2011 Example LIBRARY lt name gt lt name gt Name is symbolic and defined by ENTITY cmpl sig IS PORT a b sel IN STD LO
27. C5 c5 c5 r3 c5 c5 I CO C5 C5 r3 r3 c5 c5 c5 c5 c5 I CO C5 C5 C5 C5 r3 c5 c5 r3 c L L L 1 L L L L L L L gt lt WO COO 1 C Un CO NEF ODO L L L L LI L L LI L L L END PACKAGE BODY 5 6 4 About the Code The code in Lab5 vhd is broken up into a variety of processes SampleGen and Debounce are processes used together to debounce the input signal from the momentary push button KEY3 on the development board The hardware samples the push button at a rate of 2 kHz and after 20 consecutive low readings in this case the push button switches are active low the hardware considers the button to have been pressed The program uses a finite state machine to represent the various states used These states are idle countdown timing and score Idle is when the hardware is waiting for the user to initiate the game Countdown is a timed countdown sequence which adds a delay before the millisecond timer starts counting Timing is when the millisecond timer starts counting how long it takes the user to push the button to stop the counting Score freezes the display to show the user s reaction time The process Timer State Machine is what defines the requirements to change from one state to the next This process stores the next desired state onto the next state signal which is then set as the current state by the State Transitions process The Output Process contains everything that happens within each of the individual st
28. Flow Summary Eee Flow Settings Flow Non Default Global Setting PERS Flow Elapsed Time PERS Flow 05 Summary 3 Flows Log ter TimeQuest Timing Analyzer 65 summary PERS Parallel Compilation PERS clocks eb Slow Mode SES Fmax Summary 6S Setup Summary PER Hold Summary Em Model Fmax w Model Fmax Summary Compilation Report Slow a Clock TClock 1121 Mame TEST 48 hints MHz 420 17 MHz CLE limit due to minimum mmusmupuuusaumanumanmumanasananan nnunsuuuuuuuuuuxuumuAREHRHAHEHREUSHRERRHRESRAESSUHAESARRRS RHAREHREARREREESREHREEREREAESEREESSHAESARRREREARRRREARREE 4 In the Compilation Report click on Analysis amp Synthesis and then expand the subheading State Machines This shows the encoding type used by the compiler to identify the different states The encoding type is currently User Encoded meaning that the VHDL code specifies the encoding used Alternately the compiler can be configured to use a specific encoding type The VHDL code currently is using a Sequential Encoding scheme to identify the states abe Lab3 vhd EB Compilation Report BE Legal Notice FF Flow Summary PERS Flow Settings PES Flow Non Default Global Settings BEES Flow Elapsed Time EEE Flow OS Summary amp h Flow Log Em Analysis amp Synthesis eh summary amp h Settings SEA Parallel Compilation BEES Source Files Read SEa Resource Usage Summary g Resource Utilization by Entity hy State M
29. I x S lt WAIT END PROCESS END TBarch IBRARY ieee SE ieee std_logic_1164 ALL ENTITY Testbench IS END Testbench ARCHITECTURE TBarch OF Testbench IS COMPONENT And2 IS PORT x IN std_logic y IN std_logic F OUT std_logic END COMPONENT SIGNAL x_s y_s F_s std_logic BEGIN CompToTest And2 PORT MAP x_s y_s F_s PROCESS BEGIN Test all possible input combinations yas lt Ole xX S lt Oe WAIT FOR 10 ns vV G s oa KS lt WAIT FOR 10 ns y s lt 1 x Ss lt WAIT FOR 10 ns Vesa lt ele xs c WAIT END PROCESS END TBarch 19 Component instantiation statement CompToTest d2 PORT MAP x S y S f s Note order same as in component declaration positional IBRARY ieee SE ieee std logic 1164 ALL ENTITY Testbench IS END Testbench ARCHITECTURE TBarch OF Testbench IS COMPONENT And2 IS PORT x IN std logic y IN std logic F OUT std logic END COMPONENT SIGNAL x s y S F s std logic Connects maps component BEGIN ports to signals Type of component From earlier component declarations Name of new instance Must be distinct Combinational Circuits Component Instantiations Pieee ieee std logic 1164 ALL ENTITY And2 IS PORT x IN std logic y IN std logic F OUT std logic END And2 ARCHITECTURE And2 beh OF And2 IS BEGIN PROCESS x y BEGIN F x AND y END PROCESS END And2 beh Do co cocoa 7
30. Il Software Design Series Foundation Learning Objectives Circle One You learned to Strongly Strongly Agree Agree Neutral Disagree Disagree Create a new Quartus II project 5 4 3 2 1 Create design components using MegaWizard manager 5 4 3 2 1 Compile a design and view results 5 4 3 2 1 Use settings and assignments to control results 5 4 3 2 1 Make pin assignments and evaluate 5 4 3 2 1 Use the TimeQuest timing analyzer 5 4 3 2 1 Additional comments regarding the teaching of this material National Science Foundation Advanced Technological Education VHDL and FPGA design workshop Post Course Evaluation Summer 201 1 Please take a few minutes to answer the following questions Your responses will be used to improve this course for future students Thank you in advance for your participation Mastery of Main Course Objectives Circle One Complete No Mastery Mastery Ability to implement basic constructs of VHDL 5 4 3 2 1 Ability to implement modeling structures of VHDL 5 4 3 2 1 Ability to use software tools to check the code for correctness and correct errors 5 4 3 2 1 Additional content topics you would have liked to have had covered Quality of Instruction Circle One Strongly Strongly Agree Agree Neutral Disagree Disagree The instruction was clearly presented 5 4 3 2 1 Any questions asked were properly answered 5 4 3 2 1 The materials provided helped me to learn 5 4 3 2 1 The pace of the c
31. Memory Initialization File Vernfication Debugging Files n Sustem Sources and Probes File Logic Analyzer Interface File Signall ap Il Logic Analyzer File Vector Waveform File Other Files AHDL Include File Black Symbol File Chain Description File Synopsys Design Constraints File Text File ad Cancel 2 5 2 Copy and paste the following code into your new VHDL file then save it by selectingFile gt Save Name the file And2 and click Save in the Save As dialog box Lab 2 Introduction to VHDL Two Input AND Gate Behavioral VHDL Code LIBRARY eee USE ieee std log 1164 ALL ENTITY Gate And2 IS FORT XS F lt x AND y END PROCESS END Gate And2 beh This is a basic two input AND Gate written using Behavioral style VHDL The AND gate has two inputs x and y which are ANDed together and the result of the logic operation is returned on F The Process sensitivity list includes x and y so whenever either of the two change in value the process will execute and generate a new result 3 Create another new VHDL file following the directions in step 1 of task 2 4 Copy and paste the following code into your new VHDL file then save it by selecting File gt Save Name the file Xor2 and click Save in the Save As dialog box Lab 2 Introduction to VHDL Two Input XOR Gate Behavioral VHDL Code LIBRARY eee USE T1666 Std ogL C 1164 ALLE ENTITY Gate XOR2 IS PORT x IN std
32. Minor update to language VHDL 2008 Second major update to language Check tool for support Course will cover constructs supported by the Quartus Il software version 9 1 94 4f 8 29 2011 HDLs for Design and Synthesis DLs became increasingly used for designing ICs using top down design process Design Converting a higher level description into a lower level one Describe circuit in HDL simulate Physical design tools automatically convert to low level IC design Describe behavior in HDL simulate Synthesis 1020304050 60 708090100 10 e e g Describe addition as A B C rather oso than as circuit of hundreds of logic gates Compact description designers get function right first Design circuit Manually or Using synthesis tools which automatically convert HDL behavior to HDL circuit Simulate circuit should match Al HDLs for DLs for synthesis is growing Synthesis Circuits are more complex Synthesis tools are maturing But HDLs originally defined for simulation General language Many constructs not suitable for synthesis e g wait statements pointers recursive function calls Behavior description may simulate but not synthesize or may synthesize to incorrect or inefficient circuit e Not necessarily synthesis tool s fault 48 ALL HDLs for HDL language Synthesis General and complex many uses But use for synthesizing circuits
33. Setup U5B Blaster USB 0 Mode JTAG Progress 0 Enable real time ISP to allow background programming For MA I devices as ja e mnm Tem TES EF2C3BFB7Z DO333572 FFFFFFFF m Auto Detect For Help press Fi Then click the Start button to program the DE2 board When the progress bar reaches 100 programming is complete Task 4 Play the Game 1 The game is started by pressing KEY3 on the development board This causes the hardware to change states from idle to countdown turns on the first eight red LEDs and begins the countdown to when the timer starts The countdown is not displayed in order to maintain the element of surprise 2 When the countdown completes the hardware changes to the timer state and begins incrementing the millisecond counter the red LEDs are shut off and the first eight green LEDs are turned on The user must press KEY3 on the development board as soon as possible after the green LEDs light in order to obtain the quickest reaction time 3 When the user presses KEY3 the state is changed to the score state where the millisecond display is frozen in order to display the user s reaction time 4 Pressing the reset button KEY1 at this point will return the hardware to the idle state where the game can be played again 5 9 National Science Foundation Advanced Technological Education VHDL and FPGA design workshop Pre Course Evaluation Summer 2011 Please take a few minutes to ans
34. User Encoded e Johnson Undefined States Noise and spurious events in hardware can cause state machines to enter undefined states If state machines do not consider undefined states it can cause mysterious lock ups in hardware Good engineering practice is to consider these states To account for undefined states Explicitly code for them manual Use safe synthesis constraint automatic 103 8 29 2011 Cat w wash drain current state next state state type PROCESS current state door closed full heat demand done empty BEGIN next state current state CASE current state is WHEN idle gt IF door closed 1 THEN next state lt END IF WHEN gt IF full 1 THEN next state lt heat w END IF WHEN heat w gt IF heat demand 0 THEN next state lt wash PEDIR This code does not consider WHEN wash gt IF heat demand 1 THEN next state lt heat w undefined states ELSIF done 1 THEN next state lt drain The when others statement END IF only considers other WHEN drain gt IF empty 1 THEN next state lt idle enumerated states END IF The states 101 110 amp WHEN others gt 111 are not considered next_state lt idle Heat_demand 0 END CASE END PROCESS Creating Safe State Machines WHEN OTHERS clause does not make state machines safe Once state machine is re
35. Viewer to open the RTL Viewer This displays a schematic diagram of the circuit design Take note of the number of multipliers used x reu U hu uz t j xr 0 A E CLK NND Multa result2 73 0 requ E Mresult2 73 u resulti 23 0 req vi OLD U ua E T D a E esultt 23 0 E xs k Mibi dn MULTIP LIEF ENA CLP z 7 0 DD w T 0 p 5 Goto Lines 21 and 22 in the VHDL code and add parenthesis aroundx reg y reg in each line This optimizes resource sharing by not having to do the same operation multiple times 14 Mult Process PROCESS clk 15 BEGIN 16 GIF RISING EDGE CIK THEN 1 w reg lt w 15 x reg lt x 19 y req lt v at z reg lt zr al resulti lt w reg xX reg v redi resulte z ix reg y reg z reg 23 temp w d Egewp z reg s E reu ao tENb Ey reg lt E rei M y reg 26 re sulti s temp w reg temp xy reg aoe results lt temp xy reg temp Fed ao END IF 29 END PROCESS 3 3 6 Save the changes to Lab3a vhd then compile the design again and view the results in the Compilation Report Ignore any warnings at this time This time it can be seen that the number of Embedded Multiplier 9 bit elements has been reduced by one this is due to the resource sharing technique we used Compilation Report Flow 5 3 4 abe Lab3a vhd 3 Compilation Report amp E Legal Notice EP Flow Summary
36. amp 1800 SystemVerilog supported Use Quartus ll integrated synthesis to synthesize View supported commands in built in help 2f Find highlight matching delimiters 2 Text EN File Edit Project EB d 5 y EHE 58 59 60 61 62 63 64 65 66 69 C altera_trn Quartus_ Window AAAM US HDlarchitecture rtl of fractal is Elcomponent asyne_receiver Elrort clk rxd in std logic rxd data ready out std logic rxd data out std logic vector 7 downto end component Processing fols aes ab El component async transmitter BHlport clk txd start in std logic end component Eleomponent myfifo PORT E STD_LOGIC STD LOGIC VECTOR 17 STD_LOGIC STD_LOGIc STD_LOGIC Collapse expand functions end component Design Files Bookmarks on off jump to Z cvare Design Series Veri 2 8 29 2011 g Features Insert Template Edit menu A HP usta accusat iman Ters plane Language templates T2 Full Diay RAM and FUHR Lage Port FU Sapte Deal Peet RAH bee Sample Dua Pest RAM pira el Ta Drusi Prog HORS nne zh True Dra Port Foi jc cles are Fort Rob Dus Port FOH Shit llegeien does cnintar k enable cunt un react Preview window edit before inserting amp save as user template dm M chars En hijal Caris Save User Templale Ton madi hingat 15 d Are Laingia Ace pou ee i e bengis Fpa aai l tr Doa chai vou Cn dee
37. be used as component in another entity And soon Hierarchy powerful mechanism for managing complexity E ad CompCircuit Ed M CompCircuit 76 Dit 2x1 mux example 2x1 mux circuit from earlier Now consider register with control inputs such as load or shift Could describe structurally e Four flip flops four muxes and some combinational logic to convert control inputs to mux select inputs We ll describe behaviorally Operation Maintain present value Shift left Shift right Shift right Shr has priority over Shl Parallel load Parallel load Id has priority Parallel load Id has priority Parallel load Id has priority OO OO OO gt O O 8 29 2011 ENTITY Mux2 IS PORT il i0 IN std_logic s0 IN std logic d OUT std logic END Mux2 ARCHITECTURE Struct OF Mux2 IS COMPONENT And2 IS PORT x y IN std logic F OUT std logic END COMPONENT COMPONENT Or2 IS PORT x y IN std logic F OUT std logic END COMPONENT COMPONENT Inv IS PORT x IN std logic F OUT std logic END COMPONENT SIGNAL nl n2 n3 std logic BEGIN Inv 1 And2 1 And2 2 Or2 1 END Struct Inv PORT MAP sO And2 PORT MAP i0 And2 PORT MAP il Or2 PORT MAP n2 nl nl n2 s0 n3 n3 d Multifu nction Register Be 2 11 havior Operation Maintain value Shit left Shift right Parallel load Compact register operation table clea
38. code more readable reusable Two types Functions Synthesize to combinatorial logic Procedures Cansynthesize to combinatorial or sequential logic Signal assignments in procedures called from clocked processes generate registers Maytest for clock edges May not be supported by all synthesis tools Must not contain WAIT statements e Each call generates a separate block of logic Nologic sharing Implement manual resource sharing if possible discussed later 98 ymmon cause of instability Behavior of loop depends on the relative propagation delays through logic Propagation delays can change Simulation tools may not match hardware behavior Bedback loops should include registers Logic 8 29 2011 PROCESS clk clrn BEGIN IF clrn 0 THEN q lt 0 ELSIF rising edge clk THEN q lt d END IF END PROCESS x a clrn lt ctrll XOR ctrl2 AND q PROCESS clk clrn BEGIN IF clrn 0 THEN q lt 0 ELSIF rising edge clk el Se i END IF END PROCESS PROCESS clk BEGIN IF rising edge clk THEN clrn lt ctrl1 XOR ctrl2 AND q END IF END PROCESS 99 8 29 2011 Enumerated data type is used to define the different states in the state machine Using constants for states may not be recognized as state machine TYPE state_type IS idle fill heat_w wash drain One or two signals assigned to the name of the state variable SIGNAL cur
39. d 4 lt Input gt PIN device edge d 5 Input PIN B d 6 Input PIN B18 0 Wy L N ON EN V 0 d 7 lt input PIN_B19 d 3 lt Input gt IDBANK 3 d 2 lt Input gt IDBANK 3 ANA gt On i N UAG lati lt input IOBANK 3 1 d 0 Input IOBANK_3 Pin number PIN_B16 o L LL Nn 0 0 0 0 OOD rn 3 Koc ODIO 9 AO O9 p p 1 0 standard 3 3Y LVTTL default wee sik ACC A oL o Co Co c CC ACC n e neg Properties Name Value v Edit gt lt d Filter Pins all 170 Bank 3 Direction Location 1 0 Bank Pins assigned General Function Column 1 0 Input PIN B19 3 Pins unassigned n Function EM 1T L ipu PIN B18 a Input PIN B17 VREE TENO m Input PIN B16 Input IOBANK 3 Input IOBANK 3 Input IOBAMK 3 Input IOBANK_3 ji Filter nodes displayed 39 8 29 2011 Assigning Pin Locations Using Pin Planner 3 Select available locations from list of pins color coded by I O bank x Named 1 Edit XJ Filter Pins all Node Name Direction yn_out 6 vn out 5 yn out 4 vn out 3 vn out 2 yn out 1 vn out 0 lt lt new node Location I O Bank I O Bank 8 I O Bank 8 I O Bank 7 I O Bank 7 I O Bank 7 I O Bank 10 I O Bank 8 Column I O Column I O Column I O Column I O Column I O Column I O Column Io Column I O
40. ict Pisoni les Few Reales Ban TIE D specific design entities Assignment Editor 35 8 29 2011 Michiaa itter Settings Standard Fit Fitter Effort Longest compile time Eor Fast Fit Possibly lesser performance Faster compile Specify options for Fitting Auto Fit Compile stops after meeting timing Optimize hold timing All Paths Conserves CPU time C Optimize multi corner timing Will mimic standard fit for hard to fit designs Default for new designs Timing driven compilation PowerPlay power optimization Off Fitter effort Standard Fit highest effort One fitting attempt East Fit up to 50 Faster compilation may reduce fmax Auto Fit reduce Fitter effort after meeting timing requirements Default Parameters Desired worst case slack margin 0 ns 7 Timing Analysis Settings TimeQuest Timing Analyzer Classic Timing Analyzer Settings C Limit to one fitting attempt Classic Timing Analyzer Reportinc Assembler Seed 1 Design Assistant SignalTap II Logic Analyzer Logic Analyzer Interface PowerPlay Power Analyzer Settings SSN Analyzer Tcl set global assignment name FITTER EFFORT lt Effort Levels O Planning Need I O standards increasing in complexity FPGA CPLD I O structure increasing in complexity Results in increased pin placement guidelines PCB development performed simultaneously with FPG
41. io oe Quartus Version 3 1 Build 222 10 21 2008 SJ Full version Flow Non DeFaull Global Settings ar H M Lab3 EEE Flow Elapsed Time giu xu s ET Flows Si mmary Top level Entity M ame Labia SE Flow Log Eus Cyclone Il 9 Analysis amp Synthesis Device EP2C ISFE 2C AL Fitter Timing Models Final eh Assembler Met timing requirements Tes 39 Timing Analyzer Total lagic elements 1r 33215 1x Total combinational Functions 133 216 lt 1 Dedicated logic registers 167 S3 216 214 Total registers 16 Total ping Bl 4r5 17 Total virtual ping Il Total memory bits 0 483 840 0 Embedded Multiplier 3 bit elements 5 70 7 XJ Total PLL U 4 0 x The Compilation Report indicates that many more logic elements and registers are being used in the design now 11 Open the Timing Analyzer Summary to see that the clock speed has increased due to the pipelining abe Lab3a vad Compilation Report Timing Timing Analyzer Summary R equired Actual ie de her 2X Compilation Report 8 E Legal Notice FF Flow Summary SEE Flow Settings 11 worstoasetsu na Na None Sons PES Flow Non Default Global Settings Worst case too M Mone 10 345 ns ES Flow Elapsed Time Worst case th N None 2530 5 PERS Flow 05 Summary S EB Flow Log Analysis amp Synthesis Fitter cy Assembler eig Timing 4nalyzer BERN Summary hE Settings Clock setup LLE MN Mone 213 04 MHz Total number af failed paths
42. is greatly oT LLL restricted patos HDL behavi Simulate Rst_s E m ehavior gt Synthesis tool understands sensitivity lists if statements Synthesis tool may not understand A wait statements while loops even if the HDL simulates correctly f the circuit is bad don t blame the synthesis tool We will emphasize use of VHDL for design and synthesis Only the functionality of the circuit no structure E No specific hardware intent l M output f outputn He a Uebel IF shift_left THEN FOR j IN high DOWNTO low LOOP shft j shft j 1 END LOOP output lt shft AFTER 5ns Left bit shifter Behavioral Modeling 8 29 2011 49 8 29 2011 Michigantech unctionality and structure of the circuit B Call out the specific hardware Higher level component input f output 7 Lower level Component Lower level ComponentO outputn Structural Modeling VHDL Basics O Sets of constructs Simulation Synthesis amp simulation The VHDL language is made up of reserved keywords The language is for the most part not CASE sensitive VHDL statements are terminated with a VHDL is white space insensitive Comment support End of line EOL comment everything from symbol to EOL is commented Delimited comment everything between symbols is commented Supported in VHDL 2008 only 50 8 29 2011 VHDL Design Units ENTITY us
43. selected by the Fitter Specific device selected in Available devices list U Hardcopy compatible only Other la Ken n a Device and Pin Options Available devices Name Device and Pin Options fractal_150 EP3SESOF484C2 Advanced i EP3SESOF484C3 Advanced Category EP3SES50F484C4 Advanced f EP35E50F484C4L Advanced l keira i i um EP3SESOF48413 Advanced gramming Files Specify general device options These options are not dependent on the Unused Pins configuration scheme Dual Purpose Pins Capacitive Loading Options Board Trace Model I O Timing Auto restart configuration after error d dcl eld t C Release clears before tri states in Placemen 0 migration devices selected Error Detection CRC J Enable user supplied start up clock CLKUSR C Enable device wide reset DEV CLRn IC Enable device wide output enable DEV OE Enable INIT DONE output Migration compatibility 4 Settings fractal_150 Category Change settings Top level entity Files Libraries You can change the top level entity For the desic e Ad d remove fi les Tode 7 and Conditions revision For each entity in order to maintain settii b Li braries Temperature Top level entity fractal Compilation Process Settings s Compiler setti ngs Early Timing Estimate Recently selected top level entities Fractal Incremental Compilation EDA tool setti ngs H Pelias des Optimizations Description
44. single value Disadvantages vs signals Must be assigned to signal before process ends Do not represent physical hardware unless equated with signal Must be handled with care Requires fully understand assigning values to variables and signals in same process and how dataflow is effected 8 29 2011 96 8 29 2011 ariables amp Latches Recommendations Assign an initial value or signal to a variable unless feedback is desired If a variable is not assigned an initial value or signal in a combinatorial process a latch will be generated This could cause your design to not function as intended Variable Uninitialized ITECTURE logic OF cmb_vari IS BEGIN PROCESS iO il a VARIABLE val BAUER NUR Variable used without BEGIN on IF a 0 THEN initialization val val ELSE val val 1 END IF CASE val IS case val WHEN 0 gt 2 q lt 10 WHEN OTHERS gt q lt il END CASE END PROCESS END ARCHITECTURE logic 97 8 29 2011 Assign Initial Value to Variable SAITECTURE logic OF cmb vari IS BEGIN PROCESS i0 il a VARIABLE val INTEGER RANGE O TO 1 BEGIN val 0 IF a 0 THEN val val ELSE val val 1 END IF Assign initial value or signal to variable case val 3 CASE val IS WHEN 0 gt q lt 10 WHEN OTHERS gt q lt il END CASE END PROCESS END ARCHITECTURE logic Synthesizable Subprograms Make
45. v Include subentities Selected Nodes Cancel 2 11 Name Assignments Eros Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Unassigned Inaszsinnied Pers Input Group Input Input Input Input Output Input Output Gro BIF ra for us to enter values and interpret the results Insert Node or Bus Pee Type Multiple Items Cancel Value type 3 9 Level Node Finder jJ Radix Unsigned Decimal M ultiple ltem Multiple Items Mame Bus width Start index Display gray code count as binary count en Unassigned Unassigned Unassigned ae Group Input Group Input Output Gro In the Insert Node or Bus window change Radix to Unsigned Decimal This will make it easier 5 SelectEdit gt End Time to open the End Time window Change the end time to 500 ns This is how long the simulated circuit will operate for Click OK to exit the End Time window End Time Time a ns Default extension options Extension value Last clock pattern End time extension per signal SignalName Direction Made Extension value E A Input Unsigned Decimal Default extension value EB Input Unsigned Decimal Default extension value Sel Input Unsigned Decimal Default extension value Ei Sum Output Unsigned Decimal Default extens
46. warnings at this time 1 16 Task 5 Program the DE2 Development Board 1 Onthe Altera DE2 Development board plug the USB Cable into the USB Blaster Port Plug the other end ofthe USB Cable into the computer Plug the 9v power supply into the 9V DC Power Supply Connector on the DE2 board and plug the other end into a 120v wall socket Press the Power ON OFF Switch to power on the DE2 board Make sure that the RUN PROG Switch for JTAG AS Modes is in the RUN position USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGAVideo 10 100M Port Port Port in in Out In Port Pot RS 232 Port 9v DC Power 4 Supply Connector i i l t l 27 MHz Oscillator u alia ul WI d xr HA a E il re V BEEE ja 9 ef von i iiS 24 bit Audio Codec em P5 2 Keyboard Mouse Port Power ON OFF Switch r Nes amp s rm isinna 1j Ray ser Lir VGA 10 bit DAC USB Host Slave Controller TUBE TREE Ethernet 10 100M Controller Expansion Header 2 JP2 Altera USB Blaster Controller Chipset Expansion Header 1 JP1 Altera EPCS16 Configuration Device o o MEME a m rem Altera Cyclone II FPGA RUN PROG Switch for JTAG AS Modes dJ 3 5 16x2 LCD Module z E m 4 us sp Card Slot 7 Segment Displays ole gl GE Beas pies zyn 3 8 Green LEDs 18 Red LEDs U 5 5 5 SE amm 2 i NW Ran IrDA Transceiver nl Velalalalelaleiala zl a d uil Wa SMA Extemal Cloc
47. window Click the Simulator Settings heading and set Simulation Mode to Functional Simulation input should be the name of your vwf file Lab2 vwf If not click the ellipses and select Lab2 vwf Click OK to save the changes and close the Settings window Settings Lab2 Eal Category General Simulator Settings Files Libraries Select simulation options 5 Device Operating Settings and Conditions 3 Compilation Process Settings es ss I Ao _ Early Timing Estimate Simulation input Add Multiple Files gt Incremental Compilation o Physical Synthesis Optimizations Simulation period EDA Tool Settings Simulation made aeea f Run simulation until all vector stimuli are used m Analysis amp Synthesis Settings Fitter Settings C End simulation at Timing Analysis Settings Assembler Glitch filtering options ato 0 Design Assistant Signall ap IIl Logic Analyzer More Settings Le Logic Analyzer Interface EE Simulator Settings Simulation Yertication Simulation Output Files PowerPlay Power Analyzer Settings SSN Analyzer Description Specifies the type of simulation to perform for the current Simulation focus 8 Click the Start Compilation button on the Menu bar to compile the design Ignore any warnings generated 9 Select Processing gt Generate Functional Simulation Netlist and click OK when it has completed 10 Run th
48. x ala r Pin Check All E BK PLL T Comb cell Uncheck All Register cell m Clack control black Clock delay control black Embedded multiplier block Delete All 2 15 3 Double click lt lt new gt gt in the To column and select or type A O Double click the adjacent cell under Location and type PIN_A13 For a shortcut you can simply type A13 and the Assignment Editor will find PIN_A13 for you Continue to assign the pins as seen in the table below To Location DE2 Board Description PIN_A13 PIN_N1 SW10 gt gt gt SS used Z U _ m me 6 UJ Ug ES 8 B 3 PINV2 sw _ 9 Sdl J PINND5 sw Sum 3 Note A complete list of pin assignments for the DE2 Development Board can be found here http www terasic com tw attachment archive 30 DE2 Pin Table pd 4 Save the pin assignments by selecting File gt Save from the Menu Bar or by clicking the Save button amp on the toolbar 5 Plugin and power on the DE2 board Make sure that the RUN PROG Switch for JTAG AS Modes is in the RUN position 2 16 6 2 17 In the Quartus II window click the Programmer button on the Toolbar to open the Programmer window a The Hardware Setup must be USB Blaster USB 0 If not click the Hardware Setup button and select USB Blaster USB 0 from the drop down menu for Currently selected hardware Mode should be set to JTAG Make sure tha
49. y IN std logic F OUT std logic OUT std logic F OUT std logic END Inv END Or2 ENTITY Declares a new type of component Named And in this example PORT List of inputs and outputs of entity x IN std logic gt port x is an input port of type std logic std logic short for standard logic a logical bit type versus say an integer type which can be 0 or 1 more later un Ports in list separated by semicolons 57 8 29 2011 Entities and Ports gt gt ENTITY And2 IS ENTITY Or2 IS ENTITY Inv IS PORT x IN std_logic PORT x IN std_logic PORT x IN std_logic y IN std_logic y IN std_logic F OUT std_logic F OUT std_logic F OUT std_logic END Inv END And2 END Or2 e VHDL has several dozen reserved words ENTITY IS PORT IN OUT and END are reserved words above Our convention Reserved words are UPPER CASE User cannot use reserved words when naming items like ports or entities e User defined names Begin with letter optionally followed by sequence of letters numbers or underscore e No two underscores in a row and can t end in underscore Valid names A x Hello JXYZ B14 Sig432 Wire_23 Index counter 1 Inl test_entity Invalid names IN reserved word Wire ends in underscore Wire__23 two underscores in a row 4x1Mux doesn t start with a letter in4 doesn t start with a letter e Note VHDL is case insensit
50. 05060 70 8090100 10 8 29 2011 46 VHDL e VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit Project of the U S Dept of Defense VHDL defined in 1980s Syntax like Ada software programming language e Ada also a U S DoD creation IEEE adopted VHDL standard 1076 in 1987 e Other HDLs Verilog Defined in 1980s C like syntax IEE standard 1364 in 1995 VHDL amp Verilog very similar in capabilities differ mostly in syntax SystemC Defined in 2000s by several companies C libraries and macro routines IEEE standard 1666 in 2005 Excels for system level cumbersome for logic level 8 29 2011 ARCHITECTURE Beh OF DoorOpener IS BEGIN PROCESS c h p BGEIN f lt NOT c AND h OR p END PROCESS END Beh module DoorOpener c h p f Input e Sb D output f reg f always c or h or p begin E es le e p end endmodule include systemc h SC MODULE DoorOpener sc in sc logic c h p sc out sc logics f SC CTOR DoorOpener SC METHOD comblogic sensitive lt lt c lt lt h lt lt p void comblogic f write c read amp h read PrreadiOnDE VHDL Versions Version Comments VHDL 1987 Initial version accepted by IEEE VHDL 1993 First major update to language Increased flexibility and added missing constructs amp operations VHDL 2000 Minor update to language VHDL 2002
51. 2 5 v default oe iaaa rar 2 5 w obl mit Um iaa Ya 2 5 V cbs EN an rra 2 5 V eh d cde eh s E a K Type Beasage a FF J ji System JA Peocesging 120 Tes zira Infos jy Inda 113 y A Wanna Ti TAE Cried Worse 5 JA Erie JA u Fas f Passage iz Pin Planner zr View Window 2 Displays graphical representation of chip package Use to make or edit design I O assignments Use to locate other package pins power amp configuration pins e All Pins list Displays I O pins signals in design as indicated by filter Use to edit pin settings properties directly Groups list Similar to All Pins list except displays only groups amp buses Use to make bus and group assignments Use to create new user defined groups 38 8 29 2011 igning Pin Locations Using Pin Planner 0 Drag amp drop multiple a a a Q A hignlighiea pins or buses Am a v E dit Drag amp drop single pin tooltips provide pin information tak Choose n or pin alignment direction Pin Planner toolbar or Edit menu Using Pin Planner 2 m D altera 71 qdesigns fir filter fir filter filtref Pin Planner EIE Double click pin or I O pw Tools Window bank to open Properties dialog box Eoo Drag amp drop to I O Rufi sesigned tota TESETITSIDBANK 3 asol bank VREF block or 8 input D output H
52. 25 44 PM s Labz vhd i VHDL 2 5 18 11 03 33 53 PM ENNEEEE VYHOL 5 05 31 11 09 44 05 AM Or3 vhd Edit WHOL 3 05 18 11 02 23 38 PM Xor2 vhd ee un At td 12 23 37 PM Compile Compile Selected Add to Project 4 Compile All Remove From Project Compile Sut of Date Close Project Compile Order Update Compile Report a Compile Summary Properties Project Settings Compile Properties ll a Once the compilation is complete click the Restart button to restart the simulation then click Run to run the simulation again Now it can be seen that the testing condition we added to the test bench file occurs from 30 to 40 ns and the result is as expected cout_s is high indicating overflow and sum_s is all low uu ev BE sels caut s 9p ave Cursor 1 0011 Dunn 0011 0100 1100 TETTE xm mm TI 10010 nm ood 0010 ooo Jnn10 In110 TETTE a000 l 1 1 Lab 5 A VHDL Reaction Timer Lab 5 A VHDL Reaction Timer This lab will combine many advanced VHDL techniques including timers seven segment display drivers packages and functions and state machines to create a simple game that to test a person s reaction time Task 1 Create a New Project 1 Start the New Project Wizard Create a new project using the same procedure from the previous labs Set the Working Directory Project Name and Top Level Design Entity as seen in the table below Working Directory H Altera_T
53. 6 On page 4 of the MegaWizard Plug In Manager click Next 1 9 7 Verify that Mux3x1 vhd Mux3x1 cmp and Mux3x1_inst vhd are selected to be created and click Finish A dialog box may appear about the creation of a Quartus II Ip File If so simply click Yes MegaWizard Plug In Manager LPM_MUX page 5 of 5 Summary 4 LPM_MUX Ca Deumetan i Parameter 2 FDA i Summary Settings Turn en the Files you wish Ea generate 4 gray checkmark indicates a File that is automatically generated and a red checkmark indicates an optional File Click Finish to generate the selected Files The state of each checkbox is maintained in zm subsequent Megawizard Plug In Manager sessions d datatx 3 0 The Megavizard Plug In Manager creates the selected Files in the Following directory co oI Haltera TrainingiLabsiLabli bf Musas vhd Variation file O Musas me SHDL Include file 4 Mus3 1 cmp YHDL component declaration File O Musas bsf Quartus symbol file 4 Mus3 l inst hd lnstantiation template File 8 Compile the Design To perform a full compilation select Processing Start Compilation Alternatively select the Start Compilation button on the toolbar You may ignore any warnings that may appear at this time Task 3 Assign Pins 1 From the Menu Bar select Assignments gt Assignment Editor 2 From the drop down menu at the top for Category select Pin E 2i db Cukenory INE S NNNM o al amp
54. A design Pin assignments need to be verified earlier in design cycle Designers need easy way to transfer pin assignments into board tools 36 8 29 2011 Michiganiech Creating O Related Assignments Pin Planner Import from spreadsheet in CSV format Type directly into OSF file Scripting Using synthesis attributes in HDL Note Other methods tools are available in the Quartus Il software to make I O assignments The above are the most common or recommended Pin Planner Interactive graphical tool for assigning pins Drag amp drop pin assignments Set pin I O standards Reserve future I O locations eee gt Assign Constraints folder in Tasks window e Three main sections Package View All Pins list Groups list 3 8 29 2011 Pin Planner C allera trn Quartuz l Software Deripn Series Faundation OlIF10 Q ExS Verllop pipemult plpemult_ ic ila Fie Edt View Processing Toos aT E Packa Sr Toolbar _ Cyclone Ill EP3C5F2560 Top age View a Hini hanh Writ Uu dae dates 7 0 xK G gr sez i BF datahir 0 XE E 2 7T B 9 10 141 12 13 14 15 1B j E q 0 rel H De wraddnes 4 0 C Che FDI F el I AE TOSA 20900099 97 00 f Oy NO 2 Tel 00 po S M V AA N N ve p w S X E 2 5 XC mpy wa e Lob Io Farrell Recueil Far Copocbann wx EX OF chi ng 2 5 V defaut i datas 7 n 25 v defuit All Pins list E re hix
55. ASIC designs Generate and more Lead Principal Electrical Jabil St Petersburg FL Engineer Medical and FW design for medical devices FPGA and CPLO design experience using VHDL or DSP design experience is a plus Abdty to weigh cost function i Internet Protected Mode Off 8 29 2011 8 29 2011 Why Help is Needed PGA s are horrendously complex much more than computer software Many tools coding systems etc Analog non ideal timing behavior Many types of devices Code synthesis Place amp Route are not deterministic e In short a design frequently Is theoretically correct Simulates OK Failsin a real part Why are they important They have the ability to revolutionize the way that prototyping is done Allows companies to get to market quicker and stay in market longer 8 29 2011 Xilinx Largest manufacturer of HW Develop hardware and software e Embedded PowerPC University Program Altera e Second largest manufacturer Develop HW and SW University Program Which is best It depends Time Existing resources Money Level of effort Preference University Programs Major manufacturers want to provide you with the resources to be successful A Xilinx University Program s gt Rock 8 29 2011 10 8 29 2011 AUP Altera University Program SBROWN altera com Stephen Brown Very ag
56. C6 t Resource Usage Summary Timing Models Final t Resource Utilization by Entity EEE RAM Summary Met timing requirements N BB Optimization Results Total logic elements 101 5136 2 Source Assignments Total combinational functions 100 5135 22 amp Parameter Settings by Entity Instance Dedicated logic registers 32 5136 1 8 eL LPM Parameter Settings Total registers 48 amp i Messages Total pins 44 183 24 Fitter Total virtual pins 0 Assembler Total memory bits 512 423 936 lt 1 TimeQuase Timing Analyzer Embedded Multiplier 9 bit elements 0 46 0 J TimeQuest Timing Analyzer G Total PLLs 0 2 0 Each compiler executable generates separate folder 60 For Help press F1 8 29 2011 30 8 29 2011 Netlist Viewers RTL Viewer Schematic of design after Analysis and Elaboration Visually check initial HDL before synthesis optimizations Locate synthesized nodes for assigning constraints Debug verification issues Technology Map Viewers Post Mapping or Post Fitting Graphically represents results of mapping post synthesis amp fitting Analyze critical timing paths graphically Locate nodes amp node names after optimizations cross probing RTL Viewer RIL Viewer C faltera_trn Quartus_Il_Software_Design_Series_Foundation QIIF10_O Ex1 Verilog pipemult pipemult_Ic EIE File Edit View Tools Window BP lite E RIA amp Q 4 Page Title pipemult Pa
57. Compilation Report El Legal Notice er Flow Summary Flow Status Successful Wed May 25 08 58 17 2011 SE Pa Quartus II Version 4 1 Build 222 10 21 2009 SJ Full Version Flow Non Default Global Settings ES Flow Elapsed Time Revision PSU Lab3 Sr Flow05 Summary suas Entity Marne Labia E Flow Log Family Cyclone Il S Analysis amp Synthesis Device EP2CS5F6 2C6 Fitter Timing Models Final eh Assembler Mat timing requirements Tes en Timing Analyzer Total logic elements dors Peel eds Total combinational functions 1 7 S3 216 lt 1 Dedicated logic registers Oy 33 215 0 Total registers 0 Total pins als a z Total virtual pins Total memory bits Uy 483 840 0 3 Embedded Multiplier 3 bit elements 5 70 3J Total PLL 0 4 0 3 Inthe Compilation Report click on Timing Analyzer to display the Timing Analyzer Summary Here you can see that the maximum clock speed of this design is currently 165 89 MHz abe Lab3a vhd Compilation Report Timing Compilation Report Timing Analyzer Summary El Legal Notice I Slack Pequired Actual PET Flow Summary Jpe acm Time Ehe Flow Settings 5 352 ns a Flow Nan Default Global Settings worst case too GES None 8411 ns a Flow Elapsed Time Worst case th AeA Mone AES Flu BEE Flow 05 Summary Clock Setup CLK N A None 165 89 MHz BE Flow Log Timing Analyzer Seal Summary Ehe Settings 4 Select Tools gt Netlist Viewers gt RTL
58. De bergie a uom kerpinie IH I VLL m ZI tune Quartus II Full Compilation Flow Analysis amp Elaboration mp Fitter Executed in parallel multi processor or multi core systems only Assembler i i EDA Netlist Writer TimeQuest Timing Analysis Functional Netlist Programming amp Configuration files Simulation Post Fit Simulation Files 28 8 29 2011 Processing kA A 7 oh fe E re ets us 2 hes ec 2 art Compilation Full DERE uem EEE Start Analysis amp Elaboration re ie M hU Checks syntax amp builds hierarchy a Ay M S vat Anaras Uh Labor spen Performs initial synthesis Update Memory riskaution Fhe MT Start anys b Syrtes i b Compilation papat Che Eb Start Partition Merge Start Analysis amp Synthesis Mann y e Funchal Simsion hetit soda cami Synthesizes amp optimizes code cu Pas Start ss ring Anshar Ces Cheb L Short Times Ting amp nshyzer Sir Seren De b ik i Start Fitter amp Silicon Raport m 3 nn Writer e Stuart eon sisti Places amp routes design E Compi Tool a Sarl Pier Play Pirar Ano pner Air Cal oP amp Ei Todd r Short SSH rhy per Generates output netlists Bemis Muse alain Start Assembler Vs Se Anabyaer Tec FF Start LO Abignment Anaya St ass Tum Araber Fat Tina Meile Generate programming files x RATEN Tea een wer Sarl Chaise Tieng Anahrser Cornbraind Cher Analyze rs z en vex E Bart
59. FATE Lab 1 Introduction to Quartus II Lab 1 Introduction to Quartus Il This lab is designed to familiarize you with using many ofthe common aspects of the Quartus II software through a complete design phase You will create a new project create a new vhdl file use the MegaWizard Plug In Manager compile the design plan and manage I O assignments apply timing analysis using the TimeQuest Timing Analyzer write Synopsys Design Contraint SDC files and program a design onto the Altera DE2 Development Board 1 1 Task 1 Create a New Project 1 2 1 Start the Quartus II software From the Windows Start Menu select All Programs gt Other Apps gt Altera gt Quartus 119 1 gt Quartus II 9 1 32 Bit Start the New Project Wizard If the opening splash screen is displayed select Create a New Project New Project Wizard otherwise from the Quartus II Menu Bar select File gt New Project Wizard Select the Working Directory and Project Name Working Directory H Altera_Training Lab1 Click Next to advance to page 2 of the New Project Wizard Note A window may pop up stating that the chosen working directory does not exist Click Yes to create It Mew Project Wizard Directory Name Top Level Entity page 1 of 5 E3 What is the working directory Far this project H sAltera Training Labi ves What is the name of this project Labi i What iz the name of the top level design entity for this project
60. GIC compiler tool x y z OUT STD LOGIC c Note Remember that WORK and STD END ENTITY cmpl sig do not need to be defined ARCHITECTURE logic OF cmpl sig IS BEGIN USElib name pack name object Simple signal assignment X lt a AND NOT sel OR b AND sel ALLis a reserved word for object name Conditional signal assignment Y lt a WHEN sel 0 ELSE B e Placing the library use clause first will Selected signal assignment allow all following design units to access WITH sel SELECT it Z lt a WHEN 0 B WHEN 1 O WHEN OTHERS END ARCHITECTURE logic Types Defined in STANDARD Vpe BIT Package 2 logic value system O 1 SIGNAL a temp BIT Bit vector array of bits SIGNAL temp BIT VECTOR 3 DOWNTO 0 SIGNAL temp BIT VECTOR 0 TO 3 Type BOOLEAN False true Type INTEGER Positive and negative values in decimal SIGNAL int tmp INTEGER 32 bit number SIGNAL int tmpl1 INTEGER RANGE O TO 255 8 bit number 99 8 29 2011 Other Types Defined in Standard Type NATURAL Package Integer with range 0 to 2 Type POSITIVE Integer with range 1 to 2 Type CHARACTER ASCII characters Type STRING Array of characters Type TIME Value includes units of time e g ps us ns ms sec min hr Type REAL Double precision floating point numbers Ci 2 Libraries SRARY IEEE cont Contains the following packages
61. Gheack Ba Eve Al Bend lock Coraes W O Assignment Start Luabon wher Post rethada Kart Lausbon Anker Past Fibnia Eme Powe rPlay Start Test erh Template Aries SSN Switching Noise goin m m Start Design Assistant Processing Options Sat Compishon and Semen l Shift ompilation Design Flows Default flat compilation flow Design compiled as a whole Global optimizations performed ncremental flow on by default for new projects User assigns design partitions Each partition processed separately results merged Post synthesis or post fit netlists for partitions are reused Benefits Decrease compilation time Preserve compilation results and timing performance Enable faster timing closure 29 Utility Windows Full Compilation BE 00 00 20 View menu gt Utility Windows Analysis amp Synthesis D 00 00 09 Fitter 00 Sk a Time Assembler 00 Compile Design 00 00 57 ON Analysis amp Synthesis 00 00 35 Fitter Place amp Route 00 00 22 Assembler Generate programming files TimeQuest Timing Analyzer Status bars indicate compilation progress TimeQuest Timing Analysis EHEH Message window displays informational Messages warning amp error messages Manually flag selected Message messages for later review Info Fitter routing operations endin Info The Fitter perforpes ompilation No optimizations were skipp e design s timing al Info Sta
62. HEN idle gt WHEN gt water lt 1 WHEN heat_w gt spin lt 1 heat lt 1 WHEN wash gt spin lt 1 WHEN drain Et Output logic function of spin lt E current state only pump lt 17 END CASE END PROCESS Heat demand 0 Encoding Styles Binary Grey Code One Hot Custom Encoding Encoding Encoding Encoding m Tom oo me m Quartus II default encoding styles for Altera devices One hot encoding for look up table LUT devices e Architecture features lesser fan in per cell and an abundance of registers Binary minimal bit or grey code encoding for product term devices e Architecture features fewer registers and greater fan in 102 8 29 2011 Encoding Style Assignment Editor Ae Enn fan Ja i ES Pin amp Timing gt ae Options 1 F Show assignments for specific nodes Check All Uncheck All Delete All x Information The Assignment Editor is the interface for creating editing and viewing individual assignments including pin assignments in the Quartus II software X v ee Zr OE From Tr Assignment Name aue Enabled EN current state State Machine Processing User Encoded lt new gt gt ED lt lt new gt gt dr E US Hal epow m LIE m Ex 49 e He 4 Apply Assignment to Options State Variable One Hot Gray Minimal Bits Sequential
63. LOGIC VECTOR 1 DOWNTO 07 output OUT STD LOGIC VECTOR 3 DOWNTO 0 END Labl ARCHITECTURE Structure OF Labl IS COMPONENT Mux3x1 IS PORT clock T D LOGIC VECTOR 3 DOWNTO 0 sel result STD 3 DOWNTO 0 END COMPONENT BEGIN MuxOut Mux3x1 PORT MAP clk inputO inputl input2 sel output END Structure 3 Create an 4 Bit 3x1 Multiplexer using the MegaWizard Plug in Manager Select Tools gt MegaWizard Plug In Manager Select the radio button for Create a new custom megafunction variation and click Next MegaWizard Plug In Manager page 1 The Megaw izard Plug In Manager helps you create or modify design files that contain custom variations of megafunctions Which action do vou want to perform f Create a new custom megafunction variation t Edit an existing custom megafunction variation t Copy an existing custom megafunction variation Copyright E 1991 2009 Altera Corporation Lancel jl Next gt ifi 1 7 4 From the Gates menu select the LPM_MUX subitem and name the file Mux3x1 and click Next MegaWizard Plug In Manager page 2a Which megafunctien would you like to customize Select a megafunction from the list below E B Installed Plug Ins e Altera SOPC Builder Arithmetic Communications fg DSP mE Gates eq LPM AND a LPM _BUSTHI A LPM LLSHIFT 47 LPM CONSTANT 4 LPM_DECODE 4e LPM INV 423 LPM MUH iz LPM_OR ie LPM OF ann mme Interfaces
64. N 54 gt IF B 1 THEN next state lt 55 ELSE next state lt S1 END IF WHEN 55 gt IF A 0 AND B 1 THEN next state lt 2 ELSIF A 1 AND B 0 THEN next state lt 3 END IF WHEN OTHERS gt next state current state END CASE END PROCESS Output Process PROCESS current state BEGIN state data lt OTHERS gt 0 CASE current state IS HEN S1 gt state data lt 001 WHEN 52 gt state data lt 010 WHEN 53 gt state data lt 011 WHEN 54 gt state data lt 100 WHEN 55 gt state data lt 101 WHEN OTHERS gt NULL END CASE END PROCESS END Lab3b arch 2 SelectProject gt Setas Top Level Entity to specify that Lab3b vhd is now the main file for the design Compile that code using the Start Compilation button Click OK when compilation is complete 3 8 3 Click on the Warning tab in the Messages pane to view the warnings Message Il Warning l 8631 VHDL Frocess Statement warning at Lab3b vhdi34 Ea Warning Latch next state 54 l48 has unsafe behavior AY Warning Latch next state se 164 has unsafe behavior ih Warning Latch next state 53 166 has unsafe behavior AY Warning Latch next state 55 1350 has unsafe behavior AY Warning Found 3 output pins without output pin load capacitance Warnins The Reasertme 1717 TIrised Pins setting has nnt heen 2naecifii Sestem 34 A Processing 6 A Extralnto A Info 64 A Warning 11 A
65. QuartusII9 1 gt Quartus II 9 1 32 Bit 2 Start the New Project Wizard If the opening splash screen is displayed select Create a New Project New Project Wizard otherwise from the Quartus II Menu Bar select File gt New Project Wizard 3 Select the Working Directory and Project Name Working Directory H Altera_Training Lab2 Click Next to advance to page 2 of the New Project Wizard Note A window may pop up stating that the chosen working directory does not exist Click Yes to create it Mew Project Wizard Directory Mame Top Level Entity page 1 of 5 fx What is the working directory for this project H Altera_Training Labe What is the name of this project What is the name of the top level design entity for this project This name is case sensitive and must exactly match the entity name in the design File Lab2 Use Existing Project Settings Finish Cancel 2 2 4 Click Next again as we will not be adding any preexisting design files at this time 5 Select the family and Device Settings From the pull down menu labeled Family select Cyclone Il In the list of available devices select EPC235F672C6 Click Next New Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation M Device family gt shown Available device list Family Cyclone Il r Package Any fll d Fin count Ary Target device Spee
66. R E STD LOGIC 1164 ALL IP END ENTITY cmpl sig ARCHITECTURE logic OF cmpl_sig IS BEGIN Simple signal assignment x lt a AND NOT sel OR b AND sel Conditional signal assignment y lt a WHEN sel 0 ELSE b Selected signal assignment WITH sel SELECT z lt a WHEN 0 b WHEN 1 X WHEN OTHERS END ARCHITECTURE logic Process Statements Implicit process Types Concurrent signal assignments Component instantiations Process sensitive to all inputs e g Read side of signal assignment Explicit process PROCESS keyword defines process boundary 64 ocess sensitive to explicit optional sensitivity list Events transitions on signals in sensitivity list trigger process 051 X21 122 etc Declaration section allows declaration of local objects and names Process contents consist of sequential statements and simple signal assignments Process statement is executed infinitely unless broken by a WAIT statement or sensitivity list Sensitivity list implies a WAIT statement at the end of the process Due to all processes being executed once at beginning of model execution Process can have multiple WAIT statements Process can not have both a sensitivity list and WAIT statement c Note Logic synthesis places restrictions on the usage of WAIT statements as well as on the usage of sensitivity lists Statement PROCESS Statement PROCESS a b BEGIN
67. R Create Revision CI Specify Project Libraries TI Import Database Advisors Create Design MIT Create New Design File IT Open Existing Design File J Add Remove Files in Project ivi er Megawizard Plug In Manager IP cores and megafunctions Er SOPC Builder system generation Assign Constraints TI Import Assignments 107 Set Project and Compiler Settings og Design Partitions Open Design Partition Planner amp Edit LogicLock Regions Open LogicLock Regions Window 2 Edit Pin Assignments Open Pin Planner 12 Edit Logic Options Open Assignment E ditor i CIE Export Assignments M Compile Design RO Program Device Open Programmer H IC Verify Design CIE Export Database OD Archive Project Tel Scripts Custom Task Flow cl Console Window Enter and execute Tcl commands directly in the GUI View menu gt Utility Windows gt Tcl Console x Quartus II Tcl Console project close project open pipemult set global assignment name VvHDL FILE mult whd execute flow compile Tcl Console Execute from command line using Tcl shell Gmarctus_ sh shell e Run complete scripts from Tools menu gt Tel Scripts 42 8 29 2011 21 Ypical PLD Design Flow gt Design entry RTL coding J Behavioral or structural description of design mnn RTL simulation Functional simulation UUU Verify logic model amp data flow e Synthesis Mapping Translate design into device specif
68. Read SDC File in the TasKs window to read in an SDC file Click the ellipses to select the Targets which opens up the Name Finder window Click List in the Matches field and select clk Click the single right arrow E add it to the list of selected names and then click OK Click Run in the Create Clock dialog box to create the clock Mame Finder Collection get parts Filter Options Case insensitive Matches List clk input LI input 1 inputi input a input LU inputifi input 2 inputi 3 inputz U inputz 1 inputz 2 inputz 3 output SOC command l get parts ck OF Cancel 6 Select Constraints gt Set Input Delay from the Menu Bar For Clock name select clk Make a Delay value of 20 ns Click the ellipses to select the Targets Click List in the Matches field and select all of the input and sel names Click the single right arrow to add them to the list of selected names and then click OK Click Run in the Set Input Delay window to create the input timing constraints Name Finder Collection Filter Options Case insensitive Io Hierarchical l Compatibility mode Matches List 18 matches found 14 selected names 1 13 input a autput 0 imputi 0 inputi t inputi z imputi 3 Tay ave
69. STD LOGIC 1164 STD LOGIC types amp related functions NUMERIC STD unsigned arithmetic functions using standard logic vectors defined as SIGNED and UNSIGNED data type STD LOGIC ARITH arithmetic functions using standard logic vectors as SIGNED or UNSIGNED STD LOGIC SIGNED signed arithmetic functions directly using standard logic vectors STD LOGIC UNSIGNED unsigned arithmetic functions directly using standard logic vectors STD LOGIC TEXTIO file operations using std logic Packages actually developed by Synopsys but accepted and supported as standard VHDL by most synthesis and simulation tools 06 8 29 2011 Types Defined in ALE STD LOGIC 1164 Be STD LOGIC Package 9 logic value system U x 0 1 2 W U H e 1 Logic high e U Undefined e 0 Logic low e H Weak logic high e X Unknown e L Weak logic low e Z not Z Tri state e W Weak unknown e Don t Care Resolved type supports signals with multiple drivers Driving multiple values onto same signal results in known value Type STD ULOGIC Same 9 value system as STD LOGIC Unresolved type Does not support multiple signal drivers Driving multiple values onto same signal results in error D OR NOT Gates Entities and Ports E ENTITY And2 IS ENTITY Or2 IS ENTITY Inv IS PORT x IN std logic PORT x IN std logic PORT x IN std logic IN std logic
70. Select Vector Waveform File under the Verification Debugging Files heading SOFC Builder System Design Files amp HDL File Black Diagram Schematic File EDIF File State Machine File System erilog HDL File Tel Script File erlag HDL File WHOL File E Memory Files Hexadecimal Intel Format File Memory Initialization File m Verfication D ebugging Files oo eS ystem Sources and Probes File Logic Analyzer Interface File SignalT ap Il Logic Analyzer File Other Files amp HDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File 2 Add Signals to the Waveform Select Edit gt Insert gt Insert Node or Bus to open the Insert Node or Bus window Insert Node or Bus Type INPLIT Cancel Value type 9 Level Node Finder Radis Binary Bus width 1 Start indes 0 Display gray code count as binary count 2 10 3 Click the Node Finder button in the Insert Node or Bus window to open the Node Finder window From the Filter drop down menu select Pins all and click the List button This will display all the inputs and outputs to the circuit Highlight all the the Input Groups A and B the Input Sel and Output Group Sum in the Nodes Found window and click the right arrow to select them Then click OK to close the Node Finder window Node Finder Mamed li Filter i Look in EA Modes Found a
71. This name i case sensitive and must exactly match the entity name in the design File Lab S Use Existing Project Settings Finish Cancel 4 Click Next again as we will not be adding any preexisting design files at this time 5 Select the family and Device Settings From the pull down menu labeled Family select Cyclone II In the list of available devices select EPC235F672C6 Click Next New Project Wizard Family amp Device Settings page 3 of 5 Select the family and device you want to target for compilation M Device family gt shown Available device list Family Cyclone Il r Package Any fll d Fin count Ary Target device Speed grade Any C Auto device selected by the Fitter I Show advanced devices Specific device selected in Available devices list Hardon Available devices Core voltage LE Mem EP2C200 24008 239616 EP2C35F 48406 483840 EP2C35F484C7 483840 EP2C35F484C8 483840 EP2C35F 48418 JEP2C35F67206 EP2C35FB 207 EP2C35FB 208 CO a 3EPECTMo lt Back Finish Cancel 6 Click Next again as we will not be using any third party EDA tools 1 3 7 Click Finish to complete the New Project Wizard New Project Wizard Summary page 5 of 5 When wou click Finish the project will be created with the following settings Project directory H Altera Trainig LabsLab 1 Project name Lab Top evel design entity Lab Humber of tiles
72. a b c d z lt a b c s Ope 106 8 29 2011 Operators a b c d 4 bit vectors Example Unbalanced Balanced z a b c d z a b c d 4x4 X X 16 bit e EU through 2 stages of multiply Delay through 3 stages of multiply Resource Sharing Reduces number of operators needed Reduces area Two types Sharing operators among mutually exclusive functions Sharing common subexpressions Synthesis tools can perform automatic resource sharing Feature can be enabled or disabled 107 processi rst clk variable tmp_q std_logic_vector 7 DOWNTO 0 begin if rst 0 then tmp_q OTHERS gt 0 elsif rising_edge clk then if updn 1 then tmp_q tmp_q 1 else tmp q tmp q 1 end if end if q lt tmp_q end process rocess rst clk variable tmp_q std logic vector 7 DOWNTO 0 variable dir integer range 1 to 1 begin if rst 0 then tmp_q OTHERS gt 0 elsif rising edge clk then if updn 1 then dir 1 else dir 1 end if tmp_q tmp_q dir end if q lt tmp_q end process 8 29 2011 tuallV Exclusive Operators Up down counter 2 adders are mutually exclusive amp can be shared typically IF THEN ELSE with same operator in both choices Registers ar ng Mutually Exclusive Operators Up down counter Only one adder required clk rst Registers 108 8 29 2011 How Many Multipliers
73. achines hE State Machine Lab3 curr e Optimization Results e Source Assignments 3 11 Compilation Repor a ATL Viewer amp State Machine Viewer State Machine Lab3 current_state Encoding Type User Encoded current state b curent_state 5 current state 4 curent state SZ cument state 53 D curent state 54 current state 55 1 5 Select Line 16 in the Lab3b vhd code and click the Comment selected text button Then select Line 14 and click the Uncomment selected text button This changes the encoding type to Gray Encoding Save the changes to Lab3b vhd and compile the design to see the results of changing the State machine encoding 10 ATTRIBUTE syn encoding STRING 11 ATTRIBUTE syn encoding OF State types TYPE IS 12 m on OOF010 O0100 O1000 10000 One Hot Encoding 13 a I GENERE EE Ba ea SS en ie BS 14 rpg OJE EE X A E ee ee ED de REN RE BSHI Lili bE So Johnson Enmboodirmg 16 SER OE Le DEE eee Se eae 1a Eneoding 6 Again look at the Flow Summary of the Compilation Report and Fmax Summary under the Slow 3 12 Model in the TimQuest Timing Analyzer section of the Compilation Report Compare the current values to the previous results Lines 12 through 16 in the Lab3b vhd file each contain a different encoding type which can be selected by uncommenting the desired line and then compiling the design again and comparing the change
74. added U Humber of user libranes added U Device assignments Family name Cyclone ll Device EP2C35F 6 206 EDA tools Design entry synthesis None Simulation More Timing analysis None Operating conditions Core voltage Ti Junction temperature range 0 05 E tae Task 2 Create Add and Compile Design Files 1 Create a new Design File Select File gt New from the Menu Bar Select VHDL File from the Design Files list and click OK SUPC Builder Sytem Design Files AHOL File Black Diagram 5 chematic File EDIF File State Machine File System Verlag HOL File Tel Script File Verlag HOL File SHOL File Memory Files Hexadecimal Intel Farmat File Memory Initialization File Verificatian D ebuaging Files n Sustem Sources and Probes File Logic Analyzer Interface File Signall ap II Logic Analyzer File Vector Waveform File H Other Files SHOL Include File Black Symbol File Chain Description File Synopsys Design Constraints File Text File wt Cancel 1 5 1 6 2 Copy and paste the following code into your new VHDL file then save it by selectingFile gt Save Keep the default file name and click Save in the Save As dialog box Lab 1 Introduction to Quartus II VHDL Code LIBRARY eee USE ieee std logic 1164 all ENTITY Labl IS PORT clk IN STD LOGI C input0 inputl input2 IN STD LOGIC VECTOR 3 DOWNTO 0 sel IN STD
75. al behavior Output l l en 3 d i ELSIF s1 0 AND s0 1 THEN value is purely a function of the i4 qoe present input values on ELSIF si 1 AND s0 0 THEN Sequential behavior Output _ de 12 value is a function of present and ELSE past input values i e the system i d lt i3 has memory EN CEU END PROCESS END Beh 89 8 29 2011 Latches vs Registers Altera devices have registers in logic elements not latches Latches are implemented using combinatorial logic amp can make timing analysis more complicated Look up table LUT devices use LUTs in combinatorial loops Product term devices use more product terms Recommendations Design with registers RTL Watch out for inferred latches Latches inferred on combinatorial outputs when results not specified for set of input conditions Lead to simulation synthesis mismatches Structure LSE like WHEN ELSE concurrent assignment structure implies prioritization amp dependency Nth clause implies all N 1 previous clauses not true Beware of needlessly ballooning logic Logical Equation lt condl gt eA lt condl gt cond2 B lt condl gt lt cond2 gt cond3 C Consider restructuring IF statements May flatten the multiplexer and reduce logic IF cond1 THEN p IF cond1 AND cond2 THEN IF cond2 THEN e If sequential statements are mut
76. are hardware 3 30 pm Implementation Adaption Plan Issues at schools 4 00 pm Conclusions Feedback Survey 81 8 29 2011 Please go to Lab3 VHDL Testbench in the Manual Advanced VHDL Design Techniques FSM Writing synthesizable VHDL Create state machines and control their encoding Optimize designs to improve resource usage and performance 82 State Diagram JV VO V Code for FSM e State machine states must be an enumerated data type TYPE state type IS idle tapl tap2 tap3 tap4 Object which stores the value of the current state must be a signal of the user defined type SIGNAL filter state type 8 29 2011 83 8 29 2011 Michiganech riting VHDL Code for FSM cont To determine next state transition logic Usea CASE statement inside a sequential process e Use 1 of 2 methods to determine state machine outputs 1 Use a combinatorial process with a CASE statement 2 Use conditional and or selected signal assignments for each output E STD LOGIC 1164 ALL ENTITY filter sm IS PORT clk reset nw IN STD LOGIC select OUT STD LOGIC VECTOR 1 DOWNTO 0 nxt first OUT STD LOGIC END ENTITY filter_sm ARCHITECTURE logic OF filter_sm IS TYPE state_type IS idle tapl tap2 tap3 tap4 SIGNAL filter state_type BEGIN nn FSM VHDL Code Enumerated Data Type Enumerated data type 84 IF reset 1 THEN filter lt idle ELSIF clk
77. ate a new result 7 Create another new VHDL file following the directions in step 1 of task 2 8 Copy and paste the following code into your new VHDL file then save it by selecting File gt Save Name the file FullAdder and click Save in the Save As dialog box Lab 2 Introduction to VHDL Full Adder Structural VHDL Code LIBRARY i eee USE ieee std logic_1164 ALL ENTITY Full Ad d PORT A IN B N END Full Adder ARCHITECTURE Full Adder struct OF FullAdder IS COMPONENT Gate And2 IS PORT x f END COMPONENT COMPONENT Gate XOR2 IS PORT x f END COMPONENT COMPONENT Gate OR3 IS FORT bxe Vy Zi NEG Pid logit f OUT std logic END COMPONENT SIGNAL XOR2 0 out AND2 0 out AND2 1 out AND2 2 out std logic Gate XOR2 PORT MAP Gate XOR2 PORT MAP Gate AND2 PORT MAP XOR2 0 out Gate AND2 PORT MAP A 0 out Cin Sum AND2 0 out AND2 1 out AND2 2 out out AND 1 out AND2 2 out Cout B 2 B C Gate AND2 PORT MAP Ci Gate OR3 PORT MAP END Full Adder struct A X A A B N OR in n D2 0 This is an example of structural style VHDL which utilizes the multiple components we previously created and stitches them together to produce the desired result In this case there are two instances of the XOR gate used three AND gates used and one OR gate to create the full adder The argument list for each component instance is fashioned in a way to produce t
78. ates In the Idle state within the the green and red LEDs are turned off and all timers and counters are reset to zero In the Countdown state the red LEDs are turned on and the countdown timer starts When the countdown timer is done countdown_done is set high Once countdown_done is high the current_state becomes the Timing state Here the millisecond timer starts counting until the user presses the button to stop it Finally in the Score state the user s time is displayed in milliseconds Pressing the reset button KEY1 on the DE2 development board will return you to the idle state at any point The Time_Display_Process takes in the elapsed time in binary format converts that from binary to BCD and then to a value suitable to use to display the desired decimal digit on one of four seven segment displays The bin_to_7seg vhd file contains two functions used by the Lab5 vhd code within the Time_Display_Process The first function is Bin_to_BCD which uses a double dabble algorithm to convert a 16 bit binary value to five 4 bit BCD values although only four ofthese BCD values are used by the Lab5 vhd code The other function BCD_to_7seg converts the BCD values to a 7 bit value that represents each digit for the seven segment displays As part of this lab exercise in the Lab5 vhd file you will need to finish the case statement in the Timer_State_Machine process as well as the function calls in the Time_Display_Process used to
79. base Convert MAX PLUS II Project Save Project recommend using top level file name E New Project Wizard Directory Name Top Level En page 1 of 5 What is the working directory for this project C faltera_trn Quartus_II_Software_Design_Series_Foundation QUF10_O Ex1 erllog What is the name of this project pipemult What is the name of the top level design entity for this project This name is case sensitive and must exactly match the entity name in the design file pipemult Top level entity does not need to be the same name as top level file name Tcl project new project name 23 8 29 2011 N Hew Project Wizard esign files Add Files page 2 of 5 Sekal es cnc ec eon nnd Ln eee i n eine Cik Peed E eo de cg e in Ihe pr p ac ben Ho praal Mata vou can dens sd desgn files bo the precast later Graphic ia rar VHDL Flne Type sy Deipfin edd HD Veron Verilog SystemVerilog EDIF VQM m Add library paths User libraries MegaCore AMPPSM Pre compiled VHDL packages Tcl set_global_assignment name VHDL_FILE lt filename vhd gt Tcl set_global_assignment name USER_LIBRARIES lt library_path_name gt Add Files Device Selection New Project Wizard Family amp Device Set Choose device family Select the family and device you wan df compilation Device Family Show in Available devices list Family Cyclone HII Package FBGA
80. cked No internal logic Checks I O locations amp constraints with respect to other I O amp I O banks Each I O bank supports a single Vecio O connected to logic Checks I O locations amp constraints with respect to other I O I O banks amp internal resources PLL must be driven by a dedicated clock input pin Note When working with design files synthesize design before running I O Assignment Analysis Q2 fof Compilation Report Fitter section fev Pin out file ee O pin tables Output pin loading Y Quartus Il Didaltera t qdesiges fir_fiter fir_filty Pie dt View Propet Ascoreerts en Took De c us Project Nanvgahor t H e O rules checking Lowy Staxit EP317 404 P mer Messages on I O assignment issues Compiler assumptions Device amp pin migration issues I O bank voltages amp standards Type rie Messu i Jain Beleched device migration psth implemented 8 pins oF GHD Warning Devices selected for migration baye different speed qrades info Selected device migration path t ure 0 pins as regular Into Selecced device migration path armat ure fl pinse am DOS Ile migrsriu n patch East us a m4 1 rJ pink az ga ta L os info Selected device Jain Feleched device migration Path caet usc 2 pins Info Fitter renverred user pins inen dedicated prezrags amp imz pins a d I xi RI Eem A Processing Daana J into wameg Clea Waring A En
81. cognized synthesis tool only accounts for explicitly defined states Exception Number of states equals power of 2 AND binary grey encoding enabled Safe state machines created using synthesis constraints Quartus Il software uses e SAFE STATE MACHINE assignment applied project wide and to individual FSMs VHDL synthesis attribute May increase logic usage 9 current state Safe State Machine new new 104 8 29 2011 Optimization amp Performance m Balancing operators m Resource sharing Logic duplication Pipelining Operators Synthesis tools replace operators with pre defined pre optimized blocks of logic Designer should control when amp how many operators Ex Dividers Dividers are large blocks of logic Every mod and rem inserts a divider block and leaves it up to synthesis tool to optimize Better resource optimization usually involves cleverly using multipliers or shift operations to do divide 105 8 29 2011 from Operators Synthesis tools break down code into logic blocks They then assemble optimize amp map to hardware IF sel 10 THEN pis y lt atb ELSE gt y lt a 10 END IF 1 Mulitplexer 1 Comparator Operators Jarenthesis to define logic groupings Increases performance May increase utilization Balances delay from all inputs to output Circuit functionality unchanged Unbalanced Balanced z lt
82. d grade Any C Auto device selected by the Fitter I Show advanced devices Specific device selected in Available devices list Hardon Available devices Core voltage LE Mem EP2C200 24008 239616 EP2C35F 48406 483840 EP2C35F484C7 483840 EP2C35F484C8 483840 EP2C35F 48418 JEP2C35F67206 EP2C35FB 207 EP2C35FB 208 CO a 3EPECTMo lt Back Finish Cancel 6 Click Next again as we will not be using any third party EDA tools 2 3 7 Click Finish to complete the New Project Wizard New Project Wizard Summary page 5 of 5 When you click Finish the project will be created with the following settings Project directory H Altera Traning Lab2 Project name Top level design entity Number of files added Humber af user libraries added Device assignments Family name Cyclone Il Device EP2C35F 6 206 EDA tools Design entrsynthesis zMone Simulation Mones Timing analysis None gt Operating conditions Core voltage J A Junction temperature range 0 65 C Task 2 Create Add and Compile Design Files 1 Create a new Design File Select File gt New from the Menu Bar Select VHDL File from the Design Files list and click OK SUFL Builder Sytem Design Files AHOL File Black Diagram Schematic File EDIF File State Machine File Syster erlog HOL File Tel Script File Merlog HOL File Memory Files Hexadecimal Intel Format File
83. dapters Tools Help EDA Interfaces Shortcut to Altera forums A A File c Jaltera10 0fb LJ Quartus II Help Version 10 0 Getting Started with Quartus II Managing Projects Y Using Project Revisions Archiving Projects Project Database File Export and Y Using Advisors for Design Optimi Viewing Reports and Messages Creating Designs Y Using HDL with the Quartus II Sc Y Using Altera Megafunctions Creating System Level Designs Assigning Constraints Compiling Designs Running Timing Analysis Achieving Timing Closure Y Power Estimation and Analysis Signal Integrity Analysis Be aena moa ith Amial anal M QUARTUS TUTORIAL Welcome Quartus II Introduction e Welcome to the Quartus Il Software The Quartus Il development software provides a complete design environment far on a programmable chip SOPC design Regardless of whpthoarwe a auter or a Linux workstation the Quartus Il software ensures easy design e A rward device programming The following sections describe the general Expand all topics e Quartus Il software Quartus II Highlights Design Capabilities NativeLink Integration with other EDA Tools Web browser based allows for easy search in page Click any of the following flow icons for more information a includes block based design Design Entry system level design amp software development B U It n Syst Help menu gt Getting Started Tutorial or fro
84. display the time Some hints are provided in the comments in the code Task 2 Pin Assignments 1 Make the Following Pin Assignments To location __ DE2BoardDescription 6 digit1 S PIN ADI1 SevenSegmentDigitO 3 _ 8 digit1 5 PIN V14 SevenSegmentDigitO 5 9 digit1 6 PINV13 Seven Segment Digit 0 6 ED R RS R ee ee ee RD RD E l ee ee EL 5 7 Seven Segment Digit 2 6 Seven Segment Digit 3 0 Seven Segment Digit 3 1 Seven Segment Digit 3 2 27 Seven Segment Digit 3 3 28 Seven Segment Digit 3 4 29 Seven Segment Digit 3 5 41 me mel mm bl i EN l l d d O 2 Click Save to save the pin assignments 3 Compile the Design by clicking on the Start Compilation button Task 3 Program the DE2 Development Board 1 Plugin and power on the DE2 board Make sure that the RUN PROG Switch for JTAG AS Modes is in the RUN position 2 Inthe Quartus II window click the Programmer button on the Toolbar to open the Programmer window xD The Hardware Setup must be USB Blaster USB 0 If not click the Hardware Setup button and select USB Blaster USB 0 from the drop down menu for Currently selected hardware Mode should be set to JTAG Make sure that the File is Lab5 sof Device is EP2C35F672 and the Program Configure box is checked 5 8 o Quartus II C Delete Lab5 Lab5 Lab5 Lab5 cdf File Edit Processing Tools Window a cz Hardware
85. e A Suepeised ieg E Hepu of Efl Far Help press Fl Note See Appendix for special reports and information generated only for Stratix Il Cyclone Ill and newer devices 42 Introduction to VHDL Implement basic constructs of VHDL Implement modeling structures of VHDL 8 29 2011 43 8 29 2011 VHSIC Very High Speed Integrated Circuit Hardware VHDL Description Language What is VHDL e IEEE industry standard hardware description language e High level description language for both simulation amp synthesis Facilitates portability and productivity as design logic and verification stimulus are both vendor and tool independent 44 8 29 2011 Terminology HDL A hardware description language is a software programming language that is used to model a piece of hardware Behavioral modeling Acomponent is described by its input output response Structural modeling A component is described by interconnecting lower level components primitives Terminology cont Register Transfer Level RTL A type of behavioral modeling for the purpose of synthesis Hardware is implied or inferred Synthesizable Synthesis Translating HDL to a circuit and then optimizing the represented circuit Process Basic unit of execution in VHDL Process executions are converted to equivalent hardware 45 Digital Systems and HDLs Typical digital components per IC
86. e Menu Bar Click the ellipses next to File name in the Settings window that popped up Select Script Files in the drop down box for Files of type in the Select File window Select the Lab1 out sdc file and click Open Click Add and then OK in the Settings window settings Lab Category General Files Libraries Select the design Files you want to include in the project Click Add All to add all design files in the LL Dens project directory ta the project F F jr Fitter Setting Operating Settings and Conditions Compilation Process Settings Filename Lab1 out sdc E Add Early Timing Estimate Incremental Compilation Filename Type Library Design entry sy HDL version Add all Physical Synthesis Optimizations Labi out sde Spnopsys De None gt l EDA Tool Settings Labl vhd WHOL File None gt Hen Analysis amp Synthesis Settings Muss3xl qip IP Variation File None gt n Musas vhd WHOL File Moner 12 Compile your design by clicking the Start Compilation button on the toolbar ai 13 Click the Critical Warning tab in the Messages window to see that the timing requirements have not been met This is because of the long input and output delays specified 14 Expand the TimeQuest Timing Analyzer category in the Compilation Report and note that the 1 15 Slow Model Fast Model and Multicorner Timing Analysis Summary reports are in red indicating
87. e command on the Processing menu to run an early timing estimate Y ou can specify settings for the early timing estimate in the Use Netlist Viewers to view your design schematic Settings dialog box when a project is open Software Options Open Settings dialog box Early Timing Estimate page 42 Generate Compact Report Table Format 42 Additional report File options 42 Run Process at Lower Priority 2 MAX PLUS II Look and Feel 42 Add Tcl commands to toolbar buttons 42 Update assignments to disk immediately lt 2 Suppress Messages 42 Color messages during command line compilation 4 Use an External Text Editor 42 Change the Tooltip Delay 42 Project Settings Enable Version Compatible Database 42 Hide Entity Name 42 Specify the output directory For compilation results 42 Specify what is done during a normal compilation 42 Choose how the Fitter will process your design 42 Use Physical Synthesis to improve performance 42 Use Synthesis Netlist Optimizations to improve perfi 42 Use the Design Assistant to check For errors Provides useful instructions on using the Quartus Il software amp links to settings Available sections include New features in current release Helpful features and project settings available to designers For Help press F1 18 3 Quartus Il Help Version 10 0 Mozilla Firefox File Edit wiew History Bookmarks Help o PNG Messages Glossary Megafunctions LPM Devices and A
88. e simulation by clicking the Start Simulation button 5 on the Toolbar Click OK once the simulator has completed 2 14 11 The output waveforms for Cout and Sum should look similar to the screen capture below Master Time Bar 1 Pointer U ps Interval ps Start T pz End 500 0 ng 160 0 ng 240 0 ng 320 0 ns 400 0 ns 460 0 ns Value at ps pz m us qp er X B E b dx bod EL Ro gu Sel UO Sum UO O A dU ISASA 2 ATARI A415 AMIA 0 Cout BU When Sel is low A is added to B and the result is displayed as the value of Sum When Sel is high B is subtracted from A and Sum is the result 12 Change the simulation mode to Timing by selecting Assignments gt Settings to open the Settings window Click the Simulator Settings heading and set Simulation Mode to Timing 13 Click the Start Simulation button and observe the change in the output waveforms for Cout and Sum In Timing mode the simulator uses estimated or actual timing information to test the logical operation and the timing of your design Master Time Bar ps 1 Porter 35 79 ne Interval 35 79 ns Start End 160 0 ng 440 0 ng 320 0 ng 400 0 ng 450 0 hi EIER 000 4 6 2 RIZR EB ER Cle ae 0 Task 4 Implementing the Design on the DE2 Board 1 From the Menu Bar select Assignments gt Assignment Editor 2 From the drop down menu at the top for Category select Pin Category B e al Timing Logic Options
89. ed Inputs 1 Input output output 3 iInNpuUtO O imput fi input z2 INpuUtO 3 imputi 0 imputi i input 2 imputi 3 Input O inputzl 1 inpubz 2 inpubz 3 sel U sel 1 SOC command OF Help get ports finputO O inputi inputO inputO 3 input D input 1 input 2 inputi 3 inputz U inputz Cancel 7 Select Constraints gt Set Output Delay from the Menu Bar For Clock name select clk Make a Delay value of 20 ns 8 Click the ellipses to select the Targets Click List in the Matches field and select all of the output names Click the single right arrow to add it to the list of selected names and then click OK Click Run in the Set Input Delay window to create the output timing constraints set Output Delay Clock name clk Use falling clock edge Output delay options C Minimum f Masimum t Both Delay value Ei ng Add delay Targets llget parts foutput output 1 output output 3 E SOC command set output delay clock 1 clk 20 get ports output 0 autput 1 autpu Hun Cancel Help 9 Select Constraints gt Write SDC File from the Menu Bar to save the SDC file Click Save in the Save As dialog box 10 Close the TimeQuest Timing Analyzer 1 14 11 Add the SDC File to Your Project In the Quartus II window select Project gt Add Remove Files in Project from th
90. ed state is idle WHEN OTHERS gt next state lt idle END CASE END PROCESS Timer State Machine wee eee eee State Transitions Process Loads the next state onto the current state or resets the state to idle if the reset button is pressed State Transitions PROCESS reset clk BEGIN IF reset 0 THEN Current state lt idle ELSIF rising edge clk THEN current slave lt Next state END IF END PROCESS state transitions cree eee Output Process Process n e rocess is what controls the LED the outputs as seen user ocess PROCESS current State CK Two 16 bit countdown counters to create a delay for the countdown state variable countdown count countdown count2 integer range 0 to 65535 A delay counter used to delay the incrementing of timing_count so that timing count is in milliseconds variable timing counter integer range 0 to 49999 16 bit binary value of the time count in milliseconds variable timing count std logic vector 15 DOWNTO 0 5 3 BEGIN IF rising edge clk THEN CASE current state 5 Reset everything in le WHEN idle DG lt OTHERS gt DR lt OTHERS gt elapsed time lt 0 timing count 0 timing counter countdown countl countdown count2 rm rm a Turn red LEDS on and begin countdown counter when countdown counter is done countdown done is high WHEN countdown gt LEDG lt OTHERS gt 0 LEDR lt OTHERS gt
91. ed to define external view of a model i e symbol ARCHITECTURE used to define the function of the model i e schematic PACKAGE Collection of information that can be referenced by VHDL models i e LIBRARY Consists of two parts PACKAGE declaration and PACKAGE body NTITY Declaration Port Declarations END ENTITY lt entity_name gt 1076 1993 version Analogy symbol lt entity_name gt can be any alpha numerical name Port declarations Used to describe the inputs and outputs i e pins Generic declarations Used to pass information into a model Close entity in one of 3 ways END ENTITY lt entity_name gt VHDL 93 and later END ENTITY VHDL 93 and later END All VHDL versions 51 8 29 2011 or Declarations TITY lt entity_name gt IS END ENTITY lt entity_name gt e Structure class object name mode type class what can be done to an object object name identifier name used to refer to object mode directional IN input OUT output INOUT bidirectional BUFFER output w internal feedback lt Type gt what can be contained in the object discussed later ARCHITECTURE alogy schematic Describes the functionality and timing of a model Must be associated with an ENTITY ENTITY can have multiple architectures ARCHITECTURE statements execute concurrently processes ARCHITECTURE styles Behavioral how des
92. equires another M simulation cycle or transition on a b IF lt condition1 gt THEN sequence of statement s ELSIF lt condition2 gt THEN sequence of statement s ELSE sequence of statement s END IF 8 29 2011 IBRARY IEEE USE IEEE STD_LOGIC_1164 ALL ENTITY simp_prc IS PORT a b IN STD LOGIC y OUT STD LOGIC END ENTITY simp prc ARCHITECTURE logic OF simp prc IS SIGNAL c STD LOGIC BEGIN PROCESS a b END PROCESS END ARCHITECTURE logic IF THEN Statements E Example PROCESS sela selb a b c BEGIN END PROCESS 67 8 29 2011 Statements Indicate behavior and express order Must be used inside explicit processes Sequential statements F THEN statement CASE statement Looping statements WAIT statements _ 7 Statements Similar to conditional signal assignment Implicit Process Explicit Process q lt a WHEN sela 1 ELSE PROCESS sela selb a b c b WHEN selb 1 ELSE BEGIN END PROCESS 68 8 29 2011 m Example CASE expression IS PROCESS sel a b c d WHEN lt condition1 gt gt BEGIN sequence of statements WHEN lt condition2 gt gt sequence of statements WHEN OTHERS gt optional sequence of statements END CASE END PROCESS CASE Statement Similar to selected signal assignment Implicit Process Explicit Process WITH sel SELECT PROCESS sel a b c d q lt
93. et clocks clk fz get ports tinputi1 1 TZ set input delay add delay clock get clocks iclk x get ports trinputi z 73 set input delay add delay clock get clocks iclki m get ports tinputi 3 74 set input delay add delay clock get clocks clk z get ports rinputz U0 5 set input delay add delay clock get clocks iclki En get ports tinputz 1 T6 set input delay add delay clock get clocks clk fz get ports finpute 2 i Te set input delay add delay clock get clocks clk rx get ports tinputz 3 To set input delay add delay clock get clocks clki z get ports sel 0 vg set input delay add delay clock get clocks iclk ae get ports isel i oo ol nz E S222 2222222222222 22222222 22222 a 222 2a a EL EE a3 Set Output Delay aq HERR HET a a a HT EEE EEE HH RR EE EEE EEE SE oo ab set output delay add delay clock get clocks iclk get ports ioutput U of set output delay add delay clock get clocks iclk get ports ioutput 1 ag set output delay add delay clock get clocks iclk get ports ioutput z eg set output delay add delay clock get clocks iclk get ports ioutput 3 Save the Lab1 out sdc file by clicking on the Save button on the Menu Bar ul 17 Compile the design again by clicking the Start Compilation button on the toolbar and check the TimeQuest Timing Analyzer reports again to see that the design has now passed the timing analysis Ignore any
94. f data for input2 The output of the multiplexer is displayed on the first four green LEDs located above the blue push buttons on the DE2 board Their pattern will correspond to the four bits of the selected data stream Lab 2 Introduction to VHDL Lab 2 Introduction to VHDL In this lab you will design test and simulate a basic logic circuit using the Quartus II development software The circuit you will create is a ripple carry four bit adder subtractor using both behavioral and structural VHDL coding Below is a schematic diagram of the complete circuit The component make up includes four full adders and four XOR logic gates The inputs are two four bit numbers A and B and an add subtract selection input Sel The outputs are four bit sum Sum and a carry out output Cout B Bi 3 Sel FullAdders FullAdder FullAdder FullAdder Sum Sum aN Sum Sum C Below is a detailed diagram of the full adder circuit used It consists of three two input AND gates two XOR gates and one three input OR gate The individual gates will be coded separately using behavioral style VHDL and then stitched together using structural style VHDL to create the full adder E C Sum B E AND2 0 Cin AND2 0 out Cout i F AND2 1 AND2 2 2 1 Task 1 Create a New Project 1 Start the Quartus II software From the Windows Start Menu select All Programs gt Other Apps gt Altera gt
95. fa JTAG accessible Extensions mm Memory Compiler p Storage IP MegaStore Which device Family will you be Cyclone ll using Which type of output File do you want to create C AHOL f VHDL Yerlog HDL What name do you want for the output file Browse H ltera_TraininghLabs4Lab Nux Return to this page for another create operation Mate To compile a project successful in the Quartus software pour design files must be in the project directory in the global user libraries specified in the Options dialog box Tools menu ar a user library specified in the User Libraries page of the Settings dialog bos Assignments menu Y aur curent user library directores are Cancel lt Back Next gt 5 Select 3 for the number of data inputs from the drop down box Select 4 bits for the width ofthe data input and result output buses from the drop down box Under Do you want to pipeline the multiplexer Select Yes and set the output latency to 1 clock cycle Click Next MegaWizard Plug In Manager LPM_MUX page 3 of 5 Parameter zi Settings Currently selected device Family Cyclone II Match projectidefault S datalx 3 0 e um How many data inputs do you want 3 ww Len 0 How wide should the data input and EN the result output buses be bits Do vou want to pipeline the multiplexer i Mo Yes I want an output latency of Clack cycles cote an RT Sear input
96. ge 1 of 1 x Find Find v List Look in pipemult d Options Include subentities Find result I Find in NEE 1 ay data a 7 OS E w m datab 7 0 T n E an n addr ss 4 D wren Netlist Navigator Bm x rdaddress 4 DES B pipemult wr ad dr es s 4 D 5529 Instances mi Dr rego H EJ mult mult inst ram ram inst IF Primitives E gt Pins T Nets Schematic view Selects objects and text 10095 00 00 03 62 mierarcay d Derform elaboration first e g Analysis amp Elaboration OR Analysis amp Synthesis 31 8 29 2011 Schematic View RTL Viewer Represents design using logic blocks amp nets O pins Registers Muxes Gates AND OR etc Operators adders multipliers etc Place pointer over any element in schematic to see details Name Internal resource count Compilation Summary Compilation includes synthesis amp fitting e Compilation Report contains detailed information on compilation results Use Quartus II software tools to understand how design was processed RTL Viewer Technology Map Viewers State Machine Viewer Chip Planner Resource Property Editors 32 8 29 2011 ynthesis amp Fitting Control Controlled using two methods Settings Project wide switches Assignments Individual entity node controls Both accessed in Assig
97. gic elements in the logic arrays 150 18x18 bit embedded multipliers 250 M4K RAM blocks 622 I O element pins Four phased locked loops hat projects are FPGAs good for Aerospace amp Defense Radiation tolerant FPGAs along with intellectual property for image processing waveform generation and partial reconfiguration for SDRs Automotive Automotive silicon and IP solutions for gateway and driver assistance systems comfort convenience and in vehicle infotainment Broadcast Solutions enabling a vast array of broadcast chain tasks as video and audio finds its way from the studio to production and transmission and then to the consumer Consumer Cost effective solutions enabling next generation full featured consumer applications such as converged handsets digital flat panel displays information appliances home networking and residential set top boxes Industrial Scientific Medical Industry compliant solutions addressing market specific needs and challenges in industrial automation motor control and high end medical imaging Storage amp Server Data processing solutions for Network Attached Storage NAS Storage Area Network SAN servers storage appliances and more Wireless Communications RF base band connectivity transport and networking solutions for wireless equipment addressing standards such as WCDMA HSDPA WiMAX and others Wired Communications End to end solutions for the Reprogrammable Netw
98. gressive at supporting schools Pros Good software and hardware Cons have limited educational support material XUP Xilinx University Program xup xilinx com Only give away what they make or have signicant investment in Pros Give away hardware and software Cons Slow and not a positive donation 11 Altera DE2 Development Board USB USB USB Ethernet Blaster Device Host Mic Line Line Video VGAVideo 10 100M Pot Port Port in in Out In Port Pot RS 232 Port 9V DC Power Supply Connector 1 t 27 MHz Oscillator M t 1 24 bit Audio Codec lt PS 2 Keyboard Mouse Port VGA 10 bit DAC i Ethernet 10 100M Controller en 4 Expansion Header 2 JP2 Altera USB Blaster Controller Chipset a H r Altera EPCS16 Configuration Device re Power ON OFF Switch USB Host Slave Controller TV Decoder NTSC PAL ar Expansion Header 1 JP1 Altera Cyclone II FPGA RUN PROG Switch for JTAG AS Modes 16x2 LCD Module SD Card Slot e CE NER 5 Green LEDs 47 EO En 3 IrDA Transceiver Iziziainininininininininizininlcials 879 E SMA External Clock dh th d id oh d d bad dh dh es gh dd bas Lid had I Ti 4 7 Segment Displays 18 Red LEDs z 18 Toggle Switches j 4 Debounced Pushbutton Switches 50 MHz Oscillator 8 MB SDRAM 512 KB SRAM 4 MB Flash Memory What do you really need to start e Quartus Software e DE2 FPGA board 8 29 2011 12 Obta
99. he Add items to the Project window Type Lab4 in the Create Project File window and click OK m i Create Project File File Mame Lab Browse Add File as type Folder VHDL Tor Level Ok Cancel Click Close in the Add items to the Project window to close it 4 2 Cancel 5 Double click on Lab4 vhd in the project window of ModelSim to open an editor pane Copy and paste the following code into the editor pane Lab 4 Testbenching Testbench Code ieee std logic 1164 ALL ITY Lab4 IS HI TECTURE OMPONENT ctor 3 DOWNTO 0 ector 3 DOWNTO 0 ctor 3 DOWNTO 0 END COMPONENT SIGNAL A s B vector 3 DOWNTO 0 SIGNAL Sel s BEGIN CompToTest Lab2 PORT MAP As B s E Sum s Cout _ s PROCESS PROCESS Bs lt 0000 Sel s lt 0 lt 0001 Sel s lt 1 lt 0010 Sel s lt 0 Srsresaroa gt m II a END PROCESS END TBarch 6 Save the changes to Lab4 vhd by clicking the Save button on the toolbar Compile all the files by selecting Compile gt Compile All from the menu bar 4 3 Task 2 Simulating the Circuit 4 4 1 SelectSimulate gt Start Simulation from the menu bar to open the Start Simulation window Expand the work directory select lab4 and click OK 2 KA Start 5imulation Design VHDL Verilog Libraries SDF Others Name Tvpe Fame work Library HE gate_and2 Entity HE gate or3 Enti
100. he desired connections based on the schematic diagram of the adder subtractor circuit A SIGNAL declaration is used to define the connections that are internal to the circuit These signals carry the signal from one component to another 9 Create another new VHDL file following the directions in step 1 of task 2 10 Copy and paste the following code into your new VHDL file then save it by selecting File gt Save Name the file Lab2 and click Save in the Save As dialog box This is the Full Adder circuit written using Structural style VHDL Lab 2 Introduct on to VHDL Adder Subtractor Structural VHDL Code LIBRARY eee USE ieee std logic 1164 ALL ENTITY Lab2 A B s S PORT ctor 3 DOWNTO 0 3 DOWNTO 0 el U END Lab2 ARCHITECTURE AddSub struct OF Lab2 IS E END COMPONENT COMPONENT Full Adder PORT A IN st B IN std logi Cin IN std Sum OUT std Cout OUT st END COMPONENT SIGNAL XOR2 0 out XOR2 1 out XOR2 2 out XOR2 3 out std logic SIGNAL cl c2 c3 std logic Gate XOR2 PORT XOR2 0 out Gate XOR2 PORT XOR2 1 out Gate XOR2 PORT XOR2 2 out Gate XOR2 PORT XOR2 3 out 0 FullAdder XOR2 0 out iF XOR2 1 out XOR2 2 out XOR2 3 out I LI I LI I END AddSub struct 11 Compile the design by clicking the Start Compilation button on the Toolbar Task 3 Simulate Design using Quartus II 1 Create a Vector Waveform File vwf Click the New File icon on the Menu Bar i
101. hematic diagram to the previous one and you can See that the number of multipliers used has been reduced by one rezultz 23 D req EE ere suit2 23 0 result 1 23 0 9 Goto Lines 21 and 22 again and highlight both lines by clicking and dragging with the mouse Then click the Comment selected text button on the vertical Text Editor Menu Bar a Next highlight Lines 23 though 27 and click the Uncomment selected text button which is located below the Comment selected text button The section of code should now look similar to the image below 14 Mult Process PROCESS clk 15 BEGIN 16 GIF RISING EDGE clk THEN 17 w reg lt w 15 x reg lt x 19 y reg lt wv 20 z req lt amp a Bm resultl w reg Arte Frege aes lt eaults x reg v rEg E reg d temp w reg lt w reg 24 temp z reg lt z reg 25 temp xy reg lt x reg y reg 26 resulti lt temp w reg temp xy reg Y resulta lt temp xy reg temp z reg ad END IF ad END PROCESS The newly uncommented code uses temporary registers to increase clocking speed by pipelining 3 6 10 Save the changes to Lab3a vhd then compile the design again and view the results in the Compilation Report Ignore any warnings at this time abe Laba vhd Compilation Report Flow 5 e Compilation Report Sb E Legal Notice jes Flow Summary Flow Status Successful Wed May 25 09 10 56 2011 cim Lom
102. his lab will show how to write testbench files to test your circuit designs using the ModelSim software Task 1 Create a New Project 4 1 1 Start the ModelSim software From the Windows Start Menu select All Programs gt Altera gt ModelSim Altera 6 5b Quartus II 9 1 Starter Edition gt ModelSim Altera 6 5b Quartus II 9 1 Starter Edition 2 SelectFile gt New gt Projectto open the Create Project window For the Project Name type Lab4 For the Project Location type H Altera_Training Lab4 Then click OK Click OK again if you are asked to create the project directory w Create Pro ject Project Mame Lab4 Project Location IH filtera Training Lab4 Browse Default Library Mame Work Copy Settings From modelsim ase modelsim ini Browsa Copy Library Mappings Reference Library Mappings OK Cancel 3 Inthe Add items to the Project window click Add Existing File Click Browse on the Add file to Project window and browse to H Altera_Training Lab2 Select all ofthe vhd files and click open Select files to add to project Look in Lab2 do t Andz hd 3 fulladder vhd Lab hd la Desktop EY hy Documents hy Computer u My Network File name ande vhd tulladdervhd Lab vad Ors y v Places Files of type HEL Files v vL vhd vhdl vho hdi vo Y Then click OK in the Add file to Project window 4 Click Create New File in t
103. ic primitives Optimization to meet required area amp performance constraints Quartus II synthesis or 3 party synthesis tools Result Post synthesis netlist Place amp route Fitting Map primitives to specific locations inside Target technology with reference to area amp performance constraints Specify routing resources to be used Quartus II Fitter Result Post fit netlist Design Flow Timing analysis TimeQuest Timing Analyzer Verify performance specifications were met Static timing analysis Gate level simulation optional Simulation with timing delays taken into account Verify design will work in target technology PC board simulation amp test Simulate board design Program amp test device on board Use SignalTap II Logic Analyzer or other on chip tools for debugging 8 29 2011 22 8 29 2011 Quartus II Projects Description Collection of related design files amp libraries Must have a designated top level entity Target a single device Store settings in Quartus Il Settings File OSF Compiled netlist information stored in db folder in project directory Create new projects with New Project Wizard Can be created using Tcl scripts aE Edit View Project Assignments D Mew a E Start Project gt Open H Create Revision ia New Project wizard M Specify Project Libraries le Open Project Se ined Import Data
104. ichivaniech K constrained type e Synthesizable if base type is synthesizable e Use to make code more readable and flexible Place in package to use throughout design ARCHITECTURE logic OF subtype test IS SUBTYPE word IS std logic vector 31 DOWNTO 0 SIGNAL mem read mem write word SUBTYPE dec count IS INTEGER RANGE O TO 9 SIGNAL ones tens dec count BEGIN Data Type OWS user to create data type name and values Must create constant signal or variable of that type to use Usedin Making code more readable Finite state machines Enumerated type declaration TYPE your data type IS data type items or values separated by commas TYPE enum IS idle fill heat w wash drain SIGNAL dshwshr st enum drain led lt 1 WHEN dshwsher st drain ELSE 0 13 8 29 2011 Array Creates multi dimensional data type for storing values Must create constant signal or variable of that type Used to create memories and store simulation vectors array depth TYPE lt array_type_name gt IS ARRAY integer range OF data type Array type Declaration what can be stored in each array address y ASIII I
105. ign Files Tasks window AHDL File Task Block Diagram Schematic File E U Start Project EDIF File EE S State Machine File ISOIS SystemVerilog HDL File Sy Create Design da a Verilog HDL File EHI Open Existing Design File Memory Files l L Add Remove Files in Project Hexadecimal Intel Format File Dee Memory Initialization File Pe MegaWizard Plug In Manager IP cores and megafunctions Yerification Debugging Files In System Sources and Probes File Logic Analyzer Interface File SignalTap II Logic Analyzer File Other Files AHDL Include File Block Symbol File Chain Description File Synopsys Design Constraints File Text File Creating New Design Files amp Others 26 8 29 2011 MichiganTechws Design Entry Quartus II Text Editor features Block commenting Line numbering in HDL text files Bookmarks Syntax coloring Find replace text Find and highlight matching delimiters Function collapse expand Create amp edit sdc files for TimeQuest timing analyzer described later Preview editing of full design and construct HDL templates e Enter text description VHDL vhd vhdl Verilog v vlg Verilog vh SystemVerilog sv Verilog amp VHDL VHDL VHSIC hardware description language EEE Std 1076 1987 amp 1993 supported Partial IEEE Std 1076 2008 support EEE Std 1076 3 1997 synthesis packages supported Verilog EEE Std 1364 1995 amp 2001
106. igns operate RTL designs are described in terms of registers Functional no timing Structural netlist Gate component level Hybrid mixture of the two styles End architecture with END ARCHITECTURE architecture name gt VHDL 93 amp later END ARCHITECTURE VHDL 93 amp later END All VHDL versions 52 8 29 2011 ITECTURE lt identifier gt OF lt entity_identifier gt IS ARCHITECTURE declaration section list does not include all SIGNAL temp INTEGER 1 signal declarations with optional default values CONSTANT load boolean true constant declarations Type declarations discussed later Component declarations discussed later Subprogram declarations discussed later Subprogram body discussed later Subtype declarations Attribute declarations Attribute specifications BEGIN PROCESS statements Concurrent procedural calls Concurrent signal assignment Component instantiation statements Generate statements END ARCHITECTURE lt architecture_identifier gt Modeling Structure ENTITY entity_name IS port declarations END ENTITY entity_name ARCHITECTURE arch_name OF entity_name IS internal signal declarations enumerated data type declarations component declarations BEGIN signal assignment statements PROCESS statements component instantiations END ARCHITECTURE arch_name 53 8 29 2011 Putting It All pU Together PORT a b sel IN
107. il the equivalent of 40 ns passes in simulation time WAIT UNTIL clk 0 a lt 0010 b lt 0011 WAIT FOR 40 NS IF sum 5 THEN error TRUE END IF E Pause execution of the WAIT process indefinitely END PROCESS stim wo Types of RTL Process Statements zombinatorial process Sensitive to all inputs read by the process Example a PROCESS a b sel b PROCESS ALL VHDL 2008 2 Sensitivity list includes all inputs used by the combinatorial logic Sequential process Sensitive to select inputs clock and asynchronous control signals Example PROCESS clr clk Sensitivity list does not include the d input only the clock or and control signals 71 8 29 2011 USE IEEE STD_LOGIC_1164 ALL ENTITY dff1 IS PORT d IN STD_LOGIC clk IN STD_LOGIC q OUT STD LOGIC END ENTITY dff1 ARCHITECTURE logic OF dff1 IS cIK EVENT AND clk 1 re clk clk is the signal name any name BEGIN EVENT is a VHDL attribute IF clk EVENT AND clk 1 THEN specifying that there needs END Mn To be a change in signal value END PROCESS clkz 1 means positive edge END ARCHITECTURE behavior triggered VHDL has built in data types to model hardware e g BIT BOOLEAN STD LOGIC VHDL also allows creation of brand new types for declaring objects i e constants signals variables Subtype Enumerated Data Type Array 12 8 29 2011 M
108. in sequential behavior PORT il i0 IN std logic Referred to as inferred latch n cM OUr ee Logic END Dcd2x4 Wrong 2x4 decoder example Hasmemory up Beh OF Dcd2x4 IS Nocompiler error PROCESS il i0 Missing assignments to BEGIN o uror aee ogar outputs d2 d1 dO IF il 0 AND i0 0 THEN d3 2 0 CA lt 707 di uou do zu ili0 10 gt d2 1 ELSIF il 0 AND i0 1 THEN others 0 d3 ga Ots cA lt ug ili0 11 gt d3 1 di lt 1 d0 lt 0 but d2 stays same ELSIF il 1 AND i0 0 THEN d3i lt 0n Rd cu di lt 0 dO lt 0 ELSIF il 1 AND i0 1 THEN doie E END IF Note missing assignments to all outputs in last ELSIF END PROCESS END Beh 92 Bitfall often occurs due to not 8 29 2011 Common Pitfall Output not Assigned on Every Pass considering all possible input combinations PROCESS il i0 BEGIN IF il 0 AND i0 0 THEN d2 lt Y Te dO lt Y le AND i0 1 THEN d2 1z s dO 13 Te AND i0 2 Cw lt d0 lt 0 END PROCESS THEN Te Last ELSE missing so not all input combinations are covered 1 e 1110211 not covered no update to the outputs Mutually Exclusive IF ELSE Latches Beware of building unnecessary dependencies e g Outputs x y z are mutually exclusive IF ELSIF causes all outputs to be dependant on all tests amp creates latches PROCESS sel a b c BEGIN IF sel O10
109. ining licensing and service contract with Altera f you decide to go with Altera we can help you with currently available resources Register with AUP Get software Quartus Software Quratus is the software used to make the project we are going to complete We will cover this package more in the next slides and during the practical exercise 8 29 2011 13 8 29 2011 Quartus II Software Design Series Foundation Objectives Create a new Quartus II project Choose supported design entry methods Compile a design into an FPGA Locate resulting compilation information Create design constraints assignments amp settings Manage I O assignments Perform timing analysis amp obtain results 14 8 29 2011 AND S RIAN A Complete Solutior RT MAK Croton dirota BB ee CPLDs Low cost FPGAs High density Mid range Transceiver ASICs high performance FPGAS FPGAs Nios Il Quartus Il Software CUAKTUS II Two Editions L amp amp RUAK TUS H CRUAR MUS 93 Subscription Edition Web Edition Devices Supported All Selected Devices Features 100 95 Distribution Internet amp DVD Internet amp DVD Price Paid Free no license required Feature Comparison available on Altera web site 15 8 29 2011 Quartus Il Design Software Fully integrated development tool Multiple design entry methods Logic synthesis Place amp route Timing amp power a
110. ion value tae 6 Click A in the Name column and press Ctrl Alt B to open the Arbitrary Value window End 40 ns for the Start time and 160 ns for the End time Enter 10 for the Numeric or named value Arbitrary Value Time range Start time M0 ns End time 1 bl ns Arbitrary value Radix Unsigned Decimal Numeric or named value HB o e Cancel Repeat this process for A to assign a value of 7 from 160 ns to 310 ns Assign B the value of 5 from 100 ns to 230 ns and a value of 2 from 230 ns to 390 ns 2 12 2 13 On the waveform row for Sel click and drag to highlight the waveform from 130 ns to 200 ns Press Ctrl Alt 1 to assign this section of the waveform a value of 1 Repeat this process for the value of Sel from 270 ns to 350 ns Master Time Bar Ops H d Pointer 174 88 ns Interval 174 88 ns Start 130 0ns Enc 200 0 ne a He 160 0 ns 2400 ns 3200 ns 400 0 Hs 480 0 a Value at Ups After completing the signal assignments the waveform graph should look similar to the image below Master Time Bar Ip a Pointer Ops Interval O ps Stark End an n ns 160 0 ns 240 0 ns 200 ns 400 0 ns 480 0 nz Leave Sum with a value of undefined X as values for this will be generated when the simulation runs Click the Save icon ic on the Menu bar and save the vwf file with the filename Lab2 vwf 7 From the Toolbar select Assignments gt Settings to open the Settings
111. ircuit reprogrammability feature provides a more than just a standard gate array FPGAs have gained rapid acceptance and growth over the past decade because they can be applied to a very wide range of applications random logic Custom computing machine device controllers communication encoding and filtering programmable logic becomes the dominant form of digital logic design and implementation 8 29 2011 FPGA design flow Design Flow is the step by step methodology to go through the process of FPGA design The design flow can be divided into 6 basic steps Design Entry Functional Verification and Simulation FPGA Synthesis FPGA Place amp Route Circuit Analysis Timing Power Programming FPGA devices FPGA Design Flow l Analysis Path Implementation Path 8 29 2011 Description of Design steps Design Entry describes the design that has to be implemented onto FPGA Functional Verification and Simulation checks logical correctness of design FPGA synthesis converts design entry into actual gates blocks needed FPGA Place amp Route selects the optimal position and minimizes length of interconnections on device Time Analysis determines the speed of the circuit which has been completely placed and routed Programming to FPGA downloads bitstream codes onto FPGA devices Cyclone II FPGA Architecture Cyclone II EP2C20 Device Block Diagram The Cyclone II FPGA has up to 68 416 lo
112. ive ENTITY Entity entity even EnTiTy all mean the same Architecture Modeling Signals Fundamentals Signal Assignments Operators Processes Variables Sequential Statements Subprograms Types 08 8 29 2011 onstants Associates value to name Constant declaration Can be declared in ENTITY ARCHITECTURE or PACKAGE annot be changed by executing code Remember generics are constants parameters that can be overwritten by passing new values into the entity at compile time not during code execution Improves code readability Increases code flexibility Signals ignals represent physical interconnect wire that communicate between processes functions PROCESS PROCESS Functional Functional Block Signal declaration Can be declared in PACKAGE ENTITY and ARCHITECTURE 59 8 29 2011 Ssigning Values to Signals SIGNAL temp STD LOGIC VECTOR 7 DOWNTO 0 Signal assignments are represented by lt Examples All bits temp lt 10101010 temp lt x aa 1076 1993 VHDL also supports o for octal and b for binary Bit slicing temp 7 DOWNTO 4 lt 1010 Single bit temp 7 lt 1 e Use double quotes to assign multi bit values and single quotes to assign single bit values 119 2 implied processes gt Parenthesis give the order of operation E Expressions use VHDL operators to describe behavio
113. k 18 Toggle Switches S M WEIN IL 1I a NT i uk z 7 4 Debounced Pushbutton Switches 50 MHz Oscillator 8 MB SDRAM 512 KB SRAM 4 MB Flash Memory Image Source DE2 Development and Education Board User Manual version 1 42 Altera Corperation 2008 u 1 17 2 In the Quartus II window click the Programmer button on the Toolbar to open the Programmer window a The Hardware Setup must be USB Blaster USB 0 If not click the Hardware Setup button and select USB Blaster USB 0 from the drop down menu for Currently selected hardware Mode should be set to JTAG Make sure that the File is Lab1 sof Device is EP2C35F672 and the Program Configure box is checked ju Quartus II H Altera_Training Labs Lab1 Lab1 Lab1 Lab1 cdf File Edit Processing Tools Window EN Hardware Setup LISB Blaster USB 0 Enable real time ISP to allow background programming for MS Il devices pelt Start n Auto Detect Ga Add File G Add Device gus For Help press F1 1 18 Then click the Start button to program the DE2 board When the progress bar reaches 10096 programming is complete You can now test the program on the DEZ board by using the toggle switches located along the bottom of the board SWO and SW1 are the selector inputs to the multiplexer SW4 through SW7 are the four bits of data for inputO SW9 through SW11 are the four bits of data for input1 SW13 through SW17 are the four bits o
114. language and programmable logic design Curriculum has not yet caught up to industry needs industry must be driving the curriculum development Research Background Respond to the Market needs of Skilled FPGA Engineers Historically electrical engineering technology Associate and Baccalaureate programs have included a traditional logic design course These topics are far from most current industry practice in logic design EET two year and four year programs must teach digital logic using VHDL and FPGA 3 and students must be equipped with design skills that are current relevant and widely used in industry The major objectives of this curriculum shift are to give technology students at Michigan Technological and College of Lake County the opportunity to learn and experience logic design using FPGA 8 29 2011 D s g 4 4 N VO Block a gt s able Programmable Programmable Interconnect DD gg no O DO oo oo DD Introduced by Xilinx in mid 1980 for implementing digital logic F ield P rogrammable G ate A rray FPGA Can be visualized as a set of programmable logic blocks embedded in programmable interconnect Interconnect architecture provides the connectivity between logic blocks Programming Technology determines the method of storing configuration PGA Re programmable Logic Applications When FPGA first introduced it was considered as another form of gate array SRAM FPGA in c
115. ll use ieee std logic unsigned all entity fractal is port i resetn in std_logic Window menu gt Detach Attach Window Perform all project tasks Focus on compilation tasks Tasks X Tasks ax Flow Full Design v Flow Compilation v Start Project i Open New Project Wizard amp Open Existing Project C Advisors C Create Design C Assign Constraints Compile Design mE gc TI Export Database 7 Archive Project Compile Design gt Analysis amp Synthesis M Fitter Place amp Route H Assembler Generate programming files Early Timing Estimate 4 Classic Timing Analysis NC 4 HI EDA Netist Writer Faster compile iterations N Program Device Open Programmer Tasks Flow Early Timing Estimate with Synthesis v v E P Analysis amp Synthesis iu M Partition Merge E p Early Timing Estimate with Synthesis Double click any v E M Fitter Place amp Route 00 00 25 task to run v E M TimeQuest Timing Analysis 00 00 11 N Program Device Open Programmer 8 29 2011 20 stomize the Tasks display e Add Tcl scripts for quick access Tasks ax Flow Early Timing Estimate with Synthesis vi Compilation Early Timing Estimate with Synthesis of Full Design My Design Flow lt lt New Flow gt gt P Edit Flow Select tasks to include in the custom flow Custom flow My Design Flow ivi Open New Project wizard vig Open Existing Project O
116. m Lab 2 Introduction to VHDL Day 2 9 00 am Lab 3 VHDL Testbench Lab 10 00 am Advanced VHDL 11 00 am Lab 4 Advanced VHDL 1 00 pm Final Project using DE2 3 00 pm Support System Software hardware 3 30 pm Implementation Adaption Plan Issues at schools 4 00 pm Conclusions Feedback Survey 8 29 2011 Introductions Your Name Your Affiliations Experience with VHDL and FPGA Your intended learning goals Pre test Pre Survey Workshop Goals Participants will Be able to identify the importance of teaching engineering technology students relevant skills in hardware modeling and FPGA design Demonstrate the understanding of the fundamental concepts of hardware description languages and gain knowledge on programmable logic devices PLD Gain hands on expertise on the hardware and software necessary to establish a re configurable lab at their respective institutions Gain hands on lab experience by practicing modeling basic building blocks of digital systems and learn the FPGA design flow Develop potential curricular resources to be used at their respective institutions 8 29 2011 8 29 2011 Introduction FPGA based re programmable logic design became more attractive as a design medium during the last decade only 19 5 of 4 year and 16 5 of 2 year electrical and computer engineering technology programs at US academic institutions currently have a curriculum component in hardware description
117. m the Getting Started window Select one of the following tutorial modules Module 1 Quartus Il Introduction 5 minutes Module 2 Create a Design 30 minutes Module 3 Compile a Design 40 minutes Module 4 Run Timing Analysis 40 minutes Module 5 Run Timing Simulation 30 minutes Module 6 Configure a Device 20 minutes Ei Module 7 Incremental Compilation 40 minutes 8 29 2011 19 Quartus II File Edit View my Edit Windows C ee Text Editor C altera trn Quartus I Software Design Series Verification QllV9 1 Ex2 fractal frac EIER View Project Processing Tools Window Dc ugs tT EEE e AMES S a Project Navigator Entity AY Stratix II EPA 8558 fractal af Hierarchy Tasks Flow Ful Design Task H C std cy Cra El e Sepal z 7 ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS amp STRATIX Pat amp Tm Off and Altera marks in and outside the U S 411 infopmat i j i ovided on an as is basis Click again to re attach Module Name fractal File Name fractal vhd Module Function This file contains the top level module for Lab 2 REVISION HISTORY Revision 1 0 09 22 2009 Initial release B o o o o KK KKK KKK EKER KEE KEKE KKK ETEK KEK KKK HEHEHE KEKE KEK KEE EKER a library ieee use ieee std logic 1164 all use ieee numeric std ALL use ieee std logic arith a
118. nalysis Simulation ModelSim Altera Edition Device programming More Features MegaWizard Plug In Manager amp SOPC Builder design tools TimeQuest Timing Analyzer Incremental compilation feature PowerPlay Power Analyzer NativeLink 3 party EDA tool integration Debugging capabilities From HDL to device in system 32 amp 64 bit Windows amp Linux support Multi processor support Node locked amp network licensing options 16 P 34 8 29 2011 Welcome to the Quartus Il Software Getting Started With Quartus Il Software Start Designing Start Learning Designing with Quartus Il software The audio video interactive tutorial teaches requires a project you the basic features of Quartus Il software Turn on or off in Tools gt Options Open Recent Project top pipemult pipemult mult8x8 Quartus II Default Operating Environment E ani xj De it qae pot damgneani Cosa oou finde den Cl d Um eem us qe Cen HOS de mus OB cmi A PDs 1 35 ae FUIT M mL SC eee c poned OD the I O Ramsizrzmzt Marningm rwpcrt for detailm wee B weni Brit k adcriemm T Egg rp ox LESER DCERRTEZE JA Bene Ramage Set att Fil 17 8 29 2011 Dynamic menus as Compilation controls Pin Planner Chip Planner Compilation Report Quartus Il C altera rn Quartus_Il_Software_Design_Series_Verification ON 9_is fractal_150 File s ie Project Assignments Processing Tools Wind
119. nments menu or Tasks window Stored in OSF file for project revision Quartus II C altera trn Quartus Software Design Series Verif File Edit View Projec 4 Assignments p ocessing Tools Window Help D c E al 9 Device Project Navigator Settings Ctrl Shift E Session Constraints TimeQuest Timing Analyzer Wizard m Import Assignments Entity amp Assignment Editor CtrH Shift A Set Project and Compiler Settings diy Stratix III AUTO 2 Pin Planner Ctrl Shift N E Design Partitions Open Design Partition Planner H ian Fractal Remove Assignments RA Edit Pin Assignments Open Pin Planner i Back Annotate Assignments Ze Edit Logic Options Open Assignment E ditor Import Assignments i Export Assignments Export Assignments lt Assignment Time Groups Hierarchy Files a LogicLock Regions Window eg Ec Design Partitions Window T Settings Project wide switches that affect entire design Examples Device selection Synthesis optimization Fitter settings Physical synthesis Design Assistant Located in Settings dialog box Assignments menu Set Project and Compiler Settings task in Tasks window 33 8 29 2011 Device Settings en ee or D j a O g B OX Device Family Show in Available devices list Family Stratix III Package any all Pin count Any Devices Speed grade Any Show advanced devices Target device Auto device
120. ocess to either increment the counter or signal a state change SI GNAL sample std logic Maxi mum nu pulses needed to qualify as clean input CONSTANT PULS mb d input E integer 20 er of goo COUNT MAX Counter used to record the number of good in 2 d pulses SIGNAL counter integer range 0 to PULSE COUNT put MAX The KEY0 3 push buttons on the DE2 board are active low so sync is the nverse of the KEY3 push button s value SIGNAL sync std logic tcc cc cc cc ccccce Sampl eGen Process f A counter that sends a signal to sample the input button when the maximum count is reached Sampl eGen process clk Sample counter is a counter used to control the sample frequency sample frequency clock frequency sample counter max 1 variable sample counter integer range 0 to 24999 begin if rising edge clk then if reset 0 then sample lt 0 sample counter 0 else if sample counter 24999 then sample counter el sample N else sample gs sample counter Por counter 1 end if end if end if end process cc c cc c c ccc c cce Debounce Process n I A ccce A counter that is incrememnted every sample pulse while the input button is pressed when the switch is not pressed the counter is reset to zero If the counter is at its maxi mum the debouncer output is high otherwise its low Debounce process clk begin if rising edge clk then if reset 0 then
121. on of logic supported e Synthesis Code is interpreted amp hardware created Knowledge of PLD architecture is important Synthesis tools require certain coding to generate correct logic Subset of VHDL language supported Coding style is important for fast amp efficient logic Initialization controlled by device Logic implementation can be adjusted to support initialization Pre amp post synthesis logic should operate the same 86 8 29 2011 Writing Synthesizable VHDL Synthesizable VHDL Constructs Sensitivity lists Latches vs registers IF THEN ELSE structures CASE statements Variables ARCHITECTURE CONFIGURATION PACKAGE Concurrent signal assignments PROCESS SIGNAL VARIABLE non shared CONSTANT IF ELSE CASE Loops fixed iteration Multi dimensional arrays PORT GENERIC constant COMPONENT yynthesizabl VHDL Constructs Component amp direct instantiation GENERATE FUNCTION PROCEDURE ASSERT constant false WAIT one per process TYPE SUBTYPE Synthesis tools may place certain restrictions on supported constructs See the online help in Quartus Il or your target synthesis tool for a complete list 8 8 29 2011 Some Non Synthesizable VHDL Re Constructs These are some of the constructs ASSERT not supported by Quartus II DISCONNECT synthesis _ See the online help in Quartus Il FILE or your target synthesis tool for GROUP a complete li
122. opr The VHDL compiler can understand this operation because an arithmetic eig Zu OE opr IS operation is defined for the sum lt a b built in data type END ARCHITECTURE example INTEGER gt Note remember the library STD and the package STANDARD do not need to be referenced 122 61 8 29 2011 Conditional Signal Assignments Format m Example q lt a WHEN sela 1 ELSE b WHEN selb 1 ELSE C 2 Implied process Assignments mg Example WITH sel SELECT q lt a WHEN 00 b WHEN 01 c WHEN 10 d WHEN OTHERS gt Implied process 62 8 29 2011 All possible conditions must be considered WHEN OTHERS clause evaluates all other possible conditions that are not specifically stated See next slide gt Assignment D_LOGIC_1164 ALL ENTITY cmpl_sig IS PORT sel is of STD_LOGIC data type a b sel INSTD_LOGIC z OUT STD_LOGIC What are the values for a STD LOGIC data type ARCHITECTURE logic OF cmpl sig IS e Answer 0 T X Z BEGIN Selected signal assignment Therefore is the WHEN OTHERS clause necessary Answer YES END ENTITY cmpl_sig END ARCHITECTURE logic 63 8 29 2011 Signal Assignments The signal assignments execute in parallel and therefore the order we list the statements should not affect the ENTITY cmpl_sig is outcome PORT ENTITY a b sel INSTD_LOGIC x y z OUT STD LOGIC ARCHITECTU
123. orking Linecard Packet Processing Framer MAC serial backplanes and more Who uses them www fpgajobs com cese em 0l TUM 1 Se e fpgagcbs com ix j Ar Comen PP Select at Fevertes ae hd M ime Gen lentes hba 0 Bl Corpu ifcemunen by iB IPGA lob a om o Eiger ny Th Gr wy lc cc Featured Job Postings from the Web Jun 30 Principal Hardware Mercury Computer Chelmsford MA Lngineer IPGA Systems Prnapal Hardware Ingenser FPGA Locabon Chelmsford MA Last Updated 06 Description job Kesponub tbes FPGA deere w h 10 years expenence Senior Systems Logineer pcs Alexandria VA wate design Worked on US ARMY TACOM TARDEC advanced technology progr asprogr aes Expenence with FPGA CPLO designs and C C programmino is a Software SRA International Columbia MD Developer Engineer Talent Pool 1 5C1 FSP C Linux device drivers OSP Shell FPGA VHOCL Tools Developers keywords lava C Linux Window s Unux reverse engineenng DNI Shil FPGA ASIC Doveupment Carrlercomm Encinitas CA Engineer FPGA ASIC Development EngimeerCamerComm is seelong an FPGA ASIC developme ol modem and or network interface FPGA ASIC dessona Generate and e FPGA ASIC Verification Carriercomm Encinitas CA Lngineer CarerComes i seeking a PPGA ASIC ver cakion engineer to develop and exe of modem and or network interface FPOA
124. ourse was appropriate for the amount of material to be learned 5 4 3 2 1 All things taken into consideration considered the instruction to be excellent Additional comments regarding the teaching of this course or suggestions for improvement Advanced VHDL Design Technique Learning Objectives Circle One You learned to Strongly Strongly Agree Agree Neutral Disagree Disagree Write synthesizable VHDL 5 4 3 2 1 Control state machine implementation 5 4 3 2 1 Optimize a design using operator balancing resource sharing and pipelining 5 4 3 2 1 Create a test bench and run a simulation 5 4 3 2 1 Additional comments regarding the teaching of this material Quartus Il Software Design Series Foundation Learning Objectives Circle One You learned to Strongly Strongly Agree Agree Neutral Disagree Disagree Create a new Quartus II project 5 4 3 2 1 Create design components using MegaWizard manager 5 4 3 2 1 Compile a design and view results 5 4 3 2 1 Use settings and assignments to control results 5 4 3 2 1 Make pin assignments and evaluate 5 4 3 2 1 Use the TimeQuest timing analyzer 5 4 3 2 1 Additional comments regarding the teaching of this material
125. ow Help Deka amp X 56 o conata 150 LP e SVS Dr Fm seo Project Navigator Bx e frackal vhd 8 a TS Imm v BAT EE AAAA 0T Mx SERE ALTERA ARRIA CYCLONE HARDCOPY diy Stratix II EP2590H484C4 are Reg U S Pat amp Tm Off an amp Bo fractal sa All informatig TEGACORE NIOS QUARTUS amp SA a marks in and outside the d on an as is basis TimeQuest timing analyzer To reset views 1 Tools gt Customize Toolbars Reset All 2 Restart Quartus II Main Toolbar ips amp Tricks AAVISOr f Quartus Il Tips amp Tricks Help menu gt Tips amp Tricks File Edit Tools Window Tips amp Tricks Get an Early Timing Estimate 42 What s New in this Release 42 Quartus II Features J Detach windows From the Frame in the Quartus II s Description Recommendation You can get an early timing estimate without running a full compilation You can use the Start Early Timing Estimate command on the Processing menu to get a full timing report based on estimated delays for the design This command 42 Get advice on optimizing your design and the featur 4 amp 2 Use Incremental Compilation 42 Use SignalProbe to quickly pull out internal signals t 42 Use the PowerPlay Power Analyzer to check For pot can run the Fitter up to ten times faster than a full fit and produces estimated delays within 20 of what a full compilation can achieve Use the Start Early Timing Estimat
126. r 120 60 Operator Type Logical Relational Shifting 2 Addition amp Sign Arithmetic Concatenation Multiplication Miscellaneous exponentiation abs absolute value TA TY opr IS PORT 8 29 2011 Operators Operator Name Symbol NOT AND OR NAND NOR XOR XNOR Low lt lt gt SLL SRL SLA SRA ROL ROR P amp MOD REM ABS High 1 Not supported in VHDL 87 2 Supported in NUMERIC STD package for SIGNED UNSIGNED data types Arithmetic Function uc tet 5 SESS CESS EE END ENTITY
127. raining Lab5 Note After clicking Next a window may pop up stating that the chosen working directory does not exist Click Yes to create it Continue With the New Project Wizard using the same settings as before 2 Create a New File Create a new VHDL file as discussed previously Copy and paste the following code into your new vhdl file and save it as Lab5 vhd Lab 5 A VHDL Reaction Timer Reaction Timer Code 1164 all uns gned ALL clock signal from the DE2 board IN std logic KEY3 and KEYO on the DE2 board push button reset IN std logic f LEDS Out p L d logic vector 7 DOWNTO 0 uts for the LEDR LEDG OUT st t 7 segment dis outpu 13 TE OUT std logic vector 6 DOWNTO 0 ae p digitl digit2 di dy o END ARCHITECTURE Lab5 beh of Lab5 IS Type definition for the four states used for the state machine Type Ti mer State IS idle countdown timing score Signals of type Timer State used to control the state machine SIGNAL current state next state Timer State idle 16 bit binary value of the elapsed time in millise a nds SIGNAL elapsed time std logic vector 15 DOWNTO 0 THE Flag that indicates the status of the countdown SIGNAL countdown done std logic 0 5 1 Flag that Indicates a good Input signal and the desire to change states SIGNAL state change std logic 0 Sample pulse generated by the SampleGen process used by the Debounce pr
128. rent_state next_state state_type Use CASE statement to do the next state logic instead of IF THEN statement Synthesis tools recognize CASE statements for implementing state machines Use CASE or IF THEN ELSE for output logic Highlighting State in State Transition Table Highlights Corresponding State in State Flow Diagram State Transition Encoding Table Tranaionz A needing 100 ENTITY wm IS PORT clk reset door_closed full in std_logic heat_demand done empty in std_logic water spin heat pump out std_logic END ENTITY wm ARCHITECTURE behave OF wm IS TYPE state_type IS idle fill heat_w wash drain SIGNAL current_state next_state state_type BEGIN SS clk reset BEGIN IF reset 1 THEN current state lt idle ELSIF risting edge clk THEN current state lt next state END IF END PROCESS PROCESS current state door closed full heat demand done empty BEGIN next state lt curren CASE current state IS WHEN idle gt IF door closed 1 THEN next state lt WHEN gt IF full 1 THEN next_state lt heat_w Heat demand 0 Sequential state Heat demand 0 transitions Default next state is current state Combinatorial next state logic 8 29 2011 101 8 29 2011 Outputs Default output So water lt 0 conditions spin lt 05 Pd heat 05 pom pump lt 05 Pus CASE current state IS W
129. rly showing priorities f Statement ELSIF parts ensure correct priority of control inputs Rst has first priority then Ld then Shr and finally Shl Shift by assigning each bit Recall that statement order doesn t matter Use signal R for storage Can t use port Q because OUT port cannot be read by process Use concurrent signal assignment to update Q when R changes Equivalent to process R begin Q lt R end process Idea Create new Testbench entity that provides test vectors to component s inputs 8 29 2011 fReg4 IS I IN std_logic_vector 3 DOWNTO 0 Q OUT std logic vector 3 DOWNTO 0 Ld Shr Shl Shr in Shl in IN std logic Clk Rst IN std logic END MfReg4 ARCHITECTURE Beh OF MfReg4 IS SIGNAL R std logic vector 3 DOWNTO 0 BEGIN PROCESS Clk BEGIN IF Clk 1 AND Clk EVENT THEN IF Rst 1 THEN R lt 0000 ELSIF Ld 1 THEN R lt I ELSIF Shr 1 THEN R 3 lt Shr_in R 2 lt R 3 R 1 lt R 2 R 0 lt R 1 ELSIF Shl 1 THEN R 0 lt Shl_in R 1 lt R 0 R 2 lt R 1 R 3 lt R 2 eue uA Id shr shl END PROCESS Operation Maintain value Shit left Shift right Parallel load Q lt R END Beh AND Gate Simulation and Testbenches Testbench CompToTest And2 A testbench is a setup for applying test vectors to test a design The setup creates an entity called Testbench having no inputs or outputs
130. rte ing delay annotation 5 Ag Found 16 output pins without output pin load capacitance assignment Info Delay annotation completed successfully Info Design uses memory blocks Violating setup or hold times of memory block Ss registers for either read Warning The Reserve All Unused Pins setting has not been specified and will q Alt to As output driving grow Info Generated suppressed messages file C altera trn Quartus II Software Des Series_Foundation QIIF _2 5olw Info Quartus II Fitter was successful 0 errors 4 warnings Info LE AE TR TH N TR TR TR TR TR TH EE EE EE EE EE EE v gt 22 System 2 h Processing 103 Extra Info Info 94 Warning 9 Critical Warning Error Suppressed 5 resa Flag 2 Message 109 of 203 gt E 9 e zl P X NLINGO ompil ation Report uartus II C altera_trn Quartus_lI_Software_Design_ Series_Foundation OIIF9_0 Solutions Final_proje EIER File Edit View Tools Window S Compilation Report Flow Summary ae Window Detach Window to BEB Flow Settings release from Quartus II workspace g Flow Non Default Global Settings 2n don an Flow Status Successful Thu Mar 12 19 18 54 2009 amp Flow Log Quartus Il Version 3 0 Build 132 02 25 2009 SJ Full Version amp C3 Analysis amp Synthesis Revision Name pipemult Ic amp F summary Top level Entity Name pipemult eL Settings Family Cyclone Ill GOES Source Files Read Device EP3C5F256
131. s to the number of design components used and the clock speed Alternately the encoding type can be set by the Quartus II software by selecting Assignments gt Settings and then selecting the Analysis amp Synthesis heading and clicking the More Settings button to open the More Analysis amp Synthesis Settings window Then select State Machine Processing in the drop down menu for Name In the drop down menu for Setting select the desired state machine encoding then click OK in the More Analysis amp Synthesis Settings window and in the Settings window to save the changes More Analysis amp Synthesis Settings Specify the settings for the logic options in your project Assignments made to an individual node or entity in the Assignment Editor will override the option settings in this dialog box Option Reset Mame State Machine Processing Setting User Encoded m Reset All User Encoded Existing option settings Setting Add Pass Through Logic to Inferred HM On Allow Any RAM Size For Recognition Off Allow Any ROM Size For Recognition Off Allow Any Shift Register Size For Recognition Ot Allow Synchronous Control Signals On Analysis amp Synthesis Message Level Medium Auto Cary Chains n Auto Cock Enable Heplacement On Auto Gated Clack Conversion Lm Auto Open Drain Pins On Auto R b Replacement n Auto RAM to Logic Cell Conversion Off hi iba Feen rie Carina Lab 4 VHDL Testbenching Lab 4 VHDL Testbenching T
132. st NEW Physical delay types PROTECTED SHARED VARIABLE Signal assignment delays PROCESS Statements ymbinatorial PROCESS Sensitive to all signals used on right hand side of assignment statements Example PROt e Sequential PROCESS Sensitive to a clock and control signals Example PROCESS clr clk Sensitivity list does not include the d input only the clock or and control signals 88 8 29 2011 Incomplete sensitivity list in combinatorial PROCESS blocks may result in differences between RTL amp gate level simulations Synthesis tool synthesizes as if sensitivity list complete PROCESS a b ncorrect Way the simulated behavior is no y a AND b AND c hat of the synthesized 3 input AND gate PROCESS a b c Correct way for the intended AND logic y a AND b AND c Common Pitfall Missing Inputs from Sensitivity List list when LIBRARY ieee ribing combinational behavior j i USE ieee std_logic_1164 ALL Results in sequential behavior ENTITY Mux4 IS Wrong 4x1 mux example PORT i3 i2 il i0 IN std logic sl s0 IN std logic e Has memory d OUT std logic No compiler error Missing i3 i0 from gt Muxd Justnot amux seus Myers ARCHITECTURE Beh OF Mux4 IS BEGIN Recomputes d if sl Note missing i3 i2 il i0 or sO changes PROCESS sl s0 BEGIN Fails to recompute d if i3 IF sl 0 AND s0 0 THEN Reminder or i2 i0 changes ee Combination
133. std logic vector 15 DOWNTO 0 bin BEGIN for i in O to 15 loop bcd 19 downto 1 bcd 18 downto 0 bcd 0 bint 15 bint 15 downto 1 bint 14 downto 0 bint 0 0 if i lt 15 and bcd 3 downt bcd 3 downto 0 end if if i lt 15 and bcd 7 downto 4 gt 0100 then l g downto 4 bcd 7 downto 4 0011 en IT gt 0100 then 0 bcd 3 downto 0 0011 5 5 if i lt 15 and bcd 11 downto bcd 11 downto 8 bc end if if i lt 15 and bcd 15 downto 12 gt 0100 the seg ee downto 12 bcd 15 downto 12 end if if i lt 15 and bcd 19 downto 16 gt 0100 the bcd 19 downto 16 bcd 19 downto 16 end if END LOOP RETURN BCD END FUNCTI ON 8 gt 0100 then d 11 downto 8 0011 N Tou EL N 0011 BCD to 7 Seg Display Conversion Function FUNCTION BCD to 7Seg bcd std logic vector 3 DOWNTO 0 return std_logic_ Vecbor IS variable seg7 std logic vector 6 downto 0 others BEGIN CASE bcd IS WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN END CASE RETURN seg7 END FUNCTION c5c5c5c5co5co5coco TE CO Co r2 r3 r3 p3 C5 c5 c5 c5 T1 C5 C I L3 C5 C5 I3 r3 c5 c5 Ir C5 r3 OF OF c5 rn c co D CD D D D D D D CD OOM CO C2 CO C CO OO cO cO c c dc 44 4444 444 uH ugggggg gg a I CO C5 r3 C5 C5 c5 c5 c5 Ln Lr I CO C5 r3 C5 C5 c5 r3 r3 r3 c5 I I Or OF r3 I3 Or c5 I I CO r3 OOF OOF c5 I CO C5 C5 C5
134. t PROCESS filter BEGIN Undetermined output CASE filter IS conditions implies mm a sel missing Latch generated for WHEN tapl gt ALL 3 outputs sel lt 00 fee eec Us nxt missing WHEN tap2 gt sel lt 01 first lt 0 nxt missing WHEN tap3 gt an ae oe nxt amp first missing WHEN tap4 gt sel lt 11 END CASE END PROCESS output 95 Latches Removed Shs where output is determined Case Statements output PROCESS filter B l To remove latches amp ensure first lt 0 outputs are never undetermined is bu Use signal initialization at WHEN idle gt beginning of case statement WHEN tap1 gt case statement only deals with changes sal on Use dont cares for WHEN WHEN tap3 gt OTHERS clause if design sel lt 10 allows for better logic WHEN tap4 gt Be sel lt 11 optimization nxt lt 1 Manually set output in each case END CASE END PROCESS output Variables May synthesize to hardware depending on use Advantages vs signals Variables are a more behavioral construct as they don t have a direct correlation to hardware like signals and may lead to more efficient logic Simulate more efficiently as they require less memory Signals not updated immediately so simulator must store two values current and next value for every changing signal Variables updated immediately so simulator stores
135. t State Machine Viewer 2 Goto Assignments gt Settings and select Timing Analysis Settings Select Use TimeQuest Timing Analyzer during compilation under the Timing analysis processing heading Click OK to close the Settings window then compile the design again Settings Lab3 Category General Timing Analysis Settings Files E Libraries Specify whether to use the Timelluest Timing Analyzer or the Classic Timing Analyzer as the default E Device timing analysis tool The Timelduest Timing Analyzer requires a Synopsys Design Constraints File E ii perdin Senintiscand Conditions containing timing constraints or exceptions Compilation Process Settings H EDA Tool Settings r Timing analysis processing Analysis amp Synthesis Settings f Use TimeQuest Timing Analyzer during compilation 0 0 WHOL Input i Use Classic Timing Analyzer during compilation Verlag HOL Input Default Parameters z Fitter Settings ERT iming na eis 5 ettings 0 TimeQuest Timing Analyzer Classic Timing Analyzer Settings Classic Timing Analyzer Repo 3 10 3 Inthe Compilation Report Flow Summary note the number of Total logic elements and Dedicated logic registers used Then under the TimeQuest Timing Analyzer Summary select Slow Model and view the maximum clock frequency of the design abe Lab3b vhd Compilation Report 8 E Legal Notice PET
136. t the File is Lab2 sof Device is EP2C35F672 and the Program Configure box is checked Ml Quartus Il H Altera_Training Lab2 _ab Lab Lab2 cdf Bk x File Edit Processing Tools Window PL E d Mode JTAG Progress 0 Enable real time ISP ta allow background programming For MA II devices mwa e ee pa ee Bram Lab2 sal EP2L35FB 2 O02F 3031 FFFFFFFF de Auto Detect For Help press Fi Then click the Start button to program the DE2 board When the progress bar reaches 10096 programming is complete You can now test the program on the DE2 board by using the toggle switches located along the bottom of the board SWO is the add subtract selector Low is for addition SW9 through SW12 are the four bits of data for A SW13 through SW17 are the four bits of data for B The output of the operation is displayed on the first four green LEDs located above the blue push buttons on the DE2 board LEDG4 is the indicator for Cout Lab 3 Advanced VHDL Lab 3 Advanced VHDL This lab will demonstrate many advanced VHDL techniques and how they can be used to your advantage to create efficient VHDL code Topics include operator balancing resource sharing preventing unwanted latches and state machine encoding schemes Task 1 Create a New Project 1 Startthe New Project Wizard Create a new project using the same procedure from the previous labs Set the Working Directory Project Name and Top Level Design Entit
137. that they have failed the timing analysis Expanding each of the red submenus will show the failures in more detail TimeQuest Timing Analyzer 3 Summary PES Parallel Compilation EEE SDC File List EEE Clocks eb Slow Model 89 Fast Model SEE Multicorner Timing Analysis Summary 15 In the Files section of the Project Navigator double click on Lab1 out sdc to directly edit the SDC file Project Ma vigatar x abd Labi vhd A B Musx3e1 ip Habo Mug3xil vhd HO 16 Scroll down in the Lab1 out sdc file to find the Set Input Delay and Set Output Delay sections These should be starting on lines 63 and 83 for this example For each input line that reads similar to set_input_delay add_delay clock et ports inputO 0 Change the 20 000 ns delay to 2 000 ns Repeat this process for all the input and delays be E HL LL LL 22222222 2222222222222 ee ee LU 53 Set Input Delay 6 4 Honc kc e e E RR UR AEA S S CR C RN UU e S S S TATA EAA RU AEA n 65 66 set input delay add delay clock get clocks elk Poa get ports tinputD n ET set input delay add delay clock get clocks clk z get ports rinput 1 68 set input delay add delay clock get clocks iclki Er get ports finputoO e i 69 ser input delay add delay clock get clocks cl1k fz get ports finputO s i TO set input delay add delay clock get clocks iclki ae get ports finputli O i 71 set input delay add delay clock g
138. ty HE gate_xor Entity x HE lab Entity 3 lab4 Entity X HE Fulladder Entity Hi 220model Library Hi 220model ver Library In 1 wl A Path H Altera Training Lab4 work H Alrera Training Labz Ande had H Altera Training Lab2 ors vhd H Altera Training Labe or vhd H Altera Training Labz Labz hd H Altera Training Lab4JLab4 vhd H Altera Training Labz Fulladder vl MODEL TECH Jaleerafvhadllzz m t MODEL TECH alteralverilagrzzt E 31 gt Design Unitis Resolution work lab default m Optimization Enable optimization Optimization Options In the sim pane right click on lab4 and select Add gt To wave gt Allitems in region This adds the signals from the test bench file to the waveform so we can see their values when the simulation runs You may need to play around with the window sizing some in order to expand the waveform window to a reasonable size T ol My ge To List Copy To Lo Find Fenmand Salartar To Dataflow d All items in region q Ld All items in region and below All items in design 3 Change the simulation Run Length to 50 ns by typing it into the entry box on the toolbar s Then click the Run button Eu to start the simulation Press the minus key to zoom out to an appropriate size To zoom in press shift The resulting waveform should be similar to the image below Messages aon Bui
139. ually exclusive individual IF structures may be more efficient 90 8 29 2011 When Writing IF ELSE Structures Cover all cases Uncovered cases in combinatorial processes result in latches For efficiency consider Using don t cares or X for final ELSE clause avoiding unnecessary default conditions e Synthesis tool has freedom to encode don t cares for maximum optimization Assigning initial values and explicitly covering only those results different from initial values Unwanted Latches e Combinatorial processes that do not cover all possible input conditions generate latches PROCESS sel a b c sel 0 LOGIC BEGIN sel 1 LATCH sel 2 output IF sel 001 THEN S output lt a C ELSIF sel 010 THEN output lt b ELSIF sel 100 THEN output lt c END IF END PROCESS 91 8 29 2011 nwanted Latches Removed Close all IF ELSE structures If possible assign don t care s to else clause for improved logic optimization PROCESS sel a b c BEGIN IF sel 001 THEN output lt a ELSIF sel 010 THEN output lt b ELSIF sel 100 THEN output lt c ELSE output lt OTHERS gt X END IF END PROCESS all Output no Assigned on Every Pass LIBRARY ieee Ig to assign every output on every pass DES secet ces Nope Lac etr ough the process for combinational behavior E E TS ers Results
140. wer the following questions Your responses will be used to improve this course for future students Thank you in advance for your participation Mastery of Main Course Objectives Circle One Complete No Mastery Mastery Ability to implement basic constructs of VHDL 5 4 3 2 1 Ability to implement modeling structures of VHDL 5 4 3 2 1 Ability to use software tools to check the code for correctness and correct errors 5 4 3 2 1 Additional content topics you would have liked to have had covered Quality of Instruction Circle One Strongly Strongly Agree Agree Neutral Disagree Disagree The instruction was clearly presented 5 4 3 2 1 Any questions asked were properly answered 5 4 3 2 1 The materials provided helped me to learn 5 4 3 2 1 The pace of the course was appropriate for the amount of material to be learned 5 4 3 2 1 All things taken into consideration considered the instruction to be excellent Additional comments regarding the teaching of this course or suggestions for improvement Advanced VHDL Design Technique Learning Objectives Circle One You learned to Strongly Strongly Agree Agree Neutral Disagree Disagree Write synthesizable VHDL 5 4 3 2 1 Control state machine implementation 5 4 3 2 1 Optimize a design using operator balancing resource sharing and pipelining 5 4 3 2 1 Create a test bench and run a simulation 5 4 3 2 1 Additional comments regarding the teaching of this material Quartus
141. xamples EIER Compilation Process Settings Specify Compilation Process options Parallel compilation Use global parallel compilation setting Smart compilation Skips entire compiler modules when not required Saves compiler time Uses more disk space Generate version compatible database This option specifies YOM File nameTo LUMPMSLONT Sri Scart ven Ver eT c Use all available processors Maximum processors allowed Run Assembler during compilation C Run RTL Viewer preprocessing duri Save a node level netlist of the en TITTTGT TT File name C Export version compatible database Export directory Save project output files in specified directory Directory name More Settings Tcl set_global_assignment name SMART_RECOMPILE ON Physical Synthesis Optimize during synthesis or re synthesize based on Fitter output Spey ee Ur end ee ea S daro ported ad et Peoria ter s deii IX ES DIM EZ up be Lc irri Fn Coil o tor Makes incremental changes that u improve results for a given placement Compensates for routing delays from Fitter Apply globally Settings or only to bern tere Set borimo dare eee ee GANTT ee eee 1 Drs gim dng pete and rg ees e p coder ee rere Jia me dae per rt m CGT Wi rer Pr et gir T feira aia erregen r Peto epin pe enn Verr fo rg oni al n Ps or d Feia peru hen For brara ine Loge Sater
142. y as seen in the table below Working Directory H Altera_Training Lab3 Note After clicking Next a window may pop up stating that the chosen working directory does not exist Click Yes to create it Continue With the New Project Wizard using the same settings as before 2 Create a New File Create a new VHDL file as discussed previously Copy and paste the following code into your new vhdl file and save it as Lab3a vhd Lab 3a Advanced VHDL Resource Sharing Code LIBRARY i eee USE 186e 5td Logic 1164 all USE ieee std logic unsigned all ENTITY Lab3a IS PORT w X tor 7 DOWNTO 0 OUT std logic vector 23 DOWNTO 0 END ARCHITECTURE Lab3a arch OF Lab3a IS SIGNAL w reg x reg OWNTO 0 SIGNAL temp w reg t SIGNAL temp xy reg 1 1 1 I D DA A Dow gy N NA xX DO AHH r temp xy reg resultl lt t result2 lt t D IF y reg temp xy reg g temp z reg EN END PROCESS END Lab3a arch 3 1 Task 2 Operator Balancing and Resource Sharing 3 2 1 Compile that code as is using the Start Compilation button Ignore any warnings at this time 2 After compilation is complete observe the Flow Summary in the Compilation Report that has been generated Note the Total logic elements Total combinational functions Dedicated logic registers and Embedded Multiplier 9 bit elements used in this design abe Lab3a vhd Compilation Report Flow S

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