Module A9M9750_2 - Digi International
Contents
1. 26 230400 3 460800 qe 921600 0 fe ies Ei Be es 6 5 647 9600 95 323 371 23 1843200 N ZU CPUs using PLL on modules with 200MHz and 162 5MHz will use the values from column 1 allowing baud rates from 75 921600Bd A 125MHz CPU will have a PLL multiplier ND 17 resulting in a X1 SYS 4 clock source This module will use column 2 resulting in a baud rate from 75 460800Bd Column 3 or 4 is used when PLL bypassed or CPU clock never changes in the application 3 18 PC Bus Module A9M9750 2 This bus SCL SDA is connected on the module to a serial EEPROM with C interface on device address 0xA0 OxA1 Device address OxDO 0xD1 connects to an RTC on board All other addresses can be used externally Due to a timing bug in the PC state machine the maximum clock frequency in slow mode should be 50KHz and 200KHz in fast mode Otherwise minimum setup time for the target can be violated SDA changes after half low time of SCK instead of shortly after falling edge so setup time for data is 2 5us 100KHz and 612 5ns 400KHz Important Use only 3 3V devices 35 Module A9M9750 2 3 19 LCD Controller STN amp TFT An LCD interface for STN or TFT LCD s is provided with up to 24 data lines and 6 control lines Usage for LCD disables serial ports C D and most GPIOs The module provides the full LCD interface 24 data lines LCCD0 23 GPIO24 47 and 6 control2. Po PLL ND2 RTSA GPIO9 RXDA SPIA DI 5 AM a nr se SPIA DO emi E SPIB_EN KN E SPIB CLK GROS DSRB GPIO4 PLLNDO ye DTRB 13 Module A9M9750 2 rey eme Te eee n EEE ataa HE E AGRIO E CTSBH REE ERE RR TA GPIO1 RXDB SPIB DI GPIOO PLL FSO yes TXDB SPIB DO The GPIO configuration pins marked as protected are separated from the external connector pins with an analog switch when RESET active or their output signal is buffered So external signal connections cannot change the preset hardware configurations on the module or external configuration pins The switched port lines have 10K pull ups when open to prevent floating signals Switching time at the rising edge of PWRGOOD is delayed about 200ns configuration is latched 5 system crystal clock cycles after the rising edge of PWRGOOD in the CPU Using not protected pins for configuration purposes is possible if the major load is the configuration resistor RTCK is not connected to external and has no switching logic RSTOUT is generated from RESET DONE amp PWRGOOD So RESET DONE cannot be loaded externally Another three configuration pins on the CPU are used for internal tests from NetSilicon and to switch from normal mode to ARM JTAG debug or boundary scan mode Switching is done with the configuration pins DEBUG EN and OCD ENZ described in the next chapter PLLTST BISTEN SCANEN AF 21 AD20 AE21 ee e
3. e i HE d TXDC IRO3 LCDD16 GPI044 TXDD 1284 LCDD20 PER ONLIN E 1284 STRB LCDD21 1284 ALFD LCDD22 GPIO45 RXDD GPIO46 RTSD Module A9M9750 2 Port Alternate Alternate Alternate Alternate On Module Name Function Function Function 01 Function 02 default used Functio 00 UART 00 misc as n 03 default at power up GPIO47 CTSDH Oo 1284INIT LCDD23 GPIO48 Timer14 1284P SEL DMA1 REQ GPIO49 Timer 15 1284 DMA R B NAND P LOG DONE Flash 3 12 PCI CardBus Port All address data and control signals are provided to connect a PCI or CardBus interface compliant to PCI specification 2 1 and 2 2 protocol All module signals are not buffered clock buffering clock distribution and casually necessary buffers for other PCI signals have to be added on the application board If no internal PCI clock is used the PCI clock has to be generated externally too PCI CLKIN and PCI CLKOUT have series resistors populated with OR in the moment between CPU and connector these two signals can be shorted near the CPU optionally on the module Generation PCI clock see clock chapter Pull up resistors on the module are provided for PCI GNT1 3 PCI REQ1 3ff PCI INTA D PCI PERR PCI SERR PCI STOP PCI DEVSELf PCI IRDY PCI TRDY and PCI FRAMEH PCI CENTRAL RSC pin is default low internal pull down the internal PCI resources and the internal PCI arbiter of the NS975
4. CE TXDA SPI A RXDA SPI A 27 Module A9M9750 2 Port Alternate Alternate Alternate Alternate On Module Name Function Function Function 01 Function 02 default used Functio 00 UART 00 misc as n 03 default at power up GPIO10 RTSA Reserved Reserved RTSA GPIO11 CTSA KG IRQ2 dupe CTSA dupe GPIO12 DTRA Reserved Reserved GPIO12 il ak eger dupe as RTC_INT RXCLKA TXCLKA GPIO16 1284P JAM Timer 11 TSE Overcuren dupe dupe GPIO17 USE Reserved Reserved Power Rela GPIO18 Ethernet IRQ3 dupe CAM Reject GPIO19 Ethernet LCD HSYNC DMA1 ACK LCD iad la Reject GPIO20 DTRC LCDCLK Reserved LCD GPIO21 DSRC LCD Reserved LCD Ee e ame b RXCLKC BIAS D EN TXCLKC LINE END dupe GPIO24 DTRD LCDDO Reserved LCD 28 Module A9M9750 2 Port Alternate Alternate Alternate Alternate On Module Name Function Function Function 01 Function 02 default used Functio 00 UART 00 misc as n 03 default at power up oe LL dupe RXCLKD GPIO27 DCDD SPID EN LCDD3 Timer 4 LCD TXCLKD GPI028 DE Ext IRQ 1 LCDD4 ages R dupe GPIO29 LCDD5 LCDD9 dupe dupe dupe GPI032 EXTIRQ2 1284 DO LCDD8 GPIO33 1284 D1 LCDD9 TXDC GPIO41 RXDC I Timer11 LCDD17 GPIO42 RTSC I Timer12 LCDD18 GPIO43 CTSC I Timer13 LCDD19 Er mo ud po er i GPIO34 Timer9 1284D2 LCDD10
5. If both signals are true a delay of about 20 40ms starts Delay time is settable with a capacitor at U15 After this time output RES goes low and 3 3V IN are connected to 3 3V with the FET switch U18 with a ramp up time of lt 20ms Output RES goes high it is connected as PWREN to the external connector of the module The outputs of U16 change their state immediately when either 3 3V IN lt 3 0V or 1 5V lt 1 2V So the 3 3V on the module is switched off immediately and ramps down in a few ms 38 Module A9M9750 2 3 25 Voltage Supervision and RESET Generation Voltage supervision and RESET generation is done for 1 5V core and 3 3V I O voltage by a triple voltage supervisor with RESET TPS3307 18 External or manual RESET control is done by connecting RSTIN to ground The push pull RESET output with 470R series resistor is connected to the PWRGOOD signal 3 3V is supervised with SENSE1 and SENSE2 1 5V with SENSE3 MR is connected to RSTIN for manual RESET control An optional pull up 10K increases the current out of RSTIN to at least 330uA when connected to Gnd 39 Module A9M9750 2 4 Bootloader Every module is delivered with a bootloader UBOOT pre installed in NAND Flash The bootloader is capable of booting the Operating System from NAND Flash via a serial port or via Ethernet Parameters can be passed to the kernel from the bootloader Some requirements e Calculation of Baudrates Timer Values dep
6. Module A detailed pin description is available named Pin Description A9M9750 X pdf or doc 8 2 Pinning Module on A9MVali Validation Board This pinning is included in the specification of the validation board A9MVali X doc or pdf 8 3 Pinning Module on A9M9750DEV Development Board This pinning is included in the specification of the development board Spec Devkit A9M9750 A9M9360 X doc or pdf 47
7. SDRAM CLKOUTO feeds the SDRAM A 2 signal path with the same length as the connection between CPU and SDRAM is coupled to the feedback input SDRAM_CLKINO SDM CLKOUTO and SDM CLKINO are decoupled with a 22R resistor each The feedback inputs SDRAM CLK1 3 are grounded 20 Module A9M9750 2 3 7 Serial Boot EEPROM Boot SPI Channel Settings Connected to SPI channel B GPIOO gt SI GPIO1 gt SO GPIO6 gt SCK GPIO7 gt CS is a serial SPI EEPROM 8Kx8 containing initialization values and boot program It is loaded after end of RESET low into the SDRAM if configuration line RESET DONE is pulled low at the rising edge of RESET default on module The module has to be in little endian mode a CPU bug prevents booting via SPI EEPROM in big endian mode To allow external usage of the SPI channel after boot the SPI chip select is divided into an internal and an external SPI chip select Activation internal chip select SPIB INT while RESET DONE low activation external chip select SPI ENB with RESET DONE high 3 8 Chip Selects Memory Map NS9750 CPU provides 8 chip selects divided in 4 channels for dynamic RAMs and 4 static chip selects Every chip select has a 256MB range Below the whole memory map of the NS9750 chip Address Range Size Comments Mbyte SDM CSO0 0x00000000 0x0FFFFFFF SDRAM 1 bank on bank 0 a SDM CS1 0x10000000 0x1FFFFFFF SDM CS2 0x20000000 0x2FFFFFFF E SDM CS3 0x30000000 0x3FFFFFFF EXT
8. User defined software SCONF3 read Bit 31 configuration pin can be GEN_ID read in GEN ID register bit 31 default high 16 Module A9M9750 2 Recommended Combinations of DEBUG ENZ and OCD ENf BB MS 17 Module A9M9750 2 3 6 Clock Generation Different clocks will have to be generated for the module in the CPU 1 Input clock at X1 C8 29 4912 MHz with PLL multiplied to 398 1312 MHz 727 2 2 CPU clock 199 0656 MHz or 162 5 or 125 MHz depending on CPU version Multiplied input clock divided by 2 These frequencies are the default values set by strapping pins PLL Multiplier and divider vaues can be changed at runtime by software a 4ms RESET allows PLL to lock usage needs cold warmstart detection in the software 3 AHB clock 99 5328 MHz 81 25 62 5 MHz Multiplied input clock divided by 4 4 BBUS clock 49 7664 MHz 40 625 31 25 MHz Multiplied input clock divided by 8 5 PCI clock internally is fixed to input clock divided by 14 14 12 10 or 8 are strapping options For other frequencies an external clock source connected to PCI CLK IN AB24 has to be used 6 LCD clock by either dividing input clock by 4 8 16 or 32 or using an external clock source connected to LCDCLOCK J2 7 External clock CLKOUT NS9750 has no dedicated external clock pin CLKOUT3 from the memory controller is used to generate an external clock of half CPU clock 99 5328MHz or 81 25MHz or 62 5MHz This clo
9. the module on the base board Board to Board Module Connector X3 X4 Base Board Connector X3 X4 Distance h No of Qty Supplier Order No No Of Pins Supplier Order No Pins 5 mm 60 AMP 177984 2 Berg 61083 061009 60 2 AMP 177983 2 Berg 61082 061009 44 Module A9M9750 2 6 mm 7 mm 8 mm 60 AMP 179029 2 Berg 61083 062009 60 AMP 179030 2 Berg 61083 063009 60 AMP 179031 2 Berg 61083 064009 45 Module A9M9750 2 7 Known Faults and Limitations 7 1 USB Pins are not 5V tolerant As all pins of the NS9750 the USB data pins are not 5V tolerant To overcome this problem there is a protection circuit on the NetSilicon evaluation board Fix Adding protection circuit on the base board VALI DEV Realised on A9M9750 1 in the moment 7 2 Timing Bug in IIC Stage A timing bug reduces setup and hold times for IIC SDA signals to half low time of IIC SCK Workaround Use half maximum frequency i e 50KHz in slow mode and 200KHz in fast mode 7 3 PLL Clock Generation instable NS9750A1 CPU may produce frequency shifts on the memory clock if used at low temperatures and supply voltages at the upper limit Workaround feeding system and USB clock with oscillators eliminates this bug A9M9750 2 modules have oscillators for system and USB clock 46 Module A9M9750 2 8 Appendix 8 1 Pinning
10. to be made on the base board 48MHz USB clock is generated on the module with a 48MHz crystal in fundamental configuration 3 15 UART Channels Up to 4 UART channels with all handshake signals are provided channels A GP108 15 B GP100 7 C GPIO20 23 amp GPIO40 43 D GPIO24 27 amp GP1044 47 They can be used in asynchronous mode as UART Baud rates are supported up to 1 8MHz in asynchronous mode 3 16 SPI Channels SPI channel B GPIOO 1 6 7 is connected to the serial 8Kx8 SPI EEPROM U23 when RSTOUT asserted The EEPROM contains the boot program and the initial SDRAM parameters for booting via SPI Usage of this channel at runtime is provided by deconnecting the boot EEPROM with the deassertion of RSTOUT 31 Module A9M9750 2 using 4 switches The other SPI channels can be used free if not used in UART mode or blocked by other GPIO usage 3 17 Calculation of Baudrates Baud rate generators in the NS9750 have different clock sources selectable 1 X1 SYS OSC M It is the frequency of the input crystal divided by M M depends on the multiplier settings PLL ND of the PLL M 2 at PLL ND gt 19 decimal 14 7456MHz with 29 4912MHz crystal or M 4 at PLL ND lt 19 decimal 7 3728MHz Cannot be used with PLL bypassed 2 BCLK For 199 0656MHz CPU is BCLK 49 7668MHZ Only internal source when PLL bypassed 3 External receive clock from GPIO pins 4 External transmit clock from GPIO pins These values can
11. 0 active RTCK high This is the PCI host version PCI IDSEL is connected via series resistor on the module to PCI AD11 NS9750 must be PCI device0 The PCI IDSEL line of an external PCI Connector has to be connected to PCI AD signal gt 11 for example connected to PCI AD13 the connector is configured as PCI device 2 30 Module A9M9750 2 If external arbiter and no internal resources selected PCI CENTRAL RSC high and RTCK low no pull up resistors are populated PCI device version PCI IDSEL is controlled by the external host the series resistor on the module not populated 3 13 10 100Mbps Ethernet Port The module has a Mil PHY chip on board Adress selection is set to 1 The transmit signals TPOP and TPON from the PHY are neither decoupled nor terminated on the module The receive signals TPIP and TPIN are capacitively coupled with 220pF to the PHY They have an AC termination to Gnd with 49R9 from each signal AC coupling with 100nF to Gnd Signals for link and speed LEDs are provided No transformer Ethernet connector or indication LEDs are on the module these parts have to be provided by the base board PHY clock of 25MHz is generated in the PHY chip with a 25MHz crystal 3 14 USB 2 0 full and low speed Host and Device Controller The USB section of the NS9750 CPU provides USB and USB signals and two USB control signals USB PWR and USB OVCURR All external configuration for a USB device or a USB host interface has
12. 32 16 MByte or 16MX32 64 MByte SDRAM onboard Larger chips can be populated depending on availability the highest address connected is A12 Range of chip select is 256M Timing considerations assumes 99 5328MHz SDRAM and 49 7664MHz BBus clock usage of 1MX32X4 75ns SDRAM with CAS latency of 2 and 100MHz SDRAM clock Recommended register settings 1 Control Register 0xA070 0000 set to 0x1 normal mode reset address mirror enable memory controller Status Register 0xA070 0004 read only Configuration Register 0xA070 0008 set to 0x0 clock ratio 1 1 little endian mode Dynamic Memory Control Register 0xA070 0020 set to 0x3 memory clock enabled Dynamic Memory Refresh Timer register 0xA070 0024 set to 0x63 16us refresh time with 100MHz SDRAM clock Dynamic Memory Read Configuration Register 0xA070 0028 set to Ox1 command delayed strategy clock not delayed modify only Bit0 1 min 0x1 max 0x3 Dynamic Memory Precharge Command Period Register 0xA070 0030 set to 0x1 2 clock cycles TRP 20ns modify only bit0 3 Dynamic Memory Active to Precharge Command Period Register 0xA070 0034 set to 0x4 5 clock cycles TRAS 45ns modify only bit0 3 Dynamic Memory Self refresh Exit Time Register 0xA070 0038 set to OxF 0x10 clock cycles TSREX modify only bit0 3 25 Module A9M9750 2 10 11 12 13 14 15 16 17 18 19 20 21 Dynamic Mem
13. 6 32 64 MBytesSDRAM 25 3 11 50 GPIO Pins multiplexed withotherFunctions 27 12 POIGSrdBUS POI anarak ide sa da Sat st gel sl sa ses da SUK ONUR dl 30 3 13 10 100Mbps Ethernet Port ra Sam Glam Ge i ai 31 3 14 USB 2 0 full and low speed Host and DeviceController 31 3 15 WART Channels caw as ana da al as ak ala OST T Gem Ard GLA GSE 31 TLES a NANOS is e NE le me em 31 3 17 Calculation of Baudrates eee 32 STEG BS rasana aaa aE mah a TAA AG an a O an ee aa a a aa Ng anan ee re 34 3 19 LCD Controller STN amp TET aana a pa a ala Ba a akl 36 3 20 Serial EEPROM for storing Configuration Parameters 36 e EE Eee PE EP ME ierik aldim ie 36 3 22 JTAG Boundary Scan aaa Aadalen Ae AN 36 3 23 Single 3 3V Power Supply Laste a Mi e elik aa 38 3 24 Power Sequencing on A9M9750 2Module 38 3 25 Voltage Supervision and RESET Generatlon 39 A Bootloader ai la andere haw alay m kikke 40 Module A9M9750 2 SONA DE Me ee aker kre e e eee e ERR 40 2 Mechanics nansa oa edad Ab Raed eae MATE sant Sl Ne mal 42 6 1 ExtendedModule 44 KnownFaultsandlimitations 46 7 1 USBPinsarenot5Vtolerant nn ennen 46 7 2 Tim
14. CSO 0x40000000 0x4FFFFFFF e jawa CS0 EE KA aai Le Rasy Memoy Flash Memory es Rad fe erer a HE CS2 P A TT CS3 GINI E AN ANG memory ere ME memory 21 Module A9M9750 2 PCI Oo 0xA0000000 0xA00FFFFF L PCI IO i 0xA0100000 0xA01FFFFF MEN 0xA0200000 0xA02FFFFF Be S 0xA0300000 0xA03FFFFF R FE OxA0400000 0xA04FFFFF WA reserved 0xA0500000 0xA05FFFFF reserved Ethernet OxA0600000 0xA06FFFFF Ethernet Commun ication Module Memory 0xA0700000 0xA07FFFFF Memory Controlle OxA0800000 0xA08FFFFF LCD Controlle System 0xA0900000 0xA09FFFFF reserved 0XA0A00000 0xFFFFFFFF 1536 reserved 22 Module A9M9750 2 3 9 NAND Flash A9M9750 has 32Mx8 64Mx8 or 128Mx8 NAND Flash onboard Optionally greater sizes can be populated depending on availability The NS9750 does limit the address range of a single chip select to 256MByte but this is not relevant for NAND Flash as the interface to the NAND flash needs always 32 kByte here due to usage of A13 14 for address and command control The NAND flash is accessed with EXT_CS1 The chip can be write protected externally with the signal FWP Timing considerations assumes 99 5328MHz AHB and 49 7664MHz BBus clock Static memory controller has a clock of 99 5328MHz 10 048ns per clock cycle The AHB memory controller needs 5 cycles 50ns for every seguence from start to the activation of the memories addr
15. EL Endian mode PD 2k2 no GP1044 resistor not 0 Big endian optional TXDD or populated sets to 1 Little endian SPI DOD little endian 11 Module A9M9750 2 Data Sheet of NS9750 Usage on Module TR GP1044 is inverted SPI Boot does not work in big endian mode GPI049 CS1POLSEL Chip select 1 Er 10k Not relevant on polarity module as we do 0 Active high always boot from 1 Active low SPI EEPROM GP1049 is inverted Used as FR B PU 10k is at NAND Flash 32 of the 50 GPIO pins allow user specific configurations They are latched in the GEN ID register with the rising edge of RESET address 0xA0900210 poss a Mil n usage Protection RER 60488 DMAIL REQ Gro pf EE E GR06 1 A Vo GROS 1 LODD GRIQ44 ENDSEL yes LCDD20 GROS EDDA 7 VO T 31 GPIO41 SCONF3 yes o LCDD17 30 GPI040 SCONF2 yes LCDD16 26 GPI036 MOD VERO yes LCDD12 2 GROS 1 LODD 24 SGRIOS4 LCDD10 23 GPIo33 1 LCDD9 2 GRO2 T LCDD8 2 GR 31 f LOnD7 20 GRO0 LODDE 12 Module A9M9750 2 SR Kana n usage Protection fe 19 GPI029 LCODDS GPO28 1 LODD4 fore PLL ISI ME 5 HERE sd TI EN e LCD CIK Z e PLLBP LCD HSYNC ei LCD PWREN PLL ND4 USB PWRREL g 6 EA i NTT SPI ENA NANA pang SPI CLKA as RTC INI GRO
16. Module A9M9750 2 Users Manual Module A9M9750 2 Copyright 2005 FS Forth Systeme GmbH Postfach 1103 79200 Breisach Germany Release of Document April 05 2005 Filename UM Module A9M9750 2 doc Author Karl Rudolf Program Version All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of FS Forth Systeme GmbH Module A9M9750 2 1 Revision History 2005 04 05 V1 00 KR Initial Version derived from Spec A9M9750 2 Module Module A9M9750 2 Table of Contents 1 Revisiom History GE e Pa e e e mars 3 2 Introduction sise ee a erman al alen dil 6 2 1 Benefits of the ModARM9 Concept 6 2 2 Common aI 6 2 3 Differences between A9M9750 1 and A9M9750 2Modules 7 2 4 Planned and realised Variants for A9YM9750 2Module 8 3 A9M9 50 Features ara ase ul na alel sens az ga Na a ag Ta ak ai 9 le Size 60 X 44 MM raner AT 9 3 2 2x120 pin Connectors aaa kana e Ga a re KA ene one 9 3 3 NS9750 CPU on the A9M9750 2Module 9 3 4 Configuration Pins CPU eee lk edil Kanik reies 10 3 5 Configuration Pins Module esse 15 3 6 Clock Generation Lake ag aa ag ga NE meali ENG Si a S le o sl 18 3 7 Serial Boot EEPROM Boot SPI Channel Settings 21 3 8 Chip Selects Memory Map sss eee 21 3 9 NAND Flash EE A My EM 23 3 10 1
17. SB clock is generated by crystal circuits Stable clocks are ensured only when both clocks are made by oscillators This information was distributed by NetSilicon when the A9M9750_1 redesign was finished So another redesign was necessary ending in the module A9M9750 2 Differences in detail 1 System clock 29 4912MHz now made with oscillator 2 USB clock 48MHz now made with oscillator 3 RSTIN directly connected to U13 pin 7 MR 4 Pull up resistor R34 from RSTIN to 3 3V added Module A9M9750 2 2 4 Planned and realised Variants for A9M9750 2 Module Modules using CPU A1 chips with working PLL will have at least two speed and temperature variants 1 CPU speed 199 0656MHz 0 70 temperature range Realised V01 0364 with 32M NAND Flash and 16M SDRAM V02 0380 with 32M NAND Flash and 64M SDRAM 2 CPU speed 162 5MHz 40 85 temperature range Not realised in the moment Maybe a PCI host and client version of each variant will be created which have different parts in the PCI block populated Module A9M9750 2 3 A9M9750 Features 3 1 Size 60 x 44 mm The A9M9750 module has a size of 60 X 44 mm 3 2 2 x 120 pin connectors Two 120 pin connectors on the long side of the module allow accessing most signals of the NetSilicon NS9750 CPU An optional extension with another two 60 pin connectors is planned This will extend the length of the module from 60mm to approximately 95MM Pin compatible in power su
18. be the same for modules with and without used CPU PLL when BBus is used as clock source UM UART mode either 8 16 32 Normally 16 taken M input clock divider 2 for ND gt 19 0 lt N lt 16383 decimal for baud rate generator count General calculation formula divider N for clock source 1 N X1_SYS_OSC M UM Baudrate 1 simplifies for X1_SYS_OSC 2 14 7456MHz to N 921600 Baudrate 1 and for X1 SYS OSC 4 7 3728MHz to 32 Module A9M9750 2 N 460800 Baudrate 1 Example for 38400 Bd N 460800 38400 1 11 error 0 General calculation formula divider N for clock source 2 N BCLK UM Baudrate 1 simplifies for 49 7664MHz to N 3110400 Baudrate 1 Example for 38400 Bd N 3110400 38400 1 80 error 0 Simplifies for 40 5504MHz to N 2 534400 Baudrate 1 Example for 38400Bd N 2 534400 38400 1 65 error 0 33 Module A9M9750 2 Count values vs Baud Rate Clock Baud Rate N X1_SYS 2 N X1_SYS 4 N BBus N BBus 14 7456MHz 7 3728MHz 49 7664MHz 40 5504MHz Error Error Error Error 12287 150 6143 300 3071 10367 1535 5183 1200 767 2591 2400 383 1295 4800 191 7200 127 431 14400 63 31 09 215 6 19200 47 161 28800 31 107 38400 23 80 57600 15 7 53 115200 7
19. ck is buffered with a clock buffer with 4ns slew rates allowing up to 50mA output currents 3 3V Oscillators PLL settings and resulting frequencies Modules with Modules with 200MHz CPU 162 5MHz CPU 0 70 40 85 Oscillator 29 4912 29 4912 PLL ND 4 0 PLL Multiplier 0611111 27 10610000 22 18 Module A9M9750 2 Modules with Modules with 200MHz CPU 162 5MHz CPU 0 70 40 85 PLL FS 1 0 PLL divider 0b11 2 0617 2 PLL IS 1 0 value 10b11 ND16 31 0b11 ND16 31 VCO output Oscillator PLL MHz 796 2624 648 8064 Multiplier resulting PLL clock VCO MHz 398 1312 324 4032 PLL Divider 199 0656 CPU clock PLL 2 199 0656 162 2016 AHB SDRAM and external MHz 99 5328 81 1008 clock CPU 2 BBUS clock AHB 2 49 7664 40 5504 UART Baud Rate Clock MHz 14 4560 14 4560 X1 SYS CLK M internal PCI clock 28 4379 32 4403 19 Module A9M9750 2 Summary Clock Frequencies on Module Oscillator 29 4912MHz PLL ND 4 0 PLL Multiplier 11111 27 CPU PLL active PLL FS 1 0 PLL divider 11 2 CPU PLL active PLL 1S 1 0 value 11 ND16 31 CPU PLL active resulting PLL clock 398 1312 CPU clock 199 0656 AHB SDRAM and external clock 99 5328 BBUS clock 49 7664 UART Baud Rate Clock BBus 49 7664 PCI clock 33 33MHz with external oscillator LCD clock 99 5328MHz 49 7668MHz 24 8834MHz or 12 4417MHz
20. e eS eml e Debug enadle 4 0 0 Boundary Scan enable 14 Module A9M9750 2 3 5 Configuration Pins Module Module configuration pins change either hardware configurations on the module HCONFO 3 or they are user specific and can be read in the GEN ID register SCONFO 3 Signal name PU external Comment PD pin name DEBUG EN CPU Mode Select PU 10K HCONFO 0 Disconnects TRSTH and PWRGOOD for JTAG and Boundary scandebug mode 1 TRST and PWRGOOD connected for normal mode default FWP internal NAND flash write PU 10K HCONF1 protect 0 write protect active 1 no write protect OCD EN JTAG Boundary Scan PU 10K HCONF2 SelectJTAG function selection mode 0 ARM Debug Mode DEBUG ENZ has BISTEN set to high to be low too 1 Boundary Scan Mode BISTEN set to low default CARDBSEL CardBus pe default PCI mode Mode Bootstrap Select can be changed 0 CardBus mode externally with pin 1 PCI mode HCONF3 GPIO38 User defined software SCONFO read Bit 28 configuration pin can be GEN_ID read in GEN ID register bit 28 default high GPIO39 User defined software SCONF 1 read Bit 29 configuration pin can be GEN_ID read in GEN ID register bit 29 default high GPIO40 User defined software configuration pin can be SCONF2 read Bit 30 GEN ID 15 Module A9M9750 2 Signal name PU external Comment PD pin name read in GEN ID register DE bit 30 default high GPIO41
21. ed The minimum distance is 5mm Therefore the height of the parts mounted on the bottom side of the module should not exceed 2 5mm The height of the parts mounted at the top side should not exceed 4 1mm Board to Board Module Connector X1 X2 Base Board Connector X1 X2 Distance h No of Pins Qty Supplier Order No No Of Supplier Order No Pins 5 mm 120 AMP 177984 5 Berg 61083 121000 6 mm 120 2 AMP 177983 5 120 AMP 179029 5 Berg 61082 121000 Berg 61083 122000 7 mm 120 AMP 179030 5 Berg 61083 123000 8 mm 120 AMP 179031 5 Berg 61083 124000 42 Module A9M9750 2 Mechanical Drawing from TOP View 2 2 2x 43 Module A9M9750 2 Mechanical Drawing from Side View The size of h depends on the board to board connectors The size between the board to board connectors is measured from pad to pad 6 1 Extended Module For further modules in the ModARM9 family it might be necessary to have some additional hardware placed on the module which will need more signal lines connected between module and base board than currently available To meet these future requirements an extended board was defined which has two additional board to board connectors with 60 pins each The size of the extended module is defined as 92 x 44mm Two holes for M2 screws catercornered are provided to enable fixing of
22. ends on the different possible clock sources PLL active BASE CLK MHz CPU CLK MHz comment Yes 398 1312 199 0656 BASE CLK 29 4912 MHz ND 1 2 BASE CLK 29 4912 MHz 27 2 The PLLNDSW bits must be taken into account for calculating baudrates and timer values Yes 324 4032 162 2016 BASE CLK 29 4912 MHz ND 1 FS BASE CLK 29 4912 MHz 22 2 The PLLNDSW bits must be taken into account for calculating baudrates and timer values Yes 250 6752 125 3376 BASE_CLK 29 4912 MHz ND 1 FS BASE CLK 29 4912 MHz 17 2 The PLLNDSW bits must be taken into account for calculating baudrates and timer values e Bootloader is able to update the bootloader itself e Not finished 5 Software 40 Module A9M9750 2 The ARM926 core in the NS9750 contains an MMU thus allowing Operating Systems such as Linux and Windows CE to be supported Board Support Packages for Windows CE net 4 2 and Linux using kernel 2 6 x are in development Other Operating Systems can be supported on reguest 41 Module A9M9750 2 6 Mechanics The module size is defined to 60 x 44mm Two holes for M2 screws catercornered are provided to enable fixing of the module on the base board Two board to board connectors are used on the module Depending on the counterpart on the base board different distances between module and base board can be realiz
23. ess data and control signals This timing overhead occurs once per single operation and when running burst cycles The read or write cycle has a minimum time of one cycle 10ns The static memory controller allows different adjustments for the memory timings Values in the registers of static CS1 verified with module w 199MHz CPU clock HCLK 99 5328MHz 10 048ns per cycle Chip Select 1 Configuration MEM StConfig1 0x80 no write protect write buffer disabled extended wait disabled BEx used chip select low active bus width 8bit Write Enable Delay MEM StWaitWen1 0x1 2 HCLK cycles CS setup is Ons Output Enable Delay MEM StWaitOen1 0x3 3 HCLK cycles data setup is 20ns Length OE in non page mode Delay 1 read in page mode 23 Module A9M9750 2 MEM StWaitRd1 0x8 9 HCLK cycles OE width is 60ns Important Length OE is value from this register minus value in MEM StWaitOen Delay next read in page mode MEM StWaitpage1 0x6 8 HCLK cycles data rate is 50ns Delay write MEM StWaitWr1 0x5 6 HCLK cycles min write length is 45ns Delay between data direction change MEM StWaitTurn1 0x7 7 HCLK cycles delay between WE high and RD low is 60ns 24 Module A9M9750 2 3 10 16 32 64 MBytes SDRAM One SDRAM bank is available It is connected to CS4 SDM CS0 CS5 SDM CS14 CS6 SDM CS2 and CS7 SDM CS34 are lost The module does not provide external SDRAM connection A9M9750 has 4MX
24. ing Bug in WC Stage eee 46 7 3 PLLClockGenerationinstable gt gt 46 SAD DENNA DE sa nama mal nda A ag A a aba a a NE aa E ilin 47 8 1 Pinning Module s s esasi anana anana Alka S men 47 8 2 Pinning Module on A9MValiValidationBoard 47 8 3 Pinning Module on A9M9750DEV DevelopmentBoard 47 Module A9M9750 2 2 Introduction There are now a number of interesting ARM9 based SoC solutions available on the market These chips are usually designed for particular market segments which implies a departure from the one size fits all philosophy for the modules To accommodate this the ModARM9 concept foresees more than one ARM9 based module with the modules having a common subset of functions One or two of these modules will become a standard product at FS Forth the others will be custom designs The first standard module based on the NetSilicon NS9750 is called the A9M9750 The 1 silicon of the NS9750 had a lot of bugs some of these needed hardware work arounds extending the 1 A9M9750_0 modules size about 8mm on the long side With the announcement of the 2 silicon NS9750 A1 most of the important bugs are fixed all new modules A9M9750 X have the original size of 60X44mm Due to the fact of PLL instabilities in the 2 silicon the module A9M9750 2 was necessary with changed generators for system and USB cloc
25. k 2 1 Benefits of the ModARM9 Concept One of the problems constantly faced at any design house involved in custom designs is how to re use the work done in previous designs The ModARM9 concept is designed to help address this by expanding the common set of tools available to the design engineers For example an evaluation board will be designed which is the same for all modules This will allow the common features of a new module to be tested quickly If the new module is a custom design then the customer s base board must be used to test all the peripherals available on the module This will allow custom designs to be offered at a more attractive price than previously possible 2 2 Common Features Below are the common features of this module which will be covered in further detail later in the document e ARM9 core with MMU Module A9M9750 2 e Size 60mm x 44mm with 240 pin connector e SDRAM 16MB 256MB e NAND Flash 32MB 256MB e 2 4 serial RS232 interfaces e Host or device USB interface USB2 0 compliant e 10 100Mbps Ethernet interface e C interface 100KHz and 400KHz e SPI interfaces e JTAG interface This means that approx 150 pins of the connector are reserved for the above functionality the others are free for module specific functions 2 3 Differences between A9M9750_1 and A9M9750 2 Modules The NS9750_A1 chips has still an important bug System frequencies are instable if system and U
26. levant on 0 BEx function module 1 WEx function CONFO is inverted CARDBSEL CardBus yes HCONF3 default PCI mode Mode Bootstrap Select can be changed 0 CardBus mode externally with pin 1 PCI mode HCONF3 MEMRDSEL Memory no no always command Interface read mode delayed mode Bootstrap Select clock delayed 0 Command delayed mode does not mode work 1 Clock delayed mode CONF4 3 CS1DWSEL Chip Select1 no no default 32bit 10 Module A9M9750 2 Data Sheet of NS9750 Usage on Module Data width bootstrap select Not relevant on 00 16 bits module as we do 01 8 bits always boot from 10 reserved SPI EEPROM 11 32 bits GPIO2 0 PLL FS 1 0 PLL config pins on Frequency divider select module n c 00 4 01 8 10 1 11 2 default GPIO2 inverted GPIOO not inverted GP1017 1 PLL_ND 4 0 PLL multiplier 5 PD 2 10 8 4 ND 1 2K2 b11010 26 decimal optional PLL multiplier default 27 GPIO10 4 inverted RTSA GPIO12 DTRA GPIO19 PLLBP PLL bypass PD 2k2 GPIO19 0 PLL bypassed optional LCDHSY 1 PLL not bypassed GPIO19 is inverted GPI024 2 PLL 1S 1 0 PLL charge 0 pump current ND 00 NDO 3 01 ND4 7 10 ND8 15 11 ND16 31 default GPIO36 MODVERSO LSB Module PD 2k2 GPIO36 GPIO36 left open Version optional LCDD12 GPIO37 MODVERS1 MSB Module PD 2k2 GPIO37 GPIO37 PD Version LCDD13 GPIO37 GPIO36 0 1 V2 0 CPU PLL ok GP1044 ENDS
27. lines GP1018 23 This interface allows connection of most TFT and STN monchrome and color LCDs Details see NS9750 hardware user manual 3 20 Serial EEPROM for storing Configuration Parameters The nonvolatile storage of parameters like MAC address etc is supported with a serial 8Kx8 EEPROM 24LC64 or similar connected to the I2C bus at device address 0xA0 OxA1 3 21 RTC An RTC MAXIM DALLAS DS1337 in uSOP8 case on the module is connected to the ISC bus device address OxDO OxD1 It has its own 32 768KHz clock crystal Power is taken from 3 3V when provided otherwise from Ver fed by an external battery An interrupt line GPIO13 is connected to the RTC it can be opened by depopulating a resistor 3 22 JTAG Boundary Scan NS9750 support JTAG and boundary scan with the signals TCK TMS TDI TDO and TRST The signal RTCK is not connected to external It is only used on the module for PCI arbiter selection Selection between normal mode and debug mode is done with the external signal DEBUG EN HCONFO Selection between ARM debug mode and boundary scan mode is done with the signal OCD EN HCONF2 See table below DEBUG ENE OCD ENE mods Commeni 4 4 fromme 36 Module A9M9750 2 1 not Boundary Scan possible recommended here too but TRST is connected with SRST system may hang 0 1 fARMdebug S 0 O 0 JBoundaySscan 37 Module A9M9750 2 3 23 Single 3 3V Power Sup
28. ory Last Data Out to Active Time Register 0xA070 003C set to 0x1 2 clock cycles TAPR ns modify only bit0 3 Dynamic Memory Last Data In to Active Command Time Register 0xA070 0040 set to 0x5 6 clock cycles TDAL or TAPW 40ns modify only bit0 3 Dynamic Memory Write Recovery Time Register 0xA070 0044 set to 0x0 1 clock cycle TWR or TDPL or TRWL or TAPW 10ns modify only bit0 3 Dynamic Memory Active to Active Command Period Register 0xA070 0048 set to 0x6 7 clock cycles TRC 65ns modify only bit0 3 Dynamic Memory Auto Refresh Period Register 0xA070 004C set to 0x6 7 clock cycles TRFC ns modify only bit0 4 Dynamic Memory Exit Self refresh Register 0xA070 0050 set to Ox1F 0x20 clock cycles TXSR modify only bit0 4 Dynamic Memory Active Bank A to Active Bank B Time Register 0xA070 0054 set to 0x1 2 clock cycles TRRD 15ns modify only bit0 3 Dynamic Memory Load Mode Register to Active Command Register 0xA070 0058 set to 0x1 2 clock cycles TMRD ns modify only bit0 3 Dynamic Memory Configuration 0 Register 0xA070 0100 set for 1MX32X4 to 0x00084500 buffers enabled 32 bit extended bus high performance address mapping 128Mb 4MX32 4 banks 12 rows 8 columns modify only bits 20 14 12 07 Dynamic Memory RAS and CAS Delay 0 Register 0xA070 104 set to 0x203 3 RAS 2CAS modify only bits 0 1 RAS and 8 9 CAS System Control Dynamic Memory Base Registe
29. ply The module has 3 3V IN supply pins VLIO pins are connected to 3 3V IN too for the A9M9750 2 module These signals have EMI filters near the connector to suppress emission of the module Internal voltages 1 5V core voltage with up to 700mA will be converted by a switching regulator to keep losses small This regulator is connected to VLIO Worst case power consumption of the NS9750 is at full operation with 200MHz clock 1 05W for the core 1 5V about 700mA and 0 65W for the I O ring 3 3V about 200mA In sleep mode power consumption decreases to 170 350mW 120 240mA for the core and 10 90mW 3 30mA for the I O ring depending on the ports used for wake up 3 24 Power Sequencing on A9M9750 2 Module Power up and power down behavior recommended by NetSilicon and TOSHIBA for the NS9750 Power up core voltage will be first to rise I O voltage 3 3V will ramp up in lt 100ms when core voltage rises over 80 of its nominal value Power down I O voltage will ramp down in lt 100ms when core voltage falls below 80 will be ensured by hardware The sequencing circuit is realised with two comparators a variable delay and a FET switch TPS2022 U18 between 3 3V IN and 3 3V on the module The 1 comparator TLV3012 U12 with a 3 0V threshold supervizes 3 3V IN Its output becomes true if 3 3V IN gt 3 0V The 2 comparator TLC7701 U16 supervizes 1 5V core voltage When 1 5V core voltage gt 1 3V the output becomes true
30. pply and main port functions to other ModARM9 modules 3 3 NS9750 CPU on the A9M9750 2 Module NS9750 CPU has a 32 bit ARM926EJ S core Further details see Hardware Reference 9000624c pdf NetSilicon has planned to support two temperature ranges e 0 70 C with 200MHz CPU clock e 40 85 C with 162 5MHz CPU clock Module A9M9750 2 3 4 Configuration Pins CPU Several pins allow configuration of the CPU before booting CPU pins have weak pull ups value range is 15 300K for a default configuration Most pins do not have configuration options some are connected for internal configuration on the module some others allow external configuration via external connector pins The configuration state is latched 5 system crystal clock cycles after the rising edge of the PWRGOOD signal at the RESET input of the CPU 5 1 29 4912 10E6 169 5ns Data Sheet of NS9750 Usage on Module CPU PU PD external external Comment Pin configu pin name rable PCIAC PCI Arbiter PD 2k2 no no internal PCI arbiter Configuration optional on PCI host 0 External PCI Arbiter version external 1 Internal PCI Arbiter PCI arbiter on PCI device version pin RTCK is not provided on module RESET D BOOTDS Boot Mode PD 2k2 no RSTOUT Boot mode default ONE 0 Boot from SPI from serial SPI EEPROM EEPROM 1 Boot from Flash ROM CS1LEP Chip select 1 byte no no Set to WEx lane enable polarity function Not Bootstrap Select re
31. r 4 0xA090 01D0 set to 0x00000000 Start Adress 0 modify only bits31 12 System Control Dynamic Memory Mask Register 4 OxA090 01D4 set to 0xF0000000 Range 256MByte 0x00000000 OxOFFFFFFF modify only bits31 12 26 Module A9M9750 2 3 11 50 GPIO Pins multiplexed with other Functions NS9750 has 50 GPIO pins All pins are multiplexed with other functions UART SPI USB DMA parallel port IEEE1284 LCD port timers interrupt inputs Using a pin as GPIO means always to give up another functionality Port Name Functio n 03 default at power up GPIOO GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 Alternate Function 00 UART TXDB RXDB RTSB CTSB DTRB DSRB RIB RXCLKB DCDB TXCLKB TXDA RXDA Alternate Alternate Function 00 misc SPI Boot DMAO DO and DONE dupe SPIB_DO DMAO REQ Dupe SPI Boot DI and SPIB DI 1284 ACK 1284 BUSY 1284 ERR 1284P JAM DMAO Ack dupe SPIA DO SPI Boot CLK and SPIB CLK SPI Boot CE and SPIB CE Alternate Timer 1 dupe DMA1 ACK DMAO REQ DMAO DONE DMAO ACK Timer 7 dupe IRQ1 Reserved Timer 8 dupe On Module Function 01 Function 02 default used as TXDB SPI Boot DO or external SPIB DO RXDB SPI Boot DI or external SPIB SI RTSB DMA CTSB DMA DTRB DSRB DMA RIB SPI Boot CL K or external SPIB CLK DCDBt SPI Boot CE ff or external SPIB
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