XS40, XSP, XS95 Board User Manual
Contents
1. ME Ao lt sol dhez jo anyo anyo anyo s 5 je E zt cu 8 101SNEOX IYSAOJSNGIX GJINI HOLIMS Se vg er OZd vi sg cr teliza zwvix H de Z8 sr Se zzd oe 18 Ef HE eer DE Bord 8 101SNEOX al FISNGIX T Gad gede S D I 009 Lu IZSNGI Izd vEdl ar 3 X 94 Ef ze pH e ze gt AAN lid eede SEH Ce 00 SEZSHAIX zed SEH a DH it oos o GISNEJ VSSNGOX N3Sd Id gy lt OH ec er ze pol z zr gt AAN Est JIV ocd i M Er 00 63 ZISNGIX CES va ISY OL Sr a D 42248 oo BY SISNGIX HEG ZO S SSC ze gt ver Daia Steen ERNA SESNEOX gej 49d drs PITER zi ir 49 P GG G SNGIX Ze 205 ale Keng S Ser LESNGIX 8 oi el TZSNGOX WZSNGOX Se saaier a E 6ESNADX Dis 9 ZZSNAIX PZSNGOX ELIF S ci zr D CO Eld 9 cr akai SISNGIX 0 SHGIK 091299 SR I SOSNGIK E er Dt ERD W od ld SC ENER 19 P P A TERN AE ZOSNAIX gin gt D Ss TEE etana FREAK VSNGOX 7 Song WOSNGOX E ut UKSA 6ZSNGIK LSI pl GZSNADIX AS IN v SERA Ee ER r gt ders TOSMGOK as HON pe er ZISNGIX Aen 9YN G EP rb SOSNGOX Ast dyn CH Z Et r DR Zur D T Oe greng 6Y r IG r ir D genl Ast IPN F 8 0S P vISTL wer m 2 Ro Ma Si S Ast ON Elei KH T OT zysha Ast Gen PEL ven T v er ik grsnaox Bremer 4 30 Ent gir enz AC RTS ir B EE Grengen Q 97901 of Er TESNAIX VOGShSIX 0E 8 30 DEET2. G E IND K ha ii N ko ko 8 REN REBNSSSS AAAAAA e Figure 7 X 95 Board programmer s model 23 XTAL1 RST ALE PSEN P41 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P3 7 RD P3 6 WR P3 5 TI P3 4 TO P3 3 INTI P3 2 INTO P3 1 TXD P3 0 RXD PO 7 A7ID7 PO 6 AGIDS PO 5 ASIDS PO 4 A4 D4 PO 8 A3 D3 P0 2 A21D2 PO 1 A1 D1 P0 0 AOJDO P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 32K x 8 SRAM XS40 and XSP Board Schematic EMV DC ain 089 99N and DZ ENN 2 cer amp E oi zr aa S AOL g ar LG AAN anzz Anez z Er oz ir 0691 64 e SE 13 KI 9 zr 6i ir P os s er DIE Lo Fav 2 p ves LENI BERG agn DEE HOLIMS ano an if 4 19 e ze D eg NANE Sun O AGT 991d IK08 age STEET 08917 7 gen l u
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4. P2 5 413 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 8051 uC 32K x 8 SRAM e Table 8 XS95 Board pin descriptions XS95 Pin Connects to Description These pins drive the individual segments of the LED display S0 S6 and DP They also drive the color horizontal and vertical sync signals for a VGA monitor These pins are driven by the data output pins of the PC parallel port Clocking signals can only be reliably applied through pins 46 and 47 since these have additional hysterisis circuitry the port pins indicated in parentheses Pin 63 connects to the data write pin of the uC and the write enable pin of the RAM Pin 70 connects to a status input pin of the PC parallel port These pins connect to Port 0 of the uC which is also a multiplexed address data port These pins also connect to the data pins of the RAM These pins connect to Port 2 of the uC which also outputs the upper address byte These pins also connect to the 7 upper address bits of the RAM 21 PC_S6 lt PC 5 lt PC 4 PC_S3 lt PC Parallel Port Status Inputs l VGA Inputs 7 Segment LED 12 MHz VSYNC lt HSYNC lt RED ___ REDO GREEN ___ _ _ __ GREENO BLUE1 lt _____ _ ___ BLUEO lt __ __ Osc PC_D7 PC DE PC DS PC D4 PC D3 PC_D2 PC DI PC DO PC Parallel Port Data Outputs Free Pins
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6. You will have to download a mouse or keyboard driver circuit to your XS Board to actually display an image You can find an example keyboard driver at www xess com FPGA Setting the J umpers on Your XS Board The default jumper settings shown in Table 2 and Table 3 configure your XS Board for use in a logic design environment You will need to change the jumper settings only if you are m using your XS40 or XSP Board in a stand alone mode where it is unconnected from the PC parallel port m executing microcontroller code from internal ROM instead of the external RAM on the XS Board m reprogramming the clock frequency on your XS40 or XSP Board The procedures for performing the operations are described in the rest of this manual e Table 2 umper settings for XS95 Board Jumper Setting Purpose J7 1 2 ext The shunt should be installed on pins 1 and 2 ext if the 8031 microcontroller program is stored in the default external 32 KByte RAM U8 of the XS95 Board 2 3 int The shunt should be installed on pins 2 and 3 int if the program is stored internally in the microcontroller Jumper JA J6 J7 J8 J10 J11 J12 Setting On default Off On Off default 1 2 ext default 2 3 int On Off On Off default On default Off Off default On e Table 3 J umper settings for XS40 and XSP Boards Purpose A shunt should be installed if you are downloading the XS40 o
7. also impose limitations on how your program and the FPLD hardware will interact High level views of how the microcontroller RAM and FPLD on the XS40 XSP and XS95 Boards are connected are shown in Figure 5 Figure 6 and Figure 7 respectively More detailed schematics are presented at the end of this manual The oscillator output goes directly to a synchronous clock input of the FPLD The FPLD can control the clock it sends to the XTAL1 clock input of the microcontroller 15 The microcontroller multiplexes the lower eight bits of a memory address with eight bits of data and outputs this on its PO port Both the RAM data lines and the FPLD are connected to PO The RAM uses this connection to send and receive data to and from the microcontroller The FPLD is programmed to latch the address from PO under control of the ALE signal and send the latched address bits to the lower eight address lines of the RAM Meanwhile the upper eight bits of the address are output on port P2 of the microcontroller The RAM uses the lower seven of these address bits The FPLD also receives the upper eight address bits and decodes these along with the PSEN and read write control line from pin P3 6 of port P3 from the microcontroller to generate the CE and OE signals that enable the RAM and its output drivers respectively Either of the CE or OE signals can be pulled high to disable the RAM and prevent it from having any effect on the rest of the XS Board circu
8. an XS40 005E XS40 005XL or XS40 010E Boards The XS40 Board can directly program the Atmel chip and the FPGAs on these boards have bitstream files which are small enough to fit in the AT17C256 The following steps will enable you to load your design into the Atmel EEPROM 1 Turn off power to the XS Board 2 Place a shunt on jumper J6 This enables the programming circuitry in the Atmel EEPROM chip 12 3 Apply power to the XS Board 4 Use the following command to load the FPGA bitstream file into the EEPROM C gt XSLOAD SERIAL_EEPROM CIRCUIT BIT It will take less than a minute to program the contents of the bitstream in CIRCUIT BIT into the Atmel EEPROM 5 Turn off power to the XS Board 6 Remove the shunt on jumper J6 This disables the programming circuitry in the Atmel EEPROM chip so your design cannot be overwritten Once you have your design loaded into a XILINX or Atmel EEPROM you can place it in socket U7 on the XS Board Then the following steps will make the XS Board configure itself from the EEPROM instead of the PC parallel port interface 1 2 3 4 Remove the downloading cable from connector J1 of the XS Board As an alternative you can use the command XSPORT 0 to make sure the upper two data bits of the parallel port are at logic 0 These bits are connected to the mode pins of the FPGA and must be at logic 0 or the FPGA will not power up in the active serial mode Place a shunt o
9. Board will be labeled as an XS40 but the socket will contain a Xilinx Spartan FPGA with an XCS prefix a6 cable with a male DB 25 connector on each end m a3 5 floppy diskette or CDROM with software utilities for using the XS40 XSP or XS95 Board and documentation Chapter Installation Installing the XSTOOLs Utilities and Documentation XILINX currently provides the Foundation tools for programming their FPGAs and CPLDs Any recent version of XILINX software should generate bitstream configuration files that are compatible with your XS40 XSP or XS95 Boards Follow the directions XILINX provides for installing their software XESS Corp provides the additional XSTOOLs utilities for interfacing a PC to your XS Board Run the SETUP EXE program on the 3 5 diskette or CDROM to install these utilities Once the XSTOOLS are installed you will see the following subdirectories XSTOOLS BIN contains the executable programs for downloading to the XS Board and for applying signals to the XS Board through the printer port An assembler for the microcontroller is also included XSTOOLS DOCS contains the documentation and schematics for the XS40 XSP and XS95 Boards Applying Power to Your XS Board You can use your XS Board in two ways distinguished by the method you use to apply power to the board Using a 9VDC wall mount You can use your XS Board all by itself to experiment logic and microcontroller designs Just place th
10. L 2608 Sweetgum Drive Apex NC 27502 Toll free 800 549 9377 A International 919 387 0076 FAX 919 387 1302 Corporation XS40 XSP XS95 Board User Manual How to install test and use your new XS Board Copyright 1997 1999 by X Engineering Software Systems Corporation All XS prefix product designations are trademarks of XESS Corp All XC prefix product designations are trademarks of Xilinx ABEL is a trademark of DATA I O Corporation All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electronic mechanical photocopying recording or otherwise without the prior written permission of the publisher Printed in the United States of America Limited Warranty X Engineering Software Systems Corp XESS warrants that the Product in the course of its normal use will be free from defects in material and workmanship for a period of one 1 year and will conform to XESS s specification therefor This limited warranty shall commence on the date appearing on your purchase receipt XESS shall have no liability for any Product returned if XESS determines that the asserted defect a is not present b cannot reasonably be rectified because of damage occurring before XESS receives the Product or c is attributable to misuse improper installation alteration accident or mishandling while in your possession Subject to the limitations specif
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12. atile Designs in Your XS Board Once your design is finished you may want to store the design on the XS Board so that it is configured for operation as soon as power is applied This is easy with the XS95 Board The XC9500 CPLD always stores its current configuration in an on chip Flash memory This configuration is restored whenever power is applied to the XS95 Board So your design is always available even when the board is not connected to a PC But the XC4000 or XCS FPGA on the XS40 or XSP Board stores its configuration in an on chip RAM which is erased whenever power is interrupted You can place an external serial EEPROM in socket U7 which stores the FPGA configuration and reloads it on power up The XILINX XC1700 series of serial EEPROMs is a good choice for this but you will need an external programmer to load your bitstream into the XC1700 chip Also the XC1700 is one time programmable OTP so you will need a new chip every time you change your logic design Table 5 lists the serial EEPROM chips you need for storing the bitstream files for the various types of XS Boards e Table 5 Recommended XILINX serial EEPROMS for various types of XS Boards XS Board Type Bitstream Size XILINX EEPROM XS40 005E 95 008 XC17128E XS40 005XL 151 960 XC17256E XS40 010E 178 144 XC17256E XS40 010XL 283 424 XC1701 XSP 010 95 008 XC17S10 You also have the option of storing your design into an AT17C256 Atmel reprogrammable serial EEPROM if you have
13. connect to Port 0 of the uC which is also a multiplexed address data port These pins also connect to the data pins of the RAM These pins connect to Port 2 of the uC which also outputs the upper address byte These pins also connect to the 7 upper address bits of the RAM These pins drive the 8 lower address bits of the RAM 19 PC Parallel Port Status Inputs VGA Inputs 7 Segment LED Prog Osc t on S 25 Ee Eg oa oa PO S7 4 PC 6 lt PC SS lt PC SA PC 3 lt VSYNC lt HSYNC lt RED REDO lt _______ GREEN1 lt __________ GREENO BLUE lt _____ _ __ BLUEO lt ______ 100 MHz PC DS pse e PPPPPCPP kaas RASNSSSE BREE PC D4 PC D PC D2 PC DI PC DO e Figure 6 XSP Board programmer s model 20 PS 2 Port KB DATA KE CLK XTAL1 RST ALE PSEN P41 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P3 7 RD P3 6 WR P3 5 TI P3 4 T0 P3 3 NT P3 2 INTO P3 1 TXD P3 0 RXD PO 7 A7ID7 P0 6 AG D6 P0 5 ASIDS P0 4 A41D4 PO 3 A3 D3 P0 2 A2 D2 P0 1 AUDI P0 0 AO DO P2 7 A15 P2 6 A14
14. e XS Board on a non conducting surface as shown in Figure 1 Then apply power to jack J9 of the XS Board from a 9V DC wall transformer with a 2 1 mm female center positive plug See Figure 2 or Figure 3 for the location of jack J9 on your XS40 XSP or XS95 Board respectively The on board voltage regulation circuitry will create the voltages required by the rest of the XS Board circuitry Protoboard Installation The two rows of pins from your XS Board can be plugged into a protoboard with holes spaced at 0 1 intervals One of the A C E protoboards from 3M is a good choice Once plugged in all the pins of the FPLD and microcontroller are accessible to other circuits on the protoboard The numbers printed next to the rows of pins on your XS Board correspond to the pin numbers of the FPGA or CPLD Power can still be supplied to your XS Board though jack J9 or power can be applied directly through several pins on the underside of the board Just connect 5V 3 3V and ground to the following pins for your particular type of XS Board You will need 3 3V only if your XS40 Board contains an XC4000XL type of FPGA e Table 1 Power supply pins for the various XS Boards XS Board Type GND Pin V Pin 3 3V Pin XS95 072 V1 2 49 78 none XS95 108 V1 2 49 78 none XS40 005E V1 3 52 2 54 none XS40 005XL V1 3 52 2 54 XS40 010E V1 3 52 2 54 none XS40 010XL V1 3 52 2 54 XSP 010 V1 3 52 2 54 none PC parallel port PS 2 mouse or
15. er port The FPLD has direct access to these signals The microcontroller can also access them if you program the FPLD to pass the data bits onto the FPLD VO pins connected to the microcontroller Communication from the XS Board back to the PC also occurs through the parallel port The parallel port status pins are connected to pins of microcontroller ports P1 and P3 Either the microcontroller or the FPLD can drive the status pins The PC can read the status pins to fetch data from the XS Board The FPGAs on the XS40 and XSP Boards also have access to the clock and data lines of a keyboard or mouse attached to the PS 2 port of the board 16 e Table 6 XS40 Board pin descriptions xsaopin Connecisto Description o y O eaen JI bek ee EES a loo pg pg These pins drive the individual segments of the LED display SO S6 and DP They also drive the color and horizontal sync signals for a VGA monitor These pins are driven by the data ail pins of the PC parallel port Clocking signals can only be reliably applied through pins 44 and 45 since these have additional hysterisis circuitry Pins 32 and 34 are mode signals for the FPGA so you must adjust your design to account for the way that the Foundation tools handle these pins These pins connect to the pins of Port 1 of the uC Some of the pins are also connected to the status input pins of the PC parallel port Pin 67 drives the vertical sync signal for a VGA monitor These p
16. ied above your sole and exclusive warranty shall be during the period of warranty specified above and at XESS s option the repair or replacement of the product The foregoing warranty of XESS shall extend to repaired or replaced Products for the balance of the applicable period of the original warranty or thirty 30 days from the date of shipment of a repaired or replaced Product whichever is longer THE FOREGOING LIMITED WARRANTY IS XESS S SOLE WARRANTY AND IS APPLICABLE ONLY TO PRODUCTS SOLD AS NEW THE REMEDIES PROVIDED HEREIN ARE IN LIEU OF a ANY AND ALL OTHER REMEDIES AND WARRANTIES WHETHER EXPRESSED OR IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE AND b ANY AND ALL OBLIGATIONS AND LIABILITIES OF XESS FOR DAMAGES INCLUDING BUT NOT LIMITED TO ACCIDENTAL CONSEQUENTIAL OR SPECIAL DAMAGES OR ANY FINANCIAL LOSS LOST PROFITS OR EXPENSES OR LOST DATA ARISING OUT OF OR IN CONNECTION WITH THE PURCHASE USE OR PERFORMANCE OF THE PRODUCT EVEN IF XESS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES In the United States some statutes do not allow exclusion or limitations of incidental or consequential damages so the limitations above may not apply to you This warranty gives you specific legal rights and you may also have other rights which vary from state to state Chapter Preliminaries Getting Help Here are some places to get help if
17. ile When the XS Board is loaded with the hardware and software you need to test it to see if it really works The answer usually starts as No so you need a method of injecting test 14 signals and observing the results XSPORT is a simple program that lets you send test signals to the XS Board through the PC parallel port You can trace the reaction of your system to signals from the parallel port by programming the microcontroller and the FPLD to output status information on the LED digit much like placing printf statements in your C language programs This is admittedly crude but will serve if you don t have access to programmable stimulus generators and logic analyzers Get specifications v Define inputs and outputs v Partition functions into the microcontroller and the FPLD Enter 8031 assembly Enter truth tables and code into a ASM file logic equations into a ABL file Use ASM51 assembler Use XILINX F1 to to produce a HEX file produce a bitstream file Ls Use XSLOAD to download the HE la and bitstream files to the XS Board v Use XSPORT to debug the hardware and software e Figure 4 FPLD microcontroller design flow XS Board Component Interconnections The microcontroller and the FPLD on the XS Board are already connected together These existing connections save you the effort of having to wire them yourself but they
18. ins connect to some of the pins of Port 3 of the uC The uC has specialized functions for each of the port pins indicated in parentheses Pin 62 connects to the data write pin of the uC and the write enable pin of the RAM Pin 69 connects to a status input pin of the PC parallel port and the PS 2 data line Pin 68 connects to the These pins connect to Port 0 of the uC which is also a multiplexed address data port These pins also connect to the data pins of the RAM These pins connect to Port 2 of the uC which also outputs the upper address byte These pins also connect to the 7 upper address bits of the RAM These pins drive the 8 lower address bits of the RAM 17 PC Parallel Port Status Inputs VGA Inputs 7 Segment LED Prog Osc PC Parallel Port Data Outputs PO S7 4 PC 6 lt PC_S5 lt PC_S4 lt PC 3 lt VSYNC lt HSYNC lt RED REDO lt ________ GREENI lt __________ GREENO BLUE lt _____ _ ___ BLUEO lt ______ 100 MHz PC D7 pse e Perprrpek gab RASNSSSE BREE PC D6 PC DS PC D4 PC D PC D2 PC DI PC DO e Figure 5 X 40 Board
19. itry One of the outputs of the CPLD controls the reset line of the microcontroller The microcontroller can be prevented from having any effect on the rest of the circuitry by forcing the RST pin high through the FPLD When RST is active the microcontroller pins are weakly pulled high Many of the I O pins of ports P1 and P3 of the microcontroller connect to the FPLD and can be used for general purpose I O between the microcontroller and the FPLD In addition to being general purpose VO the P3 pins also have special functions such as serial transmitters receivers interrupt inputs timer inputs and external RAM read write control signals If you aren t using a particular special function then you can use the associated pin for general purpose VO between the microcontroller and the FPLD In many cases however you will program the FPLD to make use of the special purpose microcontroller pins For example the FPLD could generate microcontroller interrupts If you want to use the special purpose pin with an external circuit then the FPLD I O pin connected to it must be tristated An LED digit connects directly to the FPLD These same FPLD pins also drive the VGA monitor connector The FPLD can be programmed so the microcontroller can control the LEDs either through P1 or P3 or by memory mapping a latch for the LED into the memory space of the 8031 The PC can transmit signals to the XS Board through the eight data output bits of the print
20. keyboard 9VDC center positive power supply VGA monitor e Figure 1 External connections to the XS Board PC Parallel Port J8 not installed Serial EEPROM Socket FPGA Microcontroller P 2 Mouse or Keyboard VGA Monitor e Figure 2 Arrangement of components on the XS40 and XSP Boards PC Parallel Port 12 MHz Osc QVDC Power Supply C Microcontroller VGA Monitor e Figure 3 Arrangement of components on the XS95 Board Connecting a PC to Your XS Board The 6 cable included with your XS Board connects it to the parallel port of a PC One end of the cable attaches to the printer port and the other connects to the female DB 25 connector J1 at the top of the XS Board as shown in Figure 1 Connecting a VGA Monitor to Your XS Board You can display images on a VGA monitor by connecting it to the 15 pin J2 connector at the bottom of your XS Board see Figure 1 You will have to download a VGA driver circuit to your XS Board to actually display an image You can find an example VGA driver at www xess com FPGA Connecting a Mouse or Keyboard to Your XS Board You can accept inputs from a keyboard or mouse by connecting it to the J5 PS 2 connector at the bottom of your XS40 or XSP Board see Figure 1 The XS95 Board does not have a PS 2 connector
21. mputed by the microcontroller and some by the FPLD There will also be some new intra system inputs and outputs created by the need for the microcontroller and the FPLD to cooperate In general the FPLD will be used mainly for low level functions where signal transitions occur more frequently and the control logic is simpler A specialized serial transmitter receiver would be a good example Conversely the microcontroller will be used for higher level functions where the responses occur less quickly and the control logic is more complex Reacting to commands passed in by the receiver is a good example Once the design has been partitioned and you have assigned the various inputs outputs and functions to the microcontroller and the FPLD then you can begin doing detailed design of the software and hardware For the software you can use your favorite editor to create a ASM assembly language file and assemble it with ASM51 to create a HES file for the 8031 microcontroller on the XS Board For the FPLD hardware portion you will enter truth tables and logic equations into a ABL or VHDL file and compile it into a BIT or SVF bitstream file using the XILINX Foundation software With the HEX 8031 program file and the FPLD bitstream file in hand you can download them to the XS Board using the XSLOAD program XSLOAD stores the contents of the HES file into the static RAM on the XS Board and then it reconfigures the FPLD by loading it with the bitstream f
22. n jumper J10 This sets the FPGA into the active serial mode so it will provide a clock signal to the EEPROM which sequences the loading of the configuration from the EEPROM into the FPGA Remove the shunts on jumpers J4 and J11 This prevents the PC interface circuitry on the XS Board from interfering with the clock and data signals from the FPGA Apply power to the XS Board The FPGA will be configured from the serial EEPROM You may reattach the downloading cable if you need to inject test signals into your design using the XSPORT program 13 Programmer s Models This section discusses the organization of components on the XS Boards and introduces the concepts required to create applications that use both the microcontroller and the FPLD field programmable logic device Building FPLD based designs is covered in detail in the Practical Xilinx Designer by Prentice Hall Microcontroller FPLD Design Flow The basic design flow for building microcontroller FPLD applications is shown in Figure 4 Initially you have to get the specifications for the system you are trying to design Then you have to determine what inputs are available to your system and what outputs it will generate At this point you have to partition the functions of your system between the microcontroller and the FPLD Some of the input signals will go to the microcontroller some will go to the FPLD and some will go to both Likewise some of the outputs will be co
23. nto your XS40 or XSP Board as follows C gt XSLOAD CIRCUIT BIT where CIRCUIT BIT is an XC4000 or Spartan bitstream file that contains the configuration for the XC4000 or XCS FPGA Make sure the file contains a bitstream for the type of FPGA chip installed on your XS40 or XSP Board This file is created using the XILINX Foundation software tools You can download an XC9500 based design into the XS95 Board as follows C gt XSLOAD CIRCUIT SVF where CIRCUIT SVF is an XC9500 bitstream file that contains the configuration for the XC9500 CPLD Make sure the file contains a bitstream for the type of XC9500 chip installed on your XS95 Board This file is created using the XILINX Foundation software tools Use one of the following commands if you need to configure the FPGA or CPLD and also download an Intel formatted HEX file into the static RAM of the XS Board C gt XSLOAD FILE HEX CIRCUIT BIT C gt XSLOAD FILE HEX CIRCUIT SVF where CIRCUIT BIT is a bitstream file and FILE HEX is a file containing hexadecimal data The HEX file could contain microcontroller object code generated by the ASM51 11 assembler or it could be arbitrary data from some other source Whatever its source the hexadecimal data is downloaded into the XS Board RAM XSLOAD assumes the XS Board is connected to parallel port 1 of your PC You can specify another port number using the P option like so C gt XSLOAD P 2 FILE HEX CIRCUIT BIT Storing Non Vol
24. on the clock frequency you want to use The XSSETCLK will prompt you to remove the power and download cables from your XS Board Then you should place a shunt on jumper J12 Then re attach the download cable Then reattach the power cable only after the download cable is attached When power is restored to the XS Board the programmable oscillator will power up in its programming mode instead of generating a clock signal Press RETURN and the clock divisor will be programmed into the oscillator chip If you wish to change the value of the divisor you may re issue the XSSETCLK command at this point with a new divisor value without having to power down the XS Board Once again remove the power and download cables from your XS Board Then remove the shunt from jumper J12 Then re attach the download cable and the power cable When power is restored to the XS Board the programmable oscillator will power up in its active mode and output a clock signal at the set frequency 10 Chapter Programming This section will show you how to download a logic design from a PC into your XS Board and how to store a design in non volatile memory on your XS Board that will become active when power is applied Downloading Designs into Your XS Board During the development and testing phases you will usually connect the XS Board to the parallel port of a PC and download your circuit each time you make changes to it You can download an FPGA design i
25. onfiguration you can test the board using one of the commands listed in Table 4 You must execute the command in a DOS window and be in the XSTOOLSIBIN directory to run the XSTEST command e Table 4 Commands for testing the various types of XS Boards XS Board Type Test Command XS95 072 XSTEST XS95 072 XS95 108 XSTEST XS95 108 XS40 005E XSTEST XS40 005E XS40 005XL XSTEST XS40 005XL XS40 010E XSTEST XS40 010E XS40 010XL XSTEST XS40 010XL XSP 010 XSTEST XSP 010 The test procedure programs the FPGA or CPLD loads the RAM with a test program for the microcontroller and then the microcontroller executes this program The total test period including programming the board is about 15 seconds for an XS40 or XSP Board and about a minute for an XS95 Board If the test completes successfully then you will see a O displayed on the LED digit However if the test program detects an error then the LED digit displays an E or remains blank In this case check the following items m Make sure the board is receiving power from a 9V DC power supply through jack J9 or through the VCC and GND pins m Check that the board is sitting upon a non conducting surface and that there are no connections to any of the pins except for the VCC and GND pins if this is the way you are powering the board m Verify that the jumpers are in their default configuration m Make sure the downloading cable is securely attached to the XS Board and the PC parallel po
26. programmer s model 18 PS 2 Port KB DATA KE CLK XTAL1 RST ALE PSEN P4 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P3 7 RD P3 6 WR P3 5 TI P3 4 T0 P3 3 NT P3 2 INTO P3 1 TXD P3 0 RXD PO 7 A7 D7 P0 6 AG D6 P0 5 A5 D5 P0 4 A4 D4 P0 3 A3 D3 P0 2 A2 D2 P0 1 A1 D1 P0 0 AO DO P2 7 A15 P2 6 A14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 8051 uC 32K x 8 SRAM e Table 7 XSP Board pin descriptions xsaopin Connecisto Description o yO some JI P3 1 TXD PC_S6 PS 2 DATA These pins drive the individual segments of the LED display S0 S6 and DP They also drive the color and horizontal sync signals for a VGA monitor An input driven hy th DON MHz nraarammahia n N These pins are driven by the data output pins of the PC parallel port Clocking signals can only be reliably applied through pins 44 and 45 since these have additional hysterisis circuitry connected to the status input pins of the PC parallel port Pin 67 drives the vertical sync signal for a VGA monitor These pins connect to some of the pins of Port 3 of the uC The uC has specialized functions for each of the port pins indicated in parentheses Pin 62 connects to the data write pin of the uC and the write enable pin of the RAM Pin 69 connects to a status input pin of the PC parallel port and the PS 2 data line Pin 68 connects to the PS 2 clock line These pins
27. r XSP Board through the parallel port The shunt should be removed if the XS40 or XSP Board is being configured from the on board serial EEPROM U7 The shunt should be installed when the on board serial EEPROM U7 is being programmed The shunt should be removed during normal board use The shunt should be installed on pins 1 and 2 ext if the 8031 microcontroller program is stored in the external 32 KByte RAM U8 of the XS40 Board The shunt should be installed on pins 2 and 3 int if the program is stored internally in the microcontroller The shunt should be installed in XS40 or XSP Boards which use the 3 3V XC4000XL type of FPGAs The shunt should be removed on XS40 or XSP Boards which use the 5V XC4000E type of FPGAs The shunt should be installed if the XS40 or XSP Board is being configured from the on board serial EEPROM The shunt should be removed if the XS40 or XSP Board is being downloaded from the PC parallel port The shunt should be installed if the XS40 or XSP Board is being downloaded from the PC parallel port The shunt should be removed if the XS40 or XSP Board is being configured from the on board serial EEPROM The shunt should be removed during normal operations when the programmable oscillator is generating a clock signal The shunt should be installed when the programmable oscillator frequency is being set Testing Your XS Board Once your XS Board is installed and the jumpers are in their default c
28. rt m Verify that the parallel port is in ECP mode The mode is usually set in the BIOS as either SPP EPP ECP or bidirectional ECP mode works most reliably while bidirectional mode is not recommended If all these checks are positive then test the board using another PC In our experience 99 9 of all problems are due to the parallel port If you cannot get your XS Board to pass the test even after taking these steps then contact XESS Corp to get a replacement board Programming the XS Board Clock Oscillator The XS40 and XSP Boards have a 100 MHz programmable oscillator a Dallas Semiconductor DS1075Z 100 The 100 MHz master frequency can be divided by factors of 1 2 up to 2048 to get clock frequencies of 100 MHz 50 MHz down to 48 8 KHz respectively The divided frequency is sent to the rest of the circuitry as a clock signal The divisor is stored in non volatile memory in the oscillator chip so it will resume operation at its set frequency whenever power is applied to the board These steps will store a particular divisor into the oscillator chip memory 1 Ina DOS window use the following command with arguments that list the type of XS Board you are using and the particular clock divisor you want CA XSSETCLK X540 005XL 8 2 3 This example command will set the programmable oscillator on an XS40 005XL Board to a frequency of 100 MHz 8 12 5 MHz You may use any divisor between 1 and 2048 depending up
29. you encounter problems m f you can t get the XS Board hardware to work send an e mail message describing your problem to fpga bugs xess com or check our web site at http Awww xess com FPGA Our web site also has m answers to frequently asked questions http Avww xess com FPGA ho01000 html m example designs for the XS Boards http Avww xess com FPGA ho03000 html m aplace to sign up for our email forum where you can post questions to other XS Board users http Avww xess com FPGA list_reg html m If you can t get your XILINX Foundation software tools installed properly send an e mail message describing your problem to hotline xilinx com or check their web site at http Avww xilinx com m The XS Boards require an external power supply to operate They do not draw power through the downloading cable from the PC parallel port m f you are connecting a 9VDC power supply to your XS Board please make sure the center terminal of the plug is positive and the outer sleeve is negative m The V1 3 version of the XS40 and XSP Boards now use a programmable oscillator with a default setting of 50 MHz You must reprogram the oscillator if you want to use another frequency The procedure for doing this is described on page 9 The XS95 Board uses a 12 MHz fixed frequency oscillator and does not need to be programmed Packing List Here is what you should have received in your package m anXS40 XS95 or XSP Board note that your XSP
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