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1. m emm m emm mm emm CS ee OS mm I GE We REES m pe CS me pe qme mm eque 98 99 5100 S101 5102 5103 5104 5105 5106 107 5108 5109 S110 S111 112 113 114 115 116 117 118 119 120 121 122 123 www kontron com User s Guide SMARCSAT30 Edge finger NVIDIA T30 CPU Notes GE VDSO i LVDS Transmitter LVDS Transmitter LCD_PWR2 LVDS Transmitter LVDS Transmitter VDS2 LVDS Transmitter LVDS Transmitter VDS2 LCD VDD EN AG29 D 5 VI D06 LVDS CK LVDS Transmitter LVDS CK LVDS Transmitter D LVDS Transmitter D L N L L LVDS Transmitter AB25 GENI 12C SCL V29 GEN DC SDA AC25 GPIO PU4 MAX V CPLD R i D P Not used SVD EDP HPD WDT TIME OUT CIE WAREN AF22 VDD RTC LID EE SLEEP MAX V CPLD PEX_WAKE RTC Power PMUTPS65911C 8125 6 8127 8128 8129 S130 S131 8132 S133 S134 S135 S136 S137 S138 S139 S140 S141 S142 8143 S144 S145 S146 S147 S148 S149 PMUTPS65911C www kontron com PMUTPS65911C e frr HU IIS me E m ULPI DATA3 PMUTPS65911C PMU TPS65911C and MAX V CPLD GMI_OE Pull up Pull down option MAX V CPLD BI Tiedto GNDto indicate 1 8V I O 5155 FORCE RECOV S156 BATLOW S157 TEST S158 VDD_IO_SEL www kontron com 4 2 JTAG Figure 12 showsthe SMARC sAT30 JTAG connectorslocation and pin out OVI
2. ii 64 42 2 ConnectorJ1 GPLD JTAG nun ence en dr de Eb ne 66 3 www kontron com 5 SMARGSATSD EG 67 Dal Watchdog TIME E 67 5 1 1 CPLD Watchdog Time 67 5 1 2 Tegra T30 SoC Watchdog Timer 67 5 2 PMUGPIO elg 67 5 3 SMARGSATS0 VO ini a 69 Ee 74 5 5 SMARC sAT30 Power Management 74 516 BoardllD EEPROM namin ae 75 5 Thema Design GonsiderdllOllB eet geen 76 6 1 Thermal Management zoe shine en n dei edh Up edin 76 6 2 Heat Spreader Dimensions iii 76 Gr DN EE 77 6 4 Operation without a Heat Spreader Heat Sink i 77 DEN S SL ET Aa SOMWA jap OE 78 ZA ener m 78 Kl A II A ae 78 7 3 SMARC sAT30 Linux for Tegra Modifications AA 78 7 4 Kontron BSP Board Support Package 78 RE E e ricatdea hl 79 8 1 SMARC sAT30 Boot Up Sequence sse netten tenente tenen 79 82 BOOT Selection EE 80 St SMARGSATSU Programming Methods nee ee 82 9 1 eMMC Flash amp External SD Card Programming Using Force Recovery Method 82 9 2 SPI Flash Programming ra solaiioneficef gni assenze ht dit 82 10 Appendix A Major Components BOM sesenta tnter tens 83 11 Appendix B Document Revision History inni 84 4 www kontron com Table of Figures Figire 1 SMARCG SATSO Block RENE 11 Figure 2 T30 Module LVDS LCD Implementation 15 Figure 3 T30 Module Parallel LCD Implemerntsl
3. in 0 25 C increments Only the two MSB s are used so you will only get 0x00 0x40 0x80 OxcO for 0 0 0 25 0 50 and 0 75 respectively To read the local NCT72 measured ambient temp run I2cget y Ox4c 0x00 This will return the local temp in binary in 1 C increments There is no added granularity register for the local temp The CPU thermal diode readout is a valuable tool to use during system development It should be used to characterize and qualify the system thermal solution 5 5 SMARCSAT30 Power Management The SMARC sAT30 module supports the following system and power management modes LPO Deep Sleep Mode LP1 Sleep Mode Active Mode Low Power mode support and supported resume events are software dependant Please consult the software release notes available with the SMARC sAT30 board support package at http emdcustomersection kontron com www kontron com 5 6 Board ID EEPROM The SMARC sAT30 module includes an I2C serial EEPROM available on the 12C_PM bus An Atmel 24C32 or equivalent EEPROMis used in the module The device operates at 1 8V The Module serial EEPROMis placed at 12C slave addresses A2 A1 AO set to 0 I2C slave address 50 hex 7 bit address format or AO A1 hex 8 bit format for DC EEPROMs address bits AG A5 A4 A3 are set to binary 0101 convention The module serial EEPROM is intended to retain module parameter information including serial number The module serial EEPROM
4. Bottom Caution 1 45 mm maximum without PCB whereas the SMARC specification defines as 1 3mm as the maximum 3 4 4 Layout Diagrams Top side major component IC and Connector information is shown in Figure 7 and 8 SMARC sAT30 Top side components 52 3mm 39 9mm 4X 2 7mm 6mm PAD M2 5x4mmSCREW 27 4mm 50 0mm 42 4mm 22 0mm 12 0mm TYP 4 0mm TYP 23 0mm 33 5mm 82 0mm 2x 4 2mm 6 2mm PAD M2 5x3mm STANDOFF HEAT SPREADER MOUNTING Figure7 SMARC sAT30 Top Side Components www kontron com DDR3 REGULATOR Je 000000 S PIN 1 Se BL B DDR RANKO DO 0 7 al a 200000 5 Q ER UA DIO m 0 V 1V2 3 REGULATOR FREE ET m 0000 00 00 00 00 oo ES o s si ET HE TW ACCU 0000 00000000000000000 oo o o o oo o oo o o o 0000 00000000 1000000000 000000000000 o EXE HE a mmm SE Pi ooo oo oo oo oo oo oo oo ooo 0000000 T30 CPU U10 V_3V3 REGULATOR J3 EDGE FINGER PRIMARY SIDE 3 0000000000000000 75 Figure 8 SMARC sAT30 Top Side Components Labeled Bottom side major component IC amp Connector information is shown in Figure 8 SMARC sAT30 Bottom Side Components SMARC sAT30 height information is shown in Figure 9 SMARC sAT30 Edge View below U16 o o DI 000 0000 000 0000 000 0000 000 0000 e o 0000 DDR RANKO DQ 116 23 SPI FLASH HOLVINDIN ABLS DAS A o o DDR RANKO DA 24 31 eMMC FLASH
5. Module LVDS transmitter the GBE controller and miscellaneous Module circuits The figures below given below are subject to change t ctiv CPUFI PCle GB SA Active state n dp 1 2 GHz QC Linux Desktop Active state 1 2 GHz QC MPEG4 decode Active state All 4 cores 1 2 GHz QC Stress Test 100 load Active State 1 2 GHz QC MPEG4 decode Active State 1 2 GHz QC MPEG4 decode Sleep State Power Save mode enabled co o MI o o State P1 P0 Sleep State P1 DeepSleep LPO State There are many options configurable in software And there are trade offs for example the Power Save option does save power and the response to events such as keyboard and mouse activity can be sluggish Evaluation units are available from Kontron to allow users to check out some of these tradeoffs Mi L L L MI o o www kontron com 3 6 Environmental Specification 3 6 1 Operating Temperature The SMARC sAT30 module operates from 0 C to 60 air temperature with a passive heat sink arrangement Higher ambient temperature performance may be achieved with a passive or active cooling solution and will depend on system level thermal properties 3 6 2 Humidity Operating 10 to 90 RH non condensing Non operating 5 to 95 RH non condensing 3 6 3 RoHS Compliance The SMARC sAT30 module is compliant to the 2002 95 EC RoHS directive www kontron com 4 Connectors 4 1 SMARCsAT30 Edge Co
6. Module for the GbE controller described in Section 3 2 13 Gigabit Ethernet Controller GbE Interface Two are used for SMARC external PCle interfaces PCIe interfacesignalsareexposedonthe SMARCsAT30edgeconnectorasshownbelow PCle_Link A P89 PCIE A TX AF21 PEX L4 TXP PCIEA TX P Differential PCle Link A transmit data pair 0 Series decoupling caps are provided PCIE_A_TX AG21 PEX L4 TXN PCIEA TX N gt in the Module P86 PCIE A RX AH24 PEX L4 RXP PCIEA RX P Differential PCle Link A receive data pair 0 Series coupling caps are not provided in the P87 PCIE A RX AJ24 PEX L4 RXN PCIEA RX N Module P83 PCIE A REFCK AB23 PEX CLK2P PCIEA REF CLK P aaa P84 PCIE A REFCK AB24 PEX CLK2N PCIEA REF CLK N reference clock output P78 PCIE A CKREQ AD26 PEX L1 CLKREQ PCIEA CLK REQ PCle Port A clock request input P74 PCIE A PRSNT AD24 PEXL1 PRSNT PCIEA PRSNT PCIe Port A present input PCle Port B reset output active low Provision is provided to P75 PCIE A RST4 AG27 PEX L1 RST T30 PCIEA RSTH connectpin P75to GMI_AD15 F1 through a 0 ohm resistor R303 R303 should not be installed PCle LinkB S90 PCIE B TX AF18 PEX LO TXP PCIEB TX P Differential PCle Link B transmit data pair 0 591 PCIE B TX AG18 PEX LO TXN PCIEB TX N ut provided in the Module www kontron com SMARC sAT30 Edge Finger NVIDIA T30 CPU Net Name 587 PCIE B RX AH19 PEX LO RXP PCIEB RX P Differential
7. Old VI Og 1 Figure 13 SMARG sAT30 JTAG Connectors 4 2 1 Connector J2 T30 CPU JTAG T30 SoC JTAG connector pin1 8 location detail is shown in the figure below P74 P75 P156 Figure 14 T30 CPU JTAG www kontron com Connector JST SM10B SRSS TB 1mm pitch R A SMD Header Li E mm E er Fee E m NN 1 wa i mum E i Caution The JTAG portis for internal use only Do not connect any devices www kontron com 4 2 2 Connector Ji CPLD JTAG CPLD JTAG connector pin1 8 location detail is shown in the figure below PIN ovir ado S O OG 5 0000000000 I DODDODOL Figure 15 CPLD JTAG Connector JST SM08B SRSS TB 1mm pitch R A SMD Header V_3V3 3 3 Volts JTAG_CPLD_TDI C pee UN cl No Connect Caution The JTAG portis for internal use only Do not connect any devices www kontron com 5 SMARC sAT30 Special Features 5 1 Watchdog Timer The SMARC sAT30 module implements two Watchdog Timers WDTs Each one of these options is described below 5 1 1 CPLD Watchdog Timer TBD This feature is yet to be implemented This is the functionality described by the SMARC Specification 5 1 2 TegraT30SoC Watchdog Timer NVIDIA s Tegra T30 features an internal WDT Kontron s Linux kernel enables the internal T30 WDT and makes this functionality available to users through the standard Linux Watchdog API A description of the API is available following the link be
8. com er H35NI3 3903 USB port power enable and over current logic implementationbetweenthe CPLD and SMARC sAT30 edge connectoris shown in the table below to loto Ire usBo EN OCH EN USBO VBUS OC PSR FIGHE BOWeren DIS over current indication signal Ko pe Ire USBI EN OCH EN USBI VBUS OCH oe NE ore current indication signal L10 on pri USB2 EN OCH EN USB2 VBUS OC Ree current indication signal Power distribution for external USB plug in peripherals USB memory sticks cameras keyboards mice etc is typically handled by USB power switches such as the Texas Instruments TPS2052B Micrel MIC2026 1 or similar devices on the Carrier board The Enable pin on the Carrier board USB power switch must be active high and the Over Current pin OC must be open drain active low these are commonly available No pull up is required on the USB power switch Enable or OC line they are tied together on the Carrier and fed to the Module USBx EN OGt pin The pull up is on the Module e USBx_VBUS DV Pwr Switched Pwr IT USBx_EN_OC Enable TPS2052B OC SMARC CARRIER MXM3 CONNECTOR J40 Figure5 USB Power Distribution Implementation on Carrier www kontron com 3 2 13 PCle Interfaces The SMARC sAT30 module supports two external PCle x 1 interfaces designated PCIE A and PCIE Bin the SMARC specification Of the three the NVIDIA T30 CPU PCle interfaces one is used on the
9. for handling electrostatic discharge sensitive devices 2 1 8 www kontron com Feature Set Overview SMARC compliant in an 82mm x 50mm form factor NVIDIA Tegra 3 quad core ARM Cortex A9 SoC Upto 1 3GHz operation Quad core operation restricted temperature range Upto 1 2 GHz operation Quad core over 0 60 C temp range with appropriate heat sink Upto 1 4 GHz operation Single core mode Up to 2GB of DDR3 SDRAM support On board NAND flash eMMC support upto 64GB On board Intel 1210 Springville GbE controller Single channel 18bit LVDS display support 24 bit 18 bit compatible as well 24 bit parallel LCD display support HDMI output 1 8V Module I O support GPIO support SDIO support 128 support DC support Two Serial Camera interfaces CSI Two PCle ports USB and USB On The Go OTG support Watch Dog Timer WDT support UART support SATA support 2 2 Software Support Hardware Abstraction The Kontron sAT30 Module is supported by Kontron BSPs Board Support Package The first SAT30 BSP targets Linux support and is available under Kontron part number 771 242 00 BSPs for other operating systems are planned Check with your Kontron contact for the latest BSPs This manual goes into a lot of detail on I O particulars information is provided on exactly how the various SMARC edge fingers tie into the NVIDIA SoC an
10. period The LVDS clock edges are off from the 7 bit frame boundaries by 2 pixel periods Unfortunately there are two different 24 bit color mappings in use The more common one sometimes referred to as 24 bit standard color mapping is not compatible with 18 bit panels as it places the most significant RGB color data on the 4 LVDS data pair the pair that is not used on 18 bit panels There is a less common 24 bit 18 bit compatible mapping that puts the least significant color bits of the 24 bit set onto the 4 LVDS pair and allows 24 bit color depths T30 CPU U10 AG9 AF16 AF10 AG11 T30 LCD D 0 23 T30 LCD DE T30 LCD HSYNC Lo T30 LCD VSYNC gt T30_LCD_PCLK A3 A4 B4 A2 LVDS XMITTER U25 TI SN75LVDS83B H2 Hi G2 GI E2 E1 C2 C1 D2 D1 LCD LVDS YOP LCD LVDS YON _ LCD LVDS Y1P LCD LVDS Y1N ennio sl LCD LVDS Y2P LCD LVDS YAN LCD LVDS Y3P LCD LVDS Y3N N op LCD LVDS CLKOUTP LCD LVDS CLKOUTN n S125 S126 S128 S129 S131 S132 er 435NI4 3903 S137 S138 S134 S135 Figure 2 T30 Module LVDS LCD Implementation www kontron com The following table details exactly how the NVIDIA Tegra parallel LCD pins are mapped to the on Module Texas Instruments SN75LVDS83B LVDS transmitter For 18 bit displays LVDS channels 0 1 2 are used For 24 bit di
11. the NVIDIA pin names and the SMARC pin names have different assumptions about color mappings which can make things confusing Basically NVIDIA maps the 18 bits or R G B for 6 bit color depth to D17 0 For NVIDIA the extra bits used for a 24 bit color implementation come out on NVIDIA D23 18 The SMARC has a different convention Red is D23 16 Blue is D15 8 and Green is D7 0 For 24 bit implementations all bits are used For 18 bit implementations in SMARC the least significant bits Red D17 16 Green D9 8 Blue D1 0 are dropped www kontron com 19 www kontron com pe fer pe fo fjet I GJ Fr I I BE esper I O Gs EE fe fe fee The LCD DUAL PCK signal is used to latch odd and even pixels into separate latches on the Carrier board for high resolution displays either for parallel LCD implementations or dual channel LVDS The LCD DUAL PCK is derived on the Module from the LCD PCK pixel clock The LCD DUAL PCK is one half the frequency of the LCD PCK clock The Module hardware ensures that the dual pixel clock is phased correctly with the display field The LCD DUAL PCK rising edge is used to latch odd pixels and the falling edge to latch even pixels The upper leftmost pixel in the display image is pixel 1 an odd pixel followed by pixel 2 an even pixel and so on LCD DUAL PCK is generated using the module s CPLD www kontron com 3 2 9 Carrier Based 24 bit Color Depth LVDS The Module parallel LCD pat
12. the SMARC Edge fingers are shown here SMARCSAT30 Edge finger Intel 210 Net Name Notes ER EP eda Bi directionaltransmit receive pair 0 GbE MDIO MC GbE MDIO N to magnetics GENDE BE MONSE Bi directionaltransmit receive pair 1 GbE_MDI1 GbE MDN N to magnetics GJENDE MOIS SENDER Bi directionaltransmit receive pair2 GbE_MDI2 MDI2 GbE_MDI2_N to magnetics GbE MDB Vo SENDE Bi directionaltransmit receive pair3 GbE_MDI3 MDI3 GbE MDI3 N to magnetics GbE_LINK1004 LEDO GE LINK1008 Link speed indiealion LED for 100Mbps open drain P22 GbE LINK1000 33 LED e al e f r 1000Mbps open drain GbE LINK ACT LED2 GbE LINK ACT Link activity LED open drain S146 PEX_WAKE PE_WAKE PCIE_WAKE PCle GbE wake signal www kontron com User s Guide 3 2 16 SDIO Interface The SMARC sAT30 module supports a 4bit SDIO interface per the SMARC specification The SDIO interface uses 3 3V signaling per the SMARC spec and for compatibility with commonly available SDIO cards SDIOinterface signalsareexposedonthe SMARC sAT30edge connector as shownbelow EA SDMMC1_DATO SDIO D 0 SDMMC1_DAT1 SDIO_D 1 SDIO_D2 SDMMC1_DAT2 SDIO_D 2 SDIO_D3 SDMMC1_DAT3 SDIO D 3 L E LAR L signal K u bull SDIO DO SDIO DI SDIO Data SDIO CK SDMMC1_CLK SDIO_CLK SDIO Clock signal SDIO_WP CLK2 OUT SDIO WP SDIO write protect signal SDIO_CD GPIO_PV2 SDIO_CD SDIO card detect SDIO PWR EN DE GPIO PV3 SDIO PWR EN S
13. 1210 Springville MDI 4 pairs for GBE GBE plus support signals LEDs etc 82mm x 50mm Form Factor Controller Figure 1 SMARC sAT30 Block Diagram User s Guide 314 Pin 0 5mm pitch edge finger pattern for use with MXM3 style carrier board connector aka the SMARC Carrier Connector Actual pin order on the connector will differ from what is implied here 24 bit LVDS requires 18 bit compatible display Interfaces shown in gray and with N C designation are not used on this module but may be used on other modules www kontron com User s Guide 3 2 SMARCSAT3O General Functions This section lists the complete feature set supported bythe SMARC sAT30 module 3 2 1 SMARCSAT30 Feature Set The following table summarizes the SMARC features implemented on the sAT30 vs the maximum possible allowed in the SMARC specification All mandatory features required by the SMARC specification are implemented in the SAT30 Module LVDS Display support 1 Yes 1 Parallel LCD support 1 Yes 1 HDMI Display support 1 Yes 1 CSI Camera support Dual and SOA T Quad lanes 2 Yes lane only Quad lane is not supported Parallel Camera support 2 No 0 USB Interface 3 Yes 3 PCle Interface 3 Yes 2 SATA Interface 1 Yes 1 GbE Interface 1 Yes 1 SDIO Interface 1 Yes 1 SDMMC Interface 1 Yes 4 bit is used 1 SPI Interface 2 Yes 2 12S In
14. 24 0mm 50 0mm 10 0mm LVDS TRANSMITTER 12 0mm TYP VUY PU III III III 5158 S1 4 0mmCTYP gt 82 0mm Figure 9 SMARC sAT30 Bottom Side Components www kontron com 2 5X3mm STANDOFF r 3 00mm 3 1mm 1 7mm 5 2 95mm 1 2mm I 1 45mm Figure 10 SMARC sAT30 Edge View 3 4 5 Module Assembly Hardware The SMARC sAT30 module is attached to the carrier with four M2 5 screws A 4mm length screw is usually used The attachment holes are located on the corners of the module Attachment holes have a 6mm diameter pad 2 7 mm dia drill hole as shown Figure7 SMARCSAT30 Topsidecomponents 3 4 6 Module Cooling Solution Attachment Two Penn Engineering and Manufacturing PEM www pemnet com SMTSO surface mount standoffs with M2 5 internal threads and 3mm stand off height are soldered into the Module top side adjacent to the Tegra SoC They are provided for the attachment of a heat spreader or heat sink independent of the corner mounting holes The PEM SMTSO parts have excellent pull strength and the Module PCB will deform before the standoffs can be pulled out The heat sink heat spreader mounting holes are shown in Figure 7 SMARC sAT30 Top side components The Heat Spreader is secured to the Module with two 6mm flathead M2 5 screws For a large area heat spreader or heat sink the corner holes should be used as well with suitable standoffs www kontron com 3 5 Electrical Specificati
15. 3_DAT1 SDMMC3_DAT2 SDMMC3_DAT3 Not used Not used Not used Not used SDMMC3_CLK SDMMC3_CMD SDMMC3_DAT6 CLK1_OUT DAP2_FS DAP2 DOUT DAP2 DIN Through a 33 ohm DAP2 SCLK Series resistor R295 DAP3 FS DAP3 DOUT DAP3 DIN www kontron com User s Guide SMARCSAT30Edge finger Notes pou E f ban Not used Not used 28 3 PCAM ON _CSI1 SPDIF OUT A28 SPDIF OUT SPDIF IN H27 SPDIF IN FB DIFFO Not used m LL mm I mam TT I E E See age Not used Not used AFB DIFF2 A Not used FB DIFF2 GND 546 S47 548 549 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 563 S64 565 566 567 568 S69 70 71 S Not used AFB_DIFF3 www kontron com Io A YA pem pa mxm 00 mw fe mum ee mm fe C a ee er ee NT b P BI ND ND ND CIE_B_REFCK AK28 PEX CLKIN PCIE B RX AH19 PEX LO RXP P B d A m FU IE EC mum me eee mum pe see o EH i pum m mew O mum qe mum m LE EC ms qmm ms I I ms mm ms ee epee I S72 S73 574 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 585 586 87 88 89 S90 S91 S92 S93 S94 S95 S96 97 S www kontron com ESTE m S L S L H L L AAA Coi i A es e CS I IS m CE CS ms pem mm pem mm em p cw a 3 wi IS LI E ms eme I mm emm
16. 4 NAND D4 CT configuration selection strap D2 GMI AD05 NAND D5 BCT DEER selection strap B3 GMI AD06 NAND D6 BCT configuration selection strap BCT confi i GMI_AD07 NAND D7 C OT iguration selection strap GMI_ADV LOT NAND ALE JTAG selection strap GMI CLK oq NAND CLE JTAG selection strap NAND_RE F2 GMI_OE Force recovery selection FORCE_RECOVERY strap G4 GMI_WR NAND_WE Normal ao of T30 CPU selection strap USBO Power enable Si GMI_CS4 EN USBO VBUS CPLD between T30 CPU and CPLD USB1 Power enable GMI_CS6 MS EN USB1 VBUS CPLD between T30 CPU and CPLD USB2 Power enable www kontron com N es USBO Over current USBO OC CPLD indication between T30 CPUandCPLD n gt GMI ADO9 A GMI_CS1 USB1 Over current USB1 OC CPLD indication betveen T30 CPUandCPLD USB2 Over current USB2 OC GPLD indication between T30 CPUandCPLD GbE PCIE DISt GbE disable signal n a GMI_AD14 D MI_AD15 PCIE A RST CARD PEX RST PCle A optional active low reset MFG MODE R T30 CPU manufacturing mode control signal SATA_ACT SATA_ACT_LED SATA activity indicator D5 D MI_WP GMI_CS3 AG30 VI VSYNC S153 CARRIER STBY CARRIER STBYE ea indication LVDST itter I VI DO4 LVDS_SHTDN E disable signal I D06 S133 LCD VDD EN EN VDD PNL LCD Data povver enable E A EN 3V3 FUSE V 3V3 Fuse power enable VI D09 EN 3V3 HVDDPEX Md enable Excessive temperature TEMP ALERT indication signal from temp
17. 51001 1016 12 4 1GB DDR3LV Dram 16 GB eMMC Flash 1 2 GHz Quadcore Commercial Grade T30 SoG 51001 2016 12 4 2GB DDR3LV Dram 16 GBeMMC Flash 1 2 GHz Quadcore Commercial Grade T30 SoC Additional SKUs may become available SKU variations would include alternative eMMC options including possibly no on Module eMMC Check with your Kontron contact or on the Kontron web site for updated information 3 2 5 On board Storage The SMARC sAT30 module supports an 8MB SPI flash memory device The module also supports an eMMC flash option up to 64GB The standard SKUs support 16 GB eMMC flash www kontron com 3 2 6 Clocks A 32 768 KHz clock is required for the Tegra T30 CPU RTC Real Time Clock and PMC Power Management Controller This clock is provided by Power Management Unit PMU The Tegra T30 CPU is provided with a 12 MHz clock using a crystal in normal oscillation mode On chip Oscillator www kontron com 3 2 7 LVDS Serialized LCD Display Interface LVDS LCD operation is not native to the NVIDIA Tegra SoC The Module LVDS output is created on the Module from the Tegra 24 bit LCD parallel data path This is evident in the block diagram above Figure 1 SMARC sAT30 Block Diagram The LVDS color packing used on the Module is in the 18 bit color compatible mode more details on this can be found later in this section and in the Ultra Low Power Computer On Module Hardware Specification The display connection may be 18
18. B4 P115 KB_ROWOO P116 GPIO5 P113 PWM_OUT GPIO6 TACHIN GPIO7 PCAM FLD GPIO8 CANO ERR GPIO9 CAN1_ERR ULPI DATA6 P118 GPIO10 KB ROW06 P119 GPIO11 KBROWO09 EN 3V3 GbE GPIO5 PWM OUT GPIO6 TAGHIN GPIO7 PCAM FLD GPIO9 GPIO10 GPIO11 User s Guide Default Function Boot code should set this to output high Alternate Function PWM output Default Function Boot code should set this to input Alternate Function Tachometer input Default Function Boot code should set this to input Alternate Function Parallel camera field input signal Default Function Boot code should set this to input Alternate Function General purpose IO Default Function Boot code should set this to input Alternate Function General purpose IO Default Function Boot code should set this to input Alternate Function General purpose IO Default Function Boot code should set this to input Alternate Function General purpose IO V 3V3 GbE power enable www kontron com LVDS Transmitter 24 bi N24 KB ROWO4 LVDS 24BITSEL data enable signal N30 KB ROWO5 LVDS 18BITSEL pisi ad s data enable signal M28 KB ROWO3 BOARD ID WP au nn protect control signal F8 GMI_AD00 ot NAND DO Boot device strap signal GMI_ADO1 GJ NAND DI Boot device strap signal GMI ADO2 e E NAND D2 Boot device strap signal GMI ADO3 e J NAND D3 Boot device strap signal BCT confi i G2 GMLADO
19. BSP for SMARC sAT30 Module Kontron part number 771 242 00 www kontron com 3 1 Specifications Functional Block Diagram Power In 3 0V to 5 25V DC Various Power lg Ser 3 0Vto 5 25V 0 na Supplies l i2c PM WDTO upplies CPLD_JTAG SS Y Boot Device Select JTAG aBootStraps CPLD Misc Ctrl Out Reset etc Misc Ctrl Ou Misc Misc Ctrl In gt 2 G Byte SKU 4x 4Gbit Misc Ctrl In Logic Pwr Btn etc 1 G Byte SKU 4x 2Gbit Pix Ck Dual Channel Pixel Cloci DDR3L 18 24 Bit 512M x 8 DDR DQ31 DQ24 LVDS LVDS gt R or I2C_GP CPLD JTAGJ Xmiter 256M x 8 RGB LCD Data and Control DDR3 L HDMI 512Mx8 DDR DQ23 DQ16 lt gt or lt CSI 2 2 Pair 256M x 8 C92 4 Pair DDR3L PIO 12 Bit PWM Tach en UARTs 2x 2 Wire and 2x 4 Wire 256M x 8 Sposi gt DDR3L SDMMC 4 bits used SMARC supports up to 8 512M x 8 DDR DQ7 DQO or I2C 4 instances one dedicated to Power Management 256M x 8 NVIDIA CANI Tegra T30 I2C PM N G Quadcore CPU Serial EEPROM CANO SIN etc N C SPI 2 instances t 125 DAP 3 instances SPDIF SPI Flash GMI SPI 8MB ATA USB Host USB2 Q USB Host HEEL USBOTG Clen Use eMMC PCle C Flash Option MMC NIC 64GB Max PCle x1_ plus support signals PCIE t PCle x1 plus support signals PCIE A PCle xi Intel
20. D card power enable The SDIOcard power should be switched onthe Carrier board andthe SDIO lines shouldbe ESD protected The SMARC Evaluation Carrier schematic is useful as an implementation reference K K K K N K NVI 1 2 3 4 6 5 M5 Mi www kontron com 3 2 17 SDMMC Interface for Carrier eMMC The SMARC sAT30 module supports a 4bit SDMMC interface that may be used with a Carrier based e MMC device The SMARC specification provides for an SDMMC data path that may be up to 8 bits wide Only the lower 4 bits are used in the sAT30 implementation EMMC devices that may be used with this interface are required to be able to operate in 1 bit 4 bit or 8 bit modes The signaling level is at the Module I O voltage level of 1 8V SDMMC interface signals are exposed on the SMARC sAT30 edge connector as shown below m rm SDMMC3 DATO T8 SDMMC O SDMMC D5 mn SDMMC3 DAT T8 SDMMC 1 SDMMC3 DAT2 T3 SDMMC 2 SDMMC3 DAT T3_SDMMC 3 SDMMC_RST SDMMC3 GLK T8 SDMMC3 CLK SDMMC3 CMD T8 SDMMC3 CMD SDMMC3 DAT6 WF_RST SDMMC Data Not used Not used Not used Not used SDMMC Clock SDMMC Command Reset signal to Carrier eMMC flash www kontron com 3 2 18 SPI Interfaces The SMARC sAT30 module supports three T30 SPI interfaces One is used on the Module for an 8MB SPI device Two are available off Module for general purpose use SPl interface signals are exposed onthe SMARCSAT 30 edge connector a
21. GE GPIO6 TACHIN G GPIO_PBB4 PIO7 PCAM_FLD A PIO9 CAN1_ERR KB_ROWO1 GPIO10 T ULPI DATA6 Gal EF i K pe BEE BEEN E JE s PWR_I2C_SCL A A PWR 12C SDA ooo BOOT_SEL1 MAX V CPLD AJ4 AK4 AK3 30 N26 25 K28 F26 AA27 G7 26 M23 1 24 M24 N27 P P P P P P P P P P P P P P 100 101 102 103 104 105 106 107 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 P www kontron com User s Guide SMARCSAT30 Edge finger NVIDIA T30 CPU Notes BOOT SEL2 MAXV CPLD RESET_OUT RESET_IN POWER_BTN NE SERO TX ND 7 9 PMU TPS65911C and MAX V CPLD PMU TPS65911C through Level Translator UART2_TXD m p PST Ga M ei pf EE GE E NN EEE Z 9 Not used Not used Not used P12 P126 P127 P128 P129 P130 P131 P132 P133 P134 P135 P136 P137 P138 P139 P140 P141 P142 P143 P144 P145 P146 P147 P148 P149 150 P www kontron com pamm i EN PCAM PXL CKO EE NENNEN feer EEE ER PG AAA ed AAA AAA EA PA poe eee ee e LL po VD AA p i i LO Eu P151 P152 P153 P154 P155 P156 1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 20 S www kontron com User s Guide SMARCSAT30 Edge finger NVIDIA T30 CPU Notes Not used Not used 542 I250 CK C28 543 I251_LRCK R4 S44 251_SDOUT M3 S45 1251_SDIN N3 Not used Not used SDMMC3_DATO SDMMC
22. P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 49 P www kontron com User s Guide SMARCSAT30Edgefinger Notes JL 1 Through 100nF capacitor C92 Through 100nF capacitor C93 Pli_CS1 S S S S SPI2 CSOf USBO HE We SS m NE E N N N SB0 U mM PCIE A PRSNT AD24 PEX L1 PRSNT MAXV CPLD D D PH CK D D USB3 DP P50 P51 P52 P53 P54 P55 P56 P57 P58 P59 P61 P62 P63 P64 P65 P67 P68 P70 P71 P72 P73 74 P www kontron com User s Guide SMARCSAT30 Edge finger NVIDIA T30 CPU Provision to connect pin P75 to GMI AD15 F1 PCIE A RST4 AG27 PEX L1 RST through a 0 ohm resistor R302 By default R302 is Not Installed Tw lue pem eee meme mf gt EN 11 i Li e fs dn mee suna i meme I p meme me qmm gt mm L mmm fee mmm ss mm A E mmm mmm p mme fem gt Ll MOS E EES mmm fem mmm si i E E E mmm ss o mmm fem LN ANNUS ER ERE mem qmm E www kontron com User s Guide HDMI TXCP HDMI TXCN SMARCSAT30 Edge finger NVIDIA T30 CPU Notes NG omr LE E K RE D HDMI DO HDMI TXDON H H HDMI HPD AG13 HDMI INT HDMI CTRL CK AGI4 DDC SCL H DMI CTRL DAT AJ10 DDC SDA P P P P P P P P HDMI_CEG AC18 HDMI_CEG Not used KB_COL00 KB COLO1 P108 GPIOO CAMO PWR J P109 GPIO1 CAMI_PWR CR sedi dl CI m manm Gs dl
23. PCle Link B receive data pair 0 Series coupling caps are not S88 PCIE B RX AJ19 PEX LO RXN PCIEB RX N PCIEB REF CLK P provided in the Module PE CLKIN PE Lo CLKREO PEX LO PRSNT S76 PCIE B RST PEX LO RST PCle Link C PCIE_C_TX NE PCIE C TX E PCIE C RX EE Differential PCle Link B reference clock output PCIEB REF CLK N PCle Port B clock request input PCle PortB present input active low PCle Port B reset output active low Not used S S S Not used E I co meet meme 1e em TA mmm O i ii 81 82 78 80 P Not used PCle Wake 146 PCIE WAKE AF22 PEX_WAKE PCIE WAKE PCle wake up interrupt to host www kontron com 3 2 14 SATA Interface The SMARC sAT30 module supports one SATA port SATA interface signals are exposed on the SMARC sAT30 edge connector as shown below SATA_TX AE16 SATA LO TXP T30 SATA TX P Differential SATAO transmit data Pair Series decoupling SATA TX AD16 SATA LO TXN T30_SATA_TX_N caps are provided in the Module P51 SATA RX AD19 SATA LO RXP T30 SATA RX P Differential SATAO receive data Pair Series decoupling SATA RX AE19 SATA LO RXN T30 SATA RX_N caps are provided in the Module Active low SATA SATA ACT A3 GMI CS3H SATA ACT LEDE dps activity indicator www kontron com 3 2 15 Gigabit Ethernet Controller GbE Interface The SMARC sAT30 module supports one GbE interface Th
24. PU Core Voltage Regulator As the name implies PM Power Management this I2C bus is used by low level software for system power management Two of the Module power regulators are attached to this bus and various voltage levels and options are continuously modified over this interface So use care if accessing this interface TI TPS62361 Buck Regulator www kontron com 3 3 SMARC sAT30 Debug 3 3 1 Serial Port for Linux Debug SMARC module has 4 serial output ports SERO GERT SER2 and SER3 Out of these 4 serial ports SERI is set as the serial debug port use with Linux for Tegra aka L4T SERI is exposed along with all other serial ports available on the module inthe SMARC Evaluation Carrier SERI pin out of the SMARC sAT30 is shown below Asynchronous serial port data out ULPI DATAO SERI TX SERI TXD Asynchronous serial ULPI_DATA1 SER1 RX SER1 RXD i port data in 3 3 2 T30 CPU JTAG A JTAG connector is provided on board for the debugging purpose Connector Reference Designator J2 is used for this purpose Pin out details are provided in section 4 2 1 Connector J2 T30 CPU JTAG www kontron com 3 4 Mechanical Specifications 3 4 1 Module Dimensions The SMARCsAT30complies with SMARC Hardware Specificationina82mm x50 mmformfactor 3 4 2 Heighton Top Caution 3 1 mm maximum without PCB whereas the SMARC specification defines as 3mm as the maximum 3 4 3 Height on
25. Povver Distribution Logic Implementation USB2 OC CPLD GMI_CS2 IO L3 OC JSBo oc oPEB J8B 1 oc oPEB JeB2 oc oPEB H2 L4 L1 L5 L2 L3 The SMARC Hardware specification defines USBx_EN_OC where x is 0 1 and 2 for use with USBO USB1 and USB2 pins as multifunction pins to use for power enable of USBx ports as well as for over current indication The SMARC SAT30 complies with this definition These nets are provided with pull up resistors on the Module The Module CPLD contains the glue logic required for this implementation The sAT30 Module USB power enable and over current indication logic implementation is shown in the following block diagram There are 10K pull up resistors on the Module on the SMARC USBx_EN_OC lines The CPLD outputs driving the USBx_EN_OC lines are open drain The Carrier board USB power switch if present is enabled by virtue of the 10K Module pull up to 3 3V 10K Pull Ups to 3 3V USBO_EN_OC USB1 EN OC USB2 EN OC f mel __ GMI CS14 IO L5 USB1 OC CPLD P62 po o I P71 USB Port0 power enable USB Porti power enable USB Port2 power enable USB port power enable and over current logic implementation between the T30 CPU and CPLD is shown in the following USB Porto over current indication signal USB Porti over current indication signal USB Port2 over current indication signal www kontron
26. Pr O kontron BT SMARG sAT30 User Guide Document revision 1 0 Table of Contents NR leren e EE Im 6 1 1 About This Document 6 1 2 Copyright NOLCO s eoe else stk DE 6 1 3 e ETC 6 1 4 Quality Standards EE 6 UE E Cl EE 6 LR Technical SUDPOM isaac tildes 7 A A 8 2 1 Feature Set OVELVIEW iii 8 2 2 Software Support Hardware Abstraction i 9 2 3 Document and Standards References sse tnter nnne 9 2 3 1 External Industry Standard Documents sssssssssssese eene 9 23 2 KontonDocUMentS cis to 10 233 Kontron Schematics eee old ties 10 2 3 4 NVIDIA Hardware Documents 10 2 9 5 NVIDIA Software DOCUMENTS rave sd laa cene ra de dens 10 2 3 6 Kontron Software BSP 10 oo Al O O E O UC 11 3 1 Functional Block Diagrammi eoe een 11 3 2 SMARC sAT30 General Functions ssssssseseseeeeenenene netten tenente nennen nene 12 3 21 SMARC SAT30 Feature Set 12 322 Form PAO ria deeg ee do Ee 13 323 CPU ii da 13 3 24 Module Memory E E nner 13 3 25 On board Storage hits card ale aliada 13 AO SE 14 3 2 7 Se EVA 15 32 8 Parallel LCD Display Int rfaGe eun a i A 18 3 2 9 Carrier Based 24 bit Color Depth UND 21 3 2 10 High Definition Multimedia Interface HDMI Interface ii 24 3 2 11 Camera Serial Interfaces CSI Interface A 25 KREE 27 2 www kontron com 32 13 PGle nterfaG
27. ST I2G Camera support data Left open to support the CSIO Serial camera selection Left open to support the CSI1 Serial camera selection Camera 0 Power Enable active low output Camera 1 Power Enable active low output Camera 0 Reset active low output Camera 1 Reset active low output www kontron com User s Guide 3 2 12 USB Interfaces The Kontron sAT30 module supports three USB ports USB 0 2 Per the SMARC specification the Kontron sAT30 module supports a USB On The Go OTG port capable of functioning either as a client or host device on the ULP COM USBO port The sAT30 module also supports two additional USB2 0 host ports on SMARC USB1 and USB2 USBinterface signalsareexposedonthe SMARC sAT30 edge connector as shown below SMARCSsAT30 Edgefinger NVIDIA T30 CPU Net Name P66 USB1 USBO Port P60 USBO W2 USB1 DP T30 USBO DP USBO port data pair P61 USBO USB1_DN T30 USBO DN V 3V8 VBUS USB host power P63 USBO VBUS DET ws USB VBUS euer nep VEH When this port is used ofthe netname as a device P64 USBO OTG ID T USBI ID ee active high USB1 Port P65 USB1 T5 USB2_DP T30 USB1 DP USB1 portdata o USB2 Port P69 USB2 pair USB2 DN T30 USB1 DN USB3 DP T30 USB2 DP USB2 port data pair USB3 DN T30 USB2 DN P70 USB2 De co m www kontron com EN_USBO_VBUS_CPLD EN_USB1_VBUS_CPLD EN USB2 VBUS CPLD Figure4 ExternalUSB Port
28. bit or 24 bit but if a 24 bit connection is used then the display must be capable of accepting an 18 bit color packing This is sometimes alternatively referred to as 6 bit pack it s 6 bits per color or 18 bits total For single channel LVDS a display resolution up to approximately 1280 x 1024 may be supported approximate because factors such as Carrier Board trace lengths routing quality cable length and quality Carrier EMI and ESD suppression device selections and display timing particulars can affect the maximum resolution achieved For high resolution displays 1280 x 1024 and higher a Carrier Board based dual channel LVDS transmitter operating from the Module parallel data path should be used instead This is described in a later section For flat panel use parallel LCD data and control information Red Green and Blue color data Display Enable Vertical Synch and Horizontal Synch are serialized onto a set of LVDS differential pairs The information is packed into frames that are 7 bits long For 18 bit color depths the data and control information utilize three LVDS channels 18 data bits 3 control bits 21 bits hence 3 channels with 7 bit frames plus a clock pair For 24 bit color depths four LVDS channels are used 24 data bits 3 control bits 1 unused bit 28 bits or 4 x 7 plus a clock pair The LVDS clock is transmitted on a separate LVDS pair The LVDS clock period is 7 times longer than the pixel clock
29. d to other Module hardware This is provided for reference and context Most of the I O particulars are covered and abstracted in the BSP and it should generally not be necessary for sAT30 users to deal with I O at the register level 2 3 Document and Standards References 2 3 1 External Industry Standard Documents CSI 2 Camera Serial Interface version 2 The CSI 2 standard is owned and maintained by the MIPI Alliance Mobile Industry Processor Alliance www mipi org Y D PHY CSI 2 physical layer standard owned and maintained by the MIPI Alliance www mipi org eMMC Embedded Multi Media Card the eMMC electrical standard is defined by JEDEC JESD84 B45 andthe mechanical standard by JESD84 C44 www jedec org GbE MDI Gigabit Ethernet Medium Dependent Interface defined by IEEE 802 3 The 1000Base T operation over copper twisted pair cabling is defined by IEEE 802 3ab www ieee org Y Y Y Y HDMI Specification Version 1 3a November 10 2006 2006 Hitachi and other companies www hdmi org Y The DC Specification Version 2 1 January 2000 Philips Semiconductor now NXP www nxp com DS Bus Specification Feb 1986 and Revised June 5 1996 Philips Semiconductor now NXP www nxp com JTAG Joint Test Action Group defined by IEEE 1149 1 2001 IEEE Standard Test Access Port and Boundary Scan Architecture www ieee org MXM3 Graphics Module Mobile PCI Express Module Electromechanical Specification Versio
30. data structure conforms to the PICMGO EEEP Embedded EEPROM Specification www kontron com 6 Thermal Design Considerations 6 1 Thermal Management An optional heat spreader plate assembly is available from Kontron for the SMARC sAT30 module The heat spreader plate on top of this assembly is NOT a heat sink It works as a SMARC standard thermal interface to be used with a heat sink or other cooling device External cooling must be provided to maintain the heat spreader plate at proper operating temperatures Under worst case conditions the cooling mechanism must maintain an ambient air and heat spreader plate temperature of 60 C or less The aluminum slugs and thermal pads on the underside of the heat spreader assembly implement thermal interfaces between the heat spreader plate and the major heat generating components on the sAT30 Module About 80 of the power dissipated within the module is conducted to the heatspreader plate and can be removed by the cooling solution You can use passive thermal management solutions with the heatspreader plates The optimum cooling solution varies depending on the SMARC application and environmental conditions 6 2 Heat Spreader Dimensions The SMARC sAT30 module includes two mounting holes for mounting the passive heat sink located to the left and right of the T30 SoC Heat spreader dimensions are shown in the diagram below TIM stands for Thermal Interface Material Figure 16 Hea
31. de with all Module features USB PCle GBE SATA enabled has a typical power consumption of 5 5W This yields a calculated CPU die temperature of 87 C pretty close to the Tegra limit The stress test at 7W puts the Tegra well over the die temperature limit if there is no heat sinking www kontron com 7 SMARC sAT30 Software 7 1 Introduction Software in the SMARC sAT30 is derived from the Linux for Tegra software release provided by NVIDIA Without changing any core functionality the software has been customized to enable native peripherals on the SMARC sAT30 module and also to support additional features http developer nvidia com mobile linux tegra The SMARC sAT30 bootloader is based in U Boot http www denx de wiki U Boot 7 2 Linux for Tegra The initial customer release for the SMARG sAT30 software package is based in Linux for Tegra release 15 based on Linux kernel version 3 1 10 Linux for Tegra is an NVIDIA Linux package that has been customized to support its Tegra series processors More details can be obtained from htip developer nvidia com mobile linux tegra 7 3 SMARC sAT30 Linux for Tegra Modifications NVIDIA has made available an evaluation platform named Cardhu Kontron has performed a few modifications to the Linux for Tegra package available for Cardhu Updated U Boot bootloader and enabled support for various LVDS panels Updated Kernel configuration file to
32. e Copyright 2012 Kontron America Inc All rights reserved No part of this document may be reproduced transmitted transcribed stored in a retrieval system or translated into any language or computer language in any form or by any means electronic mechanical photocopying recording or otherwise without the express written permission from Kontron 1 3 Trademarks The following lists the trademarks of components used in this board NVIDIA Tegra ARM and all other products and trademarks mentioned in this manual are trademarks of their respective owners 1 4 Quality Standards Kontron is certified to ISO 9000 Quality Standards 1 5 Warranty This Kontron product is warranted against defects in material and workmanship for the warranty period from the date of shipment During the warranty period Kontron will at its discretion decide to repair or replace defective products Within the warranty period the repair of products is free of charge as long as warranty conditions are observed The warranty does not apply to defects resulting from improper or inadequate maintenance or handling by the buyer unauthorized modification or misuse operation outside of the product s environmental specifications or improper installation or maintenance Kontron will not be responsible for any defects or damages to other products not supplied by Kontron that are caused by a faulty Kontron product 6 www kontron com 1 6 Technical Supp
33. e exposedonthe SMARCSAT30 edge connector as shownbelow SMARCSAT30 Edgefinger NVIDIA T30 CPU ra De me I MN HDMI Differential Signals HDMI DO HDMI TXDOP HDMI TXDO P HDMI Differential Data u HDMI DO HDMI_TXDON HDMI_TXDO_N pair 0 output HDMI Dt HDMI TXDIP HDMI TXD1 P HDMI Differential Data p HDMI Di HDMI TXD1N HDMI TXD1 N pair 1 output HDMI_D2 HDMI_TXD2P HDMI TXD2 P HDMI Differential Data HDMI D2 HDMI TXD2N HDMI TXD2 N pair 2 output P101 HDMI CK HDMI TXCP HDMI TXCLK P HDMI Differential P102 HDMI CK HDMI TXCN HDMI TXCLK N clock output HDMI Support signals P104 HDMI HPD AG13 HDMI INT HDMI HPD AP PONA Hot Plug Detect input P105 HDMI_CTRL_CK AGt4 DDC_SCL HDMI_DDC_SCL_1V8 an 12C Clock P106 HDMI CTRL DAT AJ10 DDC SDA HDMI DDC SDA 1V8 a P107 HDMI CEC AC18 HDMI CEC HDMI_CEC The Carrier board must do voltage translation for the DDC and HPD signals as well as ESD protection on all the HDMI signals The Carrier board ESD protection is important as HDMI is a hot pluggable interface A device such as the Texas Instruments TPD12S016 is recommended The Kontron SMARC Evaluation Board schematic KAI 501 146 is useful as an implementation example www kontron com 3 2 11 Camera Serial Interfaces CSI Interface The SMARC sAT30 module supports two dual lane CSI interfaces named CSIO and CSI1 according to the SMARC Hardware specification The SMARC four lane CSI interface option is not s
34. er to set the CLKSEL pin on the 2 transmitter to the opposite edge The first transmitter for odd pixels should be set tolatch the data on the rising edge of LCD DUAL PCK The second transmitter for even pixels should be set to latch the data on the falling edge of the LCD_DUAL_PCK The following table shows how the sAT30 LCD pins should be mapped to a particular LVDS transmitter the TI SN75LVDS83B for standard LVDS 24 bit color packing single and dual channel The chart shows pin numbers for the BGA version of the part The TSSOP version can be used as well although the pin numbering is different The pin names remain the same Transmitters from other vendors may be used as well For dual channel implementations the same data path pin mapping is used for both channels i e the LVDS transmitter LCD parallel data inputs are to be connected in parallel www kontron com Ca au TT oil LE AN ER mr a LING NN lc LI NU n mw CECR ps Je ica LN NN pn G R i m vi pe RR ms M Bre P LE ER LM ERES ee Es pea me ENS de E MN E puo mU pm e pmo am E oe GE PE JI gt e PE pu www kontron com S100 LCD D7 Ga S123 LCD PCK S142 LCD DUAL PCK CLKIN Single Channel Only Dual Channel Only www kontron com 3 2 10 High Definition Multimedia Interface HDMI Interface The SMARC sAT30 module supports a single HDMI interface with a resolution upto 1920x1080 pixels HDMI signals ar
35. erature sensor LCD PWR2 127 LCD_BKLT_EN LCD_BL_EN LCD Backlight Enable J27 SDMMC3 DAT4 EN_3V3_EMMC ee EN Mn power enable Reset signal to the carrier K24 SDMMC3 DAT6 37 SDMMC RST WF RST eMMC device M5 GPIO PV2 SDIO CD SDIO CD SD Card detect signal AE27 AG29 lt AE29 VI D08 AD28 AG6 GPIO PCC2 AH12 www kontron com In opto pra PV3 Im sop PWR_EN ann PWR_EN SD Card Power enable Card Power enable aca CLK2 OUT Re SDIO WP SDIO_WP Se Card write protect indication DAP1_FS S156 BATLOW BATLOW ow Daner denon fromthe carrier ES PUA S141 LCD BKLT PWM Co BL PWM LCD BE PWM output T3 ULPI_DATA3 S151 CHARGING CHARGING rici oaa charging activity indication signal www kontron com 5 4 Temperature Sensor The SMARC sAT30 module features a temperature sensor available on the I2C PM bus An On Semiconductor NCT72 has been used to implement this feature I2C address information to access this device is provided in section 3 2 22 12C Interface The temperature sensor allows two temperatures to be read 1 the Tegra SoC internal thermal diode and 2 the sAT30 Module ambient PCB temperature The temperatures can be read via Linux command line functions or via the BSP To read the CPU temp run the commands i2cget y Ox4c 0x01 i2cget y Ox4c 0x10 The first command gives you the temp in binary in 1 C increments The second command gives you added granularity in binary
36. es u vde da aaa 30 3 2 14 SATA Interface De ae 32 3 2 15 Gigabit Ethernet Controller GbE Interface AAA 33 3216 SDIO Interface ein ee 35 3 2 17 SDMM Interface for Carrier et 36 3 2 18 SPlIniterfaces e ede P eme e ie EE Ee ERE ER iaia 37 3 219 EE 38 3 2 20 SPDIF Interface visir e e e d a ad e o E E PL De du 39 3 2 21 Asynchronous Serial Porte 40 32 22 PC Interface ee iena 41 3 3 SMARG SAT30 Debug sansen pee Ui aie to tcr uas dba are 43 3 3 1 Serial Port for Linux Debug essent tnnt tenni 43 332 TSO ad OD u ea ALLE Rea genesi Leali a a eee 43 3 4 Mechanical Specifications vinos 44 3 4 1 Module DIMENSIONS ssion re penare dh hd 44 3 42 eighton Top 2 en ee eret a 44 3443 Height on Bottom 44 9 4 4 Layout Diagrams cirio d d De dE E dea e under 44 3 45 Module Assembly T 46 3 4 6 X Module Cooling Solution Attachment 46 3 5 Electrical Specification sss nennen tentent ettet tette tete tenete entes 47 3 5 1 JA 47 35 2 RTEBackup Voltage urtare edile dredh e 47 3 5 3 No Separate Standby Voltage EEN 47 354 Modulel O Voltage escocia ot 47 3 5 5 Power Consumption rua ana e 48 3 6 Environmental Specification iii 49 3 6 1 Operating Temperature 49 362 UD re SE 49 3 6 3 ROHS Compliance in stan areas 49 EGP ad 50 4 1 SMARC sAT30 Edge Connector Pin Mapping seen 50 4 2 STAGE A ED Eee E N dede 64 4 2 1 Connector J2 T30 CPUJTAG
37. etails are provided in the section 8 2 BOOT Selection The boot ROM on the Tegra 3 device fetches the Boot Configuration Table BCT and boot loader from the secondary boot device If the BCT and boot loader are fetched successfully boot ROM on the Tegra 3 device yields to the boot loader Otherwise boot ROM onthe Tegra 3 device enters USB recovery mode Note The SMARC sAT30 uses U Boot boot loader The boot loader configures processor memories and essential peripherals into known and usable state The boot loader then loads the kernel image and jump to kernel The kernel sets up the processor and all peripherals as per configuration 10 Kernelstarts various kernel daemons and processes 11 Finally kernel loads the file system and OS desktop Kontron has described the SMARC sAT30 boot sequence in the Booting SMARC white paper available in the EMD Section http emdcustomersection kontron com This is an interesting and insightful read Kontron encourages userstoreadthis documentandlearnhowto enablethe power ofthis architecture www kontron com 8 2 BOOT Selection SMARC sAT30 module can be booted from various devices or modules The boot selection is done in the carrier board By default module eMMC Flash isthe source Boot options supported by SMARC sAT30 are shown in the table below ModuleeMMC Flash mu Module SPI Carrier SATA Caution A BOOT_SELx combination not contained in the table above is not valid T
38. ge connector as shown below SMARCSAT30 Edge finger NVIDIA T30CPU I Net Name I2C PM CK M24 PWR_I2C_SCL PWR I2C SCL 1V8 Power management 12C bus clock DC PM DAT N27 PWR DC SDA PWR 120 SDA 1V8 Power management I2G bus data GPI2C 548 DC GP CK G5 549 DC GP DAT G7 CAM I2G 85 GC CAM CK AG5 PMI2C P121 P122 GENE AU SELVE General purpose 12C bus clock GEN2_12C_SDA GEN2 12C SDA 1V8 General purpose 12 bus data CAM_12C_SCL 12C_CAM_CLK 12C Camera support clock s7 IC CAM DAT AH7 CAM I2C SDA PC CAM DAT EC ms Lon s139 120 LCD CK AB25 GEN 120 SCL LCD DDC CLK on bus S140 120 LCD DAT GE PC SDA LCD DDC DATA LGD spia oi hus GEN2 DC SCL Q D di m mE data HDMI I2C P105 HDMI CTRL CK AG14 DDC SCL HDMI DDC SCL 1V8 La RARO P106 JHDMICTRLDAT AJ10 DDC SDA HDMI_DDC_SDA_1V8 i www kontron com User s Guide All five I2C busses originate in the multi master capable 12 controllers within the T30 SoC The only I2C devices on the sAT30 Module are on the I2C PM bus Those devices and their address details are listed in the following table DC PM Bus 0x2D 0x5B General purpose usage address 1 TITPS65911C U7 0x25 Voltage scaling address 2 temperatures can be read 2 OnSemiNCT72 Thermal Sensor U5 0x4C 0x99 CPU Thermal diode board ambient General purpose parameter EEPROM 3 Atmel AT24C32D EEPROM U9 0x50 OxA1 Serial number etc in PICMG EEEP format 4 Us 0x60 0xC1 C
39. h may be used to implement single or dual channel Carrier Board LVDS transmitter s The color packing may be 24 bit or 18 bit Since 18 bit single channel color packing is already available from the Module LVDS only 24 bit color packing is described in this section A single channel implementation uses one SN75LVDS83B or equivalent LVDS transmitter A dual channel implementation uses two transmitters one for the odd pixels and one for the even pixels The input to the two transmitters is the same for both parts they are wired in parallel The odd and even pixels are separated out from the input data by the rising and falling edges ofthe LCD DUAL PCK The follovving pins onthetransmitter are used slightly differently in the single and dual channel cases Pixel Clock Input Ball A2 Pin Name CLKIN For single channel implementations connect to the SMARC LCD PCKpin S123 For dual channel implementations connect to the SMARC LCD DUAL PCK pin S142 Clock Edge Select Ball D4 Pin Name CLKSEL For single channel implementations provide for resistor strapping options to tie this high or low The default strapping should be low which sets the TI LVDS transmitter to latch data in on the falling edge ofthe LCD PCK For dual channel implementations provide for strapping options to tie the CLKSEL pins high or low The two transmitters should have separate strapping options or one set of strapping options and an invert
40. he SMARC sAT30 module will default to boot from the module eMMC Flash if an invalid combination is selected The SMARC sAT30 boot selection is provided from the module CPLD as a 4bit selection to the NVIDIA Tegra T30 SoC The CPLD provides a 3bit selection from the carrier as shown in the table above NAND D 3 0 is allows pull up and pull down in the module for optional boot select configuration F6 NAND DO K6 E BOOT CPLD SELO Sia S T30cpu Ge 4 NAND CELD 4 BOOT CPLD SELI anm pe me J u23 ET BOOT CPLD SEL2 ee 5 Si NAND DI L7 C11 4 Pi25 5 Figure 17 Boot Selection Strap Implementation www kontron com IO Di P123 BOOT_SEL0 BOOT CPLD SELO IO Et1 P124 BOOT_SELt BOOT CPLD SELI IO Cit P125 BOOT_SEL2 BOOT CPLD SEL2 www kontron com 9 SMARCSAT30 Programming Methods 9 1 eMMC Flash amp External SD Card Programming Using Force Recovery Method The SMARC sAT30 module supports Force Recovery through the USBO port This port is configured in client mode vvhile Force Recovery is enabled The follovving procedure is to be follovved to configure the system into Force Recovery mode 1 Hold the Reset amp Force Recovery button for a few seconds Both buttons are located in the SMARC carrier 2 Release the Reset button initially and later release the Force Recovery button 3 Boot firmware will be downloaded to the SMARC sAT30 module iNAND Flash boot dev
41. ice using a flash script provided by NVIDIA Boot firmware can be downloaded to the Module iNAND Flash boot device from a Linux host system A valid SMARC SAT30 file set should be present on the host system The file set will contain the BCT file Boot loader Kernel root file system and some demo applications Refer to the Kontron EMD Website and download a valid BSP A sAT30 BSP will contain all files needed to flash the INAND device Follow the instructions contained inthe sTA30 BSP More details can be found in the Linux for Tegra documentation http developer nvidia com mobile linux tegra 9 2 SPI Flash Programming TBD This feature is not yet supported www kontron com 10 Appendix A ES Em ej Se Ek em m wil E E Springville VVGI210AT Sen S E ONSEMICONDUCTOR NCT72CMTR2G IC EEPROM 32Kbits AT24C32D TSSOP8 ATMEL AT24C32D XHM T IC GPLD 5M240Z MBGA100 EN 5M240ZM1 www kontron com 11 Appendix B Document Revision History Revision Date 1 0 2012 09 27 Editedby Changes SMilnor Initial Public Release User s Guide Corporate Offices Europe Middle East 8 Africa North America Oskar von Miller Str 1 14118 Stowe Drive 85386 Eching Munich Poway CA 92064 7147 Germany USA Tel 49 0 8165 77 777 Tel 1 888 294 4558 Fax 49 0 8165 77 219 Fax 1 858 677 0898 info kontron com info us kontron com Asia Pacific 17 Building Block 1 ABP 188 S
42. ignalthrough leveltranslator DE 148 L LEE Lid open close indication EN 3V3 LAN V Fa pee EN DDR BUCK 1V35 DDR3 Power regulator enable www kontron com 5 3 SMARCsAT301 0 User s Guide The SMARC sAT30 module provides multiple VO lines for various functions 12 l Os lines are used as interrupt capable GPIOs which follow SMARC hardware specification GPIO5 PWM output and GPIO6 Tachometer input support is also provided as per the SMARC hardware specification Caution These details are provided for reference Generally access to the I O is abstracted in the Kontron BSP packages GPIO functionality as well as I O mapping to the SMARC sAT30 connector is shown below z GPIOO CAMO_PWR GPIO1 CAM1_PWR GPIO2 CAMO_RST GPIO3 CAM1_RST GPIO4 HDA_RST Default Function Boot code should set this to output high Alternate Function CAMO active low camera powerenable Default Function Boot code should set this to output high Alternate Function CAM active low camera powerenable Default Function Boot code should set this to output high Alternate Function CAMOactivelowreset Default Function Boot code should set this to output high Alternate Function CAM1 activelow reset Default Function Boot code should set this to output high Alternate Function HD Audio reset active low www kontron com AB27 GPIO PU3 AA27 GPIO PU6 P114 GPIO_PB
43. is is accomplished by using the Intel 1210 Springville GbE MAC PHY using one of the T30 SoC s PCle interfaces This is diagrammed below The PCle coupling caps are not shown in the diagram AH25 GBE PCIE TX Py 5 58 fa GBEMDIOP gp p30 AJ25 GBE PCIE EX 23 57 b SBE MDIO N P29 GBE MDI1 P GBE MDI1 H 55 por E a AG23 GBE PCIE Rx P 94 54 P26 GBE_PCIE Rx N AG22 20 53 4 SBEMDI2P pp 52 GBE MDI2 N p p23 m GBE_PCIE_CLK_P GBE GBE MDI3 P T30CPU J 7 GEE PCIE GIK N 29 CONTROLLER 50 a P20 m U10 AH27 STATE 25 INTELI210 49 g OSBEMDISN po SI U27 2 gt 31 GBE LINK100 gt P21 GBE_PCIE_RST GBE_LINK1000 AG25 PEUT DS 7 33 P22 GBE_LINK_ACT 30 P25 J2 GBE_PCIE DIS 61 16 PCIE_WAKE S146 Figure 6 GbE Controller Implementation The following table details the Tegra to 1210 connection details AH25 PEX L5 TXP PE RX GLE POE DXP Differential PCIe GbE transmit data AJ25 PEX_L5_TXN PE_RX GbE_PCIE_TX_N pair AG23 PEX_L5_RXP PE TX GbE_PCIE_RX_P Differential PCle GbE receive data pair AG22 PEX L5 RXN PE TX GbE PCIE RX N AJ27 PEX CLK3P PECLK GbE PCIE CLK P Differential PCle GbE reference clock AH27 PEX CLK3N PECLK GbE PCIE CLK N AG25 PEX L2 RST PE RST GbE PCIE RSTi PCle GbE reset input GMI_AD14 SDP1 GbE PCIE DIS INTELI210PCleinterfacedisable www kontron com The details of the Intel 1210 mapping to
44. lDl case een ee rrree 18 Figure 4 External USB Port Power Distribution Logic Implementation erne 28 Figure 5 USB Power Distribution Implementation on Carrier sess 29 Figure 6 GbE Controller Implementation tes uni tnra jug snai billion aie n 3d Figure 7 SMARC sAT30 Top Side Components liceali 44 Figure 8 SMARC sAT30 Top Side Components Labeled canarios 45 Figure 9 SMARC sAT 30 Bottom Side Components 4 licei 45 Figure 10 RANE ND 46 Figure 11 SMARC sAT30 edge finger primary DIAS E 50 Figure 12 SMARC sAT30 edge finger secondary PINS rei 50 Figure 13 SMARG SATZOJTAG GONNECHOFS anne 64 Figure 14 T30 CPU JTA sme A AE AAT 64 HE GFED TA espa o sa Sr OTE FETT 66 Figure IB Feat PE ici era 76 Figure 17 Boot Selection Strap Implemenl tien ann ee 80 5 www kontron com 1 User Information 1 1 About This Document This document provides information about products from Kontron and or its subsidiaries No warranty of suitability purpose or fitness is implied While every attempt has been made to ensure that the information in this document is accurate the information contained within is supplied as is and it is subject to change without notice For the circuits descriptions and tables indicated Kontron assumes no responsibility as far as patents or other rights of third parties are concerned 1 2 Copyright Notic
45. low http www kernel org doc Documentation watchdog watchdog api txt 5 2 PMUGPIO The PMU on the SMARC sAT30 contains a few GPIOs These GPIOs are used for power management functionality but can also be used for general purpose I O These GPIOs are different from SMARC sAT30 module hardware specification GPIOs Thetable below showsthe PMU GPIO usage information details Default Function Core power CORE PWR REQ enable signal FI SLEEP S149 SLEEP SLEEP_IN Alternate Function Sleep indication from carrier board INT Eo o PMU INT PMU Interrupt signal Power bad indication from POWER HOLD carrier board used as an option Ni PWRHOLD 5150 VIN PWR BAD 7 to hold the PMU power output VIN_PWR_BAD with AND gate logic with systemreset PWRDN Pf AP_OVERHEAT High Temp warning signal www kontron com RESET_IN L6 HDRST P127 RESET INZ Reset input to the PMU through SYS RESET IN level translator PMU_ONKEY Power button input from carrier E4 PWRON P128 POWER BTN board through zero ohm ONKEY resistor ignal for T H4 NRESPWRON SYS_RESET System reset out signal for T30 CPU PMU_RESET_OUT_1V8 CI NRESPWRON2 P126 RESET OUT System reset out signal for the RESET_OUT carrier board GPIOO EN 5V CHARGEPUMP V 5V0 STBY Power regulator enable SS GPIO2 P EN VDD SoC V 1V2Powerregulatorenable GPIO3 D Peee LED2 Not Used NEN LL NN PRESENT h GPIO4 S152 CHARGER PRESENT Charger present CHARGER PRESENTA s
46. ments TRS3253E the Maxim MAX3218 and the Linear Technology LTC2801 Note that RS232 transceivers invert the signal a logic 1 is a negative voltage 3 0V to 15V and a logic 0 a positive voltage 3 0V to 15V on the RS232 line Asynchronous serial ports interface signals are exposed on the SMARC SAT30 edge connector as shown below SMARCSAT30Edgefinger NVIDIA T30 CPU SERO P129 SERO TX UART2 TXD SERO TXD Asynchronous serial port data out P130 SERO RX AB28 UART2 RXD SERO RXD Asynchronous serial port data in P131 SERO RTSH AB26 UART2 RTSH SERO RTS jin le le ke harer 5 B P132 SERO CTSH AA25 UART2 CTS SERO CTS ads Send handsker Ane fjor Asynchronous serial port data in P138 SER2 RTSH AB29 UART3 RTSH SER2 RTS kann i Sond handske keine dor P139 SER2 CTS UART3 CTSH SER2 CTS send aestieke ne or SER3 P140 SER3 TX ULPI CLK SER3 TXD Asynchronous serial port data out P141 SER3 RX ULPI DIR SER3 RXD Asynchronous serial port data in www kontron com User s Guide 3 2 22 DC Interface There are five 12C buses defined in the SMARC specification PM Power Management LCD Liquid Crystal Display GP General Purpose CAM Camera and HDMI The sAT30 supports multiple masters and slaves in fast mode 400 KHz operation A high speed mode 3 4 MHz option also exists although many I2C peripherals may have trouble with this The 12C interface signals are exposed on the SMARC sAT30 ed
47. n 3 0 Revision 1 1 2009 NVIDIA Corporation www mxm sig org PICMG EEEP Embedded EEPROM Specification Rev 1 0 August 2010 www picmg org Y Y Y Y PCI Express Specifications www pci sig org Y Serial ATA Revision 3 1 July 18 2011 Gold Revision Serial ATA International Organization www sata io org SD Specifications Part 1 Physical Layer Simplified Specification Version 3 01 May 18 2010 2010 SD Groupand SD Card Association Secure Digital www sdcard org SPDIF aka S PDIF Sony Philips Digital Interface IEC 60958 3 SPI Bus Serial Peripheral Interface de facto serial interface standard defined by Motorola A good description may be found on Wikipedia http en wikipedia org wiki Serial Peripheral Interface Bus Y Y Y USB Specifications www usb org 9 www kontron com 2 3 2 Kontron Documents Ultra Low Power Computer On Module Hardware Specification version 1 2 September 19 2012 Kontron 2012 Ultra Low Power Computer On Module Evaluation Carrier User Manual Version 1 0 September 10 2012 OKontron 2012 Ultra Low Power Computer On Module Evaluation Carrier Quick Start Manual Version 1 0 September 10 2012 Kontron 2012 2 3 3 Kontron Schematics The following schematic numbers are listed for reference The Module schematic is not usually available outside of Kontron without special permission The other schema
48. n CK C28 DAP2 SCLK DAP2 SCLK Digital audio clock 1281 S43 Gei LRCK Du DAP3 FS DAP1 FS a 544 Gei SDOUT M3 DAP3 DOUT DAP1 DOUT Digital audio Output 545 1281 SDIN N3 DAP3 DIN DAP1 DIN Digital audio Input S46 Gei CK R6 DAP3 SCLK DAP1 SCLK Digital audio clock 1282 S50 122 LRCK AA24 DAP4 FS DAPO FS i S51 1252 SDOUT W28 DAP4 DOUT DAPO DOUT Digital audio Output 552 ez SDIN AA29 DAP4_DIN DAPO_DIN Digital audio Input S53 1252 CK AA26 DAP4 SCLK DAPO SCLK Digital audio clock Audio Master clock 538 AUDIO MCK C27 On OUT AUDIO MCLK zi Se www kontron com 3 2 20 SPDIF Interface The SMARC sAT30 module supports one SPDIF interface SPDIF interface signals are exposed on the SMARC sAT30 edge connector as shown below S59 SPDIF OUT SPDIF_OUT SPDIF_OUT SPDIF_IN SPDIF_IN SPDIF_IN Digital Audio Output Digital Audio Input www kontron com iS VSS S EE 3 2 21 Asynchronous Serial Ports The SMARC sAT30 module supports four UARTs SERO 3 UARTs SERO and SER2 supports flow control signals RTS CTS UARTs SERI and SER3 do not support flow control When working with Linux for Tegra L4T SER 1 is used for T30 CPU debugging The sAT30 asynchronous serial port signals have a 1 8V level signal swing They can be converted to RS232 level and polarity signals by using a suitable RS232 transceiver There are transceivers available that accept a 1 8V signal level some examples include the Texas Instru
49. nnector Pin Mapping se 0000000000000 00000000000000000 900000000 000000000 900 00 00000000 09 III 00000000 000000000 e 28 00000000 00000000 ss 00088000 00000000 99 999 9 00000000 00000000 3 22 00000000 0000000000 9909990 oe ep 00 00 00 3259009 000000000000000 888000800000000000 a P74 P75 P156 Figure 11 SMARC sAT30 edge finger primary pins Figure 12 SMARC sAT30 edge finger secondary pins www kontron com Pin mapping between the SMARC sAT30 module edge connector and T30 SoC is shown in the table below Connections between the edge connector and other devices on the module are not shown SMARCsAT30Edgefinger NVIDIA T30 CPU P1 PCAM PXL CK1 fr Lo d Not used Z 9 U co I gt m ide i CSI1_CK PCAM_D1 ue FE E NN HU el E FE Se FE Se m HE FE E Z oO CSI_D2BP CSI_D2BN Z oO P13 CSIt_D2 PCAM D fa P14 CSI1_D2 PCAM_D7 P16 CSI1_D3 PCAM_D8 P17 CSI1_D3 PCAM_D9 Z 9 19 GbE_MDI3 P20 GbE_MDI3 P21 GbE_LINK100 P22 GbE_LINK1000 P23 GbE_MDI2 Intel 1210 www kontron com User s Guide SMARCSAT30 Edge finger NVIDIA T30 CPU Notes GbE MDI2 Intel 1210 GbE LINK ACT E MDI1 G Loi A MA Intel 1210 and OD driver GbE LP Intel 1210 e NE NEN EG MIN JE z NE ER See AE16 Through 100nF capacitor C90 SATA_TX AD16 SATA LO TXN Through 100nF capacitor C91 P24 P25 P26 P27 P28 P29 P30 P31 P32
50. on 3 5 1 Supply Voltage The SMARC sAT30 module operates over an input voltage range of 3 1V to 5 25V Power is provided from the carrier through 10 power pins as defined by the SMARC specification Caution The SMARC specification states that the input voltage range should extend down to 3 0V The sAT30 lower limit is determined by a non volatile register setting in the TI PMU used 3 5 2 RTC Backup Voltage 3 0V RTC backup power is provided through the VDD_RTC pin from the carrier board This connection provides back up power to the module PMU 3 5 3 No Separate Standby Voltage The SMARC sAT30 does not have a standby power rail Standby operationis povvered through the main supply voltage rail as definedinthe SMARC specification 3 5 4 Module I O Voltage The SMARC sAT30 module complies with the default I O voltage 1 8V level defined by SMARC Hardware specification Module pin S158 VDD_IO_SEL is tied low on the Module per the SMARC specification indicating a 1 8V I O voltage level www kontron com 3 5 5 PowerConsumption Power figures are given in the table below for the Module power consumption in various situations These are Module power figures Off Module power consumption e g display backlight display power Carrier board devices is not included here What is included in these power figures everything on the Module the Tegra SoC the DDR3L DRAM the eMMC memory the Module SPI the Module power supplies the
51. ort Technicians and engineers from Kontron and or its subsidiaries are available for technical support We are committed to making our product easy to use and will help you use our products in your systems Please consult our website at http www kontron com support for the latest product documentation utilities drivers and support contacts Consult our customer section htip emdcustomersection kontron com for the latest software downloads Product Change Notifications and additional tools and software In any case you can always contact your boardsupplierfortechnicalsupport 7 www kontron com 2 The SMARC Ultra Low Power Computer on Module sAT30 is a versatile small form factor Computer On Module that requires low power and provides high performance at low cost The module connector has 314 edge fingers that mate with a low profile 314 pin 0 5mm pitch right angle connector this connector is sometimes identified as an 321 Introduction pin connector but 7 pins are lost to the key Featuring NVIDIA s Tegra T30 System on Chip Kontron s SMARC sAT30 offers LVDS Parallel LCD HDMI Display Gigabit Ethernet PCle SATA USB USBOTG Camera support and superior graphics performance ina cost effective low power miniature package Kontron s SMARC sAT30 thin and robust design makes it an ideal building block for reliable system design Cautioni The SMARC sAT30 module is ESD sensitive equipment Users must observe precautions
52. outhern West 4th Ring Beijing 100070 P R China Tel 86 10 63751188 Fax 86 10 83682438 info kontron cn www kontron com
53. s shown below SPIO_CSO J SPI1 Cem T3 SPH Cem iu Chip Select 0 i i i i SPIO_CS1 N4 ULPI_STP men eem SP Master Chip Select 1 output SPIO_CK B28 SPI1 SCK T8 SPI SCK SPIO Master Clock output F28 F29 SPIO Master Data input input to CPU output from SPldevice SPIO_DIN SPI1_MISO T8 SPI1 MISO SPIO Master Data output SPIO DO SPI1_MOSI T3_SPI1_MOSI output from CPU input to SPldevice SPI1 Cem G SPI2 Cem T3 SPI Cen e Su SPI1_CS1 F SPI CS14 T3 SPI2 Ce si Chip Select 1 SPI1 CK D29 SPI2_SCK T3_SPI2_SCK SPI1 Master Clock output SPI1 Master Data input SPI1_DIN D30 SPI2 MISO T3 SPI2 miso input to CPU output from SPI device SPI1 Master Data output H SPH DO B27 SPI2 MOSI T3 SPI2 MOSI output from CPU input to SPldevice P54 P55 P56 P57 58 www kontron com 3 2 19 12S Interfaces The SMARC sAT30 module supports three off Module DG DAP interfaces The default SMARC audio interface is 1250 and the Kontron sAT30 bootloader implements this The other 12S ports may be used for audio if the bootloader is re configured for this or may be used for other devices that accept an 12S interface l2Sinterface signals are exposed on the SMARCsAT 30 edge connector as shown below 539 Gen LRCK C29 DAP2 FS DAP2 FS uva 540 Gen SDOUT G27 DAP2_DOUT DAP2 DOUT Digital audio Output S41 1250_SDIN F27 DAP2_DIN DAP2_DIN Digital audio Input 542 Ge
54. splays that accept 18 bit color packing channels 0 1 2 and 3 are used n ER EK LL ER ER KH T V V KZ LAN x SCH ERC ER Eus pe fore EH CH ss qus fee fora LK ER ESCH ES www kontron com x m E9 16 a AGHI LCD_PCLK CLKIN T30_LCD_PCLK rm Ss www kontron com 3 2 8 Parallel LCD Display Interface The NVIDIA Tegra parallel 24 bit LCD interface is brought to the Module edge connector The interface runs at the 1 8V Module I O voltage This voltage swing may be used directly with 1 8V capable Carrier Board LVDS transmitters such as the TI SN75LVDS88B The 1 8V signaling may not be suitable for direct connection to a parallel flat panel Generally speaking only small panels with screen diagonals of 5 or less are available with a 1 8V interface Larger parallel LCD panels are likely to use 3 3V signaling and a set of voltage translators buffers would be needed on the Carrier RED T30 LCD D 17 12 23 22 GREEN T30 LCD D 11 6 21 20 BLUE T30 LCD D 5 0 19 18 g T80 LCD DE Eds A T30 LCD HSYNC S120 dom AF16 GP s122 Z n T30 LCD VSYNC ORG pas T80 LCD PCLK Se ES H11 PLD C 1 T30_LCD_DPCLK 8142 Gio 023 SI F10 Figure 3 T30 Module Parallel LCD Implementation The mapping of the NVIDIA Tegra parallel LCD balls to the SMARC edge connector is shown in the table below Note that
55. support 12C 12S and all embedded interfaces available in the SMARC SAT30 Added support for a set of programmable GPIO s Added support for the Intel 1210 Springville SMARC sAT30 GbE Added support for common miniPCle WiFi devices Various 12C address changes Enabled SATA and PCle Kontron s SMARC sAT30 software documentation and release notes are available for download at the EMD Customer Section http emdcustomersection kontron com 7 4 Kontron BSP Board Support Package The Kontron sAT30 Module is supported by Kontron BSPs Board Support Package The first SAT30 BSP targets Linux support available under Kontron part number 771 242 00 BSPs for other operating systems are planned Check with your Kontron contact for the latest BSPs www kontron com 8 8 1 SMARC sAT30 Boot Brief SMARCSAT30 Boot Up Sequence The following steps define the SMARC sAT30 boot process at a high level 1 8 9 The power supplies on the module will be up and stable at the required voltage level after powering on the system System level hardware executes the power up sequence This sequence ends when system level hardware releases SYS RESET N The boot ROM on the Tegra 3 SoC begins executing and programs the on chip I O controllers to access the secondary boot device Secondary boot device will be selected based on the external boot device selection jumpers which are provided on the SMARC carrier board D
56. t Spreader www kontron c Far Side om The table below describes the function and assembly hardware required by each of the heatspreader holes 3mm standoffs ClearanceforM2 5 Clearance holes M2 5 Threaded Standoffs 3mm captive standoff D Clearance for M2 5 M2 5 thread M3 thread N A 6 3 Thermal Parameters The T30 SoC thermal parameters are shown in the table below Thermal Resistance CPU Junction to ambient 0 4 11 6 CAN Thermal Resistance CPU Junction to case 0yc 1 18 C W Thermal Resistance CPU case to heat spreader far surface 6cs Less than 1 C W A heat spreader is available now from Kontron for the sAT30 Module A passive heat sink solution is pending 6 4 Operation without a Heat Spreader Heat Sink The SMARC sAT30 Module is sometimes used in a room temperature environment without any heat sink at all While it is easy and convenient it is not generally recommended as it can put the Tegra CPU die at or above the 90 C limit depending on what you are running and how system performance parameters CPU speed number of cores active etc At the Linux desktop without any heat sinking at all assuming a typical Module power consumption of 1 6W and an ambient room temperature of 23 C the CPU die would be at about 42 C 1 6W 11 6 C W 23 C The temperature may actually be a bit less as not all of the assumed 1 6W is going to the Tegra Running an MPEG4 deco
57. terface 3 Yes 3 12C Interface 5 Yes 5 CAN 2 No 0 AFB 1 No 0 VO Voltage 1 8V level support Yes I O Voltage 3 3V level support No www kontron com 3 2 2 FormFactor The SMARC sAT 20 module complies with the SMARC General Specification module size requirements in an 82mm x 50mm form factor 3 2 3 CPU The SMARC sAT30 module implements NVIDIA s Tegra T30 quad core ARM processor Y 40nm Tegra T30 Cortex A9 Quad core Y Up to 1 2 GHz Quad core mode over 0 60 C operating temperature range with heatsink Y Up to 1 3 GHz Quad core mode restricted temperature range Y Up to 1 4 GHz Single core mode Y 1 Cache 32KB Instruction cache I Cache and 32 KB Data cache D Cache per core L2 Cache controller configured with 1 MByte of cache RAM Y Power optimized companion CPU core MSelect Data Routing Module Programmable clock generator for power and performance tuning Y 24 5 x 24 5 mm package Allowable CPU junction temperature range 25 C to 90 C Y NVIDIA graphics support GeForce Graphics Processor HDTV capable Video Decode Processor supported standards H 264 VC 1 MPEG4 H 263 DiVX XviD and MPEG 2 Video Encode Processor supported standards H 264 MPEG4 H 263 and JPEG OpenGL ES 2 0 Dual display pipelines 3 2 4 Module Memory The SMARC sAT30 module supports 1GB and 2GB total DDR3L memory through two separate orderable SKU s
58. tics may be available under NDA or otherwise Contact your Kontron representative for more information The SMARC Evaluation Carrier schematic is particularly useful as an example of the implementation of various interfaces on a Carrier board Y sAT30 Module KAI 501 141 latest revision SMARC Evaluation Carrier KARMA Eval Carrier Board Schematic KAI 501 146 latest revision eMMC Mezzanine Schematic KAI 501 151 latest revision KLAS Schematic Hyundai 1366 x 768 Single Ch LVDS KAI 501 162 latest revision KLAS Schematic NEC 1280 x 768 Single Ch LVDS KAI 501 163 latest revision KLAS Schematic Dual Channel LVDS 40 pin VESA Standard KAI 501 165 latest revision Y Y 2 3 4 NVIDIA Hardware Documents NVIDIA T30 Design Guidelines DG 05576 001_v10 Version 10 March 06 2012 NVIDIA T30 Datasheet DS 05160 001_v04 Version 4 0 January 31 2012 Y Y 2 3 5 NVIDIA Software Documents Y NVIDIA T30 Technical Reference manual DP 05644 001 v03 Version 0 3 November 25 2011 Tegra Linux Driver Package Developers Guide PG_06076 R15 Version R15 June 11 2012 Contained in Tegra Linux Driver Package Documents R15 tar Tegra Linux Driver Package Software Features DA 06018 R15 Version R15 June 11 2012 Contained in Tegra Linux Driver Package Documents R15 tar Tegra Linux Driver Package Release Notes R15 DN 05071 R15 Version R15 June 11 2012 Y Y Y 2 3 6 Kontron Software BSP Y Kontron
59. upported The camera interface requirements are bound to the performance of the interfaces native to the NVIDIA Tegra T30 SoC CSI interface signals are exposed on the SMARC sAT30 edge connector as shown below SMARCSAT30Edgefinger NVIDIA T30 CPU Net Name CSIO_D0 PCAM_D12 CSI DIAP CSIO DOA P CSIO Differential data pair0 in CSIo_DO PCAM D13 CSI DIAN CSIO_DOA_N CSIO D14 PCAM D14 CSI D2AP CSIO D1A P CSIO Differential data pair1 in CSIO Camera Interface CSIO CK PCAM D10 CSI CLKAP CSIO CK P CSIO Differential clock in CSIO CK PCAM D11 CSI CLKAN CSIO CK N CSI1 Camera Interface CSI1 DO PCAM D2 CSIO D1 PCAM D15 CSI D2AN CSIO D1A N CSI D1BP CSI1 DOB P CSI1 Differential data pairO in CSI D1BN CSI1 DOB N CSI D2BP CSI1 D1B P CSI1 Differential data pair1 in CSI_D2BN CSI1_D1B_N CSI1 Differential clock in CSI1_DO PCAM_D3 CSI1_D1 PCAM_D4 A A A CSI1_D1 PCAM_D5 GE CSI1_D2 PCAM_D6 p CSIt_CK PCAM_D CSI Camera support signals CAM_MCK CAM MCLK CAM MCLK Master CLK out 5 A A El DI H1 H2 G2 CSH CK P G3 CSIT CK N x IPC CAM CK CAM DC SCL I2C CAM CLK 12C Camera support clock www kontron com CAM_12C_SDA S57 PCAM_ON_CSI0 S58 PCAM ON CSI14 KB COLOO KB COLO1 KB COL02 SDMMC3 DAT 7 GPIO0 CAMO_PWR GPIO1 CAM1_PWR GPIO2 CAMO_RST GPIO31 CAM1_RST DC CAM DAT GPIOO CAMO_PWR GPIO1 CAM1_PWR GPIO2 CAMO_RST GPIO3 CAMI_R

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