NIMbox/NEMbox FPGA / VHDL Self Made Firmware Handbook
Contents
1. LVTTL NEL Sula 7 5s LOC P180 IOSTANDARD LVTTL NET SU lt cLS lt 26 gt LOC P132 IOSTANDARD LVTTL NET SU lt 1 gt lt 27 gt LOC P175 IOSTANDARD LVTTL NET Syns LOC P182 IOSTANDARD LVTTL NET SU lt ls lt 279 gt LOC P167 IOSTANDARD LVTTL NET SU lt 1 gt lt 30 gt LOC P135 IOSTANDARD LVTTL NET SU lt 1 gt lt 31 gt LOC P128 IOSTANDARD LVTTL NET SUX1 gt lt 3 gt LOC P137 IOSTANDARD LVTTL SU lt 2 gt NET SU lt 2 gt lt 3 gt LOC P190 IOSTANDARD LVTTL NET SU lt 2 gt lt 4 gt LOC P191 IOSTANDARD LVTTL NET SU lt 2 gt lt 52 LOC P194 TOSTANDARD LVTTL NET SU lt 2 gt lt 6 gt LOC P196 IOSTANDARD LVTTL NET SU lt 25 lt 7 gt LOC P198 IOSTANDARD LVTTL NET SuU lt 2 gt lt sS LOC P199 IOSTANDARD LVTTL NET SU lt 2 gt lt 9 gt LOG PLE IOSTANDARD LVTTL NET SU lt 2 gt lt 102 LOE LE PL IOSTANDARD LVTTL NET SUY lt 2 gt lt 11 gt LOG TRTA IOSTANDARD LVTTL NET SU lt 2 gt lt l7 gt Loe Sea IOSTANDARD LVTTL NET SA SN LOG VPT IOSTANDARD LVTTL NET VS gt lt A LOG PT IOSTANDARD LVTTL NET sU lt 2 gt lt 15 gt LOC P203 IOSTANDARD LVTTL NET SU lt 2 gt lt 165 gt LOC P204 IOSTANDARD LVTTL NET SU 251 LOG VP IOSTANDARD LVTTL NET SU lt 2 gt lt ee LOG Hey IOSTANDARD2. DATA Lien ES IOCOTOEn ag eV out LED ri C DIOZOUT D D Please refer to the ADS5500 datasheet for functions June 14 14 Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH 3 10 SU707 LVDS I O submodule 3 10 1 General Description The module contains 8 LVDS I Os which are separated into two groups of RJ45 receptacles Every group 1 2 has 4 channels A D and can be programmed within those groups whether as inputs or outputs 3 10 2 SU707 LVDS IO pin assignment Pin numbers are in pale green as from top view to connector Left half gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA in out JuvDs 1e7 gt 18 d7 LvDS lt B gt ir ou out IEN Ges 22 21 JeNI t gt lout 2 25 JHGHZo The conversion is done via SN75LVDS391PW transceiver chips so that all levels are LVTLL Refer to the datasheet for I O directional checks EN signals are directly passed to the FPGA June 14 15 Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH 3 11 SU709 Temperature Sensors submodule 3 11 1 General Description This submodule serves as interface to the SMT16030 SMARTEC temperature sensors which contain integrated analogue to frequency converters There the temper
3. LVTTL NET SU lt 2 gt lt 19 gt LOC P185 IOSTANDARD LVTTL NET SG LOC P187 TFOSTANDARD LVTTL NET SUSEN LOC S PILS IOSTANDARD LVTTL NET SU lt 2 gt lt 22 gt LOC PIG IOSTANDARD LVTTL NET TSUL2 gt lt 23 gt HOG RT IOSTANDARD LVTTL NET TSU lt 2 gt lt 24 gt ROC EH IOSTANDARD LVTTL NET HE 75S LOC P183 IOSTANDARD LVTTL NET SU lt 2 gt lt 26 gt LOC P205 IOSTANDARD LVTTL NET SY TV LOC P189 IOSTANDARD LVTTL NET SSK LOC P197 IOSTANDARD LVTTL NET TSU lt 2 gt lt 29 gt LOC Pp os IOSTANDARD LVTTL NET Sua2 gt lt 305 LOG Po IOSTANDARD LVTTL NET SYSE LOC PRE IOSTANDARD LVTTL NET SUR S lt 30 gt LOC PA IOSTANDARD LVTTL June 14 8 0000 A0 User s Manual NIMbox NEMbox FPGA SU lt 3 gt NET Ach LOC P46 TOSTANDARD LVTTL NET SU lt 5 gt lt gt LOC P46 TOSTANDARD ETE NET SUYLS gt lt AS AT LOC p44 IOSTANDARD LVTTL NET SuU lt s gt lt o gt LOC P45 IOSTANDARD ke KEE NET Ee Ch LOC P42 IOSTANDARD HVETE NET SULS LOC P43 IOSTANDARD LVTTL NET SUS SG LOC p39 IOSTANDARD LVTTL NET SU lt 3 gt lt 10 gt LOC P40 TOSTANDARD LVTTL NET SU lt 3 gt lt 11 gt LOC P36 IOSTANDARD LVT TPE NET SU lt 3 gt lt 12 gt LOC p37 TOSTANDARD LVTTL NET SU lt 3 gt lt 135 gt 5 LOC P51 TOSTANDARD LVTTL NET SU lt 3 gt 5 lt 12 gt L
4. amp Baus GmbH 3 8 SU704 NIM UO 3 8 1 General Description SU704 has 5 identical LEMO COAX I O connectors to be used as programmable digital I O ports Every I O port supports both NIM and TTL levels but the selected level is defined by a jumper setting on the SU704 board default level is NIM Input impedance can be set to 50 Q through a relays Every NIM output can draw a current of 16 mA thus with a 50 Q impedance the level is 0 8V The corresponding input threshold with 50 Q set is 0 4V Maximum frequency of the submodule itself is about 200 MHz and propagation delay 3 ns Hence path delay and maximum toggle frequency are mainly given by the FPGA 3 8 2 SU704 NIM I O pin assignment Pin numbers are in pale green as from top view to connector Left half gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA out OE n lt d gt 24 23 we fin Joena 30 29 _ INNIMet gt in ait June 14 13 Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH 3 9 SU706 Fast ADC submodule 3 9 1 General Description The two upper LEMO COAX receptacles ADC ADC are connected to the fast differential Flash ADC ADS5500 The ADC 1s of 14 bit resolution with 100 MHz sampling rate The input is coupled passively with a differential transform
5. LOG LOC LOC LOC KOG LOC LOC LOC pepo D80 P184 py DOET p154 po DOQ D87 D86 up Jar p72 D68 IB CH D811 D83 DKO DKI DKT p200 eg po4 DoK E ER p113 P114 EH P116 P117 P119 apra P100 PT P106 P107 p130 pioi p122 peice p138 p139 DEER DEER p7O P102 DSL dende a Wpo 3 P126 P109 P108 SU lt 0 gt SU lt 1 gt SUS2 gt SU lt 3 gt TOSTANDARD TOSTANDARD TOSTANDARD LOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD LOSTANDARD TOSTANDARD LOSTANDARD LOSTANDARD LOSTANDARD LOSTANDARD LOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD LOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD LOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD LOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD TOSTANDARD LOSTANDARD LVTTL EVIL EC LVTTL LVTTL LVTTL KVEL HVET KVEG LYETE LVTTL VELE LVTTL LVTTL LVTTL LVTTL HVIT EL KV LG LVTTL EVETTE EVETTE LVTTL KV LVTTL LYTTE BART L ok TL LVL VE LVTIL LVTTL BV ELG LVTTL TVG EVIEL LVTTL KVITLE LVTTL LVL LVTTL LVTTL LVTTL HJT LVTTL EN FG LVTTL EVIG LVTTL LVTTL GVETL Ne No No No ae ae NO ae ae ae ae ae Ne ae ae No we me No ae ae ae ae ae NO ae NO NO N
6. assignment cssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssees 15 3 11 SU709 Temperature Sensors submodule ssssecceccccecccccsssssssseccccececoccccosssssesesececcceceeessssssssse 16 GE NENT rrena E ETO ON MN 16 3 11 2 SU709 Temperature Sensors pin assignment essssssssssseccececcccccccssssssssescecceceeecessssssssse 16 S12 SU710 F st DAC submodule eegener eege eeeE 17 VEL GN 17 3122 SUTIO FaSt DAC EE TE cessssssssextedescessesssecatessscasecsbescsledescassespesepiesvasadectbesestedesess 17 3 13 SU7LL 5 Channel Delay 0 5 to CHEN 18 SASL General iesse 18 313 2 SUTIV Fast KODESCH 18 June 14 il Q000 A0 1 1 1 2 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH Advanced usage through installing self made firmware Foreword The NIMbox NEMbox is normally shipped with preinstalled firmware which is consistent with the hardware version and with the position of the installed submodules on the main FPGA board With four positions and a handful of submodule types there exist statistically too many variants for firmware and front panels that can all be supported by W Ie Ne R Hence up to a dozen of decisive NIMbox NEMbox selections can be ordered from stock while individual custom solutions can be offered on special request For these selections Wiener Plein amp Baus can offer the full LabView support with also adaptive firmware selections of hardware useable La
7. connect the FPGA for 100 MHz clock RESET button and the BUSY LED The second part describes the connections to the common interface of the FPGA to the USB interface 8 bit and EEPROM 1 bit The prior is described in more detail in the next section As you can see 29 of the 34 pins of the I O connectors are linked to the FPGA by bidirectional SU lt I gt lt J gt pins which have to be initialized all to HIGH Z with a basic VHDL code All signals should be declared in such an UCF file even once also if not directly used by the VHDL Verilog code June 14 0Q000 A0 3 4 3 5 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH FX2 USB I O RESET LED and CLOCK The FX2 USB connection is realized with a USB chip from Cypress CY7C68013 56 attached to a 24 MHz oscillator The implementation of the fixed installed core will be done with the following VHDL code corresponding to the naming conventions given in the UCF file entity DL 06 is Port CLK in std logic RES n in std logic LED out std logic PAZ FXCLk out std_logic FXAddr out std logic vector l downto 0 FXData inout std_logic_vector 7 downto 0 FXRD n out std logic FXWR nm out std logic FXSLOE n inout std logic FXEmpty in std logic FXFull in std logic FXPEnd n inout std logic SU xx Modules SU inout SU Connectors 0 to 3 end DL706 If you like to use the USB port for own data transmition purposes plea
8. shorting 3 7 2 SU703 discriminator pin assignment Pin numbers are in pale green as from top view to connector Left half gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA LYDS 25 n in D out nst gt A 3 10 out ps1 gt fin LYDS 25 p LVYDS 25 n lin D out n 2 6 5 D out p lt in LYDS 25 p LYDS 25 n lin ID out nein 8 z D out n lt 3 gt in IJLYDS 25 p LVYDS 25 n lin ID out ns4 gt 10 9 ID out p lt 4 gt in LYDS 25 p So in the UCF file you have to alter all LVDS differential lines to the LVDS standard e g NET SU lt 0 gt lt 3 gt LOC P94 TOSTANDARD LVDS 25 NET SU lt 0 gt lt 4 gt LOC P95 IOSTANDARD LVDS 25 The LVDS pairing is the done the same way for all banks as it is done in the list above Threshold and hysteresis DAC are both 12 bit MAX537s Please refer to the datasheet for programming via the SDI SCLK DAC lines Discriminators and TTL Inputs are working in parallel and without interference as long as the TTL output drivers were not output enabled Keep the negative logic output enable lines DOE n lt I gt HIGH as long as no other source is adapted to the LEMO receptacle Else one can destroy the zero ohms output fuses in front of the TTL drivers June 14 12 Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein
9. NIMbox NEMbox FPGA VHDL Self Made Firmware Handbook wien NIMbox O a e status POWER 2 WW De Ge P Ss ge d Si E i A HN ee WC H ie i E 2 PPTL LLL LLL esse arr oeere K nn 19 mmm wenen NEMbOX RESET BUSY 5V z CR FSS 22990 e e ad NIM TTL 1 0 DAC pe 02 e User s Manual 0Q000 A0 General Remarks The only purpose of this manual is a description of the product It must not be interpreted as a declaration of conformity for this product including the product and software W Ie Ne R revises this product and manual without notice Differences between the description in manual and the product are possible W Ie Ne R excludes completely any liability for loss of profits loss of business loss of use or data interrupt of business or for indirect special incidental or consequential damages of any kind even if W Ie Ne R has been advises of the possibility of such damages arising from any defect or error in this manual or product Any use of the product which may influence health of human beings requires the express written permission of W Ie Ne R Products mentioned in this manual are mentioned for identification purposes only Product names appearing in this manual may or may not be registered trademarks or copyrights of their respective companies No part of this product including the product and the software may be reproduced tr
10. O Pin Assignments System NET CLUK NET RES NET LED Back USB NET FXC IK NET FXAJOr lt 0 gt NET FXAddr lt 1 gt NET FPxData lt 02 NET FXData lt 1 gt NET FXData lt 2 gt NET FXData lt 3 gt NET FXData lt 4 gt NET FXData lt 5 gt NET FXData lt 6 gt NET FXData lt 7 gt NET YFXRD m7 NET FX R ert NET SEXO LOE on NET FXEmpty NET EXFu uLrY NET FXPEnd_n SU lt 0 gt NET SU lt 0 gt lt 3 gt NET SU lt S0 gt lt 4 gt NET SU lt U gt lt 5 gt NET SU lt 0 gt lt 6 gt NET YSU lt US lt gt M NET SOU lt 024o T NET SULSOL NET SU lt 0 gt lt L0 gt NET SU lt 0 gt lt 11 gt NET SU lt 0 gt lt 125 NET SU lt 0 gt lt 13 gt NET SY lt 0 gt lt 14 gt NET SU lt 0 gt lt 15 gt NET SU lt 0 gt lt 16 gt NET SU lt gt NET SU lt 0 gt lt 18 gt NET SU lt U gt lt 19 gt NET SJ 0 gt lt 20 gt NET SU lt 0 gt lt 21 gt NET SU lt 0 gt lt 27 gt NET SU lt 0 gt lt 23 gt NET El NET SU lt 0 gt lt 25 gt NET SU lt 0 gt lt 26 gt NET SU lt 0 gt lt 27 gt NET SU lt 0 gt lt 28 gt NET SU lt 0 gt 5 lt 20 gt NET SU lt 0 gt lt 30 gt NET SD lt 0 gt lt 3 1 NET SU lt 0 gt lt 32 gt June 14 LOC LOC LOC LOC LOC LOC LOG LOG BOG LOC LOC LOC LOC LOC LOG LOC LOC LOG LOG LOC KOG LOC LOC LOC LOC LOC LOC LOG LOC LOG LOC LOC LOC LOC LOC LOG LOC EE LOG LOG LOG LOC
11. OG P52 TOSTANDARD E keep IO WEE gt T LOC Poel TOSTANDARD LVTTL NET SU lt 3 gt lt 16 gt LOC P62 TOSTANDARD LVTTL NET SU lt 3 gt lt 75 LOC P64 IOSTANDARD gS la i NET SU lt 3 gt lt 18 gt LOC P65 IOSTANDARD HVITE NET SU lt 3 gt lt 19 gt LOC P34 TIOSTANDARD KETTE NET e Es LOC P35 IOSTANDARD Vy NET SU lt 3 gt lt 21 gt LOC Pie LOSTANDARD LVTTL NET SUSS SZZ ST HOC gt PLYSY TOSTANDARD LVTELG NET SUY lt 3 gt lt 23 gt LOC p20 TOSTANDARD LVTTL NET SU lt se lt 24 gt LOC P21 TOSTANDARD IESSE NET SU lt 3 gt lt 25 gt LOC P76 TOSTANDARD ew TE NET SU lt 3 gt lt 26 gt LOC P28 IOSTANDARD EGET NET SUS LOC P78 IOSTANDARD BEV TTE NET SU lt 3 gt lt 28 gt LOC P71 IOSTANDARD EVTEG NET MS 9T LOC P63 IOSTANDARD LVTTL NET SU lt 3s gt lt 30 gt LOG P24 IOSTANDARD LVTTL NET Et LOC P31 IOSTANDARD LVTTL NET SU lt 3 gt lt 32 gt LOC P33 IOSTANDARD LVTTL Initialize INST Ctr USBCAL OY SEN Ea ass Timing deenens NIM NEMbox Timing NEE CLR TNM NET CLK TIME SPEC TS ChLR PERIOD CLK 10 ns HIGH 50 33 INST Trekker NS ENM TFreklns TIMESPEG TS Cntlnms FROM Ticklns TO Tr klns NET Jee PrO TILG W 1e Ne R Plein amp Baus GmbH Ne No ae ae NO ae NO NO Ne NO ae ae ae Ne ae ae Ne ae Ne ae Ne ae No ae ae Ne Ne ae Ne ae d me The first three lines
12. alf gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA DATAS1 DATA lt O gt out are 6 8 pa out DATA lt 5 gt 8 7 DATA lt 4 gt out D out D out Ed FT I IDATA lt gt 10 9 DATA lt 6 gt quest gt 42 11 DELoutet gt JREF t gt 14 13 D n LE 16 15 DELout lt 2 gt fout JREF 2 gt 18 17 DELin lt 2 gt lin put ALE 20 19 DeELout lt 3 gt fout fin IREF lt 3 gt 22 21 DELin lt 3 fir out JlEs4 gt 24 23 DELouts4 gt ot n IREF lt 4 gt 26 25 DELins4 gt fin aut LE lt 5 gt 28 DELout lt 6 gt fout din REF 5 gt 30 29 DELins5 gt fin JW IHlGHzorn 1 32 a gt J HGHZorin LV LI ch Please refer to the DS1023 50 data sheet for the programming structure and the special meaning of signals June 14 18 Q000 A0
13. ansmitted transcribed stored in a retrieval system or translated into any language in any form by any means without the express written permission of W Ie Ne R June 14 1 Q000 A0 Table of contents I Advanced usage through installing self made firmware sscccccccccceccccccccccccccanssssssssceseees 3 1 1 Foreword E 3 12 T n 3 2 Download of Firmware Files JTAG and USB Inter face ccccccccccssssssssssssssssssssssccccceceececees 21 JLAG Interface Eierung 4 Ze WINDOWS Driyer for USB PL arve 5 23 Firmware download via TB 5 3 Fana AS RENNE 6 3 1 General description of NIMbox NEMDOX eesseesesssssssssseecececcecccccososssssceccccccccoccossssssssescccceceeeosos 6 32 PVAFAWALE CONMP UP ATOM cisissesssssccvecsccsivescccesssnsdsstensicesivecessecnecevevsnnsscesteestcesceussceeeuecddusteessceuseesuseeens 6 3 3 FPGA I O Pin Assignment List UCF File sscssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssssseees 7 54 FX2 USB VO RESET LED and CLOCK uns 10 Se VO E 10 30 TO NINE 11 Sr SUNM SN KE e et eg Tt eeri E E EEEE 12 3 7 1 NERT avveie 12 ML SU703 discriminator pin assignment crsssssssssssssccscccccccccccccccsssssssssssssssssscccssssessees 12 5 VALID 13 3 8 1 Gris 13 3 8 2 SV NIM V0 pre 13 39 SU706 Fast ADC submodule seseris iinne need 14 3 9 1 General TEE Eeer 14 3 9 2 SU706 Fast A DC DACHSEN geet 14 310 SU707 LVDS TO E er E 15 IOL General DESCO o 15 3 10 2 SU707 LVDS IO pin
14. ast DAC pin assignment Pin numbers are in pale green as from top view to connector Left half gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA tout DATA 0 gt 4 3 DATA lt 1 gt out out DATAI lt 2 gt 6 amp DATAT lt 3 gt fout out JDATAl lt 4 gt 8 LC DATAT lt 5 gt fout aut DATAI lt B gt 12 11 DATA1 lt 9 gt fout out JDATAl lt 10 14 EE put JDATAl lt 12 gt 16 15 DATAI lt 13 gt o JDATA2 0 gt out DATAZ2 lt 2 gt out DATA2 lt 6 gt ATA2 lt 7 gt out fout DATA2 lt 8 gt DATA2 lt 9 gt Ju out DATA2 lt 10 gt DATA2 lt 11 gt out DATA2 lt 12 gt DATA2 lt 13 gt out 9 E Ee e The programming is relatively easy please refer to the DAC2904 sheet June 14 17 Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH 3 13 SU711 5 Channel Delay 0 5 to 128 ns 3 13 1 General Description This module is capable to delay digital signals for up to 5 channels asynchronously means independent of any clock by programmable amounts of time in steps of a half nanosecond and with up to 128 steps The corresponding delay chip DS1023 50 has a basic delay of about 16 5 nanoseconds 3 13 2 SU710 Fast DAC pin assignment Pin numbers are in pale green as from top view to connector Left h
15. ature is transformed into a calibrated on chip proportional duty cycle DS put to a digital output The SU709 has 8 RM2 54 mm DUBOX connectors with GND DS 5V each for direct supply Default range of the sensor is 45 to 130 C 3 11 2 SU709 Temperature Sensors pin assignment Pin numbers are in pale green as from top view to connector Left half gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA SEN 1 gt SEN lt 3 gt SEN 5 gt SEN 7 gt mf Please refer to the SMT 16030 types of datasheets for the conversion formulae June 14 16 Q000 A0 3 12 3 12 1 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH SU710 Fast DAC submodule General Description This module is a fast 2 channel digital to analogue converter DAC2904 with 14 bit resolution each Both channels A amp B are completely independent and run with a sampling rate of up to 125 MHz Typical applications are for the generation of complex waveforms AFG Arbitrary Waveform Generator The modules circuitry allows for single operation with 2V 2V range or dual line operation with 1V 1 V range This behavior result of a to 50 Q optimized current amplifier for the first LEMO COAX output with the same current mirrored to the second output respectively 3 12 2 SU710 F
16. bView library symbols Intrinsically the NIMbox NEMbox concept allows for even more individual or home brewed solutions whether they concern mixing of W Ie Ne R submodules or even self made ones when generating the own FPGA firmware Hence within a portable NEMbox case or as a NIMbox module in a Mini Crate one can easily prepare an individual kind of portable Mini Laboratory Mechanics connectors and form factors are made simple and have the potential to realize own ideas with much reduced effort Additional advantage of self programming firmware is that no FPGA resources may be wasted and that the individual code can be optimally fitted into the FPGA device under individual path delay requirements Drawback is that the USB and LabView Interfaces were not supported for such individual firmware and hardware solutions and have to be programmed individually by the user E g the steering of the discriminator settings of the SU703 discriminator have to be accomplished by a self developed FPGA user code invoking the serial threshold DAC of this submodule etc No further help will be given other than on which pins the SDA SCL reside on the FPGA side and that the DAC is a 12 bit MAX537 device with 1 1 output ratio to program threshold levels according to further data given by its datasheet All datasheets needed for submodules can be found in the web or the W Ie Ne R file archive Hence one has to bring serious professions in VHDL Verilo
17. ble USB 6MHz usb hs Download time for the XC3S400 are seconds and for the XCFO4S EEPROM about ten seconds Also for use of the other XILINX debugging tools the JTAG interface should work June 14 4 Q000 A0 2 2 2 3 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH WINDOWS Driver for USB FX2 Once NIMbox NEMbox has been powered and connected to a USB port the hardware installation wizard will guide the user through the installation steps It is recommended not to let Windows look for a proper driver Choose instead to manually install the driver software from the NIMbox NEMbox package CD or from the CD repository on the W Ie Ne R file archive If the package drive is D the driver directory 1s D NIMbox NEMbox Version USB Driver FX2 You may look for the driver files with the Hardware Manager of Windows or run the installation script in the above directory After successful installation the user can verify the proper operation of NIMbox NEMbox in the Control Panel in the Device Manager there should be a new entry named DL7XX LogicBox With this driver it is possible not to use only the USB interface with the NIMbox NEMbox for T O data transfer but also for FPGA and EEPROM configuration download Firmware download via USB To ease firmware download from logistical and mechanical aspects the USB link is the not the fastest but most sophisticated way To download the corresponding FPGA svf file you simp
18. e ae ae ae ae Ne Ne ae ae ae ae ae ae ae Ne ae Ne Ne Ne EE cede 0Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH SU lt 1 gt NET SU lt 1 gt lt 3 gt LOC P168 IOSTANDARD LVTTL KOR D KEE e LOC P169 IOSTANDARD LVTTL NET SUG LOC P150 IOSTANDARD LVTTL NET SU lt 1 gt lt 6 gt LOC P152 TIOSTANDARD LVTTL NET Soule LOC P148 IOSTANDARD LVTTL NET SU lt 1 gt lt 8 gt LOC P149 IOSTANDARD LVTTL NET SU lt 1 gt lt 9 gt LOC P146 IOSTANDARD LVTTL NET SUX1 gt lt 10 gt LOC P147 IOSTANDARD LVTTL NET SU lt 1 gt lt I1 gt LOC P143 IOSTANDARD LVTTL NET SUITEN LOC P144 IOSTANDARD LVTTL NET Svat oS LOC P155 IOSTANDARD LVTTL NET SU lt 1 gt lt 14 gt LOC P156 IOSTANDARD LVTTL NET SU lt 1 gt lt 15 gt LOC P161 IOSTANDARD LVTTL NET SU lt 1 gt lt 165 gt LOC P162 IOSTANDARD LVTTL NET SU lt lsS lt 1 75 gt LOC P176 IOSTANDARD LVTTL NET SU lt 1 gt lt 18 gt LOC P178 IOSTANDARD LVTTL NET SU lt 1 gt lt 19 gt LOC P140 IOSTANDARD LVTTL NET SU lt 1 gt lt 20 gt LOC P141 IOSTANDARD LVTTL NET SU lt 1 gt lt 21 gt LOC P165 IOSTANDARD LVTTL NET SU lt 1 gt lt 22 gt LOC P166 IOSTANDARD LVTTL NET SU lt 1 gt lt 23 gt LOC P171 IOSTANDARD LVTTL NET SUA e lt 74S LOC P172 IOSTANDARD
19. er of 20 kHz to 50 MHz frequency range and the input voltage range is within 0 5 2 3 Vpp depending on the transformer ratio 1 16 1 1 default range is 0 5 V to 0 5 V With an external 0 Q LEMO COAX terminator adapted to one pole of the upper two LEMO COAX receptacles the ADC mode can be switched to single positive or negative polarity The grounding of the two ADC receptacles can be isolated from case ground by opening of additional solder jumpers The default jumper settings in the input circuitry behind the ADC connectors left is as follows By default JX1 and JX2 are set to 1 2 The lower two LEMO COAX receptacles T lt N gt T lt N 1 gt are connected to TTL I O drivers each Normally they will be used as CLOCK and TRIGGER input but if those signals come from the FPGA itself those drivers can be used for alternative things 3 9 2 SU706 Fast ADC pin assignment Pin numbers are in pale green as from top view to connector Left half gives information for the left row right half for the right row Pale yellow are the corresponding levels Pale red are the I O directions from view of the FPGA Pins 1 2 33 36 are not connected to the FPGA L 7 E L ESET ATA O0 gt out E D DATA 2 gt D D U r 3 i ATA lt 4 gt n U L D ae I S ae a L A ae L ATA lt 6 gt L DATA lt 8 gt DATA lt 10 gt DATA lt 12 gt L L L L L L zs TI IT n n out out out out out E ER
20. flying wire set is HW USB FLYLEADS G Provided that the customer creates FPGA firmware professionally the use of the XILINX Download Tools like IMPACT is not discussed here in detail manuals can also be found in the file archive For this case after power on the JTAG chain shall initialize in a way like this S ISE iMPACT 0 61xd C Wokumente und Einstellungen petertillWesktop WL706x_Download DL706_2_2 ipf Boundary Scan DAR File Edit View Operations Output Debug Window Help 8X DAREKMOBXHE DRL Bam eK iMPACT Flows 08 x amp Ga Boundary Scan SystemACE sl Create PROM File PROM File Formatter iH WebTalk Data xcfO4s xe3s400 di706_2 2 mes dl706 2 2 bit iMPACT Processes 0 ex Available Operations are Get Device ID i j Get Device Signature Usercode Pr og am SUC Cee de d Read Device Status One Step SVF One Step XSYF Boundary Scan Console A INFO iMPACT 0011 0111 0001 1000 0000 0000 0000 0000 INFO iMPACT 579 2 Completed downloading bit file to device INFO iMPACT 188 2 Programming completed successfully Match cycle NoWait Match cycle NoWait LCK cycle NoWait LCE cycle NoWait SJ INFO iMPACT 2 Checking done pin done 2 Programmed successfully PROGRESS END End Operation Elapsed time 1 sec P E Console Errors LA Warnings Configuration Platform Ca
21. g coding design to realize the own ideas and to exploit all the hardware features given within the NIMbox NEMbox Important Comments The NIMbox NEMbox is normally shipped with preinstalled firmware which is consistent with the hardware version and with the position of the installed submodules on the main FPGA board This paper gives all the printed lists of pin assignments needed in order to self construct the ucf pin assignment files Additionally ucf example files can be found in the W Ie Ne R file archive Further recommendations will be given in this document How self made firmware can be downloaded via JTAG or USB will be described in chapter 2 From the first hardware firmware installation of a NIMbox NEMbox the user 1s self responsible for avoiding any damage to the product due to hardware handling and firmware programming activities E g to take serious ESD precautions and check for I O directions before connecting June 14 3 Q000 A0 User s Manual NIMbox NEMbox FPGA W lIe Ne R Plein amp Baus GmbH Download of Firmware Files JTAG and USB Interface JTAG Interface Download During the development phase fastest and easiest way to download the FPGA firmware is via the JTAG interface The DL706 mainboard connector contains all pins needed to connect it with the XILINX Flying Wire Adaptor Pinl TCK yellow Pin2 GND black Pin3 TDO magenta Pin4 VREF red Pin5 TMS green Pin9 TDI white The Xilinx product number for the
22. l I O submodules To generate other voltages like 5V take ultra low profile DC DC converters of your choice e g NME line from MURATA PM line from PEAK TDK LTC etc Use pin 34 only as reference or for very low power consumers lt 10 mA per submodule or lt 40 mA in sum June 14 11 0Q000 A0 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH 3 7 SU703 Discriminator I O 3 7 1 General Description SU703 has I to 4 discriminator inputs and 4 to I TTL I O ports where the total sum of the devices is limited to 5 Le the number of LEMO COAX connectors on the front The first LEMO connector corresponds always to a discriminator while the last one always to a TTL I O port Connectors 2 to 4 are discriminators by default but their functionality can be changed with minor hardware modifications Discriminators thresholds can be programmed within the 2 5 2 5 V range and discriminators hysteresis within the 0 60 mV range both with 12 bit resolution The propagation delay of the used MAX9602 is below a nanosecond hence the capable speed is limited by the FPGA only TTL I Os can generate a current of more than 60 mA and therefore a sufficient TTL level greater 2 4V with a 50 Q terminated coaxial line If used as inputs TTL I Os must be terminated with 50 Q Alternatively it is possible to bring the input port high through a pull up resistor of about kQ and through a simple switch it is possible to bring it down by
23. ly have to start the FPGA Update exe program FPGA Update ee AE Fpga Update Tool Fpga Update Tool Ka Hardware Info Number of LogicBox 1 E miske ll Opened device 4UFAN5FPOS l Number of LogicBox 1 Opened device 4UFZN5FPOS Status Elapsed time 41 499 sec Completed 12 21 Config FPGA Config FPGA This program can be found in the W le Ne R file archive in the folder for NIM NEMbox software There also can be found some manuals how to generate svf files out of bit files Generally such file generations can be added by additional command statements at the end of a FPGA synthesis process flow to let it generate automatically after every design process The download itself lasts about 1 2 minutes June 14 5 Q000 A0 3 1 3 2 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH Hardware description General description of NIMbox NEMbox NIMbox NEMbox is a programmable module based on a FPGA board DL706 with 4 slots for I O submodules that serve as interface between the FPGA I O signals and the signals in the external environment It is equipped with a USB port for programming and read out and a connector for direct FPGA programming debugging Its 100 MHz clock makes NIMbox NEMbox well suited for processing signals with length down to 10 ns and frequencies of several MHz Such signals are common in nuclear and particle physics applications where NIM and TTL standards are used for sig
24. nal transmission and processing NIMbox can be used for several application Typical examples are ADC discriminator DAC NIM TTL logic trigger implementations gate generation and data acquisition Hardware configuration The main FPGA of the DL706 is a XILINX Spartan 3 Device XC3S400 in PQG208 Package and Speed Grade 5 Speed Grade 4 is the slower alternative For this smaller device within the Spartan 3 device family the I O path delays are much lower than for the big size variants Please refer to the Spartan 3 Device Family Datasheets for more detailed information Solder jumpers around the FPGA are by default set to switch the banks SU lt 0 gt SU lt 3 gt to a maximum input swing of 3 465V default 3V3 bottom option 2V5 top see fig 1 A ii SJT TT Te TITE TIFT 7 FT i H 1 H TTT for SU lt 2 gt 5 TT OO oP TE aa E I for SU lt 1 gt i Figure 1 TheXILINX Spartan 3 Device XC3S400 and I O Jumper Settings for slots SU lt N gt The slots for submodules on the DL706 mainboard are SU lt 0 gt SU lt 1 gt SU lt 2 gt and SU lt 3 gt counting upwards from bottom to top This is the naming convention within this document June 14 6 Q000 A0 3 3 User s Manual NIMbox NEMbox FPGA FPGA I O Pin Assignment List UCF File W Ie Ne R Plein amp Baus GmbH The following is the printout of the standard or basic DL706 user constraint file ucf DL706 Module Layout Top View Start of I
25. se install your own driver interface of your choice means your implementation specific behavioral architecture I O Connectors The I O connectors are standard two row 36 pin 100 mil IDC receptacles The counting starts from the board top view from the upper right pin 1 to the lower left pin 36 for the NIMbox NEMbox I O submodules naming conventions Figure 2 The NIMbox NEMbox I O submodule connector green position SU lt 3 gt The SU lt i gt lt j gt coding convention as in the UCF file is for lt j gt same as the pin number of the IDC connector e g Pin 3 j 3 of the uppermost module 1 3 is connected to P46 of the FPGA June 14 10 Q000 A0 3 6 User s Manual NIMbox NEMbox FPGA W le Ne R Plein amp Baus GmbH I O submodules Presently table 1 sums up all available submodules for NIMbox NEMbox Figure 3 gives the mechanical dimensions with the connector position can be derived The maximum allowed part height is 7 5 mm on bottom side and 2 3 mm on top side respectively Table 2 lists the standard pin out of the I O submodules For the accepted I O levels refer to the Spartan 3 family sheets Submodule 4x Di 1 Table 1 NIMbox NEMbox I O submodules S 2500 mil 55 mil 1850 mil SS 1600 mil TE 45 mil 3400 mil Figure 3 Mechanical card dimensions of a submodule and relative pin 1 position Li 33 NC nt connected Oe L 33 34 Table 2 Standard Pin Outs of al
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