EMMA Mobile 1 (MC-10118A, UPD77630A) Usage Restrictions
Contents
1. REG _WRITE a L1 burrier gate invalid 0x000A0268 0x00001111 REG WRITE asmu L1BUZ_ oxcooors 1 Ox000A026C 0x00000011 REG WRITE asmu Buzz Joxoooo0011 t pec ware _asmu_ asmu_BGcrRifoxo0000000 0x4C000050 CYCLE WAIT Ox000A0244 OxOO000F00 REG WRITE 0x4C000050 CYCLE WAIT Ox000A0244 0x00000700 REG WRITE 0x4C000050 CYCLE WAIT 0x000A0244 0x00000300 REG WRITE 0x4C000050 CYCLE WAIT 0x000A0208 0x00000000 IMB YB2 000585 L2 Power Off Execute below sequence on PMU PMU code PMU command MacroSelect Register name Write Data Count i 0x000A0500 0x00000000 REG_WRITE ASMU L2_POWERSW 0x00000000 le burrier gate valid 0x000A0500 0x000000FF REG WRITE ASMU L2 POWERSW 0x000000FF ar of the L2 power switch ON L2 Power On Execute below sequence on PMU PMU code 0x000A0500 0x0000007F REG write asmu L2 PowERSWIoxoo00007F fone of the L2 power switch ON 0x40000010 ovane war 0x10 wait 0x000A0500 0x0000003F REG wRire asmu 12 powersw oxooooooaF 0x40000010 ovaewar oto asmu 12 powersw 0x000A0500 0x0000001F REG_WRITE ASMU L2 POWERSW 0x0000001F 040000010 ove war o So fowo 0x000A0500 0x0000000F REG_WRITE ASMU L2 POWERSW 0x0000000F 0x4C000010 cyce war o T o 0x000A0500 0x00000007 REG WRITE ASMU L2 POWERSW 0x00000007 0x4C000010 rcvcewaT 0x000A0500 0x00000003 0x4C000010 cvcewar o ST o 0x000A0500 0x00000001 RE2. YB2 000585 lt Appendix List of restrictions gt 1 Detail of restrictions MC 10118A uPD77630A 1 AXI bus After a bus master of AXlI except ACPU bus v v reads SRC the bus master can not read other slave GPIO The FIQ interrupts of GPIO 96 117 do not work 3 DTV After stopping DMA transfer to DTV module DTV v v module continues to send transfer request to AHB bus under the specific conditions Indication of 1st FIELD even field and 2nd FIELD odd field reverses NTSC output Ma The AC spec TXSR Exit self refresh to first valid ae command of DDR SDRAM restriction oP eegrresomonrmrvemsee 7 ACPU Lz ACPU Write buffer control in the L2 Cache Controller 8 PowerSW Power switch L1 L2 L3 control 9 USB D pin pull down control te Restriction 1 AXI bus Description When a bus master of AXI except ACPU bus reads SRC ISRAM 128KB the bus master can not read other slave after read access to SRC Conditions The bus master can read SRC continuously Bus masters can read write other slaves except SRC ACPU one of the bus master can read write SRC without problem Bus masters can write slaves including SRC Workaround Bus masters which access to SDRAM one of bus slaves shall not read SRC Bus master PDMA which access to SRC shall not read SDRAM Restriction 2 FIQ interruption of GPIO Description The FIQ interrupts of GPIO 96 1 17 do not work GPIO 96 117 can be used
3. as IRQ interrupt IMB YB2 000585 Workaround Use GPIO 0 95 as FIQ interrupt Restriction 3 DMA transmission of DTV Description After stopping DMA transfer to DTV module DTV module continues to send transfer request to AHB bus under the specific conditions Workaround When DTV module user wants to stop DMA transfer to DTV module use HW_RSTZ of DT MODULECONT register 4015_0040H instead of using DTVSTOP of DT STATUS register 4015 OOOOH After stopping DMA transfer reset HW reset DTV module if DIVSTOPRAW of DT RAWSTATUS register 4015 0004H is 1 and DMAREQ of DT_DMAREQ register 4015 0024H is 1 This workaround is supported in NEC EL device driver for Linux Restriction 4 Indication abnormality of NTSC output Description Indication of 1st FIELD even field and 2nd FIELD odd field reverses NTSC output BTB 656 Right format Wrong format 264 265 283 284 524 525 Ls 1st FIELD so 2nd FIELD Workaround 1stFIELD even field and 2ndFIELD odd field are exchanged by software This workaround is supported in NEC EL device driver for Linux IMB YB2 000585 Restriction 5 DDR SDRAM memory can be used with uPD77630A only for UPD77630A Description Please use DDR SDRAM whose AC spec tXSR Exit self refresh to first valid command smaller than 132ns The products NEC Electronics checked on the data sheet are shown below Vendor Product name tXSR ns 512Mb_ 16Mx32bit Mobile
4. oto asmu 12 powersw 0x000A0500 0x0000001F REG_WRITE ASMU L2 POWERSW 0x0000001F 040000010 ove war o So fowo 0x10 Wait 0x000A0500 0x0000000F REG_WRITE ASMU L2 POWERSW 0x0000000F 0x4C000010 cyce war o T o 0x000A0500 0x00000007 REG WRITE ASMU L2 POWERSW 0x00000007 0x4C000010 rcvcewaT 0x000A0500 0x00000003 0x4C000010 cvcewar o ST o 0x000A0500 0x00000001 REG wRiTe asmu L2 powersw oxooooooo1 0x4C000010 cyo war So fow 0x000A0500 0x00000000 rec WRITE Asmu L2 Powersw oxoooooooo0 t Alll of the L2 power switch ON 0x4C000010 cyoaewar iT Ss oto 0x000A0500 0x00010100 REG waite asmu 12 powersw oxoooro100 L2 burtier gate invali O O O x lt x lt x lt l O O O IMB YB2 000585 L3 Power Off Execute below sequence on ACPU ASMU L3 POWERSW_BUZ 0x00000000 IL3 burrier Valid ASMU_L3 POWERSW BUZ 0x000000FF All of L3 power switch Off L3 Power On Execute below sequence on ACPU roa TT Restriction 9 USB D pin pull down control Description USB D pin in EM1 is always pull down with 15kohm when device mode is used To use USB without D pin pull down after Initializing please RUN USBCMD register bit0 R S 1 then set the value 0x600e0001 to USBViewport register 3 List of restrictions See Appendix 4 History EMMA Mobile1 restrictions documents IMB YB2 000509 July 3 2009 1 edition IMB
5. 0 r0 c7 c10 4 drain write buffer r0 0x1 rO r2 0x730 L2 Sync rO r2 0x730 rO 0 L2 sync_loop p15 0 r1 c7 c0 4 2t r2 IO ADDRESS MP200 SMU_ BASE r3 r2 0x80 restore CPU div rate pc Ir wait for interrupt WEI IMB YB2 000585 No 6 from normal Normal A to QR operation Normal Transition operation The division setting of ACPU clock is just the same as that of HBUS clock Before executing this the interrupts should be disable Prefetch the l Cache to avoid fetching l Cache data after Write Buffer Operation and then Drain execute Write Buffer Drain After recovering from WFI transition from QR Normal C to operation operation normal Normal A Sy IMB YB2 000585 Restriction 8 Power switch L1 L2 L3 control Description Power switch of the power domain L1 L2 and L3 should be controlled by setting the registers of each power switch and burrier gate control respectively L1 amp L2 should be controlled by PMU Please implement the sequence below L3 should be controlled by ACPU Please implement the sequence below L1 Power Off Execute below sequence on PMU PMU code PMU command Macro Select eee re Data Ox000A0268 0x00000000 REG WRITE ASMU Li_BUZ 0x00000000 i i L1 burrier gate valid 00000260 0x00000000 REG ware asmu t1 Buze ovooo0000of Jio o o ooo 0x000A0244 0x00000F0F REG WRITE ASMU 1 POWERSW 0x0
6. 0000F0F All of the L1 power switch OFF L1 Power On Execute below sequence on PMU ocos fovaewarf Joopa E 7 oso 0 040000050 CYCLE WAT 0x000A0244 0x00000F01 REG WRITE _asmu_ L1 Powersw oxoooooFo1 040000050 ovoewr tL fp i 0x000A0244 0x00000F00 REG WRITE ASMU L1 POWERSW oxoooooro Jooo Of 040000050 evoa war So ooo o So olh 0 7 i a P T eb t t i acon ovr warp S So fooi acon ovr war S Ao fooji osco fovaewarf S So ooje x50 x50 x50 x50 0x4C000050 CYCLE _ WAIT x50 x50 x50 T i i HE 0x000A0208 0x01000000 REG_ WRITE ASMU ASMU_BGCTRL 0x01000000 ia burrier gate invalid 0x000A0268 0x00001111 REG write Asmu Li Buz _Joxoooo1111 00000266 0x00000011 REG write asmu i1 Buz _ oxoooo0011 0x000A0208 0x00000000 REG WRITE ASMU ASMU_BGCTRL 0x00000000 a IMB YB2 000585 L2 Power Off Execute below sequence on PMU PMU code PMU command MacroSelect Register name Write Data Count i 0x000A0500 0x00000000 REG_WRITE ASMU L2_POWERSW 0x00000000 le burrier gate valid 0x000A0500 0x000000FF REG WRITE ASMU L2 POWERSW 0x000000FF ar of the L2 power switch ON L2 Power On Execute below sequence on PMU PMU code 0x000A0500 0x0000007F REG write asmu L2 PowERSWIoxoo00007F fone of the L2 power switch ON 0x40000010 ovaewar 0x000A0500 0x0000003F REG wRire asmu 12 powersw oxooooooaF 0x40000010 ovaewar
7. 1 User s Manual System Control General Purpose I O Interface The example below shows Normal Mode A for normal operation and Normal Mode C for QR operation IMB YB2 000585 Ordinary operation to QR operation i puck ILILILILILU UE J LJ LC N _ Normal operation ________ ___ QR operation _ Normal Mode A Normal Mode C QR operation to Ordinary operation eucok o LI LJUUUUUUL lt OR operation gg SNormall operation p Normal Mode C Normal Mode A Restriction 7 Write buffer control in the L2 Cache Controller of ACPU Description There is the write buffer 256bit x 2slot in the L2 Cache controller of ACPU Before cutting off the power switch of ACPU please drain the data in the write buffer to DRAM call this operation as Write Buffer Drain Sample program for restriction 6 amp 7 is shown below ENTRY cpu_v6_ do idle idr idr str idr mov str 2 Idr Isr cmp bne idr idr mcr idr mcr mov mcr mov str L2 sync_loop idr cmp bne 1 mcr 2 Idr str mov r2 IO_ ADDRESS MP200_ SMU_BASE r0 0x00244202 modify CPU div rate rO r2 0xf8 r3 r2 0x80 r0 3 rO r2 0x80 rO r2 0x80 r0 8 r0 3 2b backup current div slot change with Normal C slot r2 IO_ ADDRESS MP200_ L220 BASE r0 1f p15 0 rO c7 c13 1 r0 3f p15 0 rO c7 c13 1 prefetch I cache prefetch I cache rO 0 p15
8. DDR SDRAM H5MS5122DKA J3M 120 min samsung 32Mx32 Mobile DDR SDRAM K4X1G323PE 8GD6 8 120 min 32Mx32 Mobile DDR SDRAM K4X1G323PC L F E G 120 min ELPIDA 1G bits DDR Mobile RAM EDD10323BBH LS 82M words x 32 bits 120 min 512M bits DDR Mobile RAM EDD51323DBH LS 16M words x 32 bits 120 min Restriction 6 Clock setting at QR Quick Recovery operation of ACPU Description Using QR Quick Recovery operation the division setting of ACPU clock is just the same as HBUS clock just before entering QR operation To change the division setting please use mode transition of Normal Mode A B C D see P 221 of EMMA Mobile 1 User s Manual System Control General Purpose I O Interface The example below shows Normal Mode A for normal operation and Normal Mode C for QR operation Ordinary operation to QR operation euck ILILILILILUUE J LJ LC N lt ormal operation gt Normal Mode A QR operation to Ordinary operation lt QR operation Normal Mode C eucok LI LJUUUUUUL lt QR operation gt Normal Mode C lt Normal operation Normal Mode A Restriction 7 Write buffer control in the L2 Cache Controller of ACPU Description There is the write buffer 256bit x 2slot in the L2 Cache controller of ACPU Before cutting off the power switch of ACPU please drain the data in the write buffer to DRAM call this operation a
9. G wRiTe asmu L2 powersw oxooooooo1 0x4C000010 cyo war So fow 0x000A0500 0x00000000 rec WRITE Asmu L2 Powersw oxoooooooo0 t Alll of the L2 power switch ON 0x4C000010 cyoaewar iT Ss oto 0x000A0500 0x00010100 REG waite asmu 12 powersw oxoooro100 L2 burtier gate invali O O O x lt x lt x lt l O O O IMB YB2 000585 L3 Power Off Execute below sequence on ACPU ASMU L3 POWERSW_BUZ 0x00000000 IL3 burrier Valid ASMU_L3 POWERSW BUZ 0x000000FF All of L3 power switch Off L3 Power On Execute below sequence on ACPU roa TT Restriction 9 USB D pin pull down control Description USB D pin in EM1 is always pull down with 15kohm when device mode is used To use USB without D pin pull down after Initializing please RUN USBCMD register bit0 R S 1 then set the value 0x600e0001 to USBViewport register
10. Mobile Multimedia Processor Technical Information IMB YB2 000585 1 13 EMMA Mobile 1 Oct 23 2009 Mobile Platform Grou MC 10118A uPD77630A j SoC Systems Division Issued b Usage Restrictions y 2 SoC Operations Unit NEC Electronics Corporation User s Manual Notification Usage restriction S19598E S19687E classification Data Sheet S19657E S19686E Related documents Upgrade Document modification Other notification 1 Affected products MC 10118A uPD77630A 2 Newrestrictions Restriction 5 DDR SDRAM memory can be used with uPD77630A only for UPD77630A Description Please use DDR SDRAM whose AC spec tXSR Exit self refresh to first valid command smaller than 132ns The products NEC Electronics checked on the data sheet are shown below iXSR ns 512Mb_ 16Mx32bit Mobile DDR SDRAM H5MS5122DKA J3M 120 min 32Mx32 Mobile DDR SDRAM K4X1G323PE 8GD6 8 120 min 32Mx32 Mobile DDR SDRAM K4X1G323PC L F E G 120 min ELPIDA 1G bits DDR Mobile RAM EDD10323BBH LS 82M words x 32 bits 120 min 512M bits DDR Mobile RAM EDD51323DBH LS 16M words x 32 bits 120 min Restriction 6 Clock setting at QR Quick Recovery operation of ACPU Description Using QR Quick Recovery operation the division setting of ACPU clock is just the same as HBUS clock just before entering QR operation To change the division setting please use mode transition of Normal Mode A B C D see P 221 of EMMA Mobile
11. on 8 Power switch L1 L2 L3 control Description Power switch of the power domain L1 L2 and L3 should be controlled by setting the registers of each power switch and burrier gate control respectively L1 amp L2 should be controlled by PMU Please implement the sequence below L3 should be controlled by ACPU Please implement the sequence below L1 Power Off Execute below sequence on PMU PMU code PMU command Macro Select ree re Data 0x000A0268 0x00000000 REG WRITE ASMU L1_BUZ re ae burrier gate valid 0x000A0260 0x00000000 REG warme asmu Lreuz2 looo gt o O OoOO 0x000A0244 0x00000F0F REG_WRITE ASMU L1 _POWERSW sow ae of the L1 power switch OFF L1 Power On Execute below sequence on PMU PMU code PMU command Macro Select Register name _ write Data count 0x000A0244 0x00000F07 REG WRITE m One of the L1 power switch ON 0x4C000050 coewr oo 0x000A0244 0x00000F03 REG WRITE asmu_ t1 PowEeRsWloxooo00Fo3 t 0x4C000060 cvewaT ofl 0x000A0244 0x00000F01 REG WRITE asmu L1 Powerswloxoooooroi t Jlj asmu fi powersw oxoooooo 1 Jlj asmu t powerswfoooooozoo 4 Jlj asmu t1 powerswfoooooosoo 4 J l 0x000A0244 0x00000100 REG _ WRITE asmu L1 Powerswloxoooooio0 t 0x4C000050 cvoewar ss olf 0x000A0244 0x00000000 REG_ WRITE asmu L1 Powerswloxoooooo00 t All of the L1 power switch ON 0x4C000060 coewar se S o Ox000A0208 0x01000000
12. s Write Buffer Drain Sample program for restriction 6 amp 7 is shown below ENTRY cpu_v6_ do idle idr idr str idr mov str 2 Idr Isr cmp bne idr idr mcr idr mcr mov mcr mov str L2 sync_loop idr cmp bne 1 mcr 2 Idr str mov r2 IO_ ADDRESS MP200_ SMU_BASE r0 0x00244202 modify CPU div rate rO r2 0xf8 r3 r2 0x80 r0 3 rO r2 0x80 rO r2 0x80 r0 8 r0 3 2b backup current div slot change with Normal C slot r2 IO_ ADDRESS MP200_ L220 BASE r0 1f p15 0 rO c7 c13 1 r0 3f p15 0 rO c7 c13 1 prefetch I cache prefetch I cache rO 0 p15 0 r0 c7 c10 4 drain write buffer r0 0x1 rO r2 0x730 L2 Sync rO r2 0x730 rO 0 L2 sync_loop p15 0 r1 c7 c0 4 2t r2 IO ADDRESS MP200 SMU_ BASE r3 r2 0x80 restore CPU div rate pc Ir wait for interrupt WEI IMB YB2 000585 No 6 from normal Normal A to QR operation Normal Transition operation The division setting of ACPU clock is just the same as that of HBUS clock Before executing this the interrupts should be disable Prefetch the I Cache to avoid fetching I Cache data after Write Buffer Operation and then Drain execute Write Buffer Drain After recovering from WEI transition from QR Normal C to operation operation normal Normal A Sy IMB YB2 000585 Restricti
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