Home

8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User`s

1. Disable Phase porti EXTALA XTAL1 Phase locked Oscillator Phase locked Loop XTAL2 O Clock Multiplier Disable Oscillator Powerdown Disable Clock Input Powerdown Divide by two Circuit 1 2 Clock Generators Programmable Divider CLK1 0 To reset logic Disable Clocks Idle Powerdown CPU Clocks PH1 PH2 Clock Failure Detection Peripheral Clocks PH1 PH2 OSC FJ CLKOUT Disable Clocks Powerdown A5290 01 Figure 10 1 Clock Circuitry 87C196LA LB Only 10 2 ENTERING AND EXITING ONCE MODE ONCE mode isolates the device from other components in the system to allow printed circuit board testing or debugging with a clip on emulator During ONCE mode all pins except XTALI XTAL2 Vos and Vcc are weakly pulled either high or low During ONCE mode RESET must be held high or the device will exit ONCE mode and enter the reset state On the 87C196LA and LB the reset state level of all 41 general purpose I O pins has changed from a weak logic 1 wk1 to a weak logic 0 wk0 ONCE shares a package with port pin 2 6 Asserting and holding the ONCE signal high during the rising edge of RESET causes the device to enter ONCE mode To prevent accidental entry into ONCE mode configure this pin as 10 2 intel SPECIAL OPERATING MODES an output If you choose to configure this pin as an input always hold it low during reset and en sure that y
2. intel bi I O PORTS Internal Bus v cc I O Pin RESET Vss 150Q to 2000 R1 Buffer Read Port PH1 Clock Medium Pullup 300ns Delay RESET De 3 x RESET Any Write to Px_MODE Vss A5265 01 Figure 5 1 Ports 1 2 5 and 6 Internal Structure 87C196LA LB Only 5 2 1 Configuring Ports 1 2 5 and 6 Bidirectional Ports Using the port mode register you can individually configure each pin for port 1 2 5 and 6 to operate either as a general purpose I O signal I O mode or as a special function signal special function mode In either mode three configurations are possible complementary output high 5 3 8XC196LX SUPPLEMENT intel impedance input or open drain output The port direction and data output registers select the con figuration for each pin Complementary output means that the microcontroller drives the signal high or low High impedance input means that the microcontroller floats the signal Open drain output means that the microcontroller drives the signal low or floats it For I O mode the port data output register determines whether the microcontroller drives the signal high drives it low or floats it For special function mode the on chip peripheral or system function determines whether the microcontroller drives the signal high or low for complementary outputs The pins for ports 1 2 5 and 6 are weakly pulled low during and after reset Initializing the pins by w
3. nenea nana nana emana na 8 4 8 3 1 Control State Machines ese sees ee 8 4 8 3 1 1 Cyclic Redundancy Check Generator annen enne eenneennereneereneeeneeenven 8 4 8 3 1 2 BUS Contentions see e oa cate ae a d Pl a a e d a eee 8 5 8 311 37 BitArbitration iia a ail abel aa e a a a e a Ae alee 8 5 8 3 1 4 Error Detection ba estes 8 5 8 3 2 Symbol Synchronization and Timing Circuitry nnee eener nenneneneneneeenn 8 5 8 3 2 1 Elock Prescaler r a ipac ata ticas 8 6 8 39 22 Digital Filter cuina etna Aaa a aa an ete ae asa 8 6 8 3 2 3 Delay Compensation zn aaa aaa da ta e ane a oa A aa ata Da al ian 8 6 8 3 2 4 Symbol Encoding and Decoding cena nana aaa 8 6 8 3 3 Bit Arbitra ion Example zn ser acacia ea cale ent 8 7 8 4 MESSAGE FRAMES cuadrada 8 8 8 4 1 Standard Messaging eiii taifa 8 9 8 4 1 1 A ace ca a EE EA Miata ata d Dn E 8 9 8 41 27 CRO Byle sai ce ci ar aaa Suhel lee ennn iad ees 8 9 8 4 1 3 Normalization Bitar a iad hed thet br 8 9 8 4 1 4 Start and End Message Frame Symbols me nenea nenea nana 8 10 8 4 2 In frame Response Messaging mmm nenea nenea 8 12 8 4 2 1 IFR Messaging Type 1 Single Byte Single Responder nnen 8 12 8 4 2 2 IFR Messaging Type 2 Single Byte Multiple Responders nne 8 12 8 4 2 3 IFR Messaging Type 3 Multiple Bytes Single Responder nnee 8 13 8 5 TRANSMITTING AND RECEIVING MESSAGES nnen nana 8 13 8 5 1 Transmitting Messages ennn eee nn rn 8 13 8 5 2 Rec
4. 512 56 10 3 8 2 8XC196JT 52 32K 1024 512 a 6 3 6 1 87C196CA 68 32K 1024 256 51 6 3 s 1 2 8XC196KR 68 16K 512 256 56 10 3 8 2 8XC196JR 52 16K 52 256 al e 3 s 1 NOTES 1 Optional The second character of the device name indicates the presence and type of nonvolatile memory 80C196xx none 83C196xx ROM 87C196xx OTPROM or EPROM 2 Register RAM amounts include the 24 bytes allocated to core SFRs and the stack pointer 2 1 8XC196LX SUPPLEMENT intel 2 2 BLOCK DIAGRAM Figure 2 1 is a simplified block diagram that shows the major blocks within the microcontroller Observe that the slave port peripheral does not exist on the 8XC196Lx oe KEN oe Memory ROM Interrupt Controller KEN Controller este and E Peripheral Power este nn Transaction Server Note The J1850 peripheral is unique to the 87C196LB device The A D peripheral is unique to the 87C196LA LB devices A5253 01 Figure 2 1 8XC196Lx Block Diagram 2 3 INTERNAL TIMING The 87C196LA LB clock circuitry Figure 2 2 implements a phase locked loop and clock mul tiplier circuitry which can substantially increase the CPU clock rate while using a lower frequen cy input clock The clock circuitry accepts an input clock signal on XTALI provided by an external crystal or oscillator Depending on t
5. The benefit of an integrated J1850 protocol solution is threefold e Minimizes CPU overhead for reception and transmission of J1850 messages Frees up serial and parallel communications ports for other purposes e Offers significant printed circuit board area savings when compared with conventional standalone protocol devices 8 1 8XC196LX SUPPLEMENT intel The J1850 controller can handle network protocol functions including message frame sequenc ing bit arbitration in frame response IFR messaging error detection and delay compensation The J1850 communications controller Figure 8 2 consists of a control state machine CSM symbol synchronization and timing SST circuitry six control and status registers transmit and receive buffers and an interrupt handler J1850ST J1850 Communications Controller J1850RX Interrupt Handler J1850TX J_DLY DLY J J_STAT Error Detection Circuitry Compensator Symbol JTX_BUF BUF Encoder TXJ1850 Re JRX ES Circuitry Symbol Digital D a Filter Bus Error Peripheral Data Bus Cyclic RXJ1850 Redundancy Check Circuitry SST Internal Clocking A5169 01 Figure 8 2 J1850 Communications Controller Block Diagram 8 2 intel J1850 COMMUNICATIONS CONTROLLER 8 2 J1850 CONTROLLER SIGNALS AND REGISTERS Table 8 1 describes the J1850 controller s pins and Table 8 2 describes the control and
6. intel J_DLY accurately resolve bus contention duri through windowing Address Reset State 1F58H 00H The J1850 delay J_DLY register allows you compensate for the inherent propagation delays and to ng arbitration This byte register can be directly addressed 7 0 DLY4 DLY3 DLY2 DLY1 DLYO Bit Bit Number Mnemonic Function 7 5 Reserved for compatibility with future devices write zeros to these bits 4 0 DLY4 0 Delay Time These five bits specify the desired propagation delay between the J1850 controller circuitry and the off chip transceiver device in units of microseconds us 8 20 Figure 8 18 J1850 Delay J_DLY Register intel J1850 COMMUNICATIONS CONTROLLER 8 6 4 Programming the J1850 Status J_STAT Register The J1850 status register Figure 8 19 provides the current status of the message and the four interrupt sources associated with the J1850 protocol J STAT Address 1F53H Reset State 00H The J1850 status J_STAT register provides the current status of the message transfer the receive and transmit buffers and the four interrupt sources associated with the J1850 protocol This byte register can be directly addressed through windowing You must write to this register before transmitting each message Reading this register clears all bits except BUS _STAT 7 0 IFR_RCV BUS CONT BUS STAT BRK_RCV OVR_UNDR MSG_T
7. 6 The values in this column are valid until your software writes to Px_MODE A 8 intel SIGNAL DESCRIPTIONS Table A 6 83C196LD Default Signal Conditions Upon RESET i ET z Power Signals Functions Acwe acte dle fown P0 7 2 HiZ HiZ HiZ HiZ P1 0 EPAO T2CLK WK1 WK1 Note 1 Note 1 P1 1 EPA1 WK1 WK1 Note 1 Note 1 P1 2 EPA2 T2DIR WK1 WK1 Note 1 Note 1 P1 3 EPA3 WK1 WK1 Note 1 Note 1 P2 0 TXD WK1 WK1 Note 1 Note 1 P2 1 RXD WK1 WK1 Note 1 Note 1 P2 2 EXTINT WK1 WK1 Note 1 Note 1 P2 4 WK1 WK1 Note 1 Note 1 P2 6 ONCE MD1 MD1 Note 1 Note 1 P2 7 CLKOUT CLKOUT active CLKOUT active Note 1 Note 2 LoZO 1 LoZO 1 P3 7 0 AD7 0 WK1 HiZ Note 4 Note 4 P4 7 0 AD15 8 WK1 HiZ Note 4 Note 4 P5 0 ALE ADV WK1 WK1 Note 1 Note 1 P5 2 WR WRL WK1 WK1 Note 1 Note 1 P5 3 RD WK1 WK1 Note 1 Note 1 P6 0 EPA8 WK1 WK1 Note 1 Note 1 P6 1 EPA9 WK1 WK1 Note 1 Note 1 P6 4 SCO WK1 WK1 Note 1 Note 1 P6 5 SDO WK1 WK1 Note 1 Note 1 P6 6 SC1 WK1 WK1 Note 1 Note 1 P6 7 SD1 WK1 WK1 Note 1 Note 1 EA WK1 Note 5 WK1 WK1 WK1 RESET LoZO MD1 MD1 MD1 Vop HiZ HiZ LoZ1 LoZ1 m STARI Osc input HiZ Osc input HiZ nn a XTAL2 Osc output Osc output Osc output Note 3 LoZO 1 LoZO 1 LoZ0 1 NOTES 1 If Px_MODE y 0 port is as programmed If Px_
8. IN A3361 03 Figure A 2 87C196LB 52 pin PLCC Package A 5 8XC196LX SUPPLEMENT intel Table A 3 83C196LD Signals Arranged by Functional Categories Addr amp Data Input Output Input Output Cont d Processor Control Name Pin Name Pin Name Pin Name Pin ADO 22 P1 0 EPA0 T2CLK 44 P4 7 7 CLKOUT 32 AD1 21 P1 1 EPA1 43 P5 0 2 EA 24 AD2 20 P1 2 EPA2 T2DIR 42 P5 2 6 EXTINT 29 AD3 19 P1 3 EPA3 41 P5 3 5 ONCE 31 AD4 18 P2 0 TXD 27 P6 0 EPA8 45 RESET 23 AD5 17 P2 1 RXD 28 P6 1 EPA9 46 XTAL1 52 AD6 16 P2 2 29 P6 4 SCO 47 XTAL2 51 AD7 15 P2 4 30 P6 5 SDO 48 AD8 14 P2 6 31 P6 6 SC1 49 Bus Control amp Status AD9 13 P2 7 32 P6 7 SD1 50 Name Pin AD10 12 P3 0 22 ADV ALE 2 AD11 11 P3 1 21 Power amp Ground RD 5 AD12 10 P3 2 20 Name Pin WR WRL 6 AD13 9 P3 3 19 Vec 26 AD14 8 P3 4 18 Voo 40 AD15 7 P3 5 17 Vo 4 P3 6 16 Vos 1 Input P3 7 15 Vss 3 Name Pin P4 0 14 Vss 25 P0 2 33 P4 1 13 Vss 39 P0 3 34 P4 2 12 P0 4 35 P4 3 11 P0 5 36 P4 4 10 P0 6 37 P4 5 9 PO 7 38 P4 6 8 A 6 intel SIGNAL DESCRIPTIONS EI AD15 P4 7 6 FI P5 2 WR WRL 5 A P5 3 RD 2 E P5 0 ADV ALE 52 FI XTAL1 51 FI XTAL2 50 FI P6 7 SD1 49 A P6 6 SC1 48 EI P6 5 SDO 47 A P6 4 SCO 46 FI P6 1 EPA9 45 FI P6 0 EPA8 44 EI P1 0 EPAO T2CLK 43 A P1 1 EPA1 AN83C196LD 42 FI P1 2 EPA2
9. Point of Arbitration Busline A5223 01 Figure 8 5 Bit Arbitration Example 8 4 MESSAGE FRAMES A message transmission or reception is transferred within a message frame that adds control and error detection bits to the content of the message The frame for an IFR message differs slightly from that for a standard message but they contain similar information Figure 8 6 8 8 intel J1850 COMMUNICATIONS CONTROLLER Standard Frame s 1 3 Bytes 1 11 Bytes 1Byte E F Header Datat CRC D nom on In frame Response IFR Frame 5 1 3 Bytes 1 11 Bytes 1 Byte 5 N 1 32 Bytes 0 1 Byte 5 5 F Header Datat CRC D B IFR Data CRC DIE The number of data bytes to be transferred is unspecified if OEH is written to J_CMD3 0 A5225 01 Figure 8 6 J1850 Message Frames A standard message frame is initiated by the responder and contains no more than 11 data bytes to be transmitted An IFR message is a request initiating the recipient s to respond by transmit ting data within the same frame The following subsections describe each of the messaging forms 8 4 1 Standard Messaging A standard message frame can best be described as a send mode only format that is initiated by the responder either to request information or to reply to areceived message from a remote node In addition to the actual data that is being transmitted the standard message is composed of a header 1 3 bytes aCRC byte and a series of st
10. intel J1850 COMMUNICATIONS CONTROLLER 64uS 1 i 1 a 128uS ol or oL passive 1 active 1 128uS del 1 az 64uS f ol ss A SA al passive 0 active 0 A5219 01 Figure 8 3 Huntzicker Symbol Definition for J1850 A symbol is defined as a timing level formatted bit The VPW symbol timing requirements stip ulate that there is one symbol per transition and one transition per symbol This ensures that a message frame will always result in a uniform square waveform of varying level durations Fig ure 8 4 depicts a typical Huntzicker formatted data byte of hex value CCH q q o o q q pr o A5222 01 Figure 8 4 Typical VPW Waveform Bits 7 and 3 carry logic level 1 data however they are represented by a passive level symbol in keeping with the VPW requirements Bits 4 and 0 carry logic level O data and are represented by an active level symbol 8 3 3 Bit Arbitration Example The drive capacity of each symbol establishes the priority for arbitration By definition an active bus level is a driven state and a passive bus level is a non driven or idle state A driven bus state is always given priority over an idle bus in arbitration An active 0 state has priority over an active 1 state in arbitration because the active 0 state is driven over a longer duration 128 us versus the active 1 state s drive time of 64 us Similarly a passive 0 state h
11. through a window has no effect 3 7 intel 8XC196LX SUPPLEMENT Table 3 4 Windows Continued en WSR Value WSR Value rn Address for 32 byte Window for 64 byte Window Win ee 00E0 00FFH 00C0 00FFH 0080 00FFH Upper Register File CA JR JT JV KR KT LA LB LD 0160H 4BH 0140H 4AH 25H 0120H 49H 0100H 48H 24H 12H NOTE Locations 1FE0 1FFFH contain memory mapped SFRs that cannot be accessed through a window Reading these locations through a window returns FFH writing these locations through a window has no effect 3 8 intel Standard and PTS Interrupts intel CHAPTER 4 STANDARD AND PTS INTERRUPTS The interrupt structure of the 8XC196Lx is the same as that of the 8XC196Jx The only difference is that the slave port interrupts INT08 06 now support the J1850 controller peripheral 4 1 INTERRUPT SOURCES VECTORS AND PRIORITIES Table 4 1 lists the 8XC196Lx s interrupts sources default priorities 30 is highest and 0 is low est and vector addresses 4 1 8XC196LX SUPPLEMENT IN E Table 4 1 Interrupt Sources Vectors and Priorities Interr ntroller P ie rbd e PTS Service Interrupt Source Mnemonic Pi 5 gt 5 gt 5 3 5 3 5 zZ gt zZ gt A Nonmaskable Interrupt NMI INT15 203EH 30 EXTINT Pin EXTINT INT14 203CH 14 PTS14 205CH 29 Reserved a
12. 13 8 12 8 15 8 14 vi FIGURES Page 8XC196 x Bleek Diagram esns sai caii hase asks ses Hirte 2 2 Clock Circuitry 87C196LA LB Only nenea nenea ana 2 3 Internal Clock Phases Assumes PLL is Bypassed emma vennen 2 4 Effect of Clock Mode on Internal CLKOUT Frequeney nnee eenen 2 5 Unerasable PROM 1 USFR1 Register LA LB Only nenea nene 2 6 Register File Address Map nnn aansereenseerenserrvenevenensereenseenesnereennseneenenrnennene 3 3 Interrupt Mask INT_MASK Register mean nenea nenea nana 4 3 Interrupt Mask 1 INT_MASK1 Register nenea nene ren cnn 4 4 Interrupt Pending INT_PEND Register uurnsersnnnersnnnnnnnnnnnnennnn nennen ernennen eenen 4 5 Interrupt Pending 1 INT_PEND1 Register mmm 4 6 PTS Select PTSSEL Register citant dd ei E da 4 7 PTS Service PTSSRV Register men eee eee eee eneeneenanne nana ana aa 4 8 Ports 1 2 5 and 6 Internal Structure 87C196LA LB Only nennen 5 3 Ports 3 and 4 Internal Structure 87C196LA LB Only nnee eneen nennen 5 6 SSIO 0 Clock SSIOO_CLK Register nenea manea emana na 6 1 SSIO 1 Clock SSIO1_CLK Register nenea nenea nana na 6 2 EPA Block Diagram 87C196LA LB Only nenea nene nenea na 7 2 EPA Block Diagram 83C196LD Only nenea nenea nn naenae 7 3 EPA Interrupt Mask EPA_MASK Register mean nenea na 7 4 EPA Interrupt Mask 1 EPA_MASK1 Register men nenea nare 7 4 EPA Interrupt
13. 15 7 VREF 40 P0 3 ACH3 34 P4 7 7 PMODE O 35 Vos 3 P0 4 ACH4 35 P5 0 2 PMODE 1 36 Vesi 1 P0 5 ACH5 36 P5 2 6 PMODE 2 37 Vesi 25 P0 6 ACH6 37 P5 3 5 PMODE 3 38 P0 7 ACH7 38 P6 0 EPA8 COMPO 45 PROG 29 P1 0 EPAO T2CLK 44 P6 1 EPA9 COMP1 46 PVER 27 P1 1 EPA1 43 P6 4 SCO 47 P1 2 EPA2 T2DIR 42 P6 5 SDO 48 P1 3 EPA3 41 P6 6 SC1 49 P2 0 TXD 27 P6 7 SD1 50 SIGNAL DESCRIPTIONS EI AD15 P4 7 PBUS 15 6 FI P5 2 PLLEN WR WRL 5 A P5 3 RD 4 a Vpp 2 E P5 0 ADV ALE 3 E Vss core e 1 Pa Vss port 52 FI XTAL1 51 EI XTAL2 50 EI P6 7 SD1 49 FI P6 6 SC1 48 FI P6 5 SDO 47 EI P6 4 SCO AD14 P4 6 PBUS 14 AD13 P4 5 PBUS 13 AD12 P4 4 PBUS 12 P6 1 EPA9 COMP1 P6 0 EPA8 COMPO P1 0 EPAO T2CLK AD11 P4 3 PBUS 11 P1 1 EPA1 AD10 P4 2 PBUS 10 AN87C196LB20 P1 2 EPA2 T2DIR AD9 P4 1 PBUS 9 P1 3 EPA3 AD8 P4 0 PBUS 8 VREF AD7 P3 7 PBUS 7 View of component as ANGND AD6 P3 6 PBUS 6 P0 7 ACH7 PMODE 3 ADS P3 5 PBUS 5 mounted on PC board PO 6 ACH6 PMODE 2 AD4 P3 4 PBUS 4 P0 5 ACH5 PMODE 1 AD3 P3 3 PBUS 3 P0 4 ACH4 PMODE O AD2 P3 2 PBUS 2 P0 3 ACH3 NO 4 OnRDHDOrAD NNN OU NNM MN OO OO O O U UU UUU UUU o N REE SEE GER Sopa gt 202 gt 20 am Ea aar Y n 02 5 Onore N o gt XREBo5S 5 c C zopaa Ee 22382 orxx5 58 Na E XO avo lt lt Len NAN a a
14. 2080 2080 2080 2080 2080 external memory see indexed Note 1 Special purpose memory A zum Soop 2075 2006 2805 2935 anemalnaniatieor Inston external memory 1FFF AFFF AFFF AFFF 1FFF 1FFF Indirect or 1FEO 1FEO 1FEO 1FEO 1FEO treo Memory mapped SFRs indexed Indirect 1FDF 1FDF 1FDF 1FDF 1FDF 1FDF een indexed or 1F00 1F00 1F00 1F00 1F00 1F00 87C196LB es irect Indirect 1EFF indexed or 1E00 CAN SERS windowed direct External device memory or I O connected to 1DFF 1EFF 1EFF 1EFF 1EFF 1EFF address data bus Indirect or 1C00 1C00 1C00 0300 1C00 1E00 future SFR expansion indexed see Note 2 Indirect 1DFF 8 indexed or 1coo Register RAM windowed direct NOTES 1 After a reset the device fetches its first instruction from 2080H 2 The content or function of these locations may change in future device revisions in which case a program that relies on a location in this range might not function properly 3 1 8XC196LX SUPPLEMENT intel Table 3 1 Address Map Continued Device and Hex Address Range e i e E Description bis pu 9 lt E 2 gt JJ gt External device memory 3 0500 osoo oeoo osoo oeoo or O connecteato indexed address data bus 04FF 04FF O5FF O5FF Indirect or 0400 0400 0400 0400 Internal code or dat
15. 3 and 4 Internal Structure 87C196LA LB Only intel Synchronous Serial VO Port intel CHAPTER 6 SYNCHRONOUS SERIAL I O PORT The synchronous serial I O SSIO port on the 8XC196Lx has been enhanced implementing two new special function registers SSIOO CLK and SSIO1 CLK that allow you to select the oper ating mode and configure the phase and polarity of the serial clock signals 6 1 SSIO 0 CLOCK REGISTER The SSIO 0 clock SSIO_CLK register selects the phase and polarity for the SCO clock signal In standard mode SCO is channel 0 s clock signal In duplex and channel select modes SCO is the common clock signal for both SSIO channels SSIOO_CLK Address 1FB5H u Reset State 00H The SSIO 0 clock SSIOO_CLK register configures the serial clock for channel 0 In standard mode the SCO is channel O s clock signal In duplex and channel select modes SCO is the common clock signal for both SSIO channels 7 0 PHAS POLS mba bisemonic Function 7 2 Reserved for compatibility with future devices write zeros to these bits 1 PHAS Phase and Polarity Select 0 POLS For normal transfers these bits determine the idle state of the serial clock and select the serial clock signal edge on which the SSIO samples incoming data bits or shifts out outgoing data bits These bits are ignored for handshaking transfers Use SSIOO_ CON to select the type of data transfer nor
16. CONPND PHAS POLS Bit Number Bit Mnemonic Function 2 CONPND Master Contention Interrupt Pending For channel select master operations the SSIO sets this bit when the CHS pin is externally activated In a system with multiple masters an external master activates the CHS signal to request control of the serial clock This bit is valid for channel select master operations and ignored for all other operations PHAS POLS Phase and Polarity Select For normal transfers these bits determine the idle state of the serial clock and select the serial clock signal edge that the SSIO samples incoming data bits or shifts out outgoing data bits For transmissions PHAS POLS 0 0 low idle state shift on falling edges 0 1 high idle state shift on rising edges 1 0 low idle state shift on rising edges 1 1 high idle state shift on falling edges For receptions PHAS POLS 0 0 low idle state sample on rising edges 0 1 high idle state sample on falling edges 1 0 low idle state sample on falling edges 1 1 high idle state sample on rising edges These bits are ignored for duplex and channel select modes these modes use SCO as the common clock signal The SSIOO CLK register contains the phase and polarity select bits for the SCO clock signal These bits are also ignored for handshaking transfers Use SSIO1_ CON to select the type of data transfer normal or handshaking for
17. DUP CONINT CONPND PHAS POLS Bit Bit Number Mnemonic Function 7 6 Reserved for compatibility with future devices write zeros to these bits 5 CHS These bits determine the SSIO operating mode 4 DUP CHS DUP 0 0 standard mode 0 1 duplex mode 1 0 channel select half duplex mode uses SD1 only 1 1 channel select full duplex mode uses both SDO and SD1 3 CONINT Master Contention Interrupt For channel select master operations the SSIO sets the master contention interrupt pending bit CONPND when the CHS pin is externally activated In a system with multiple masters an external master activates the CHS signal to request control of the serial clock CONINT determines whether the SSIO sets both CONPND and the SSIO0 interrupt pending bit or only CONPND when the CHS pin is externally activated 0 SSIO sets only CONPND 1 SSIO sets both CONPND and the SSIO0 interrupt pending bit This bit is valid for channel select master operations and ignored for all other operations Figure 6 2 SSIO 1 Clock SSIO1_CLK Register 6 2 intel SYNCHRONOUS SERIAL I O PORT 7 SSIO1_CLK Continued Address 1FB7H Reset State 00H The SSIO 1 clock SSIO1_CLK register selects the SSIO mode of operation standard duplex or channel select enables the channel select master contention interrupt request and selects the phase and polarity for the serial clock SC1 for channel 1 CHS DUP CONINT
18. IFR messaging type 3 Figure 8 11 is ideal for requesting large amounts of information from a single source in your system You can compile up to 12 bytes of data from a remote node on a single request In our example for the same amount of CPU overhead as IFR type 1 messaging exhausted 4 96 ms you can gather up to twelve times as much information In frame Response IFR Frame 1 3 Bytes 1 11 Bytes 1 12 Bytes Header Data 8 IFR Data The number of data bytes to be transferred is unspecified if OEH is written to J_CMD3 0 A5228 01 Figure 8 11 IFR Type 3 Message Frame 8 5 TRANSMITTING AND RECEIVING MESSAGES The J1850 controller can transmit and receive messages in either standard or IFR form 8 5 1 Transmitting Messages To transmit a standard message prepare the message in register RAM and then write it to the J1850 transmit J_TX register Figure 8 12 one byte at a time 8XC196LX SUPPLEMENT intel J TX Address 1F50H Reset State 00H The J1850 transmitter J_ TX register transfers data in byte increments to the J1850 bus from the microcontroller CPU This register is buffered to allow for transmission of a second data byte while the first data byte is being shifted out This byte register can be read or written and is addressable through windowing 7 0 Transmit Byte Bit Bit Number Mnemonic Function 7 0 DB7 0 Data Bits These eight bits compose the data byte to be transmitted
19. J1850 Status LB only NMI is always enabled This nonfunctional mask bit exists for design symmetry with the INT_PEND1 register Always write zero to this bit Bit 5 is reserved on the 8XC196Lx devices and bit 0 is reserved on the 87C196LA and 83C196LD For compatibility with future devices always write zeros to these bits Figure 4 2 Interrupt Mask 1 INT_MASK1 Register 4 2 2 Interrupt Pending Registers Figures 4 3 and 4 4 illustrate the interrupt pending registers for the 8XC196Lx microcontrollers 4 4 intel STANDARD AND PTS INTERRUPTS INT_PEND Address 0009H Reset State 00H When hardware detects an interrupt request it sets the corresponding bit in the interrupt pending INT_PEND or INT_PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 7 0 LA AD EPAO EPA1 EPA2 EPA3 EPAx 7 0 LB J1850RX J1850TX AD EPAO EPA1 EPA2 EPA3 EPAx 7 0 LD EPAO EPA1 EPA2 EPA3 EPAx te Function 7 04 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared when processing transfers to the corresponding interrupt vector Bit Mnemonic Interrupt Description J1850RX J1850 Receive LB only J1850TX J1850 Transmit LB only AD A D Conversion Complete LA LB EPAO EPA Capture Compare Channel 0 EPA1 EPA Cap
20. Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FBEH Reserved Reserved 1F7EH EPA7_TIME H EPA7_TIME L 1FBCH SP_BAUD H SP_BAUD L 1F7CH Reserved EPA7_CON 1FBAH SP_CON SBUF_TX 1F7AH EPA6_TIME H EPA6_TIME L 1FB8H SP_STATUS SBUF_RX 1F78H Reserved EPA6_CON 1FB6H SSIO1_CLK Reserved 1F76H EPA5_TIME H EPA5_TIME L 1FB4H SSIOO_CLK SSIO_BAUD 1F74H Reserved EPA5_CON 1FB2H SSIO1_CON SSIO1_BUF 1F72H EPA4_TIME H EPA4_TIME L 1FBOH SSIOO_CON SSIOO_BUF 1F70H Reserved EPA4_CON A D SFRs LA LB Only 1F6EH EPA3_TIME H EPA3_TIME L Address High Odd Byte Low Even Byte 1F6CH EPA3_CON H EPA3_CON L 1FAEH AD_TIME AD_TEST 1F6AH EPA2_TIME H EPA2_TIME L 1FACH Reserved AD_COMMAND 1F68H Reserved EPA2_CON 1FAAH AD_ RESULT H AD_RESULT L 1F66H EPA1_TIME H EPA1_TIME L EPA Interrupt SFRs 1F64H EPA1_CON H EPA1_CON L Address High Odd Byte Low Even Byte 1F62H EPAO_TIME H EPAO_TIME L 1FA8H Reserved EPAIPV 1F60H Reserved EPAO_CON 1FA6H Reserved EPA_PEND1 J1850 SFRs LB Only 1FA4H Reserved EPA_MASK1 Address High Odd Byte Low Even Byte 1FA2H EPA_PEND H EPA_PEND L 1F5EH Reserved Reserved 1FAOH EPA_MASK H EPA_MASK L 1F5CH Reserved Reserved Timer 1 Timer 2 and EPA SFRs 1F5AH Reserved Reserved Address High Odd Byte Low Even Byte 1F58H Reserved J_DLY 1F9EH TIMER2 H TIMER2 L 1F56H Reserved Reserved 1F9CH
21. Pending EPA_PEND Register eee nenea 7 5 EPA Interrupt Pending 1 EPA_PEND1 Register nenea nea 7 5 EPA Interrupt Priority Vector Register EPAIPV nnen neene neren neneenerennn 7 6 Integrated J1850 Communications Protocol Solution nenea 8 1 J1850 Communications Controller Block Diagram eee nenea 8 2 Huntzicker Symbol Definition for J1850 annen nenea nana emana 8 7 Typical VPW Waveforini in isca s atit a aaa oa a ada ela aaan ka ai D aaa 8 7 Bit Arbitrati n Exampl zus cata ate ea ann 8 8 J1850 Message Frames nsi annrensenerenneeenensereen ia a a 8 9 Huntzicker Symbol Definition for the Normalization Bit eneen vennen 8 10 Definition for Start and End of Frame Symbols annen eenn eenneneenerenenenneeenn 8 11 IER Typ l Message Frame ne ee ia 8 12 IFR Type 2 Message Frame mmm eeeaeee mana mean ac nenas 8 13 IFR Type 3 Message Frame arie ea eee eaaa aa aee aa ak ar a eaaa 8 13 J1850 Transmit Message Structure mean nnennennaeenaeaaee 8 14 J1850 Transmitter J_TX Register nenea nenea nenea era 8 14 J1850 Receive Message Structure men nenea nenea nana nau 8 15 J1850 Receiver J_RX Register nnen neen sereen servenneeenensvenenseenenereenseeen 8 15 J1850 Command J_CMD Register nenea nenea nana 8 17 J1850 Configuration J_CFG Register men nenea nana 8 18 J1850 Delay J_DLY Register nenea nenea cancer 8 20 J1850
22. Reserved T2CONTROL 1F54H Reserved J_CFG 1F9AH TIMER1 H TIMER1 L 1F52H J STAT J_RX 1F98H Reserved T1CONTROL 1F50H J CMD J_TX 1F96H Reserved Reserved 1F94H Reserved Reserved 1F92H Reserved RST_SRC 1F90H Reserved Reserved EPA SFRs Address High Odd Byte Low Even Byte 1F8EH COMP1_TIME H COMP1_TIME L 1F8CH Reserved COMP1_CON 1F8AH COMPO_TIME H COMPO_TIME L 1F88H Reserved COMPO_CON 1F86H EPA9 TIME H EPA9_ TIME L 1F84H Reserved EPA9 CON 1F82H EPA8 TIME H EPA8_ TIME L 1F80H Reserved EPA8 CON 3 5 8XC196LX SUPPLEMENT intel 3 4 WINDOWING Windowing maps a segment of higher memory the upper register file or peripheral SFRs into the lower register file The window selection register WSR selects a 32 64 or 128 byte seg ment of higher memory to be windowed into the top of the lower register file space Table 3 4 lists the WSR values for windowing the upper register file for both the 8XC196Lx and 8XC196Kx Table 3 4 Windows gata WSR Value WSR Value M e bs for E A 0080 00FFH Peripheral SFRs 1FEOH 7FH Note 1FCOH 7EH 3FH Note 1FAOH 7DH 1F80H 7CH 3EH 1FH Note 1F60H 7BH 1F40H 7AH 3DH 1F20H 79H 1F00H 78H 3CH 1EH CAN Peripheral SFRs 87C196CA Only 1EEOH 77H 1ECOH 76H 3BH 1EAOH 75H 1E80H 74H 3AH 1DH 1E60H 73H 1E40H 72H 39H 1E20H 71H 1E00H 70H 38H 1CH Regist
23. Status J_STAT Register neven nenea iiid nana a 8 21 Reset Source RSTSRC Register nene nenea nana nenea aaa nana na 9 1 Clock Circuitry 87C196LA LB Only neen ennenenerennerenenenneenenenneeenenen 10 2 intel z CONTENTS FIGURES Figure Page 11 1 Slave Programming Circuit cion ee 11 3 11 2 Serial Port Programming Circuit nenea nenea manea emana n 11 4 A 1 87C196LA 52 pin PLCC Package mmm manea nana nana A 3 A 2 87C196LB 52 pin PLCC Package men nenea amana nana na nana A 5 A 3 83C196LD 52 pin PLCC Package nene nenea nenea aan na A 7 vii 8XC196LX SUPPLEMENT intel Table 1 1 2 1 2 2 2 3 2 4 3 2 3 3 4 1 5 1 7 2 8 1 8 3 8 4 11 1 11 2 11 3 11 4 A 1 A 2 A 4 A 5 A 6 viii TABLES Page Related Documents 521 222 a apa 1 2 Features of the 8XC196Lx and 8XC196Kx Product Famiies nennen 2 1 State Times at Various Frequencies men nenea nana na 2 4 Relationships Between Input Frequency Clock Multiplier and State Times 2 5 UPROM Programming Values and Locations nennen nene nenea nana 2 6 Address Map seaca 2222 een 3 1 Register File Memory Addresses men en 3 3 8XC196Lx Peripheral SFRs Windows HN ent dela eerie ee ie Interrupt Sources Vectors and Priorities mmm 4 2 Microcontroller PortS 24420 ca ce secs cated ce aa a en seo 5 1 A aie cae ce a tat erde beek kleene Eta aaa a aa 7 1 EPA Interrupt Priority Vectors nne
24. T2DIR 41 A P1 3 EPA3 P4 0 0 14 View of component as mounted on PC board AD1 P3 1 Y 21 ADO P3 0 EJ 22 RESET C 23 P2 0 TXD Y 27 P2 1 RXD E 28 P2 2 EXTINT TJ 29 P2 6 ONCE El 31 P2 7 CLKOUT E 32 A3403 02 Figure A 3 83C196LD 52 pin PLCC Package A 2 DEFAULT CONDITIONS Table A 5 lists the values of the signals for the 87C196LA and 87C196LB during various oper ating conditions Table A 6 lists the same information for the 83C196LD Table A 4 defines the symbols used to represent the pin status Refer to the DC characteristics table in the datasheet for actual specifications for Vor Vm Voy and Vin Table A 4 Definition of Status Symbols Symbol Definition Symbol Definition 0 Voltage less than or equal to Vo Vu MDO Medium pull down 1 Voltage greater than or equal to Von Vu MD1 Medium pull up HiZ High impedance WKO Weak pull down LoZO Low impedance strongly driven low WK1 Weak pull up LoZ1 Low impedance strongly driven high ODIO Open drain I O A 7 8XC196LX SUPPLEMENT Table A 5 87C196LA LB Default Signal Conditions Upon RESET Port Alternate During RESET A Power A 5 Inactive Idle Signals Functions Active Note 6 down P0 7 2 ACH7 2 HiZ HiZ HiZ HiZ P1 0 EPAO T2CLK WKO WKO Note 1 Note 1 P1 1 EPA1 WKO WKO Note 1 Note 1 P1 2 EPA2 T2DIR W
25. and symbol encoding decoding circuitry The SST supports Huntzicker encoding of symbols which entails 10 4 Kb s variable pulse width VPW operation for valid edge detection on message receptions 8 5 8XC196LX SUPPLEMENT intel 8 3 2 1 Clock Prescaler Because the 87C196LB microcontroller can operate at a variety of input frequencies Fra the clock prescaler circuitry is used to provide a single internal clock frequency f 2 to ensure that the J1850 peripheral is clocked at the proper operating frequency This is accomplished through the programmable clock prescaler bits PRE1 0 in the J_CFG register Figure 8 17 on page 8 18 The prescale bits support input frequencies of 8 12 16 and 20 MHz on the XTALI pin With the phase locked loop PLL circuitry enabled the prescale bits can support input frequencies of 4 6 8 and 10 MHz on the XTALI pin Table 8 3 details the relationships between the input frequency the configuration of PLL the in ternal clock frequency and the prescaler bits Table 8 3 Relationships Between Input Frequency PLL and Prescaler Bits Farani Internal Clock Frequency PLL PLL 1 2 PRE1 PREO Disabled Enabled 8 MHz 4 MHz 4 MHz 0 0 12 MHz 6 MHz 6 MHz 0 1 16 MHz 8 MHz 8 MHz 1 0 20 MHz 10 MHz 10 MHz 1 1 8 3 2 2 Digital Filter To automatically reject noise spikes of 8 us or less in duration the J1850 controller uses a digital filter between the RXJ1850 input pin
26. byte residing in JRX_BUF is automatically shifted into J_RX freeing JRX_BUF for another reception This process continues until an end of data EOD symbol is en countered 8XC196LX SUPPLEMENT intel If a third byte is received before J_RX is read a J1850ST core interrupt is generated and the OVR_UNDR J_STAT 3 bit records a receiver overrun error in the J_STAT register 8 5 3 IFR Messages In frame response IFR messaging is identical in setup to standard messaging for both transmis sion and reception It uses the same registers to configure communicate and control data The difference is that the requestor initiating the IFR message sequence writes the message specifying a response from either one or more nodes in the system Framing a message in this manner by passes needless CPU overhead that can result from lengthy EOF symbols and it gives you a faster response to the information you are accessing from remote sites in your system Refer to In frame Response Messaging on page 8 12 for a detailed explanation 8 6 PROGRAMMING THE J1850 CONTROLLER This section explains how to configure the J1850 controller Several registers combine to control the configuration the command register the configuration register the delay compensation reg ister and the status register Programming the J1850 controller requires that you first program the configuration and delay registers during initialization You need to program these two
27. describes the event processor array channel differenc es Chapter 8 J1850 Communications Controller describes the 87C196LB s integrated J1850 controller and explains how to configure it Chapter 9 Minimum Hardware Considerations describes device reset options through the reset source register and discusses hardware design considerations Chapter 10 Special Operating Modes illustrates the internal clock control circuitry of the 87C196LA LB and describes how to enter and exit on circuit emulation ONCE mode Chapter 11 Programming the Nonvolatile Memory describes the memory maps and rec ommended circuits to support programming of the 87C196LA LB s 24 Kbytes of OTPROM 1 1 8XC196LX SUPPLEMENT intel Appendix A Signal Descriptions provides reference information for the 8XC196Lx de vice pins including descriptions of the pin functions reset status of the I O and control pins and package pin assignments Glossary defines terms with special meaning used throughout this supplement Index lists key topics with page number references 1 2 RELATED DOCUMENTS Table 1 1 lists additional doeuments that you may find useful in designing systems incorporating the 8XC196Lx microcontrollers Table 1 1 Related Documents Title and Description Order Number 8XC196Kx 8XC196Jx 87C196CA Microcontroller Family User s Manual 272258 87C196LA 20 MHz CHMOS 16 Bit M
28. input voltage change in the same direction Large differ ential nonlinearity errors can cause the converter to exhibit nonmonotonic behavior Most significant bit of a byte or most significant byte of a word Most significant word of a double word or quad word The configuration in which the microcontroller uses both A20 0 and AD15 0 for address and also uses AD15 0 for data See also demultiplexed bus A field effect transistor with an n type conducting path channel Semiconductor material with introduced impurities doping causing it to have an excess of negatively charged carriers Constants that can be accessed with nonextended instructions Constants in page OOH are near constants See also far constants Data that can be accessed with nonextended instruc tions Data in page OOH is near data See also far data An A D converter has no missing codes if for every output code there is a unique input voltage range which produces that code only Large differential nonlinearity errors can cause the converter to miss codes intel nonlinearity nonmaskable interrupts npn transistor off isolation p channel FET p type material PC phase locked loop PIC PIH PLL GLOSSARY The maximum deviation of code transitions of the terminal based characteristic from the corre sponding code transitions of the ideal characteristic Interrupts that cannot be masked disabled and cannot be assigned to the P
29. microcoded response that enables the PTS to complete a specific task quickly The entire microcoded response to multiple PTS interrupt requests The PTS routine is controlled by the contents of the PTS control block The movement of a single byte or word from the source memory location to the destination memory location intel PTS vector QUAD WORD quantizing error RALU repeatability error reserved memory resolution sample capacitor sample delay sample delay uncertainty sample time GLOSSARY A location in special purpose memory that holds the starting address of a PTS control block An unsigned 64 bit variable with values from 0 through 26 1 The QUAD WORD variable is supported only as the operand for the EBMOVI instruction An unavoidable A D conversion error that results simply from the conversion of a continuous voltage to its integer digital representation Quantizing error is always 0 5 LSB and is the only error present in an ideal A D converter Register arithmetic logic unit A part of the CPU that consists of the ALU the PSW the master PC the microcode engine a loop counter and six registers The variation in code transitions when comparing a number of actual characteristics from the same converter on the same channel with the same temper ature voltage and frequency conditions The amount of repeatability error depends on the comparator s ability to resolve very similar voltages
30. on 83C196LD 7 6 intel J1550 Communications Controller intel CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER The J1850 communications controller manages communications between multiple network nodes This integrated peripheral supports the 10 4 Kb s VPW variable pulse width medium speed class B in vehicle network protocol It also supports both the standard and in frame re sponse IFR message framing as specified by the Society of Automotive Engineering SAE J1850 revised May 1994 technical standards Its lower cost per node makes it suitable for diag nostics and non real time data sharing in applications with high numbers of nodes This chapter details the integrated J1850 controller and explains how to configure it 8 1 J1850 FUNCTIONAL OVERVIEW The integrated J1850 communications controller transfers messages between network nodes ac cording to the J1850 protocol The complete J1850 communications protocol solution includes an on chip J1850 digital logic controller working with an external analog bus transceiver circuit Figure 8 1 illustrates the J1850 protocol with the J1850 controller integrated on the 87C196LB 16 bit microcontroller and a standalone J1850 bus transceiver device The example uses the Har ris HIP7020 as the remote transceiver device J1850 Bus TXJ1850 TX HIP7020 puta rx EN 87C196LB Microcontroller A5168 01 Figure 8 1 Integrated J1850 Communications Protocol Solution
31. operating frequency f and the CLKOUT signal with each PLLEN pin configuration Table 2 3 details the relationships between the input frequency Ey 1 the PLLEN pin the operating frequency f the clock period t and state times intel ARCHITECTURAL OVERVIEW TxucH gt XTAL1 Too A o A o 16 MHz EE PLLEN 0 j t 62 5ns gt Internal A SE CLKOUT ESS u BE a SR Dr BB PLLEN 1 et 31 25ns gt Internal U VE NS A CLKOUT A3376 01 Figure 2 4 Effect of Clock Mode on Internal CLKOUT Frequency Table 2 3 Relationships Between Input Frequency Clock Multiplier and State Times F f Frequency PLLEN Multiplier Input Frequency to Codi State Time on XTAL1 the Divide by two Circuit Period 4 MHz 0 1 4 MHz 250 ns 500 ns 8 MHz 0 1 8 MHz 125 ns 250 ns 12 MHz 0 1 12 MHz 83 5 ns 167 ns 16 MHz 0 1 16 MHz 62 5 ns 125 ns 20 MHz 0 1 20 MHz 50 ns 100 ns 4 MHz 1 2 8 MHz 125 ns 250 ns 8 MHz 1 2 16 MHz 62 5 ns 125 ns 10 MHz 1 2 20 MHz 50 ns 100 ns 2 4 EXTERNAL TIMING You can control the output frequency on the CLKOUT pin by programming two uneraseable PROM bits Figure 2 5 illustrates the read only USFR1 which reflects the state of the unerasable PROM bits You can select one of three frequencies f 2 f 4 or f 8 As Figure 2 2 on page 2 3 shows the configurable divider accepts the output of the clock generators f 2 and further di vides
32. reserved locations Any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine The basic time unit of the microcontroller the combined period of the two internal timing signals PH1 and PH2 Because the microcontroller can operate at many frequencies this manual defines time requirements in terms of state times rather than in specific units of time An A D conversion method that uses a binary search to arrive at the best digital representation of an analog input 66499 t Lowercase clock represents the period of the internal Change in the stated variable for each degree Centigrade of temperature change The change in a specification due to a change in temperature Temperature drift can be calculated by using the temperature coefficient for the specification An actual characteristic that has been translated and scaled to remove zero offset error and full scale error A terminal based characteristic resembles an actual characteristic with zero offset error and full scale error removed A graph of output code versus input voltage the characteristic of the A D converter Errors inherent in an analog to digital conversion process quantizing error zero offset error full scale error differential nonlinearity and nonlinearity Errors that are hardware dependent rather than being inherent in the process itself include feedthrough repeatability channel to cha
33. signals the presence of an error in your incoming message which immedi ately sets the J1850 bus error J1850BE bit in the J_ STAT register Figure 8 19 on page 8 21 intel J1850 COMMUNICATIONS CONTROLLER 8 3 1 2 Bus Contention Bus contention arises when multiple nodes attempt to access and transmit message frames across the J1850 bus simultaneously This creates a conflict on the bus The recognition of conflicting symbols or bits on the bus is referred to as contention detection For example if a node observes a difference between a symbol it transmits to the J1850 bus and the symbol that it detects on the bus that node has detected contention to the transmission of its message frame Only one message frame from one node vying for the bus wins arbitration on each symbol or bit of its frame This winning message frame does not experience or detect contention The message frames that were not awarded arbitration will experience contention 8 3 1 3 Bit Arbitration A bit arbitration scheme is used to resolve such conflicts as bus contention The J1850 protocol uses the carrier sense multiple access CSMA bit arbitration scheme Bit arbitration is the pro cess of settling conflicts that occur when multiple nodes attempt to transmit one bit or symbol at a time across a single bus A symbol is simply a timing level formatted bit By definition a node that detects contention has lost arbitration and will discontinue transmitting any further symb
34. status registers Table 8 1 J1850 Controller Signals Signal Type Description RXJ1850 Receive Carries digital symbols from a remote transceiver to the J1850 controller TXJ1850 O Transmit Carries digital symbols from the J1850 controller to a remote transceiver Table 8 2 Control and Status Registers Mnemonic Address Description J_CFG 1F54H J1850 Configuration Program this byte register to specify the oscillator prescaler divisor mode of operation and normalization bit format You must write to this register during the initialization sequence J_CMD 1F51H J1850 Command Program this byte register to specify the number of bytes to be transmitted in the next message frame This register also monitors the status of the message transmission in progress and it can abort ignore or retry a message if necessary Read this register to determine the status of transmissions in progress J_DLY 1F58H J1850 Delay Compensation Program this byte register to define the length of the delay time through the external transceiver to compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration You must write to this register during the initialization sequence J_RX 1F52H J1850 Receiver Read this byte register to receive data in byte increments from the J1850 bus to the microcontroller CPU This register is buf
35. that frequency to produce the desired output frequency The CLK 1 0 bits control the divisor divide f 2 by either 1 2 or 4 2 5 8XC196LX SUPPLEMENT intel USFR1 read only 4 Gn haat eset State The UPROM special function register 1 USFR1 reflects the status of unerasable programmable read only memory UPROM locations This read only register reflects the status of two bits that control the output frequency on CLKOUT 7 0 CLK1 CLKO Bit Bit Number Mnemonic Function 7 2 Reserved 1 0 CLK1 0 CLKOUT Control These bits reflect the programmed frequency of the CLKOUT signal CLK1 CLKO 0 0 divide by 1 CLKOUT f 2 0 1 divide by 2 CLKOUT f 4 1 0 divide by 4 CLKOUT f 8 1 1 divide by 1 CLKOUT f 2 Figure 2 5 Unerasable PROM 1 USFR1 Register LA LB Only To program these bits write the correct value to the locations shown in Table 2 4 using slave pro gramming mode During normal operation you can determine the values of these bits by reading the UPROM SFR Figure 2 5 You can verify a UPROM bit to make sure it programmed but you cannot erase it For this rea son Intel cannot test the bits before shipment However Intel does test the features that the UP ROM bits enable so the only undetectable defects are unlikely defects within the UPROM cells themselves Table 2 4 UPROM Programming Values and Locations To
36. to the J1850 bus Figure 8 12 J1850 Transmitter J_TX Register Transmitting the message requires that you first program the J1850 command J_CMD register to specify the number of bytes you want to transfer across the J1850 bus The number of bytes specified must include the header byte s After the start of frame SOF symbol is put on the bus the first header byte is transferred to J_TX for transmission This byte will automatically be trans ferred into the J1850 transmit buffer JTX_BUF and the second byte of the message frame will be written to J_TX The transfer of the first byte to JTX_BUF triggers the transmission process and generates the J1850 transmission J1850TX interrupt if it is enabled signaling that J_TX is available for another byte Figure 8 13 Message transmit interrupt J1850TX set J1850 Bus JTX_BUF A5235 01 Figure 8 13 J1850 Transmit Message Structure After the byte in JTX_BUF is transmitted the byte residing in J_TX is automatically shifted into JTX_BUF freeing J_TX for another byte This process continues until the CSM has resolved the number of message bytes MSG3 0 programmed into the J_CMD register If the last message byte being transmitted is shifted out before the MSGx count expires a J1850ST core interrupt is generated and the OVR_UNDR J_STAT 3 bit records a transmitter underflow error in the J_ STAT register 8 14 intel J1850 COMMUNICATIONS CON
37. 3 EPAx Shared EPA interrupt EPA 6 9 capture compare channel events EPA 0 1 compare channel eventsitt EPA 0 3 and 8 9 capture compare overruns and timer overflows can generate this multiplexed interrupt The EPA mask and pending registers decode the EPAx interrupt Write the EPA mask registers to enable the interrupt sources read the EPA pending registers to determine which source caused the interrupt ttt 87C196LA LB only Bits 6 7 are reserved on the 87C196LA and bits 5 7 are reserved on the 83C196LD For compatibility with future devices write zeros to these bits Figure 4 1 Interrupt Mask INT_MASK Register 4 3 8XC196LX SUPPLEMENT intel INT _MASK1 Address 0013H E Reset State 00H The interrupt mask 1 INT_MASK1 register enables or disables masks individual interrupt requests The El and DI instructions enable and disable servicing of all maskable interrupts INT_MASK1 can be read from or written to as a byte register PUSHA saves this register on the stack and POPA restores it 7 0 LB NMI EXTINT RI TI SSIO1 SSIOO J1850ST 7 0 LA LD NMI EXTINT RI TI SSIO1 SSIOO Bit A Number Function 7 04 Setting a bit enables the corresponding interrupt Bit Mnemonic Interrupt Description NMI Nonmaskable Interrupt EXTINT EXTINT Pin Reserved RI SIO Receive TI SIO Transmit SSIO1 SSIO1 Transfer SSIOO SSIOO Transfer J1850ST
38. 40H 0073H OAOH 11 2 OTPROM ADDRESS MAP The OTPROM contains customer specified special purpose and program memory Table 11 2 The 128 byte special purpose address partition is used for interrupt vectors the chip configura tion bytes CCBs and the security key Several locations are reserved for testing or for use in future products Write the value 20H or FFH indicated in Table 11 2 to each reserved location The remainder of the OTPROM is available for code storage 11 1 8XC196LX SUPPLEMENT Table 11 2 87C196LA LB OTPROM Address Map Address Range AR Hex Description LEFF Program memor 2080 ogra emory 207F Reserved each location must contain FFH 205E 205D 2040 PTS vectors 203F A 2030 Upper interrupt vectors 202F A 2020 Security key 201F 201C Reserved each location must contain FFH 201B Reserved must contain 20H 201A CCB1 2019 Reserved must contain 20H 2018 CCBO 2017 F 2016 OFD flag for QROM or MROM codes 2015 2014 Reserved each location must contain FFH 2013 2 2000 Lower interrupt vectors Intel manufacturing uses this location to determine whether to program the OFD bit Customers with quick ROM QROM or masked ROM MROM codes who desire oscillator failure detection should equate this location to the value OCDEH 11 3 SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAP Figure 11 1 shows the circu
39. 8XC196Lx Supplement to 8XC196Kx 8XC196Jx 87C196CA User s Manual August 1998 Order Number 272973 002 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The 8XC196Lx 8XC196Kx 8XC196Jx and 87C196CA microprocessors may contain design defects or errors known as errata which may cause the products to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distr
40. A7 EPA8 EPA9 OVRO OVRI 7 0 OVR2 OVR3 OVR8 OVR9 en Function 15 07 Any set bit indicates that the corresponding EPAx interrupt source is pending The bit is cleared when software reads the EPA interrupt priority vector register EPAIPV Bits 2 5 and 14 15 are reserved on the 8XC196Lx device family For compatibility with future devices write zeros to these bits Figure 7 5 EPA Interrupt Pending EPA_PEND Register EPA_PEND1 Address 1FA6H Reset State 00H When hardware detects a pending EPAx interrupt it sets the corresponding bit in the EPA interrupt pending register EPA_PEND or EPA_PEND1 The EPAIPV register contains a number that identifies the highest priority active multiplexed interrupt source When EPAIPV is read the EPA interrupt pending bit associated with the EPAIPV priority value is cleared 7 0 COMPO COMPIi OVRTM1 OVRTM2 Bit z Number Function 7 4 Reserved always write as zeros 3 07 Any set bit indicates that the corresponding EPAx interrupt source is pending The bit is cleared when the EPA interrupt priority vector register EPAIPV is read i 87C196LA LB only reserved on 83C196LD Figure 7 6 EPA Interrupt Pending 1 EPA_PEND1 Register 7 5 8XC196LX SUPPLEMENT intel 7 1 3 EPA Interrupt Priority Vector Register Figure 7 7 illustrates the EPA interrupt priority vector EPAIPV register for the 8XC196Lx mi c
41. AD13 9 P4 0 14 PBUS 9 13 AD14 8 P4 1 13 PBUS 10 12 Power amp Ground AD15 7 P4 2 12 PBUS 11 11 Name Pin P4 3 11 PBUS 12 10 ANGND 39 Input Output P4 4 10 PBUS 13 9 Vec 26 Name Pin P4 5 9 PBUS 14 8 Vpp 4 P0 2 ACH2 33 P4 6 8 PBUS 15 7 VREF 40 P0 3 ACH3 34 P4 7 7 PMODE O 35 Vos 3 P0 4 ACH4 35 P5 0 2 PMODE 1 36 Vesi 1 P0 5 ACH5 36 P5 2 6 PMODE 2 37 Vesi 25 P0 6 ACH6 37 P5 3 5 PMODE 3 38 P0 7 ACH7 38 P6 0 EPA8 COMPO 45 PROG 29 P1 0 EPAO T2CLK 44 P6 1 EPA9 COMP1 46 PVER 27 P1 1 EPA1 43 P6 4 SCO 47 P1 2 EPA2 T2DIR 42 P6 5 SDO 48 P1 3 EPA3 41 P6 6 SC1 49 P2 0 TXD 27 P6 7 SD1 50 SIGNAL DESCRIPTIONS EI AD15 P4 7 PBUS 15 6 E P5 2 PLLEN WR WRL 5 a P5 3 RD 2 FI P5 0 ADV ALE 52 FI XTAL1 51 EI XTAL2 50 FI P6 7 SD1 49 FI P6 6 SC1 48 FI P6 5 SDO 47 FI P6 4 SCO AD14 P4 6 PBUS 14 LJ 8 AD13 P4 5 PBUS 13 9 AD12 P4 4 PBUS 12 amp AD11 P4 3 PBUS 11 amp P1 1 EPA1 AD10 P4 2 PBUS 10 amp AN87C196LA20 P1 2 EPA2 T2DIR AD9 P4 1 PBUS 9 P1 3 EPA3 AD8 P4 0 PBUS 8 amp VREF AD7 P3 7 PBUS 7 amp View of component as ANGND AD6 P3 6 PBUS 6 E ADS P35 PBUS5 Q mounted on PC board AD4 P3 4 PBUS 4 amp AD3 P3 3 PBUS 3 amp AD2 P3 2 PBUS 2 EJ 20 P0 3 ACH3 Voc E 26 P2 0 TXD PVER E 27 P2 1 RXD PALE TJ 28 EA CI 24 P2 2 EXTINT PRO
42. CPU overhead of transmitting these messages alone amounts to a minimum of 4 96 ms refer to Table 8 4 on page 8 11 for all symbol timings In frame Response IFR Frame The number of data bytes to be transferred is unspecified if OEH is written to J_CMD3 0 A5229 01 Figure 8 9 IFR Type 1 Message Frame 8 4 2 2 IFR Messaging Type 2 Single Byte Multiple Responders When response time is the highest consideration IFR messaging type 2 is desirable IFR type 2 messaging can monitor up to 32 remote nodes on a given request see Figure 8 10 While it al lows only one byte of information per response in many cases a single byte of information is more than adequate In our example suppose that each node sensor detected a pressure of 75 P S I pounds per square inch The response the value 75 would take a single byte 46H to communicate the reply The maximum overhead required is 1 24 ms or one fourth the time it would take type 1 messaging to achieve the same results 8 12 intel J1850 COMMUNICATIONS CONTROLLER In frame Response IFR Frame lt IFR Data Field Ty 1 3 Bytes 1 11 Bytes Header Datat t The number of data bytes to be transferred is unspecified if OEH is written to J_CMD3 0 TT Each Dy block in the IFR data field represents a byte of data from a different remote node A5227 01 Figure 8 10 IFR Type 2 Message Frame 8 4 2 3 IFR Messaging Type 3 Multiple Bytes Single Responder
43. G E 29 RESET dd 23 Vssi dd 25 P2 4 AINC EJ 30 P0 2 ACH2 CI 33 P2 6 ONCE CPVER E 31 ADO P3 0 PBUS 0 E 22 P2 7 CLKOUT PACT EJ 32 AD1 P3 1 PBUS 1 E 21 P6 1 EPA9 COMP1 P6 0 EPA8 COMPO P1 0 EPAO T2CLK P0 7 ACH7 PMODE 3 P0 6 ACH6 PMODE 2 P0 5 ACH5 PMODE 1 P0 4 ACH4 PMODE O A3419 03 Figure A 1 87C196LA 52 pin PLCC Package A 3 8XC196LX SUPPLEMENT In Table A 2 87C196LB Signals Arranged by Functional Categories tel A 4 Addr amp Data Input Output Cont d Program Control Processor Control Name Pin Name Pin Name Pin Name Pin ADO 22 P2 1 RXD 28 AINC 30 EA 24 AD1 21 P2 2 29 CPVER 31 EXTINT 29 AD2 20 P2 4 RXJ1850 30 PACT 32 PLLEN 6 AD3 19 P2 6 TXJ1850 31 PALE 28 RESET 23 AD4 18 P2 7 32 PBUS O 22 XTAL1 52 AD5 17 P3 0 22 PBUS 1 21 XTAL2 51 AD6 16 P3 1 21 PBUS 2 20 AD7 15 P3 2 20 PBUS 3 19 Bus Cont amp Status AD8 14 P3 3 19 PBUS 4 18 Name Pin AD9 13 P3 4 18 PBUS 5 17 ADV ALE 2 AD10 12 P3 5 17 PBUS 6 16 CLKOUT 32 AD11 11 P3 6 16 PBUS 7 15 RD 5 AD12 10 P3 7 15 PBUS 8 14 WR WRL 6 AD13 9 P4 0 14 PBUS 9 13 AD14 8 P4 1 13 PBUS 10 12 Power amp Ground AD15 7 P4 2 12 PBUS 11 11 Name Pin P4 3 11 PBUS 12 10 ANGND 39 Input Output P4 4 10 PBUS 13 9 Vec 26 Name Pin P4 5 9 PBUS 14 8 Vpp 4 P0 2 ACH2 33 P4 6 8 PBUS
44. KO WKO Note 1 Note 1 P1 3 EPA3 WKO WKO Note 1 Note 1 P2 0 TXD WKO WKO Note 1 Note 1 P2 1 RXD WKO WKO Note 1 Note 1 P2 2 EXTINT WKO WKO Note 1 Note 1 P2 4 RXJ1850 LB only WKO WKO Note 1 Note 1 P2 6 ONCE TXJ1850 LB only MDO MDO Note 1 Note 1 P2 7 CLKOUT CLKOUT active CLKOUT active Note 1 Note 2 LoZO 1 LoZO 1 P3 7 0 AD7 0 WKO HiZ Note 4 Note 4 P4 7 0 AD15 8 WKO HiZ Note 4 Note 4 P5 0 ALE ADV WKO WKO Note 1 Note 1 P5 2 WR WRL WKO WKO Note 1 Note 1 P5 3 RD WKO WKO Note 1 Note 1 P6 0 EPA8 COMPO WKO WKO Note 1 Note 1 P6 1 EPA9 COMP1 WKO WKO Note 1 Note 1 P6 4 SCO WKO WKO Note 1 Note 1 P6 5 SDO WKO WKO Note 1 Note 1 P6 6 SC1 WKO WKO Note 1 Note 1 P6 7 SD1 WKO WKO Note 1 Note 1 EA WK1 Note 5 WK1 WK1 WK1 RESET LoZO MD1 MD1 MD1 Vop HiZ HiZ LoZ1 LoZ1 XTAL1 Osc input Osc input Osc input HiZ Osc input HiZ Hiz Hiz XTAL2 Osc output Osc output Osc output Note 3 LoZO 1 LoZO 1 LoZ0 1 NOTES 1 If Px_MODE y 0 port is as programmed If Px_MODE y 1 pin is as specified by Px_DIR and the associated peripheral 2 If P2_MODE 7 0 pin is as programmed If P2 MODE 7 1 pin is Lozo 3 If XTAL1 0 pin is LoZ1 If XTAL1 1 pin is Lozo 4 If EA 0 port is HiZ If EA 1 port is open drain I O 5 Although EA is weakly pulled high do not allow it to float Always tie EA to Vec if it is not connected to an external device
45. MODE y 1 pin is as specified by Px_DIR and the associated peripheral IRON to an external device D If P2_MODE 7 0 pin is as programmed If P2 MODE 7 1 pin is LoZO If XTAL1 0 pin is LoZ1 If XTAL1 1 pin is Lozo If EA 0 port is HiZ If EA 1 port is open drain I O Although EA is weakly pulled high do not allow it to float Always tie EA to Vec if it is not connected The values in this column are valid until your software writes to Px_MODE A 9 intel Glossary intel GLOSSARY This glossary defines acronyms abbreviations and terms that have special meaning in this man ual Chapter 1 discusses notational conventions and general terminology absolute error accumulator actual characteristic A D converter ALU assert attenuation bit BIT bit arbitration break before make The maximum difference between corresponding actual and ideal code transitions Absolute error accounts for all deviations of an actual A D converter from an ideal converter A register or storage location that forms the result of an arithmetic or logical operation A graph of output code versus input voltage of an actual A D converter An actual characteristic may vary with temperature supply voltage and frequency conditions Analog to digital converter An internal peripheral that converts an analog input to a digital value Arithmetic logic unit The part of the RALU that processes arithme
46. ONS FOR 8XC196LA LB AND LD With the exception of a few new multiplexed functions the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers The 8XC196Jx microcontrollers are 52 lead versions of 8XC196Kx microcontrollers Follow these recommendations to help maintain hardware and software compatibility between the 8XC196Lx 8XC196Kx and future microcontrollers 9 2 Bus width Since the 8XC196Lx has neither a WRH nor a BUSWIDTH pin the microcontroller cannot dynamically switch between 8 and 16 bit bus widths Program the CCBs to select 8 bit bus mode Wait states Since the 8XC196Lx has no READY pin the microcontroller cannot rely on a READY signal to control wait states Program the CCBs to limit the number of wait states 0 1 2 or 3 EPA6 EPA7 These functions exist in the 8XC196Lx but the associated pins are omitted You can use these functions as software timers to start A D conversions on 87C196LA and LB only or to reset the timers Slave port Since the 8XC196Lx has no P5 1 SLPCS and P5 4 SLPINT pins you cannot use the slave port ONCE mode On the 8XC196Lx the ONCE mode entry function is multiplexed with P2 6 and TXJ1850 on the 87C196LB rather than with P5 4 as it is on the 8XC196Kx P5 4 SLPINT ONCE NMI Since the 8XC196Lx has no NMI pin the nonmaskable interrupt is not supported Initialize the NMI vector at location 203EH to point to a RET instruction This method provides gli
47. OO Bit z Number Function 7 07 Any set bit indicates that the corresponding interrupt is pending The interrupt bit is cleared Bit 5 is reserved on the 8XC196Lx devices and bit 0 is reserved on the 87C196LA and 83C196LD For compatibility with future devices always write zeros to these bits Figure 4 4 Interrupt Pending 1 INT_PEND1 Register 4 2 3 Peripheral Transaction Server Registers Figures 4 5 and 4 6 illustrate the PTS interrupt select and service registers for the 8XC196Lx mi crocontrollers 4 6 intel STANDARD AND PTS INTERRUPTS PTSSEL Address Reset State 0004H 0000H The PTS select PTSSEL register selects either a PTS microcode routine or a standard interrupt service routine for each interrupt request Setting a bit selects a PTS microcode routine clearing a bit selects a standard interrupt service routine In PTS modes that use the PTSCOUNT register hardware clears the corresponding PTSSEL bit when PTSCOUNT reaches zero The end of PTS interrupt service routine must reset the PTSSEL bit to re enable the PTS channel 15 8 LA EXTINT RI TI SSIO1 SSIOO 7 0 AD EPAO EPA1 EPA2 EPA3 EPAx 15 8 LB EXTINT RI TI SSIO1 SSIOO J1850ST 7 0 J1850RX J1850TX AD EPAO EPA1 EPA2 EPA3 EPAx 15 8 LD EXTINT RI TI SSIO1 SSIOO 7 0 EPAO EPA1 EPA2 EPA3 EPAx nn Function 14 07 Setting a bit causes the
48. ORS AND PRIORITIES nnen eeen nenea 4 1 4 2 INTERRUPT REGISTERS ii ais sign 2 2 2 Ne a cul ied 4 2 4 2 1 Interrupt Mask Registers nn vanner enen neerenseenvenseevensvensnseeennaenenenneeeensennennoee 4 3 4 2 2 Interrupt Pending Registers annen nennen ern eennenenserenennerveneneensoevennnenennnen 4 4 4 2 3 Peripheral Transaction Server Registers nanne nene neam ne nana 4 6 CHAPTER 5 I O PORTS 5 1 VO PORTS OVERVIEW i ta oi rant al a agata Pa D ia e a ety 5 1 5 2 INTERNAL STRUCTURE FOR PORTS 1 2 5 AND 6 BIDIRECTIONAL PORTS 5 1 5 2 1 Configuring Ports 1 2 5 and 6 Bidirectional Ports aaneen 5 3 5 2 2 Special Bidirectional Port Considerations nnen nennen eeenenenneeennvennenen eeen 5 4 5 3 INTERNAL STRUCTURE FOR PORTS 3 AND 4 ADDRESS DATA BUS 5 5 8XC196LX SUPPLEMENT intel CHAPTER 6 SYNCHRONOUS SERIAL I O PORT 6 1 SSIO 0 CLOCK REGISTER camana hia ia a da t aa en 6 1 6 2 SSIO1 CLOCK REGISTER tic ci at delle 6 2 CHAPTER 7 EVENT PROCESSOR ARRAY 7 1 EPA FUNCTIONAL OVERVIEW eee nenea nenea nennen nn 7 1 7 1 1 EPA Mask Registers cuina aa RD 7 4 7 1 2 EPA Pending Registers moi ic eee Bei ale Dai i ee i ian a a ieee 7 5 7 1 3 EPA Interrupt Priority Vector Register mean eee nenea 7 6 CHAPTER 8 J1850 COMMUNICATIONS CONTROLLER 8 1 J1850 FUNCTIONAL OVERVIEW men nana nana nana 8 1 8 2 J1850 CONTROLLER SIGNALS AND REGISTERS nenea nenea nana 8 3 8 3 J1850 CONTROLLER OPERATION
49. RC bytes and a series of start and end symbols Unlike the standard message frame the actual length of the IFR message frame will differ based on the desired response Consider the following example a system s controller the requestor requests an information up date from each of four nodes the responders in the system With type messaging the controller can receive a limited information update if it sends out four separate transmissions With type 2 messaging the controller can receive a limited information update by sending one message With type 3 messaging the controller can receive unlimited information however it will require four separate transmissions The following subsections detail this example for the three IFR messag ing types 8 4 2 1 IFR Messaging Type 1 Single Byte Single Responder No IFR messaging type carries a distinct advantage or disadvantage over the other messaging types IFR messaging type 1 Figure 8 9 is ideal for use when requesting small amounts of in formation from a single source in your system In the above example suppose you want to know how many pounds of pressure each of the four remote node sites experienced after the controller sent out a request to each node sensor to exert a given amount of pressure If you use type 1 mes saging the controller will send four separate serial messages to the remote node sites in the sys tem and wait for their responses Keeping the data timing a constant the
50. SW PTS PTSCB PTS control block PTS cycle PTS interrupt PTS mode PTS routine PTS transfer Glossary 8 intel NMI stack overflow or any maskable interrupt Two of the nonmaskable interrupts unimplemented opcode and software trap are not prioritized they vector directly to the interrupt service routine when executed A partition of memory where instructions can be stored for fetching and execution An instruction that prevents an interrupt from being acknowledged until after the next instruction executes The protected instructions are DI EI DPTS EPTS POPA POPE PUSHA and PUSHF Processor status word The high byte of the PSW is the status byte which contains one bit that globally enables or disables servicing of all maskable interrupts one bit that enables or disables the PTS and six Boolean flags that reflect the state of the current program The low byte of the PSW is the INT_MASK register A PUSHA or POPA instruction saves or restores both bytes PSW INT_MASK a PUSHF or POPF saves or restores only the PSW Peripheral transaction server The microcoded hardware interrupt processor See PTS control block A block of data required for each PTS interrupt The microcode executes the proper PTS routine based on the contents of the PTS control block The microcoded response to a single PTS interrupt request Any maskable interrupt that is assigned to the PTS for interrupt processing A
51. TROLLER NOTE An overrun condition can occur on transmission if the transmit buffer JTX_BUF is overwritten 8 5 2 Receiving Messages For a message reception after a SOF is detected on the bus the controller starts to shift data sym bols into the J1850 receive buffer JRX_BUF until an entire data byte has been received This byte is automatically transferred into the J1850 receive J_RX register Figure 8 14 and the sub sequent byte is written into the empty JRX_BUF J_RX Address 1F52H Reset State 00H The J1850 receiver J_RX register transfers received data in byte increments from the J1850 bus to the microcontroller CPU This register is buffered to allow for reception of a second data byte while the first data byte is being read This byte register can be read or written and is addressable through windowing 7 0 Receive Byte ine iaca Function 7 0 DB7 0 Data Bits These eight bits compose the last data byte received from the J1850 bus Figure 8 14 J1850 Receiver J_RX Register The transfer of the first byte to J_RX triggers the reception process and generates the J1850 re ception J1850RX interrupt if it is enabled signaling that JRX_BUF is available for another byte Figure 8 15 A J1850 Bus JRX_BUF Message receive eo ep ee iii gt interrupt J1850RX set CPU A5236 01 Figure 8 15 J1850 Receive Message Structure After J_RX is read the
52. TS for processing The nonmaskable interrupts are stack overflow unimple mented opcode software trap and NMI The DI disable interrupt service and EI enable interrupt service instructions have no effect on nonmaskable interrupts A transistor consisting of one part p type material and two parts n type material The ability of an A D converter to reject isolate the signal on a deselected off output A field effect transistor with a p type conducting path Semiconductor material with introduced impurities doping causing it to have an excess of positively charged carriers Program counter A component of the clock generation circuitry The phase locked loop PLL and the input pin PLLEN combine to enable the microcontroller to attain its maximum operating frequency with an external clock whose frequency is either equal to or one half that maximum frequency or with an external oscillator whose frequency is one half that maximum frequency Programmable interrupt controller The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called simply the interrupt controller Peripheral interrupt handler An integrated module that provides interrupt vectors for specific EPA interrupt requests to the interrupt controller or PTS See phase locked loop Glossary 7 8XC196LX SUPPLEMENT prioritized interrupt program memory protected instruction P
53. TS service request or a standard interrupt service request for J1850TX J1850RX and J1850ST interrupts respectively PTSSRV 0006H PTS Service Bits 6 7 and 8 of this word register are set by hardware to request an end of PTS interrupt for the J1850 8 3 J1850 CONTROLLER OPERATION This section describes the control state machine which contains the cyclic redundancy check generator and the symbol synchronization and timing circuitry for J1850 transmissions and re ceptions 8 3 1 Control State Machine The control state machine CSM represents the engine of the digital circuitry portion of the J1850 communications controller The CSM handles all message framing for standard and in frame response IFR messaging data validation bus contention bit arbitration and error detec tion 8 3 1 1 Cyclic Redundancy Check Generator The cyclic redundancy check CRC generator circuitry calculates and checks the CRC byte gen erated for both transmitted and received standard messages as specified by SAE J1850 protocol specification for class B in vehicle networks The CRC calculation is a code byte of information that verifies the proper reception or transmission of your message The calculated CRC code byte is always appended as the last byte of your transmitted message On reception the calculated CRC checksum byte always results in a value of C4H for valid messages An invalid CRC check sum during reception
54. X MSG_RX J1850BE Bit Bit 7 Function Number Mnemonic unctio 7 IFR_RCV In frame Response Received This bit indicates whether the IFR byte has been received and is ready to be read from the J1850 receiver J_RX register 0 no action 1 IFR byte received 6 BUS_CONT J1850 Bus Contention This bit indicates whether bus contention has been detected and arbitration has been lost 0 no action 1 bus contention 5 BUS STAT J1850 Bus Status This bit indicates whether a transmission or reception is in progress on the J1850 bus 0 J1850 bus idle 1 J1850 bus busy 4 BRK_RCV Break Received This bit indicates whether a BRK symbol has been detected on the J1850 bus 0 no action 1 BRK symbol detected 3 OVR_UNDR Receive Overrun Transmit Underflow Interrupt This bit indicates whether a receive buffer overrun OVR or transmit buffer underflow UNDR has occurred An overrun occurs when a symbol is received while both J_RX and JRX_BUF contain unread bytes An underflow occurs when a transmission is attempted while both J_TX and JTX_BUF are empty 0 normal operation 1 OVR or UNDR detected Figure 8 19 J1850 Status J_STAT Register 8 21 8XC196LX SUPPLEMENT intel J_STAT Address 1F53H Reset State 00H The J1850 status J_STAT register provides the current status of the message transfer the receive and transmit buffers and th
55. X SUPPLEMENT external address far constants far data feedthrough FET full scale error hold latency ideal characteristic input leakage input series resistance integer INTEGER Glossary 4 intel A 21 bit address is presented on the microcontrollers pins The address decoded by an external device depends on how many of these address pins the external system uses See also internal address Lowercase f represents the frequency of the internal clock Constants that can be accessed only with extended instructions See also near constants Data that can be accessed only with extended instruc tions See also near data The attenuation from an input voltage on the selected channel to the A D output after the sample window closes The ability of the A D converter to reject an input on its selected channel after the sample window closes Field effect transistor The difference between the ideal and actual input voltage corresponding to the final full scale code transition of an A D converter The time it takes the microcontroller to assert HLDA after an external device asserts HOLD The characteristic of an ideal A D converter An ideal characteristic is unique its first code transition occurs when the input voltage is 0 5 LSB its full scale final code transition occurs when the input voltage is 1 5 LSB less than the full scale reference and its code widths are all exactly 1 0 LSB Thes
56. Zero offset error 1s the difference between 0 5 LSB and the actual input voltage that triggers an A D converter s first code transition intel Index intel A Address map 3 1 Address partitions map 3 1 OTPROM 11 1 program memory 11 1 special purpose memory 11 1 ALE idle powerdown reset status A 8 A 9 B Block diagram 8XC196Lx 2 2 C CLKOUT and internal timing 2 2 2 4 idle powerdown reset status A 8 A 9 output frequency 2 5 reset status 5 2 Clock circuitry 2 3 10 2 D delay register 8 20 Design considerations 9 2 Device pin reset status A 8 A 9 Documents related 1 2 E EA idle powerdown reset status A 8 A 9 EPA interrupt mask 1 register 7 4 interrupt mask register 7 4 interrupt pending 1 register 7 5 interrupt pending register 7 5 interrupt priority vector register 7 6 ESD protection 5 2 5 5 F Formulas clock period t 2 4 PH1 and PH2 frequency 2 4 state time 2 4 INDEX Frequency f 2 4 ExraLt gt 2 4 H Hardware pin reset status A 8 A 9 Idle mode pin status A 8 A 9 Internal timing 2 2 10 1 Interrupts mask 1 register 4 4 mask register 4 3 pending 1 register 4 6 pending register 4 5 priorities 4 2 sources 4 2 vectors 4 2 J J1850 communications controller 8 3 8 21 delay compensation 8 20 in frame response command register 8 17 interrupt status register 8 21 oscillator prescaler configuration register 8 18 receiver r
57. a RAM indexed External device memory er on or I O connected to a address data bus Indirect Upper register file a 03FF 01FF 017F 02FF 03FF 03FF f indexed or 0100 0100 0100 0100 0100 0100 cee register windowed direct Lower register file Direct OOFF OOFF OOFF OOFF OOFF OOFF EN 0000 0000 0000 0000 0000 0000 register RAM stack indirect or pointer and CPU SFRs indexed NOTES 1 After a reset the device fetches its first instruction from 2080H 2 The content or function of these locations may change in future device revisions in which case a program that relies on a location in this range might not function properly 3 2 REGISTER FILE Figure 3 1 compares the register file addresses of the 8XC196Lx and 8XC196Kx The register file in Figure 3 1 is divided into an upper register file and a lower register file The upper register file consists of general purpose register RAM The lower register file contains general purpose register RAM along with the stack pointer SP and the CPU special function registers SFRs Table 3 2 lists the register file memory addresses The RALU accesses the lower register file di rectly without the use of the memory controller It also accesses a windowed location directly see Windowing on page 3 6 The upper register file and the peripheral SFRs can be win dowed Registers in the lower register file and registers being windowed can be accessed with regist
58. age current from an analog input pin to ground or to the reference voltage Vazp The act of making a signal inactive disabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To deassert RD is to drive it high to deassert ALE is to drive it low The configuration in which the microcontroller uses separate lines for address and data address on A20 0 data on AD15 0 for a 16 bit bus or AD7 0 for an 8 bit bus See also multiplexed bus The difference between the actual code width and the ideal one LSB code width of the terminal based characteristic of an A D converter It provides a measure of how much the input voltage may have changed in order to produce a one count change in the conversion result Differential nonlinearity is a measure of local code width error nonlinearity is a measure of overall code transition error The process of introducing a periodic table Group III or Group V element into a Group IV element e g silicon A Group III impurity e g indium or gallium results in a p type material A Group V impurity e g arsenic or antimony results in an n type material Any 32 bit unit of data An unsigned 32 bit variable with values from O through 2 Event processor array An integrated peripheral that provides high speed input output capability Electrostatic discharge Glossary 3 8XC196L
59. and the extent to which random noise contributes to the error A memory location that is reserved for factory use or for future expansion Do not use a reserved memory location except to initialize it The number of input voltage levels that an A D converter can unambiguously distinguish between The number of useful bits of information that the converter can return A small 2 3 pF capacitor used in the A D converter circuitry to store the input voltage on the selected input channel The time period between the time that A D converter receives the start conversion signal and the time that the sample capacitor is connected to the selected channel The variation in the sample delay The period of time that the sample window is open That is the length of time that the input channel is actually connected to the sample capacitor Glossary 9 8XC196LX SUPPLEMENT sample time uncertainty sample window sampled inputs SAR set SFR SHORT INTEGER sign extension sink current source current SP special interrupt Glossary 10 intel The variation in the sample time The period of time that begins when the sample capacitor is attached to a selected channel of an A D converter and ends when the sample capacitor is disconnected from the selected channel All input pins with the exception of RESET are sampled inputs The input pin is sampled one state time before the read buffer is enabled Sam
60. and the symbol synchronization logic A noise spike is defined as an active or passive state pulse that is shorter in duration than a valid receive symbol at that state A valid receive symbol is at least 34 us in duration Any symbol cap tured on the bus between 8 us and 34 us in duration is considered invalid and is flagged by the J_STAT register as a bus symbol timing error 8 3 2 3 Delay Compensation Because the digital portion of the J1850 protocol is integrated onto the microcontroller and phys ically separated from the transceiver and J1850 bus control over critical timing parameters of various manufacturers remote transceivers is required The delay compensation circuitry ad dresses this requirement by providing the flexibility to compensate for propagation delay and pulse width variations among various transceivers The compensation circuitry synchronizes it self to the leading edge of each input symbol which allows for accurate detection of bus conten tion during bit arbitration The delay compensation is programmable through the J_DLY register Figure 8 18 on page 8 20 8 3 2 4 Symbol Encoding and Decoding The J1850 protocol supports the Huntzicker encoding method which is based on variable pulse width VPW bus modulation VPW modulation is a forced high low symbol transition formatting scheme that tracks the duration between two consecutive transitions and the level of the bus ac tive or passive Figure 8 3 8 6
61. art and end symbols 8 4 1 1 Header The header provides general information on the physical network and the necessary interface re quirements For a complete description of the header refer to the Society of Automotive Engineer ing SAE J1850 specifications revised May 1994 8 4 1 2 CRC Byte The CRC byte calculated through the cyclic redundancy check generator is a checksum value that verifies the accuracy of the data message transmitted onto the bus The CRC byte is appended to all data messages and optionally appended to IFR response messages Upon reception the CRC byte is compared with the value C4H If the values match the transmitted message is valid otherwise it is invalid and an error flag in the J_ STAT register is set 8 4 1 3 Normalization Bit The normalization bit NB found only in IFR messaging defines the start of the IFR message response data The NB is triggered by bit J_CMD 6 and is transmitted after an end of data EOD symbol is detected on the bus The timing format of the NB is assigned by the J_CFG register 8 9 8XC196LX SUPPLEMENT intel J_CFG 7 and considers whether the IFR message response has a CRC byte appended Figure 8 7 depicts the SAE preferred active level state bit format timing for the NB 4 64uS 4 128uS or 0 i 0 NB for IFR without CRC NB for IFR with CRC A5220 01 Figure 8 7 Huntzicker Symbol Definition for the Normalization Bit 8 4 1 4 Start and End M
62. art of Frame SOF 200uS End of Data EOD 280uS End of Frame EOF 3004S In frame Separation IFS 768uS Break Signal BRK A5221 01 Figure 8 8 Definition for Start and End of Frame Symbols Table 8 4 details the symbol timing characteristics supported by the 87C196LB Table 8 4 Huntzicker Symbol Timing Characteristics Name Symbol Bus Level T min T xnom T max Taxmin T max Units did Leavers 0 Passive 60 64 68 34 lt 96 us V 9 Active 122 128 134 96 lt 163 us ene avan 4 Passive 122 128 134 96 lt 163 us V 9 Active 60 64 68 34 lt 96 us Start of Frame SOF Active 193 200 207 163 lt 239 us End of Data EOD Passive 193 200 207 163 lt 239 us End of Frame EOF Passive 271 280 289 239 lt 300 us In frame Separation IFS Passive gt 300 gt 300 us Break BRK Active 768 gt 239 us NOTE Timings are based on the standard bus rate of 10 4 Kb s When operating in 4x mode the bus rate becomes 41 6 Kb s and all symbol timings are one fourth that shown 8 11 8XC196LX SUPPLEMENT intel 8 4 2 In frame Response Messaging There are three types of in frame response IFR message framings type 1 a single byte from a single responder type 2 a single byte from multiple responders and type 3 multiple bytes from a single responder Like the standard message frame the IFR frame is composed of header data and C
63. as priority over a passive 1 state because the passive 0 state comes out of its idle state in a shorter period of time 64 us versus the passive 1 state s idle time of 128 us For example Figure 8 5 illustrates four nodes vying for the bus Node B is the first node to dis continue transmitting when it attempts to transmit a passive 1 symbol onto the bus At the point 8 7 8XC196LX SUPPLEMENT intel of arbitration nodes A C and D are all transmitting an active 0 symbol thus the idle state of the passive 1 symbol is overruled in favor of the driven state of the active 0 symbol Node C is the next node to discontinue transmitting when it attempts to take control of the bus by transmitting an active 1 symbol However nodes A and D maintain control by continuing to drive the bus with an active 0 symbol Finally node D discontinues transmitting when its attempt to hold the bus in an idle state is over ruled by the driven state of the active 1 symbol on node A Thus node A is awarded arbitration The busline signal detected on the bus by the receiver reflects node A s message as this is the only node that did not experience contention o o o o q o o q Node A i i o o 4 Node B Point of Pi Arbitration gr o o o qu 4 Point of Node C A a Arbitration o o o o q o q Node D i i
64. channel 1 Figure 6 2 SSIO 1 Clock SSIO1_CLK Register Continued For transmissions SSIO1_CLK determines whether the SSIO shifts out data bits on rising or fall ing clock edges For receptions SSIO1_CLK determines whether the SSIO samples data bits on the rising or falling clock edges 6 3 intel Event Processor Array intel CHAPTER 7 EVENT PROCESSOR ARRAY The EPA on the 8XC196Lx is functionally identical to that of the 8XC196Jx however the 8XC196Lx has only two capture compare channels without pins instead of four In addition the 83C196LD has no compare only channels 7 1 EPA FUNCTIONAL OVERVIEW Table 7 1 lists the capture compare with and without pins and compare only channels for each device in the 8XC196Lx and 8XC196Kx families Table 7 1 EPA Channels Device Capture Compare Capture Compare Compare only Channels With Pins Channels Without Pins Channels 8XC196LA LB EPA3 0 and EPA9 8 EPA7 6 COMP1 0 8XC196LD EPA3 0 and EPA9 8 EPA7 6 87C196CA 8XC196Jx EPA3 0 and EPA9 8 EPA7 4 COMP1 0 8XC196Kx EPA9 0 COMP1 0 The 8XC196Lx s EPA performs input and output functions associated with two timer counters timer 1 and timer 2 as depicted in Figures 7 1 and 7 2 7 1 8XC196LX SUPPLEMENT intel Timer Counter Unit TIMER1 TIMER2 ure Compare EPA 3 0 _ Channel 0 3 EPA 3 0 Interrupts Capture Compare hannel 6 7 ur
65. corresponding interrupt to be handled by a PTS microcode routine The PTS interrupt vector locations are as follows Bit Mnemonic Interrupt EXTINT EXTINT pin Reserved RI SIO Receive TI SIO Transmit SSIO1 SSIO 1 Transfer SSIOO SSIO 0 Transfer J1850ST LB J1850 Status J1850RX LB J1850 Receive J1850TX LB J1850 Transmit AD LA LB A D Conversion Complete EPAO EPA Capture Compare Channel 0 EPA1 EPA Capture Compare Channel 1 EPA2 EPA Capture Compare Channel 2 EPA3 EPA Capture Compare Channel 3 EPAxii Multiplexed EPA PTS Vector 205CH 205AH 2058H 2056H 2054H 2052H 2050H 204EH 204CH 204AH 2048H 2046H 2044H 2042H 2040H PTS service is not useful for shared interrupts because the PTS cannot readily determine the source of these interrupts i Bit 13 is reserved on the 8XC196Lx devices and bits 6 8 are reserved on the 87C196LA and 83C196LD For compatibility with future devices write zeros to these bits Figure 4 5 PTS Select PTSSEL Register 4 7 8XC196LX SUPPLEMENT intel PTSSRV Address 0006H Reset State 0000H The PTS service PTSSRV register is used by the hardware to indicate that the final PTS interrupt has been serviced by the PTS routine When PTSCOUNT reaches zero hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit which requests the end of PTS interrupt When the end of PTS interrupt is called hardware clears the PTSSRV bit The end of PTS
66. e Compare EPA8 COMPO EPAx Indirect Interrupt Compare only Interrupt Channel 0 Processor Logic Capture Compare EPA9 COMP1 mn Channel 9 Compare only Channel 1 A5269 01 Figure 7 1 EPA Block Diagram 87C196LA LB Only 7 2 tel EVENT PROCESSOR ARRAY Timer Counter Unit TIMER1 TIMER2 ure Compare EPA 3 0 Channel 0 3 EPA 3 0 Interrupts Capture Compare hannel 6 7 ure Compare EPAS Indirect Interrupt Processor Logic Capture Compare EPA9 Channel 9 EPAx Interrupt A5281 01 Figure 7 2 EPA Block Diagram 83C196LD Only 7 3 8XC196LX SUPPLEMENT intel 7 1 1 EPA Mask Registers Figures 7 3 and 7 4 illustrate the EPA mask registers EPA MASK and EPA MASKI for the 8XC196Lx microcontroller family EPA_MASK Address 1FAOH Reset State 0000H The EPA interrupt mask EPA_ MASK register enables or disables masks interrupts associated with the shared EPAx interrupt 15 8 Lx EPA6 EPA7 EPA8 EPA9 OVRO OVR1 7 0 OVR2 OVR3 OVR8 OVR9 Bit Number Function 15 07 Setting a bit enables the corresponding interrupt as a EPAx interrupt source The shared EPAx interrupt is enabled by setting its interrupt enable bit in the interrupt mask register INT_MASK 0 1 Bits 2 5 and 14 15 are reserved on the 8XC196Lx device family For compatibility with future devices write zeros to these bit
67. e four interrupt sources associated with the J1850 protocol This byte register can be directly addressed through windowing You must write to this register before transmitting each message Reading this register clears all bits except BUS_STAT 7 0 IFR_RCV BUS CONT BUS STAT BRK RCV OVR_UNDR MSG_TX MSG_RX J1850BE Bit Bit Number Mnemonic Function 2 MSG_TX Message Transmit Interrupt This bit signals the successful transmission of a message upon detecting the EOD symbol 0 no action 1 message transmitted 1 MSG_RX Message Receive Interrupt This bit signals the successful reception of a message upon detecting the EOD symbol 0 no action 1 message received 0 J1850BE J1850 Bus Error Interrupt This bit is set if one or more of the following conditions occur e the calculated CRC for a received message does not equal C4H an incomplete byte is received on the bus an invalid bus symbol is detected on the bus e a transmission occurs and the feedback through the receiver is not detected within 60 us 8 22 Figure 8 19 J1850 Status J_STAT Register Continued intel 9 Minimum Hardware Considerations intel CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS This chapter discusses the major hardware consideration differences between the 8XC196Lx and the 8XC196Kx The 8XC196Lx has implemented a reset source SFR that reveals the source of the most recent reset re
68. e properties result in a conversion without zero offset full scale or linearity errors Quantizing error is the only error seen in an ideal A D converter Current leakage from an input pin to power or ground The effective series resistance from an analog input pin to the sample capacitor of an A D converter Any member of the set consisting of the positive and negative whole numbers and zero A 16 bit signed variable with values from zi through ST intel internal address interrupt controller interrupt latency interrupt service routine interrupt vector J1850 ISR linearity errors LONG INTEGER LSB LSW GLOSSARY The 24 bit address that the microcontroller generates See also external address The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide Also called the programmable interrupt controller PIC The total delay between the time that an interrupt is generated not acknowledged and the time that the microcontroller begins executing the interrupt service routine or PTS routine Determine the instruction in your code that has the longest execution time and use that execution time in calculating interrupt latency A software routine that you provide to service a standard interrupt request A location in special purpose memory that holds the starting address of an interrupt service routine An integrated communications controller
69. egister 8 15 registers 8 3 8 4 signals 8 3 transmitter register 8 14 Manual contents summary 1 1 1 2 N Noise reducing 5 2 O ONCE mode entering and exiting 10 2 OTPROM address map 11 1 Index 1 P Period t 2 4 Port 0 idle powerdown reset status A 8 A 9 overview 5 1 Port 1 configuring 5 3 idle powerdown reset status A 8 A 9 overview 5 1 Port 2 configuring 5 3 idle powerdown reset status A 8 A 9 overview 5 1 P2 7 reset status 5 2 Port 3 idle powerdown reset status A 8 A 9 internal structure 5 5 overview 5 1 Port 4 idle powerdown reset status A 8 A 9 internal structure 5 5 overview 5 1 Port 5 configuring 5 3 idle powerdown reset status A 8 A 9 overview 5 1 Port 6 configuring 5 3 idle powerdown reset status A 8 A 9 overview 5 1 Ports input buffers 5 2 Powerdown mode pin status A 8 A 9 PTS select register 4 7 PTS service register 4 8 R RD idle powerdown reset status A 8 A 9 Register file and windowing 3 2 description 3 3 Registers EPA_MASK 7 4 EPA_MASKI 7 4 EPA_PEND 7 5 EPA_PENDI 7 5 EPAIPV 7 6 INT_MASK 4 3 Index 2 INT_MASKI 4 4 INT_PEND 4 5 INT_PENDI 4 6 J_CFG 8 18 J_CMD 8 17 J_DLY 8 20 J_RX 8 15 J_STAT 8 21 J_TX 8 14 PTSSEL 4 7 PTSSRV 4 8 RSTSRC 9 1 SSIOO CLK 6 1 SSIO1_CLK 6 2 USFRI 2 6 Reset pin status A 8 A 9 status of CLKOUT P2 7 5 2 Reset source indicator regis
70. eiving Messages vivida ta tol eeen dennen e thy 8 15 8 5 3 IFR MeSSag8S iii AA A 8 16 intel z CONTENTS 8 6 PROGRAMMING THE J1850 CONTROLLER nnen nana naum 8 16 8 6 1 Programming the J1850 Command J_CMD Register nnen 8 16 8 6 2 Programming the J1850 Configuration J_CFG Register nene nenea 8 18 8 6 3 Programming the J1850 Delay Compensation J_DLY Register 8 19 8 6 4 Programming the J1850 Status J_ STAT Register men nenea nare 8 21 CHAPTER 9 MINIMUM HARDWARE CONSIDERATIONS 9 1 IDENTIFYING THE RESET SOURCE nana mana amana 9 1 9 2 DESIGN CONSIDERATIONS FOR 8XC196LA LB AND LD nenea 9 2 CHAPTER 10 SPECIAL OPERATING MODES 10 1 INTERNAL TIMING ondo et apa ea Athen de i Da een 10 1 10 2 ENTERING AND EXITING ONCE MODE nenea nana aaa 10 2 CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY 11 1 SIGNATURE WORD AND PROGRAMMING VOLTAGE VALUES 11 1 11 2 OTPROM ADDRESS MAP iii aa ciate i le a a pt inte baanden 11 1 11 3 SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAP nenea nana 11 2 11 4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP nenea 11 4 APPENDIX A SIGNAL DESCRIPTIONS A 1 FUNCTIONAL GROUPINGS OF SIGNALS nenea nene nana amana A 1 A2 DEFAULT CONDITIONS cout ai dad aid ase Ta aaa A 7 GLOSSARY 8XC196LX SUPPLEMENT intel Figure 2 1 2 2 2 3 2 4 2 5 3 1 4 1 4 2 4 3 4 4 4 5 4 6 5 1 5 2 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 10 8 11 8
71. er RAM 87C196JV Only 1DEOH 6FH 1DCOH 6EH 37H 1DAOH 6DH 1D80H 6CH 36H 1BH 1D60H 6BH 1D40H 6AH 35H 1D20H 69H 1D00H 68H 34H 1AH NOTE Locations 1FE0 1FFFH contain memory mapped SFRs that cannot be accessed through a window Reading these locations through a window returns FFH writing these locations through a window has no effect 3 6 intel Table 3 4 Windows Continued ADDRESS SPACE Base Address WSR Value for 32 byte Window 00E0 00FFH WSR Value for 64 byte Window 00C0 00FFH WSR Value for 128 byte Window 0080 00FFH Register RAM 87C196JV Only Continued 1CEOH 67H 1CCOH 66H 33H 1CAOH 65H 1C80H 64H 32H 19H 1C60H 63H 1C40H 62H 31H 1C20H 61H 1C00H 60H 30H 18H Upper Register File CA JT JV KT 03E0H 5FH 03C0H BEH 2FH 03A0H 5DH 0380H 5CH 2EH 17H 0360H 5BH 0340H 5AH 2DH 0320H 59H 0300H 58H 2CH 16H Upper Register File CA JT JV KT LA LB 02E0H 57H 02C0H 56H 2BH 02A0H 55H 0280H 54H 2AH 15H 0260H 53H 0240H 52H 29H 0220H 51H 0200H 50H 28H 14H Upper Register File CA JR JT JV KR KT LA LB 01E0H 4FH 01C0H 4EH 27H 01A0H 4DH 0180H 4CH 26H 13H NOTE Locations 1FE0 1FFFH contain memory mapped SFRs that cannot be accessed through a window Reading these locations through a window returns FFH writing these locations
72. er direct addressing NOTE The register file must not contain code An attempt to execute an instruction from a location in the register file causes the memory controller to fetch the instruction from external memory 3 2 ADDRESS SPACE Address O3FFH CA JT JV KT General purpose Register RAM O2FFH LA LB O1FFH JR KR 017FH LD Address 0100H OOFFH 03FFH Upper General purpose i i Register RAM ODE Register File g 001A OOFFH Lower Stack Pointer ai Ey Hood Register File CPU SFRs 0000H A5260 01 Figure 3 1 Register File Address Map Table 3 2 Register File Memory Addresses Device and Hex Address Range Description Addressing Modes JV CA JT KT LA LB JR KR LD 1DFF a Indirect indexed or 1C00 Register RAM windowed direct 03FF 03FF 02FF 01FF 017F A Indirect indexed or 0100 0100 otoo otoo ot00 Ypper register file register RAM Windowed direct OOFF OOFF OOFF OOFF OOFF y 7 Direct indirect or 001A oora oora oora oora Lower register file register RAM indexed 0019 0019 0019 0019 0019 f A Direct indirect or 0018 0018 0018 0018 0018 Lower register file stack pointer indexed 0017 0017 0017 0017 0017 A Direct indirect or 0000 0000 0000 0000 0000 Lower register file CPU SFRS indexed 3 3 8XC196LX SUPPLEMENT 3 3 PERIPHERAL SPECIAL FUNCTION REGISTERS Table 3 3 lists the peripheral SFR addresses Hig
73. essage Frame Symbols Five symbols are used to mark the start and end of a message frame and to allow the J1850 bus to properly recognize the interruption of a message transmission or reception Figure 8 8 illus trates the formats and their respective timing The 8 10 following is a description of each symbol start of frame SOF this symbol signals the start of a message frame This is an active level state symbol only and appears once per frame end of data EOD this symbol signals the end of the data transmission This is a passive level state symbol only It appears twice in IFR messaging at the end of the initial request data field and at the end of the IFR data field end of frame EOF this symbol signals the end of a message frame and returns the bus to an idle state This is a passive level state symbol only It appears once per frame in frame separation IFS the timing of this symbol allows for proper synchronization of multiple nodes during back to back transmissions Nodes contending for the bus must comply with one of two conditions before transmitting wait for the IFS minimum timing to expire wait for a rising edge on the bus after the EOF minimum timing has expired break BRK this symbol signals an interruption during a bus transmission At the point of termination all nodes are reset This is an active level state symbol J1850 COMMUNICATIONS CONTROLLER 200uS St
74. fered to allow for reception of a second data byte while the first data byte is being read J_STAT 1F53H J1850 Status Read this byte register to determine the current status of the receive and transmit buffers and the J1850 interrupt sources You can also determine bus status and in frame response messaging status All bits of this register are cleared when read with the exception of the BUS _STAT bit J_ TX 1F50H J1850 Transmitter Program this byte register to transmit data in byte increments to the J1850 bus from the microcontroller CPU This register is buffered to allow for writing of a second data byte while the first data byte is being shifted out 8 3 8XC196LX SUPPLEMENT intel Table 8 2 Control and Status Registers Continued Mnemonic Address Description INT_MASK 0008H Interrupt Mask Bits 6 and 7 in this register enable and disable the J1850 receive and transmit interrupt requests respectively INT_MASK1 0013H Interrupt Mask 1 Bit 0 in this register enables and disables the J1850 bus error interrupt request INT_PEND 0009H Interrupt Pending Bits 6 and 7 in this register when set indicate pending J1850 receive and transmit interrupt requests respectively INT_PEND1 0012H Interrupt Pending 1 Bit 0 in this register when set indicates a pending J1850 bus error interrupt request PTSSEL 0004H PTS Select Bits 6 7 and 8 of this word register select either a P
75. fference between corresponding code transitions of actual characteristics taken from different A D converter channels under the same temperature voltage and frequency conditions This error is caused by differences in DC input leakage and on channel resistance from one multiplexer channel to another A graph of output code versus input voltage the transfer function of an A D converter The integrated module that selects an external memory device during an external bus cycle The 0 value of a bit or the act of giving it a 0 value See also set 1 A set of instructions that perform a specific function a program 2 The digital value output by the A D converter The voltage corresponding to the midpoint between two adjacent code transitions on the A D converter The point at which the A D converter s output code changes from Q to Q 1 The input voltage corre sponding to a code transition is defined as the voltage that is equally likely to produce either of two adjacent codes The voltage change corresponding to the difference between two adjacent code transitions Code width deviations cause differential nonlinearity and nonlin earity errors intel contention crosstalk DC input leakage deassert demultiplexed bus differential nonlinearity doping double word DOUBLE WORD EPA ESD GLOSSARY The detection of conflicting symbols or bits on the bus See off isolation Leak
76. g Mode Address Map Address Range Description Normal Operation Serial Port Programming Mode Internal OTPROM 2000 7FFFH A000 FFFFH External memory 4000 9FFFH Do not address 2400 3FFFH Test ROM and RISM E 2000 23FFH intel A Signal Descriptions APPENDIX A SIGNAL DESCRIPTIONS This appendix provides reference information for the pin functions of the 8XC196Lx microcon trollers A 1 FUNCTIONAL GROUPINGS OF SIGNALS Tables A 1 A 2 and A 3 list the signal assignments for the 8XC196Lx microcontrollers grouped by function A diagram of each microcontroller shows the pin location of each signal A 1 8XC196LX SUPPLEMENT In Table A 1 87C196LA Signals Arranged by Functional Categories tel A 2 Addr amp Data Input Output Cont d Program Control Processor Control Name Pin Name Pin Name Pin Name Pin ADO 22 P2 1 RXD 28 AINC 30 EA 24 AD1 21 P2 2 29 CPVER 31 EXTINT 29 AD2 20 P2 4 30 PACT 32 PLLEN 6 AD3 19 P2 6 31 PALE 28 RESET 23 AD4 18 P2 7 32 PBUS O 22 XTAL1 52 AD5 17 P3 0 22 PBUS 1 21 XTAL2 51 AD6 16 P3 1 21 PBUS 2 20 AD7 15 P3 2 20 PBUS 3 19 Bus Cont amp Status AD8 14 P3 3 19 PBUS 4 18 Name Pin AD9 13 P3 4 18 PBUS 5 17 ADV ALE 2 AD10 12 P3 5 17 PBUS 6 16 CLKOUT 32 AD11 11 P3 6 16 PBUS 7 15 RD 5 AD12 10 P3 7 15 PBUS 8 14 WR WRL 6
77. he value of the PLLEN pin this frequency is routed either through the phase locked loop and multiplier or directly to the divide by two circuit The multiplier circuitry can double the input frequency Fyr 1 before the frequency f reaches the divide by two circuitry The clock generators accept the divided input frequency 2 from the divide by two circuit and produce two nonoverlapping internal timing signals PH1 and PH2 These signals are active when high NOTE This manual uses lowercase f to represent the internal clock frequency For the 87C196LA and LB f is equal to either Fy 74 or 2Fy 74 1 depending on the clock multiplier mode which is controlled by the PLLEN input pin 2 2 intel ARCHITECTURAL OVERVIEW Disable Phase 3 Coin EXTALA XTAL1 Phase locked Oscillator Phase locked Loop Clock Multiplier Disable Oscillator Powerdown Disable Clock Input Powerdown Divide by two Circuit 1 2 Clock Generators Programmable Divider CLK1 0 To reset logic Disable Clocks Idle Powerdown CPU Clocks PH1 PH2 Clock i Failure Detection Peripheral Clocks PH1 PH2 OSC r J CLKOUT Disable Clocks Powerdown A5290 01 Figure 2 2 Clock Circuitry 87C196LA LB Only The rising edges of PH1 and PH2 generate the internal CLKOUT signal Figure 2 3 The clock circuitry routes separate internal clock signals to the CPU and the peripherals
78. hlighted addresses are unique to the 8XC196Lx Table 3 3 8XC196Lx Peripheral SFRs intel Ports 3 4 5 and UPROM SFRs Ports 0 1 2 and 6 SFRs Address High Odd Byte Low Even Byte Address High Odd Byte Low Even Byte 1FFEH P4 PIN P3_PIN 1FDEH Reserved Reserved 1FFCH P4 REG P3_REG 1FDCH Reserved Reserved 1FFAH SLP_CON SLP_CMD 1FDAH Reserved PO_PIN 1FF8H Reserved SLP_STAT 1FD8H Reserved Reserved 1FF6H P5_PIN USFR 1FD6H P6_PIN P1_PIN 1FF4H P5 REG P34_DRV 1FD4H P6 REG P1_REG 1FF2H P5_DIR USFR1 LA LB 1FD2H P6_DIR P1_DIR 1FFOH P5_MODE Reserved 1FDOH P6_ MODE P1_MODE 1FEEH Reserved Reserved 1FCEH P2_PIN Reserved 1FECH Reserved Reserved 1FCCH P2 REG Reserved 1FEAH Reserved Reserved 1FCAH P2_DIR Reserved 1FE8H Reserved Reserved 1FC8H P2_MODE Reserved 1FE6H Reserved Reserved 1FC6H Reserved Reserved 1FE4H Reserved Reserved 1FC4H Reserved Reserved 1FE2H Reserved Reserved 1FC2H Reserved Reserved 1FEOH Reserved Reserved 1FCOH Reserved Reserved Must be addressed as a word intel Table 3 3 8XC196Lx Peripheral SFRs Continued ADDRESS SPACE Must be addressed as a word SIO and SSIO SFRs EPA SFRs Continued Address High
79. ibutor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 1998 Third party brands and names are the property of their respective owners intel z CONTENTS CHAPTER 1 GUIDE TO THIS MANUAL 1 1 MANUAL CONTENTS soens lad co ada aa a ai ta Da a Da da de 1 1 1 2 RELATED DOCUMENTS sie cai eel enc ities r eb Ad 1 2 CHAPTER 2 ARCHITECTURAL OVERVIEW 2 1 MICROCONTROLLER FEATURES nenea nenea 2 1 2 2 BLOCK DIAGRAM iere ea EL enneh ern ae 2 2 2 3 INTERNAL TIMING en ata arda ile 2 2 2 4 EXTERNAL TIMING 2 32 er aa ee p nnn 2 5 2 5 INTERNAL PERIPHERALS a2 ee he en ante 2 6 2 5 1 O E E O O AN a N eS 2 7 2 5 2 Synchronous Serial I O Port nenea nene nenea nana naeaeaeanar ea 2 7 2 5 3 Event Processor Array i cina ceea eek ad 2 7 2 5 4 J1850 Communications Controller mmnn nenea nenea emana 2 7 2 6 DESIGN CONSIDERATIONS men manea emana nana 2 7 CHAPTER 3 ADDRESS SPACE 3 1 ADDRESS PARTITIONS tacks Gch 2a ae at aia shear ereen 3 1 3 2 REGISTER FIEE ithe a eet E E eet ca a a ia i A 3 2 3 3 PERIPHERAL SPECIAL FUNCTION REGISTERS nenea nene nenea 3 4 3 4 WINDOWING lt ciutat ay a a a aaa a ieee 3 6 CHAPTER 4 STANDARD AND PTS INTERRUPTS 4 1 INTERRUPT SOURCES VECT
80. icrocontroller Automotive datasheet 272806 87C196LB 20 MHz CHMOS 16 Bit Microcontroller Automotive datasheet 272807 83C196LD CHMOS 16 Bit Microcontroller Automotive datasheet 272805 1 2 intel Architectural Overview intel CHAPTER 2 ARCHITECTURAL OVERVIEW This chapter describes architectural differences between the 8XC196Lx 87C196LA 87C196LB and 83C196LD and the 8XC196Kx 8XC196Kx 8XC196Jx and 87C196CA microcontroller families Both the 8XC196Lx and the 8XC196Kx are designed for high speed calculations and fast I O and share a common architecture and instruction set with few deviations This chapter provides a high level overview of the deviations between the two families NOTE This supplement describes two product families within the MCS 96 microcontroller family For brevity the name 8XC196Lx is used when the discussion applies to all three Lx controllers Likewise the name 8XC196Kx is used when the discussion applies to all the Kx Jx and CA controllers 2 1 MICROCONTROLLER FEATURES Table 2 1 lists the features of the 8XC196Lx and the 8XC196Kx Table 2 1 Features of the 8XC196Lx and 8XC196Kx Product Famiies Device Busi EPROM EA lis e Seo blica es nbs ROM 1 Ports Pins 87C196LA 52 24K 768 ENEN sas le 1 87C196LB 52 24K 768 EE ERE EAI E 1 83C196LD 52 16K 384 en ike 1 8XC196JV 52 48K 1536 512 41 l e 3 e 1 8XC196KT 68 32K 1024
81. interrupt service routine must set the PTSSEL bit to re enable the PTS channel 15 8 LA EXTINT RI TI SSIO1 SSIOO 7 0 AD EPAO EPA1 EPA2 EPA3 EPAx 15 8 LB EXTINT RI TI SSIO1 SSIOO J1850ST 7 0 J1850RX J1850TX AD EPAO EPA1 EPA2 EPA3 EPAx 15 8 LD EXTINT RI TI SSIO1 SSIOO 7 0 EPAO EPA1 EPA2 EPA3 EPAx Bits Function 14 07 A bit is set by hardware to request an end of PTS interrupt for the corresponding interrupt through its standard interrupt vector The standard interrupt vector locations are as follows Bit Mnemonic Interrupt EXTINT EXTINT pin Reserved RI SIO Receive TI SIO Transmit SSIO1 SSIO 1 Transfer SSIOO SSIO 0 Transfer J1850ST LB J1850 Status J1850RX LB J1850 Receive J1850TX LB J1850 Transmit AD LA LB A D Conversion Complete EPAO EPA Capture Compare Channel 0 EPA1 EPA Capture Compare Channel 1 EPA2 EPA Capture Compare Channel 2 EPA3 EPA Capture Compare Channel 3 EPAxii Multiplexed EPA PTS service is not useful for shared interrupts because the PTS cannot readily determine the source of these interrupts Standard Vector 203CH 203AH 2038H 2036H 2034H 2032H 2030H 202EH 202CH 202AH 2028H 2026H 2024H 2022H 2020H Bit 13 is reserved on the 8XC196Lx devices and bits 6 8 are reserved on the 87C196LA and 83C196LD For compatibility with future devices write zeros to the
82. it diagram and Table 11 3 details the address map for slave program ming of the 87C196LA and LB devices PROGRAMMING THE NONVOLATILE MEMORY XTAL1 RESET P4 7 0 P3 7 0 P2 6 P2 4 P2 2 P2 1 P2 0 VREF P0 7 PMODE 3 P0 6 PMODE 2 P0 5 PMODE 1 P0 4 PMODE O ANGND 87C196LA LB RESET CLOCK PBUS Pullups Required P4 7 P3 0 CPVER AINC PROG PALE PVER Vee 10ko A5277 01 Figure 11 1 Slave Programming Circuit Table 11 3 Slave Programming Mode Address Map Description Address Comments OTPROM 2000 7FFFH OTPROM Cells OFD 0778H OTPROM Cell DED 0758H UPROM Cell DEI 0718H UPROM Cell PCCB 0218H Test EPROM Programming Vec 0072H Read Only Programming Vpp 0073H Read Only Signature word 0070H Read Only These bits program the UPROM cells Once these bits are programmed they cannot be erased and dynamic failure analysis of the device is impossible 8XC196LX SUPPLEMENT intel 11 4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP Figure 11 2 shows the circuit and Table 11 4 details the address map for serial port programming XTAL1 XTAL2 RESET VREF P0 7 PMODE 3 P0 6 PMODE 2 PO 5 PMODE 1 P0 4 PMODE O ANGND EA P2 1 RXD P2 0 TXD 87C196LA LB A5278 01 Figure 11 2 Serial Port Programming Circuit intel PROGRAMMING THE NONVOLATILE MEMORY Table 11 4 Serial Port Programmin
83. k nodes This integrated peripheral supports the 10 4 Kb s VPW variable pulse width medium speed class B in vehicle network protocol It also supports both the standard and in frame response IFR message framing as specified by the Society of Automotive Engineering SAE J1850 revised May 1994 technical standards 2 6 DESIGN CONSIDERATIONS With the exception of a few new multiplexed functions the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers The 8XC196Jx microcontrollers are 52 lead versions of 8XC196Kx microcontrollers For registers that are implemented in both the 8XC196Lx and the 8XC196Jx configure the 8XC196Lx register as you would for the 8XC196Jx unless differences are noted in this supplement 2 7 intel Address Space intel CHAPTER 3 ADDRESS SPACE This chapter describes the differences in the address space of the 8XC196Lx from that of the 8XC196Kx 3 1 ADDRESS PARTITIONS Table 3 1 is an address map of the 8XC196Lx and 8XC196Kx microcontroller family members Table 3 1 Address Map Device and Hex Address Range Addressing Description Modes a l CA JR KR LA LB JT KT JV External device memory N FFFF FFFF FFFF FFFF FFFF FFFF or I O connected to Indirect or A000 6000 6000 8000 A000 E000 addressjdata bus indexed Program memory 9FFF 5FFF 5FFF 7FFF 9FFF DFFF internal nonvolatile or Indirect or 2080
84. mal or handshaking for channel 0 For transmissions PHAS POLS 0 0 low idle state shift on falling edges 0 1 high idle state shift on rising edges 1 0 low idle state shift on rising edges 1 1 high idle state shift on falling edges For receptions PHAS POLS 0 0 low idle state sample on rising edges 0 1 high idle state sample on falling edges 1 0 low idle state sample on falling edges 1 1 high idle state sample on rising edges Figure 6 1 SSIO 0 Clock SSIOO_CLK Register 6 1 8XC196LX SUPPLEMENT intel For transmissions SSIOO_CLK determines whether the SSIO shifts out data bits on rising or fall ing clock edges For receptions SSIOO_CLK determines whether the SSIO samples data bits on rising or falling clock edges 6 2 SSIO 1 CLOCK REGISTER SSIO1 CLK selects the SSIO mode of operation standard duplex or channel select enables the channel select master contention interrupt request and selects the phase and polarity for the serial clock SCI for channels In standard mode use this register to configure the serial clock for channel 1 SSIO1 CLK Address 1FB7H 7 Reset State 00H The SSIO 1 clock SSIO1_CLK register selects the SSIO mode of operation standard duplex or channel select enables the channel select master contention interrupt request and selects the phase and polarity for the serial clock SC1 for channel 1 7 0 CHS
85. mber 272258 or the 8XC196Lx datasheets listed in the Related Documents section of this chapter 1 1 MANUAL CONTENTS This supplement contains several chapters an appendix a glossary and an index This chapter Chapter 1 provides an overview of the supplement This section summarizes the contents of the remaining chapters and appendixes The remainder of this chapter provides references to related documentation Chapter 2 Architectural Overview compares the features of the 8XC196Lx microcon troller family with those of the 8XC196Kx microcontroller family and describes the 87C196LA LB internal clock circuitry Chapter 3 Address Space describes the addressable memory space of the 52 pin 8XC196Lx lists the peripheral special function registers SFRs and provides tables of WSR values for windowing higher memory into the lower register file for direct access Chapter 4 Standard and PTS Interrupts describes the additional interrupts for the 87C196LB s J1850 communications controller peripheral and the SFRs that support those inter rupts Chapter 5 I O Ports describes the port differences and explains the change in the port reset state from a logic 1 to a logic 0 on the 87C196LA LB Chapter 6 Synchronous Serial I O Port describes the enhanced synchronous serial I O SSIO port and explains how to program the two additional peripheral SFRs Chapter 7 Event Processor Array
86. n INT13 203AH 13 PTS13 205AH 28 SIO Receive RI INT12 2038H 12 PTS12 2058H 27 SIO Transmit TI INT11 2036H 11 PTS11 2056H 26 SSIO Channel 1 Transfer SSIO1 INT10 2034H 10 PTS10 2054H 25 SSIO Channel 0 Transfer SSIOO INTO9 2032H 09 PTSO9 2052H 24 J1850 Status LB only J1850ST INTO8 2030H 08 PTS08 2050H 23 Reserved LA LD INTO8 2030H 08 PTS08 2050H 23 Unimplemented Opcode 2012H Software TRAP Instruction 2010H J1850 Receive LB only J1850RX INTO7 200EH 07 PTSO7 204EH 22 Reserved LA LD INTO7 200EH 07 PTS07 204EH 22 J1850 Transmit LB only J1850TX INTO6 200CH 06 PTS06 204CH 21 Reserved LA LD INTO6 200CH 06 PTS06 204CH 21 A D Conv Complete LA LB AD DONE INTO5 200AH 05 PTSO5 204AH 20 Reserved LD INTO5 200AH 05 PTS05 204AH 20 EPA Capture Compare 0 EPAO INTO4 2008H 04 PTS04 2048H 19 EPA Capture Compare 1 EPA1 INTO3 2006H 03 PTS03 2046H 18 EPA Capture Compare 2 EPA2 INTO2 2004H 02 PTSO2 2044H 17 EPA Capture Compare 3 EPA3 INTO1 2002H 01 PTSO1 2042H 16 EPA Capture Compare 6 9 EPAx tt INTOO 2000H 00 PTSOO 2040H 15 EPA 0 3 8 9 Overrun EPA Compare 0 1 f Timer 1 Overflow amp Timer 2 Overflow The NMI pin is not bonded out on the 8XC196Lx To protect against glitches create a dummy interrupt service routine that contains a RET instruction ii These interrupts are individually prioritized in the EPAIPV register Read the EPA pending registers EPA_PEND and EPA_PEND1 t
87. n nenoee eee vene nennserenenseneennenennservenseneennnvenense 7 6 J1850 Controller Signals 4 caiete e an aaa at aa a ai ai 8 3 Control and Status Registers ieiunare a a A E E 8 3 Relationships Between Input Frequency PLL and Prescaler Bits 8 6 Huntzicker Symbol Timing Characteristics men nenea nene nana na 8 11 Signature Word and Programming Voltage Values nennen nana 11 1 87C196LA LB OTPROM Address Map mean nenea nana na 11 2 Slave Programming Mode Address Map nennen ennen nenea nana nana 11 3 Serial Port Programming Mode Address Map nenea nene nenea 11 5 87C196LA Signals Arranged by Functional Categories mean nenea A 2 87C196LB Signals Arranged by Functional Categories nnen eenen ennen A 4 83C196LD Signals Arranged by Functional Categories nenea nenea A 6 Definition of Status Symbols ennen neneneeernenensvennerenseennenenneneeenenenvene A 7 87C196LA LB Default Signal Conditions unseren nenea A 8 83C196LD Default Signal Conditions nenea nene neam nana A 9 intel Guide to This Manual intel CHAPTER 1 GUIDE TO THIS MANUAL This document is a supplement to the 8XC196Kx 8XC196Jx 87C196CA Microcontroller Family User s Manual It describes the differences between the 8XC196Lx and the 8XC196Kx family of microcontrollers For information not found in this supplement please consult the 8XC196Kx 8XC196Jx 87C196CA Microcontroller Family User s Manual order nu
88. n the bus and that the subsequent byte written to the J1850 transmitter J_TX register is an in frame response IFR 0 standard messaging 1 next byte written to J_TX is an IFR 5 IGNORE Ignore Incoming Message This bit instructs the bus to ignore the incoming message until an EOF symbol is detected The bit is cleared after an EOF symbol is detected 0 normal operation 1 ignore incoming message 4 ABORT Abort Transmission This bit aborts any transmission in progress and flushes the transmit buffer JTX_BUF To prevent another node from mistakenly assuming that the last byte was a CRC byte two extra 1 s are appended 0 normal operation 1 abort transmission in progress 3 0 MSG3 0 Message These four bits specify the number of bytes to be transmitted in the next message frame This number includes the header but not the CRC byte In normal messaging the maximum number of bytes you can transmit in a message frame is eleven MSG3 0 Operation Purpose FH Termination byte Terminate block transmission EH Block transmission Transmit unspecified number of bytes DH Reserved En CH Reserved B 0H Normal messaging Transmit specified number of bytes Figure 8 16 J1850 Command J_CMD Register 8 17 8XC196LX SUPPLEMENT intel 8 6 2 Programming the J1850 Configuration J_CFG Register The J1850 configuration register Figure 8 17 selects the proper oscillator prescaler initiates a t
89. nnel matching off isolation and Vcc rejection errors Universal asynchronous receiver and transmitter A part of the serial I O port Glossary 11 8XC196LX SUPPLEMENT Vee rejection VPW wait state watchdog timer WDT word WORD zero extension zero offset error Glossary 12 intel The property of an A D converter that causes it to ignore reject changes in V cc so that the actual characteristic is unaffected by those changes The effectiveness of Vcc rejection is measured by the ratio of the change in Vec to the change in the actual characteristic Variable pulse width A forced high low symbol transition formatting scheme that tracks the duration between two consecutive transitions and the level of the bus active or passive Time spent waiting for an operation to take place Wait states are added to external bus cycles to allow a slow memory device to respond to a request from the microcontroller An internal timer that resets the microcontroller if software fails to respond before the timer overflows Watchdog timer An internal timer that resets the microcontroller if software fails to respond before the timer overflows Any 16 bit unit of data An unsigned 16 bit variable with values from 0 through el A method for converting data to a larger format by filling the upper bit positions with zeros An ideal A D converter s first code transition occurs when the input voltage is 0 5 LSB
90. o determine which source caused the interrupt ttt 87C196LA LB only The 83C196LD has no EPA compare only channels 4 2 INTERRUPT REGISTERS This section describes the changes in the interrupt register bit definitions for the 8XC196Lx fam ily 4 2 intel STANDARD AND PTS INTERRUPTS 4 2 1 Interrupt Mask Registers Figures 4 1 and 4 2 illustrate the interrupt mask registers for the 8XC196Lx microcontrollers INT_MASK Address 0008H Reset State 00H The interrupt mask INT_MASK register enables or disables masks individual interrupt requests The El and DI instructions enable and disable servicing of all maskable interrupts INT_MASK is the low byte of the processor status word PSW PUSHF or PUSHA saves the contents of this register onto the stack and then clears this register Interrupt calls cannot occur immediately following a push instruction POPF or POPA restores it 7 0 LA AD EPAO EPA1 EPA2 EPA3 EPAx 7 0 LB J1850RX J1850TX AD EPAO EPA1 EPA2 EPA3 EPAx 7 0 LD EPAO EPA1 EPA2 EPA3 EPAx Bit gt Number Function 7 04 Setting a bit enables the corresponding interrupt Bit Mnemonic Interrupt Description J1850RX J1850 Receive LB only J1850TX J1850 Transmit LB only AD A D Conversion Complete LA LB EPAO EPA Capture Compare Channel 0 EPA1 EPA Capture Compare Channel 1 EPA2 EPA Capture Compare Channel 2 EPA3 EPA Capture Compare Channel
91. ols remaining in its message frame Remaining nodes vying for the bus will continue to send their symbols until the next instance of contention is detected or arbitration is awarded This process continues until a complete message frame from one node has been transmitted For details on this arbitration scheme refer to the Bit Arbitration Example on page 8 7 8 3 1 4 Error Detection The J1850 controller s error detection logic monitors the bus for four error conditions and sets the J1850BE interrupt pending bit in the J_STAT register if an error occurs The following list describes each error type e CRC error the calculated CRC checksum received on incoming messages has a value other than C4H the expected value for all received message frames bus symbol timing error the symbol stream on the J1850 bus contains an invalid symbol An invalid symbol is any signal that is between 8 us and 34 us in duration e incomplete byte error an EOD EOF symbol occurred but was not on a byte boundary the number of bits recieved was not a multiple of eight no echo the message is transmitted however the transmission s echo back through the feedback loop to the receiver has not been detected within the allowable 60 us window 8 3 2 Symbol Synchronization and Timing Circuitry The symbol synchronization and timing SST circuitry consists of a clock prescaler digital filter delay compensation circuitry and synchronization
92. our system meets the V specification to prevent inadvertent entry into ONCE mode 10 3 intel 11 Programming the Nonvolatile Memory intel CHAPTER 11 PROGRAMMING THE NONVOLATILE MEMORY The 87C196LA and LB microcontrollers contain 24 Kbytes 2000 7FFFH of one time pro grammable read only memory OTPROM OTPROM is similar to EPROM but it comes in a windowless package and cannot be erased You have the option of programming the OTPROM yourself or having the factory program it as a quick turn ROM product the latter option may not be available for all devices NOTE In this supplement OTPROM refers to the device s internal read only memory whether it is EPROM or OTPROM and EPROM refers specifically to EPROM devices The 87C196LA and LB programming signals registers and procedures are the same as those of the 87C196Kx This chapter describes the differences in memory mapping and programming cir cuits for the 87C196LA and LB 11 1 SIGNATURE WORD AND PROGRAMMING VOLTAGE VALUES The 8XC196Lx s programming voltage values are the same as those of the 8XC196Kx however the signature word value differs Table 11 1 lists the signature word and programming voltage values Table 11 1 Signature Word and Programming Voltage Values Signature Word Programming Vcc Programming Vpp Device Location Value Location Value Location Value 87C196LA 0070H 871BH 0072H 40H 0073H OAOH 87C196LB 0070H 871BH 0072H
93. peripheral that supports the 10 4 Kb s variable pulse width VPW medium speed class B in vehicle network protocol See interrupt service routine See differential nonlinearity and nonlinearity A 32 bit signed variable with values from through Def 1 Least significant bit of a byte or least significant byte of a word 2 In an A D converter the reference voltage divided by 2 where n is the number of bits to be converted For a 10 bit converter with a reference voltage of 5 12 volts one LSB is equal to 5 0 millivolts 5 12 210 Least significant word of a double word or quad word Glossary 5 8XC196LX SUPPLEMENT maskable interrupts monotonic MSB MSW multiplexed bus n channel FET n type material near constants near data no missing codes Glossary 6 intel All interrupts except stack overflow unimplemented opcode and software trap Maskable interrupts can be disabled masked by the individual mask bits in the interrupt mask registers and their servicing can be disabled by the DI disable interrupt service instruction Each maskable interrupt can be assigned to the PTS for processing The property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value and that decreasing input voltages produce adjacent codes of decreasing value In other words a converter is monotonic if every code change represents an
94. pling occurs during PH1 while CLKOUT is low and resolves the value high or low of the pin before it is presented to the internal bus If the pin value changes during the sample time the new value may or may not be recorded during the read RESET is a level sensitive input EXTINT is normally a sampled input however the powerdown circuitry uses EXTINT as a level sensitive input during powerdown mode Successive approximation register A component of the A D converter The 1 value of a bit or the act of giving it a 1 value See also clear Special function register An 8 bit signed variable with values from zo through goten A method for converting data to a larger format by filling the upper bit positions with the value of the sign This conversion preserves the positive or negative value of signed integers Current flowing into a device to ground Always a positive value Current flowing out of a device from Vcc Always a negative value Stack pointer Any of the three nonmaskable interrupts unimple mented opcode software trap or NMI intel special purpose memory standard interrupt state time or state successive approximation temperature coefficient temperature drift terminal based characteristic transfer function transfer function errors UART GLOSSARY A partition of memory used for storing the interrupt vectors PTS vectors chip configuration bytes and several
95. quest 9 1 IDENTIFYING THE RESET SOURCE The reset source RSTSRC register indicates the source of the last reset that the microcontroller encountered Figure 9 1 If more than one reset occurs at the same time all of the corresponding RSTSRC bits are set Reading this SFR clears all the register bits RSTSRC Address 1F92H Reset State XXH 1 The reset source RSTSRC register indicates the source s of the last reset that the microcontroller encountered 7 0 CFDRST WDTRST SFWRST EXTRST Hanba ee Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 CFDRST Clock Failure Detection Reset When set this bit indicates that a failed clock caused the last reset 2 WDTRST Watchdog Timer Reset When set this bit indicates that the watchdog timer caused the last reset 1 SFWRST Software Reset When set this bit indicates that either the RST instruction or the IDLPD instruction used with an illegal key caused the last reset 0 EXTRST External Reset When set this bit indicates that the RESET pin being asserted caused the last reset NOTE 1 The State of the RSTSRC register is inderterminate on a Vcc power up condition All other reset states will have the corresponding reset event bit set in the register Figure 9 1 Reset Source RSTSRC Register 9 1 8XC196LX SUPPLEMENT intel 9 2 DESIGN CONSIDERATI
96. ransmission break for debugging invokes clock quadrupling operation and selects the normal ization bit format J CFG Address 1F54H Zi Reset State 00H The J1850 configuration J_CFG register selects the proper oscilator prescaler initiates transmission break for debug invokes clock quadrupling operation and selects the normalizartion bit format This byte register can be directly addressed through windowing All J1850 bus activity is ignored until you first write to this register 7 0 NBF IFR3 4XM TXBRK RXPOL PRE1 PREO Bit Bit Number Mnemonic Funcion 7 NBF Normalization Bit Format This bit specifies which normalization bit NB format is to be used IFR with CRC Byte IFR without CRC Byte 0 active long NB 0 active short NB 1 active short NB 1 active long NB 6 IFR3 Type 3 IFR Messaging This bit selects type 3 IFR messaging which supports the in frame transfer of an unspecified number of data bytes 0 normal operation 1 type 3 IFR messaging 5 4XM Oscillator Quadruple 4x Mode This bit allows the J1850 peripheral to operate at four times the normal bit transfer rate 41 6 Kb s versus 10 4 Kb s 0 normal operation 1 4x mode operation 4 TXBRK Transmission Break This bit will terminate any transmission in progress by writing a break BRK symbol to the bus 0 normal operation 1 transmit BRK symbol onto bus 3 RXPOL Receive Polarity This bit changes the polari
97. registers only once per initializa tion sequence After initialization you must first program the command register followed by either the receive or transmit register and then the status register 8 6 1 Programming the J1850 Command J_CMD Register The J1850 command register Figure 8 16 determines the messaging type specifies the number of bytes to be transmitted in the next message frame and updates the status of the message trans mission in progress 8 16 intel J1850 COMMUNICATIONS CONTROLLER J CMD Address 1F51H z Reset State 00H The J1850 command J_CMD register determines the messaging type specifies the number of bytes to be transmitted in the next message frame and updates the status of the message transmission in progress This byte register can be directly addressed through windowing You must write to this register prior to transmitting every message 7 0 AUTO IFR IGNORE ABORT MSG3 MSG2 MSG1 MSGO Bit Bit Function Number Mnemonic unctio 7 AUTO Automatic Transmit Retry This bit when arbitration is lost on the first byte of your message prompts the transmitter to automatically retry until the byte is successfully transmitted Automatic retry applies only to the first byte 0 normal operation 1 enable automatic retry 6 IFR In frame Response Indicator This bit signals that a normalization bit NB is to be sent after an end of data symbol is detected o
98. riting to the port mode register turns off the weak pull downs To ensure that the ports are initialized correctly follow this suggested initialization sequence 1 Write to Px_DIR to configure the individual pins Clearing a bit configures a pin as a complementary output Setting a bit configures a pin as a high impedance input or open drain output 2 Write to Px_MODE to select either I O or special function mode Writing to Px_ MODE regardless of the value written turns off the weak pull downs Even if the entire port is to be used as I O its default configuration after reset you must write to Px_MODE to ensure that the weak pull downs are turned off 3 Write to Px_REG For complementary output configurations In I O mode write the data that is to be driven by the pins to the corresponding Px_ REG bits In special function mode the value is immaterial because the on chip peripheral or system function controls the pin However you must still write to Px_REG to initialize the pin For high impedance input or open drain output configurations In I O mode write to Px_REG to either float the pin making it available as a high impedance input or pull it low Setting the corresponding Px_REG bit floats the pin clearing the corresponding Px_REG bit pulls the pin low In special function mode if the on chip peripheral uses the pin as an input signal you must set the corresponding Px_REG bit so that the pin can be driven externally If
99. rocontroller family EPAIPV Address 1FA8H Reset State 00H When an EPAx interrupt occurs the EPA interrupt priority vector EPAIPV register contains a number that identifies the highest priority active multiplexed interrupt source see Table 7 2 EPAIPV allows software to branch via the TIJMP instruction to the correct interrupt service routine when EPAx is activated Reading EPAIPV clears the EPA pending bit for the interrupt associated with the value in EPAIPV When all the EPA pending bits are cleared the EPAx pending bit is also cleared 7 0 PV4 PV3 PV2 PV1 PVO Bit Bit A Number Mnemonic Function 5 7 Reserved for compatibility with future devices write zeros to these bits 4 0 PV4 0 Priority Vector These bits contain a number from 01H to 14H corresponding to the highest priority active interrupt source This value when used with the TIJMP instruction allows software to branch to the correct interrupt service routine Figure 7 7 EPA Interrupt Priority Vector Register EPAIPV Table 7 2 EPA Interrupt Priority Vectors Value Interrupt Value Interrupt Value Interrupt 14H ODH OVR1 06H OVR8 13H OCH OVR2 05H OVR9 12H EPA6 OBH OVR3 04H COMPO 11H EPA7 OAH 03H COMP1 10H EPA8 09H 02H OVRTM1 OFH EPA9 08H 01H OVRTM2 OEH OVRO 07H 00H None t 87C196LA LB only reserved
100. rrent ports 3 and 4 can source and sink During reset the active low level of RESET turns off Q1 and Q2 and turns on transistor Q4 which weakly holds the pin low Resistor R1 provides ESD protection for the pin During normal operation the device controls the port through BUS CONTROL SELECT an internal control sig nal When the device needs to access external memory it clears BUS CONTROL SELECT selecting ADDRESS DATA as the input to the multiplexer ADDRESS DATA then drives Q1 and Q2 as complementary outputs When external memory access is not required the device sets BUS CONTROL SELECT select ing Px_REG as the input to the multiplexer Px_REG then drives Q1 and Q2 If P34_ DRV is set Q1 and Q2 are driven as complementary outputs If P34 DRV is cleared Q1 is disabled and Q2 is driven as an open drain output requiring an external pull up resistor With the open drain con figuration BUS CONTROL SELECT set and P34_DRV cleared and Px_REG set the pin can be used as an input The signal on the pin is latched in the Px_PIN register The pins can be read making it easy to see which pins are driven low by the device and which are driven high by ex ternal drivers while in open drain mode 5 5 8XC196LX SUPPLEMENT Internal Bus Px REG Address Data Bus Control Select 0 Address Data 1 V0 RESET Sample 1500 to 2000 R1 Latch Buffer Read Port RESET I O Pin A5264 01 5 6 Figure 5 2 Ports
101. s Figure 7 3 EPA Interrupt Mask EPA_MASK Register EPA_MASK1 Address 1FA4H Reset State 00H The EPA interrupt mask 1 EPA_MASK1 register enables or disables masks interrupts associated with the multiplexed EPAx interrupt 7 0 COMPO COMPIi OVRTM1 OVRTM2 Bit Number Function 7 4 Reserved for compatibility with future devices write zeros to these bits 3 07 Setting a bit enables the corresponding interrupt as a multiplexed EPAx interrupt source The multiplexed EPAx interrupt is enabled by setting its interrupt enable bit in the interrupt mask register INT_MASK 0 1 i 87C196LA LB only reserved on 83C196LD Figure 7 4 EPA Interrupt Mask 1 EPA_MASK1 Register 7 4 intel EVENT PROCESSOR ARRAY 7 1 2 EPA Pending Registers Figures 7 5 and 7 6 illustrate the EPA pending registers EPA_PEND and EPA _PENDI for the 8XC196Lx microcontroller family EPA _PEND Address 1FA2H Reset State 0000H When hardware detects a pending EPA6 9 or OVRO 3 8 9 interrupt request it sets the corresponding bit in the EPA interrupt pending register EPA_PEND or EPA_PEND1 The EPAIPV register contains a number that identifies the highest priority active shared interrupt source When EPAIPV is read the EPA interrupt pending bit associated with the EPAIPV priority value is cleared 15 8 Lx EPA6 EP
102. se bits 4 8 Figure 4 6 PTS Service PTSSRV Register intel VO Ports intel CHAPTER 5 I O PORTS The I O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx However on the 87C196LA and LB the reset state level of all 41 general purpose I O pins has changed from a weak logic 1 wk1 to a weak logic 0 wk0 This chapter outlines the differences between the 87C196LA LB and the 8XC196Kx controllers 5 1 I O PORTS OVERVIEW Table 5 1 provides an overview of the 8XC196Lx and 8XC196Kx I O ports Table 5 1 Microcontroller Ports Pon Pins i ea Port 0 ion Jx Lx Standard Input only nai bc d on LD Port 1 2 En Jx Lx Standard aa ntary EPA and timers Port 2 A CK Jx Lx Standard an ntary mert ol clock Port 3 8 Memory mapped pila ini Address data bus Port 4 8 Memory mapped ar ntary Address data bus Port 5 E CA Jx Lx Memory mapped et Bus control slave port Port 6 5 io ax Log Standard en EPA SSIO 5 2 INTERNAL STRUCTURE FOR PORTS 1 2 5 AND 6 BIDIRECTIONAL PORTS Figure 5 1 shows the logic for driving the output transistors Q1 and Q2 Consult the datasheet for specifications on the amount of current that each port can source or sink In VO mode selected by clearing a port mode register bit the port data output and the port di rection registers are input to the multiplexers These signals combine to drive the gates of Q1 and Q2
103. set this bit Write this value To this location CLKO 0001H 0768H CLK1 0002H 0728H 2 5 INTERNAL PERIPHERALS The internal peripheral modules provide special functions for a variety of applications This sec tion provides a brief description of the peripherals that differ between the 8XC196Lx and the 8XC196Kx families 2 6 intel ARCHITECTURAL OVERVIEW 2 5 1 I O Ports The I O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx However on the 87C196LA and LB the reset state level of all 41 general purpose I O pins has changed from a weak logic 1 wk1 to a weak logic 0 wk0 2 5 2 Synchronous Serial I O Port The synchronous serial I O SSIO port on the 8XC196Lx has been enhanced implementing two new special function registers SSIOO_CLK and SSIO1_CLK that allow you to select the oper ating mode and configure the phase and polarity of the serial clock signals 2 5 3 Event Processor Array The 8XC196Lx s event processor array EPA is functionally identical to that of the 8XC196Jx except that it has only two EPA capture compare channels without pins instead of four In addi tion the LD has no compare only channels 2 5 4 J1850 Communications Controller The 87C196LB microcontroller has a peripheral not found on the 8XC196Kx microcontrollers or any other Lx microcontroller the J1850 peripheral The J1850 communications controller man ages communications between multiple networ
104. so that the output is high low or high impedance In special function mode selected by setting a port mode register bit SFDIR and SFDATA are input to the multiplexers These signals combine to drive the gates of Q1 and Q2 so that the output is high low or high impedance Special function output signals clear SFDIR special function 5 1 8XC196LX SUPPLEMENT intel input signals set SFDIR Even if a pin is to be used in special function mode you must still ini tialize the pin as an input or output by writing to the port direction register Resistor R1 provides ESD protection for the pin Input signals are buffered The standard ports use Schmitt triggered buffers for improved noise immunity Port 5 uses a standard input buffer because of the high speeds required for bus control functions The signals are latched into the port pin register sample latch and output onto the internal bus when the port pin register is read The falling edge of RESET turns on transistor Q3 which remains on for about 300 ns causing the pin to change rapidly to its reset state The active low level of RESET turns on transistor Q4 which weakly holds the pin low Q4 remains on weakly holding the pin low until your software writes to the port mode register NOTE P2 7 is an exception After reset P2 7 carries the CLKOUT signal half the crystal input frequency rather than being held low When CLKOUT is selected it is always a complementary output 5 2
105. tch protection only T O ports The following port pins do not exist in the 8XC196Lx PO 0 PO 1 P1 4 P1 7 P2 3 and P2 5 P5 1 and P5 4 P5 7 P6 2 and P6 3 Software can still read and write the associated Px_REG Px_MODE and Px_DIR registers Configure the registers for the omitted pins as follows Clear the corresponding Px_DIR bits Configures pins as complementary outputs Clear the corresponding Px_MODE bits Selects I O port function Write either 0 or 1 to the corresponding Px_REG bits Effectively ties signals low or high Do not use the bits associated with the omitted port pins for conditional branch instructions Treat these bits as reserved Auto programming During auto programming the 8XC196Lx supports only a 16 bit zero wait state bus configuration intel 10 Special Operating Modes intel CHAPTER 10 SPECIAL OPERATING MODES The 8XC196Lx s idle and powerdown modes are the same as those of the 8XC196Kx However the clock circuitry has changed and the on circuit emulation ONCE special purpose mode op eration has changed slightly because of the new reset state pin levels that have been implemented 10 1 INTERNAL TIMING The 87C196LA and LB clock circuitry Figure 10 1 implements a phase locked loop and clock multiplier circuitry which can substantially increase the CPU clock rate while using a lower fre quency input clock 10 1 8XC196LX SUPPLEMENT intel
106. ter 9 1 RESET idle powerdown reset status A 8 A 9 S Serial port programming mode 11 5 Signals default conditions A 8 A 9 status symbols defined A 7 State time defined 2 4 Symbols signal status A 7 Synchronous serial port 0 clock register 6 1 Synchronous serial port 1 clock register 6 2 U Unerasable PROM 1 register 2 6 W Windows and address mapped SFRs 3 6 locations that cannot be windowed 3 6 WSR values and direct addresses 3 6 WR idle powerdown reset status A 8 A 9
107. the on chip peripheral uses the pin as an output signal the value of the corresponding Px_REG bit is immaterial because the on chip peripheral or system function controls the pin However you must still write to Px_REG to initialize the pin 5 2 2 Special Bidirectional Port Considerations This section outlines special consideration for using the pins of ports 1 2 5 and 6 1 After reset your software must configure the device to match the external system This accomplished by writing appropriate configuration data into Px_ MODE Writing to Px_MODE not only configures the pins but also turns off the transistor that weakly holds the pins low For this reason even if your port is to be used as it is configured at reset you should still write data into Px_ MODE 2 P2 6 TXJ1850 is the enable pin for ONCE mode Because a high input during reset can cause the device to enter ONCE mode or a reserved test mode caution must be exercised 5 4 intel z I O PORTS in using this pin Be certain that your system meets the V specifications during reset to prevent inadvertent entry into ONCE mode or a test mode 3 Following reset P2 7 CLKOUT carries the strongly driven CLKOUT signal It is not held low When P2 7 CLKOUT is configured as CLKOUT it is always a complementary output 5 3 INTERNAL STRUCTURE FOR PORTS 3 AND 4 ADDRESS DATA BUS Figure 5 2 shows the logic of ports 3 and 4 Consult the datasheet for specifications on the amount of cu
108. tic and logical operations The act of making a signal active enabled The polarity high or low is defined by the signal name Active low signals are designated by a pound symbol suffix active high signals have no suffix To assert RD is to drive it low to assert ALE is to drive it high A decrease in amplitude voltage decay A binary digit A single bit operand that can take on the Boolean values true and false The process of settling conflicts that occur when multiple nodes attempt to transmit a bit or symbol across a single bus at the same time The property of a multiplexer which guarantees that a previously selected channel is deselected before a new channel is selected That is break before make ensures that the A D converter will not short inputs together Glossary 1 8XC196LX SUPPLEMENT byte BYTE CCBs CCRs channel to channel matching error characteristic chip select unit clear code code center code transition code width Glossary 2 intel Any 8 bit unit of data An unsigned 8 bit variable with values from 0 through 28 1 Chip configuration bytes The chip configuration registers CCRs are loaded with the contents of the CCBs after a reset Chip configuration registers Registers that define the environment in which the microcontroller will be operating The chip configuration registers are loaded with the contents of the CCBs after a reset The di
109. to provide flexibil ity in power management It also outputs the CLKOUT signal on the CLKOUT pin Because of the complex logic in the clock circuitry the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal This delay varies with temperature and voltage 2 3 8XC196LX SUPPLEMENT intel nt an tS ee 1 State Time lk 1 State Time gt PH1 EE EA CLKOUT A AN Phase 1 Phase 2 Phase 1 Phase 2 A0805 01 Figure 2 3 Internal Clock Phases Assumes PLL is Bypassed The combined period of phase and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state Table 2 2 lists state time durations at various frequencies Table 2 2 State Times at Various Frequencies f Frequency Input to the State Time Divide by two Circuit 8 MHz 250 ns 12 MHz 167 ns 16 MHz 125 ns 20 MHz 100 ns The following formulas calculate the frequency of PH1 and PH2 the duration of a state time and the duration of a clock period t PH1 in MHz PH2 State Time in us 7 Because the device can operate at many frequencies this manual defines time requirements such as instruction execution times in terms of state times rather than specific measurements Datasheets list AC characteristics in terms of clock periods t sometimes called Tosc Figure 2 4 illustrates the timing relationships between the input frequency Ey 1 the
110. ture Compare Channel 1 EPA2 EPA Capture Compare Channel 2 EPA3 EPA Capture Compare Channel 3 EPAx t Shared EPA Interrupt EPA 6 9 capture compare channel events EPA 0 1 compare channel eventsttt EPA 0 3 and 8 9 capture compare overruns and timer overflows can generate this shared interrupt Write the EPA mask registersto enable the interrupt sources read the EPA pending registers to determine which source caused the interrupt ttt 87C196LA LB only i Bits 6 7 are reserved on the 87C196LA and bits 5 7 are reserved on the 83C196LD For compatibility with future devices write zeros to these bits Figure 4 3 Interrupt Pending INT _PEND Register 4 5 8XC196LX SUPPLEMENT intel INT _PEND1 Address Reset State When hardware detects an interrupt request it sets the corresponding bit in the interrupt pending INT_PEND or INT_PEND1 registers When the vector is taken the hardware clears the pending bit Software can generate an interrupt by setting the corresponding interrupt pending bit 0012H 00H when processing transfers to the corresponding interrupt vector Interrupt Description Nonmaskable Interrupt Bit Mnemonic NMI EXTINT Reserved J1850ST EXTINT Pin SIO Receive SIO Transmit SSIO 1 Transfer SSIO 0 Transfer J1850 Status LB only 7 0 LB NMI EXTINT RI TI SSIO1 SSIOO J1850ST 7 0 LA LD NMI EXTINT RI TI SSIO1 SSI
111. ty of the receive symbol 0 normal operation Rx input inverted 1 receive polarity enabled Rx input non inverted Figure 8 17 J1850 Configuration J_CFG Register 8 18 intel J1850 COMMUNICATIONS CONTROLLER J_CFG Address 1F54H Reset State 00H The J1850 configuration J_CFG register selects the proper oscilator prescaler initiates transmission break for debug invokes clock quadrupling operation and selects the normalizartion bit format This byte register can be directly addressed through windowing All J1850 bus activity is ignored until you first write to this register 7 0 NBF IFR3 4XM TXBRK RXPOL PRE1 PREO Bit Bit Number Mnemonic Function 2 Reserved for compatibility with future devices write zero to this bit 1 0 PRE1 0 J1850 Oscillator Prescaler These bits ensure proper operation of the J1850 peripheral at the supported input frequencies Fyrau4 PRE1 PREO Frai 0 0 8 MHz 0 1 12 MHz 1 0 16 MHz 1 1 20 MHz Figure 8 17 J1850 Configuration J_CFG Register Continued 8 6 3 Programming the J1850 Delay Compensation J_DLY Register The J1850 delay compensation register Figure 8 18 allows you to program the necessary delay time through the external transceiver to compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration 8 19 8XC196LX SUPPLEMENT

8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User`s

Contents

Download Pdf Manuals

Related Search

Related Contents