CAEN V1720 Registers Description
Contents
1. This register bits 0 7 enable the channels to generate a local trigger as the digitised signal exceeds the Vth threshold BitO enables ChO to generate the trigger bit enables Ch1 to generate the trigger and so on Bits 26 24 allows to set minimum number of channels that must be over threshold beyond the triggering channel in order to actually generate the local trigger signal for example if bit 7 0 FF all channels enabled and Local trigger coincidence level 1 whenever one channel exceeds the threshold the trigger will be generated only if at least another channel is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled via bit 7 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 2 20 Filename Number of pages Page 1720 REGISTERS 22 16 CAEN Q Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 22 Front Panel Trigger Out Enable Mask 0x8110 r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 8 reserved 7 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 Channel 52. Bit Function 15 0 DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 1V range When Channel n Status bit 2 is set to 0 DC offset is updated see 2 7 2 11 Channel n ADC Configuration 0x1n9C r w Bit Function 15 0 T B D This register allows to pilot the relevant ADC signals See the LTC2242 12 12 Bit 250Msps ADC data sheet for details Filename Number of pages Page V1720 REGISTERS 22 11 CAEN Q Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 12 Channel Configuration 0x8000 r w Bit Function Allows to select Zero Suppression algorithm 0000 no zero suppression default 0010 zero length encoding ZLE 0011 full suppression based on the amplitude ZS AMP 18 12 reserved 11 0 Pack2 5 disabled 1 Pack2 5 enabled 10 7 reserved 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold 19 16 6 allows to generate local trigger either on channel over or under threshold see 2 3 and 2 6 4 0 Memory Random Access 1 Memory Sequential Access 0 Test Pattern Generation Disabled 1 Test Pattern Generation Enabled 0 Trigger Overlapping Not Enabled 1 1 Trigger Overlapping Enabled Allows to handle trigger overlap 0 reserved This register allows to perform settings wh
3. 4 0 GEO VME64X versions this register can be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field 2 36 MCST Base Address and Control OXEFOC r w Bit Function Allows to set up the board for daisy chaining 00 disabled board 9 8 01 last board 10 first board 11 intermediate 7 0 These bits contain the most significant bits of the MCST CBLT address of the module set via VME i e the address used in MCST CBLT operations 2 37 Relocation Address 0 10 r w Bit Function 15 0 These bits contains the A31 A16 bits of the address of the module it can be set via VME for a relocation of the Base Address of the module 2 38 Interrupt Status ID OxEF14 r w Bit Function 81 0 This register contains the STATUS ID that the module places on the VME data bus during the Interrupt Acknowledge cycle 2 39 Interrupt Event Number OxEF18 r w Bit Function 9 0 INTERRUPT EVENT NUMBER If inter
4. Bit Function 81 0 Output Buffer This register contains the number of events currently stored in the This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 2 29 Set Monitor DAC 0x8138 r w Bit Function 11 0 This register allows to set the DAC value 1251 This register allows to set the DAC value in Voltage level mode LSB 0 244 mV terminated on 50 Ohm 2 30 Board Info 0x8140 r Bit Function 15 8 Memory size Mbyte channel Board Type 70 0x03 1720 Filename V1720_REGISTERS Number of pages CAEN Q Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 31 Monitor Mode 0x8144 r w Bit Function This register allows to encode the Analog Monitor operation 000 majority 001 waveform generator saw tooth ramp 010 reserved 011 buffer occupancy 100 voltage level 2 0 2 32 Event Size 0x814C r Bit Function 31 0 Nr of 32 bit words in the next event 2 33 VME Control OxEFO00 r w Bit Function 7 0 Release On Register Access RORA Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode 6 0 RELOC Disabled BA is selected via Rotary Switch 1 RELOC Enabled BA is selected via RELOC register see 2
5. 7 CAEN Tools for Discovery Document type Title User s Manual MUT V1720 Registers Description Revision date 22 04 2013 RE S RESICLR REGISTER NAME ADDRESS ASIZE DSIZE MODE S BOARD INFO 0x8140 A24 A32 D32 MONITOR MODE 0x8144 A24 A32 D32 X X EVENT SIZE 0x814C 24 2 D32 X X X VME CONTROL OxEFOO A24 A32 032 X VME STATUS OxEFO4 A24 A32 D32 BOARD ID OxEFO8 A24 A32 D32 X X MULTICAST BASE ADDRESS amp CONTROL OxEFOC A24 A32 D32 X RELOCATION ADDRESS OxEF10 A24 A32 032 X INTERRUPT STATUS ID OxEF14 A24 A32 032 X INTERRUPT EVENT NUMBER OxEF18 A24 A32 032 X X BLT EVENT NUMBER OxEF1C A24 A32 032 X X SCRATCH OxEF20 A24 A32 D32 X X SW RESET OxEF24 24 32 032 W SW CLEAR OxEF28 A24 A32 D32 FLASH ENABLE OxEF2C A24 A32 032 X FLASH DATA OxEF30 A24 A32 032 X CONFIGURATION RELOAD OxEF34 A24 A32 D32 W CONFIGURATION ROM OxFO00 OxF3FC A24 A32 2 Filename V1720 REGISTERS 22 Number of pages Page 8 CAEN Tools for Discovery Document type User s Manual MUT 2 2 Title V1720 Registers Description Revision date 22 04 2013 Configuration ROM 0xF000 0xF084 The following registers contain some module s information they are D32 accessible read only These
6. BUFFER MEMORY BLOCK DIVISION cessere eene 13 Filename Number of pages Page 1720 REGISTERS 22 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 1 Important Notices The content of this document has been extracted from V1720 amp VX1720 User Manual Revision N 21 Date 06 February 2012 FOR RELEASES OF THE ROC FPGA FIRMWARE HIGHER THAN 3 8 THE CONTENT OF THIS DOCUMENT MAY RESULT NOT FULLY COMPLIANT IT IS INTENDED TO BE REPLACED BY A NEW DOCUMENT UNIFYING THE REGISTERS DESCRIPTIONS OF CAEN DIGITIZERS CURRENTLY IN PROGRESS Filename Number of pages Page 1720 REGISTERS 22 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 VME Interface The following sections will describe in detail the VME accessible registers content A N B bit fields that are not described in the register bit map are reserved and must not be over written by the User Filename Number of pages Page 1720 REGISTERS 22 6 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 1 Registers address map Table 2 1 Address Map for the Model V1720 H RE S RESCLR REGIST
7. Configuration ROM parameters and a PLL reconfiguration Filename Number of pages V1720 REGISTERS 22 Page 22
8. data are written into one Flash page at Power ON the Flash content is loaded OUI Version Board ID Revision Serial MSB Serial LSB manufacturer identifier IEEE OUI purchased version Board identifier hardware revision identifier serial number MSB serial number LSB Table 2 2 ROM Address Map for the Model V1720 Description Address Content checksum OxFOOO OxA4 checksum length2 OxF004 0x00 checksum lengthi 0 008 0x00 checksum lengthO OxFOOC 0x20 constant2 OxF010 0x83 constant1 OxF014 0x84 constantO OxF018 0x01 c_code OxFO1C 0x43 r code 0 020 0x52 oui2 OxF024 0x00 ouil 0 028 0 40 ouid OxFO2C OxE6 V1720 VX1720 0x30 V1720B VX1720B 0x31 V1720C VX1720C 0x32 vers OxF030 V1720D VX1720D 0x33 V1720E VX1720E 0x35 V1720F VX1720F 0x36 V1720G 0x37 V1720 0x00 board2 OxF034 VX1720 0x01 board1 OxF038 0x06 OxFO3C 0 8 revis3 OxF040 0x00 revis2 OxF044 0x00 revis1 OxF048 0 00 revisO OxFO4C 0x01 sernum1 OxF080 0 00 sernumO OxF084 0x16 into the Configuration RAM where it is available for readout Filename V1720 REGISTERS Number of pages 22 Page 9 CAEN Q Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 3 Channel n 25 THRES 0x1n24
9. r w Bit Function 31 0 Positive Logic 1 Negative Logic 30 11 reserved With Full Suppression based on the amplitude the 12 LSB represent the value to be compared with each sample of the event and see if it is over unedr threshold depending on the used logic With Zero Length Encoding the 12 LSB represent the value to be compared with each sample of the event and see if it is good or skip type 11 0 2 4 Channel n Z8 NSAMP 0x1n28 r w Bit Function With Full Suppression based on the amplitude ZS AMP bits 20 0 allow to set the number Ns of subsequent data which must be found over under threshold depending on the used logic necessary to validate the event if this field is set to 0 it is considered 1 With Zero length encoding ZLE bit 31 16 allows to set read the number of data to be stored before the signal crosses the threshold bit 15 0 allows to set read the number of data to be stored after the signal crosses the threshold 81 0 2 5 Channel n Threshold 0x1n80 r w Bit Function 11 0 Threshold Value for Trigger Generation Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth 4 samples 5 samples in Pack2 5 mode at least local trigger is delayed of Nth 4 5 samples with respect to input signal This register allows to
10. set Vth LSB input range 12bit 2 6 Channel n Over Under Threshold 0x1n84 r w Bit Function 11 0 Number of Data under over Threshold Each channel can generate a local trigger as the digitised signal exceeds the Vth threshold and remains under or over threshold for Nth 4 5 samples at least local trigger is delayed of Nth 4 samples 5 samples in Pack2 5 mode with respect to input signal This register allows to set Nth Filename Number of pages Page V1720 REGISTERS 22 10 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 7 Channel n Status 0x1n88 r Bit Function 5 Buffer free error 1 trying to free a number of buffers too large 4 3 reserved Channel n DAC see 2 10 Busy 2 1 Busy 0 DC offset updated 1 Memory empty 0 Memory full 2 8 Channel n AMC FPGA Firmware 0x1n8C r Bit Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format Example revision 1 3 of 12 June 2007 is 0x760C0103 2 9 Channel n Buffer Occupancy 0x1n94 r Bit Function 10 0 Occupied buffers 0 1024 2 10 Channel n DAC 0x1n98 r w
11. trigger enabled 4 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 2 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled This register bits 0 7 enable the channels to generate a TRG_OUT front panel signal as the digitised signal exceeds the Vth threshold BitO enables ChO to generate the TRG OUT bit enables Chi to generate the OUT and soon EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the TRG OUT SW TRIGGER ENABLE bit 31 enables the board to generate TRG_OUT see 2 20 6 2 23 Post Trigger Setting 0x8114 r w Bit Function 31 0 Post trigger value Allows to set the number of post trigger samples Npost PostTriggerValue 4 ConstantLatency where Npost number of post trigger samples PostTriggerValue Content of this register ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA this value is constant but the exact value may change between different firmware revisions 2 24 Front Panel I O Data 0x8118 r w Bit Function 15 0 Front Panel I O Data Allows to Readout the logic level of LVDS I Os and set the logic level of LVDS Outp
12. 37 5 0 ALIGN64 Disabled 1 ALIGN64 Enabled 0 BERR Not Enabled the module sends a DTACK signal until the CPU inquires the module 1 BERR Enabled the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 3 0 Optical Link interrupt disabled 1 Optical Link interrupt enabled 2 0 Interrupt level O interrupt disabled Bit 7 this setting is valid only for interrupts broadcasted on VMEbus interrupts broadcasted on optical link feature RORA mode only n mode interrupt status can be removed by accessing VME Control register see 2 33 and disabling the active interrupt level n ROAK mode interrupt status is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setting an Interrupt level 0 via VME Control register 4 2 34 VME Status OxEF04 Bit Function 0 BERR FLAG no Bus Error has occurred 2 1 BERR FLAG a Bus Error has occurred this bit is re set after a status register read out 1 0 The Output Buffer is not FULL 1 The Output Buffer is FULL 0 0 No Data Ready 1 Event Ready Filename Number of pages Page V1720_REGISTERS 22 CAEN Tools for Discovery Document type Title User s Manual MUT V1720 Registers Description 2 35 Board ID 0 08 Revision date Bit Function
13. 5 32 32K 40K 256K 320K 0x06 64 16K 20K 128K 160K 0x07 128 8K 10K 64K 80K 0x08 256 4K 5K 32K 40K 0x09 512 2K 2 5K 16K 20K 1024 IK 1 25K 8K 10K write access to this register causes a Software Clear This register must not be written while acquisition is running 2 16 Buffer Free 0x8010 r w Bit Function 11 0 N Frees the first Output Buffer Memory Blocks 2 17 Custom Size 0x8020 r w Bit Function 02 Custom Size disabled 31 0 40 Number of memory locations per event 1 location 2 samples or 2 locations 5 samples when Pack2 5 mode is used This register must not be written while acquisition is running Filename Number of pages Page V1720 REGISTERS 22 13 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 18 Acquisition Control 0x8100 r w Bit Function 0 COUNT ACCEPTED TRIGGERS 3 1 COUNT ALL TRIGGERS allows to reject overlapping triggers 0 Acquisition STOP 2 1 Acquisition RUN allows to RUN STOP Acquisition 00 REGISTER CONTROLLED RUN MODE 01 S INCONTROLLED RUN MODE 10 S IN GATE MODE 11 MULTI BOARD SYNC MODE Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset is automatically performed When bit 2 is reset to 0 the stored data are kept availa
14. ER NAME ADDRESS ASIZE DSIZE MODE S EVENT READOUT BUFFER 0x0000 0x0FFC 24 32 64032 X X X Channel n ZS_THRES 0x1n24 A24 A32 D32 RW X X Channel n ZS_NSAMP 0x1n28 A24 A32 D32 R W X X Channel n THRESHOLD Ox1n80 24 2 032 RW X X Channel n TIME OVER UNDER THRESHOLD Ox1n84 A24 A32 D32 RW X X Channel n STATUS Ox1n88 A24 A32 032 X X Channel n AMC FPGA FIRMWARE REVISION Ox1n8C A24 A32 032 Channel n BUFFER OCCUPANCY Ox1n94 A24 A32 032 X X X Channel n DAC 0 1 98 24 2 032 RW X X Channel n ADC CONFIGURATION Ox1n9C A24 A32 D32 RW X X CHANNEL CONFIGURATION 0x8000 24 2 032 RW X X CHANNEL CONFIGURATION BIT SET 0x8004 A24 A32 D32 X X CHANNEL CONFIGURATION BIT CLEAR 0x8008 A24 A32 D32 X X BUFFER ORGANIZATION 0x800C A24 A32 D32 RW X X BUFFER FREE 0x8010 A24 A32 D32 R W CUSTOM SIZE 0x8020 A24 A32 D32 RW X X ACQUISITION CONTROL 0x8100 A24 A32 D32 RW X X ACQUISITION STATUS 0x8104 A24 A32 032 HR SW TRIGGER 0x8108 A24 A32 D32 W TRIGGER SOURCE ENABLE MASK 0x810C A24 A32 D32 RW X X FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 A24 A32 D32 RW X X POST TRIGGER SETTING 0x8114 A24 A32 D32 RW X X FRONT PANEL I O DATA 0x8118 A24 A32 D32 RW X X FRONT PANEL I O CONTROL 0x811C A24 A32 D32 RW X X CHANNEL ENABLE MASK 0x8120 A24 A32 D32 RW X X ROC FPGA FIRMWARE REVISION 0x8124 A24 A32 032 EVENT STORED 0x812C A24 A32 032 X X X SET MONITOR DAC 0x8138 24 2 032 _ X X Filename Number of pages Page 1720 REGISTERS 22
15. REGISTERS 22 3 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 32 EVENT SZE OXS IAC R imi 20 2 33 VME CONTROL OXEFOO R W 20 2 34 VME STATUS OXEFO4 RE 20 2 35 BOARDID OXBEOS R W dessa cece es RIED ae ee eed 21 2 36 MCST BASE ADDRESS AND CONTROL OXEFOC nennen enne 21 2 37 RELOCATION ADDRESS OXEF10 2 221 2 221404 410000000 000000000000000000000000050000000 21 2 38 INTERRUPT STATUS ID OXEF14 2 1 2 2 4000 40000100000 enne enne ener rennen rennen ener enne 21 2 39 INTERRUPT EVENT NUMBER OXEF18 21 2 40 BLT EVENT NUMBER OXEF1C 21 2 41 SCRATCH 04S AUSTR 22 2 42 SOFTWARE RESET 0XEF24 22 2 43 SOFTWARE CLEAR O0XEE28 W a 22 2 44 FLASH ENABLE OXEE2C tette Hose eiat eas ne aree 22 2 45 FLASH DATA OXEF30 22 2 46 CONFIGURATION RELOAD OXEF34 22 LIST OF TABLES TABLE 2 1 ADDRESS MAP FOR THE MODEL 1720 esses 7 TABLE 2 2 ROM ADDRESS MAP FOR THE MODEL V 1720 9 TABLE 2 3 OUTPUT
16. Users Manual MUT 1720 Registers Description 22 04 2013 TABLE OF CONTENTS 1 IMPORTANT NOTICES 2 MOL T4 DIE CE DS 2 1 REGISTERS ADDRESS MAD itecto ne eden oes bra oa arto boe 2 2 CONFIGURATION 0 000 0 084 2 3 CHANNELN ZS THRES OX1N24 2 4 CHANNEL N ZS_NSAMP OX1N28 0 024 020 00000000 00000000000000000000000080000000 2 5 CHANNEL N THRESHOLD OX1N803 84 2 0 1 212 2 2424404000400 enne nennen nennen nennen nennen inner nr 2 6 CHANNEL OVER UNDER THRESHOLD OX1N84 enne enne 21 CHANNBEN STATUS OXTINS88 R 2 8 CHANNEL N AMC FPGA FIRMWARE 0X1NS8C 2 9 CHANNEL N BUFFER OCCUPANCY 0 1 94 2 10 CHANNEL N DAC 1198 isse tiet viens 2 11 CHANNEL N ADC CONFIGURATION OX1 NOC 222 40 1 4 42200000000000000000000000000000000 2 12 CHANNEL CONFIGURATION 0 8000 8 1 1 242060000001010000000000000000000000 enne nnne 2 13 CHANNEL CONFIGURATION BIT SET 0 8004 2 14 CHANNEL CONFIGURATION BIT CLEAR 0 8008 2 15 BUFFER ORGANIZATION 0 800 R W ccecsseceesesceceesseeecsneeececeececsesuececseneececsueeeceeaaeeeseesaeeesseeeeese
17. V1720 Registers Description 22 April 2013 MOD V1720 8 CHANNEL 12 BIT 250 MS S DIGITIZER CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation 4 CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boards CAEN Tools for Discovery Document type Title Revision date
18. ble for readout In Stop Mode all triggers are neglected Bits 1 0 descritpion 00 REGISTER CONTROLLED RUN MODE multiboard synchronisation via S_IN front panel signal RUN control start stop via set clear of bit 2 GATE always active Continuous Gate Mode 01 S IN CONTROLLED RUN MODE Multiboard synchronisation via S IN front panel signal S IN works both as SYNC and START command GATE always active Continuous Gate Mode 10 S IN GATE MODE Multiboard synchronisation is disabled IN works as Gate signal set clear of RUN STOP bit 11 MULTI BOARD SYNC MODE A Used only for Multiboard synchronisation 1 0 Filename Number of pages Page 1720 REGISTERS 22 14 CAEN Q Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 19 Acquisition Status 0x8104 r Bit Function Board ready for acquisition PLL and ADCs are synchronised correctly 0 not ready 1 ready 8 This bit should be checked after software reset to ensure that the board will enter immediatly run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur PLL Status Flag 0 PLL loss of lock 7 1 2 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see 2 34 PLL Bypass mode 6 0 No bypass mode 1 Bypass mode Clock sou
19. es 2 16 BUFFER FREE 0X8010 R W esses nier nen seen nnns 2 17 CUSTOM SIZE 0X8020 R W c cccecssccecsessececsecceceessececeesaeeecesseeceeseeecsesaececseneeceeaeeecseaaeeecensaeeeseeneeenes 2 18 ACQUISITION CONTROL 0X8100 eria a e o i Saiao 2 19 ACQUISITION STATUS 1045 2 20 SOFTWARE TRIGGER 0X8108 2 21 TRIGGER SOURCE ENABLE MASK 0X810C R W ccccsscccssssceceeseececseaececseneececaeeeceesaeeecsssaeeesenseeenes 2 22 FRONT PANEL TRIGGER OUT ENABLE MASK 0 8110 R W 2 23 POST TRIGGER SETTING 0X81 14 2 24 FRONT PANEL I O DATA 0 8118 2 25 FRONT PANEL CONTROL 0X81 1C 2 26 CHANNEL ENABLE MASK 0X8120 1 4 1 0 44 2000000000000000000000000005000000 2 27 ROC FPGA FIRMWARE REVISION 0 8124 24 4012 110 000000000000000000000000000050000000000000 2 28 EVENT STORED 0 812 2 29 SET MONITOR DAC 0 8138 2 30 BOARD INEO 0X8140 c ree secet E eee coe Ep CERE DAR EE 2 31 MONITOR MODE 0X8144 8 1 11 22440404 20240400 10 660 en nennen Filename Number of pages Page V1720
20. ich apply to all channels It is possible to perform selective set clear of the Channel Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0x8008 clear see the following 2 13 and 2 14 Default value is 0x10 3 2 13 Channel Configuration Bit Set 0x8004 w Bit Function Bits set to 1 means that the corresponding bits in the Channel 7 0 Configuration register are set to 1 2 14 Channel Configuration Bit Clear 0x8008 w Bit Function Bits set to 1 means that the corresponding bits the Channel 7 0 Configuration register are set to 0 Filename Number of pages Page V1720 REGISTERS 22 12 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 15 Buffer Organization 0x800C r w Bit Function 3 0 BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the following table Table 2 3 Output Buffer Memory block division REGISTER BUFFER NUMBER SIZE of one BUFFER samples SRAM 1 25MS ch SRAM 10MS ch V1720 C E F V1720B D G Std Pack2 5 Std Pack2 5 0x00 1 1M 1 25M 8M 10M 0x01 2 512K 640K 4M 5M 0x02 4 256K 320K 2M 2 5M 0x03 8 128K 160K IM 1 25M 0x04 16 64K 80K 512K 640K 0x0
21. rce 5 0 Internal 1 External EVENT FULL itis set to 1 as the maximum nr of events to be read is reached EVENT READY it is set to 1 as at least one event is available to readout 0 RUN off 2 1 RUNon 1 0 reserved 4 3 2 20 Software Trigger 0x8108 w Bit Function 31 0 A write access to this location generates a trigger via software Filename Number of pages Page V1720_REGISTERS 22 15 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 21 Trigger Source Enable Mask 0x810C r w Bit Function 31 0 Software Trigger Disabled 1 Software Trigger Enabled 30 0 External Trigger Disabled 1 External Trigger Enabled 29 27 reserved 26 24 Local trigger coincidence level default 0 23 8 reserved 7 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 6 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled 5 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 4 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 3 0 Channel 3 trigger disabled 1 Channel 8 trigger enabled 2 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled
22. rupts are enabled the module generates a request whenever it has stored in memory a Number of events INTERRUPT EVENT NUMBER 2 40 BLT Event Number OxEF1C r w Bit Function 7 0 be transferred via BLT CBLT This register contains the number of complete events which has to Filename V1720 REGISTERS Number of pages Page 22 21 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 41 Scratch OxEF20 r w Bit Function 81 0 Scratch to be used to write read words for VME test purposes 2 42 Software Reset 0 24 Bit Function 81 0 A write access to this location allows to perform a software reset 2 43 Software Clear OXEF28 w Bit Function 31 0 A write access to this location clears all the memories 2 44 Flash Enable OxEF2C r w Bit Function 0 0 Flash write ENABLED 1 Flash write DISABLED This register is handled by the Firmware upgrade tool 2 45 Flash Data OxEF30 r w Bit Function 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 2 46 Configuration Reload OxEF34 w Bit Function 81 0 A write access to this register causes a software reset a reload of
23. ut signals TRG OUT CLKOUT enabled 1 panel output signals TRG OUT CLKOUT enabled in high impedance 0 0 TRG CLK are NIM I O Levels 1 TRG CLK are TTL I O Levels Bits 5 2 are meaningful for General Purpose I O use only Filename Number of pages V1720_REGISTERS 22 Page 18 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 26 Channel Enable Mask 0x8120 r w Bit Function 7 0 Channel 7 disabled 12 Channel 7 enabled 0 Channel 6 disabled 6 1 Channel6 enabled 5 0 Channel 5 disabled 12 Channel 5 enabled 4 0 Channel 4 disabled 1 Channel 4 enabled 3 0 Channel disabled 1 Channel 3 enabled 2 0 Channel 2 disabled 1 Channel 2 enabled 1 0 Channel 1 disabled 12 Channel 1 enabled 0 0 Channel 0 disabled 12 Channel 0 enabled Enabled channels provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running 2 27 ROC FPGA Firmware Revision 0x8124 r Bit Function 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 7 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format 2 28 Event Stored 0x812C r
24. uts Filename Number of pages Page V1720_REGISTERS 22 17 CAEN Tools for Discovery Document type Title Revision date User s Manual MUT V1720 Registers Description 22 04 2013 2 25 Front Panel I O Control 0x811C r w Bit Function 15 0 I O Normal operations TRG OUT signals outside trigger presence trigger are generated according to Front Panel Trigger Out Enable Mask setting see 2 22 1 Test Mode TRG OUT is a logic level set via bit 14 14 1 TRG OUT Test Mode set to 1 0 TRG OUT Test Mode set to 0 13 10 reserved 9 PATTERN LATCH MODE 0 PATTERN field into event headers is the status of 16 LVDS Front Panel Inputs latched with board internal trigger if a post trigger value is set the internal trigger is delayed respect to external one 1 PATTERN field into event headers is the status of 16 LVDS Front Panel Inputs latched with external trigger rising edge 8 reserved 7 6 00 General Purpose 01 Programmed I O 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field 5 0 LVDS I O 15 12 are inputs 1 LVDS 15 12 are outputs 4 0 LVDS I O 11 8 are inputs 1 LVDS I O 11 8 are outputs 3 0 LVDS I O 7 4 are inputs 1 LVDS I O 7 4 are outputs 2 0 LVDS I O 3 0 are inputs 1 LVDS 3 0 are outputs 1 0 panel outp
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