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Programmer`s Reference Guide

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1. FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 9 FEF800E0 2 2 APE_TT APE_AP A R R FEF800E8 _ 80100 CTR32 88300 alg 0 818 _ FEF88000 FEF8FFF8 EXTERNAL REGISTER SET BIT gt O A A de ivmitjejoelo mwmdvsuwuotutoloeilo OE NY a hanl Aami Am o NI NI NI NIN ANI mio voi Notes 1 All empty bit fields are reserved and read as zeros 2 All status bits are shown in italics 3 All control bits are shown with underline 4 All control and status bits are shown with italics and underline Detailed Register Bit Descriptions The following sections describe the registers and their bits in detail The possible operations for each bit in the register set are as follows R The bit is a read only status bit 3 38 Computer Group Literature Center Web Site Programming Model bit is readable and writable R C The bit is cleared by writing a one to itself The possible states of the bits after local and power up reset are as defined below P The bit is affected by power up reset PURST L The bit is affected by local reset RST_ X bit is not affected by reset V The effect of reset on the bit is variab
2. 5 12 List of Tables Tabie Peg gii e 1 2 Table 1 2 Default Processor Memory Map en Uia eie telae 1 6 Table 1 3 CHRP Memory su en cae 1 7 Table 1 4 PHB Register Values for CHRP Memory Map 1 9 Table 1 5 PREP Memory Map Exanple scc tios ere bet ERE Ene to ERES ER 1 10 Table 1 6 PHB Register Values for PREP Memory Map 1 11 Table 1 7 PCLCHRP Memory sci neto sete aptae te Reb to 1 12 Table 1 8 PHB PCI Register Values for CHRP Memory Map 1 13 Table 1 9 Universe II PCI Register Values for CHRP Memory Map 1 14 Table 1 10 PCT PREP Memory MBSp SG dg RA 1 15 Table 1 11 PHB PCI Register Values for PREP Memory Map 1 16 Table 1 12 Universe II PCI Register Values for PREP Memory Map 1 17 Table 1 13 Universe II PCI Register Values for VMEbus Slave Map Example 1 22 Table 1 14 YMEbus Slave Map iiiter redeo IRSE RIEN tede 1 23 Table 1 15 16550 Access Rep Stars 1 25 Table 1 16 MK48T59 559 Access Registers 1 27 Tabl
3. Offset Value Field Type Description 50 0x32 80 51 0x33 00 52 0x34 B8 53 0x35 00 54 0x36 00 55 0x37 00 56 0x38 00 57 0x39 00 58 0x3A 00 59 0x3B 00 60 0x3C 00 61 0x3D 00 62 Ox3E 00 63 Ox3F 05 PACKET MPU Internal Clock Frequency in Hertz 350 MHz INTEGER 64 0x40 04 65 0x41 14 66 0x42 DC 67 0x43 93 68 0x44 80 69 0x45 06 PACKET MPU External Clock Frequency in Hertz 100 MHz ASCII 70 0x46 04 71 0x47 05 72 0x48 F5 73 0x49 El 74 Ox4A 00 75 0 4 09 MPU Type 750 http www motorola com computer literature A 11 A MVME2400 VPD Reference Information Table 5 VPD SROM Configuration Specification for 01 W3394F01 Continued Offset Value Field Type Description 76 0x4C 03 77 Ox4D 37 78 Ox4E 35 79 Ox4F 30 80 0x50 0A PACKET EPROM CRC INTEGER When computing the CRC this field that is 4 bytes is set to zero This CRC only covers the range as Integer 4 byte Note Lower CRC byte for the calculation of 00 and Upper byte for the calculation of CRC 255 81 0x51 04 82 0x52 Xx CRC to be filled in at ATE 83 0x53 Xx 84 0x54 85 0 55 86 0 56 FLASH Memory Configuration 1 BINARY 87 0x57 0A 88 0x58 00 89 0x59 01 90 0x5A
4. 011231 4 5167 8 91 OF 1 21 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 O 1 Name EAADR Operation Reset 00000000 http www motorola com computer literature 2 81 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Error Attribute Register The Error Attribute Register EATTR captures attribute information on the various errors that the PHB can detect If the XDPE PPER or PSER bits are set in the ESTAT register the contents of the EATTR register are zero If the XBTO bit is set the register is defined by the following figure Address FEFF002C Bit 11 1 1 1 1 1 1 1 1 2 2 2 2 2 2 3 3 0123 4567829 1121 3 6 7 8 9 OF 1 2 3 4 5 6 7 8 9 OJ 1 Name EATTR gt lt SB 28 Operation R R Reset 00 00 lo lo lolo XIDx Master ID This field contains the ID of the master which originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register TBST Transfer Burst This bit is set when the transfer in which the error occurred was a burst transfer TSIZx Transfer Size This field contains the transfer size of the PPC transfer in which th
5. CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Write N A N A 1 Beat Read 1 byte 18 18 18 18 1 Beat Read 2 to 8 bytes 54 18 54 18 1 Beat Write 21 21 B 21 21 Note The information in Table 3 3 applies to access timing when configured for devices with an access time equal to 8 clock periods Table 3 4 PPC60x Bus to ROM Flash Access Timing 505 2 100 MHz CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 42 15 36 9 36 9 36 9 150 42 4 Beat Write N A N A 1 Beat Read 1 byte 15 15 15 15 1 Beat Read 2 to 8 bytes 42 15 42 15 1 Write 21 21 gt 21 21 http www motorola com computer literature System Memory Controller SMC Note The information in Table 3 4 applies to access timing when configured for devices with an access time equal to 5 clock periods Table 3 5 PPC60x Bus to ROM Flash Access Timing 30ns 2 100 MHz CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TY
6. a tabs feq aD 2 82 PCI Interrupt Acknowledge Register 2 83 PPC Slave Address 0 1 and 2 uae ert eerte edente 2 84 Slave Offset Attribute 0 1 and 2 Registers 2 85 PPC Save Address 3 Fa ded 2 86 PPC Slave Offset Attribute 3 Registets sss sespiere tae raras iere p rra 2 87 Dr t 2 88 WDTSS TAT Turc T 2 90 General Purpose ease EP 2 90 BEI ITO jo e PH 2 91 Vendor ID Device ID 2 02 PCI Commands Status Reptglets iusisce ict rtr epa qbus 2 93 Revision Class Code Registers Lecce 2 95 Blender Ty pe We Site e 2 95 MPIC Base Address Repglster 2 96 MPIC Memory Base repe REPRE AH Rb pd 2 97 PCI Slave Address 0 1 2 and 3 rre re 2 98 PCI Slave Attribute Offset 0 1 2 and 3 2 99 CONFIG ADDRESS nR E 2 100 DATA ROGUSIED x ap A a 2 103 2 104 MPI 1 T 2 104 peuture 2 108 Global Configuration Register
7. MEA UTERE 3 1 Block Diagrami eL 3 2 Pinca Deserve T 3 6 Performa C eC 3 6 Reads WAOS P ERN ai 3 6 Single beat Reads WTOS 3 7 Address 3 7 Pape Holding VESRR PUR E NER 3 7 SDRAM Specs 3 7 SDRAM 3 9 DISP M M HH 3 10 PowerPC 60 Bus Interacts ace ee praes 3 12 Responding to Address Transits 3 12 Completing Data 2 13 PPODUE Dara PHO 3 13 lu p 4 chi codi Pe 3 13 Cache RN N R 3 14 Cache Caherency 3 14 L2 ache sits peste MEDI an M 3 14 E 3 15 3 15 luigi dcr ANT ehh 3 15 usse ro re 3 17 RONDE Isi Eel B
8. 2 49 xvii Table 2 16 PPC Register Map for iarciet erras 2 66 Table 2 17 PCI Configuration Register ees reb Rete kb bo ade tna 2 91 Table 2 15 PCI IO Resister Map ceo OE EDEN HEATH as 2 92 Table 2 19 MPIC Register espada 2 105 Table 2 20 Cascade Mode Encoding NE 2 109 Tate 2 21 Te Mode ertt Urbes Mecano 2 109 Table 3 1 60x Bus to SDRAM Estimated Access Timing at 100 2 with PETOIO SDRAMs CAS latency ab 2 uie pbi 3 8 Table 3 2 PowerPC 60x Bus to ROM Flash Access Timing ee En 3 10 Table 3 3 PowerPC 60x Bus to ROM Flash Access Timing ODE c TUS 3 10 Table 3 4 PowerPC 60x Bus to ROM Flash Access Timing 50ns 9 100MH2 3 11 Table 3 5 PowerPC 60x Bus to ROM Flash Access Timing 30ns 100MHz 3 12 Table 3 5 Eror Repor ue eei Ri ER Steps Rocio n DER URDU RUE 3 16 Table 3 7 PowerPC 60x to ROM Flash 16 Bit Width Address Mapping 3 19 Table 3 8 PowerPC 60x to ROM Flash 64 Bit Width Address Mapping 3 20 Table S9 Remar SUD deti rab Udo de EE AE EU D DO 3 36 Table 3 10 Block A B C D E F G H Configurations eere 3 42 Table 3 11 ROM Bloek A Size
9. 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 Bit 1098765 4 3 2 1 0 91 8 7 6 5 4 3 2 1 0 9 8 71 6543 2 1 0 PSADD2 90 PSOFF2 PSATT2 94 PSADD3 98 PSOFF3 PSATT3 9C Table 2 18 PCI I O Register 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 109 87 6 5 4 3 2 109 8 7 6 5 43 2 10987 6 5 CONFIG_ADDRESS CF8 CONFIG_DATA CFC Vendor ID Device ID Registers Offset 00 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 I 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 43210 Name DEVID VENID Operation R R Reset 4803 1057 VENID Vendor ID This register identifies the manufacturer of the device This identifier is allocated by the PCI SIG to ensure uniqueness 1057 has been assigned to Motorola This register is duplicated in the PPC Registers DEVID Device ID This register identifies the particular device The Hawk will always return 4803 This register is duplicated in the PPC Registers 2 92 Computer Group Literature Center Web Site Registers PCI Command Status Registers The Command Register COMMAND provides course control over the PHB ability to generate and respond to PCI cycles The bits within the COMMAND register are defined as follows Offset 04 Bit S DJ oer ow lee
10. 2 108 Vendor Identification RIG uri PE 2 110 Frocessor Imi RecN is 2 110 IPI ovii duni 4c E 2 111 SSUES Vect AREE an E xem 2 112 Timer Fregueney Diis I 2 112 Timer Current Count Rents Ree iu 2 113 Timer Basecount EE 2 114 Timer Vecto PHOEBE aa oor apir 2 115 Timer Destian R 2 116 External Source Vector Pnonty Registers cc icc aaepe tinet 2 116 External Source Destination 2 118 PHB Detected Errors Vector Priority 1 2 118 PHE Detected Errors Destination Register eite rete 2 119 Interprocessor Interrupt Dispatch 22222 2 120 Interrupt Task Priority Reise bete iive teneis bep aa 2 120 Interrupt Acknowledge Resisteta zione irte pete lacked sk 2 121 Interrupt Registers aoa diaeta Hese iy 2 122 CHAPTER3 System Memory Controller SMC PRO E E ER ein 3 1 3 1 supe i PET 3 1
11. aeo o en AL AY A Q1 AN AY AY ei SS SS SS SS en Name STATUS COMMAND o lt A m X am S lt 9 lees S el 4a e m m Beis wed 1 o 55 Operation E E zzE ZIZ ZZ a a En Eo Eo En En Eo o E a EP EE EP Er EE E 22 22 22 Reset oooooco o ojoo lo oooo oj ooooio oloo lo onjoo IOSP IO Space Enable If set the PHB will respond to PCI I O accesses when appropriate If cleared the PHB will not respond to PCI I O space accesses MEMSP Memory Space Enable If set the PHB will respond to PCI memory space accesses when appropriate If cleared the PHB will not respond to PCI memory space accesses MSTR Bus Master Enable If set the PHB may act as a master on PCI If cleared the PHB may not act as a PCI master PERR Parity Error Response If set the PHB will check parity on all PCI transfers If cleared the PHB will ignore any parity errors that it detects and continue normal operation SERR System Error Enable This bit enables the SERR output pin If clear the PHB will never drive SERR If set the PHB will drive SERR active when a system error is detected The Status Register STATUS is used to record information for PCI bus related events The bits within the STATUS register are defined as follows http www motorola com computer literature 2 93 Hawk PCI Host Bridge amp Multi Processor Interrupt
12. eee DU obese Doris WESEL VEL 2 4 MH aes ie 2 4 p 2 5 lager i cr p D RS 2 5 PPC os I Gs 2 7 PPC EIR t H 2 9 PPE Wester uL 2 10 2 15 PS NM er re 2 17 PPC Bos 2 17 PELEUS T 2 19 Address rini t 2 19 eir EE 2 22 1 001 5 2 26 e ri pe 2 26 Generating PEIC d e 2 30 2 34 jS ni pp Mr i0 T MM EN 2 38 When PPC Devices are Big Endispi iue eter ntes rob Hispa 2 38 When PPC Devices axe Little 2 39 d mE 2 40 sama E 2 41 2 42 PCUPPC Contention Han E se cass ie oir pte 2 44 Transdetom PR 2 47 PHE Hardware Cons BEHEIODO a 2 49
13. 3 49 Eiror Address Res ic rer perte PIE PR EE PER 3 50 Soruib Refresh epe Vra R HRS E EET VERRE URS EERUS 3 51 Scb Address 4714 jr e 3 52 ROM Base Size 3 53 ROM B 517 cenione 3 56 ROM Speed Attributes Registers eroe teret certe 3 58 Data Panty Error Log uei cepe 3 59 Data Parity Error Address 3 60 Data Panty Error Upper Data 3 60 Data Parity Error Lower Data Register re nente 3 61 DC Clock Prescaler Register e Ree dI de Spei 3 61 PE Contor oii qe m PU 3 62 nd d 10 TER 3 63 DC Transmiter Data a oci dio ede 3 64 UC Receiver 3 65 SDRAM Enable and Size Register Blocks E F G H 3 65 SDRAM Base Address Register Blocks 3 66 SDRAM Speed Attributes Besstef ee eoe 3 68 Address Parity Error Log Ree iter cuis 3 70 Address Parity Error Address Register ste e 3 71 Mo EE 3 71 External 3 72
14. AT EE 3 73 SEE n n ri ipo PER e 3 74 Programming ROMP bash Devices iita nina entre rene canes KURSE RA 3 74 Whiting tothe Control Diete ode ego Epub UH 3 74 Initializing SDRAM Related Control Registers eee 3 75 SDRAM Spesd ATIDIIMSS pr ER bu UE 3 75 SDRAM eir Ec 3 76 em 3 76 SDRAM Base Address and Enable iier ciae atre tae Men 3 76 SDRAM Control Registers Initialization Example 3 77 Optional Method for Sizing SDRAM sisisi uie sistere 3 82 deli E 3 86 CHAPTER 4 Universe VMEbus to PCI Chip General LTT ld UN discedere vea Nac VOR HE NER 4 1 4 1 Product Overview DESUMBS 4 1 4 2 Architectural CV CIV 4 2 SITIOS MIEI eeina n 4 4 PCI Bus Inter ate si 4 5 Inteceupter and Interrupt Handler iiec 4 6 DMA Conttollef M 4 7 Registers Universe II Control and Status Registers UCSR 4 8 Universe II Resister Map secet tho tek erre
15. MID Current PPC Data Bus Master 00 device on ABGO 01 device on 1 10 device on ABG2 11 Hawk Computer Group Literature Center Web Site Registers Arbiter PCI Arbiter Control Registers The Arbiter Register XARB provides control and status for the Arbiter Please refer to the section titled PPC Arbiter for more information The bits within the XARB register are defined as follows Address FEFFO00C Bit 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 0111213141516 71 8 9 OF 11 2 3 4 5 6 7 890 1 2 3 4 5 6 7 8 9 O 1 Name XARB PARB 55205220 BRE 25532229322 3 Eri pri ETI 255 AB gt gt Operation RW 0 le le a ZEE 22212222 zz Reset 0 DIS JO IO o iIoO o le Io o im Io Io Io o o o o IO o oO oojo FBRx Flatten Burst Read This field is used by the PPC Arbiter to control how bus pipelining will be affected after all burst read cycles The encoding of this field is shown in the table below FSRx Flatten Single Read This field is used by the PPC Arbiter to control how bus pipelining will be affected after all single beat read cycles The encoding of this field is shown in the table below FBWx Flastten Burst Write This field is used by the PPC Arbiter to control how bus pipelining will be affected afte
16. Input EXTL Request Input http www motorola com computer literature 2 15 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller While RST_ is asserted XARBO through XARB4 will be held in tri state If the internal arbiter mode is selected then XARBO through XARB3 will be driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST_ If the external arbiter mode has been selected then XARB4 will be driven to an active state no more than ten clock periods after PHB has detected a rising edge on RST The PPC Arbiter implements the following prioritization scheme HAWK Highest Priority a EXTL CPUx CPUy Lowest Priority The PPC Arbiter is controlled by the XARB register within the PHB PPC60x register group The PPC Arbiter supports two prioritization schemes Both schemes affect the priority of the CPU s with respect to each other The CPU fixed option always places the priority of CPUO over that of CPU1 The CPU rotating option gives priority on a rotational basis between CPUO and CPUI In all cases the priority of the CPUs remains fixed with respect to the priority of HAWK and EXTL with HAWK always having the highest priority of all The PPC Arbiter supports four parking modes Parking is implemented only on the CPUs and is not implemented on either HAWK or EXTL The parking options include parking on CPUO parking on CPUI park
17. INT 0 Figure 2 9 MPIC Block Diagram http www motorola com computer literature 2 57 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Program Visible Registers These are the registers that software can access They are described in detail in the MPIC Registers section Interrupt Pending Register IPR The interrupt signals to MPIC are qualified and synchronized to the clock by the IPR If the interrupt source is internal to the Hawk ASIC or external with their Sense bit 0 edge sensitive a bit is set in the IPR That bit is cleared when the interrupt associated with that bit is acknowledged If the interrupt source is external and level activated the output from the IPR is not negated until the level into the IPR is negated Externally sourced interrupts are qualified based upon their Sense and or Pol bits in the Vector Priority register IPI and Timer Interrupts are generated internally to the Hawk ASIC and are qualified by their Destination bit Since the internally generated interrupts use direct delivery mode with multicast capability there are two bits in the IPR one for each processor associated with each IPI and Timer interrupt source The MASK bits from the Vector Priority registers is used to qualify the output of the IPR Therefore if an interrupt condition is detected when the MASK bit is set that interrupt will be requested when the MASK bit is lowered Interrupt Selector IS
18. LOAD DEVICE ADDR WR BIT TO I2C TRANSMITTER DATA REG READ 2 STATUS REG Y LOAD WORD ADDR TO I2C TRANSMITTER DATA REG READ 2 STATUS REG Y LOAD DATA TO 2 TRANSMITTER DATA REG READ 2 STATUS REG Y LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ 2 STATUS REG Y END Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 5 Programming Sequence for I2C Byte Write 3 24 Computer Group Literature Center Web Site Functional Description 2 Random Read The I C random read begins in the same manner as the PC byte write The first step in the programming sequence should be to test the 12 cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the 12 start and 12 enbl bits in the 2C Control Register and then writing the device address bits 7 1 and write bit bit 0 0 to the 72C Transmitter Data Register The i2 bit will be automatically clear with the write cycle to the PC Transmitter Data Register The PC Status Register must now be polled to test the i2_cmplt and i2_ackin bits The i2_cmplt bit becomes set when the device address and write bit have been transmitted and the i2_ackin bit provides status as to wheth
19. oco NI NIN AIAN AY AT ele SIKIS SISISIS E E EIEIEIE E E E E E E EIEIEIE E E E E 8 SIS RISE 2 221222 22222 4 24 24 24 24 m 24 24 Reset i al aalala B alallala B 4 x ANN 4 xX Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write http www motorola com computer literature System Memory Controller SMC Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 Bit Counter to increment at least 100 times The wait period needs to happen during the envelope ram e f g h en ram e f g h en enables
20. FEFF0004 REVID 0008 GCSR FEFF000C XARB PARB FEFF0010 XPAD FEFF0014 FEFF0018 FEFF001C FEFF0020 ETEST EENAB FEFF0024 ESTAT FEFF0028 EADDR 002 EATTR FEFF0030 PIACK FEFF0034 FEFF0038 2 66 Computer Group Literature Center Web Site Registers Table 2 16 PPC Register Map for PHB Continued Bit gt 003 412234567 111 89012 111 4 5 6 Mom 112 8 90 2222 22 45 6789 3 3 0 1 FEFF0040 XSADDO FEFF0044 XSOFFO XSATTO FEFF0048 XSADDI FEFF004C XSOFFI XS ATTI FEFF0050 XSADD2 FEFF0054 XSOFF2 XSATT2 FEFF0058 XSADD3 005 XSOFF3 XSATT3 FEFF0060 WDTICNTL FEFF0064 WDTISTAT FFEF0068 WDT2CNTL 006 WDT2STAT FEFF0070 GPREGO Upper FEFF0074 GPREGO Lower FEFF078 GPREGI Upper FEFF07C GPREGI1 Lower Vendor ID Device ID Registers Address 0000 Bit 0121345 6 7 m ON oo VENID Operation R Reset 1057 http www motorola com computer literature Hawk PCI Host Bridge amp
21. CR CSR space be sure to add 508 KBytes 0 7 00 to the address offsets provided in the table Table 4 1 Universe Register Map Offset Register Name 000 PCI Configuration Space ID Register PCI ID 004 PCI Configuration Space Control and Status Register PCI CSR 008 PCI Configuration Class Register PCI CLASS 00C PCI Configuration Miscellaneous 0 Register PCI MISCO 010 PCI Configuration Base Address Register PCI BS 014 PCI Unimplemented 018 PCI Unimplemented 01C PCI Unimplemented 020 PCI Unimplemented 024 PCI Unimplemented 028 PCI Reserved 02C PCI Reserved 030 PCI Unimplemented 034 PCI Reserved 038 PCI Reserved 03C PCI Configuration Miscellaneous 1 Register PCI MISCI 040 OFF PCI Unimplemented 100 PCI Slave Image 0 Control LSIO CTL 104 PCI Slave Image 0 Base Address Register LSIO BS http www motorola com computer literature 4 9 Universe II VMEbus to PCI Chip Table 4 1 Universe Register Map Continued Offset Register Name 108 PCI Slave Image 0 Bound Address Register LSIO BD 10 PCI Slave Image 0 Translation Offset LSIO TO 110 Universe II Reserved 114 PCI Slave Image 1 Control LSI1 CTL 118 PCI Slave Image 1 Base Address Register 5 BS PCI Slave Image 1 Bound Address Register LSI1 BD 120 PCI Slave Image 1
22. System Memory Controller SMC ROM Flash Speeds The SMC provides the interface for two blocks of ROM Flash Access times to ROM Flash are programmable for each block Access times are also affected by block width Refer to the following tables for some specific timing numbers Table 3 2 PPC60x Bus to ROM Flash Access Timing 120ns 2 100 MHz CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 70 22 64 16 64 16 64 16 262 70 4 Beat Write N A N A 1 Read 1 byte 22 22 22 22 1 Beat Read 2 to 8 bytes 70 22 70 22 1 Beat Write 21 21 21 21 Note Table 3 3 PPC60x Bus to ROM Flash Access Timing 80ns 100 MHz The information in Table 3 2 applies to access timing when configured for devices with an access time equal to 12 clock periods CLOCK PERIODS REQUIRED FOR Total 1st Beat 2nd Beat 3rd Beat 4th Beat Clocks ACCESS TYPE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 54 18 48 12 48 12 48 12 198 54 3 10 Computer Group Literature Center Web Site Functional Description Table 3 3 PPC60x Bus to ROM Flash Access Timing 80ns 100 MHz Continued
23. Available in 313 pin Plastic and 324 pin contact Ceramic BGA Functional Description Architectural Overview This section introduces the general architecture of the Universe II This description makes reference to the functional block diagram provided in Figure 4 1 that follows Notice that for each of the interfaces VMEbus and PCI bus there are three functionally distinct modules master module slave module and interrupt module These modules are connected to the different functional channels operating in the Universe II These channels are VME Slave Channel PCI Bus Slave Channel DMA Channel Interrupt Channel Register Channel The Architectural Overview is organized into the following sections VMEbus Interface PCI Bus Interface 4 2 Computer Group Literature Center Web Site Functional Description a Interrupter and Interrupt Handler DMA Controller These sections describe the operation of the Universe II in terms of the different modules and channels illustrated in the following figure DMA Channel gt DMA bidirectional FIFO PCI Bus VMEbus Interface Interface VMEbus Slave Channel PCI posted writes FIFO VME Master E i prefetch read FIFO Slave He coupled read l i
24. Table 1 10 PCI PREP Memory Map PCI Address Size Notes Start End 0000 0000 FFFF 16M PCI ISA Memory Space 0100 0000 2FFF FFFF 752 VMEbus 32 032 Super Program 3 3000 0000 37FF FFFF 128M VMEbus A32 D16 Super Program 3 3800 0000 38FE FFFF 16M 64K VMEbus A24 D16 Super Program 4 38FF 0000 38FF FFFF 64K VMEbus A16 D16 Super Program 4 3900 0000 39FE FFFF 16M 64K VMEbus A24 D32 Super Data 4 39FF 0000 39FF FFFF 64K VMEbus A16 D32 Super Data 4 3A00 0000 3AFE FFFF 16M 64K VMEbus A24 D16 User Program 4 3AFF 0000 3AFF FFFF 64K VMEbus A16 D26 User Program 4 3B00 0000 3BFEFFFF 16M 64K VMEbus A24 D32 User Data 4 3BFF 0000 3BFF FFFF 64K VMEbus A16 D32 User Data 4 http www motorola com computer literature 1 15 Board Description and Memory Maps Table 1 10 PCI PREP Memory Map Continued PCI Address Size Definition Notes Start End 3 00 0000 7FFF 1G 64 PCI Memory Space 8000 0000 FBFF FFFF 2G 64M Onboard ECC DRAM 1 0000 256K MPIC 1 4 0000 FFFF FFFF 64M 256K PCI Memory Space Notes 1 Programmable via the PHB s PCI Configuration registers For the MVME2400 series RAM size is limited to 256MB 2 To enabled the CHRP io hole program the PHB to ignore the 0x000A0000 0x000FFFFF address range 3 Programmable mapping via the four PCI Slave Images in th
25. The processor will not receive interrupts with a priority level equal to or lower than its current task priority Therefore setting the current task priority to 15 prohibits the delivery of all interrupts to the associated processor Nesting of Interrupt Events A processor is guaranteed never to have an in service interrupt preempted by an equal or lower priority source An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI End of Interrupt is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt Spurious Vector Generation Under certain circumstances the MPIC will not have a valid vector to return to the processor during an interrupt acknowledge cycle In these cases the spurious vector from the spurious vector register will be returned The following cases would cause a spurious vector fetch INT is asserted in response to an externally sourced interrupt which is activated with level sensitive logic and the asserted level is negated before the interrupt is acknowledged INT is asserted for an interrupt source which is masked using the mask bit in the Vector Priority register before the interrupt is acknowledged Interprocessor Interrupts IPI Processor 0 and 1 can generate interrupts which are targeted for the other processor or both processors There are four Interprocessor Inte
26. The scale factor is calculated as follows XPAD 256 where 1 is the frequency of the CLK input in MHz The following table shows the scale factors for some common CLK frequencies Frequency XPAD 100 9C 83 AD 66 BE 50 CE 2 76 Computer Group Literature Center Web Site Registers PPC Error Test Error Enable Register The Error Test Register ETEST provides a way to inject certain types of errors to test the PHB error capture and status circuitry The bits within the ETEST are defined as follows Address FEFF0020 Bit e A vr eg St CO EY O N e SEY w N NNT 0 0 ETEST EENAB 22 552 S lt lt da s pes os ot a a ee iE A A Al A A A A As AAAA A A A aa a e Ole Al lt CQ P lt aa P lt P lt 5252 5555 5252552 5855255 eA eA 04 e o Reset o OHO o o o o o o OY o OY 9 9 o o 9 O OY o OY O o o o O O o o DPEx Dat
27. 0 1 2134 56 78 9 OF 1 213 4 5 6 7 8 9 OF 1 2 3 4 5 6 71 8 9 O 1 Name GCSR T Sm ESE E Reset LEND Endian Select If set the bus is operating in little endian mode The PPC address will be modified as described in the section titled When PPC Devices are Little Endian When LEND is clear the PPC bus is operating in Big Endian mode and all data to from PCI is swapped as described in the section titled When PPC Devices are Big Endian PFBR PCI Flush Before Read If set the PHB will guarantee that all PPC initiated posted write transactions will be completed before any PCI initiated read transactions will be allowed to complete When PFBR is clear there will be no correlation between these transaction types and their order of completion Please refer to the section on Transaction Ordering for more information XMBH PPC Master Bus Hog If set the PPC master of the PHB will operate in the Bus Hog mode Bus Hog mode means the PPC master will continually request the PPC bus for the entire duration of each transfer If Bus Hog is not enabled the PPC master will request the bus in a normal manner Please refer to the section on PPC Master for more information http www motorola com computer literature 2 69 Hawk PCI Host B
28. 7 6 5 4 3 2 109876 5 4 3 21 10 TIMER BASECOUNT BC Operation R W Reset 00000000 CI Count Inhibit Setting this bit to one inhibits counting for this timer Setting this bit to zero allows counting to proceed BC Base Count This field contains the 31 bit count for this timer When a value is written into this register and the CI bit transitions from a 1 to a O it is copied into the corresponding Current Count register and the toggle bit in the Current Count register is cleared When the timer counts down to zero the Current Count register is reloaded from the Base Count register and the timer s interrupt becomes pending in MPIC processing 2 114 Computer Group Literature Center Web Site Registers Timer Vector Priority Registers Offset Timer 0 01120 Timer 1 01160 Timer 2 011A0 Timer 3 011E0 Bit 3 1 3 0 2 9 2 2 2 2 2 2 2 2 2 8 7 6 5 4 3 2 1 O 9 8 7 6 5 4 3 2 11 OF of 81 76 5432 1 0 mi Name T IMER VECTOR PRIORITY gt 4 PRIOR VECTOR Operation R W R R W Reset 000 0 00 00 MASK Mask Setting this bit disables any further i
29. BIT SD7 SD6 SD5 SD4 SD3 SD2 SDI 5 0 FIELD VA7 VA6 VA5 VA4 LMEN OPER R W R R R RESET 0 0 0 0 0 0 0 VA 7 4 Lower Base Address for the location monitor function LMEN This bit must be set to enable the location monitor function Semaphore Register 1 The Semaphore Register 1 is an 8 bit register located at ISA I O address x1004 The Universe II ASIC is programmed so that this register can be accessible from the VMEbus This register can only be updated if bit 7 is low or if the new value has the most significant bit cleared When bit 7 is high this register will not latch in the new value if the new value has the most significant bit set REG Semaphore Register 1 Offset 1004 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SDO FIELD SEM1 OPER R W RESET 0 0 0 0 0 0 0 0 http www motorola com computer literature 1 31 Board Description and Memory Maps Semaphore Register 2 The Semaphore Register 2 is an 8 bit register located at ISA I O address x1005 The Universe II ASIC is programmed so that this register can be accessible from the VMEbus This register can only be updated if bit 7 is low or if the new value has the most significant bit cleared When bit 7 is high this register will not latch in the new value if the new value has the most significant bit set REG Semaphore Register 2 Offset 1005 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SDO F
30. Byte Lane Selection Results KEY ENAB RELOAD WDT WDTXxCNTL Register RES 0 7 8 15 16 23 24 34 Prescaler Counter RES ENAB RELOAD Enable No No Change No Change No Change No Change Yes No No Update from Updatefrom No Change No Change RES ENAB RELOAD Yes No Update from Updatefrom No Change No Change RES ENAB RELOAD Yes No Yes Yes Update from Update from No Change Update from RES ENAB data bus data bus Yes Yes No X Update from Updatefrom Updatefrom No Change data bus RELOAD data bus Yes Yes Update from Updatefrom Updatefrom No Change data bus RELOAD data bus Yes Yes Yes Yes Update from Updatefrom Updatefrom Update from data bus data bus data bus data bus The WDTxCNTL register will always become unarmed after the second write regardless of byte lane selection Reads may be performed at any time from the WDTxCNTL register and will not affect the write arming sequence PCI PPC Contention Handling The PHB has a mechanism that detects when there is a possible resource contention problem that is deadlock as a result of overlapping PPC and PCI initiated transactions The PPC Slave PCI Slave and PCI Master functions contain the logic needed to implement this feature 2 44 Computer Group Literature Center Web Site Functional Description The PCI Slave and the PPC Slave contribute to this mechanism in the following manner Each sl
31. CF 10 ckd4 30 50 70 rd53 90 0 rd50 D0 rd46 F0 11 31 49 51 rd43 71 91 rd39 BI DI 1 12 32 rd63 52 rd40 72 92 416 B2 D2 F2 813 rd17 33 53 73 593 B3 D3 rd60 F3 14 34 rd62 54 rd59 74 94 rd56 B4 D4 F4 rdl 2 15 11 35 55 75 595 B5 D5 5 16 10 36 56 76 96 B6 D6 F6 17 37 57 77 97 B7 D7 F7 18 38 rd61 58 rd58 78 98 rd57 B8 D8 8 19 rd7 39 59 79 99 B9 D9 F9 3 5A 7A rd20 9 DA FA 1B 53 55 7 9 BB DB http www motorola com computer literature 3 87 System Memory Controller SMC Table 3 22 Single Bit Errors Ordered by Syndrome Code Continued o o o o v o E E 2 2 2 3 Ez 5 S 5 un un un un un SIC rd5 3C 5C 7C 59 BC DC FC 1D 3D rd2g 5 7D 9D BD DD 1E 3E 5E 7E 9E rd36 BE DE FE IF 3F 5F 7 9F DF FF 2 3 88 Computer Group Literature Center Web Site Universe VMEbus to PCI Chip Note of the information in this chapter is taken from the Universe
32. For example when using 8 bit devices the code will be split so that every other 4 byte segment goes in each device Writing to the Control Registers Software should not change control register bits that affect SDRAM operation while SDRAM is being accessed Because of pipelining software should always make sure that the two accesses before and after the updating of critical bits are not SDRAM accesses A possible scenario for trouble would be to execute code out of SDRAM while updating the critical SDRAM control register bits The preferred method is to be executing code out of ROM Flash and avoiding SDRAM accesses while updating these bits Computer Group Literature Center Web Site Software Considerations Some registers have additional requirements for writing For more information refer to the register sections in this chapter titled SDRAM Enable and Size Register Blocks A B C D SDRAM Base Address Register Blocks A B C D SDRAM Enable and Size Register Blocks E F G H SDRAM Base Address Register Blocks E F G H and SDRAM Speed Attributes Register Since software has no way of controlling refresh scrub accesses to SDRAM the hardware is designed so that updating control bits coincidentally with refreshes is not a problem As with SDRAM control bits software should not change control bits that affect ROM Flash while the affected Block is being accessed This generally means that the ROM Flash size base address ena
33. II User Manual which is listed in Appendix B Related Documentation Refer to that manual for complete information General Information Introduction The Universe II VMEbus interface chip CA91C142 provides a reliable high performance 64 bit VMEbus to PCI interface in one device Designed by Tundra Semiconductor Corporation in consultation with Motorola the Universe II is compliant with the VME64 specification and is tuned to the new generation of high speed processors The Universe is ideally suited for CPU boards acting as both master and slave in the VMEbus system and is particularly fitted for PCI local systems The Universe II is manufactured in a CMOS process Product Overview Features Fully compliant 64 bit 33 MHz PCI local bus interface Fully compliant high performance 64 bit VMEbus interface Integral FIFOs for write posting to maximize bandwidth utilization Programmable controller with linked list support VMEbus transfer rates of 60 70 MB ytes sec Complete suite of VMEbus address and data transfer modes A32 A24 A16 master and slave D64 MBLT D32 D16 D08 master and slave 4 1 Universe II VMEbus to PCI Chip BLT ADOH RMW LOCK Automatic initialization for slave only applications Flexible register set programmable from both the PCI bus and VMEbus ports Full VMEbus system controller functionality a IEEE 1149 1 JTAG testability support and
34. Multi Processor Interrupt Controller VENID Vendor ID This register identifies the manufacturer of the device This identifier is allocated by the PCI SIG to ensure uniqueness 1057 has been assigned to Motorola and is hardwired as a read only value This register is duplicated in the PCI Configuration Registers DEVID Device ID This register identifies this particular device The Hawk will always return 4803 This register is duplicated in the PCI Configuration Registers Revision ID Register Address FEFF0004 Bit 1 1 1 1 1 dy dy a 1 2 2 2 2 2 2 2 2 2 2 3 3 0 1 3 41 5 6 7 8 9 O 1 2 3 6 7 8 9 O 1 2 3 4 5 6 7 8 9 OF 1 Name REVID Operation R R R R Reset 00 01 00 00 REVID Revision ID This register identifies the PHB revision level This register is duplicated in the PCI Configuration Registers 2 68 Computer Group Literature Center Web Site Registers General Control Status Feature Registers The General Control Status Feature Registers GCSR provides miscellaneous control and status information for the PHB The bits within the GCSR are defined as follows Address 0008 Bit 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3
35. Multi Processor Interrupt Controller MPIC Functional Description 2 50 i TET 2 50 quet 2 51 External Inbercupt ateri AGE anti appris nah nt Yk 2 51 CoR S irap qe 2 52 latercupt Source pen daa 2 52 Processor Task PUIDUIEYS 2 53 viii Nesting ot Interr pt 5 2 53 Spurious Vector Celo 2 53 2 53 XA Lapis ee T 2 54 PHB Detected Biot usce n edet E Re 2 54 fin 2 55 Interrupt Delivery Modes en he eR CY RM GERE 2 55 Block rur inl via RR 2 56 Program Visible nre E 2 58 Interrupt Pendine Register IPR ies 2 58 Iiterrapt Selector 5 Jeina 2 58 Intercupt Request AID ni 2 59 In Service Resister c essere c IR CORR HR RU VOR Fe CHR NU YER A HR EUR FREUE 2 59 M IE 2 59
36. PCI ISA interrupt assignments 5 6 pipelining removing 2 7 PMC slots described 1 5 PowerPC 60x address to ROM Flash address mapping with 2 32 bit or 1 64 bit 3 20 PowerPC 60x bus to ROM Flash access tim ing using 32 64 bit devices 3 10 PowerPC 60x bus to ROM Flash access tim ing using 8 bit devices 3 10 PowerPC 60x to ROM Flash address map ping when ROM Flash is 16 bits wide 8 bits per Falcon 3 19 PowerPC 60x to ROM Flash address map ping with 2 8 bit devices 3 19 Power Up Reset status bit 3 45 PPC address mapping 2 5 contention with PCI 2 44 PPC Arbiter debug functions 2 16 parking modes 2 16 prioritization schemes 2 16 PPC Arbiter Control Register 2 71 PPC Bus interface limits 2 5 PPC Bus Address Space 2 19 PPC bus arbiter 2 15 PPC Bus features 2 1 PPC Bus Interface 2 1 PPC bus timer 2 17 PPC devices as little endian 2 39 when Big Endian 2 38 PPC Error Address Register 2 8 1 PPC Error Attribute Register EATTR 2 82 PPC Error Enable Register 2 77 PPC Error Status Register 2 79 PPC Master Bug Hog 2 14 doing prefetched reads 2 13 read ahead mode 2 12 PPC master 2 10 PPC Parity 2 17 PPC registers 2 66 PPC slave role 2 7 PPC Slave Address 3 Register 2 85 PPC Slave Address Register 2 86 PPC Slave Offset Attribute 0 1 and 2 Reg isters 2 87 PPC60x Data Parity 3 13 PREP Memory Map Universe II PCI Register Values 1 17 PREP memory map PHB PCI Register Values 1 16 PHB Register values 1 11 PREP memory map examp
37. Programming a be 2 61 octo piss 2 61 e E 2 62 cv i MTM M 2 63 Totermrocessor ap ope em dod ebd dois 2 63 Dynamically Changing I O Interrupt Configuration 2 63 Biel WEP Bel 2 63 Interrapt Acknowledge Registers xis 2 64 EET 2 64 Ciment Task Priority 2 64 Ae E 2 64 amp Interrupt epis 2 65 j oui E 2 65 A 0 A 2 66 Vendor TEE Deviee IO cic opone tin SE IAS LEO 2 67 Revision IO pec 2 68 General Control Status Feature Registers 2 69 Arbite PCI Arbiter Control Registers retener inn 2 71 Hardware Control Status Prescaler Adjust Register 2 74 Brror Test Error Enable iiu ouest 2 77 PPC Error Stale eo 2 79 PPC Error Address Beg stet Laune RP 2 81 PPC Error Attribute
38. READ I2C STATUS REG Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 7 Programming Sequence for I2C Current Address Read 3 28 Computer Group Literature Center Web Site Functional Description 2 Page Write The PC page write is initiated the same as the PC byte write but instead of sending a stop sequence after the first data word the PC master controller will transmit more data words before a stop sequence is generated The first step in the programming sequence should be to test the i2_cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the i2_start and i2_enbl bits in the PC Control Register and then writing the device address bits 7 1 and write bit bit 0 0 to the Transmitter Data Register 12 cmplt bit will be automatically clear with the write cycle to the Transmitter Data Register The Status Register must now be polled to test the 12 cmplt and 12 ackin bits The i2 cmplt bit becomes set when the device address and write bit have been transmitted and the i2 ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the initial word address will be loaded into the C Transmitter Data Register to be transmitted to the slave device Again i2 cmplt and i2 ackin b
39. acit ier boe ede 3 54 Table 3 12 rom TV and rom b ry encoding esitise er er nra nie 3 54 Table 3 13 Read Write to 3 55 Table 3 14 ROM Block B Size Encoding cr enr 3 57 Table 3 15 ROM Speed Bit Encodings Licinii Eois htt Sonido 3 58 Table 3 16 Encoding TUI 3 69 Table TT au e 3 69 Table 3 18 Deriving tras trp trcd and trc Control Bit Values from SPE 3 78 Table 3 19 Programming SDRAM SIA ie rentia 3 81 Table 3 20 Address Lists for Different Block Size Checks 3 85 Table 3 21 Syndrome Codes Ordered by Bit m Error eee ete 3 86 Table 3 22 Single Bit Errors Ordered by Syndrome 3 87 Table 4 1 Universe TT Resister My Hb 4 9 Table 5 1 Hawk Arbitration Assignments sis ee tnnt ssves tht trant 5 1 Table 5 2 MPIC Intertupt AsSIERDODEs aeneae 5 3 Table 5 3 PIB PCEISA Interr pt 5 2 5 6 Table 5 4 Reset Sources and Devices Affected iuis eic errore rio tertie 5 8 Table 5 5 N
40. care to the C Transmitter Data Register The PC Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will relinquish the ASIC master s possession of the bus http www motorola com computer literature 3 25 System Memory Controller SMC DEVICE ADDR WORD ADDR x DEVICE ADDR M wl A M B SDA START S nC C START S D K K B DATA x A N O STOP K A i k ACK and DATA from Slave Device BEGIN 1 READ 2 STATUS REG LOAD 09 START CONDITION CONTROL REG LOAD DEVICE ADDR WR TO TRANSMITTER DATA REG READ 2 STATUS REG 4 READ I2C STATUS REG N N Y LOAD DUMMY DATA TO LOAD WORD ADDR x TO TRANSMITTER DATA REG TRANSMITTER DATA REG READ I2C STATUS REG lt lt READ 2 STATUS REG MPLT DATIN 12 N Y READ I2C RECEIVER DATA REG LOAD 09 REPEATED START CONDITION TO I2C CONTROL REG LOAD 05 STOP CONDITION TO CONTROL REG LOAD DEVICE ADDR RD BIT TO TRANSMITTER DATA REG LOAD DUMMY DATA TO TRANSMITTER DATA REG READ I2C STATUS REG Stop condition should be generate
41. includes general reference information The VPD identifies board information that may be useful during board initialization configuration and verification Appendix B Related Documentation includes all documentation related to the MVME240x Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW164 2900 S Diablo Way Tempe Arizona 85282 xxii You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements Manual Terminology Throughout this manual a convention is used which precedes data and address parameters by a character identifying the numeric format as follows dollar specifies a hexadecimal character percent specifies a binary number amp ampersand specifies a decimal number For example 12 is the decimal number twelve and 12 is the decimal number eighteen Unless otherwise specified all address references are hexadecimal An asterisk following the signal name for signals which are level significant denotes tha
42. rro SHEER E Rea 4 0 CHAPTER 5 Programming Details adr Epic cade asa 5 1 PEE PMN UMD xorg E lise bes L on upto onn 5 1 I termopt E iA imde tip aeq Rd 5 2 e 5 3 5235 Ine HD BS 5 4 EIL od ENERO 5 7 zoo T o 5 7 DONI e E E DM 5 7 P i LEM 5 8 Universe II Chip Problems after a PCI Reset recente 5 8 Eror Noniiication and Handling seio otc 5 9 BRIDE IS EE MEME MM 5 10 Processor Memory DOOTXID tomi aieo cpi r 5 13 MIP ee ai I ERBEN Eus 5 13 PECO du uu ME 5 13 5 13 I ELITSE E E E 5 13 I eL s rp D 5 14 Universe IM s DBVolv eel dvi pma st inp 5 14 OTE Be crepat epe S ase es uius 5 14 ROM F lash EINE UD EE 5 15 APPENDIX A MVME2400 VPD Reference Information Product Data CV PD Introduction 1 oer DUREE ER IE ERR EAE 1 Data Defmitlolis EE 1 VPD Data Definitions Product C
43. 1 13 register values 1 9 Universe II PCI Register Values 1 14 CHRP memory map example 1 7 CLK FREQUENCY 3 44 CLK Frequency Register SMC 3 44 clock frequency 3 44 combining merging and collapsing 2 28 command types 2 23 from PCI Master 2 27 PPC slave 2 8 CONFIG ADDRESS Register 2 100 CONFIG DATA Register 2 103 configuration options Hawk 3 34 configuration registers 2 19 configuration requirements Hawk 3 34 configuration type as used by PHB 2 32 contention between PCI and PPC 2 44 contention handling explained PHB 2 45 control bit descriptions 3 38 control bit definition x conventions manual ix Critical Word First CWF as supported by PCI Master 2 27 CSR accesses SMC 3 34 CSR architecture SMC 3 35 CSR base address 3 35 CSR reads and writes 3 35 CWEF burst transfers explained 2 27 cycle types SMC 3 15 D data discarded from prefetched reads 2 13 data parity PPC 2 17 Data Parity Error Address Register SMC 3 60 Data Parity Error Log Register SMC 3 59 Data Parity Error Lower Data Register SMC 3 61 Data Parity Error Upper Data Register SMC 3 60 data throughput PPC Slave to PCI Master 2 9 data transfer PPC Master rates 2 10 relationship between PCI Slave and PPC60x bus 2 11 data transfers SMC 3 13 decimal number ix IN 2 Computer Group Literature Center Web Site decoder priorities 2 21 decoders address PCI to PPC 2 5 for PCI to PPC addressing 2 19 PPC to PCI 2 7 default PCI me
44. 1 24 Computer Group Literature Center Web Site ISA Local Resource Bus ISA Local Resource Bus W83C553 PIB Registers The PIB contains ISA Bridge I O registers for various functions These registers are actually accessible from the PCI bus Refer to the W83C553 Data Sheet for details UART 16550 compatible provides the MVME2400 series with an asynchronous serial port Refer to the TL16C550 Data Sheet for additional details and programming information The following table shows the mapping of the 16550 registers within the MVME2400 series s ISA I O space beginning at address Ox2f8 Table 1 15 16550 Access Registers ISA I O Address Function 0000 02f8 Receiver Buffer Read Transmitter Holding Write 0000 03f9 Interrupt Enable 0000 03fa Interrupt Identification Read FIFO Control Write 0000 03fb Line Control 0000 03fc MODEM control 0000 03fd Line Status 0000 03fe MODEM Status 0000 03ff Scratch http www motorola com computer literature 1 25 Board Description and Memory Maps General Purpose Software Readable Header SRH Switch S3 Switch S3 is an eight pole single throw switch with software readable switch settings These settings can be read as a register at ISA I O address 801 hexadecimal Each switch pole can be set to either logic 0 or logic 1 A logic 0 means the switch is in the ON position for that particular bit A logic 1 means the switch is in the
45. 1 6 Memoty Maps 1 12 bislzo rS appe 1 18 System Contiotration Intonation teo nra Ha 1 23 TSA Local Resource di T n 1 25 33533 tree IARE FERRI 1 25 T 1 25 General Purpose Software Readable Header SRH Switch 53 1 26 NVRAM RTC amp Watchdog Timer Registers eee 1 26 VME ung e 1 27 LMISIG Control E AE E Rondo 1 28 LM SIG Status REGIST 1 29 Location Monitor Upper Base Address 1 30 Location Monitor Lower Base Address Register 1 31 Semaphore Register RT 1 31 Semaphore Register 2 oerte nbi FOR 1 32 VME Geographical Address Register VGAR esses 1 32 Emulated 78536 Registers and Port Pins rre ts 1 32 F CAO Port PINS T 1 33 vii DEC pantie pk Bo eT oe 1 34 CHAPTER2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller M nnn 2 1 i t 2 1 j po f M 2 1 dnos db 2 3 Functional
46. 2 PPC Master Transaction Profiles and Starting Offsets Start Offset that is from 0x00 0x20 0x40 etc Ox 00 gt Ox 07 Write Profile Burst 0x00 Burst 0x20 Read Profile Burst 0x00 Burst 0x20 Notes Most efficient 08 gt Ox 0f Single 0x08 Single 0x10 Single 0x18 Burst 0x20 Burst 0x00 Burst 0x20 Discard read beat 0x00 10 gt Ox 17 Single 0x10 Single 0x18 Burst 0x20 Burst 0x00 Burst 0x20 Discard read beat 0x00 and 0x08 18 gt 0 1 Single 0x18 Burst 0x20 Single 0x18 Burst 0x20 While the PCI Slave is filling the PCI FIFO with write data the PPC Master can be moving previously posted write data onto the PPC60x bus In general the 60 bus is running at a higher clock rate than the PCI bus which means the PCI bus can transfer data at a continuous uninterrupted burst while the 60 bus transfers data in distributed multiple bursts The PHB write posting mechanism has been tuned to create the most efficient possible data transfer between the two busses during typical operation It is conceivable that some non typical conditions could exist that would upset the default write post tuning of the PHB For example if a PPC60x master is excessively using 60 bus bandwidth then the additional latency associated with obtaining ownership of the 60 bus might caus
47. 5 PCI FIFO 2 26 used with PCI Slave 2 22 PCI Interface 2 1 purpose 2 19 PCI interface 2 18 PCI Interface features 2 1 PCIInterrupt Acknowledge Register 2 83 PCI Master explained 2 4 PCI master 2 26 PCI master command codes 2 27 PCI memory maps 1 12 PCI PREP memory map 1 15 PCI registers 2 91 PCIrequest speculative 2 47 PCI Slave disconnect scenarios 2 24 with PCI Master 2 26 PCI slave 2 22 PCI Slave Address 0 1 2 and 3 Registers 2 08 PCI Slave Attribute Offset 0 1 2 and 3 Registers 2 99 PCI slave response command types 2 23 PCI spread I O address translation 2 31 PCI to MPC address decoding 2 20 PCI to MPC address translation 2 21 PCI write posting 2 26 PCI Bthernet 5 13 PCI graphics 5 14 PCI SCSI 5 13 performance SMC 3 6 PHB viii 2 1 address mapping 2 5 configuration type 2 32 contention handling explained 2 45 endian conversion 2 38 retuning write thresholds 2 11 spread I O addressing 2 31 watchdog timers 2 42 PHB Configuration registers as mapped within PCI Configuration space 2 19 PHB errors types described 2 41 PHB PCI Register Values CHRP memory map 1 13 PREP Memory Map 1 16 PHB Register Values CHRP Memory Map 1 9 IN 6 Computer Group Literature Center Web Site PHB Register values PREP Memory Map 1 11 PHB registers 2 40 PHB Detected Errors Destination Register 2 119 PHB Detected Errors Vector Priority Regis ter 2 118 PIB 8259 interrupts 5 4 PIB interrupt handler block diagram 5 5
48. COUNT 3 50 scbO scbl 3 51 scien 3 45 3 47 scof 3 50 scrub counter 3 51 Scrub Write Enable control bit 3 51 Scrub Refresh Register SMC 3 51 SDRAM Operational Method for Sizing 3 82 sizing 3 76 speed attributes 3 75 SDRAM Attributes Register SMC 3 41 SDRAM Base Address Register http www motorola com computer literature IN 9 lt moz xXmoz Index SMC 3 66 SDRAM Base Address Enable 3 76 SDRAM Base Register SMC 3 43 SDRAM block organization 3 9 SDRAM Control Registers Initialization Example 3 77 SDRAM Enable and Size Register SMC 3 65 SDRAM registers initializing 3 75 SDRAM Speed Attributes Register SMC 3 68 SDRAM speeds 3 7 Semaphore Register 1 1 31 Semaphore Register 2 1 32 Serial Presence Detect SPD 3 76 Seven Segment Display Register 1 27 sien 3 48 Single Bit Error Counter 3 50 single word definition x single beat reads writes 3 7 single bit error 3 16 single bit errors ordered by syndrome code 3 87 sizing SDRAM 3 76 small endian x SMC 32 Bit Counter 3 71 address parity 3 13 Address Parity Error Address Register 3 71 Address Parity Error Log Register 3 70 block diagram 3 2 cache coherency 3 14 CLK Frequency Register 3 44 CSR Accesses 3 34 cycle types 3 15 data parity 3 13 Data Parity Error Upper Data Register 3 60 data transfers 3 13 ECC Control Register 3 45 Error Address Register 3 50 error correction 3 15 Error Logger Register 3 49 error logging 3 17 External Register Se
49. Controller P66M PCI66 MHz This bit indicates the PHB is capable of supporting a 66 67 MHz PCI bus FAST Fast Back to Back Capable This bit indicates that the PHB is capable of accepting fast back to back transactions with different targets DPAR Data Parity Detected This bitis set when three conditions are met 1 the PHB asserted PERR_ itself or observed PERR_ asserted 2 the PHB was the PCI master for the transfer in which the error occurred 3 the PERR bit in the PCI Command Register is set This bit is cleared by writing it to 1 writing 0 has no effect SELTIM DEVSEL Timing This field indicates that the PHB will always assert DEVSEL_ as a medium responder SIGTA Signaled Target Abort This bit is set by the PCI slave whenever it terminates a transaction with a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVTA Received Target Abort This bit is set by the PCI master whenever its transaction is terminated by a target abort It is cleared by writing it to 1 writing a 0 has no effect RCVMA Received Master Abort This bit is set by the PCI master whenever its transaction except for Special Cycles is terminated by a master abort It is cleared by writing it to 1 writing a 0 has no effect SIGSE Signaled System Error This bit is set whenever the PHB asserts SERR_ It is cleared by writing it to 1 writing 0 has no effect RCVPE Detected Parity Error This bit is set whe
50. Details Endian Issues The MVME2400 series supports both Little Endian software and Big Endian software Because the PowerPC processor is inherently Big Endian PCI is inherently Little Endian and the VMEbus is Big Endian things do get rather confusing The following figures shows how the MVME2400 series handles the Endian issue in Big Endian and Little Endian modes 5 10 Computer Group Literature Center Web Site Endian Issues Big Endian PROGRAM 60X System Bus Hawk N way Byte Swap Big Endian Little Endian PCI Local Bus Universe Il N way Byte Swap Little Endian 4 Big Endian VMEbus 1898 9609 Figure 5 3 Big Endian Mode http www motorola com computer literature 5 11 Programming Details Little Endian PROGRAM Little Endian 4 Big Endian EA Modification XOR 60X System Bus Hawk EA Modification Big Endian Little Endian PCI Local Bus Universe Il N way Byte Swap Little Endian 4 Big Endian 1899 9609 Figure 5 4 Little Endian Mode 5 12 Computer Group Literature Center Web Site Endian Issues Processor Memory Domain The MPC604 processor can operate in both Big Endian and Little Endian mode However it always treats the external processor memory bus as Big Endian by performing address rearrangement and reordering when running in Little Endian mode The MPIC registers inside the Hawk the registers inside th
51. Hawk s SDRAM buffer control signals cause the buffers to drive toward the Hawk during power up reset Other configuration information is needed by software to properly configure the Hawk s control registers This information can be obtained from devices connected to the I C bus Programming Model CSR Architecture The CSR Control and Status Register set consists of the chip s internal register set and its external register set The base address of the CSR is hard coded to the address FEF80000 or FEF90000 if the RD 5 pin is low at reset Accesses to the CSR are performed on the upper 32 bits of the PPC60x data bus Unlike the internal register set data for the external register set can be writen and read on both the upper and lower halves of the PPC60x data bus CSR read accesses can have a size of 1 2 4 or 8 bytes with any alignment CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned Register Summary Table 3 9 shows a summary of the internal and external register set http www motorola com computer literature 3 35 System Memory Controller SMC Table 3 9 Register Summary BID e le emite eee Eam ESESERASSASAREASS FEF80000 VENDID DEVID FEF80
52. Interrupt Controller RELOAD Reload This field is written with a value that will be used to reload the timer The RELOAD field may only be modified on the second step of a successful two step arming process WDTXxSTAT Registers Address WDTISTAT FEFF0064 WDT2STAT FEFFO06C a nS SS oS SA SS SS WDTxSTAT Name COUNT Operation R R Reset 00 00 FF The Watchdog Timer Status Registers WDTISTAT and WDT2STAT are used to provide status information from the watchdog timer functions within the PHB The field within WDTxSTAT registers is defined as follows COUNT Count This read only field reflects the instantaneous counter value of the WDT General Purpose Registers Address GPREGO Upper FEFF0070 GPREGO Lower SFEFF0074 GPREGI Upper SFEFF0078 GPREGI Lower SFEFF007C Bit 11 1 1 1 1 1111222222222 2 3 3 012 34 5678090 12 3 4 5 8 9 O 1 2 3 4 5 6 7 8 9 O 1 Name GPREGx Operation R W Reset 00000000 2 90 Computer Group Literature Center Web Site Registers The General Purpose Registers 0 GPREG2 and are provided for inter process message passing or general purpose storage They do not contr
53. Mbyte of ROM FLASH Bank A appears at this range after a reset if the rom b rv control bit is cleared If the rom b rv control bit is set then this address range maps to ROM FLASH Bank B Processor CHRP Memory Map The following table shows a recommended CHRP memory map from the point of view of the processor Table 1 3 CHRP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top dram dram size System Memory onboard SDRAM 1 2 4000 0000 3G 48M PCI Memory Space 3 4 8 4000 0000 to FCFF FFFF FD00 0000 FDFF FFFF 16M Zero Based PCI ISA Memory Space 3 8 mapped to 00000000 to 00FFFFFF 0000 FE7F FFFF 8M Zero Based PCI ISA I O Space 3 5 8 mapped to 00000000 to 007 FFFFF FE80 0000 FEF7 FFFF 7 5M Reserved FEF8 0000 FEF8 FFFF 64K SMC Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF 64K PHB Registers 9 http www motorola com computer literature 1 7 Board Description and Memory Maps Table 1 3 CHRP Memory Map Example Continued Processor Address Size Definition Notes Start 00 0000 FF7F 8M ROM FLASH Bank A 1 6 80 0000 FF8F FFFF IM ROM FLASH Bank B 1 6 FF90 0000 FFEF FFFF 6M Reserved FFFO 0000 FFFF FFFF IM ROM FLASH Bank A or Bank B 7 Notes 1 Programmable via the Hawk ASIC For 2400 series RAM size is li
54. Modify Memory Read Line Memory Write Write with Kill Burst 00110 Memory Write and Invalidate Memory Write Write with Flush Single Beat 00010 Memory Write and Invalidate The PPC master incorporates an optional operating mode called Bus Hog When Bus Hog is enabled the PPC master will continually request the PPC bus for the entire duration of each PCI transfer When Bus Hog is not enabled the PPC master will structure its bus request actions according to the requirements of the FIFO The Bug Hog mode was primarily designed to assist with system level debugging and is not intended for normal modes of operation It is a brute force method of guaranteeing that all PCI to PPC60x transactions will be performed without any intervention by host CPU transactions 2 14 Computer Group Literature Center Web Site Functional Description N Caution PPC Arbiter Caution should be exercised when using this mode since the over generosity of bus ownership to the PPC master can be detrimental to the host CPU s performance The Bus Hog mode be controlled by the bit within the GCSR The default state for is disabled PHB has an internal 60 bus arbiter The use of this arbiter is optional If the internal arbiter 1s disabled then the PHB must be allowed to participate an externally implemented PPC60x arbitration mechanism The selection of either internal or external PPC arbitra
55. Monitor Lower Base Address 0000 1004 VMEbus Semaphore Register 1 0000 1005 VMEbus Semaphore Register 2 0000 1006 VMEbus Geographical Address Status These registers are described in the following sub sections LM SIG Control Register The LM SIG Control Register is an 8 bit register located at ISA I O address x1000 This register provides a method to generate software interrupts The Universe II ASIC is programmed so that this register can be accessed from the VMEbus to generate software interrupts to the processor s REG LM SIG Control Register Offset 1000 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SDO FIELD SET SET SET SET CLR CLR CLR CLR SIGI SIGO LMI LMO SIGI SIGO LMI LMO OPER WRITE ONLY RESET 0 0 0 0 0 0 0 0 SET SIG1 Writing a 1 to this bit will set the SIGI status bit SET SIGO Writing a 1 to this bit will set the SIGO status bit 1 28 Computer Group Literature Center Web Site ISA Local Resource Bus SET LMI1 Writing a 1 to this bit will set the status bit SET LMO0 Writing a 1 to this bit will set the LMO status bit CLR SIG1 Writing a 1 to this bit will clear the SIGI status bit CLR 5160 Writing a 1 to this bit will clear the SIGO status bit CLR LMI Writing a 1 to this bit will clear status bit CLR LMO0 Writing a 1 to this bit will clear the LMO status bit LM SIG Status Register The LM SIG Status Register is an 8 bit register located at ISA I O add
56. PCIO CONN2 PCI PMC bus 0 connector 2 present 2 PCO PCIO CONN3 PCI PMC bus 0 connector 3 present 3 PCO_PCIO_CONN4 PCI PMC bus 0 connector 4 present 4 PCO PCII CONNI PCI PMC bus 1 connector 1 present 5 PCO CONN2 PCI PMC bus 1 connector 2 present 6 PCO CONN3 PCI PMC bus 1 connector 3 present 7 PCO CONNA PCI PMC bus 1 connector 4 present 8 PCO ISA CONNI ISA bus connector 1 present 9 PCO ISA CONN2 ISA bus connector 2 present http www motorola com computer literature A MVME2400 VPD Reference Information Table A 2 MVME2400 Product Configuration Options Data Continued Bit Number Bit Mnemonic Bit Description 10 PCO ISA CONN3 ISA bus connector 3 present 11 PCO_ISA_CONN4 ISA bus connector 4 present 12 PCO EIDEI CONNI IDE EIDE device 1 connector 1 present 13 PCO EIDEI CONN2 IDE EIDE device 1 connector 2 present 14 PCO EIDE2 CONNI IDE EIDE device 2 connector 1 present 15 EIDE2 CONN2 IDE EIDE device 2 connector 2 present 16 PCO CONN Ethernet device 1 connector present 17 2 CONN Ethernet device 2 connector present 18 CONN Ethernet device 3 connector present 19 PCO ENET4 CONN Ethernet device 4 connector present 20 PCO 5 5 CONN SCSI device 1 connector present 21 PCO SCSD CONN SCSI device 2 connector present 22 SCSI3 CONN SCSI device 3 connecto
57. PPC bus This offset allows PPC resources to reside at addresses that would not normally be visible from PCI CONFIG ADDRESS Register The description of the CONFIG ADDRESS register is presented in three perspectives from the PCI bus from the PPC Bus in Big Endian mode and from the PPC bus in Little Endian mode Note view from the PCI bus is purely conceptual since there is no way to access CONFIG ADDRESS register from the PCI bus 2 100 Computer Group Literature Center Web Site Registers Conceptual perspective from the PCI bus Offset CFB CFA CF9 CF8 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 11 1 1 1 1 1 1 1 1 O 9 8 7 6 5 432109876543 109875654232 10 Name CONFIG ADDRESS BUS DEV FUN REG Operation R R W R W R W R W uu Reset 00 00 00 0 00 oo Perspective from the PPC bus in Big Endian mode Offset 8 9 CFA CFB Bit DH 111 1 1 11 11 122 22 222 2 2 2 3 3 012131415 6 7 81 910121345 6 7 8 9 0 1 2 3 4 5 6 7 8 9 OF 1 Name CONFIG_ADDRESS REG DEV FUN BUS gt Operation R W w la R W R W R W Z R Rese
58. ROM Flash 3 17 four beat reads writes 3 6 functional description 1 5 Hawk PHB 2 4 http www motorola com computer literature IN 3 lt moz xXmoz Index SMC 3 6 Universe II 4 2 G General Control Register SMC 3 40 General Control Status Feature Registers 2 69 general information Universe II 4 1 General Purpose Registers 2 90 general purpose software readable header 1 26 general purpose software readable header J17 1 26 generating PCI configuration cycles 2 32 generating PCI cycles 2 30 generating PCI interrupt acknowledge cycles 2 34 generating PCI memory and I O cycles 2 30 generating PCI special cycles 2 33 Global Configuration Register 2 108 H half word definition x Hawk address parity 3 13 configuration options 3 34 data parity 3 13 ECC Codes 3 86 error notification and handling 5 9 I2C Byte Write 3 22 I2C Current Address Read 3 27 I2C Interface 3 21 I2C Page Write 3 29 I2C Random Read 3 25 I2C Sequential Read 3 31 programming details 5 1 programming ROM Flash devices 3 74 writing to the control registers 3 74 Hawk block diagram 2 3 Hawk MPIC interrupts 5 3 Hawk MPIC control registers 2 22 Hawk s DEVSEL pin as criteria for PHB config mapping 2 19 Hawk s I2C bus 3 76 Hawk s PCI arbiter priority schemes 2 35 Hawk s SMC overview 3 1 Header Type Register 2 95 hexadecimal character ix T O Base Register MPIC 2 96 I2C Byte Write Hawk 3 22 I2C Clock Prescaler R
59. SIETE EEIE TETEE EE AEE Petes CHES eee cea rae ee pa genera a D es ead a qr CC MM i PCI Bus Slave Channel gt PCI x PCI gt posted writes FIFO VMEbus BUS Slave coupledreadlogic Master i E eres m a i i a a a E E a a A a a a E P B rca cali are en i Interrupt Channel 1 Interrupt Handler a VME n r Interrupts Interrupter Interrupts 7 i eo EI o LIENE ein ea a ea Register Channel lt 1894 9609 Figure 4 1 Architectural Diagram for the Universe II http www motorola com computer literature 4 3 Universe II VMEbus to PCI Chip VMEbus Interface Universe II as VMEbus Slave The Universe II VME Slave Channel accepts all of the addressing and data transfer modes documented in the VME64 specification except A64 and those intended to support 3U applications that is 40 and MD32 Incoming write transactions from the VMEbus may be treated as either coupled or posted depending upon the programming of the VMEbus slave image Refer to VME Slave Images in the Universe II User Manual listed in Appendix B Related Documentation With posted write transactions data is written
60. SRC 9 DESTINATION REGISTER 10130 INT SRC 10 VECTOR PRIORITY REGISTER 10140 INT SRC 10 DESTINATION REGISTER 10150 INT SRC 11 VECTOR PRIORITY REGISTER 10160 INT SRC 11 DESTINATION REGISTER 10170 INT SRC 12 VECTOR PRIORITY REGISTER 10180 INT SRC 12 DESTINATION REGISTER 10190 INT SRC 13 VECTOR PRIORITY REGISTER 101a0 2 106 Computer Group Literature Center Web Site Registers Table 2 19 MPIC Register Map Continued 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 Off 1098765 4321098765 4 3 21109 8 7 6 5 413 2 1 0 INT SRC 13 DESTINATION REGISTER 101b0 INT SRC 14 VECTOR PRIORITY REGISTER 101c0 INT SRC 14 DESTINATION REGISTER 101d0 INT SRC 15 VECTOR PRIORITY REGISTER 101 0 INT SRC 15 DESTINATION REGISTER 101f0 PHB DETECTED ERRORS VECTOR PRIORITY REGISTER 10200 PHB DETECTED ERRORS DESTINATION REGISTER 10210 IPI 0 DISPATCH REGISTER PROC 0 20040 IPI 1 DISPATCH REGISTER PROC 0 20050 IPI 2 DISPATCH REGISTER PROC 0 20060 IPI 3 DISPATCH REGISTER PROC 0 20070 CURRENT TASK PRIORITY REGISTER PROC 0 20080 IACK REGISTER 200a0 EOI REGISTER 200b0 0 DISPATCH REGISTER PROC 1 21040 1 DISPATCH REGISTER PROC 1 21050 IPI 2 DISPATCH REGISTER PROC 1 21060 IPI 3 DISPATCH REGISTER PROC 1 21070 CURRENT TASK PRIORITY REGISTER
61. Slave Image 1 Base Address Register VSII BS FIC VMEbus Slave Image 1 Bound Address Register VSI1 BD F20 VMEbus Slave Image 1 Translation Offset VSII TO F24 Universe II Reserved F28 VMEbus Slave Image 2 Control VSD F2C VMEbus Slave Image 2 Base Address Register VSD BS F30 VMEbus Slave Image 2 Bound Address Register VSI2 BD F34 VMEbus Slave Image 2 Translation Offset VSD TO F38 Universe II Reserved F3C VMEbus Slave Image 3 Control VSI3 CTL F40 VMEbus Slave Image 3 Base Address Register VSI3 BS F44 VMEbus Slave Image 3 Bound Address Register VSI3 BD F48 VMEbus Slave Image 3 Translation Offset VSI3 TO F6C Universe II Reserved F70 VMEbus Register Access Image Control Register VRAI CTL F74 VMEbus Register Access Image Base Address VRAI BS F78 Universe II Reserved F7C Universe II Reserved F80 VMEbus CSR Control Register VCSR CTL F84 VMEbus CSR Translation Offset VCSR TO 4 12 Computer Group Literature Center Web Site Registers Universe II Control and Status Registers UCSR Table 4 1 Universe Register Map Continued Offset Register Name F88 VMEbus AM Code Error Log V_AMERR F8C VMEbus Address Error Log VAERR F90 FEC Universe Reserved FFO VME CR CSR Reserved FF4 VMEbus CSR Bit Clear Register VCSR_CLR FF8 VMEbus CSR Bit Set Register VCSR_SET FFC VMEbus CSR Base Address Register VCSR_BS Register space marked as Reserved should not be overwritten Unimplemented regist
62. The Off field is the address offset from the base address of the MPIC registers in the PPC IO or PPC MEMORY space Note that this map does not depict linear addressing The PCI SLAVE of the PHB has two decoders for generating the MPIC select These decoders will generate a select and acknowledge all accesses which are in a reserved 256K byte range If the index into that 256K block does not decode a valid MPIC register address the logic will return 00000000 The registers are 8 16 or 32 bits accessible 2 104 Computer Group Literature Center Web Site Registers Table 2 19 MPIC Register Map 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 11 1 1 1 Off 1098765 4321098765 4 3 21109 8 7 6 5 4 3 2110 FEATURE REPORTING REGISTER 0 01000 GLOBAL CONFIGURATION REGISTER 0 01020 MPIC VENDOR IDENTIFICATION REGISTER 01080 PROCESSOR INIT REGISTER 01090 IPIO VECTOR PRIORITY REGISTER 010a0 VECTOR PRIORITY REGISTER 010b0 IPI2 VECTOR PRIORITY REGISTER 010c0 IPI3 VECTOR PRIORITY REGISTER 010d0 SP REGISTER 010e0 TIMER FREQUENCY REPORTING REGISTER 010f0 TIMER 0 CURRENT COUNT REGISTER 01100 TIMER 0 BASE COUNT REGISTER 01110 TIMER 0 VECTOR PRIORITY REGISTER 01120 TIMER 0 DESTINATION REGISTER 01130 TIMER 1 CURRENT COUNT REGISTER 01140 TIMER 1 BASE COUNT REGISTER 01150 TIMER 1 VECTOR PRIORITY REGISTER 0
63. The interruption would occur at a time past the latest qualified retry window and the PPC Slave would be unable to retry the transaction Therefore all burst write transactions will be posted regardless of the write posting attribute within the associated map decoder register If the PPC Slave is servicing a posted write transaction and the PPC FIFO can accept the transaction the assertion of AACK_ and TA will occur as soon as the PPC Slave decode logic settles out and the PPC bus protocol allows for the assertion If the PPC FIFO is full the PPC Slave will hold the processor with wait states AACK_ will not be asserted until there is room within the PPC FIFO to store the pending transaction The PPC slave divides PPC command types into three categories address only write and read If a command type is an address only and the address presented at the time of the command is a valid PHB address the PPC slave will respond immediately by asserting AACK The PHB will not respond to address only cycles where the address presented is not a PHB address The response of the PPC slave to command types is listed in the following table Table 2 1 PPC Slave Response Command Types PPC Transfer Type Transfer Transaction Encoding Clean Block 00000 Addr Only Flush Block 00100 Addr Only SYNC 01000 Addr Only Kill Block 01100 Addr Only EIEIO 10000 Addr Only 2 8 Computer Group Literature Center Web Site Funct
64. There is an Interrupt Selector IS for each processor The IS receives interrupt requests from the IPR If the interrupt request are from an external source they are qualified by the destination bit for that interrupt and processor If they are from an internal source they have been qualified The output of the IS will be the highest priority interrupt that has been qualified This output is the priority of the selected interrupt and its source identification The IS will resolve an interrupt request in two PHB clock ticks The IS also receives a second set of inputs from the ISR During the End Of Interrupt cycle these inputs are used to select which bits are to be cleared in the ISR Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Functional Description Interrupt Request Register IRR There is an Interrupt Request Register IRR for each processor The IRR always passes the output of the IS except during Interrupt Acknowledge cycles This guarantees that the vector which is read from the Interrupt Acknowledge Register is not changing due to the arrival of a higher priority interrupt The IRR also serves as a pipeline register for the two tick propagation time through the IS In Service Register ISR There is a In Service Register ISR for each processor The contents of the ISR is the priority and source of all interrupts which are in service The ISR receives a bit set command during I
65. Wait again for the 32 Bit Counter to increment at least 100 times before resuming accesses to SDRAM cl3 When cl3 is cleared the SMC assumes that the SDRAM runs with a CAS latency of 2 When cl3 is set the SMC assumes that it runs with a CAS_latency of 3 Computer Group Literature Center Web Site Programming Model Note Writing so as to change cl3 from 1 to 0 or vice versa causes the SMC to perform a mode register set operation to the SDRAM array The mode register set operation updates the SDRAM s CAS latency to match cl3 trc0 1 2 Together trc0 1 2 determine the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trc parameter These bits are encoded as follows Table 3 16 Trc Encoding trc0 1 2 Minimum Clocks for Trc 26000 8 26001 9 26010 10 26011 11 100 reserved 26101 reserved 20110 6 20111 7 tras0 1 Together tras0 1 determine the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its tRAS parameter These bits are encoded as follows Table 3 17 tras Encoding tras0 1 Minimum Clocks for tras 2000 4 01 5 10 6 11 7 http www motorola com computer literature 3 69 System Memory Controller SMC swr dpl swr dpl causes the SMC to always wait until four clocks after the write command portion of a single write before allowing a precharge to occur This function may
66. accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 bit counter see Detailed Register Bit Descriptions further on in this chapter to increment at least 100 times The wait period needs to happen during the envelope http www motorola com computer literature 3 41 System Memory Controller SMC ram a b c d en ram a b c d en enables 60x accesses to the corresponding block of SDRAM when set and disables them when cleared Note that ram e f g h en are located at SFEF800CO refer to the section on SDRAM Enable and Size Register Blocks E F G H further on in this chapter for more information They operate the same for blocks E H as these bits do for blocks A D ram a b c d siz0 3 These control bits define the size of their corresponding block of SDRAM Table 3 10 shows the block configuration assumed by the SMC for each value of ram siz0 ram 5173 Note that ram e f g h size0 3 are located at FEF800C0 They operate identically for blocks E H as these bits do for blocks A D Table 3 10 Block_A B C D E F G H Configurations ram a h Component Number of Block SDRAM siz0 3 Configuration SDRAM SIZE Technology Components I
67. and if the address falls within the specified range the access is passed on to the PCI An example of this is shown in Figure 2 2 PPC Bus Address 8 0 8 6 1 2 3 4 1516 31 M Decodeis gt lt XSADDx Register 17 0 8 019000 1 31 Figure 2 2 PPC to PCI Address Decoding There are no limits imposed by the PHB on how large of an address space a map decoder can represent There is a lower limit of a minimum of 64 KBytes due to the resolution of the address compare logic For each map there is an associated set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the PCI transfer characteristics 2 6 Computer Group Literature Center Web Site Functional Description PPC Slave Each map decoder also includes a programmable 16 bit address offset The offset is added to the 16 most significant bits of the PPC address and the result is used as the PCI address This offset allows PCI devices to reside at any PCI address independent of the PPC address map An example of this is shown in the following figure PPC Bus Address 8 0 8 0 1 2 9 4 1 A V PEE EN XSOFFx Register 9 00 0 al M Y PCI Bus Address 1 0 8 0 1 2 9 4 1 Figure 2 3 PPC to PCI Address Translation Care should be taken to assure that all programmable decoders decode unique address
68. are that all SDRAM accesses must have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 Bit Counter described further on in this chapter to increment at least 100 times The wait period needs to happen during the envelope RAM A B C D BASE These control bits define the base address for their block s SDRAM RAM A B C D BASE bits 0 7 8 15 16 23 24 3 correspond to PPC60x address bits 0 7 For larger SDRAM sizes http www motorola com computer literature 3 43 System Memory Controller SMC the lower significant bits of A B C D BASE are ignored This means that the block s base address will always appear at an even multiple of its size Remember that bit 0 is MSB Note E F G H BASE are located at FEF800C8 refer to the section on SDRAM Base Address Register Blocks They operate the same for blocks E H as these bits do for blocks A D Also note that the combination of RAM X BASE and ram x siz should never be programmed such that SDRAM responds at the same address as the CSR ROM Flash Externa
69. back to back transactions The PCI slave meets the first criteria of being able to successfully track the state of the PCI bus without the existence of an IDLE state between transactions The second criteria associate with signal turn around timing is met by default since the PCI Slave functions as a medium responder Latency The PCI slave does not have any hardware mechanisms in place to guarantee that the initial and subsequent target latency requirements are met Typically this is not a problem since the bandwidth of the PPC bus far exceeds the bandwidth of the PCI bus Exclusive Access The PCI Slave fully supports the PCI lock function From the perspective of the PPC bus the PHB enables a lock to a single 32 byte cache line When a cache line has been locked the PHB snoops all transactions on the PPC bus If a snoop hit happens the PHB retries the transaction Note that the retry is benign since there is no follow on transaction after the retry is asserted The PHB contiues to snoop and retry all accesses to the locked cache line until a valid unlock is presented to the PHB and the last locked cache line transaction is successfully executed Note that the PHB locks the cache line that encompasses the actual address of the locked transaction For example a locked access to offset 0x28 creates a lock on the cache line starting at offset 0x20 From the perspective of the PCI bus the PCI Slave locks the entire resource Any at
70. bit correspond to offset 3 from the location monitor base address This bit can only be cleared by a reset or by writing a 1 to the CLR control bit LMO status bit This bit can be set by either the location monitor function or the SET LMO control bit LMO correspond to offset 1 from the location monitor base address This bit can only be cleared by a reset or by writing a 1 to the CLR LMO control bit Location Monitor Upper Base Address Register The Location Monitor Upper Base Address Register is an 8 bit register located at ISA I O address x1002 The Universe II ASIC is programmed so that this register can be accessed from the VMEbus to provide VMEbus location monitor function REG Location Monitor Upper Base Address Register Offset 1002 BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SDO FIELD 15 14 13 12 11 10 9 8 R W RESET 0 0 0 0 0 0 0 0 VA 15 8 Upper Base Address for the location monitor function 1 30 Computer Group Literature Center Web Site ISA Local Resource Bus Location Monitor Lower Base Address Register The Location Monitor Lower Base Address Register is an 8 bit register located at ISA I O address x1003 The Universe II ASIC is programmed so that this register can be accessed from the VMEbus to provide VMEbus location monitor function REG Location Monitor Lower Base Address Register Offset 1003
71. com computer literature Board Description and Memory Maps PCI Memory Maps The PCI memory map is controlled by the PHB portion of the Hawk ASIC and the Universe II ASIC The PHB and the Universe II ASIC have flexible programming Map Decoder registers to customize the system to fit many different applications Default PCI Memory Map After a reset the PHB and the Universe II ASIC turn all the PCI slave map decoders off Software must program the appropriate map decoders for a specific environment PCI CHRP Memory Map The following table shows a PCI memory map of the MVME2400 series that is CHRP compatible from the point of view of the PCI local bus Table 1 7 PCI CHRP Memory Map PCI Address Size Definition Notes Start End 0000 0000 top dram dram size Onboard ECC DRAM 1 4000 0000 FFFF 3G 256M VMEbus A32 D22 Super Program 3 F000 0000 F7FF FFFF 128M VMEbus A32 D16 Super Program 3 F800 0000 FSFE FFFF 16M 64K VMEbus A24 D16 Super Program 4 F8FF 0000 F8FF FFFF 64K VMEbus A16 D16 Super Program 4 F900 0000 F9FE FFFF 16M 64K VMEbus A24 D32 Super Data 4 F9FF 0000 F9FF FFFF 64K VMEbus A16 D32 Super Data 4 FA000000 FAFEFFFF 16M 64K VMEbus A24 D16 User Program 4 FAFF 0000 FAFF FFFF 64K VMEbus A16 D16 User Program 4 FB000000 FBFEFFFF 16M 64K VMEbus A24 D32 User Data 4 FBFF 0000 FBFF FFFF 64K VMEbus A16 D32 User Data 4 Computer Gro
72. cycle 3 14 Computer Group Literature Center Web Site Functional Description ECC Error Correction Code The SMC performs single bit error correction and double bit error detection for SDRAM across 64 bits of data using 8 check bits No checking is provided for ROM Flash Cycle Types To support ECC the SMC always deals with SDRAM using full width 72 bit accesses When the PPC60x bus master requests any size read of SDRAM the SMC reads the full width at least once When the PPC60x bus master requests a four beat write to SDRAM the SMC writes all 72 bits four times When the PPC60x bus master requests a single beat write to SDRAM the SMC performs a full width read cycle to SDRAM merges in the appropriate PPC60x bus write data and writes full width back to SDRAM Error Reporting The SMC checks data from the SDRAM during single and four beat reads during single beat writes and during scrubs Table 3 6 shows the actions it takes for different errors during these accesses http www motorola com computer literature 3 15 System Memory Controller SMC Note that the SMC does not assert on double bit errors In fact the SMC does not have a TEA_ signal pin and it assumes that the system does not implement The SMC can however assert machine check on double bit error Table 3 6 Error Reporting Error Single Beat Four Single Beat Write Four
73. devices access to devices residing on the PCI Local Bus In the remainder of this chapter the PPC60x bus will be referred to as the bus and the PCI Local Bus as PCI PCI is a high performance 32 bit or 64 bit burst mode synchronous bus capable of transfer rates of 132 MByte sec in 32 bit mode or 264 MByte sec in 64 bit mode using a 33 MHz clock PPC Bus Interface Direct interface to MPC750 processor 64 bit data bus 32 bit address bus Four independent software programmable slave map decoders Multi level write post FIFO for writes to PCI Support for PPC bus clock speeds up to 100 MHz Selectable big or little endian operation 3 3 V signal levels PCIInterface Fully PCI Rev 2 1 compliant 32 bit addressing 32 or 64 bit data bus Support for accesses to all three PCI address spaces Multiple level write posting buffers for writes to the PPC bus 2 1 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Read ahead buffer for reads from the PPC bus Four independent software programmable slave map decoders Interrupt Controller MPIC compliant MPIC programming model Support for 16 external interrupt sources and two processors Supports 15 programmable Interrupt and Processor Task priority levels Supports the connection of an external 8259 for ISA AT compatibility Distributed interrupt delivery for external I O interrupts Multiprocessor interrupt control allowing any interru
74. if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem fem Austausch der Batterie Ersatznur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers CE Notice European Community Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class B EN50082 1 1997 Electromagnetic Compatibility Generic Immunity Standard Part 1 Residential Commercial and Light Industry System products also fulfill EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will m
75. indicates the number of SDRAM blocks that belong to an SPD 3 Obtain the CAS latency information for all blocks that are present to determine whether to set or to clear the c13 bit For each SDRAM block that is present a Check SPD byte 18 to determine which CAS latencies are supported b If aCAS latency of 2 is supported then go to step 3 Otherwise a CAS latency of 3 is all that is supported for this block c If a CAS latency of 2 is supported check SPD byte 23 to determine the CAS latency _2 cycle time If the CAS latency 2 http www motorola com computer literature 3 77 System Memory Controller SMC cycle time is less than or equal to the period of the system clock then this block can operate with a CAS latency of 2 Otherwise a CAS latency of 3 is all that is supported for this block If any block does not support a CAS latency of 2 then cl3 is to be set If all of the blocks support a CAS latency of 2 then the bit is to be cleared Do not update the bit at this point You will use the information from this step later 4 Determine the values to use for tras trp tred and trc The values to use for tras trp trcd and trc can be obtained from the SPD The tras bits determine the minimum tRAS time produced by the Hawk The trp bit determines the minimum tRP time produced by the Hawk etc Each set of bits should accommodate the slowest block of SDRAM The SPD parameters are specified in nanosecond
76. is enabled The priority scheme can be programmed by writing the field in the PCI Arbiter control register The default setting for priority scheme is fixed mode The Fixed mode holds each requestor at a fixed level in its hierarchy The levels of priority for each requestor is programmable by writing the HEIR field in the PCI Arbiter control register The following table describes all available settings for the HEIR field in fixed mode Table 2 10 Fixed Mode Priority Level Setting HEIR Priority Levels Setting Highest Lowest 000 PARB6 5 PARB4 PARB3 PARB2 PARBO HAWK 001 HAWK PARB6 5 PARB4 PARB3 PARB2 PARBI PARBO 010 PARBO HAWK PARB6 PARB5 PARB4 PARB3 PARB2 011 1 HAWK PARB6 PARB5 PARB4 PARB3 PARB2 100 PARB2 PARBO HAWK PARB6 PARB5 4 PARB3 101 PARB3 PARB2 PARBO HAWK PARB6 PARB5 PARB4 110 PARB4 PARB3 2 PARBI PARBO HAWK PARB6 PARBS 111 5 PARB4 PARB3 PARB2 PARBO HAWK PARB6 Notes 0007 is the default setting in fixed mode The HEIR setting only covers a small subset of all possible combinations It is the responsibility of the system designer to connect the request grant pair in a manner most beneficial to their design goals http www m
77. mcken 3 48 Memory Base Register 2 97 memory map processor CHRP 1 7 memory maps 1 6 mien 3 48 MK48T59 559 access registers 1 27 MPC address mapping 2 5 arbiter 2 15 MPC bus address space 2 19 bus interface 2 5 slave 2 7 MPC Slave Address 0 1 and 2 Registers 2 84 slave response command types 2 8 to PCI address decoding 2 6 MPC to PCI address translation 2 7 write posting 2 9 MPC604 processor memory domain 5 13 MPIC viii 2 1 interface with PHB 2 5 MPIC Registers 2 104 MPIC registers 2 104 MPIC s involvement 5 13 Multi Processor Interrupt Controller viii 2 1 MVME2300 series system block diagram 1 4 MVME2400 endian issues 5 10 interrupt handling 5 2 sources of reset 5 7 MVME2400 description 1 3 MVME2400 series http www motorola com computer literature IN 5 lt moz xXmoz Index programmable registers 1 1 MVME240x features 1 2 MVME2600 series interrupt architecture 5 2 N negation definition x NVRAM RTC amp Watchdog Timer Registers 1 26 overview 1 1 2 1 SMC 3 1 P parity 2 30 PCI Slave 2 25 PCI contention with PPC 2 44 PCI address mapping 2 19 PCI arbiter Hawk internal version 2 34 PCI arbitration Hawk 5 1 PCI arbitration assignments 5 1 PCI bus interface 4 5 PCI CHRP memory map 1 12 PCI Command Status Registers 2 93 PCI configuration access 1 11 PCI configuration register map 2 91 PCI domain 5 13 PCI expansion described 1
78. ranges since overlapping address ranges will lead to undefined operation The PPC slave provides the interface between the PPC bus and the PPC FIFO The PPC slave is responsible for tracking and maintaining coherency to the PPC60x processor bus protocol The actions taken by the PPC Slave to service a transaction are dependent upon whether the transaction is posted or compelled During compelled transactions such as a read or a non posted single beat write the PPC Slave will hold off asserting AACK until after the transaction has completed on the PCI bus This has the effect of removing all levels of pipelining during compelled PHB accesses The interdependency between the assertion of http www motorola com computer literature 2 7 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller AACK andTA allows the PPC Slave to assert a retry to the processor in the event that the transaction is unable to complete on the PCI side It should be noted that any transaction that crosses a PCI word boundary could be disrupted after only having a portion of the data transferred The PPC Slave cannot perform compelled burst write transactions The PPC bus protocol mandates that the qualified retry window must occur no later than the assertion of the first of a burst transaction If the PHB were to attempt a compelled linkage for all beats within a burst write there is a possibility that the transaction could be interrupted
79. rom b siz control bits are the size of ROM Flash for Block B They are encoded as shown in the following table Table 3 14 ROM Block B Size Encoding rom b siz BLOCK SIZE 20000 1Mbytes 001 2Mbytes 010 4Mbytes 20011 8Mbytes 26100 16Mbytes 26101 32Mbytes 20110 64Mbytes 111 Reserved rom b rv and rom a rv determine which if either of Blocks A and B is the source of reset vectors or any other access in the range SFFF00000 FFFFFFFF as shown in Table 3 12 rom b is initialized at power up reset to match the value on the pin rom b en When rom b en is set accesses to Block B ROM Flash in the address range selected by ROM B BASE are enabled When rom b en is cleared they are disabled rom b we When rom b we is set writes to Block B ROM Flash are enabled When rom b we is cleared they are disabled Refer back to Table 3 13 for more details http www motorola com computer literature 3 57 System Memory Controller SMC ROM Speed Attributes Registers Address FEF80060 Bit AI A en tlan Of ER co ALO A Aen co oof A oO o A AY en st Sa a Sa a Sa Re Sa Se A I A eoo eoe ee Name o Sis BB EE 2 0 EB EE Ss s s Operation READ ZERO READ ZERO READ ZERO 4 ea 24 l 4 Reset X X X Aud
80. sources There are also six other interrupt sources inside the MPIC two cross processor interrupts and four timer interrupts All ISA interrupts go through the 8259 pair in the PIB The output of the PIB then goes through the MPIC in the Hawk Refer to Chapter 2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller for details on the MPIC The following table shows the interrupt assignments for the MPIC on the MVME2400 series Table 5 2 MPIC Interrupt Assignments MPIC Edge Polarity Interrupt Source Notes IRQ Level IRQO Level High PIB 8259 1 IRQI N A N A Not used IRQ2 Level Low PCI Ethernet 3 IRQ3 Level Low Hawk WDTIO L resistor population option 4 Level Low Hawk WDT20_L resistor population option IRQS Level Low PCI VME INT 0 Universe II LINTO 2 3 IRQ6 Level Low PCI VME INT 1 Universe II LINT1 2 IRQ7 Level Low PCI VME INT 2 Universe II LINT2 2 IRQ8 Level Low PCI VME INT 3 Universe II LINT3 2 IRQ9 Level Low INTA PMC2 INTB PCIX INTA 3 IRQIO Level Low INTB PMC2 INTC PCIX INTB IRQ11 Level Low INTC PMC2 INTD PCIX INTC IRQ12 Level Low INTD PMC2 INTA PCIX INTD IRQ13 Level Low LM SIG Interrupt 0 3 IRQ14 Level Low LM SIG Interrupt 1 3 15 N A N A Not used http www motorola com computer literature 5 3 Programming Details No
81. that allow software to control certain functions and to monitor some status External Register Set The SMC has an external register chip select pin which enables it to talk to an external set of registers This interface is like the ROM Flash interface but with less flexibility It is intended for the system designer to be able to implement general purpose status control signals with this external set Refer to the Register Summary further on in this chapter for a description of this register set The SMC has a mode in which two of its pins become control register outputs When the SMC is to operate in this mode the External Register Set cannot be implemented The two control bits appear in the range where the External Register Set would have been had it been implemented Chip Configuration Some configuration options in the Hawk must be configured at power up reset time before software performs any accesses to it The Hawk obtains this information by latching the value on some of the upper RD signals just 3 34 Computer Group Literature Center Web Site Programming Model after the rising edge of the PURST signal pin A recommended way to control the RD signals during reset is to place pull up or pull down resistors on the RD bus If there is a set of buffers between the RD bus and the ROM Flash devices it is best to put the pull up pull down resistors on the far side of the buffers so that loading will be kept to a minimum The
82. the calculation of CRC 01 0x01 4F 02 0x02 54 03 0x03 4F 04 0x04 52 05 0x05 4F 06 0x06 4C 07 0x07 41 08 0x08 01 BINARY Size of VPD in bytes 09 0x09 00 10 0x0a 01 PACKET Product Identifier MVME2431 1 ASCII 11 0 0A 12 Ox0c 4D 13 Ox0d 56 14 0x0e 4D 15 OxOf 45 16 0x10 32 17 0x11 34 18 0x12 33 19 0x13 31 20 0x14 2D 2 0x15 31 22 0x16 02 PACKET Factory Assembly Number 01 W3394F01C ASCII http www motorola com computer literature A 9 A MVME2400 VPD Reference Information Table 5 VPD SROM Configuration Specification for 01 W3394F01 Continued Offset Value Field Type Description 23 0x17 0C 24 0x18 30 25 0x19 31 26 0x1a 2D 27 0x1b 57 28 0 1 33 29 0x1d 33 30 0 1 39 31 Ox1f 34 32 0x20 46 33 0x21 30 34 0x22 31 35 0x23 43 36 0x24 03 PACKET Serial Number ASCII 37 0x25 07 38 0x26 XX Serial number to be filled in at ATE 39 0x27 XX 40 0x28 XX 41 0x29 XX 42 0x2a XX 43 0x2b XX 44 0x2c XX 45 0x2d 04 PACKET Product Configuration Options Data BINARY 46 0x2e 10 47 0x2f CO 48 0x30 00 49 0x31 80 A 10 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Table A 5 VPD SROM Configuration Specification for 01 W3394F01 Continued
83. the writing of a one to itself or by power up reset escb escb indicates the entity that was accessing SDRAM at the last logging of a single or multiple bit error by the SMC If escb is 1 it indicates that the scrubber was accessing SDRAM If escb is 0 it indicates that the PPC60x bus master was accessing SDRAM esen When set esen allows errors that occur during scrubs to be logged When cleared esen does not allow errors that occur during Scrubs to be logged embt embt is set by the logging of a multiple bit error It is cleared by the logging of a single bit error It is undefined after power up reset The syndrome code is meaningless if its embt bit is set esbt esbt is set by the logging of a single bit error It is cleared by the logging of a multiple bit error When the SMC logs a single bit error the syndrome code indicates which bit was in error Refer to the section on ECC Codes http www motorola com computer literature 3 49 System Memory Controller SMC ERR SYNDROME ERR SYNDROME reflects the syndrome value at the last logging of an error This eight bit code indicates the position of the data error When all the bits are zero there was no error Note that if the logged error was multiple bit then these bits are meaningless Refer to the section on ECC Codes for a decoding of the syndromes esblk0 esblk1 esbik2 Together these three bits indicate which block of SDRAM was being accessed when the SMC
84. to PCI This offset allows PCI resources to reside at addresses that would not normally be visible from the PPC bus The PPC Slave Attributes Registers XSATTO 5 XSATT2 contain attribute information associated with the mapping of PPC memory space to PCI memory io space The bits within the XSATTx registers defined as follows REN Read Enable If set the corresponding PPC Slave is enabled for read transactions WEN Write Enable If set the corresponding PPC Slave is enabled for write transactions WPEN Write Post Enable If set write posting is enable for the corresponding PPC Slave http www motorola com computer literature 2 85 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller MEM PCI Memory Cycle If set the corresponding PPC Slave will generate transfers to or from PCI memory space When clear the corresponding PPC Slave will generate transfers to or from PCI I O space using the addressing mode defined by the IOM field IOM PCI I O Mode If set the corresponding PPC Slave will generate PCI I O cycles using spread addressing as defined in the section titled Generating PCI Cycles When clear the corresponding PPC Slave will generate PCI I O cycles using contiguous addressing This field only has meaning when the MEM bit is clear PPC Slave Address 3 Register Address MSADD3 FEFF0058 Bit O 1 2 EN EN EN N N
85. to this register signals the end of processing for the highest priority interrupt currently in service by the associated processor The write operation will update the In Service register by retiring the highest priority interrupt Reading this register returns zeros 2 122 Computer Group Literature Center Web Site System Memory Controller SMC Introduction The SMC in the Hawk ASIC is equivalent to the former Falcon Pair portion of a Falcon Raven chipset As were its predecessors it is designed for the MVME family of boards The SMC has interfaces between the PowerPC60x bus also called PPC60x bus or bus and SDRAM ROM Flash and its Control and Status Register sets CSR Note that the term SDRAM refers to Synchronous Dynamic Random Access Memory and is used throughout this document Overview This chapter provides a functional description and programming model for the SMC portion of the Hawk Most of the information for using the device in a system programming it in a system and testing it is contained here Bit Ordering Convention All SMC bused signals are named using Big Endian bit ordering bit 0 is the most significant bit except for the RA signals which use Little Endian bit ordering bit 0 is the least significant bit Features SDRAM Interface Double bit error detect Single bit error correct on 72 bit basis Two blocks with up to 256 Mbytes each at 100 MHz Eight blocks with up to 256 Mbyte
86. 0 Reserved Unsupported 1001 Reserved CONADD CONDAT Read 1010 Configuration Read CONADD CONDAT Write 1011 Configuration Write Unsupported 1100 Memory Read Multiple Unsupported 1101 Dual Address Cycle PPC Mapped PCI Read 0 1 1110 Memory Read Line Space Unsupported 1111 Memory Write and Invalidate Addressing The PCI Master generates all memory transactions using the Linear Incrementing addressing mode Combining Merging and Collapsing The PCI Master does not participate in any of these protocols Master Initiated Termination The PCI Master can handle any defined method of target retry target disconnect or target abort If the target responds with a retry the PCI Master waits for the required two clock periods and attempts the transaction again This process continues indefinitely until the transaction is completed the transaction is aborted by the target or if the transaction is aborted due to a PHB detected bridge lock The same happens if the target responds with a disconnect and there is still data to be transferred If the PCI Master detects a target abort during a read any untransferred read data is filled with ones If the PCI Master detects a target abort during a write any untransferred portions of data will be dropped The same rule applies if the PCI Master generates a Master Abort cycle 2 28 Computer Group Literature Center Web Site Functional Description Arbitrati
87. 00 00 00 2 108 Computer Group Literature Center Web Site Registers R Reset Controller Writing a one to this bit forces the controller logic to be reset This bit is cleared automatically when the reset sequence is complete While this bit is set the values of all other register are undefined EINTT External Interrupt Type This read only bit indicates the external interrupt type serial or parallel mode When this bit is set MPIC is in serial mode for external interrupts 0 through 15 When this bit is cleared MPIC is in parallel mode for external interrupts M Cascade Mode If the Cascade mode M bit is cleared the MPIC is completely disabled To activate the MPIC set the M bit mixed mode independent of the 8259 s presence The Cascade mode allows cascading of an external 8259 pair connected to the first interrupt source input pin 0 In the Pass Through mode interrupt source 0 is passed directly through to the processor 0 INT pin MPIC is bypassed in this scenario In the mixed mode the 8259 interrupts are delivered using the priority and distribution mechanism of the MPIC The Vector Priority and Destination registers for interrupt source 0 are used to control the delivery mode for all 8259 generated interrupt sources Table 2 20 Cascade Mode Encoding M Mode 0 Pass Through Mixed TIE Tie Mode Writing a one to this register bit will cause a tie in external in
88. 00 FAX 408 258 3659 Related Specifications For additional information refer to the following table for related specifications As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice B 4 Computer Group Literature Center Web Site Related Specifications Table B 3 Related Specifications Document Title and Source VME64 Specification VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale Arizona 85260 3415 Telephone 602 951 8866 FAX 602 951 0720 NOTE An earlier version of this specification is available as Publication Number ANSI VITA 1 1994 Versatile Backplane Bus VMEbus ANSI IEEE Institute of Electrical and Electronics Engineers Inc Standard 1014 Publication and Sales Department 1987 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 OR Microprocessor system bus for 1 to 4 byte data IEC 821 BUS Bureau Central de la Commission Electrotechnique Internationale 3 rue de Varemb Geneva Switzerland IEEE Common Mezzanine Card Specification CMC P1386 Draft 2 0 Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 http www motorola com computer literature R
89. 00 769 3772 FAX 1 800 POWERfax FAX 1 800 769 3732 TL16C550C UART SLLS177E Texas Instruments P O Box 655303 Dallas Texas 75265 web www ti com DECchip 21143 PCI Fast Ethernet LAN Controller EC QWC3B TE Hardware Reference Manual Digital Equipment Corporation Maynard Massachusetts DECchip Information Line Telephone United States and Canada 1 800 332 2717 TTY United States only 1 800 332 2515 Telephone outside North America 1 508 568 6868 W83C553 Enhanced System I O Controller with PCI Arbiter PIB W83C553 Winbond Electronics Corporation Winbond Systems Laboratory 2730 Orchard Parkway San Jose CA 95134 Telephone 408 943 6666 FAX 408 943 6668 http www motorola com computer literature B 3 Related Documentation Table B 2 Manufacturers Documents Continued Document Title and Source Publication Number M 48 559 CMOS 8K x 8 TIMEKEEPER SRAM Data Sheet M48T59 SGS Thomson Microelectronics Group Marketing Headquarters or nearest Sales Office 1000 East Bell Road Phoenix Arizona 85022 Telephone 602 867 6100 Universe II User Manual Universe Tundra Semiconductor Corporation Part Number 603 March Road 9000000 MD303 1 Kanata ON K2K 2M5 Canada Telephone 1 800 267 7231 OR 695 High Glen Drive San Jose California 95133 USA Telephone 408 258 36
90. 00000 FFFFFFFF The overall enable and write enable bits are always cleared at reset The reset vector enable bit is cleared or set at reset depending on external jumper configuration This allows the board http www motorola com computer literature 3 17 System Memory Controller SMC designer to use external jumpers to enable disable Block A B ROM Flash as the source of reset vectors 2 The base address for each block is software programmable At reset Block A s base address is 5 000000 and Block B s base address is FF400000 As noted above in addition to appearing at the programmed base address the first IMbyte of Block also appears at FFFO0000 FFFFFFFF if the reset vector enable bit is set 3 The assumed size for each block is software programmable It is initialized to its smallest setting at reset 4 The access time for each block is software programmable 5 The assumed width for Block A B is determined by an external jumper at reset time It also is available as a status bit and cannot be changed by software When the width status bit is cleared the block s ROM Flash is considered to be 16 bits wide where each half of the SMC interfaces to 8 bits In this mode the following rules are enforced a only single byte writes are allowed all other sizes are ignored and b all reads are allowed multiple accesses are performed to the ROM Flash devices when the read is for greater than one by
91. 008 Bo 91 9 REVID ae PU FEF80010 o o o RAMA 6 RAMB 9 RAMC gt RAMD S SIZ SIZ SIZ SIZ FEF80018 RAM A BASE RAM B BASE RAM C BASE RAM D BASE FEF80020 CLK FREQUENCY amp FEF80028 2 Alo S a sS 919 2 HHE FEF80030 e gu E S glg S ERR SYNDROME 2 2 S SBE COUNT o 2l FEF80038 ERROR_ADDRESS FEF80040 SCRUB O 289 2 FREQUENCY FEF80048 SCRUB ADDRESS ROM 42 g SIZ ggg 888 3 36 Computer Group Literature Center Web Site Programming Model Table 3 9 Register Summary Continued FEF80058 ROM B BASE 5 o 2 ROM bs pa g B SIZ g ggg FEF80060 5 Su Qo 4 4 gEg gg gg gg 80068 DPETT GWDP D o o e 55 FEF80070 DPE_A FEF80078 DPE_DH FEF80080 DPE_DL ey 12 FEF80098 5 nl al o 800 0 a E d SEX FEF800A8 I2 DATAWR FEF800B0 I2 DATARD FEF800C0 5 5 5 lt 5 SIZ E SIZ 5 SIZ E SIZ http www motorola com computer literature 3 37 System Memory Controller SMC Table 3 9 Register Summary Continued
92. 0198176 5 4 3 2 0 9 8 7 6 5 4 3 2 1098 7 6 54 3 21 0 Name VECTOR Operation R R R Reset 00 00 00 FF On PowerPC based systems Interrupt Acknowledge is implemented as a read request to a memory mapped Interrupt Acknowledge register Reading the Interrupt Acknowledge register returns the interrupt vector corresponding to the highest priority pending interrupt Reading this register also has the following side effects Reading this register without a pending interrupt will return a value of FF hex The associated bit in the Interrupt Pending Register is cleared Reading this register will update the In Service register VECTOR Vector This vector is returned when the Interrupt Acknowledge register is read http www motorola com computer literature 2 121 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller End of Interrupt Registers Offset Processor 0 200B0 Processor 1 210BO Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 10198176 5 4 3 2 0 9 8 7 6 5 4 3 2 1 O 9 gt 76 54 3 21 0 Name EOI Operation R R R R W Reset 00 00 00 0 0 EOI End of Interrupt There is one EOI register per processor EOI Code values other than 0 are currently undefined Data values written to this register are ignored zero is assumed Writing
93. 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 OF 9 8 7 6 5 4 3 2 1 0 765423210 Name CONFIG DATA Data D Data C Data B Data A Operation R W R W R W R W Reset n a n a n a n a Perspective from the PPC bus in Big Endian mode Offset CFC CFD CFE CFF Bit DL 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 0 1 2 31 41 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 1 4 5 6 7 8 9 O 1 Name CONFIG_DATA Data A Data B Data C Data D Operation R W R W R W R W Reset n a n a n a n a http www motorola com computer literature 2 103 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Perspective from the bus in Little Endian mode Offset CF8 CF9 CFA CFB Bit DH 11 1 1 1 111 1 111 2 22 2 2 2 2 2 2 2 3 3 0121 34 56 78 9 OF 1 2 3 4 5 6 7 89 0 1 2 3 4 5 6 7 8 9 O 1 CONFIG DATA Data D Data Data Data Operation R W R W R W R W Reset n a n a n a n a MPIC Registers The following conventions are used in the Hawk register charts a R Read Only field a R W Read Write field a S Writing a ONE to this field sets this field a C Writing a ONE to this field clears this field MPIC Registers The MPIC register map is shown in the following table
94. 1160 TIMER IDESTINATION REGISTER 01170 TIMER 2 CURRENT COUNT REGISTER 01180 TIMER 2 BASE COUNT REGISTER 01190 TIMER 2 VECTOR PRIORITY REGISTER 011a0 TIMER 2 DESTINATION REGISTER 011b0 TIMER 3 CURRENT COUNT REGISTER 011c0 TIMER 3 BASE COUNT REGISTER 011d0 TIMER 3 VECTOR PRIORITY REGISTER 011 0 http www motorola com computer literature 2 105 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 19 MPIC Register Map Continued 332222222222111111111 1 Off 1098765 4321098765 4321098765 43 210 TIMER 3 DESTINATION REGISTER 011f0 INT SRC 0 VECTOR PRIORITY REGISTER 10000 INT SRC 0 DESTINATION REGISTER 10010 INT SRC 1 VECTOR PRIORITY REGISTER 10020 INT SRC 1 DESTINATION REGISTER 10030 INT SRC 2 VECTOR PRIORITY REGISTER 10040 INT SRC 2 DESTINATION REGISTER 10050 INT SRC 3 VECTOR PRIORITY REGISTER 10060 INT SRC 3 DESTINATION REGISTER 10070 INT SRC 4 VECTOR PRIORITY REGISTER 10080 INT SRC 4 DESTINATION REGISTER 10090 INT SRC 5 VECTOR PRIORITY REGISTER 100a0 INT SRC 5 DESTINATION REGISTER 100b0 INT SRC 6 VECTOR PRIORITY REGISTER 100c0 INT SRC 6 DESTINATION REGISTER 100d0 INT SRC 7 VECTOR PRIORITY REGISTER 100e0 INT SRC 7 DESTINATION REGISTER 100f0 INT SRC 8 VECTOR PRIORITY REGISTER 10100 INT SRC 8 DESTINATION REGISTER 10110 INT SRC 9 VECTOR PRIORITY REGISTER 10120 INT
95. 22 91 0 5 C4 92 0x5C 10 93 0x5D 04 94 0 5 02 95 0 5 20 96 0x60 20 97 0x61 00 98 0x62 OB PACKET FLASH Memory Configuration 2 BINARY A 12 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Table A 5 VPD SROM Configuration Specification for 01 W3394F01 Continued Offset Value Field Type Description 99 0x63 0A 100 0x64 FF 101 0x65 FF 102 0x66 FF 103 0x67 FF 104 0x68 08 105 0x69 02 106 02 0x6A 107 08 Ox6B 108 08 0x6C 109 01 0x6D 110 OE PACKET L2 Cache Configuration Ox6E BINARY 111 Ox6F OF 112 0x70 FF 113 0x71 FF 114 0x72 FF 115 0x73 FF 116 0x74 20 117 0x75 02 118 0x76 02 119 0x77 20 120 0x78 00 121 0x79 00 http www motorola com computer literature A 13 MVME2400 VPD Reference Information Table 5 VPD SROM Configuration Specification for 01 W3394F01 Continued Offset Value Field Type Description 122 00 0x7A 123 01 0x7B 124 02 0x7C 125 01 0x7D 126 04 Ox7E 127 OD PACKET Host PCI Bus Clock Frequency in Hertz 33 MHz Ox7F INTEGER 128 0x80 04 129 0x81 01 130 0 82 131 0 83 132 0 84 55 133 0 85 BINARY Reserved for future expansion 255 FF BINARY Reserved for future expansion Ox
96. 23 24 25 26 27 28 29 30 31 NAY SFP UD C0 DY Name swr_dpll 0 1 2 tras tras1 tdp 0 0 0 trp 0 0 0 trcd Operation 24 04 04 Reset 1P R W R R 1 1 1 1 R R 1 1 R R lt gt lt X P lt A PS P lt P lt P lt P lt The SDRAM Speed Attributes Register should be programmed based on the SDRAM device characteristics and the Hawk s operating frequency to ensure reliable operation In order for writes to this register to work properly they should be separated from any SDRAM accesses by a refresh before the write and by another refresh after the write The refreshes serve two purposes 1 they make sure that all of the SDRAMs are idle ensuring that mode register set operations for cl3 updates work properly and 2 they make sure that no SDRAM accesses happen during the write A simple way to meet theses requirments is to use the following sequence 1 Make sure all accesses to SDRAM are done 2 Wait for the 32 Bit Counter to increment at least 100 times 3 Perform the write writes to this register and other SMC registers if desired 4
97. 4 3 2 1 0 Name PROCESSOR INIT T Operation R R R R az zz Reset 00 00 00 00 oe P1 PROCESSOR 1 Writing a 1 to P1 will assert the Soft Reset input of processor 1 Writing a 0 to it will negate the SRESET signal P0 PROCESSOR 0 Writing a 1 to PO will assert the Soft Reset input of processor 0 Writing a 0 to it will negate the SRESET signal The Soft Reset input to the 604 is negative edge sensitive 2 110 Computer Group Literature Center Web Site Registers IPI Vector Priority Registers Offset 0 010A0 IPI 1 010BO IPI 2 010CO 3 010D0 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 H 1 0 9 8 7 6 5 4 3 2 1 OF 9 8 7 6 5 4 3 2 1 OF of gt 71 6 5 4 3 21 10 Name IPI VECTOR PRIORITY gt PRIOR VECTOR w R R W R R W Reset 8000 0 00 00 MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT ACTIVITY The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0
98. 95 Interprocessor Interrupt Dispatch 2 120 Interrupt Acknowledge 2 121 Interrupt Task Priority 2 120 IPI Vector Priority MPIC 2 111 MPIC 2 104 MPIC I O Base Address 2 96 MPIC Memory Base 2 97 PCI 2 91 PCIInterrupt Acknowledge 2 83 PCI Slave Address 2 98 PCI Slave Attribute 2 99 PHB Detected Errors Destination 2 119 PHB Detected Errors Vector Priority 2 118 PPC Error Address 2 81 PPC Error Attribute 2 82 PPC Error Enable 2 77 PPC Error Status 2 79 PPC Slave Address 2 86 PPC Slave Offset Attribute 2 85 2 87 Processor Init MPIC 2 110 MC 32 Bit Counter 3 71 MC Address Parity Error Address 3 71 MC Address Parity Error Log 3 70 MC Base Address 3 66 MC Data Parity Error Address 3 60 MC Data Parity Error Log 3 59 MC Data Parity Error Lower Data 3 61 MC Data Parity Error Upper Data 3 60 MC ECC Control 3 45 MC Error Address 3 50 MC Error Logger 3 49 MC External Register set 3 72 MC General Control Register 3 40 MC 12 Clock Prescaler 3 61 MC 12 Control 3 62 MC I2C Receiver Data 3 65 MC I2C Status 3 63 MC 12 Transmitter Data 3 64 MC ROM A Base Size 3 53 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 SMC ROM B Base Size 3 56 IN 8 Computer Group Literature Center Web Site MC Speed Attributes 3 58 MC Scrub Address 3 52 MC Scrub Refresh 3 51 MC SDRAM Base Address 3 43 MC SDRAM Enable and Size 3 41 3 65 SMC SDRAM Speed Attributes 3 68 SMC tben 3 73 SMC Vend
99. A Apple Computer Inc P O Box 319 Buffalo NY 14207 Telephone 1 800 282 2732 FAX 716 871 6511 OR IBM 1580 Route 52 Bldg 504 Hopewell Junction NY 12533 7531 Telephone 1 800 PowerPC OR Morgan Kaufmann PUblishers Inc 340 Pine street Sixth Floor San Francisco CA 94104 3205 USA Telephone 413 392 2665 FAX 415 982 2665I Publication Number Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Electronic Industries Association Engineering Department 2001 Eye Street N W Washington D C 20006 ANSI EIA 232 D Standard http www motorola com computer literature Related Documentation B URLs The following URLs uniform resource locators may provide helpful sources of additional information about this product related services and development tools Please note that while these URLs have been verified they are subject to change without notice a Motorola Computer Group http www motorola com computer a Motorola Computer Group OEM Services http www motorola com computer support B 8 Computer Group Literature Center Web Site Index Numerics 16550 access registers 1 25 16550 UART 1 25 32 Bit Counter 3 71 SMC 3 71 8259 interrupts PIB 5 4 A AACK as used with PPC Slave 2 7 access timing ROM 3 10 address decoders PPC to PCI 2 7 limits on PHB map decoding 2 6 address decod
100. ANSMITTER DATA REG Y LOAD DATA n TO TRANSMITTER DATA REG READ I2C STATUS REG LOAD WORD ADDR 1 I2C TRANSMITTER DATA REG READ 2 STATUS 4 READ 2 STATUS REG LOAD 05 STOP CONDITION CONTROL REG LOAD DUMMY DATA TO TRANSMITTER DATA REG READ I2C STATUS REG Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 8 Programming Sequence for I2C Page Write 3 30 Computer Group Literature Center Web Site Functional Description I2C Sequential Read The PC sequential read can be initiated by either an PC random read described here or an current address read The first step in the programming sequence of an PC random read initiation is to test the i2 cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the i2 start and i2 enblbits in the C Control Register and then writing the device address bits 7 1 and write bit bit 020 to the Transmitter Data Register The i2 cmplt bit is automatically cleared with the write cycle to the Transmitter Data Register The Status Register must now be polled to test the i2 cmplt and i2 ackin bits The i2 cmplt bit becomes set when the device address and write bit are transmitted a
101. Aa AA Aj A rom 5 40 1 rom a spd0 1 determine the access timing used for ROM Flash Block A The encoding of these bits are shown in Table 3 15 The device access times shown in the table are conservative and allow time for buffers on address control and data signals For more accurate information see the sections entitled ROM Flash Speeds and External Register Set Writes that change these bits must be enveloped by a period of time in which no accesses to ROM Flash Block A occur A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before and after the write Table 3 15 ROM Speed Bit Encodings rom a b spd0 1 Approximate ROM Block A B Device Access Time 00 12 Clock Periods 120ns 100MHz 180ns 66 67MHz 01 8 Clock Periods 80ns 100MHz 120ns 66 67MHz 10 5 Clock Periods 50ns 100MHz 75ns 9 66 67MHz 2611 3 Clock Periods 30ns 9 100MHz 45ns 66 67MHz rom b spd0 1 rom b spd0 1 determines the access timing used for ROM Flash Block B Refer to the table above 3 58 Computer Group Literature Center Web Site Programming Model Writes that change these bits must be enveloped by a period of time in which no accesses to ROM Flash Bank B occur simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before a
102. Attribute 3 Registers Address XSOFF3 XSATT3 SFEFF005C BH XSOFF3 XS ATT3 zz z z gt Operation R W R 24 24 24 24 Reset Regbase Oxfeff0000 gt 8000 00 Regbase Oxfefe0000 gt 7000 Slave Offset Register3 XSOFF3 contains offset information associated with the mapping of PPC memory space to PCI memory IO space The field within the XSOFF3 register is defined as follows XSOFFx PPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PPC address to determine the PCI address used for transfers from the PPC bus to PCI This offset allows PCI resources to reside at addresses that would not normally be visible from the PPC bus It is initialized to 8000 to facilitate a zero based access to PCI space The PPC Slave Attributes Register3 XSATT3 contains attribute information associated with the mapping of PPC memory space to PCI memory IO space The bits within the XSATT3 register are defined as follows REN Read Enable If set the corresponding PPC slave is enabled for read transactions WEN Write Enable If set the corresponding PPC slave is enabled for write transactions http www motorola com computer literatu
103. B3 gt PARB2 gt PARB1 O11 gt PARBO gt HAWK gt PARB6 gt PARBS gt PARB4 gt PARB3 gt PARB2 100 PARB2 gt PARBI gt PARBO gt HAWK gt PARB6 gt PARBS gt PARB4 gt PARB3 101 PARB3 gt PARB2 gt PARBI gt PARBO gt HAWK gt PARB6 gt 5 gt 4 110 PARB4 gt PARB3 gt PARB2 gt PARBI gt PARBO gt HAWK gt PARB6 gt 5 111 5 gt PARB4 gt PARB3 gt PARB2 gt gt PARBO gt HAWK gt PARB6 When using the mixed priority scheme the encoding of this field is shown in the following table http www motorola com computer literature 2 73 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller HIER Priority ordering highest to lowest 000 Group gt Group 2 gt Group 3 gt Group 4 001 Group 4 gt Group gt Group 2 gt Group 3 010 Group 3 gt Group 4 gt Group 1 gt Group 2 011 Group 2 gt Group 3 gt Group 4 gt Group 1 100 Reserved 101 Reserved 110 Reserved 111 Reserved POL Park on lock If set the PCI Arbiter will park the bus on the master that successfully obtains a PCI bus lock The PCI Arbiter keeps the locking master parked and does not allow any non locked masters to obtain access of the PCI bus until the locking master releases the lock If this bitis cleared the PCI Arbiter does not distinguish betwee
104. Beat Write Scrub Type Beat Read Terminate the Terminate the This cycle is not PPC60x bus cycle PPC60x bus cycle seen on the normally normally PPC60x bus Provide corrected Correct the data Write corrected data to the PPC60x read from data back to Single Bit bus master SDRAM merge SDRAM if so Error with the write enabled data and write the corrected merged data to SDRAM Assert SMC INT Assert SMC INT Assert SMC INT if so enabled if so enabled if so enabled Terminate the Terminate the This cycle is not PPC60x bus cycle PPC60x bus cycle seen on the normally normally PPC60x bus Provide miss Do not perform the N A Do not perform corrected write portion of the write portion Double Bit SDRAM data to the read modify of the read Error the PPC 60x bus write cycle to modify write master SDRAM cycle to SDRAM Assert SMC INT Assert SMC INT Assert SMC INT if so enabled if so enabled if so enabled Assert MCHKO if Assert MCHKO if so enabled so enabled Triple Some of these errors are detected correctly and are treated the same as double bit greater errors The rest could show up as error or single bit error both of which Bit Error are incorrect 3 16 Computer Group Literature Center Web Site Functional Description Notes 1 No opportunity for error since no read of SDRAM occurs during a four beat write 2 The SMC asserts its interrupt output SMC INT upon de
105. C60x address bus during PPC60x address cycle TS asserted to AACK_ asserted It is cleared by writing a one to it or by power up reset ape_tt0 4 ape tt is the value that was on the TTO TT4 signals when the apelog bit was set 3 70 Computer Group Literature Center Web Site Programming Model ape 0 3 APE AP is the value that was on the APO AP7 signals when the apelog bit was set ape me When ape me is set the transition of the apelog bit from false to true causes the Hawk to pulse its machine check interrupt request pin MCHKO true When ape me is cleared apelog does not affect the Address Parity Error Address Register Address FEF800E8 Bit SO A A ca tf ALO A DY ay A OY SEY Of OOF NF AAA a a a a SEIN NI NI NI NI A og Name APE_A Operation READ ONLY Reset 0 PL APE_A APE_A is the address of the last PPC60x address bus parity error that was logged by the Hawk It is updated only when apelog goes from 0 to 1 32 Bit Counter Address FEF80100 Bit J GO CA Os I JOO o 5 IN IN IN IN IN IN IN OO SIF IN JO gt IO Oo JO r2 G2 gt UA O 100 OD O Name CTR32 O
106. CI master received target abort PPER PCI parity error PSER PCI system error Each of these error conditions will cause an error status bit to be set in the PPC Error Status Register ESTAT If a second error is detected while any of the error bits is set the OVFL bit is asserted but none of the error bits are changed Each bit in the ESTAT may be cleared by writing a 1 to it writing a 0 to it has no effect New error bits may be set only when all previous error bits have been cleared When any bit in the ESTAT is set the PHB will attempt to latch as much information as possible about the error in the PPC Error Address EADDR and Attribute Registers EATTR Information is saved as follows http www motorola com computer literature 2 41 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Error Status Error Address and Attributes XBTO From PPC bus XDPE From PPC bus PRTA From PCI bus PSMA From PCI bus PPER Invalid PSER Invalid Each ESTAT error bit may be programmed to generate a machine check and or a standard interrupt The error response is programmed through the PPC Error Enable Register EENAB on a source by source basis When machine check is enabled either the XID field in the EATTR Register or the DFLT bit in the EENAB Register determine the master to which the machine check is directed For errors in which the master who originated the transaction can be d
107. Cause Action Single bit ECC Store Write corrected data to memory Load Present corrected data to the MPC master Generate interrupt via MPIC if so enabled Double bit ECC Store Terminate the bus cycle normally without writing toSDRAM Load Present un corrected data to the MPC master Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled MPC Bus Time Out Store Discard write data and terminate bus cycle normally Load Present undefined data to the MPC master Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Target Abort Store Discard write data and terminate bus cycle normally Load Return all 17 and terminate bus cycle normally Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled PCI Master Abort Store Discard write data and terminate bus cycle normally Load Return all 175 and terminate bus cycle normally Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled Detected Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled SERR Detected Generate interrupt via MPIC if so enabled Generate Machine Check Interrupt to the Processor s if so enabled http www motorola com computer literature 5 9 Programming
108. Controller MPIC and the System Memory Controller SMC The MVME2400 series also includes 9MB of Flash memory 32MB to 256MB of ECC protected SDRAM and a rich set of features of I O peripherals The I O peripheral devices on the PCI bus include the Universe II VMEbus interface ASIC and two PMC slots Functions provided from the ISA bus are one asynchronous serial port a real time clock counters timers and a software readable header The MVME2400 series board interfaces to the VMEbus via the P1 and P2 connectors which use the 5 row 160 pin connectors as specified in the proposed VME64 Extension Standard It also draws 5V 12V and 12V power from the VMEbus backplane through these two connectors Additional power of 2 0V and 3 3V is regulated onboard from the 5V power Front panel connectors on the MVME2400 series board include an RJ45 connector for the Ethernet 10 Base T 100 Base Tx interface and an RJ45 connector for the async serial debug port The front panel also includes RESET and ABORT switches and status LEDs MVME2400 series contains two IEEE1386 1 PCI Mezzanine Card PMC slots These PMC slots are 64 bit capable and support both front and rear I O Pins 1 through 64 of PMC slot 1 connector 114 are routed to row C and row A of the 5 row DIN P2 connector Pins 1 through 46 of PMC slot 2 connector J24 are routed to row D and row Z of P2 Additional PCI expansion is supported with a 114 pin Mictor connector This co
109. DPE field within the ETEST register can be used to purposely inject data parity errors on specific data parity lines Data parity errors can only be injected during cycles where PHB is sourcing PPC data PHB will generate address parity whenever it is sourcing a PPC address This will happen for all PPC Master transactions Valid address parity will be presented when ABB is being asserted PHB has a mechanism to purposely inject address parity errors for testability The APE field within the ETEST register can be used to purposely inject address parity errors on specific address parity lines Address parity errors can only be injected during cycles where PHB is sourcing a PPC address PHB does not have the ability to check for address parity errors PPC Bus Timer The PPC Timer allows the current bus master to recover from a potential lock up condition caused when there is no response to a transfer request The time out length of the bus timer is determined by the XBT field within the GCSR http www motorola com computer literature 2 17 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The PPC Timer is designed to handle the case where an address tenure is not closed out by the assertion of AACK The PPC Timer will not handle the case where a data tenure is not closed out by the appropriate number of assertions The Timer will start timing at the exact moment when the PPC60x bus pipeline has gone flat I
110. DRAM MVME2402 3 MPC750 233 MHz 64MB ECC SDRAM MVME2431 1 MPC750 350MHz 32MB ECC SDRAM MVME2432 1 MPC750 350MHz 32MB ECC SDRAM MVME2433 1 MPC750 350MHz 128MB ECC SDRAM MVME2433 3 MPC750 350MHz 128MB ECC SDRAM MVME2434 1 MPC750 350MHz 256MB ECC SDRAM MVME2434 3 MPC750 350MHz 256MB ECC SDRAM Summary of Changes Date Changes Replaces August 2000 If Cascade Mode M is cleared the MPIC is disabled Cascade Mode on page 2 109 Overview of Contents Chapter 1 Board Description and Memory Maps briefly describes the board level hardware features of the MVME2400 series VME Processor Modules Chapter 2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller describes the architecture and usage of the PowerPC to PCI Local Bus Bridge PHB and the Multi Processor Interrupt Controller MPIC portion of the Hawk ASIC Chapter 3 System Memory Controller SMC provides a functional description and programming model for the SMC portion of the Hawk Most of the information for using the device in a system programming it in a system and testing it is contained here Chapter 4 Universe II VMEbus to PCI Chip includes general information a functional description and status and control register information Chapter 5 Programming Details contains details of several programming functions that are not tied to any specific ASIC chip Appendix A MVM E2400 VPD Reference Information
111. Ebus http www motorola com computer literature IN 11 lt moz xXmoz Index master mapping diagram 1 19 slave mapping diagram 1 21 VMEbus domain in endian issues 5 14 VMEbus interface to Universe II 4 4 MEbus interrupt handling 4 7 MEbus mapping 1 18 MEbus master map 1 18 MEbus slave map 1 20 VMEbus slave map example 1 23 Universe II PCI Register Values 1 22 VPD A 1 example of SROM data A 9 use of 1 23 VPD FLASH Memory Configuration Data A 5 VPD L2 Cache Configuration Data A 6 VPD Product Configuration Options A 3 VPD definitions A 1 W83C553 registers 1 25 Watchdog Timer registers 2 43 watchdog timers as part of PHB 2 42 WDTXxCNTL register 2 43 WDTXxCNTL Registers 2 88 WDTXxSTAT Registers 2 90 when MPC devices are big endian 2 38 word definition x write posting as part of PHB tuning 2 11 writing to the control registers 3 74 2 78536 1 33 78536 CIO port pins assignment 1 33 V V V V IN 12 Computer Group Literature Center Web Site
112. F Upper X3FFFFFA 7FFFFF Upper X3FFFFFB 7FFFFF Upper X3FFFFFC 7FFFFF Lower X3FFFFFD 7FFFFF Lower X3FFFFFE 7FFFFF Lower X3FFFFFF 7FFFFF Lower 2 Interface The ASIC has an PC Inter Integrated Circuit two wire serial interface bus Serial Clock Line SCL and Serial Data Line SDA This interface has master only capability and may be used to communicate the configuration information to a slave device such as serial EEPROM The IC interface is compatible with these devices and the inclusion of a serial EEPROM in the memory subsystem may be desirable The EEPROM could maintain the configuration information related to the memory subsystem even when the power is removed from the system Each slave device connected to the 2 bus is software addressable bya unique address The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400pF For C bus programming the ASIC is the only master on the bus and the serial EEPROM devices are all slaves The 2 bus supports 7 bit addressing mode and transmits data one byte at a time in a serial fashion http www motorola com computer literature 3 21 System Memory Controller SMC with the most significant bit MSB being sent out first Five registers are required to perform the bus data transfer operations These are the rc Clock Prescaler Register PC Control Register PC Status Register PC Transmitte
113. FF Note Upper CRC byte for the calculation of CRC Note This data will change to reflect the specific configuration of the corresponding board assembly number to which it applies A 14 Computer Group Literature Center Web Site Related Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual You can obtain paper or electronic copies of Motorola Computer Group publications by Contacting your local Motorola sales office a Visiting Motorola Computer Group s World Wide Web literature site http www motorola com computer literature Table B 1 Motorola Computer Group Documents Document Title Motorola Publication Number MVME2400 Series VME Processor Module V2400A IH Installation and Use MVME2400 Series VME Processor Module V2400A PG Programmer s Reference Guide this manual PPCBug Firmware Package User s Manual Parts 1 and 2 PPCBUGAI UM PPCBUGA2 UM PPCBug Diagnostics Manual PPCDIAA UM PMCspan PMC Adapter Carrier Module Installation and Use PMCSPANA IH To obtain the most up to date product information in PDF or HTML format visit http www motorola com computer literature Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these source
114. H Bank Default rom b Default Mapping for FFF00000 FFFFFFFF 0 ROM FLASH Bank A 1 ROM FLASH Bank http www motorola com computer literature 5 15 MVME2400 VPD Reference Information Vital Product Data VPD Introduction The data listed in the following tables are for general reference information The VPD identifies board information that may be useful during board initialization configuration and verification VPD Data Definitions The following table describes and lists the currently assigned packet identifiers Note Additional packet identifiers may be added to this list as future versions of the VPD are released Table A 1 VPD Packet Types ID Size Description Data Type Notes 00 N A Guaranteed Illegal N A 01 Variable Product Identifier for example MBX MTX ASCII 1 2600 750 MVME2400 etc 02 Variable Factory Assembly Number for example 01 ASCII 1 W3394F01C etc 03 Variable Serial Number for example 3383185 etc ASCII 1 04 10 Product Configuration Options Data Binary The data in this packet further describes the board configuration for example header population I O routing etc Its exact contents is dependent upon the product configuration type A following table describes this packet 05 04 MPU Internal Clock Frequency in Hertz forexample Integer 4 byte 2 350 000 000 dec
115. I master signals master abort to terminate a PCI transaction It may be cleared by writing it to a 1 writing it to a 0 has no effect When the PSMAM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the PSMAI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PRTA PCI Master Received Target Abort This bit is set when the PCI master receives target abort to terminate a PCI transaction It may be cleared by writing it to a 1 writing it to a has no effect When the PRTAM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the PRTAI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PPC Error Address Register The Error Address Register EADDR captures addressing information on the various errors that the PHB can detect The register captures the PPC address when the XBTO bit is set in the ESTAT register The register captures the PCI address when the PSMA or PRTA bits are set in the ESTAT register The register s contents are not defined when the XDPE PPER or PSER bits are set in the ESTAT register Address FEFF0028 Bit jami N N N N N N N N N w w
116. IELD SEM2 OPER R W RESET 0 0 0 0 0 0 0 VME Geographical Address Register VGAR The VME Geographical Address Register is an 8 bit read only register located at ISA I O address x1006 This register reflects the states of the geographical address pins at the 5 row 160 connector REG VME Geographical Address Register Offset 1006 BIT SD7 SD6 SD5 SD4 SD3 SD2 SDI 5 0 FIELD 4 2 1 READ ONLY RESET X X X X X X X Emulated Z8536 CIO Registers and Port Pins Although the MVME2400 series does not use a 78536 there are several functions within this part that are emulated within an ISA Register PLD These functions are accessed by reading writing the Port A B C Data Registers and Control Register Note that the Pseudo IACK function is not implemented in the MVME2400 series Computer Group Literature Center Web Site ISA Local Resource Bus The MVME2400 implements the Z8536 CIO functions according to the following table Table 1 18 Emulated Z8536 Access Registers PCI I O Address Function 0000 0844 Port C s Data Register 0000 0845 Port B s Data Register 0000 0846 Port A s Data Register 0000 0847 Control Register 78536 CIO Port Pins The following table shows the signal function and port mapping for the Z8536 CIO emulation The direction of these ports are fixed
117. IFO The PCI Slave can accept either 32 bit or 64 bit transactions however it can only accept 32 bit addressing There is no limit to the length of the transfer that the PCI Slave can handle During posted write cycles the PCI Slave will continue to accept write data until the PCI FIFO is full If the PCI FIFO is full the PCI Slave will hold off the master with wait states until there is more room in the FIFO The PCI Slave will not initiate a disconnect If the write transaction is compelled the PCI Slave will hold off the master with wait states while each beat of data is being transferred The PCI Slave will issue TRDY only after the data transfer has successfully completed on the PPC bus If a read transaction is being performed within an address space marked for prefetching the PCI Slave in conjunction with the PPC Master will attempt to read ahead far enough on the PPC bus to allow for an uninterrupted burst transaction on the PCI bus Read transactions within address spaces marked for no prefetching will receive a TRDY indication on the PCI bus only after one burst read has successfully completed on the PPC bus Each read on the PPC bus will only be started after the previous read has been acknowledged on the PCI bus and there is an indication that the PCI Master wishes for more data to be transferred The following paragraphs identify some associations between the operation of the PCI slave and the PCI 2 1 Local Bus Specification requirem
118. Interrupt Controller MPIC Functional Description There is a possibility for a priority tie between the two processors when resolving external interrupts In that case the interrupt will be delivered to processor 0 or processor 1 as determined by the TIE mode bit This case is not defined in the above rule set Programming Notes External Interrupt Service The following summarizes how an external interrupt is serviced An external interrupt occurs The processor state is saved in the machine status save restore registers A new value is loaded into the Machine State Register MSR The External Interrupt Enable bit in the new MSR MSRee is set to zero Control is transferred to the O S external interrupt handler Theexternal interrupt handler calculates the address of the Interrupt Acknowledge register for this processor MPIC Base Address 0x200A00 processor ID shifted left 12 bits The external interrupt handler issues an Interrupt Acknowledge request to read the interrupt vector from the Hawk MPIC If the interrupt vector indicates the interrupt source is the 8259 the interrupt handler issues a second Interrupt Acknowledge request to read the interrupt vector from the 8259 The Hawk MPIC does not interact with the vector fetch from the 8259 The interrupt handler saves the processor state and other interrupt specific information in system memory and re enables for external interrupts the MSRee bit is
119. MPIC interrupt controller When this bit is clear no interrupt will be asserted PPC Error Status Register The Error Status Register ESTAT provides an array of status bits pertaining to the various errors that the PHB can detect The bits within the ESTAT are defined in the following paragraphs http www motorola com computer literature 2 79 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Address FEFF0024 Bit sae N N N N N N N 95 l EN Name Bou ST HAO m Operation R R R 500 0 DA OLAX IHdd 0 Of8 IHSd 0 D A VINSd 0 A 00 00 OVF Error Status Overflow This bitis set when any error is detected and any of the error status bits are already set It may be cleared by writing a 1 to it writing a 0 to it has no effect XBTO Address Bus Time out This bit is set when the timer times out It may be cleared by writing a 1 to it writing a 0 to it has no effect When the XBTOM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the XBTOI bit in the EENAB register is set the assertion of this bit w
120. MVME2400 Series VME Processor Module Programmer s Reference Guide V2400A PG2 August 2000 Copyright 2000 Motorola Inc rights reserved Printed in the United States of America Motorola and the Motorola symbol are registered trademarks of Motorola Inc Motorola and the Motorola symbol are registered trademarks of Motorola Inc PowerStack VMEmodule M and VMEsystem are trademarks of Motorola Inc PowerPC PowerPC 603 and PowerPC 604 are trademarks of IBM Corp and are used by Motorola Inc under license from IBM Corp AIX is a trademark of IBM Corp Timekeeper and Zeropower are trademarks of Thompson Components other products mentioned in this document are trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to
121. Maps Feature Summary There are many models based on the MVME2400 series architecture The following table summarizes the major features of the MVME2400 series Table 1 1 MVME240x Features Feature Microprocessor Description 233 MHZ 750 PowerPC processor MVME2401 2402 models 350 MHZ MPC750 PowerPC processor MVME2431 2434 models Form factor 6U VMEbus SDRAM Double Bit Error detect Single Bit Error correct across 72 bits 32MB 64MB 128MB or 256MB SDRAM L2 Cache back side L2 Cache using late write or burst mode SRAMS Flash memory Sockets for IMB 8 MB Soldered on board Memory Controller Hawk s SMC System Memory Controller PCI Host Bridge Hawk s PHB PCI Host Bridge Interrupt Controller Hawk s MPIC Multi Processor Interrupt Controller PCIInterface 32 64 bit Data 33MHz operation Real time clock 8KB with and battery backup SGS Thomson M48T59 Peripheral Support One 16C550 compatible async serial port routed to front panel RJ45 10 Base T 100 Base Tx Ethernet interface routed to front panel RJ45 Switches Reset RST and Abort ABT Status LEDs Four Board fail BFL CPU PMC one for PMC slot 2 one for slot 1 Timers One 16 bit timer in W83C553 ISA bridge four 32 bit timers in MPIC device Watchdog timer provided in SGS Thomson M48T59 VME I O VMEbus P2 connector Serial I O One asyn
122. N N N N N N N ww o 3456 7890 12 34 5 6 7 8 9 0 12 3 4 5 6 7 8 9 0 1 Name XSADD3 START END Operation R W R W Reset Regbase Oxfeff0000 gt 8000 Regbase Oxfeff0000 gt 8080 Regbase Oxfefe0000 gt 9000 Regbase Oxfefe0000 gt 9080 The PPC Slave Address Register3 XSADD3 contains address information associated with the mapping of PPC memory space to PCI memory io space XSADD3 in conjunctiion with XSOFF3 XSATT3 is the only register group that can be used to initiate access to the PCI CONFIG ADDRESS 80000CF8 and DATA 80000CFC registers The power up value of XSADD3 and XSOFF3 XSATT3 are set to allow access to these special register spaces without PPC register initialization The fields within XSADD3 are defined as follows START Start Address This field determines the start address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address Computer Group Literature Center Web Site Registers END End Address This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address PPC Slave Offset
123. OAD DEVICE ADDR RD BIT TO I2C TRANSMITTER DATA REG READ I2C STATUS REG LOAD DUMMY DATA TO 2 TRANSMITTER DATA REG READ I2C STATUS REG MPLT DATIN 12 READ 2 RECEIVER DATA REG LOAD 01 TO 2 CONTROL REG A Y LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Stop condition should be generated to abort the transfer after a software wait loop 1ms has been expired Figure 3 9 Programming Sequence for 2 Sequential Read http www motorola com computer literature 3 33 System Memory Controller SMC Refresh Scrub The SMC performs refresh by doing a burst of 4 CAS Before RAS CBR refresh cycles to each block of SDRAM once every 60us It performs scrubs by replacing every 128th refresh burst with a read cycle to 8 bytes in each block of SDRAM If during the read cycle the SMC detects a single bit error it performs a write cycle back to SDRAM using corrected data providing the SWEN control bit is set It does not perform the write if the SWEN bit is cleared If the SMC detects a double bit error it does not perform a write If so enabled single and double bit scrub errors are logged and the PPC60x bus master is notified via interrupt CSR Accesses The SMC has a set of control and status registers CSR
124. OFF position for that particular bit SRH Register Bit 0 is associated with Pin 1 and Pin 16 of the SRH and SRH Register Bit 7 is associated with Pin 8 and Pin 9 ofthe SRH The SRH is a read only register If Motorola s PowerPC firmware PPCBug is being used it reserves all bits SRHO to SRH7 If itis not being used the switch can be used for other applications E 15 1 E 16 SRHO 0 SRHO 1 SRH1 0 SRH1 1 SRH2 0 SRH2 1 pa SRHS 0 5 1 SRH4 0 SRH4 1 SRH5 0 SRH5 1 SRH6 0 m SRH6 1 SRH7 0 SRH7 1 Figure 1 4 General Purpose Software Readable Header NVRAM RTC amp Watchdog Timer Registers The M48T59 559 provides the MVME2400 series with 8K of non volatile SRAM a time of day clock and a watchdog timer Accesses to the M48T59 559 are accomplished via three registers The NVRAM RTC Address Strobe 0 Register the NVRAM RTC Address Strobe 1 Register Computer Group Literature Center Web Site ISA Local Resource Bus and the NVRAM RTC Data Port Register The NVRAM RTC Address Strobe 0 Register latches the lower 8 bits of the address and the NVRAM RTC Address Strobe 1 Register latches the upper 5 bits of the address Table 1 16 MK48T59 559 A
125. OZWRite 1 ReaD After start sequence with 12 DATAWR 31 0 subsequent writes to the PC Transmitter Data Register will cause the contents of I2_DATAWR to be transmitted to the responding slave device After a start sequence with 12 DATAWR 31 1 subsequent writes to the Transmitter Data Register data don t care will cause the responding slave device to transmit data to the Receiver Data Register If a value is written to I2 DATAWR data don t care when the i2 stop and 12 enbl bits in the C Control Register are set a stop sequence is generated Computer Group Literature Center Web Site Programming Model I2C Receiver Data Register Address FEF800B0 Bit S A Aca 00 A A AI eg fq OE Yay FY SEY FS ER DY NY a Sa ERIN NIN NIN NIN AY NTA Name 12 DATARD Operation READ ZERO READ ZERO READ ZERO READ Reset x X X I2 DATARD The I2 DATARD contains the receive byte for data transfers During PC sequential read operation the current receive byte must be read before any new one can be brough in A read of this register will automatically clear the 12 datin bit in the PC Status Register SDRAM Enable and Size Register Blocks E F G H Address FEF800C0 Bit o SP Aca s uuenrm wvo ioei mwm weteoo ay SEY SO EF OD NY
126. PE 16 64 16 64 16 64 16 64 16 64 Bits Bits Bits Bits Bits Bits Bits Bits Bits Bits 4 Beat Read 34 13 28 7 28 7 28 7 118 34 4 Beat Write N A N A 1 Beat Read 1 byte 13 13 13 13 1 Read 2 to 8 bytes 34 13 34 13 1 Beat Write 21 21 E E E 21 21 Note The information in Table 3 5 applies to access timing when configured for devices with an access time equal to 3 clock periods PPC60x Bus Interface The SMC has a PowerPC slave interface only It has no PowerPC master interface The slave interface is the mechanism for all accesses to SDRAM ROM Flash and the internal and external register sets Responding to Address Transfers When the SMC detects an address transfer that it is to respond to it asserts AACK immediately if there is no uncompleted PPC60x bus data transfer in process If there is one in process then the SMC waits and asserts coincident with the uncompleted data transfer s last data beat if the SMC is the slave for the previous data If it is not it holds off AACK_ until the CLK after the previous data transfer s last data beat Computer Group Literature Center Web Site Functional Description Completing Data Transfers If an address transfer to the SMC will have an associated data transfer the SMC begins a read or write cycle to the accessed entity SDRAM ROM Flash Internal or External Register as soon as the e
127. PO teres 3 17 DS UD D 3 21 LE 3 22 PE Tun sino o PR TN 3 25 IE Cument Address Belus ocaecat 3 27 Co d dii O 3 29 eee ener 3 31 BST EN MUR E E 3 34 3 34 e uci aan ces 3 34 CCo ETA fte Ib Ud renee Semen HELL 3 34 IA e 3 35 m T TM Ener 3 35 Bener QUU RS uenia RA Da prt uit it tute ME 3 35 Detailed Register Bit Descripsi cacario voe a pe p mea e Urbi 3 38 Tengo sev men M anata 3 39 Revision ID General Control Register erret ettet teens 3 40 SDRAM Enable and Size Register Blocks A B C 3 41 SDRAM Base Address Register Blocks 3 43 CLE Frequency 3 44 BOC Control 3 45 Error Logger iaceo co tree
128. PROC 1 21080 IACK REGISTER 210a0 P1 EOI REGISTER 210b0 P1 http www motorola com computer literature 2 107 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Feature Reporting Register Offset 01000 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 I 1 0 9 8 7 6 5 4 3 2 1 OF 9 8 7 6 5 4 3 2 109876 5 43 2110 Name FEATURE REPORTING NIRQ NCPU VID Operation R R R R Reset 0 00 0 01 02 NIRQ Number of IRQs The number of the highest external IRQ source supported The Timer and PHB Detected Error interrupts are excluded from this count NCPU Number of CPUs The number of the highest physical CPU supported There are two CPUs supported by this design CPU 0 and CPU 1 VID Version ID Version ID for this interrupt controller This value reports what level of the specification is supported by this implementation Version level of 02 is used for the initial release of the MPIC specification Global Configuration Register Offset 01020 Bit 332 22 22 22 22 2 1 1 1 1 1 1 1 1 1 I 1 0 9 8 7 6 5 4 3 2 1 OF 9 876 5 4 3 2 1 O of 8 76 54 32 1 0 Name GLOBAL CONFIGURATION seid Z m H Operation 3 R R R R Reset jo 00
129. Ratio RD 10 12 000 Reserved 100 1 1 010 2 1 110 3 1 001 3 2 101 Reserved 011 5 2 111 Reserved Multi Processor Interrupt Controller MPIC Functional Description The MPIC is a multi processor structured intelligent interrupt controller MPIC Features a MPIC programming model Supports two processors Supports 16 external interrupts Supports 15 programmable Interrupt amp Processor Task priority levels Supports the connection of an external 8259 for ISA AT compatibility Distributed interrupt delivery for external I O interrupts Direct Multicast interrupt delivery for Interprocessor and timer interrupts Four Interprocessor Interrupt sources 2 50 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Functional Description Four timers Q Processor initialization control Architecture The PCI Slave of the PHB implements two address decoders for placing the MPIC registers in PCI IO or PCI Memory space Access to these registers require PPC and PCI bus mastership These accesses include interrupt and timer initialization and interrupt vector reads The MPIC receives interrupt inputs from 16 external sources four interprocessor sources four timer sources and one PHB internal error detection source The externally sourced interrupts 1 through 15 have two modes of activation low level or active high positive edge External interr
130. Register Offset 10 Bit 3 3 2 2 2 2 2 2 2 2 22 22 1 1 1 1 1 1 1 1 1 1 1098765 4321098 5 4 3 1 98765423210 Name MIBAR BASE a v s Operation R W R Reset 0000 0000 MPIC I O Base Address Register MIBAR controls the mapping of the MPIC control registers in PCI I O space IO MEM IO Space Indicator This bit is hard wired to a logic one to indicate PCI I O space RES Reserved This bit is hard wired to zero BASE Base Address These bits define the I O space base address of the MPIC control registers The MIBAR decoder is disabled when the BASE value is zero 2 96 Computer Group Literature Center Web Site Registers MPIC Memory Base Register Offset 14 Bit 3 3 2 2 2 2 2 2 2 2 222 1 1 1 1 1 1 1 1 1 H 1098716 5 4 3 21 1019 8 7 5 321 98765423210 Name MMBAR BASE ZEKE SEE Operation R W R mum Reset 0000 0000 lololo The MPIC Memory Base Address Register MMBAR controls the mapping of the MPIC control registers in PCI memory space IO MEM IO Space Indicator This bit is hard wired to a logic zero to indicate PCI memory space MTYPx Memory Type These bits are hard wired to zero to indicate that the MPIC registers c
131. Register Address FEF80048 Bit A A en A AQ SY AY de SE OE OO NY oc ooo NINN AN C9 Name c S SCRUB ADDRESS 215271 Operation 4 READ WRITE nd 24 Reset oq OP SCRUB ADDRESS These bits form the address counter used by the scrubber for all blocks of SDRAM The scrub address counter increments by one each time a scrub to one location completes to all of the blocks of SDRAM When it reaches all 1s it rolls back over to all 0 and continues counting The SCRUB ADDRESS counter is readable and writable for test purposes Note Note that for each block the most significant bits of SCRUB ADDRESS COUNTER are meaningful only when their SDRAM devices are large enough to require them 3 52 Computer Group Literature Center Web Site Programming Model ROM A Base Size Register Address FEF80050 Bit J QO ON 3 00 iD ID IN IN IN IN IN IN IN BW SIE JD gt 100 SO J GO 100 Name ROM A BASE alg 5 5 c eeesss B B B B le me o 2 EE TS lt 7 9 Operation READ WRITE Te zm z g 616 READ ZERO 5 PL Siecle I lt
132. S Hr y 4 AD31 24 AD23 16 AD15 08 AD07 00 1916 9610 Figure 2 7 Big to Little Endian Data Swap When PPC Devices are Little Endian When all PPC devices are operating in Little Endian mode the originating address is modified to remove the exclusive ORing applied by PPC60x processors Note that no data swapping is performed Address modification happens to the originating address regardless of whether the http www motorola com computer literature 2 39 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller transaction originates from the PCI bus or the PPC bus The three low order address bits are exclusive ORed with a three bit value that depends on the length of the operand as shown in the following table Table 2 13 Address Modification for Little Endian Transfers Data Length bytes Address Modification 1 with 111 2 XOR with 110 4 XOR with 100 8 no change Note only legal data lengths supported in little endian mode are 1 2 4 or 8 byte aligned transfers Since this method has some difficulties dealing with unaligned PCI originated transfers the PPC master of the PHB will break up all unaligned PCI transfers into multiple aligned transfers into multiple aligned transfers on the PPC bus PHB Registers The PHB registers are not sensitive to changes in Big Endian and Little Endian mode With respect to the PPC bus but not
133. Translation Offset LSI1 TO 124 Universe II Reserved 128 PCI Slave Image 2 Control 512 12 PCI Slave Image 2 Base Address Register LSD BS 130 PCI Slave Image 2 Bound Address Register LSID BD 134 PCI Slave Image 2 Translation Offset LSD TO 138 Universe II Reserved 13C PCI Slave Image 3 Control LSI3 CTL 140 PCI Slave Image 3 Base Address Register LSI3 BS 144 PCI Slave Image 3 Bound Address Register LSI3 BD 148 PCI Slave Image 3 Translation Offset LSI3 TO 14C 16C Universe II Reserved 170 Special Cycle Control Register 5 174 Special Cycle PCI bus Address Register SCYC ADDR 178 Special Cycle Swap Compare Enable Register SCYC EN 17C Special Cycle Compare Data Register SCYC CMP 180 Special Cycle Swap Data Register SCYC SWP 184 PCI Miscellaneous Register LMISC 188 Special PCI Slave Image SLSI 18C PCI Command Error Log Register L CMDERR 190 PCI Address Error Log LAERR 194 Universe Reserved 200 DMA Transfer Control Register DCTL 4 10 Computer Group Literature Center Web Site Registers Universe II Control and Status Registers UCSR Table 4 1 Universe Register Map Continued Offset Register Name 204 DMA Transfer Byte Count Register DTBC 208 DMA PCI bus Address Register DLA 20C Universe II Reserved 210 DMA VMEbus Address Register DVA 214 Universe II Reserved 218 DMA Command Packet Pointer DCPP 21C
134. Universe II Reserved 220 DMA General Control and Status Register DGCS 224 DMA Linked List Update Enable Register D LLUE 228 2FC Universe II Reserved 300 PCI Interrupt Enable LINT EN 304 PCI Interrupt Status LINT STAT 308 PCI Interrupt Map 0 LINT MAPO 30C PCIInterrupt Map 1 LINT MAPI 310 VMEbus Interrupt Enable VINT_EN 314 VMEbus Interrupt Status VINT_STAT 318 VMEbus Interrupt Map 0 VINT_MAPO 31C VMEbus Interrupt Map 1 VINT MAPI 320 Interrupt Status ID Out STATID 324 STATUS ID V1 STATID 328 VIRQ2 STATUS ID V2 STATID 32 VIRQ3 STATUS ID V3 STATID 330 VIRQ4 STATUS ID V4 STATID 334 VIRQS5 STATUS ID V5 STATID 338 VIRQ6 STATUS ID V6 STATID 33C VIRQ7 STATUS ID V7 STATID 340 3FC Universe II Reserved 400 Master Control MAST CTL 404 Miscellaneous Control MISC CTL http www motorola com computer literature Universe II VMEbus to PCI Chip Table 4 1 Universe Register Map Continued Offset Register Name 408 Miscellaneous Status MISC STAT 40C User AM Codes Register USER AM 410 EFC Universe II Reserved F00 VMEbus Slave Image 0 Control VSIO CTL F04 VMEbus Slave Image 0 Base Address Register VSIO BS F08 VMEbus Slave Image 0 Bound Address Register VSIO BD FOC VMEbus Slave Image 0 Translation Offset VSIO_TO F10 Universe Reserved F14 VMEbus Slave Image 1 Control VSII F18 VMEbus
135. Upper XXFFFFFA 7FFFFE Upper XXFFFFFB 7FFFFF Upper http www motorola com computer literature 3 19 System Memory Controller SMC Table 3 7 PPC60x to ROM Flash 16 Bit Width Address Mapping Continued PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected XXFFFFFC 7FFFFC Lower XXFFFFFD 7FFFFD Lower XXFFFFFE 7FFFFE Lower XXFFFFFF 7FFFFF Lower Table 3 8 PPC60x to ROM Flash 64 Bit Width Address Mapping PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected X0000000 000000 Upper X0000001 000000 Upper X0000002 000000 Upper X0000003 000000 Upper X0000004 000000 Lower X0000005 000000 Lower X0000006 000000 Lower X0000007 000000 Lower X0000008 000001 Upper X0000009 000001 Upper X000000A 000001 Upper X000000B 000001 Upper X000000C 000001 Lower X000000D 000001 Lower X000000E 000001 Lower X000000F 000001 Lower X3FFFFFO 7FFFFE Upper X3FFFFFI 7FFFFE Upper 3 20 Computer Group Literature Center Web Site Functional Description Table 3 8 PPC60x to ROM Flash 64 Bit Width Address Mapping PPC60x 0 1 ROM Flash A22 A0 ROM Flash Device Selected X3FFFFF2 7FFFFE Upper X3FFFFF3 7FFFFE Upper X3FFFFFA 7FFFFE Lower X3FFFFFS 7FFFFE Lower X3FFFFF6 7FFFFE Lower X3FFFFF7 7FFFFE Lower X3FFFFF8 7FFFFF Upper X3FFFFF9 7FFFF
136. XX XXXX 134 LSD TO XXXX XXXX 13C LSI3 CTL 0000 0000 http www motorola com computer literature Board Description and Memory Maps Table 1 12 Universe PCI Register Values for PREP Memory Continued Configuration Configuration Register Value Address Offset Register Name 140 LSI3 BS XXXX XXXX 144 LSI3 BD XXXX XXXX 148 LSI3 TO XXXX XXXX 188 SLSI C0A05338 VMEbus Mapping Note For the MVME2400 series RAM size is limited to 256MB VMEbus Master Map The processor can access any address range in the VMEbus with the help from the address translation capabilities of the Universe II ASIC The recommended mapping is shown in the Processor Memory Maps section The following figure illustrates how the VMEbus master mapping is accomplished 1 18 Computer Group Literature Center Web Site Programming Model PROCESSOR PCI MEMORY VMEBUS C ONBOARD MEMORY PROGRAMMABLE SPACE NOTE2 PCI MEMORY NOTE 1 SPACE m d s VME A24 VME A16 NOME VME A24 VME A16 NOTE 1 PCI ISA VME A24 MEMORY SPACE VME A16 PCI SPACE VME A24 VME A16 RESOURCES 11553 00 9609 Figure 1 2 VMEbus Master Mapping http www motorola com computer literature 1 19 Board Description and Memory Maps Notes 1 Programmable mapping done by the Hawk ASIC 2 Progra
137. a Parity Error Enable These bits are used for test reasons to purposely inject data parity errors whenever the PHB is sourcing PPC data A data parity error will be created on the correcponding PPC data parity bus if a bit is set For example setting DPEO will cause DPO to be generated incorrectly If the bit is cleared the PHB will generate correct data parity APEx Address Parity Error Enable These bits are used for test reasons to purposely inject address parity errors whenever the PHB is acting as a PPC bus master An address parity error will be created on the corresponding PPC address parity bus if a bit is set For example setting APEO will cause APO to be generated incorrectly If the bit is cleared the PHB will generate correct address parity The Error Enable Register EENAB controls how the PHB is to respond to the detection of various errors In particular each error type can uniquely be programmed to generate a machine check generate an interrupt generate both or generate neither The bits within the ETEST are defined as follows http www motorola com computer literature 2 77 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller DFLT Default PPC Master ID This bit determines which MCHK_ pin will be asserted for error conditions in which the PPC master ID cannot be determined or the PHB was the PPC master For example in the event of a PCI parity error for a transaction in which the PHB s PCI mas
138. able describes the pins and its function for both modes Table 2 9 PCI Arbiter Pin Description Pin Name Pin Reset Internal Arbiter External Arbiter Type Direction Function Direction Function PARBIO Input Input ext req input HAWK gnt PARBII Input Input extreql Input NA PARBI2 Input Input extreq2 Input NA PARBI3 Input Input ext req3 _ Input NA PARBIA Input Input ext req4 Input NA PARBIS5 Input Input extreq5 Input NA PARBI6 Input Input ext req6_ Input NA PARBOO Output Tristate Output ext gnt0_ Output HAWK req_ 1 Output Tristate Output ext gntl Output NA PARBO2 Output Tristate Output ext gnt2_ Output NA PARBO3 Output Tristate Output ext gnt3_ Output NA PARBO4 Output Tristate Output ext gnt4_ Output NA 5 Output Tristate Output ext gnt5_ Output NA PARBO6 Output Tristate Output ext gnt6_ Output NA 2 34 Computer Group Literature Center Web Site Functional Description The Hawk s PCI arbiter has various programming options It supports 3 different priority schemes fixed round robin and mixed mode It also allows various levels of reprioritization programming options within fixed and mixed modes Parking can be programmed to any of the requestors the last requestor or none A special bit is added to hold grant asserted for an agent that initiates a lock cycle Once a lock cycle is detected the grant is held asserted until the PCILOCK pin is released This feature works only when the bit
139. accesses to the corresponding block of SDRAM when set and disables them when cleared Note ram a b c d are located at FEF80010 refer to the section on SDRAM Enable and Size Register Blocks A B C D for more information They operate the same for blocks A D as these bits do for blocks E H ram e f g h 5120 3 These control bits define the size of their corresponding block of SDRAM Note ram a b c d siz0 3 are located at SFEF80010 They operate identically for blocks A D as these bits do for blocks E H The table associated with the previous section on blocks A B C D shows how these bits relate to the block configuration SDRAM Base Address Register Blocks E F G H Address FEF800C8 Bit o A Aen tf eq A 1 ZY AY a a NI ANI NIA NTA AY on Name RAM E BASE RAM F BASE RAM G BASE RAM H BASE Operation READ WRITE READ WRITE READ WRITE READ WRITE Reset 0 PL Writes to this register must be enveloped by a period of time in which accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must have completed before the write starts and none 3 66 Computer Group Literature Center Web Site Programming Model should begin until after the write is done A simple way to do this is to perform at le
140. ache Configuration Data The L2 cache configuration data packet consists of byte fields that show the size organization and type of the L2 cache memory array The following table s further describe the L2 cache memory configuration VPD data packet Table A 4 L2 Cache Configuration Data Byte Field Field Mnemonic Field Description Offset Size Bytes 00 2 L2C MID Manufacturer s Identifier FFFF Undefined Not Applicable 02 2 L2C DID Manufacturer s Device Identifier FFFF Undefined Not Applicable 04 1 L2C DDW Device Data Width for example 8 bits 16 bits 32 bits 64 bits 128 bits 05 1 L2C NOD Number of Devices Present 06 1 L2C Number of Columns Interleaves 07 1 CW Column Width in Bits This will always be a multiple of the device s data width A 6 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Table A 4 L2 Cache Configuration Data Continued Byte Field Field Mnemonic Field Description Offset Size Bytes 08 1 12 _ L2 Cache Type 00 Arthur Backside 01 External 02 In Line 09 1 L2C ASSOCIATE Associative Microprocessor Number If Applicable 0A 1 L2C OPERATIONMODE Operation Mode 00 Either Write Through or Write Back S W Configurable 01 Either Write Through or Write Back H W Configurable 02 Write Through Only 03 Write Back Only http www motorola com com
141. ad and or write check bit operations Clear the dere and rweb bits in the Data Control register QN Un A Perform the desired testing related to the location locations that have had their check bits altered 7 Enable scrub writes by setting the swen bit if it was set before derc Setting derc to one alters SMC operation as follows 1 During reads data is presented to the PPC60x data bus uncorrected from the SDRAM array 2 During single beat writes data is written without correcting single bit errors that may occur on the read portion of the read modify write Check bits are generated for the data being written 3 During single beat writes the write portion of the read modify write happens regardless of whether there is a multiple bit error during the read portion No correction of data is attempted Check bits are generated for the data being written 4 During scrub cycles if swen is set a read writes to SDRAM happens with no attempt to correct data bits Check bits are generated for the data being written derc is useful for initializing SDRAM after power up and for testing SDRAM but it should be cleared during normal system operation apien When apien is set the logging of a PPC60x address parity error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal SMC INT signal to the MPIC is asserted scien When scien is set the rolling over of the SBE COUNT register cau
142. ad from the Status Register will clear this bit i2 ackin This bit is set if the addressed slave device is acknowledged to either a start sequence or data writes from the PC master controller and cleared otherwise The master controller will automatically clear this bit at the beginning of the next valid PC operation i2_cmplt This bitis set after the master controller has successfully completed the requested PC operation and cleared at the beginning of every valid PC operation This bit is also set after power up http www motorola com computer literature 3 63 System Memory Controller SMC 2 Transmitter Data Register Address FEF800A8 Bit CN SF WI WO E gt CO 10 11 12 13 14 15 16 17 18 19 WEL o 30 31 21 22 23 I2 DATAWR Operation READ ZERO READ ZERO READ ZERO READ WRITE Reset X X 0 PL I2 DATAWR The I2 DATAWR contains the transmit byte for PC data transfers If a value is written to 12 DATAWR when the i2_start and i2 enbl bits in the C Control Register are set a start sequence is generated immediately followed by the transmission of the contents of the 12 DATAWR to the responding slave device The I2 DATAWR 24 30 is the device address and the I2 DATAWR 31 is WR RD bit
143. aintain the required EMC safety performance In accordance with European Community directives a Declaration of Conformity has been made and is on file within the European Union The Declaration of Conformity is available on request Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is s
144. alid decoded cycles as a medium responder Target Initiated Termination The PCI Slave normally strives to complete transactions without issuing disconnects or retries There are four exceptions where the PCI Slace performs a disconnect All burst configuration cycles are terminated with a disconnect after one data beat has been transferred All transactions that have a byte enable hole are disconnected All transactions attempting to perform non linear addressing mode are terminated with a disconnect after one data beat is transferred A transaction that crosses from a valid PHB deode space to an invalid PHB decode space is disconnected Note that this does not include crossing contiguous multiple map decoder space in which case PHB does not issue a disconnect There are two exceptions where the PCI Slave performs a retry disconnect with no data transfer While within a lock sequence the PCI Slave retries all non locking masters a Atthe completion of a lock sequence between the times the two locks are released on the PCI bus and the PPC bus accesses to the PCI Slave regardless of who is the master will be retried Delayed Transactions The PCI Slave does not participate in the delayed transaction protocol 2 24 Computer Group Literature Center Web Site Functional Description Fast Back to Back Transactions The PCI Slave supports both of the fundamental target requirements for fast
145. ally place EXTI through EXT15 on SI DAT during the next 15 clock periods This process may be repeated at any rate with the fastest possible next assertion of SI STA on the clock following the sampling of EXT15 Each scan process must always scan exactly 16 external interrupts CSR s Readability Unless explicitly specified all registers are readable and return the last value written The exceptions are the IPI dispatch registers and the EOI registers which return zero s on reads the interrupt source ACT bit which returns current interrupt source status the interrupt acknowledge register which returns the vector of the highest priority interrupt which is currently pending and reserved bits which returns zero s The interrupt acknowledge register is also the only register which exhibits any read side effects Interrupt Source Priority Each interrupt source is assigned a priority value in the range from 0 to 15 where 15 is the highest In order for delivery of an interrupt to take place the priority of the source must be greater than that of the destination processor Therefore setting a source priority to zero inhibits interrupt 2 52 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Functional Description Processor s Current Task Priority Each processor has a task priority register which is set by system software to indicate the relative importance of the task running on that processor
146. always the address internal to the processor the PPC registers are always represented in Big Endian mode This means that the processor s internal view of the PPC registers will appear different depending on which mode the processor is operating in With respect with the PCI bus the configuration registers are always represented in Little Endian mode The CONFIG ADDRESS and CONFIG DATA registers are actually represented in PCI space to the processor and are subject to the Endian functions For example the powerup location of the CONFIG ADDRESS register with respect to the PPC bus is 80000cf8 when the PHB is in Big Endian mode When the PHB is switched to Little Endian mode the 2 40 Computer Group Literature Center Web Site Functional Description CONFIG ADDRESS register with respect to the PPC bus is 80000cfc Note that in both cases the address generated internal to the processor will be 80000cf8 The contents of the CONFIG ADDRESS register are not subject to the Endian function The data associated with PIACK accesses is subject to the Endian swapping function The address of a PIACK cycle is undefined therefore address modification during Little Endian mode is not an issue Error Handling The PHB is capable of detecting and reporting the following errors to one or more PPC masters XBTO PPC address bus time out XDPE PPC data parity error PSMA PCI master signalled master abort PRTA P
147. amp MSATTI 0300 00C2 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 amp MSATT2 0000 0002 FEFF 0058 MSADD3 FE00 FE7F FEFF 005C MSOFF3 amp MSATT3 0200 00CO http www motorola com computer literature 1 9 Board Description and Memory Maps Processor PREP Memory Map The Hawk ASIC can be programmed for PREP compatible memory map The following table shows the PREP memory map of the MVME2400 series from the point of view of the processor Table 1 5 PREP Memory Map Example Processor Address Size Definition Notes Start End 0000 0000 top dram dram size System Memory onboard DRAM 1 8000 0000 1G Zero Based PCI I O Space 2 0000 0000 3FFFF FFFF C000 0000 FCFF FFFF 1G 48M Zero Based PCI ISA Memory Space 2 5 0000 0000 FD00 0000 FEF7 FFFF 40 5M Reserved FEF8 0000 FEF8 FFFF 64K SMC Registers FEF9 0000 FEFE FFFF 384K Reserved FEFF 0000 FEFF FFFF 64K PHB Registers 6 FF00 0000 FF7F FFFF 8M ROM FLASH Bank A 1 3 FF80 0000 8 FFFF IM ROM FLASH Bank B 1 3 FF90 0000 FFEF FFFF 6M Reserved FFFO 0000 FFFF FFFF IM ROM FLASH Bank A or Bank B 4 Notes 1 Programmable via the SMC For the MVME2400 series RAM size is limited to 256MB and ROM FLASH to 9MB 2 Programmable via the Hawk s PHB 3 The actual size of each ROM FLASH bank may vary 4 The first 1 Mbyte of ROM FLASH Bank A appears at this range after a r
148. an be located anywhere in the 32 bit address space PRE Prefetch This bit 15 hard wired to zero to indicate that the MPIC registers are not prefetchable BASE Base Address These bits define the memory space base address of the MPIC control registers The MBASE decoder is disabled when the BASE value is zero http www motorola com computer literature 2 97 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI Slave Address 0 1 2 and 3 Registers Offset PSADDO 80 PSADDI 88 PSADD2 90 PSADD3 98 Bit me 3 3 2 2 2 2 2 2 2 2 2 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 21 1098756254232 10 Name PSADDx START END Operation R W R W Reset 0000 0000 The PCI Slave Address Registers PSADDx contain address information associated with the mapping of PCI memory space to PPC memory space The fields within the PSADDx registers are defined as follows START Start Address This field determines the start address of a particular memory area on the PCI bus which will be used to access PPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address END End Address This field determines the end address of a particular memory area on the PCI bus which will be used to ac
149. an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate in an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do no
150. and stat3 are read only status bits that indicate the levels that were on the RD13 RD14 15 and RD16 signal pins respectively at power up reset They provide a means to pass information to software using pull up pull down resistors on the RD bus or on a buffered RD bus SDRAM Enable and Size Register Blocks A B C D Address FEF80010 Bit SD I A en wo roo o A A eg cq co KR oof a oO a SO A A un a a a Sa SP A IA A A A a A AY eo wu SES SS Ss SFIS nlanln n o ajajajaj o aln l RR ED ni nl nin 4 as ajo CO Urn H E E EIgIB E E E EIEIBH S S SIS SIO GIO Operation gt 2 2 2 2 2 zzz zzz 24 c4 A c2 22 EZ G2 ed CZ GA CZ 22 24 ed 2 ZZ 2 Reset a alallala 04 04 a a A alallala aj alallala a xX xX a x xolololol AMX d x xuoo o o Writes to this register must be enveloped by a period of time in which no accesses to SDRAM occur The requirements of the envelope are that all SDRAM accesses must have completed before the write starts and none should begin until after the write is done A simple way to do this is to perform at least two read
151. ast two read accesses to this or another register before and after the write Additionally sometime during the envelope before or after the write all of the SDRAMs open pages must be closed and the Hawk s open page tracker reset The way to do this is to allow enough time for at least one SDRAM refresh to occur by waiting for the 32 Bit Counter to increment at least 100 times The wait period needs to happen during the envelope RAM E F G H BASE These control bits define the base address for their block s SDRAM RAM E F G H BASE bits 0 7 8 15 16 23 24 3 correspond to PPC60x address bits 0 7 For larger SDRAM sizes the lower significant bits of RAM E F G H BASE are ignored This means that the block s base address will always appear at an even multiple of its size Remember that bit 0 is MSB Note A B C D BASE are located at FEF80018 refer to the section titled SDRAM Base Address Register Blocks A B C D for more information They operate the same for blocks A D as these bits do for blocks E H Also note that the combination of RAM X BASE and ram x siz should never be programmed such that SDRAM responds at the same address as the CSR ROM Flash External Register Set or any other slave on the PowerPC bus http www motorola com computer literature 3 67 System Memory Controller SMC SDRAM Speed Attributes Register Address FEF800D0 Bit 0 1 12 13 5 16 17 18 9 20 21 22
152. aster controller does not respond with an acknowledge This can be http www motorola com computer literature 3 31 System Memory Controller SMC accomplished by setting only the i2 enbl bit in the Control Register before receiving the last data word A stop sequence then must be transmitted to the slave device by first setting the 12 stop and i2_enbl bits in the PC Control Register and then writing a dummy data data don t care to the C Transmitter Data Register The Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will relinquish the ASIC master s possession of the bus 3 32 Computer Group Literature Center Web Site Functional Description SDA DEVICE ADDR WORD ADDR 1 DEVICE ADDR DATA 1 M w A A M R A A START S R C START S K K B K 7 ACK and DATA from Slave Device BEGIN READ 2 STATUS REG LOAD 09 START CONDITION I2C CONTROL REG LOAD DEVICE ADDR WR BIT TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Y LOAD WORD ADDR 1 TO I2C TRANSMITTER DATA REG READ I2C STATUS REG Y LOAD 0B REPEATED START CONDITION TO I2C CONTROL REG L
153. at Read after 1 Beat Read SDRAM Bank Active Page Miss 3 8 Computer Group Literature Center Web Site Functional Description Table 3 1 60x Bus to SDRAM Estimated Access Timing at 100MHz with PC100 SDRAMs CAS latency of 2 Continued Access Type Access Time Comments tB1 tB2 tB3 tB4 1 Read after 1 Beat Read 5 SDRAM Bank Active Page Hit 1 Beat Write after idle 5 SDRAM Bank Active or Inactive 1 Beat Write after 1 Beat Write 13 SDRAM Bank Active Page Miss 1 Beat Write after 1 Beat Write 8 SDRAM Bank Active Page Hit Notes SDRAM speed attributes are programmed for the following CAS latency 2 tRCD 2 CLK Periods 2CLK Periods tRAS 5 CLK Periods tRC 7 CLK Periods tDP 2 CLK Periods and the swr dpl bit is set in the SDRAM Speed Attributes Register The Hawk is configured for external registers on the SDRAM control signals SDRAM Organization The SDRAM is organized as 1 2 3 4 5 6 7 or 8 blocks 72 bits wide with 64 of the bits being normal data and the other 8 being checkbits The 72 bits of SDRAM for each block can be made up of x4 x8 or x16 components or of 72 bit DIMMs that are made up of x4 or x8 components The 72 bit unbuffered DIMMs can be used as long as AC timing is met and they use the components listed All components must be organized with 4 internal banks http www motorola com computer literature 3 9
154. ave function will issue a stall signal to the PCI Master anytime it is currently processing a transaction that must have control of the opposing bus before the transaction can be completed The events that activate this signal are Readcycle with no read data in the FIFO Non posted write cycle Posted write cycle and FIFO full A simultaneous indication of a stall from both slaves means that a bridge lock has happened To resolve this one of the slaves must back out of its currently pending transaction This will allow the other stalled slave to proceed with its transaction When the PCI Master detects bridge lock it will always signal the PPC Slave to take actions to resolve the bridge lock If the PPC bus is currently supporting a read cycle of any type the PPC Slave will terminate the pending cycle with a retry Note that if the read cycle is across a mod 4 address boundary that is from address Ox 02 3 bytes it is possible that a portion of the read could have been completed before the stall condition was detected The previously read data will be discarded and the current transaction will be retried If the PPC bus is currently supporting a posted write transaction the transaction will be allowed to complete since this type of transaction is guaranteed completion If the PPC bus is currently supporting a non posted write transaction the transaction will be terminated with a retry Note A mod 4 non posted write tra
155. back to the PHB The MPIC Interface is controlled exclusively by the PCI Slave The data path function imposes some restrictions on access to the MPIC the PCI Registers and the PPC Registers The MPIC and the PCI Registers are only accessible to PCI originated transactions The PPC Registers are only accessible to PPC originated transactions PHB has several small blocks that support various PPC functions Arbitration is provide by the PPC Arbiter block Cache line locking via PCI Lock is handled by the PPC Lock block Finally a timer function is implemented in the PPC Timer block PHB also provides miscellaneous support for various PCI functions Arbitration on the PCI bus is handled by the PCI Arbiter block Parity checking and generation is handled within the PCI Parity block PPC Bus Interface The PPC Bus Interface is designed to be coupled directly to up to two PPC601 PPC603 or PPC604 microprocessors and one peripheral PPC60x master device It uses a subset of the capabilities of the PPC bus protocol PPC Address Mapping The PHB will map either PCI memory space or PCI I O space into PPC address space using four programmable map decoders These decoders provide windows into the PCI bus from the PPC bus The most significant http www motorola com computer literature 2 5 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller 16 bits of the PPC address are compared with the address range of each map decoder
156. ble write enable etc are changed only while executing initially in the reset vector area SFFF00000 FFFFFFFF Initializing SDRAM Related Control Registers In order to establish proper SDRAM operation software must configure control register bits in Hawk that affect each SDRAM block s speed size base address and enable The SDRAM speed attributes are the same for all blocks and are controlled by one 32 bit register The size base address and enable can be different for each block and are controlled in individual 8 bit registers SDRAM Speed Attributes The SDRAM speed attributes come up from power up reset initialized to the slowest settings that Hawk is capable of This allows SDRAM accesses to be performed before the SDRAM speed attributes are known An example of a need for this is when software requires some working memory that it can use while gathering and evaluating SDRAM device data from serial EEPROM s Once software knows the SDRAM speed parameters for all blocks it should discontinue accessing SDRAM for at least one refresh period before and after it programs the SDRAM speed attribute bits http www motorola com computer literature 3 75 System Memory Controller SMC SDRAM Size The SDRAM size control bits come up from power up reset cleared to zero Once software has determined the correct size for an SDRAM block it should set the block s size bits to match The value programmed into the size bits tel
157. capes 2 39 Figure 2 8 Serial Mode Interrupt tin seed bae teet 2 52 2 9 MPK pi mais Bcc b 2 57 Figure 3 1 Hawk Used with Synchronous DRAM in a System 3 3 Figure 3 2 Hawk s System Memory Controller Internal Data Paths 3 4 Figure 3 3 Overall SDRAM Connections 4 Blocks using Register Buffers 3 5 Figure 3 4 Hawk s System Memory Controller Block Diagram 3 6 Figure 3 5 Programming Sequence for I2C Byte Write 44 2 3 24 Figure 3 6 Programming Sequence for I2C Random Read 3 26 Figure 3 7 Programming Sequence for I2C Current Address Read 3 28 Figure 3 8 Programming Sequence for IAC Page Write iiec eren 3 30 Figure 3 9 Programming Sequence for I2C Sequential Read 3 33 Figure 3 10 Read Write Check bit Data uet ttt tete ess 3 46 Figure 4 1 Architectural Diagram for the Universe 2 222222 4 3 Figure 4 2 UCSR Access Mechanisms ie pe ERR br 4 8 Figure 5 1 MVME2400 Series Interrupt Architecture 5 2 Figure 5 2 PIB Interrupt Handler Block Diagtam 5 5 Piguie 3 3 Mode reiecit ec 5 11 Figure MEDI
158. causes an interprocessor interrupt request to be sent to one or more processors Note that each IPI Dispatch Register has two addresses These registers are considered to be per processor registers and there is one address per processor Reading these registers returns zeros P1 Processor 1 The interrupt is directed to processor 1 PO Processor 0 The interrupt is directed to processor 0 Interrupt Task Priority Registers Offset Processor 0 20080 Processor 1 21080 Bit 3 3 2 2 2 2 2 2 2 2 222 1 1 1 1 1 1 1 1 1 1 10198176 5 4 3 2 0 9 8 7 6 5 4 3 2 101098 7 6 54 321 0 Name INTERRUPT TASK PRIORITY TP Operation R R R R R W Reset 00 00 00 0 F 2 120 Computer Group Literature Center Web Site Registers There is one Task Priority Register per processor Priority levels from 0 lowest to 15 highest are supported Setting the Task Priority Register to 15 masks all interrupts to this processor Hardware will set the task register to F when it is reset or when the Init bit associated with this processor is written to a one Interrupt Acknowledge Registers Offset Processor 0 200A0 Processor 1 210A0 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1
159. ccess Registers PCII O Address Function 0000 0074 NVRAM RTC Address Strobe 0 A7 A0 0000 0075 NVRAM RTC Address Strobe 1 A15 A8 0000 0077 NVRAM RIC Data Register The and is accessed through the above three registers When accessing a NVRAM RTC location follow the following procedure 1 Write the low address 7 0 of the to the NVRAM RTC STBO register 2 Write the high address A15 A8 of the NVRAM to the NVRAM RTC STBI register and 3 Then read or write the NVRAM RTC Data Port Refer to the M48T59 Data Sheet for additional details and programming information VME Registers The following registers provide the following functions for the VMEbus interface a software interrupt capability a location monitor function and a geographical address status For these registers to be accessible from the VMEbus the Universe II ASIC must be programmed to map the VMEbus Slave Image into the appropriate PCI I O address range Refer to the VMEbus Slave Map section for additional details The following table shows the registers provided for various VME functions http www motorola com computer literature 1 27 Board Description and Memory Maps Table 1 17 VME Registers PCI I O Address Function 0000 1000 LM SIG Control Register 0000 1001 LM SIG Status Register 0000 1002 VMEbus Location Monitor Upper Base Address 0000 1003 VMEbus Location
160. cess PPC bus resources The value of this field will be compared with the upper 16 bits of the incoming PCI address 2 08 Computer Group Literature Center Web Site Registers PCI Slave Attribute Offset 0 1 2 and 3 Registers Offset PSOFFO PSATTO 84 PSOFFI PSATTI 8C PSOFF2 PSATT2 94 PSOFF3 PSATT3 9C Bit l ew Of ws en a er AL A Q1 C e A Sa A a ooo xen A Name PSOFFx PSATTx C Z gt e f 5 gt lt gt oS lt mi Bx 2102 04 04 ISI Oa Operation R W 222 2 gt 222Z 212 Reset 0000 The PCI Slave Attribute Registers contain attribute information associated with the mapping of PCI memory space to PPC memory space The fields within the PSATTx registers are defined as follows INV Invalidate Enable If set the PPC master will issue a transfer type code which specifies the current transaction should cause an invalidate for each PPC transaction originated by the corresponding PCI slave The transfer type codes generated are shown in Table 2 5 GBL Global Enable If set the PPC master will assert the pin for each PPC transaction originated by the corres
161. cessor when the priority of the interrupt is greater than the priority contained in the task register for that processor and when the priority of the interrupt is greater than any interrupt which is in service for that processor An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI is received for that interrupt The EOI cycle indicates the end of processing for the highest priority in service interrupt In the distributed delivery mode the interrupt is pointed to one or more processors but it will be delivered to only one processor Therefore for externally sourced or I O interrupts multicast delivery is not supported The interrupt is delivered to a processor when the priority of the interrupt is greater than the priority contained in the task register for that processor and when the priority of the interrupt is greater than any http www motorola com computer literature 2 55 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller interrupt which is in service for that processor and when the priority of that interrupt is the highest of all interrupts pending for that processor and when that interrupt is not in service for the other processor If both destination bits are set for each processor the interrupt will be delivered to the processor that has a lower task register priority Note due to a deadlock condition that can occur when the task r
162. chronous debug port via RJ45 connector on front panel Ethernet I O 10 Base T 100 Base Tx connections via RJ45 connector on front panel 1 2 Computer Group Literature Center Web Site System Block Diagram Table 1 1 MVME240x Features Continued Feature PCI interface Description Two IEEE P1386 1 PCI Mezzanine Card PMC slots for one double width or two single width PMCs Front panel and or VMEbus P2 I O on both PMC slots One 114 pin Mictor connector for optional PMCspan expansion module VMEbus interface VMEbus system controller functions 64 bit PCI Universe IT VMEbus to local bus interface A32 A24 A16 D64 MBLT D32 D16 D08 Master and Slave System Block Diagram MVME2400 is a VMEbus based single slot Single Board Computer based on the PowerPC MPC750 processor The MVME2400 features two PCI Mezzanine Card slots an Ethernet Interface serial port up to 9MB of boot FLASH and up to 256MB of ECC protected system RAM The Hawk ASIC controls all of the functions previously controlled by the Raven Falcon chipsets in addition to new functionality The Hawk provides the interface to the PowerPC 60x Bus the interface to all on board SDRAMs error notification for SDRAMs the interface to ROM Flash the I2C master the external status control register support synchronous PPC60x PCI clock ratio support the interface to the PCI and an interrupt controller PCI devices include V ME Eth
163. cycle The SMC INT internal signal and the MCHKO pin are the only non polled notification that a multiple bit error has occurred The SMC does Caution TEA as a result of a multiple bit error In fact the SMC does not have a TEA_ signal pin and it assumes that the system does not implement TEA 3 48 Computer Group Literature Center Web Site Programming Model Error Logger Register Address FEF80030 Bit I gt 4 ON OD IQ IN IN IN IN IN IN IN Wo SIRE TN gt CA Os YI 100 JW JO JY ON 00 Name B 0 2 ERR SYNDROME EE 8 SBE COUNT xd mu amp 6 Operation 5 7 7 READ ONLY READ WRITE R bo OP op 4 elog When set elog indicates that a single or a multiple bit error has been logged by the SMC If elog is set by a multiple bit error then no more errors will be logged until software clears it If elog is set by a single bit error then no more single bit errors will be logged until software clears it however if elog is set by a single bit error and a multiple bit error occurs the multiple bit error will be logged and the single bit error information overwritten elog can only be set by the logging of an error and cleared by
164. d by i2_datin 1 in the IC Status Register the system software may then read the data by polling the PC Receiver Data Register The master controller does not acknowledge the read data for a single byte transmission on the PC bus but must complete the transmission by sending a stop sequence to the slave device This can be accomplished by first setting the 12 stop 12 enbl bits in the I7C Control Register and then writing a dummy data data don t care to the C Transmitter Data Register The PC Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will relinquish the ASIC master s possession of the PC bus http www motorola com computer literature 3 27 System Memory Controller SMC DEVICE ADDR DATA of last ADDR 1 M R A N SDA START S D O STOP K A A N K ACK and DATA from Slave Device BEGIN READ 2 STATUS REG LOAD 09 START CONDITION I2C CONTROL REG LOAD DEVICE ADDR RD BIT I2C TRANSMITTER DATA REG READ I2C STATUS REG N Y LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG READ I2C STATUS REG MPLT DATIN 1 7 READ I2C RECEIVER DATA REG LOAD 05 STOP CONDITION TO I2C CONTROL REG LOAD DUMMY DATA TO I2C TRANSMITTER DATA REG
165. d to abort the transfer after a software wait loop 1ms has been expired Figure 3 6 Programming Sequence for 2 Random Read 3 26 Computer Group Literature Center Web Site Functional Description 2 Current Address Read The slave device should maintain the last address accessed during the last read or write operation incremented by one The first step in the programming sequence should be to test the 12 cmplt bit for the operation complete status The next step is to initiate a start sequence by first setting the i2 start and 12 enbl bits in the 2C Control Register and then writing the device address bits 7 1 and read bit bit 0 1 to the 2C Transmitter Data Register The i2_cmplt bit will be automatically clear with the write cycle to the PC Transmitter Data Register The PC Status Register must now be polled to test the i2_cmplt i2_ackin bits The i2 cmplt bit becomes set when the device address and read bit have been transmitted and the i2_ackin bit provides status as to whether or not a slave device acknowledged the device address With the successful transmission of the device address the I7C master controller writes dummy value data don t care to the Transmitter Data Register This causes the PC master controller to initiate a read transmission from the slave device Again i2 cmplt bit must be tested for proper response After the PC master controller has received a byte of data indicate
166. d to mapping MPIC into PCI Memory space The mapping of PPC address space is handled by device specific registers located above the 64 byte header These control registers support a mapping scheme that is functionally similar to the PCI to PPC mapping scheme described in the section titled PPC Address Mapping PPC Bus Address Space The PHB will map PPC address space into PCI Memory space using four programmable map decoders The most significant 16 bits of the PCI address is compared with the address range of each map decoder and if the address falls within the specified range the access is passed on to the PPC bus An example of this is shown in the following figure http www motorola com computer literature 2 19 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI Bus Address 18 0 8 0 1 2 3 4 Decodeis gt lt Y PSADDx Register E 0 8 0 9 0 0 0 1 Figure 2 4 PCI to Address Decoding There are no limits imposed by the PHB on how large of an address space a map decoder can represent There is a lower limit of a minimum of 64 KBytes due to the resolution of the address compare logic For each map there is an independent set of attributes These attributes are used to enable read accesses enable write accesses enable write posting and define the PPC bus transfer characteristics 2 20 Computer Group Literature Center Web Site Functional Descriptio
167. device address With the successful transmission of the device address the word address will be loaded into the Transmitter Data Register to be transmitted to the slave device Again i2_cmplt and i2_ackin bits must be tested for proper response After the word address is successfully transmitted the next data loaded into the C Transmitter Data Register will be transferred to the address location selected previously within the slave device After i2_cmplt and i2_ackin bits have been tested for proper response a stop sequence must be transmitted to the slave device by first setting the i2_stop and i2_enbl bits in the PC Control Register and then writing a dummy data data don t care to the Transmitter Data Register The Computer Group Literature Center Web Site Functional Description Status Register must now be polled to test i2 cmplt bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master s possession of the PC bus http www motorola com computer literature 3 23 System Memory Controller SMC DEVICE ADDR WORD ADDR DATA M SDA START S R C C STOP B K K A from Slave Device BEGIN 0 ox READ 2 STATUS REG LOAD 09 START CONDITION I2C CONTROL REG
168. dge amp Multi Processor Interrupt Controller Parity The PCI Master supports address parity generation data parity generation and data parity error detection Cache Support The PCI Master does not participate in the PCI caching protocol Generating PCI Cycles There are four basic types of bus cycles that can be generated on the PCI bus Memory and Configuration Special Cycle Interrupt Acknowledge Generating PCI Memory and I O Cycles Each programmable slave may be configured to generate PCI I O or memory accesses through the MEM and IOM fields in its XSATTx register as shown below MEM IOM PCI Cycle Type Memory Contiguous I O Spread I O If the MEM bit is set the PHB performs Memory addressing on the PCI bus The PHB takes the PPC bus address applies the offset specified in the XSOFFx register and maps the result directly to the PCI bus The IBM CHRP specification describes two approaches for handling PCI I O addressing contiguous or spread address modes When the MEM bit 16 cleared the bit is used to select between these two modes whenever a PCI I O cycle is to be performed 2 30 Computer Group Literature Center Web Site Functional Description The PHB performs contiguous I O addressing when the MEM bit is clear and the IOM bit is clear The PHB takes the PPC address apply the offset specified in the XSOFFXx register and map the result di
169. e 1 17 1 28 Table 1 18 Eiulated 78536 Access 1 33 Table t 19 235304 10 Port Pms Gries Wises 1 33 Table 2 1 Slave Response Command 2 22 2 2 2 8 Table 2 2 PPC Master Transaction Profiles and Starting Offsets 2 11 Table 2 3 PPC Master Write Posting Options esee etre aet 2 12 Table 2 4 PPC Master Read Ahead Options uode eret etti epe iae 2 13 Vale 2 3 PPC Master Transfer TUBES usse ene 2 14 Table 2 6 PPC Arbiter Pin Assignments 2 15 Table 2 7 PCI Slave Response Command Types sese 2 23 Table 2 8 PCI Master Command Colts eoe ic ross Reto Hae ME noa 2 27 Table 2 9 PCI Arbiter Pin Descciptlon 2 34 Table 2 10 Fixed Mode Priority Level Setting coro orn rU E Ge a aane 2 35 Table 2 11 Mixed Mode Priority Level Setting nee ee 2 36 Table 2 12 aad ener ee p e RP Me anes 2 37 Table 2 13 Address Modification for Little Endian Transfers 2 40 Table 2 14 WDTXCNTL Programing iicet oriri puso ta rib perpe Rp ku pe 2 44 Table 2 15 PHB Blane ware C ODE BREL
170. e Universe II ASIC 4 Programmable mapping via the Special Slave Image 51 51 in the Universe II ASIC The following table shows the programmed values for the associated PHB PCI registers for the PREP compatible memory map Table 1 11 PHB PCI Register Values for PREP Memory Map Configuration Configuration Register Value Address Offset Register Name 14 MPIC MBASE 00 0000 80 PSADDO 8000 FBFF 84 5 amp PSATTO 8000 00 88 PSADDI 0000 0000 8C PSOFFI amp PSATTI 0000 0000 1 16 Computer Group Literature Center Web Site Programming Model Table 1 11 PHB PCI Register Values for PREP Memory Map Continued Configuration Configuration Register Value Address Offset Register Name 90 PSADD2 0000 0000 94 PSOFF2 amp PSATT2 0000 0000 98 PSADD3 0000 0000 9C PSOFF3 amp PSATT3 0000 0000 The next table shows the programmed values for the associated Universe II PCI registers for the PCI PREP memory map Table 1 12 Universe PCI Register Values for PREP Memory Configuration Configuration Register Value Address Offset Register Name 100 LSIO CTL C082 5100 104 LSIO BS 0100 0000 108 LSIO BD 3000 0000 10C LSIO TO XXXX 0000 114 LSII1 C042 5100 118 LSII BS 3000 0000 11C 151 BD 3800 0000 120 151 TO XXXX 0000 128 LSD 0000 0000 12C LSD BS XXXX XXXX 130 LSD BD XX
171. e MPIC a typical value would be 7de290 which is 66 8 MHz or 8 25 MHz Note Clock frequencies on the Hawk are derived from the PCI clock 2 112 Computer Group Literature Center Web Site Registers Timer Current Count Registers Offset Timer 0 01100 Timer 1 01140 Timer 2 01180 Timer 3 011CO Bit 332 22 22 22 22 2 1 1 1 1 1 1 1 1 1 1 10987625432 1 OF 9 8 7 6 5 4 3 21 1 OF of gt 76 5 4 3 21 10 Name TIMER CURRENT COUNT CC Operation R Reset 00000000 T Toggle This bit toggles whenever the current count decrements to zero The bit is cleared when a value is written into the corresponding base register and the CI bit of the corresponding base register transitions from a 1 to a 0 CC Current Count The current count field decrements while the Count Inhibit bit is the Base Count Register is zero When the timer counts down to zero the Current Count register is reloaded from the Base Count register and the timer s interrupt becomes pending in MPIC processing http www motorola com computer literature 2 113 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Timer Basecount Registers Offset Timer 0 01110 Timer 1 01150 Timer 2 01190 Timer 3 011DO Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 I 1 0 9 8 7 6 5 4 3 2 1 OF 9 8
172. e PPC60x bus it may be necessary to tune the read ahead mechanism to compensate for this Additional tuning of the read ahead function is controlled by the RXFT RMFT Read Any FIFO Threshold Read Multiple FIFO Threshold fields in the PSATTX registers These fields can be used to characterize when the PPC Master will continue reading ahead with respect to the PCI FIFO threshold The FIFO threshold should be raised to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus Table 2 4 summarizes the PHB available read ahead options Computer Group Literature Center Web Site Functional Description Table 2 4 PPC Master Read Ahead Options RXFT RAEN PCI Initial Continuation Subsequent Command Read Size Read Size 0 Read lcacheline PCI received 1 cache line Read Line data and FRAME asserted 00 1 Read 4 cache lines FIFO lt 0 FIFO gt 4 Read Dine cache lines cache lines XX 00 Read Multiple 01 XX 1 Read 4 cache lines FIFO lt 1 FIFO gt 4 Read Dine cache line cache lines 01 Read Multiple 10 XX 1 Read 4 cache lines FIFO lt 2 FIFO gt 4 Read lane cache lines cache lines XX 10 Read Multiple 11 Read 4 cache lines FIFO lt 3 FIFO gt 4 Reading cache lines cache lines XX 11 Read Multiple Upon completion of a prefetched read transaction any residual read data left within the PCI FIFO
173. e SMC the SDRAM the ROM FLASH and the system registers always appear as Big Endian MPIC s Involvement Since PCI is Little Endian the MPIC performs byte swapping in both directions from PCI to memory and from the processor to PCI to maintain address invariance when it is programmed to operate in Big Endian mode with the processor and the memory sub system In Little Endian mode it reverse rearranges the address for PCI bound accesses and rearranges the address for memory bound accesses from PCI In this case no byte swapping is done PCI Domain PCI SCSI PCI Ethernet The PCI bus is inherently Little Endian and all devices connected directly to PCI will operate in Little Endian mode regardless of the mode of operation in the processor s domain The MVME2400 series does not implement SCSI Ethernet is byte stream oriented with the byte having the lowest address in memory being the first one to be transferred regardless of the endian mode Since address invariance is maintained by the Hawk in both Little Endian http www motorola com computer literature 5 13 Programming Details PCI Graphics and Big Endian mode there should be no endian issues for the Ethernet data Big Endian software must still however be aware of the byte swapping effect when accessing the registers of the PCI Ethernet device The effects of byte swapping on Big Endian software must be considered by Big Endian software Note There ar
174. e error occurred Transfer Type This field contains the transfer type of the transfer in which the error occurred If the PSMA or PRTA bits are set the register is defined in the following table 2 82 Computer Group Literature Center Web Site Registers Address FEFF002C Bit 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 0 1 2 3 41 51617 8910112314567 8 9 OF 1 2 3 4 5 6 7 8 9 0 Name EATTR z ollas ss 5 BIEBOwOI IOJO lt IK IK IK lt IK IK IK lt lt lt amp lt WIN o Operation R R 4 a Reset 00 00 Slolojololololololololololololo WP Write Post Completion This bit is set when the PCI master detects an error while completing a write post transfer XIDx PPC Master ID This field contains the ID of the PPC master which originated the transfer in which the error occurred The encoding scheme is identical to that used in the GCSR register PCI Command This field contains the PCI command of the PCI transfer in which the error occurred BYTEXx PCI Byte Enable This field contains the PCI byte enables of the PCI transfer in which the error occurred A set bit designates a selected byte PCI Interrupt Acknowledge Register The PCI Interrupt Acknowledge Register PIACK is a read only register tha
175. e lock resolution Between PCI writes the PPC Master will be taking PPC60x bus bandwidth trying to empty write posted data which will further hamper the ability of the processor to complete its read transaction PHB offers an optional speculative PCI request mode that helps the processor complete read cycles from PCI space If a bridge lock resolution cycle happens when the PPC Slave is hosting a compelled cycle the PCI Master will speculatively assert a request on the PCI bus Sometime later when the processor comes back a retries the compelled cycle the results of the PCI Master holding the request will increase the chance of the processor successfully completing its cycle PCI speculative requesting will only be effective if the PCI arbiter will at least some times consider the PHB to be a higher priority master than the master performing the PPC60x bound write cycles The PCI Master obeys the PCI specification for benign requests and will unconditionally remove speculative request after 16 clocks The PHB considers the speculative PCI request mode to be the default mode of operation If this is not desired then the speculative PCI request mode can be disable by changing the SPRQ bit in the HCSR Transaction Ordering All transactions will be completed on the destination bus in the same order that they are completed on the originating bus A read or a compelled write transaction will force all previously issued write posted transactio
176. e no graphics the MVME2400 series boards Universe Il s Involvement Since PCI is Little Endian and the VMEbus is Big Endian the Universe performs byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the mode of operation in the processor s domain VMEbus Domain The VMEbus is inherently Big Endian and all devices connected directly to VMEbus are expected to operate in Big Endian mode regardless of the mode of operation in the processor s domain In Big Endian mode byte swapping is performed by the Universe II and then by the MPIC The result has the desirable effect by being transparent to the Big Endian software In Little Endian mode however software must be aware of the byte swapping effect from the Universe II and the address reverse rearranging effect of the MPIC Computer Group Literature Center Web Site ROM Flash Initialization ROM Flash Initialization There are two methods used to inject code into the Flash in Bank A 1 In circuit programming and 2 Loading it from the ROM Flash Bank B For the second method the hardware must direct the SMC to map the FFF00000 FFFFFFFF address range to Bank B following a hard reset Bank A then can be programmed by code from Bank B Software can determine the mapping of the FFF00000 FFFFFFFF address range by examining the rom b rv bit in the SMC s Rom B Base Size Register Table 5 6 ROM FLAS
177. e section titled PCI Arbiter for more information The bits within the PARB register are defined as follows PRIx Priority This field is used by the PCI Arbiter to establish a particular bus priority scheme The encoding of this field is shown in the following table PRI Priority Scheme 00 Fixed 01 Round Robin 10 Mixed 11 Reserved 2 72 Computer Group Literature Center Web Site Registers PRKx Parking This field is used by the PCI Arbiter to establish a particular bus parking scheme The encoding of this field is shown in the following table Parking Scheme 0000 Park on last master 0001 Park always on PARB6 0010 Park always on PARB5 0011 Park always on PARBA 0100 Park always on PARB3 0101 Park always on PARB2 0110 Park always on PARBI 0111 Park always on PARBO 1000 Parkalways on HAWK 1111 HIERx Hierarchy This field is used by the PCI Arbiter to establish a particular priority ordering when using a fixed or mixed mode priority scheme When using the fixed priority scheme the encoding of this field is shown in the table below HIER Priority ordering highest to lowest 000 PARB6 PARBS gt PARB4 PARB3 PARB2 PARBI PARBO gt HAWK 001 HAWK gt PARB6 gt PARBS gt PARB4 gt PARB3 gt PARB2 gt PARBI gt PARBO 010 PARBO gt HAWK gt PARB6 gt PARBS gt PARB4 gt PAR
178. e the PCI Slave to stall if the PCI FIFO gets full If the PCI Slave is continuously stalling during write posted transactions then further tuning might be needed This can be accomplished by changing the WXFT Write Any FIFO Threshold field within the http www motorola com computer literature 2 11 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PSATTx registers to recharacterize PHB write posting mechanism The FIFO threshold should be lowered to anticipate any additional latencies incurred by the PPC Master on the PPC60x bus The following table summarizes the PHB available write posting options Table 2 3 PPC Master Write Posting Options WXFT WPEN PPC60x Start PPC60x Continuation XX 0 FIFO 1 dword FIFO 1 dword 00 1 FIFO gt 4 cache lines FIFO gt 1 cache line 01 1 FIFO gt 3 cache lines FIFO gt 1 cache line 10 1 FIFO gt 2 cache lines FIFO gt 1 cache line 11 1 FIFO gt 1 cache lines FIFO gt 1 cache line The PPC Master has an optional read ahead mode controlled by the RAEN bit in the PSATTx registers that allows the PPC Master to prefetch data in bursts and store it in the PCI FIFO The contents of the PCI FIFO will then be used to satisfy the data requirements for the remainder of the PCI read transaction The PHB read ahead mechanism has been tuned for maximum efficiency during typical operation conditions If excessive latencies are encountered on th
179. e transactions write data is captured from the PPC60x bus within the PPC Input block This data is fed into the PPC FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus During read transactions read data is captured from the PCI bus within the PCI Input block From there the data is fed into the PPC FIFO The PPC Output block removes the data from the FIFO and presents it to the 60 bus All PCI originated PPC bound transactions utilize the PCI Slave and PPC Master functions for maintaining bus tracking and control During both write and read transactions the PCI Slave will place command information 24 Computer Group Literature Center Web Site Functional Description into the PCI FIFO The PPC Master will draw this command information from the PCI FIFO when it is ready to process the transaction During write transactions write data is captured from the PCI bus within the PCI Input block This data is fed into the PCI FIFO The PPC Output block removes the data from the FIFO and presents it to the PPC60x bus During read transactions read data is captured from the PPC60x bus within the PPC Input block From there the data is fed into the PCI FIFO The PCI Output block removes the data from the FIFO and presents it to the PCI bus The MPIC is hosted by the PHB A custom MPIC Interface is provided to allow write data and control to be passed to the MPIC and to allow read data to be passed
180. ections titled SDRAM Enable and Size Register Blocks A B C D and SDRAM Enable and Size Register Blocks E F G H for more information 10 Make sure the software is no longer using SDRAM and disable the block that was being used 11 Wait for at least one SDRAM refresh to complete simple way to do this is to wait for the 32 bit counter to increment at least 100 times Refer to the section titled 32 Bit Counter for more http www motorola com computer literature 3 81 System Memory Controller SMC 12 information Note that the refdis control bit must not be set in the ECC Control Register Now that at least one refresh has occurred since SDRAM was last accessed it is okay to write to the SDRAM control registers a Program the SDRAM Speed Attributes Register using the information obtained in steps 3 and 4 and the fact that the swr dp and tdp bits should be set to 1 s Program the SDRAM Base Address Register Blocks A B C D and the SDRAM Base Address Register Blocks E F G H Each block s base address should be programmed so that it is an even multiple of its size The size information was obtained in Step 5 If the isa hole bit is to be set this may be a good time to do that also Refer to the Revision ID General Control Register section for more information Program the SDRAM Enable and Size Register Blocks A B C D and the SDRAM Enable and Size Register Blocks E F G H Use the information from s
181. eed attributes size and base address have been programmed and time for at least one refresh has passed it can be enabled Computer Group Literature Center Web Site Software Considerations SDRAM Control Registers Initialization Example The following is a possible sequence for initializing SDRAM control registers 1 Get a small piece of SDRAM for software to use for this routine optional This routine assumes that SDRAM related control bits are still at the power up reset default settings We will use a small enough piece of SDRAM that the address signals that are affected by SDRAM size will not matter For each SDRAM block a Setthe block s base address to some even multiple of 32Mbytes Refer to the section entitled SDRAM Base Address Register Blocks A B C D for more information b Set the block s size to 4Mx16 and enable it Refer to the section entitled SDRAM Enable and Size Register Blocks A B C D for more information c Test the first IMbyte of the block d If the test fails disable the block clear its size to OMbyutes disable it and then repeat steps 1 through 5 with the next block If the test passes go ahead and use the first 1M of the block 2 Using the bus determine which memory blocks are present Using the addressing scheme established by the board designer probe for SPD s to determine which blocks of SDRAM are present SPD byte 0 could be used to determine SPD presence SPD Byte 5
182. egister SMC 3 61 I2C Control Register SMC 3 62 I2C Current Address Read Hawk 3 27 I2C EEPROMs 3 76 I2C Interface Hawk 3 21 I2C Page Write Hawk 3 29 I2C Random Read Hawk 3 25 I2C Receiver Data Register SMC 3 65 I2C Sequential Read Hawk 3 31 I2C Status Register SMC 3 63 I2C Transmitter Data Register SMC 3 64 initializing SDRAM related control registers 3 75 IN 4 Computer Group Literature Center Web Site Interprocessor Interrupt Dispatch Registers 2 120 Interrupt Acknowledge Registers 2 121 Interrupt Controller features 2 2 interrupt handling on MVME2400 5 2 Interrupt Task Priority Registers 2 120 interrupter 4 6 interrupter and interrupt handler 4 6 interrupts Hawk MPIC 5 3 introduction Hawk PHB MPIC 2 1 PHB MPIC 2 1 programming details for Hawk 5 1 SMC 3 1 Universe II 4 1 IPI Vector Priority Registers 2 111 ISA Bus resources available 1 25 ISA DMA channels 1 34 5 7 ISA local resource bus 1 25 L L2 cache support SMC 3 14 L2CLM 3 14 Large Scale Integration LSI 1 1 latency PCI Slave 2 25 Little Endian mode of PPC devices 2 39 little endian mode 5 12 LM SIG Control Register 1 28 LM SIG Status Register 1 29 Location Monitor Lower Base Address Reg ister 1 31 Location Monitor Upper Base Address Reg ister 1 30 Lock Resolution programmable 2 46 manual terminology x manufacturers documents 1 map decoders PPC to PCI 2 7 mapping PPC address 2 5 master initiated termination 2 28
183. egister priorities for each processor are the same and both processors are targeted for interrupt delivery the interrupt will be delivered to processor or processor 1 as determined by the TIE mode Additionally If priorities are set the same for competing interrupts external int 0 is given the highest priority in hardware followed by external int 1 through 15 and then followed by timer 0 through timer 3 and followed by IPI 0 and 1 For example if both extO and ext1 interrupts are pending with the same assigned priority during the following interrupt acknowledge cycles the first vector returned shall be that of ext0 and then 1 This is an arbitrary choice Block Diagram Description The description of the block diagram shown in Figure 2 9 focuses on the theory of operation for the interrupt delivery logic If the preceding section is a satisfactory description of the interrupt delivery modes and the reader is not interested in the logic implementation this section can be skipped 2 56 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Functional Description Program Visible Registers Int signals Y IPR Interrupt Interrupt Selector 1 Selector 0 IRR 1 IRR 0 Y Y ISR 1 ISR 0 Y Y Interrupt Router INT 1
184. elated Documentation Table B 3 Related Specifications Continued Document Title and Source Publication Number IEEE PCI Mezzanine Card Specification PMC P1386 1 Draft 2 0 Institute of Electrical and Electronics Engineers Inc Publication and Sales Department 345 East 47th Street New York New York 10017 21633 Telephone 1 800 678 4333 Peripheral Component Interconnect PCI Local Bus Specification PCI Local Bus Revision 2 0 Specification PCI Special Interest Group P O Box 14070 Portland Oregon 97214 4070 Marketing Help Line Telephone 503 696 6111 Document Specification Ordering Telephone 1 800 433 5177 503 797 4207 FAX 503 234 6762 PowerPC Reference Platform PRP Specification MPR PPC RPU 02 Third Edition Version 1 0 Volumes I and II International Business Machines Corporation Power Personal Systems Architecture 11400 Burnet Rd Austin TX 78758 3493 Document Specification Ordering Telephone 1 800 PowerPC Telephone 1 800 769 3772 Telephone 708 296 9332 B 6 Computer Group Literature Center Web Site Related Specifications Table B 3 Related Specifications Continued Document Title and Source PowerPC Microprocessor Common Hardware Reference Platform A System Architecture CHRP Version 1 0 Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com OR AFD
185. ents Computer Group Literature Center Web Site Functional Description Command Types The following table shows which types of PCI cycles the slave has been designed to accept Table 2 7 PCI Slave Response Command Types Command Type Slave Response Interrupt Acknowledge No Special Cycle No I O Read Yes I O Write Yes Reserved No Reserved No Memory Read Yes Memory Write Yes Reserved No Reserved No Configuration Read Yes Configuration Write Yes Memory Read Multiple Yes Dual Address Cycle No Memory Read Line Yes Memory Write and Invalidate Yes Addressing The PCI Slave will accept any combination of byte enables during read or write cycles During write cycles a discontinuity that is a hole in the byte enables forces the PCI Slave to issue a disconnect During all read cycles the PCI Slave returns an entire word of data regardless of the byte enables During I O read cycles the PCI Slave performs integrity checking of the byte enables against the address being presented and assert SERR in the event there is an error http www motorola com computer literature 2 23 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode The PCI Slave performs a disconnect with data if any other mode of addressing is attempted Device Selection The PCI slave will always respond v
186. er or not a slave device acknowledged the device address With the successful transmission of the device address the word address will be loaded into PC Transmitter Data Register to be transmitted to the slave device Again i2_cmplt and i2_ackin bits must be tested for proper response At this point the slave device is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the i2_start and i2_enbl bits in the PC Control Register and then writing the device address bits 7 1 and read bit bit 021 to the PC Transmitter Data Register After 12 cmplt and 12 ackin bits have been tested for proper response the master controller writes a dummy value data don t care to the Transmitter Data Register This causes the PC master controller to initiate a read transmission from the slave device Again i2 cmplt bit must be tested for proper response After the PC master controller has received a byte of data indicated by i2_datin 1 in the IC Status Register the system software may then read the data by polling the PC Receiver Data Register The master controller does not acknowledge the read data for a single byte transmission on the bus but must complete the transmission by sending a stop sequence to the slave device This can be accomplished by first setting the 12 stop and i2 enbl bits in the I7C Control Register and then writing a dummy data data don t
187. ernet and two PMC slots Standard I O functions are provided by the UART device which resides on the ISA bus The NVRAM RTC also resides on the ISA bus The general system block diagram for MVME2400 series is shown below http www motorola com computer literature 1 3 Board Description and Memory Maps Debug Connector m SDRAM 2 2 64 128 256 L2 Cache m S FLASH 5 1MB to 9 gt S System Processor z Registers MPC750 X x Clock Hawk ASIC Generator System Memory Controller SMC S and PCI Host Bridge PHB a L E S 5 33MHz 32 64 bit PCI Local Bus E 3 S 2 A Ethernet PIB VME Bridge W83c553 Universe II ISA d Registers egisters Buffers RTC NVRAM WD M48T59 ISA Bus TL16C550 UART mn PMC Front IO Slot2 51011 Front IO Front Panel VME PI Wo 2067 9708 Figure 1 1 MVME2400 Series System Block Diagram 1 4 Computer Group Literature Center Web Site Functional Description Functional Description Overview The MVME2400 series is a family of single slot VME processor modules It consists of the MPC750 processor and L2 cache that directly connects to the MPC750 the Hawk ASIC which is made up of the PCI Bridge PHB the Multi Processor Interrupt
188. ers PCI to PPC 2 5 address mapping PPC 2 5 address modification for little endian trans fers 2 40 address offsets as part of map decoders 2 21 address parity PPC60x 3 13 Address Parity Error Address Register SMC 3 71 Address Parity Error Log Register SMC 3 70 address pipelining 3 7 address transfers 3 12 address data stepping 2 29 addressing to PCI Slave 2 23 addressing mode for PCI Master 2 28 PCI Slave limits 2 24 Application Specific Integrated ASIC 1 1 arbiter as controlled by the XARB register 2 16 Hawk s internal 2 34 PPC 2 15 2 16 arbitration from PCI Master 2 29 arbitration latency 2 29 arbitration parking 2 37 architectural diagram for the Universe 4 3 architectural overview 2 4 Universe II 4 2 ARTRY 3 14 assertion definition x asterisk as denotes signal level ix Circuit big to little endian data swap 2 39 big endian x big endian mode 5 11 binary number ix bit descriptions 3 38 bit ordering convention SMC 3 1 block diagram 2 3 SMC poriton of Hawk 3 2 block diagrams IN 1 xXmoz Index Hawk with SDRAMs 3 2 board configuration information 1 23 bridge PHB viii 2 1 PowerPC to PCI Local Bus Bridge viii 2 1 bus cycle types on the PCI bus 2 30 Bus Hog PPC master device 2 14 bus interface 60x to SMC 3 12 byte ordering x byte definition x C cache coherency SMC 3 14 cache coherency restrictions 3 14 cache support 2 26 2 30 CHRP memory map PHB PCI Register Values
189. ers return a value of 0 on reads writes complete Caution normally http www motorola com computer literature Programming Details Introduction This chapter contains details of several programming functions that are not tied to any specific ASIC chip PCI Arbitration arbitration can be performed by either the Hawk ASIC default or the PIB The Hawk ASIC supports eight external PCI masters This includes Hawk and 7 external PCI masters The arbitration assignments on the MVME2400 series when the Hawk is the PCI arbiter are as follows Table 5 1 Hawk Arbitration Assignments PCI Bus Request PCI Master s Request 0 Hawk ASIC Request 1 PIB Request 2 Universe II ASIC VMEbus Request 3 PMC Slot 1 Request 4 PMC Slot 2 Request 5 PCIX Slot Request 6 Ethernet 5 1 Programming Details Interrupt Handling The interrupt architecture of the MVME2400 series SBC is shown in the following figure PIB 8529 Pair Processor Hawk MPIC Processor SERR amp PERR_ PCI Interrupts ISA Interrupts 11559 00 9609 Figure 5 1 MVME2400 Series Interrupt Architecture 5 2 Computer Group Literature Center Web Site Interrupt Handling Hawk MPIC The Hawk ASIC has a built in interrupt controller that meets the Multi Processor Interrupt Controller MPIC Specification This MPIC supports up to two processors and 16 external interrupt
190. eset if the rom b rv control bit is cleared If the rom b rv Computer Group Literature Center Web Site Programming Model control bit is set then this address range maps to ROM FLASH Bank B 5 This range can be mapped to the VMEbus by programming the Universe II ASIC accordingly 6 The only method to generate a PCI Interrupt Acknowledge cycle 8259 IACK is to perform a read access to the PHB s PIACK register at OXFEFF0030 The following table shows the programmed values for the associated PHB registers for the processor PREP memory map Table 1 6 PHB Register Values for PREP Memory Map Address Register Name Register Value FEFF 0040 MSADDO C000 FCFF FEFF 0044 MSOFFO amp MSATTO 4000 00C2 FEFF 0048 MSADDI 0000 0000 FEFF 004C MSOFFI amp MSATTI 0000 0002 FEFF 0050 MSADD2 0000 0000 FEFF 0054 MSOFF2 amp MSATT2 0000 0002 FEFF 0058 MSADD3 8000 BFFF FEFF 005C MSOFF3 amp MSATT3 8000 00 0 PCI Configuration Access PCI Configuration accesses are accomplished via the CONFIG ADD and CONFIG DAT registers These two registers are implemented by the PHB portion of the Hawk ASIC In the CHRP memory map example the CONFIG ADD and CONFIG DAT registers are located at OXFE000CF8 and OxFEO00CFC respectively With the PREP memory map the CONFIG ADD register and the CONFIG DAT register are located at 0 80000 8 and 0 80000 respectively http www motorola
191. et and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms and 1 are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions Xxiv Conventions Used This Manual The following typographical conventions are used in this document bold is used for user input that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts Enter Return or CR lt gt represents the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d Board Description and Memory Maps Introduction This manual provides programming infor
192. etermined the XID field 1s used For errors not associated with a particular PPC master or associated with masters other than processor 0 1 or 2 the DFLT bit is used One example of an error condition which cannot be associated with a particular PPC master would be a PCI system error Watchdog Timers PHB features two watchdog timers called Watchdog Timer 1 WDT1 and Watchdog Timer 2 WDT2 Although both timers are functionally equivalent each timer operates completely independent of each other WDTI and WDT 2 are initialized at reset to a count value of 8 seconds and 16 seconds respectively The timers are designed to be reloaded by software at any time When not being loaded the timer will continuously decrement itself until either reloaded by software or a count of zero is reached If a timer reaches a count of zero an output signal will be asserted and the count will remain at zero until reloaded by software or PHB reset is asserted External logic can use the output signals of the timers to generate interrupts machine checks etc 2 42 Computer Group Literature Center Web Site Functional Description Each timer is composed of a prescaler and a counter The prescaler determines the resolution of the timer and is programmable to any binary value between 1 us and 32 768 us The counter counts in the units provided by the prescaler For example the watchdog timer would reach a count of zero within 24 us if the prescaler was p
193. g and writing check bits is DO D7 Each 8 bit check bit location services 64 bits of normal data The figure below shows the relationship between normal data and check bit data Normal View of Data rwcb 0 64 bits 0 1 2 3 4 5 6 7 Check bit View rwcb 1 Figure 3 10 Read Write Check bit Data Paths Note that if test software wishes to force a single bit error to a location using the rwcb function the scrubber may correct the location before the test software gets a chance to check for the single bit error This can be avoided by disabling scrub writes Also note that writing bad check bits can set the elog bit in the Error Logger Register The writing of check bits causes the SMC to perform a read modify write to SDRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered by the write check bits operation To avoid this it is recommended that the derc bit also be set while the rwcb bit is set possible sequence for performing read write check bits is as follows 1 Disable scrub writes by clearing the swen bit if it is set 3 46 Computer Group Literature Center Web Site Programming Model 2 Make sure software is not using DRAM at this point because while rwcb is set DRAM will not function as normal memory Set the derc and rwcb bits in the Data Control register Perform the desired re
194. ging the vector priority or destination of I O interrupt sources This is provided to support systems which allow dynamic configuration of I O devices In order to change the vector priority or destination of an active interrupt source the following sequence should be performed Mask the source using the MASK bit in the vector priority register Wait for the activity bit ACT for that source to be cleared Make the desired changes Unmask the source This sequence ensures that the vector priority destination and mask information remain valid until all processing of pending interrupts is complete Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event If multiple nested interrupts are in service the EOI command terminates the interrupt service of the http www motorola com computer literature 2 63 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller highest priority source Once an interrupt is acknowledged only sources of higher priority will be allowed to interrupt the processor until the EOI command is received This register should always be written with a value of zero which is the nonspecific EOI command Interrupt Acknowledge Register 8259 Mode Upon receipt of an interrupt signal the processor may read this register to retrieve the vector of the interrupt source which caused the interrupt The 8259 mode bits con
195. gister Address FEF80040 Bit t A A cal wo A of Alo a SY aE OY COL NY Dani Dani Aami pm NI NI NI NI NIN NINN ayo Name FREQUENCY Operation READ ZERO READ ZERO READ WRITE cd cz cd na cz e 2 Reset ala gt lt gt lt gt lt gt lt Xx X 00 P scb0 scb1 These bits increment every time the scrubber completes scrub of the entire SDRAM When they reach binary 11 they roll over to binary 00 and continue These bits are cleared by power up reset swen When set swen allows the scrubber to perform write cycles When cleared swen prevents scrubber writes SCRUB FREQUENCY Determines the rate of scrubbing by setting the roll over count for the scrub prescale counter Each time the SMC performs a refresh burst the scrub prescale counter increments by one When the scrub prescale counter reaches the value stored in this register it clears and resumes counting starting at 0 Note that when this register is all O s the scrub prescale counter does not increment disabling any scrubs from occurring Since SCRUB FREQUENCY is cleared to 0 at power up reset scrubbing is disabled until software programs a non zero value into it http www motorola com computer literature 3 51 System Memory Controller SMC Scrub Address
196. group 4 group 1 PARB4 amp 3 2 amp 1 PARBO amp HAWK PARB6 amp 5 Notes 000 is the default setting in mixed mode The HEIR setting only covers a small subset of all possible combinations and the requestors within each group is fixed and cannot be interchanged with other groups It is the 2 36 Computer Group Literature Center Web Site Functional Description responsibility of the system designer to connect the request grant pair in a manner most beneficial to their design goals other combinations in the HEIR setting not specified in the table are invalid and should not be used Arbitration parking is programmable by writing to the PRK field of the PCI arbiter control register Parking can be programmed for any of the requestors last requestor or none The following table describes all available settings for the PRK field Table 2 12 Arbitration Setting PRK setting Function 0000 Park on last requestor 0001 Park on PARB6 0010 Park on PARB5 0011 Park on PARB4 0100 Park on PARB3 0101 Park on PARB2 0110 Park on PARBI 0111 Park on PARBO 1000 Park on HAWK 1111 Parking disabled Notes 1 1000 is the default setting 2 Parking disabled is a test mode only and should not be used since no one will drive the PCI bus when in idle state 3 All other combinations in the PRK setting not specified in the table are invalid and should not be used http
197. guration Configuration Register Value Register Value Address Offset Register Name Aliasing OFF Aliasing ON 8C PSOFFI amp PSATTI 0000 0000 0000 00FX 90 PSADD2 0000 0000 0000 0000 94 PSOFF2 amp PSATT2 0000 0000 0000 0000 98 PSADD3 0000 0000 0000 0000 9C PSOFF3 amp PSATT3 0000 0000 0000 0000 The next table shows the programmed values for the associated Universe II PCI registers for the PCI CHRP memory map Table 1 9 Universe Il PCI Register Values for CHRP Memory Map Configuration Configuration Register Value Address Offset Register Name 100 LSIO C082 5100 104 LSIO BS 4000 0000 108 LSIO BD 000 0000 10C LSIO TO XXXX 0000 114 LSII CTL C042 5100 118 LSII BS F000 0000 11C LSI1_BD F800 0000 120 151 TO XXXX 0000 128 LSI2 0000 0000 12C LSD BS XXXX XXXX 130 LSD BD XXXX XXXX 134 LSD TO XXXX XXXX 1 14 Computer Group Literature Center Web Site Programming Model Table 1 9 Universe PCI Register Values for CHRP Memory Continued Configuration Configuration Register Value Address Offset Register Name 13C LSI3 CTL 0000 0000 140 LSI3 BS XXXX XXXX 144 LSI3 BD XXXX XXXX 148 LSI3 TO XXXX XXXX 188 SLSI 053 8 PCI PREP Memory The following table shows a PCI memory map of the MVME2400 series that is PREP compatible from the point of view of the PCI local bus
198. guration options 47 Reserved for future configuration options 48 127 Reserved for future configuration options VPD Data Definitions FLASH Memory Configuration Data The FLASH memory configuration data packet consists of byte fields which indicate the size organization type of the FLASH memory array The following table s further describe the FLASH memory configuration VPD data packet Table A 3 FLASH Memory Configuration Data Byte Field Field Field Description Offset Size Mnemonic Bytes 00 2 FMC MID Manufacturer s Identifier FFFF Undefined Not Applicable 02 2 FMC DID Manufacturer s Device Identifier FFFF Undefined Not Applicable 04 1 FMC DDW Device Data Width for example 8 bits 16 bits 05 1 FMC NOD Number of Devices Sockets Present http www motorola com computer literature 5 MVME2400 VPD Reference Information Table A 3 FLASH Memory Configuration Data Byte Field Field Field Description Offset Size Mnemonic Bytes 06 1 Number of Columns Interleaves 07 1 CW Column Width in Bits This will always be a multiple of the device s data width 08 1 FMC_WEDW Write Erase Data Width The FLASH memory devices must be programmed in parallel when the write erase data width exceeds the device s data width 09 1 BANK Bank Number of FLASH Memory Array O2 A 1 B VPD Data Definitions L2 C
199. he PPC Slave attempt to move data in either single beat or four beat burst transactions The PCI Master supports 32 bit and 64 bit transactions in the following manner PPC60x single beat transactions regardless of the byte count are subdivided into one or two 32 bit transfers depending on the alignment and the size of the transaction This includes single beat 8 byte transactions All PPC60x burst transactions are transferred in 64 bit mode if the PCI bus has 64 bit mode enabled If at any time during the transaction the PCI target indicates it can not support 64 bit mode the PCI Master continues to transfer the remaining data within that transaction in 32 bit mode 2 26 Computer Group Literature Center Web Site Functional Description The PCI Master can support Critical Word First CWF burst transfers The PCI Master divides this transaction into two parts The first part starts on the address presented with the CWF transfer request and continues up to the end of the current cache line The second transfer starts at the beginning of the associated cache line and works its way up to but not including the word addressed by the CWF request It should be noted that even though the PCI Master can support burst transactions a majority of the transaction types handled are single beat transfers Typically PCI space is not configured as cache able therefore burst transactions to PCI space would not naturally occur I
200. he PPC bus using any single beat valid transfer size The PCI Configuration Registers reside in PCI configuration space These are primarily accessible from the PPC bus by using the CONFIG ADDRESS DATA registers The PPC Registers are described first the PCI Registers are described next A complete discussion of the MPIC Registers can be found later in this chapter It is possible to place the base address of the PPC registers at either SFEFF0000 or SFEFE0000 Having two choices for where the base registers reside allows the system designer to use two of the Hawk s PCI Host Bridges connected to one PPC60x bus Please refer to the section http www motorola com computer literature 2 65 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller entitled PHB Hardware Configuration for more information references to the PPC registers of PHB within this document are made with respect to the base address SFEFF0000 The following conventions are used in the Hawk register charts R Read Only field R W Read Write field 5 Writing a ONE to this field sets this field Writing a ONE to this field clears this field PPC Registers The PPC register map of the PHB is shown in Table 2 6 Table 2 16 PPC Register Map for PHB 1111111111 0 1 2 3 4 5 6 7 8901234560789 FEFF0000 VENID DEVID Bit gt 2 2 2 1123 gt N Un N AN JN 9 N N eu mU 1 1 e t
201. he SDRAM being used e Make sure the following bits are initialized as follows refdis 0 rwcb 0 derc 1 scien 0 dpien 0 sien 0 mien 0 mbe_me 0 SCRUB_FREQUENCY 00 Refer to the ECC Control Register section and the Scrub Refresh Register section for more information f Make sure that ROM Flash banks A and B are not enabled to respond in the range 00000000 20000000 Refer to the section on ROM A Base Size Register and ROM B Base Size Register for more information g Make sure that no other devices are set up to respond in the range 00000000 20000000 2 For each of the Blocks A through H http www motorola com computer literature 3 83 System Memory Controller SMC a Set the block s base address to 00000000 Refer to the sections titled SDRAM Base Address Register Blocks A B C D and SDRAM Enable and Size Register Blocks E F G H b Enable the block and make sure that the other seven blocks are disabled Refer to the same sections as referenced in the previous step c Set the block s size control bits Start with the largest possible 512Mbytes Refer to the same sections as referenced in the previous step d Wait for at least one SDRAM refresh to complete e Write a unique 64 bit data pattern to each one of a specified list of addresses The list of addresses to be written varies depending on the size that is currently being checked The address lists are shown in t
202. he table below f Read back all of the addresses that have been written If all of the addresses still contain exactly what was written then the block s size has been found It is the size for which it is currently programmed If any of the addresses do not contain exactly what was written then the block s memory size is less than that for which it is programmed Sizing needs to continue for this block by programming its control bits to the next smaller size waiting for at least one refresh to complete and repeating steps e and f g If no match is found for any size then the block is unpopulated and has a size of OMB Its size should be programmed to 0 3 84 Computer Group Literature Center Web Site Software Considerations Table 3 20 Address Lists for Different Block Size Checks 512MB 256MB 256MB 128MB 128MB 128MB 64Mx4 32Mx8 32Mx4 16 16 46Mx8 16 4 00000000 500000000 00000000 00000000 00000000 00000000 00008000 00004000 00008000 04000000 00004000 00004000 10000000 08000000 64MB 64MB 32MB 8Mx16 8Mx8 4 16 900000000 500000000 00000000 900002000 500002000 00001000 Notes 1 16 8 and 16Mx4 the same If the real size is either one of these this algorithm will program for 16Mx8 regardless of whether the SDRAM size is 16Mx8 or 16Mx4 This is not a problem because the Hawk behaves identically when progra
203. he type of LCD panel connected in an MPC821 based application FF N A Termination Packet follows the last initialized data N A packet A 2 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Notes 1 The data size is variable Its actual size is dependent upon the product configuration type Integer values are formatted stored in big endian byte ordering This packet may be omitted if the ethernet interface is non existent or the ethernet interface has an associative SROM for example DEC21x4x This packet may contain an additional byte following the address data This additional byte indicates the ethernet interface number This additional byte would be specified in applications where the host product supports multiple ethernet interfaces For each ethernet interface present the instance number would be incremented by one starting with zero VPD Data Definitions Product Configuration Options Data The product configuration options data packet consists of a binary bit field The first bit of the first byte is bit O that is PowerPC bit numbering An option is present when the assigned bit is a one the following table further describes the product configuration options VPD data packet Table A 2 MVME2400 Product Configuration Options Data Bit Number Bit Mnemonic Bit Description 0 PCO PCIO CONNI PCI PMC bus 0 connector 1 present 1 PCO
204. ields the Register Number the Function Number the Device Number and the Bus Number The Register Number and the Function Number get passed along to the PCI bus as portion of the lower address bits 2 32 Computer Group Literature Center Web Site Functional Description When performing a configuration cycle the PHB uses the upper 20 address bits as IDSEL lines During the address phase of a configuration cycle only one of the upper address bits will be set The device that has its IDSEL connected to the address bit being asserted is selected for a configuration cycle The PHB decodes the Device Number to determine which of the upper address lines to assert The decoding of the five bit Device Number is show as follows Device Number Address Bit 00000 AD31 00001 01010 All Zeros 01011 ADII 01100 AD12 etc etc 11101 AD29 11110 AD30 11111 All Zeros The Bus Number determines which bus is the target for the configuration read cycle The PHB will always host PCI bus 0 Accesses that are to be performed on the PCI bus connected to the PHB must have zero programmed into the Bus Number If the configuration access is targeted for another PCI bus then that bus number should be programmed into the Bus Number field The PHB will detect a non zero field and convert the transaction to a Type 1 Configuration cycle Generating PCI Special Cycles The PHB supports the method stated in PCI L
205. ill assert an interrupt through the MPIC XDPE PPC Data Parity Error This bit is set when the PHB detects a data bus parity error It may be cleared by writing a 1 to it writing a 0 to it has no effect When the XDPEM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the XID field in the EATTR register When the XDPEI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PPER PCI Parity Error This bit is set when the PCI PERR pin is asserted It may be cleared by writing it to a 1 writing it to a 0 has no effect When the PPERM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the EATTR register When the PPERI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC 2 80 Computer Group Literature Center Web Site Registers PSER PCI System Error This bit is set when the PCI SERR_ pin is asserted It may be cleared by writing it to a 1 writing it to a 0 has no effect When the PSERM bit in the EENAB register is set the assertion of this bit will assert MCHK to the master designated by the DFLT bit in the EATTR register When the PSERI bit in the EENAB register is set the assertion of this bit will assert an interrupt through the MPIC PSMA PCI Master Signalled Master Abort This bit is set when the PC
206. ill be made available by a signal which is external to the Hawk ASIC Presumably this signal would be connected to an externally sourced interrupt input of a MPIC controller in a different device Since the MPIC specification defines external I O interrupts to operate in the distributed mode the delivery mode of this error interrupt should be consistent 2 54 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Functional Description Timers There is a divide by eight pre scaler which is synchronized to the PHB clock PPC60x processor clock The output of the prescaler enables the decrement of the four timers The timers may be used for system timing or to generate periodic interrupts Each timer has four registers which are used for configuration and control They are Current Count Register Base Count Register Vector Priority Register a Destination Register Interrupt Delivery Modes The direct and distributed interrupt delivery modes are supported Note that the direct delivery mode has sub modes of multicast or non multicast The IPI s and Timer interrupts operate in the direct delivery mode The externally sourced or I O interrupts operate in the distributed mode In the direct delivery mode the interrupt is directed to one or both processors If it is directed to two processors that is multicast it will be delivered to two processors The interrupt is delivered to the pro
207. imal etc MVME2400 VPD Reference Information Table A 1 VPD Packet Types Continued ID Size Description Data Type Notes 06 04 MPU External Clock Frequency in Hertz for example Integer 4 byte 2 100 000 000 decimal etc This is also called the local processor bus frequency 07 04 Reference Clock Frequency in Hertz for example Integer 4 byte 2 32 768 decimal etc This value is the frequency of the crystal driving the OSCM 08 06 Ethernet Address for example 08003E26A475 etc Binary 3 4 09 Variable MPU Type for example 601 602 603 604 750 801 ASCII 1 821 823 860 860DC 860DE 860DH 860EN 860MH etc OA 4 EEPROM CRC Integer 4 byte 2 This packet is optional This packet would be utilized in environments where CRC protection is required When computing the CRC this field that is 4 bytes is set to Zero This CRC only covers the range as specified the size field OB 9 FLASH Memory Configuration Binary A table found later in this document further describes this packet 0 TBD VLSI Device Revisions Versions Binary OD 04 Host PCI Bus Clock Frequency in Hertz forexample Integer 4 byte 2 33 333 333 decimal etc OE Variable L2 Cache Configuration Binary A table found later in this document further describes this packet OF Reserved BF C0 User Defined FE An example of a user defined packet could be t
208. in hardware Table 1 19 Z8536 CIO Port Pins Assignment Port Signal Name Direction Descriptions Pin PAO IO Not used IO Not used PA2 IO Not used PA3 IO Not used 4 IO Not used PA5 IO Not used PA6 BRDFAIL Output Board Fail When set will cause BFL LED to be lit IO Not used PBO IO Not used 1 IO Not used PB2 IO Not used PB3 IO Not used http www motorola com computer literature 1 33 Board Description and Memory Maps Table 1 19 Z8536 CIO Port Pins Assignment Continued Port Signal Name Direction Descriptions Pin PB4 Not used PB5 IO Not used PB6 Not used PB7 _ Input Status of ABORT signal PCO IO Not used PCI Not used PC2 BASETYPO Input Genesis Base Module Type PC3 Input 00b Genesis II see Base Module Status Register 01b MVME1600 011 10b Reserved 11b MVME1600 001 ISA DMA Channels The MVME2400 series does not implement any ISA DMA channels 1 34 Computer Group Literature Center Web Site Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Introduction Overview Features This chapter describes the architecture and usage of the PowerPC to PCI Local Bus Bridge PHB and the Multi Processor Interrupt Controller MPIC portion of the Hawk ASIC The Hawk is intended to provide PowerPC 60x PPC60x compliant
209. ing on the last CPU or parking disabled There are various system level debug functions provided by the PPC Arbiter The Arbiter has the optional ability to flatten the PPC60x bus pipeline Flattening can be imposed uniquely on single beat reads single beat writes burst reads and burst writes It is possible to further qualify the ability to flatten based on whether there is a switch in masters or whether to flatten unconditionally for each transfer type This is a debug function only and is not intended for normal operation 2 16 Computer Group Literature Center Web Site Functional Description PPC Parity PHB will generate data parity whenever it is sourcing PPC data This happens during PPC Master write cycles and PPC Slave read cycles Valid data parity will be presented when DBB_ is asserted for PPC Master write cycles Valid data parity will be presented when TA is asserted for PPC Slave read cycles PHB will check data parity whenever it is sinking PPC data This happens during PPC Master read cycles and PPC Slave write cycles Data parity will be considered valid anytime has been asserted If a data parity error is detected then the PHB will latch address and attribute information within the ESTAT EADDR and EATTR registers and an interrupt or machine check will be generated depending on the programming of the ESTAT register PHB has a mechanism to purposely induce data parity errors for testability The
210. initiated the transaction When this bit is clear MCHK will not be asserted 2 78 Computer Group Literature Center Web Site Registers XBTOI PPC Address Bus Time out Interrupt Enable When this bit is set the XBTO bit in the MERST register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted XDPEI PPC Data Parity Error Interrupt Enable When this bit is set the XDPE bit in the ESTAT register will be used to assert an interrupt through the MPIC When this bit is clear no interrupt will be asserted PPERI PCI Parity Error Interrupt Enable When this bit is set the PPER bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PSERI PCI System Error Interrupt Enable When this bit is set the PSER bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PSMAI PCI Master Signalled Master Abort Interrupt Enable When this bitis set the PSMA bit in the ESTAT register will be used to assert an interrupt through the MPIC interrupt controller When this bit is clear no interrupt will be asserted PRTAI PCI Master Received Target Abort Interrupt Enable When this bitis set the PRTA bit in the ESTAT register will be used to assert an interrupt through the
211. interfaces to 32 bits rom a 64 matches the value that was on the RD2 pin at power up reset It cannot be changed by software rom a siz The rom a siz control bits are the size of ROM Flash for Block A They are encoded as shown in the following table Table 3 11 ROM Block A Size Encoding rom a siz BLOCK SIZE 206000 1 001 2 010 4MB 20011 8MB 26100 16MB 101 32 110 64 111 Reserved rom a rv and rom b rv determine which if either of Blocks A and B is the source of reset vectors or any other access in the range 00000 FFFFFFFF as shown in the table below Table 3 12 rom a rv and rom b rv encoding rom a rv rom b rv Result 0 0 Neither Block is the source of reset vectors 0 1 Block B is the source of reset vectors 1 0 Block A is the source of reset vectors 1 1 Block B is the source of reset vectors rom a rv is initialized at power up reset to match the value on the RDO pin 3 54 Computer Group Literature Center Web Site Programming Model rom a en When rom a en is set accesses to Block A ROM Flash in the address range selected by ROM A BASE are enabled When rom a en is cleared they are disabled rom a we When rom a we is set writes to Block A ROM Flash are enabled When rom a we is cleared they are disabled Note that if rom a 64 is cleared only 1 byte writes are allowed If rom a 64 is set only 4 byte wri
212. ional Description PPC FIFO Table 2 1 PPC Slave Response Command Types Continued PPC Transfer Type Transfer Transaction Encoding ECOWX 10100 No Response TLB Invalidate 11000 Addr Only ECIWX 11100 No Response LWARX 00001 Addr Only STWCX 00101 Addr Only TLBSYNC 01001 Addr Only ICBI 01101 Addr Only Reserved 1 01 No Response Write with flush 00010 Write Write with kill 00110 Write Read 01010 Read Read with intent to modify 01110 Read Write with flush atomic 10010 Write Reserved 10110 No Response Read atomic 11010 Read Read with intent to modify atomic 11110 Read Reserved 00011 No Response Reserved 00111 No Response Read with no intent to cache 01011 Read Reserved 01111 No Response Reserved 1 11 No Response A 64 bit by 8 entry FIFO 2 cache lines total is used to hold data between the PPC Slave and the PCI Master to ensure that optimum data throughput is maintained The same FIFO is used for both read and write transactions A 46 bit by 4 entry FIFO is used to hold command information being passed between the PPC Slave and the PCI Master If write posting has been enabled then maximum number of transactions that may be posted is http www motorola com computer literature Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PPC Master limited by the abilities of either the data FIFO or the command FIFO For example two b
213. ions multicast delivery P1 Processor 1 The interrupt is directed to processor 1 PO Processor 0 The interrupt is directed to processor 0 External Source Vector Priority Registers Offset Int Src 0 10000 Int Src 2 gt Int Src15 10020 gt 101E0 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 10198176 5 4 3 2 0 9 8 7 6 5 4 3 2 101098 7 6 54 321 0 Name EXTERNAL SOURCE VECTOR PRIORITY gt PRIOR VECTOR Q 2 4 2 tri Operation wI R R W R R W zz Reset 000 0 00 00 2 116 Computer Group Literature Center Web Site Registers MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set POL Polarity This bit sets the polarity for external interrupts Setting this bit to a zero enables active low or negative edge Setting this bit to a one enables active high or positive edge Only External Interrupt Source uses this bit in this register SENSE Sense This b
214. is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined during a request for the interrupt associated with this vector http www motorola com computer literature 2 111 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Spurious Vector Register Offset 010E0 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 OF of 81 71 6 5 4 3 21 10 Name VECTOR Operation R R R R W Reset 00 00 00 FF VECTOR This vector is returned when the Interrupt Acknowledge register is read during a spurious vector fetch Timer Frequency Register Offset 010F0 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 I 1 1 1 1 1 1 1 I 1019 8 7 6 5 4 3 2 OF 9 8765432 1 0 98 7 6 54 32 10 Name TIMER FREQUENCY Operation R W Reset 00000000 This register is used to report the frequency in Hz of the clock source for the global timers Following reset this register contains zero The system initialization code must initialize this register to one eighth the MPIC clock frequency For the PHB implementation of th
215. it sets the sense for external interrupts Setting this bit to a zero enables edge sensitive interrupts Setting this bit to a one enables level sensitive interrupts For external interrupt sources 1 through 15 setting this bit to a zero enables positive edge triggered interrupts Setting this bit to a one enables active low level triggered interrupts PRIOR Priority Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR Vector This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector http www motorola com computer literature 2 117 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller External Source Destination Registers Offset Int Src 0 10010 Int Src 2 gt Int Sre 15 10030 gt 101F0 Bit 3 3 2 2 2 2 2 2 2 2 2 22 1 1 1 1 1 1 1 1 1 1 1 O 9 8 7 6 5 4 3 2 1 OF 9 8 7 6 5 4 3 2 1029875654232 10 Name EXTERNAL SOURCE DESTINATION S Operation R R R Z Reset 00 00 00 00 ojo This register indicates the possible destinations for the external interrupt sources These interrupts operate in the Distributed interrupt delivery mode P1 Processor 1 The interrupt is pointed to processor 1 PO Proce
216. iterature 3 13 System Memory Controller SMC During any address transfer cycle on the PPC60x the SMC checks each of the 4 8 bit PPC60x address lanes and its corresponding AP signal for odd parity If any of the 4 lanes has even parity the SMC logs the error in the CSR and can generate a machine check if so enabled Note SMC does not generate address parity because it is not a PPC60x address master Refer to the Address Parity Error Log Register section further on in this document for additional control register details Cache Coherency The SMC supports cache coherency to SDRAM only It does this by monitoring the ARTRY control signal on the PPC60x bus and behaving appropriately when it is asserted When ARTRY is asserted if the access is a SDRAM read the SMC does not source the data for that access If the access is a SDRAM write the SMC does not write the data for that access Depending upon when the retry occurs the SMC may cycle the SDRAM even though the data transfer does not happen Cache Coherency Restrictions The PPC60x GBL_ signal must not be asserted in the CSR areas L2 Cache Support The SMC provides support for a look aside L2 cache only at 66 67MHz by implementing a hold off input L2CLM On cycles that select the SMC the SMC samples L2CLM on the second rising edge of the CLK input after the assertion of TS If L2CLM is high the SMC responds normally to the cycle If it is low the SMC ignores the
217. its must be tested for proper response After the initial word address is successfully transmitted the first data word loaded into the 72C Transmitter Data Register will be transferred to the initial address location of the slave device After i2 cmplt and i2 ackin bits have been tested for proper response the next data word loaded into the 12 Transmitter Data Register will be transferred to the next address location of the slave device and so on until the block transfer is complete A stop sequence then must be transmitted to the slave device by first setting the i2 stop and 12 enbl bits in the PC Control Register and then writing a dummy data data don t care to the PC Transmitter Data Register The 2C Status Register must now be polled to test i2_cmplt bit for the operation complete status The stop sequence will initiate a programming cycle for the serial EEPROM and also relinquish the ASIC master s possession of the PC bus http www motorola com computer literature 3 29 System Memory Controller SMC DEVICE ADDR WORD ADDR 1 DATA 1 DATA M SDA START S C eeo C STOP B K K K K from Slave Device BEGIN READ 2 STATUS REG LOAD 09 START CONDITION TO I2C CONTROL REG LOAD DEVICE ADDR WR BIT I2C TR
218. l Register Set or any other slave on the PowerPC bus CLK Frequency Register Address FEF80020 Bit e mme SSNS 16 e o SCA OS 3 59 B S e Name CLK eojjeji iir FREQUENCY E Operation READ WRITE READ ZERO READ ZERO w vmm Reset 64 P X X lt aid CLK FREQUENCY These bits should be programmed with the hexadecimal value of the operating CLOCK frequency in MHz that is 42 for 66 MHz When these bits are programmed this way the chip s prescale counter produces a 1 MHz approximate output The output of the chip prescale counter is used by the refresher scrubber and the 32 bit counter After power up this register is initialized to 64 for 100 MHz The formula is Counter Output Frequency Clock Frequency CLK FREQUENCY 3 44 Computer Group Literature Center Web Site Programming Model For example if the Clock Frequency is 100 MHz and CLK FREQUENCY is 64 then the counter output frequency is 100 MHZ 100 1 MHz When the CLK pin is operating slower than 100 MHz software should program CLK FREQUENCY to be at least as slow as the CLK pin s frequency as soon as possible after power up reset so that SDRAM refresh does not get behind It is okay for the software then to take some time to up CLK FREQUENCY to the correct value Refresh will get behind only when the actual CLK
219. l Data Paths 3 4 Computer Group Literature Center Web Site Block Diagrams DO D1 CS CO C1 CS BO B1 CS 1 CS BA RA RAS CAS WE DOM VW Ww RDO 6 0 gt SDRAM SDRAM SDRAM SDRAM BLOCK A BLOCK B BLOCK C BLOCK D Figure 3 3 Overall SDRAM Connections 4 Blocks using Register Buffers http www motorola com computer literature 3 5 System Memory Controller SMC PPC60x Ctrl PPC60x SDRAM lt gt amp ROM Flash CONTROL MEM Ctrl INTERFACE REFRESHER SDRAM pean SCRUBBER ADDRESS MULTIPLEXOR PPC60x Attr PPC60x 99 ADDRESS DECODER PPC60x Addr 2 Bus 2 INTERFACE 3 MEM Data MULTIPLEXOR Figure 3 4 Hawk s System Memory Controller Block Diagram STATUS CONTROL REGISTERS Functional Description The following sections describe the logical function of the SMC The SMC has interfaces between the PowerPC bus and SDRAM ROM Flash and its Control and Status Register sets CSR Performance Four beat Reads Writes The SMC performs best when doing bursting 4 beat accesses This is made possible by the burst nature of synchronous DRAMs When the PPC60x master begins a burst read to SDRAM the SMC starts the access 3 6 Computer Group Literature Center Web Site Functio
220. le Vendor Device Register Address FEF80000 a io fool 9 SSE VENDID DEVID Operation READ ONLY READ ONLY Reset 1057 4803 VENDID This read only register contains the value 1057 It is the vendor number assigned to Motorola Inc DEVID This read only register contains the value 4803 It is the device number for the Hawk http www motorola com computer literature 3 39 System Memory Controller SMC Revision ID General Control Register Address FEF80008 Bit 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 29 ay N 7 8 9 REVID aonly 22 pu statO 28 pu stat pu stat2 30 pu stat3 31 Operation READ ONLY 0 0 0 0 0 0 0 R W tben en 0 0 0 0 0 0 R R R R R R R R R R R R R 24 R R Reset 01 a daja gt d gt d gt d x oo gt gt gt xx pI lt I gt gt gt gt 0 PL R W isa_hole 23 X tben en tben en controls the enable for the pl tben pO tben output signals When tben en is set the PClm _ input pin becomes the pl tben output pin and the ercs output
221. le 1 10 Prescaler Adjust Register 2 74 priority schemes described PCI arbiter 2 35 PRK as used in arbitration parking 2 37 processor CHRP memory map 1 7 Processor Init Register 2 110 processor memory map 1 6 processor memory maps 1 6 processor PREP memory map 1 10 processor memory domain MPC604 5 13 product overview features Universe 4 1 http www motorola com computer literature IN 7 lt moz xXmoz Index Programmable Lock Resolution 2 46 programming details 5 1 programming model 1 6 programming ROM Flash devices 3 74 R RAM A BASE 3 43 3 66 RAM B BASE 3 43 3 66 RAM C BASE 3 43 3 66 RAM D BASE 3 43 3 64 3 65 3 66 Raven MPC register map 2 66 Raven PCI Host Bridge amp Multi Processor Interrupt Controller chip 2 1 Raven PCI I O register map 2 92 RavenMPIC interrupt assignments 5 3 RavenMPIC register map 2 105 read ahead mode in PPC Master 2 12 Read Write to ROM Flash 3 55 readable switch settings 1 26 refresh scrub 3 34 SMC 3 34 Refresh Scrub Address Register SMC 3 52 register bit descriptions SMC 3 38 register map 2 66 PCI 2 91 register summary 3 35 Registers programmable in ASICs 1 1 registers CLK Frequency 3 44 CONFIG ADDRESS 2 100 DATA 2 103 End of Interrupt 2 122 External Source Destination 2 118 External Source Vector Priority 2 116 Feature Reporting 2 108 General Purpose 2 90 Global Configuration 2 108 Hardware Control Status Register 2 74 Header Type 2
222. logged a scrub error esblk0 esblk1 esbik2 are 0 0 0 for Block A 0 0 1 for Block B 0 1 0 for Block C and 0 1 1 for Block D etc scof scof is set by the SBE COUNT register rolling over from FF to 00 It is cleared by software writing a 1 to it SBE COUNT SBE COUNT keeps track of the number of single bit errors that have occurred since it was last cleared It counts up by one each time it detects a single bit error independent of the state of the elog bit The SBE COUNT is cleared by power up reset and by software writing all zeros to itself When SBE COUNT rolls over from FF to 00 the SMC sets the scof bit The rolling over of SBE COUNT pulses the internal interrupt signal SMC INT low if the scien bit is set Error Address Register Address FEF80038 Bit o A AF A A AQ SY OF SEO OO ban bani bani bani bani Dani NINN NINN ANN Name ERROR_ADDRESS READ ONLY c c c Reset x ox ERROR ADDRESS These bits reflect the value that corresponds to bits 0 28 of the PPC60x address bus when the SMC last logged an error during a PowerPC access to SDRAM They reflect the value of the SCRUB ADDRESS counter if the error was logged during a scrub cycle 3 50 Computer Group Literature Center Web Site Programming Model Scrub Refresh Re
223. ls the Hawk how big the block is for map decoding and how to translate that block s 60x addresses to SDRAM addresses Programming a block s size to non zero also allows it to participate in scrubbing if scrubbing is enabled After software programs the size bits it should wait for a refresh to happen before beginning to access SDRAM 2 EEPROMs Most of the information needed to program the SDRAM speed attributes and size is provided by EEPROM devices that are connected to Hawk s bus The EEPROM devices contain data in a specific format called Serial Presence Detect SPD Board designers can implement one EEPROM for each of Hawk s SDRAM blocks or they can implement one EEPROM for several such blocks When using DIMMs the board designer can use the EEPROM that is provided on the DIMM EEPROMs that are used for SPD can be wired to appear at one of 8 different device locations Board designers should establish an EEPROM addressing scheme that will allow software to know which PC address to use to find information for each SDRAM block For example hardware could always place the EEPROM for SDRAM block A at the first address block B at the second etc Whatever addressing scheme is used should also deal with cases where multiple blocks are described by one PC EEPROM SDRAM Base Address and Enable Each block needs to be programmed for a unique base address that is an even multiple of its size Once a block s sp
224. lt I IS vZ X Haa Writes to this register must be enveloped by a period of time in which no accesses to ROM Flash Block A occur A simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before and after the write ROM A BASE These control bits define the base address for ROM Flash Block A ROM A BASE bits 0 11 correspond to PPC60x address bits 0 11 respectively For larger ROM Flash sizes the lower significant bits of ROM A BASE are ignored This means that the block s base address will always appear at an even multiple of its size ROM A BASE is initialized to FFO at power up or local bus reset Note Note that in addition to the programmed address the first 1 Mbyte of Block A also appears at FFF00000 FFFFFFFF if the rom rv bit is set and the rom b rv bit is cleared Also note that the combination of ROM BASE and rom a siz should never be programmed such that ROM Flash Block A responds at the same address as the CSR SDRAM External Register Set or any other slave on the PowerPC bus rom a 64 rom a 64 indicates the width of ROM Flash being used for Block A When rom a 64 is cleared Block is 16 bits wide where each half of SMC interfaces to 8 bits When rom a 64 is set http www motorola com computer literature 3 53 System Memory Controller SMC Block 15 64 bits wide where each half of the SMC
225. mation for the MVME240x VME Processor Modules Extensive programming information is provided for the primary Application Specific Integrated Circuit ASIC devices used on the boards the Hawk and Universe II chips Reference information is included in Appendix B Related Documentation for the Large Scale Integration LSI devices used on the boards and sources for additional information are listed This chapter briefly describes the board level hardware features of the MVME2400 series VME Processor Modules The chapter begins with a board level overview and features list Memory maps are next and are the major feature of this chapter Programmable registers in the MVME2400 series that reside in ASICs covered in the chapters on those ASICs Chapter 2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller and Chapter 3 System Memory Controller SMC cover the Hawk ASIC Chapter 4 Universe II VMEbus to PCI Chip covers the Universe II chip and Chapter 5 Programming Details covers certain programming features such as interrupts and exceptions Appendix B Related Documentation lists all related documentation Overview The MVME2400 series VME Processor Module family hereafter sometimes referred to simply as the MVME240x or the V2400 series provides many standard features required by a computer system Ethernet interface async serial port boot Flash and up to 256MB of ECC DRAM 1 1 Board Description and Memory
226. mited to 256MB and ROM FLASH to 9MB To enable the Processor hole area program the SMC to ignore 0x000A0000 0x000BFFFF address range and program the PHB to map this address range to PCI memory space Programmable via PHB CHRP requires the starting address for the PCI memory space to be 256MB aligned Programmable via PHB for either contiguous or spread I O mode The actual size of each ROM FLASH bank may vary The first one Mbyte of ROM FLASH Bank A appears at this range after a reset if the rom b rv control bit is cleared If the rom b rv control bit is set then this address range maps to ROM FLASH Bank B This range can be mapped to the VMEbus by programming the Universe II ASIC accordingly The map shown is the recommended setting which uses the Special PCI Slave Image and two of the four programmable PCI Slave Images 1 8 Computer Group Literature Center Web Site Programming Model 9 The only method to generate a PCI Interrupt Acknowledge cycle 8259 IACK is to perform a read access to the PHB s PIACK register at OXFEFF0030 The following table shows the programmed values for the associated PHB registers for the processor CHRP memory map Table 1 4 PHB Register Values for CHRP Memory Map Address Register Name Register Value FEFF 0040 MSADDO 4000 FCFF FEFF 0044 MSOFFO0 amp MSATTO 0000 00C2 FEFF 0048 MSADDI FD00 FDFF FEFF 004C MSOFFI
227. mmable mapping via the four PCI Slave Images in the Universe II ASIC 3 Programmable mapping via the Special Slave Image 51 81 in the Universe II ASIC VMEbus Slave Map The eight programmable VME Slave Images in the Universe II ASIC allow other VMEbus masters to get to any devices on the MVME2400 series The combination of the four Universe II VME Slave Images and the four PHB PCI Slave Decoders offers a lot of flexibility for mapping the system resources as seen from the VMEbus In most applications the VMEbus only needs to see the system memory and perhaps the software interrupt registers 5 and SIR2 registers An example of the VMEbus slave map is shown below 1 20 Computer Group Literature Center Web Site Programming Model Processor PCI Memory VMEbus NOTE 2 Onboard Memory 4 1 ISA Space PCI I O Space Software INT Registers 1896 9609 Figure 1 3 VMEbus Slave Mapping Notes 1 Programmable mapping via the four VME Slave Images in the Universe II ASIC 2 Programmable mapping via PCI Slave Images in the Hawk ASIC 3 Fixed mapping via the PIB device http www motorola com computer literature 1 21 Board Description and Memory Maps The following table shows the programmed values for the associated Universe II registers for the VMEbus slave function Table 1 13 Universe PCI Register Values fo
228. mmed for either size 2 8Mx16 and 8 8 are the same The same idea that applies to 16Mx8 and 16Mx4 applies to them 3 This needed only to check for non zero size 3 Wait enough time to allow at least 1 SDRAM refresh to occur before beginning any SDRAM accesses http www motorola com computer literature System Memory Controller SMC ECC Codes When the Hawk reports a single bit error software can use the syndrome that was logged by the Hawk to determine which bit was in error Table 3 2 shows the syndrome for each possible single bit error Table 3 22 shows the same information ordered by syndrome Table 3 21 Syndrome Codes Ordered by Bit in Error Bit Syndrome Bit Bit Syndrome Bit Syndrome Bit Syndrome 4A rd16 92 rd32 A4 rd48 29 0 01 4C rd17 13 rd33 C4 rd49 31 ckdl 02 rd2 2C rd18 0B 434 C2 rd50 BO ckd2 04 2A rd19 8A rd35 A2 rd51 8 ckd3 08 rd4 9 rd20 7A rd36 9E rd52 A7 ckd4 10 rd5 1C rd21 07 rd37 1 rd53 70 ckd5 20 rd6 1A rd22 86 rd38 1 rd54 68 ckd6 40 rd7 19 rd23 46 rd39 91 1455 64 ckd7 80 rd8 25 rd24 49 rd40 52 rd56 94 149 26 rd25 89 rd41 62 rd57 98 1410 16 rd26 85 rd42 61 rd58 58 11 15 rd27 545 rd43 51 rd59 54 rd12 F4 rd28 3D
229. mory map 1 12 default processor memory map 1 6 delayed transactions PCI Slave 2 24 derc 3 47 device selection 2 24 Disable Error Correction control bit 3 47 DMA controller 4 7 documentation related A 1 B 1 double word definition x DRAM enable bits 3 42 DRAM size control bits 3 42 E ECC SMC 3 15 ECC Codes Hawk 3 86 ECC codes 3 86 ECC Control Register SMC 3 45 EEPROM access 3 76 elog 3 49 embt 3 49 emulated Z8536 access registers 1 33 emulated Z8536 CIO registers and port pins 1 32 Endian Conversion 2 38 endian conversion 2 38 endian issues MVME2400 5 10 End of Interrupt Registers 2 122 Error Address Register SMC 3 50 error correction 3 15 Error Correction Codes 3 86 error detection 3 15 error handling 2 41 Error Logger Register 3 49 SMC 3 49 error logging 3 17 SMC 3 17 error notification and handling 5 9 Hawk 5 9 error reporting 3 16 ERROR ADDRESS 3 50 ERROR SYNDROME 3 50 esbt 3 49 escb 3 49 3 49 exceptions MVME2400 5 7 exclusive access 2 29 PCI Slave 2 25 External Register Set SMC 3 34 3 72 external register set reads and writes 3 35 External Source Destination Registers 2 118 External Source Vector Priority Registers 2 116 F Falcon ECC Memory Controller chip set 3 1 false definition x fast back to back transactions 2 29 PCI Slave 2 25 Feature Reporting Register 2 108 features 2 1 SMC 3 1 FIFO from PPC Slave to PCI Master 2 9 with PCI Slave 2 26 FIFO structure explained 2 4 Flash see
230. n Each map decoder also includes a programmable 16 bit address offset The offset is added to the 16 most significant bits of the PCI address and the result is used as the PPC address This offset allows devices to reside at any PPC address independent of the PCI address map An example of this is shown in the following figure PCI Bus Address 8 0 8 01 2 3 4 T A PSOFFx Register 9000 y Bus Address 1 0 8 0 1 2 9 4 1 Figure 2 5 PCI to Address Translation AII PHB address decoders are prioritized so that programming multiple decoders to respond to the same address is not a problem When the PCI address falls into the range of more than one decoder only the highest priority one will respond The decoders are prioritized as shown below Decoder Priority PCI Slave0 highest PCI Slave 1 PCI Slave 2 PCI Slave 3 lowest http www motorola com computer literature 2 21 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI Slave MPIC Control Registers The MPIC control registers are located within either PCI Memory or PCI I O space using traditional PCI defined base registers within the predefined 64 byte header Please see the section on Multi Processor Interrupt Controller MPIC Functional Description for more information The PCI Slave provides the control logic needed to interface the PCI bus to the PCI F
231. n R W R W Reset 0000 0000 START Start Address This field determines the start address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address END End Address This field determines the end address of a particular memory area on the PPC bus which will be used to access PCI bus resources The value of this field will be compared with the upper 16 bits of the incoming PPC address 2 84 Computer Group Literature Center Web Site Registers PPC Slave Offset Attribute 0 1 and 2 Registers Address XSOFFO XSATTO FEFF0044 XSOFFI XSATTI SFEFF004C XSOFF2 XSATT2 FEFF0054 Bit M fon Ese Gu a SS Kan E Name XSOFFx XSATTx A gt 2 2 gt Operation R W R zz im zm 72 22 72 ez 22 22 Reset 0000 00 The PPC Slave Offset Registers XSOFF0 XSOFF1 and XSOFF2 contains offset information associated with the mapping of PPC memory space to PCI memory io space The field within the XSOFFYXx registers is defined as follows XSOFFYx PPC Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PPC address to determine the PCI address used for transfers from the PPC bus
232. n ID General Control Register is set When tben_en is cleared the External Register Set interface is enabled and appears in its designated range When tben_en is set the External Register Set interface is disabled and the SMC does not respond to accesses in its designated range except that it responds to the address of this tben register p1_tben When the en bit is set the L2CLM_ input pin becomes the P1_TBEN output pin and it tracks the value on p1_tben When pl is 0 the TBEN pin is low and when p1_tben is 1 the P1 TBEN pin is high When the tben en bit is cleared 1 tben has no effect on any pin http www motorola com computer literature 3 73 System Memory Controller SMC 0 tben When the tben en bit is set the ERCS_ output pin becomes the TBEN output pin and it tracks the value on 0 tben When pO tben is 0 the PO TBEN pin is low and when p1 is 1 the PO TBEN pin is high When the tben en bit is cleared tben has no effect on any pin Note When tben enis high L2CLM_ cannot be driven by an external L2 cache controller and no External Register Set devices can be controlled Software Considerations This section contains information that will be useful in programming a system that uses the Hawk Programming ROM Flash Devices Those who program devices to be controlled by the Hawk should make note of the address mapping that is shown in Table 3 7 and in Table 3 8
233. n locked and non locked cycles ENA Enable This read only bit indicates the enabled state of the PCI Arbiter If set the PCI Arbiter is enabled and is acting as the system arbiter If cleared the PCI Arbiter is disabled and external logic is implementing the system arbiter Please refer to the section titled PHB Hardware Configuration for more information on how this bit gets set Hardware Control Status Prescaler Adjust Register The Hardware Control Status Register HCSR provides hardware specific control and status information for the PHB The bits within the HCSR are defined as follows 2 74 Computer Group Literature Center Web Site Registers Address FEFF0010 Bit o A A en wp Of EY cof DO SG QT ea xot ooo e a Alen of 4 A Q1 l 69 e HCSR XPAD alo alo BIE 5d gt lt 5 lt m ug Reset 00 9 XPRx PPC PCI Clock Ratio This is read only field that is used to indicate the clock ratio that has been established by the PHB at the release of reset The encoding of this field is shown in the following table XPR PPC60x PCI clock ratio 000 Undefined 001 1 1 010 2 1 011 3 1 100 3 2 101 Undefined 110 5 2 111 Undefi
234. n other words the current address tenure is pending closure all previous data tenures have completed and the current pending data tenure awaiting closer is logically associated with the current address tenure The time out function will be aborted if AACK is asserted anytime before the time out period has passed If the time out period reaches expiration then the PPC Timer will assert AACK_ to close the faulty address tenure If the transaction was an address only cycle then no further action will be taken If the faulty transaction was a data transfer cycle then the PPC Timer will assert the appropriate number of TA s to close the pending data tenure Error information related to the faulty transaction will be latched within the ESTAT EADDR and EATTR registers and an interrupt or machine check will be generated depending on the programming of the ESTAT register There are two exceptions that will dynamically disable the PPC Timer If the transaction is PCI bound then the burden of closing out a transaction is left to the PCI bus Note that a transaction to the 0 registers is considered to be PCI bound since the completion of these types of accesses depends on the ability of the PCI bus to empty PCI bound write posted data A second exception is the assertion of the XBTCLM signal This is an open collector wired OR bi directional signal that is used by a bridge to indicate the burden of timing a transaction has been passed on
235. n the Block 0000 OMBytes 0001 4Mx16 5 32 64Mbit 0010 8Mx8 9 64MBytes 64Mbit 0011 8 16 5 64MBytes 128Mbit 0100 16Mx4 18 128MBytes 64Mbit 0101 16Mx8 9 128MBytes 128Mbit 0110 16 16 5 128MBytes 256Mbit 260111 32Mx4 18 256MBytes 128Mbit 261000 32Mx8 9 256MBytes 256Mbit 1001 64Mx4 18 512MBytes 256Mbit 1010 Reserved 111 3 42 Computer Group Literature Center Web Site Programming Model Notes All SDRAM components should be organized with 4 internal banks When DIMMs are used the Component Configuration refers to the configuration of the devices used on the DIMMs Itis important that all of the ram a b c d e f g h siz0 3 bits be set to accurately match the actual size of their corresponding blocks This includes clearing them to binary 00000 if their corresponding blocks are not present Failure to do so will cause problems with addressing and with scrub logging SDRAM Base Address Register Blocks A B C D Address FEF80018 Bit RD NOSES 5315 SIS ISIS O3 IRIRIRIN ISIS ISIS Name RAM A BASE RAM B BASE RAM C BASE RAM D BASE Operation READ WRITE READ WRITE READ WRITE READ WRITE Reset 0 PL 0 PL Writes to this register must be enveloped by period of time in which no accesses to SDRAM occur The requirements of the envelope
236. nal Description and when the access time is reached the SDRAM provides all four beats of data one on each clock Hence the SMC can provide the four beats of data with zero idle clocks between each beat Single beat Reads Writes Because of start up addressing and completion overhead single beat accesses to and from the PPC60x bus do not achieve data rates as high as do four beat accesses Single beat writes are the slowest because they require that the SMC perform a read cycle then a write cycle to the SDRAM in order to complete Fortunately in most PPC 60x systems single beat accesses can be held to a minimum especially with data cache and copyback modes in place Address Pipelining The SMC takes advantage of the fact that PPC60x processors can do address pipelining Many times while a data cycle is finishing the PPC60x processor begins a new address cycle The SMC can begin the next SDRAM access earlier when this happens thus increasing throughput Page Holding Further savings comes when the new address is close enough to a previous one that it falls within an open page in the SDRAM array When this happens the SMC can transfer the data for the next cycle without having to wait to activate a new page in SDRAM In the SMC this feature is referred to as page holding SDRAM Speeds The SDRAM that the Hawk ASIC controls uses the 60x clock The SMC can be configured to operate at several different 60x clock frequencies usi
237. nation 2 24 tben Register SMC 3 73 Timer Basecount Registers 2 114 Timer Current Count Registers 2 113 Timer Destination Registers 2 116 Timer Frequency Register 2 112 Timer Vector Priority Registers 2 115 timing ROM Flash access 3 10 transaction burst 2 8 instance of interrupt 2 8 transaction ordering 2 47 transactions unable to retry 2 8 transfer types generated by PPC Master 2 14 PCI command code dependent 2 14 PPC60x bus 2 14 triple or greater bit error 3 16 true definition x U JART 1 25 CSR access mechanisms 4 8 Jniverse VMEbus to PCI chip 4 1 niverse as PCI master 4 6 niverse as PCI slave 4 5 niverse as VMEbus master 4 4 niverse as VMEbus slave 4 4 niverse chip problems after a PCI reset 5 8 niverse II function described 4 1 Jniverse II ASIC programming for VME Register info 1 27 Universe II PCI Register Values CHRP Memory Map 1 14 PREP Memory Map 1 17 Jniverse II register map 4 9 niverse s involvement with endian issues 5 14 URLs uniform resource locators B 8 V Vendor ID Device ID Registers 2 92 Vendor ID Device ID Registers 2 67 Vendor Identification Register 2 110 Vendor Device Register SMC 3 39 Vital Product Data VPD 1 23 A 1 4 compelled 2 7 VME Geographical Address Register PCI originated PPC bound described 2 4 VGAR 1 32 posted 2 7 VME Registers 1 27 PPC originated PCI bound described2 4 registers 1 27 PPC Slave limits 2 8 VM
238. nd after the write Data Parity Error Log Register Address FEF80068 Bit eo AI A 00 DLO SG A eg w e oO a A DN NI NI NI NI NINE ATA AN Name d oA o 5 gt 19 E 8 DP 5 E GWDP oO oO 0 o 0 o oo o lt gt Operation y READ ONLY 2 READ WRITE c e 4 c 04 Reset al a a GO PL dpelog dpelog is set when a parity error occurs on the PPC60x data bus during a PPC60x data cycle whose parity the SMC is qualified to check It is cleared by writing a one to it or by power up reset tt0 4 tt is the value that was on the TTO TT4 signals when the dpelog bit was set DPE DP DPE DP is the value that was on the DPO DP7 signals when the dpelog bit was set dpe ckall When dpe ckall is set the Hawk checks data parity on all cycles in which is asserted When ckall is cleared the Hawk checks data parity on cycles when 15 asserted only during writes to the Hawk Note Note that the Hawk does not check parity during cycles in which there is a qualified ARTRY_ at the same time as the TA_ http www mot
239. nd the 12 ackin bit provides status as to whether or nota slave device acknowledged the device address With the successful transmission of the device address the initial word address 15 loaded into the C Transmitter Data Register to be transmitted to the slave device Again i2 cmplt and i2 ackin bits must be tested for proper response At this point the slave device is still in a write mode Therefore another start sequence must be sent to the slave to change the mode to read by first setting the i2 start 12 ackout and 12 enbl bits in the PC Control Register and then writing the device address bits 7 1 and read bit bit 0 1 to the PC Transmitter Data Register After 12 cmplt and i2 ackin bits are tested for proper response the master controller writes a dummy value data don t care to the PC Transmitter Data Register This causes the I C master controller to initiate a read transmission from the slave device After the 2 master controller has received a byte of data indicated by 12 datin 1 in the PC Status Register and the 12 cmplt bit has also been tested for proper status the master controller responds with an acknowledge and the system software may then read the data by polling the Receiver Data Register As long as the slave device receives an acknowledge it will continue to increment the word address and serially clock out sequential data words The PC sequential read operation is terminated when the PC m
240. ned SPRQ Speculative PCI Request If set the PHB PCI Master will perform speculative PCI requesting when a PCI bound transaction has been retried due to bridge lock resolution If cleared the PCI Master will only request the PCI bus when a transaction is pending within the PHB FIFOs http www motorola com computer literature 2 75 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller WLRTXx Write Lock Resolution Threshold This field is used by the PHB to determine a PPC bound write FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction The encoding of this field is shown in the following table WLRT Write lock resolution threshold 00 Match write threshold mode that is PSATTx WXFT 01 Immediate 10 FIFO full 11 FIFO full RLRTx Read Lock Resolution Threshold This field is used by the PHB to determine a PPC bound read FIFO threshold at which a bridge lock resolution will create a retry on a pending PCI bound transaction The encoding of this field is shown in the following table RLRT Read lock resolution threshold 00 Match read threshold mode that is PSATTx RXFT or RMFT 01 Immediate 10 FIFO less than 1 cache line 11 FIFO less than 1 cache line The PPC Prescaler Adjust Register XPAD is used to specify a scale factor for the prescaler to ensure that the time base for the bus timer is
241. never the PHB detects a parity error even if parity error checking is disabled see bit PERR in the PCI Command Status Registers It is cleared by writing it to 1 writing a 0 has no effect 2 94 Computer Group Literature Center Web Site Registers Revision ID Class Code Registers Offset 08 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 I 1 0 9 8 7 6 5 4 3 2 1 OF 9 8 7 6 5 4 3 2 1 OF of 81 71 6 5 4 3 21 10 Name CLASS REVID Operation R R Reset 060000 01 REVID Revision ID This register identifies the PHB revision level This register is duplicated in the PPC Registers CLASS Class Code This register identifies PHB as the following Base Class Code 06 PCI Bridge Device Subclass Code 00 PCI Host Bridge Program Class Code 00 Not Used Header Type Register Offset 0C Bii AAAI MISA E ES E ES enn Ea hse A P Rn Name HEADER Operation R R R Reset 00 00 00 00 The Header Type Register Header identifies the PHB as the following Header Type 00 Single Function Configuration Header http www motorola com computer literature 2 95 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller MPIC Base Address
242. ng SDRAMs that have various speed characteristics The bits that control this configuration are located in the SDRAM Speed Attributes Register which is described in the Register portion of this section Refer to the table below for some specific timing numbers http www motorola com computer literature 3 7 System Memory Controller SMC Table 3 1 60x Bus to SDRAM Estimated Access Timing at 100MHz with PC100 SDRAMs CAS latency of 2 Access Type 4 Beat Read after idle SDRAM Bank Inactive Access Time tB1 tB2 tB3 tB4 10 1 1 1 Comments 4 Beat Read after idle SDRAM Bank Active Page Miss 12 1 1 1 4 Beat Read after idle SDRAM Bank Active Page Hit 7 1 1 1 4 Beat Read after 4 Beat Read SDRAM Bank Active Page Miss 5 1 1 1 4 Beat Read after 4 Beat Read SDRAM Bank Active Page Hit 2 5 1 1 1 2 5 1 1 1 is an average of 2 1 1 1 half of the time and 3 1 1 1 the other half 4 Beat Write after idle SDRAM Bank Active or Inactive 4 1 1 1 4 Beat Write after 4 Beat Write SDRAM Bank Active Page Miss 6 1 1 1 4 Beat Write after 4 Beat Write SDRAM Bank Active Page Hit 3 1 1 1 3 1 1 1 for the second burst write after idle 2 1 1 1 for subsequent burst writes 1 Beat Read after idle SDRAM Bank Inactive 10 1 Beat Read after idle SDRAM Bank Active Page Miss 12 1 Beat Read after idle SDRAM Bank Active Page Hit 1 Be
243. nnection allows stacking of one or two PMCspan dual PMC carrier boards to increase the I O capability Each PMCspan board requires an additional VME slot http www motorola com computer literature 1 5 Board Description and Memory Maps Programming Model Memory Maps The following sections describe the memory maps for the MVME2400 series Processor Memory Maps The Processor memory map is controlled by the Hawk ASIC The Hawk ASIC has flexible programming Map Decoder registers to customize the system to fit many different applications Default Processor Memory Map After a reset the Hawk ASIC provides the default processor memory map as shown in the following table Table 1 2 Default Processor Memory Map Processor Address Size Definition Notes Start End 0000 0000 7FFF FFFF 2G Not mapped 8000 0000 8001 FFFF 128K PCI ISA I O Space 1 8002 0000 FEF7 FFFF 2G 16M Not mapped 640K FEF8 0000 FEF8 FFFF 64K SMC Registers FEF9 0000 FEFE FFFF 384K Not mapped FEFF 0000 FEFF FFFF 64K PHB Registers 00 0000 15 Not mapped FFFO 0000 FFFF FFFF IM ROM FLASH Bank A or Bank B 2 Computer Group Literature Center Web Site Programming Model Notes 1 This default map for PCI ISA I O space allows software to determine if the system is MPC105 based or Hawk based by examining either the PHB Device ID or the CPU Type Register 2 The first one
244. not be required If such is the case swr_dpl can be cleared by software tdp tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its tdp parameter When tdp is 0 the minimum time provided for Tdp is 1 clock When tdp is 1 the minimum is 2 clocks trp trp determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its Trp parameter When trp is 0 the minimum time provided for Trp is 2 clocks When trp is 1 the minimum is 3 clocks tred tred determines the minimum number of clock cycles that the SMC assumes the SDRAM requires to satisfy its tred parameter When tred is 0 the minimum time provided for tred is 2 clocks When trcd is 1 the minimum is 3 clocks Address Parity Error Log Register Address FEF800E0 Bit oA UA eo ban bani hanl bani m9 I NY ee ms BEBE 2 o of ol ol 8 8 amp 8 S 8 Operation y 2 READ ZERO E e 24 24 24 in o Reset AX al e oo oo o x x xxo o lt PS PX PS PX PSS apelog apelog is set when a parity error occurs on the PP
245. ns to be flushed from the FIFO write posted transfers will be completed before aread or compelled write is begun to assure that all transfers are completed in the order issued http www motorola com computer literature 2 47 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI Configuration cycles intended for internal PHB registers will also be delayed if PHB is busy so that control bits which may affect write posting do not change until all write posted transactions have completed For the same reason all PPC60x write posted transfers will also be completed before any access to the PHB PPC registers is begun The PCI Local Bus Specification 2 1 states that posted write buffers in both directions must be flushed before completing a read in either direction PHB supports this by providing two optional FIFO flushing options The XFBR PPC60x Flush Before Read bit within the GCSR register controls the flushing of PCI write posted data when performing PPC originated read transactions The PFBR PCI Flush Before Read bit within the GCSR register controls the flushing of PPC write posted data when performing PCI originated read transactions The PFBR and XFBR functions are completely independent of each other however both functions must be enabled to guarantee full compliance with PCI Local Bus Specification 2 1 When the XFBR bit is set the PHB will handle read transactions originating from the PPC bus in the f
246. nsaction could be interrupted between write cycles and thereby result in a partially completed write cycle It is recommended that write cycles to write sensitive non posted locations be performed on mod 4 address boundaries The PCI Master must make the determination to perform the resolution function since it must make some decisions on possibly removing a currently pending command from the PPC FIFO http www motorola com computer literature 2 45 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller There are some performance issues related to bridge lock resolution PHB offers two mechanism that allow fine tuning of the bridge lock resolution function Programmable Lock Resolution Consider the scenario where the PPC Slave is hosting a read cycle and the PCI Slave is hosting a posted write transaction If both transactions happen at roughly the same time then the PPC Slave will hold off its transaction until the PCI Slave can fill the PCI FIFO with write posted data Once this happens both slaves will be stalled and a bridge lock resolution cycle will happen The effect of this was to make the PPC Slave waste PPC bus bandwidth In addition a full PCI FIFO will cause the PCI Slave to start issuing wait states to the PCI bus From the perspective of the PCI bus a better solution would be to select a PCI FIFO threshold that will allow the bridge lock resolution cycle to happen early enough to keep the PCI FIFO from ge
247. nterrupt 0 1 4 14 IRQ6 N A N A Not used 15 IRQ7 N A N A Not used Notes 1 Internally generated by the PIB 2 After a reset all ISA IRQ interrupt lines default to edge sensitive mode 3 These PCI interrupts are routed to the ISA interrupts by programming the PRIQ Route Control Registers in the PIB The PCI to ISA interrupt assignments in this table are suggested Each 5 6 Computer Group Literature Center Web Site ISA DMA Channels 4 ISA IRQ to which a PCI interrupt is routed to MUST be programmed for level sensitive mode Use this routing for PCI interrupts only when the MPIC is either not present or not used The MPIC when present should be used for these interrupts ISA DMA Channels The MVME2400 series does not implement any ISA DMA channels Exceptions Sources of Reset There are nine potential sources of reset on the MVME2400 series They are ON A Q N Power On Reset RESET Switch Watchdog Timer Reset via the MK48T59 Timekeeper device Port 92 Register via the PIB I O Reset via the Clock Divisor Register in the PIB VMEbus SYSRESET signal Local software reset via the Universe II ASIC MISC Register VME System Reset Via the Universe II ASIC MISC CTL Register VME CSR reset via the Universe II ASIC VCSR SET Register http www motorola com computer literature 5 7 Programming Details The following table shows which devices are affected by vari
248. nterrupt Acknowledge cycles and a bit clear command during End Of Interrupt cycles ISR is implemented as a 40 bit register with individual bit set and clear functions Fifteen bits are used to store the priority level of each interrupt which is in service Twenty five bits are used to store the source identification of each interrupt which is in service Therefore there is one bit for each possible interrupt priority and one bit for each possible interrupt source Interrupt Router The Interrupt Router monitors the outputs from the ISR s Current Task Priority Registers Destination Registers and the IRR s to determine when to assert a processor s INT pin When considering the following rule sets it is important to remember that there are two types of inputs to the Interrupt Selectors If the interrupt is a distributed class interrupt there is a single bit in the IPR associated with this interrupt and it is delivered to both Interrupt Selectors This IPR bit is qualified by the destination register contents for that interrupt before the Interrupt Selector compares its priority to the priority of all other requesting interrupts for that processor If the interrupt is programmed to be edge sensitive the IPR bit is cleared when the vector for that interrupt is returned when the Interrupt Acknowledge register is examined On the other hand if the interrupt is a direct multicast class interrupt there are two bits in the IPR associated wi
249. nterrupts are ROAK while hardware and internal interrupts are RORA DMA Controller The Universe II provides an internal DMA controller for high performance data transfer between the PCI and VMEbus DMA operations between the source and destination bus are decoupled through the use of a single bidirectional FIFO DMAFIFO Parameters for the DMA transfer are software configurable in the Universe II registers Refer to the section entitled DMA Controller in the Universe II User Manual listed in Appendix B Related Documentation The principal mechanism for DMA transfers is the same for operations in either direction PCI to VME or VME to PCD only the relative identity of the source and destination bus changes In a DMA transfer the Universe II gains control of the source bus and reads data into its DMAFIFO Following specific rules of DMAFIFO operation refer to the section entitled FIFO Operation and Bus Ownership in the Universe II User Manual listed in Appendix B Related Documentation it then acquires the destination bus and writes data from its DMAFIFO The DMA controller can be programmed to perform multiple blocks of transfers using entries in a linked list The DMA will work through the transfers in the linked list following pointers at the end of each linked list entry Linked list operation is initiated through a pointer in an internal Universe II register but the linked list itself resides in PCI bus memory http www mo
250. nterrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set PRIOR Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrupt associated with this vector http www motorola com computer literature 2 115 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Timer Destination Registers Offset Timer 0 01130 Timer 1 01170 Timer 2 011B0 Timer 3 011F0 N N Bit 3 3 2 2 2 2 2 2 2 1 0 9 8 7 6 5 4 3 2 1 OF 9 8 7 6 5 4 3 2 109876 5 4 3 2 1 TIMER DESTINATION Id Operation R R R R 0 Od Reset 00 00 00 00 This register indicates the destinations for this timer s interrupts Timer interrupts operate in the Directed delivery interrupt mode This register may specify multiple destinat
251. ntity is free If the data transfer will be a read the SMC begins providing data to the PPC60x bus as soon as the entity has data ready and the PPC60x data bus is granted If the data transfer will be a write the SMC begins latching data from the PowerPC data bus as soon as any previously latched data is no longer needed and the PPC60x data bus is available PPC60x Data Parity The Hawk has 8 DP pins for generating and checking PPC 60x data bus parity During read cycles that access the SMC the Hawk generates the correct value on DPO DP7 so that each data byte lane along with its corresponding DP signal has odd parity This can be changed on a lane basis to even parity by software bits that can force the generation of wrong even parity During write cycles to the SMC the SMC checks each of the eight PPC60x data byte lanes and its corresponding DP signal for odd parity If any of the eight lanes has even parity the SMC logs the error in the CSR and can generate a machine check if so enabled While normal default operation is for the SMC to check data parity only on writes to it it can be programmed to check data parity on all reads or writes to any device on the PPC bus Refer to the Data Parity Error Log Register section further on in this document for additional control register details PPC60x Address Parity The Hawk has 4 AP pins for generating and checking PPC60x address bus parity http www motorola com computer l
252. ocal Bus Specification 2 1 using Configuration Mechanism 1 to generate special cycles To prime the PHB for a special cycle the host processor must write a 32 bit value to the CONFIG_ADDRESS register The contents of the write are defined later in this chapter under the CONFIG_ADDRESS Register definition After the write to CONFIG_ADDRESS has been accomplished the next write to the CONFIG_DATA register causes the PHB to generate a special cycle on the PCI bus The write data is driven onto AD 31 0 during the special cycle s data phase http www motorola com computer literature 2 33 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Generating PCI Interrupt Acknowledge Cycles Performing a read from the PIACK register will initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the PHB will present the resulting vector information obtained from the PCI bus as read data PCI Arbiter The Hawk s internal PCI arbiter supports up to 8 PCI masters This includes Hawk and 7 other external PCI masters The arbiter can be configured to be enabled or disabled at reset time by strapping the rd 9 bit either high for enabled or low for disabled The following t
253. of columns is COLUMNS and the value in SPD byte 4 is C then COLUMNS 2 Calculate the total number of addresses within each device If the total number of addresses a device is A then AZROWS X COLUMNS Calculate the total number of locations in the block using the results of step 3 and SPD byte 17 If the total number of locations in the block is L and the value in byte 17 is 4 then L Ax4 or 2 22 4 Note that the Hawk only works if byte 17 is 4 Obtain the primary device width from SPD byte 13 Determine the size bits based on the results of steps d and e using the following table Computer Group Literature Center Web Site Software Considerations Table 3 19 Programming SDRAM 517 Bits Total Number Primary Block Size 2 Value to be of Locations Device Width programmed within the into the Block L Block s ram x Sizbits 4 4M 16 32Mbytes 260001 8M 8 64Mbytes 260010 8M 16 64Mbytes 0011 16M 4 128Mbytes 0100 16M 8 128Mbytes 0101 16M 16 128Mbytes 0110 32M 4 256Mbytes 260111 32M 8 256Mbytes 1000 64M 4 512Mbytes 1001 Notes 1 Total Number of block Locations L is 2 x 2 x 4 where R is the value in SPD byte 3 and C is the value in SPD byte 4 2 Primary Device Width is from SPD byte 13 3 Block Size is the total number of block locations L x 8 bytes 4 ram x siz refers to ram_a_siz ram b siz ram_c_siz etc Refer to the s
254. of the PIB Timer1 CounterO IRQ1 PIRQO IRQx PIRQ Route IRQS Control Register Controller 1 INTR IRQ4 4 1 IRQ5 IRQ6 PIRQ1_ IRQx IRQ7 PIRQ Route Control Register PIRQ2 IRQx IRQ8 PIRQ Route Control Register IRQ9 IRQ10 IRQ11 Controller 2 PIRQS_ PIRQ Route IRQx IRQ12 INT2 j gt 4 IR Control Register Rai IRQ14 IRQ15 1897 9609 Figure 5 2 PIB Interrupt Handler Block Diagram http www motorola com computer literature 5 5 Programming Details Table 5 3 PIB PCI ISA Interrupt Assignments The assignments of the PCI and ISA interrupts supported by the PIB are as follows PRI ISA PCI al Edge Interrupt Source Notes IRQ IRQ Level 2 3 5 2 1 IRQO Edge High Timer 1 Counter 0 1 2 IRQI N A Not used 3 10 IRQ2 Edge High Cascade Interrupt from INT2 3 IRQ8_ INT2 Edge Low ABORT Switch Interrupt 4 IRQ9 N A Not used 5 IRQIO PIRQO_ Level Low PCI Ethernet Interrupt 2 3 4 6 IRQI1 PIRQI_ Level Low Universe II Interrupt LINTO 2 3 4 7 IRQ12 N A N A Not used 8 IRQ13 N A N A Not used 9 IRQ14 PIRQ2_ N A N A Not used 10 IRQI5 PIRQ3_ Level Low PMC PCIX Interrupt 2 3 4 11 IRQ3 N A N A Not used 12 IRQ4 Edge High COMI 16550 13 5 Level High LM SIG I
255. of this operation To allow PCI masters to perform RMW and ADOH cycles the Universe II provides a Special Cycle Generator The Special Cycle Generator can be used in combination with a VMEbus ownership function to guarantee PCI masters exclusive access to VMEbus resources over several VMEbus transactions and Refer to the sections entitled Exclusive Accesses and RMW Cycles in the Universe IT User Manual Appendix B Related Documentation for a full description of this functionality http www motorola com computer literature 4 5 Universe II VMEbus to PCI Chip Universe II as PCI Master The Universe II becomes PCI master when the PCI Master Interface is internally requested by the VME Slave Channel or the DMA Channel There are mechanisms provided which allow the user to configure the relative priority of the VME Slave Channel and the DMA Channel Interrupter and Interrupt Handler Interrupter The Universe II interrupt channel provides a flexible scheme to map interrupts to either the PCI bus or VMEbus interface Interrupts are generated from either hardware or software sources Refer to the section entitled Interrupter in the Universe User Manual listed in Appendix B Related Documentation for a full description of hardware and software sources Interrupt sources can be mapped to any of the PCI bus or VMEbus interrupt output pins Interrupt sources mapped to VMEbus interrupts are generated on the VMEb
256. ol any hardware PCI Registers The PCI Configuration Registers are compliant with the configuration register set described in the PCI Local Bus Specification Revision 2 1 The CONFIG ADDRESS Register and the CONFIG DATA Register described in this section are accessed from the PPC bus within PCI I O space write operations to reserved registers will be treated as no ops That is the access will be completed normally on the bus and the data will be discarded Read accesses to reserved or unimplemented registers will be completed normally and a data value of 0 returned The PCI Configuration Register map of the PHB is shown in Table 2 17 The PCI I O Register map of the PHB is shown in Table 2 18 Table 2 17 PCI Configuration Register Map 33222222222211111111 1 1 lt Bit 1098765 432109 ils 6 5 4 3 21109876 5 4132 1 0 DEVID VENID 00 STATUS COMMAND 04 CLASS REVID 08 HEADER 0C MIBAR 10 MMBAR 14 18 7C PSADDO 80 PSOFFO PSATTO 84 PSADDI 88 PSOFFI PSATTI 8C http www motorola com computer literature 2 91 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 17 PCI Configuration Register Map Continued
257. ollowing manner Write posted transactions originating from the processor bus are flushed by the nature of the FIFO architecture The PHB will hold the processor with wait states until the PCI bound FIFO is empty Write posted transactions originated from the PCI bus are flushed whenever the PCI slave has accepted a write posted transaction and the transaction has not completed on the PPC bus The PPC Slave address decode logic settles out several clocks after the assertion of TS at which time the PPC Slave can determine the transaction type If it is a read and XFBR is enabled the PPC Slave will look at the ps_fbrabt signal If this signal is active the PPC Slave will retry the processor When the PFBR bit is set PHB will handle read transactions originating from the PCI bus in the following manner Write posted transactions originating from the PCI bus are flushed by the nature of the FIFO architecture The PHB will hold the PCI Master with wait states until the PPC bound FIFO is empty 2 48 Computer Group Literature Center Web Site Functional Description Write posted transactions originated from the PPC60x bus are flushed in the following manner The PPC Slave will set a signal called xs fbrabt anytime it has committed to performing a posted write transaction This signal will remain asserted until the PCI bound FIFO count has reached zero The PCI Slave decode logic settles out several clocks afte
258. on The PCI Master can support parking on the PCI bus There are two cases where the PCI Master continuously asserts its request Ifthe PCI Master starts a transaction that is going to take more than one assertion of FRAME the PCI Master continuously asserts its request until the transaction has completed For example the PCI Master continuously asserts requests during the first part of a two part critical word first transaction Ifatleast one command is pending within the FIFO The PCI Master always removes its request when it receives a disconnect Or a retry There is a case where the PCI Master could assert a request but not actually perform a bus cycle This may happen if the PCI Master is placed in the speculative request mode Refer to the section entitled PCI PPC Contention Handling for more information In no case will the PCI Master assert its request for more than 16 clocks without starting a transaction Fast Back to Back Transactions The PCI Master does not generate fast back to back transactions Arbitration Latency Because a bulk of the transactions are limited to single beat transfers on PCI the PCI Master does not implement a Master Latency Timer Exclusive Access The PCI Master 15 not able to initiate exclusive access transactions Address Data Stepping The PCI Master does not participate in the Address Data Stepping protocol http www motorola com computer literature 2 29 Hawk PCI Host Bri
259. onfiguration Options Data A 3 VPD Data Definitions FLASH Memory Configuration Data A 5 VPD Data Definitions L2 Cache Configuration A 6 xiii Example VPD SROM 9 APPENDIX Related Documentation Motorola Computer Group Documenis ueris ae B 1 Wlanvifactiiners Brei M B 1 Related Specie pons NR B 4 List of Figures Figure 1 1 MVME2400 Series System Block Diagram 22 2 2 1 4 Figure 1 2 Master 1 19 Fiame Slave 1 21 Figure 1 4 General Purpose Software Readable 1 26 Figure 2 1 Hawk s PCI Host Bridge Block Diagram eee 2 3 2 2 PPC to PCI Address Decodtlg eoce retten rb tre reat 2 6 Figure 2 3 PPC to PCI Address Translation saec epe 2 7 Faguie 2 4 PCI to PPC Address Decodiug usine rrt to tros 2 20 Figure 2 5 PCI ta PPC Address Translation nii arde brin 2 21 Figure 2 6 PCI Spread Address Translation iiec teet 2 31 Figure 2 7 Big ta Little Data Swap eorr
260. or Device Register 3 39 Spurious Vector MPIC 2 112 Timer Basecount MPIC 2 114 Timer Current Count MPIC 2 113 Timer Destination 2 116 Timer Frequency MPIC 2 112 Timer Vector Priority 2 115 Vendor Identification MPIC 2 110 WDTXCNTL 2 88 WDTXxSTAT 2 90 writing to the control registers 3 74 registers Universe II Control and Status Registers UCSR 4 8 related documentation ordering A 1 B 1 related specifications B 4 reset sources and devices affected 5 8 Resources via ISA Local Resource Bus 1 25 Revision ID 3 40 Revision ID Register 2 68 Revision ID Class Code Registers 2 95 Revision ID General Control Register 3 39 ROM 5 15 ROM Block A Size Encodings 3 54 ROM Block B Size Encoding 3 57 ROM Speed Attributes Register SMC 3 58 ROM Flash 3 17 ROM Flash A Base Address control bits 3 53 ROM Flash A Base Size Register SMC 3 53 ROM Flash A size encoding 3 54 ROM Flash A Width control bit 3 54 ROM Flash B Base Address control bits 3 56 ANNNN ROM Flash B Base Size Register SMC 3 56 ROM Flash B Width control bit 3 57 ROM FLASH bank default 5 15 ROM Flash initialization SMC 5 15 ROM Flash Interface 3 17 ROM Flash interface 3 17 ROM Flash speeds of SMC 3 10 rom_a_64 3 54 ROM_A_BASE 3 53 rom_a_en 3 55 rom_a_rv 3 54 a rv and rom b rv encoding 3 54 rom siz 3 54 rom a we 3 55 rom b 64 3 57 B BASE 3 56 rom b en 3 57 rom b rv 3 57 rom b 512 3 57 rom b we 3 57 Row Address 3 52 rwcb 3 46 S SBE
261. orola com computer literature 3 59 System Memory Controller SMC dpe me When dpe me is set the transition of the dpelog bit from false to true causes the Hawk to pulse its machine check interrupt request pin MCHKO true When dpe me is cleared the Hawk does not assert its MCHKO pin based on the dpelog bit GWDP The GWDPO0 GWDPT bits are used to invert the value that is driven onto DPO DP7 respectively during reads to the Hawk This allows test software to generate wrong even parity on selected byte lanes For example to create a parity error on DH24 DH31 and DP3 during Hawk reads software should set GWDP3 Data Parity Error Address Register Address FEF80070 i e e el o S 9 2 SIR lt amp amp 4 8 5 4 3 RS Name DPE A Operation READ ONLY Reset 0 PL DPE A DPE A isthe address ofthe last PPC60x data bus parity error that was logged by the Hawk It is updated only when dpelog goes from 0 to 1 Data Parity Error Upper Data Register Address SFEF80078 Bit o nqieexeemelemeioamuwoeroodo SY AY OF SE OY CO NY eve C9 09 Name DPE_DH Operation READ ONLY Reset 0 PL DPE DH DPE DH is the value on the upper half of the PPC60x data bus at the time of the la
262. otification and Handlitig n rere 5 9 Table 5 6 KONUPLASH Bank oeste prn Ee anesan 5 15 xviii Table 1 Table 2 Table 3 Table 4 5 Table B 1 Table B 2 Table B 3 VPD Packet NRA 1 MVME2400 Product Configuration Options Data 3 FLASH Memory Configuration Data 22222 2 2 A 5 L2 Cache Configuration se rr HERR ERR toas oai iu tig 6 VPD SROM Configuration Specification for 01 W3394F01 9 Motorola Computer Group Documents eerte ntes B 1 DOCHDNERES io uelis Ur bia B 2 Related S pect t SOR oou nece etie adc bbc epis bob BS pt urea B 5 xix About This Manual The MVME2400 Series VME Processor Module Programmer s Reference Guide provides brief board level information complete memory maps and detailed ASIC chip information including register bit descriptions for the MVME2400 series VME Processor Modules also called MVME240x in this manual The information contained in this manual applies to the single board computers built from some of the plug together components listed in the following table Model Number Description MVME 2401 1 MPC750 233MHz 32MB SDRAM MVME2401 3 MPC750 233MHz 32MB SDRAM MVME2402 1 MPC750 233MHz 64MB ECC S
263. otorola com computer literature 2 35 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller When the arbiter is programmed for round robin priority mode the arbiter maintains fairness and provides equal opportunity to the requestors by rotating its grants The contents in HEIR field are don t cares when operated in this mode When the arbiter is programmed for mixed mode the 8 requestors are divided up into 4 groups and each groups is occupied by 2 requestors PARB6 and PARBS are defined in groupl PARB4 and PARB3 are defined in group 2 PARB2 and are defined in group 3 PARBO and are defined in group 4 Arbitration is set for round robin mode between the 2 requestors within each group and set for fixed mode between the 4 groups The levels of priority for each group is programmable by writing the HEIR field in the PCI Arbiter control register The following table describes all available setting for the HEIR field in mixed mode Table 2 11 Mixed Mode Priority Level Setting HEIR PRIORITY Levels Setting Highest Lowest 000 group 1 group 2 group 3 group 4 PARB6 amp 5 4 amp 3 2 amp 1 PARBO amp HAWK 001 group 4 group 1 group 2 group 3 PARBO amp HAWK PARB6 amp 5 PARB4 amp 3 2 amp 1 010 group 3 group 4 group 1 group 2 PAR2 amp 1 PARBO amp HAWK PARB6 amp 5 PARB4 amp 3 011 group 2 group 3
264. ous reset sources Table 5 4 Reset Sources and Devices Affected Device Affected 7 z 2 5 p S 2 q 5 z S 5 Z al i oO 2 5 A e 5 Power On X X X x Reset Switch X X X X X x Watchdog MK48T59 VME System Reset SYSRESET Signal System Software Reset MISC X X X X X X Register VME Local Software Reset MISC CTL x x x x x Register VME CSR Reset VCSR_SET Register Hot Reset Port 92 Register Reset Clock Divisor Register x x Soft Reset Software can assert the SRESET pin of any processor by programming the Processor Init Register of the MPIC appropriately Universe Chip Problems after a PCI Reset Under certain conditions there can be problems with the Universe II chip after a PCI reset Refer to Chapter 4 Universe II VMEbus to PCI Chip for details 5 8 Computer Group Literature Center Web Site Exceptions Error Notification and Handling The Hawk ASIC can detect certain hardware errors and can be programmed to report these errors via the MPIC interrupts or Machine Check Interrupt Note that the TEA signal is not used at all by the MVME2400 series The following table summarizes how the hardware errors are handled by the MVME2400 series Table 5 5 Error Notification and Handling
265. peration READ WRITE Reset 0 PL CTR32 CTR32 is a 32 bit free running counter that increments once per microsecond if the CLK FREQUENCY register has been programmed properly Notice that CTR32 is cleared by power up and local reset http www motorola com computer literature 3 71 System Memory Controller SMC Note When the system clock is a fractional frequency such as 66 67MHz CTR32 will count at a fractional amount faster or slower than 1MHz depending on the programming of the CLK FREQUENCY Register External Register Set Address 88000 FEF8FFF8 Bit JR gt Oo I OO o re IN IN NIN IN W o2 SJ IN JH gt ID 100 o Q O Jr IN G0 gt 1 00 O O Name EXTERNAL REGISTER SET Operation READ WRITE Reset X PL EXTERNAL REGISTER SET The EXTERNAL REGISTER SET is user provided and is external to the Hawk It is enabled only when the en bit is cleared When the tben en bit is set the EXTERNAL REGISTER SET is disabled and the Hawk does not respond in its range except for the tben register at FEF88300 The tben register which is internal to Hawk responds only when tben_en is set The Hawk s EXTERNAL REGISTER SET interface is similar to that for ROM Flash Block A and B In fact another name for the External Regis
266. pin becomes the pO tben output pin Also the SMC does not respond to accesses that fall within the external register set address range except for the address FEF88300 When tben en is cleared the Clm and ercs_ pins retain their normal function and the SMC does respoond to external register set accesses Software should only set the tben_en bit when there is no external L2 cache connected to the I Clm_ pin and when there is no external register set REVID The REVID bits are hard wired to indicate the revision level of the SMC The value for the first revision is 01 aonly en Normally the SMC responds to address only cycles only if they fall within the address range of one of its enabled map decoders When the aonly en bit is set the SMC also responds to address only cycles that fall outside of the range of its enabled map decoders provided they are not acknowledged by some other slave within 8 clock periods aonly en is read only and reflects the level that was on the RD4 pin at power up reset time 3 40 Computer Group Literature Center Web Site Programming Model isa hole When itis set isa hole disables any of the SDRAM or ROM Flash blocks from responding to PowerPC accesses in the range from 000A0000 to 000BFFFF This has the effect of creating a hole the SDRAM memory map for accesses to ISA When isa_hole is cleared there is no hole created in the memory map pu statO0 pu stat3 pu statO pu statl stat2
267. pin s frequency is lower than the value programmed into CLK FREQUENCY por por is set by the occurrence of power up reset It is cleared by writing a one to it Writing a to it has no effect ECC Control Register Address FEF80028 Bit J to Jud Jen Jan Joo JR 1 1 1 t 12 t2 2 2 SIRE IN o gt NID 2 t G9 gt J SO Name IO I O l oO o AO jojojo j2 5 pOIoo eoPIo HS 8 C CERES EUG B Operation READ ZERO PERAR EEE e Reset gt gt lt gt lt xeeirxxuiselejss be gt lt be bx S 9 d d EE p 1 E refdis When set refdis causes the refresher and all of its associated counters and state machines to be cleared and maintained that way until refdis is removed cleared If a refresh cycle is in process when refdis is updated by a write to this register the update does not take effect until the refresh cycle has completed This prevents the generation of illegal cycles to the SDRAM when refdis is updated http www motorola com computer literature 3 45 System Memory Controller SMC rwcb When set rwcb causes reads and writes to SDRAM from the PPC60x bus to access check bit data rather than normal data The data path used for readin
268. ponding PCI slave RAEN Read Ahead Enable If set read ahead is enabled for the corresponding PCI slave WPEN Write Post Enable If set write posting is enabled for the corresponding PCI slave WEN Write Enable If set the corresponding PCI slave is enabled for write transactions REN Read Enable If set the corresponding PCI slave is enabled for read transactions http www motorola com computer literature 2 99 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller RMFTXx Read Multiple FIFO Threshold This field is used by the PHB to determine a FIFO threshold at which to continue prefetching data from local memory during PCI read multiple transactions This threshold applies to subsequent prefetch reads since all initial prefetch reads will be four cache lines This field is only applicable if read ahead has been enabled The encoding of this field is shown in the table below Subsequent Prefetch FIFO Threshold 00 0 Cache lines 01 Cache line 10 2 Cache lines 11 3 Cache lines The PCI Slave Offset Registers contain offset information associated with the mapping of PCI memory space to PPC memory space The field within the PSOFFx registers is defined as follows PSOFFx PCI Slave Offset This register contains a 16 bit offset that is added to the upper 16 bits of the PCI address to determine the PPC address used for transfers from PCI to the
269. pt source to be directed to either processor Multilevel cross processor interrupt control for multiprocessor synchronization Four Interprocessor Interrupt sources Four 32 bit tick timers Processor initialization control Two 64 bit general purpose registers for cross processor messaging Computer Group Literature Center Web Site 2 3 Block Diagram Block Diagram 007 Jaq Odd Odd Odd Jeisew ld Aled lOd 19 518151534 DIJN eS 9 8lS 19d L 2 1S0H 5 Odd Odd 4 15 Odd ABIS Odd T lt lt xn B TM Oda Bred 70 0913 lt TED 32010 129 299 lt 1 7 0314 ma i XnIN mndno 19d 0313 sng Figure 2 1 Hawk s PCI Host Bridge Block Diagram http www motorola com computer literature 2 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Functional Descrip
270. puter literature MVME2400 VPD Reference Information Table A 4 L2 Cache Configuration Data Continued Byte Offset OB Field Size Bytes 1 Field Mnemonic L2C_ERROR_DETECT Field Description Error Detection Type 00 None 01 Parity 02 ECC 0C L2C SIZE L2 Cache Size Should agree with the physical organization above 00 256K 01 512K 02 IM 03 2M 04 AM 0 L2C TYPE BACKSIDE L2 Cache Type Backside Configurations 00 Late Write Sync 1nS Hold Differential Clock Parity 01 Pipelined Sync Burst 0 5nS Hold No Differentia Clock Parity 02 Late Write Sync 1nS Hold Differential Clock No Parity 03 Pipelined Sync Burst 0 5nS Hold No Differential Clock No Parity L2C RATIO BACKSIDE L2 Cache Core to Cache Ration Backside Configurations 00 Disabled 01 1 1 1 02 3 2 1 5 03 2 1 2 04 5 2 2 5 05 3 1 3 Note Itis possible for a product to contain multiple L2 cache configuration packets Computer Group Literature Center Web Site Vital Product Data VPD Introduction Example VPD SROM One MVME2400 board build configuration example is provided below Table 5 VPD SROM Configuration Specification for 01 W3394F01 Offset Value Field Type Description 00 0x00 4D ASCII Eye Catcher MOTOROLA Note Lowest CRC byte for
271. r SMC 2 Control Register Address FEF80098 Bit SF WI WO CO 10 11 12 13 14 15 16 17 18 19 20 24 29 30 21 22 23 25 26 27 28 Stop 12 ackout 12 start 12 sto Operation READ ZERO READ ZERO READ ZERO 04 Reset X X R W R W R W OPL R W PI lt I lt I PS i2_start When set the master controller generates a start sequence on the bus on the next write to the Transmitter Data Register and clears the 12 cmplt bit in the Status Register After the start sequence and the PC Transmitter Data Register contents have been transmitted the C master controller will automatically clear the i2 start bit and then set the 12 cmplt bit in the PC Status Register i2 stop When set the master controller generates a stop sequence on the C bus on the next dummy write data don t care to the PC Transmitter Data Register and clears the i2 cmplt bit in the PC Status Register After the stop sequence has been transmitted the master controller will automatically clear the i2 stop bit and then set the i2 cmplt bit in the Status Register i2 ackout When set the master controller generates an acknowledge on the PC bus during read cycles This bit should be used only in the PC seq
272. r Data Register and Receiver Data Register The serial data SDA is an open drain bidirectional line on which data can be transferred at a rate up to 100 Kbits s in the standard mode or up to 400 kbits s in the fast mode The C serial clock SCL is programmable vial2 PRESCALE VAL bits in the Clock Prescaler Register The PC clock frequency is determined by the following formula CLOCK SYSTEM CLOCK I2 PRESCALE VAL41 2 The bus has the ability to perform byte write page write current address read random read and sequential read operations 12C Byte Write The 2C Status Register contains the 12 bit which is used to indicate if the C master controller is ready to perform an operation Therefore the first step in the programming sequence should be to test the 12 bit for the operation complete status The next step is to initiate a start sequence by first setting the 12 start and 12 enbl bits in the PC Control Register and then writing the device address bits 7 1 and write bit bit 0 0 to the 2C Transmitter Data Register The i2 cmplt bit will be automatically clear with the write cycle to the Transmitter Data Register The PC Status Register must now be polled to test the i2_cmplt and i2_ackin bits The i2_cmplt bit becomes set when the device address and write bit have been transmitted and the i2_ackin bit provides status as to whether or not a slave device acknowledged the
273. r VMEbus Slave Map Example Configuration Configuration Register Value Register Value Address Offset Register Name CHRP PREP VSIO CTL COF2 0001 COF2 0001 F04 VSIO BS 4000 0000 4000 0000 8 VSIO BD 4000 1000 4000 1000 VSIO TO C000 1000 C000 1000 14 8 EOF2 00 0 EOF2 00 0 18 VSII BS 1000 0000 1000 0000 1 8 BD 2000 0000 2000 0000 20 VSII TO F000 0000 7000 0000 F28 VSD CTL 0000 0000 0000 0000 F2C VSD BS XXXX XXXX XXXX XXXX F30 VSI2_BD XXXX XXXX XXXX XXXX F34 VSD TO XXXX XXXX XXXX XXXX VSI3 0000 0000 0000 0000 40 VSI3 BS XXXX XXXX XXXX XXXX F44 VSI3_BD XXXX XXXX XXXX XXXX 48 VSI3 XXXX XXXX XXXX XXXX The above register values yield the following VMEbus slave map 1 22 Computer Group Literature Center Web Site Programming Model Table 1 14 VMEbus Slave Map Example VMEbus Address Size CHRP Map PREP Map Range Mode 4000 0000 A32 U S P D 4K I O Space PCI ISA I O Space 4000 OFFF D08 16 32 0000 1000 0000 1FFF 0000 1000 0000 1FFF 1000 0000 A32 U S P D 256M PCI ISA Memory Space PCI ISA Memory Space 1 FFFF D08 16 32 64 On board DRAM On board DRAM RMW 0000 0000 OFFF FFFF 8000 0000 8FFF FFFF System Configuration Information The MVME2400 uses a 512 byte serial EEPROM to store Vital Product Data VPD The VPD is a
274. r all burst write cycles The encoding of this field is shown in the table below FSWx Flatten Single Write This field is used by the PPC Arbiter to control how bus pipelining will be affected after all single beat write cycles The encoding of this field is shown in the table below FBR FSR FBW FSW Effects on Bus Pipelining 00 None 01 10 Flatten always 11 Flatten if switching masters http www motorola com computer literature 2 71 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PRI Priority If set the PPC Arbiter will impose a rotating between CPUO grants If cleared a fixed priority will be established between CPUO and CPUI grants with CPUO having a higher priority than CPUI PRKx Parking This field determines how the PPC Arbiter will implement CPU parking The encoding of this field is shown in the table below PRK CPU Parking 00 None 01 Park on last CPU 10 Park always on CPUO 11 Park always on CPUI ENA Enable This read only bit indicates the enabled state of the PPC Arbiter If set the PPC Arbiter is enabled and is acting as the system arbiter If cleared the PPC Arbiter is disabled and external logic is implementing the system arbiter Refer to the section titled PHB Hardware Configuration for more information on how this bit gets set The PCI Arbiter Register PARB provides control and status for the PCI Arbiter Refer to th
275. r present 23 PCO_SCSI4_CONN SCSI device 4 connector present 24 PCO_SERIAL1_CONN Serial device 1 connector present 25 PCO_SERIAL2_CONN Serial device 2 connector present 26 PCO SERIAL3 CONN Serial device 3 connector present 27 SERIALA4 CONN Serial device 4 connector present 28 PCO FLOPPY CONNI Floppy device connector 1 present 29 PCO FLOPPY CONN2 Floppy device connector 2 present 30 PCO PARALLEL CONN Parallel device 1 connector present 31 PCO PARALLEL2 CONN Parallel device 2 connector present 32 PCO PMCI IO CONN PMC slot 1 I O connector present 33 PCO PMC2 IO CONN PMC slot 2 connector present 34 PCO USBO CONN USB channel 0 connector present 35 PCO USBI1 USB channel 1 connector present 36 PCO KEYBOARD CONN Keyboard connector present 37 PCO MOUSE CONN Mouse connector present 38 PCO_VGA1_CONN VGA device connector present A 4 Computer Group Literature Center Web Site Vital Product Data VPD Introduction Table A 2 MVME2400 Product Configuration Options Data Continued Bit Number Bit Mnemonic Bit Description 39 PCO SPEAKER CONN Speaker connector present 40 PCO VME CONN VME backplane connector present 41 Compact PCI backplane connector present 42 PCO ABORT SWITCH Abort switch present 43 PCO BDFAIL LIGHT Board fail light present 44 PCO SWREAD HEADER Software readable header present 45 Reserved for future configuration options 46 Reserved for future confi
276. r the assertion of FRAME at which time the PCI Slave can determine the transaction type If it is a read and PFBR is enabled the PCI Slave will look at the xs fbrabt signal If this signal is active the PCI Slave will retry the PCI Master PHB Hardware Configuration Hawk has the ability to perform custom hardware configuration to accommodate different system requirements The PHB has several functions that may be optionally enabled or disabled using passive hardware external to Hawk The selection process occurs at the first rising edge of CLK after RST has been released of the sampled pins are cascaded with several layers of registers to eliminate problems with hold time The following table summarizes the hardware configuration options that relate to the PHB Table 2 15 PHB Hardware Configuration Function Sample Pin s Sampled Meaning State PCI 64 bit Enable REQ64 0 64 bit PCI Bus 1 32 bit PCI Bus PPC Register Base RD 5 0 Register Base FEFF0000 1 Register Base FEFE0000 MPIC Interrupt Type RD 7 0 Parallel Interrupts 1 Serial Interrupts PPC Arbiter Mode RD 8 0 Disabled 1 Enabled PCI Arbiter Mode RD 9 0 Disabled 1 Enabled http www motorola com computer literature 2 49 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 15 PHB Hardware Configuration Continued Function Sample Pin s Sampled Meaning State PPC PCI Clock
277. rd44 4F rd60 D3 rd13 0E rd29 83 rd45 EO rd61 38 rd14 0D rd30 43 46 DO rd62 34 rd15 8C rd31 23 rd47 C8 rd63 32 amp Syndrome 3 86 Computer Group Literature Center Web Site ECC Codes Table 3 22 Single Bit Errors Ordered by Syndrome Code 8 1 a 8 8 4 amp 5 amp 3 E 00 20 ckd5 40 ckd6 60 80 ckd7 A0 8 0 rd4 5 01 0 21 41 61 rd42 81 1 rd38 Cl rd37 1 02 ckdl 22 42 62 rd41 82 A2 rd35 C2 rd34 E2 03 23 rd31 43 rd30 63 83 rd29 A3 C3 04 ckd2 24 44 64 rd55 84 A4 rd32 C4 rd33 E4 05 25 45 rd27 65 85 rd26 5 C5 5 06 26 9 46 rd23 66 86 rd22 A6 C6 E6 07 rd21 27 47 67 587 7 452 C7 E7 08 ckd3 28 48 68 rd54 88 8 rd51 C8 rd47 8 09 29 48 49 24 69 89 25 9 9 9 4 0A 2A rd3 4A 6 8 rd19 AA CA EA 0B rd18 2B 4B 6B 8B CB 0C 2C rd2 4C 86 58 rd15 AC CC 0D 414 520 4D 6D 8D AD CD ED 0E rd13 2E 4E 6E 8E CE 2 4F rd44 6F 8F AF
278. re 2 87 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller WPEN Write Post Enable If set write posting is enabled for the corresponding PPC slave PCI I O Mode If set the corresponding PPC slave will generate PCI I O cycles using spread addressing as defined in the section on Generating PCI Cycles When clear the corresponding PPC slave will generate PCI I O cycles using contiguous addressing WDTXCNTL Registers Address WDTICNTL FEFF0060 WDT2CNTL FEFF0068 Bit o l AT e DS SA x vq O AT SEY SO OO OY a EN TNT 01 NTT 0 WDTxCNTL Name gt 22 RES RELOAD m Operation W z R W 2 Reset 00 00 7 or 8 FF The Watchdog Timer Control Registers WDTICNTL WDT2CNTL are used to provide control information to the watchdog timer functions within the PHB The fields within WDTXCNTL registers are defined as follows KEY Key This field is used during the two step arming process of the Control register This field is sensitive to the following data patterns PATTERN_1 55 PATTERN_2 AA The Control register will be in the armed state if PATTERN_1 is written to the KEY field The Control register will be changed if in the armed state PATTERN 2 is written to
279. rectly to PCI The PHB performs spread I O addressing when the MEM bit is clear and the IOM bit is set The PHB takes the PPC address applies the offset specified in the MSOFFYx register and maps the result to PCI as shown in the following figure PPC Address Offset 31 12 11 54 0 X J 31 25 24 54 0 0000000 PCI Address 1915 9702 Figure 2 6 PCI Spread Address Translation Spread I O addressing allows each PCI device s I O registers to reside on a different PPC memory page so device drivers can be protected from each other using memory page protection All I O accesses must be performed within natural word boundaries Any I O access that is not contained within a natural word boundary results in unpredictable operation For example an I O transfer of four bytes starting at address 80000010 is considered a valid transfer An I O transfer of four bytes starting at address 8000001 1 is considered an invalid transfer since it crosses the natural word boundary at address 80000013 80000014 http www motorola com computer literature 2 31 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Generating PCI Configuration Cycles The PHB uses configuration Mechanism 1 as defined in the PCI Local Bus Specification 2 1 to generate configuration cycles Please refer to this specification for a complete description of this function Configuration Mechanism 1 uses an address regis
280. ress x1001 This register in conjunction with the LM SIG Control Register provides a method to generate interrupts The Universe II ASIC is programmed so that this register can be accessed from the VMEbus to provide a capability to generate software interrupts to the onboard processor s from the VMEbus REG LM SIG Status Register Offset 1001 BIT SD7 SD6 SD5 SD4 SD3 SD2 SDI SDO FIELD EN EN EN EN SIGI SIGO LMO SIGI SIGO LMO OPER R W READ ONLY RESET 0 0 0 0 0 0 0 0 EN SIG1 When the EN SIGI bit is set a LM SIG Interrupt 1 is generated if the SIGI bit is asserted SIGO When the EN SIGO bit is set a LM SIG Interrupt 0 is generated if the SIGO bit is asserted EN LM1 When the EN LMI bit is set a LM SIG Interrupt 1 is generated and the LM1 bit is asserted EN 0 When the EN LMO bit is set a LM SIG Interrupt 0 is generated and the LMO bit is asserted http www motorola com computer literature 1 29 Board Description and Memory Maps SIG1 SIGI status bit This bit can only be set by the SET LMI control bit It can only be cleared by a reset or by writing a 1 to the CLR LMI control bit SIGO SIGO status bit This bit can only be set by the SET LMO control bit It can only be cleared by a reset or by writing a 1 to the CLR LMO control bit status bit This bit can be set by either the location monitor function or the SET LMI control
281. rface 4 4 Computer Group Literature Center Web Site Functional Description The Universe II s VME Master Interface generates all of the addressing and data transfer modes documented in the VME64 specification except A64 and those intended to support 3U applications that is A40 and MD32 The Universe II is also compatible with all VMEbus modules conforming to pre VME64 specifications As VMEbus master the Universe II supports Read Modify Write RMW and Address Only with Handshake but does not accept RETRY as a termination from the VMEbus slave The ADOH cycle is used to implement the VMEbus Lock command allowing a PCI master to lock VMEbus resources PCI Bus Interface Universe II as PCI Slave Read transactions from the PCI bus are always processed as coupled Write transactions may be either coupled or posted depending upon the setting of the PCI bus slave image Refer to the section entitled Bus Slave Images in the Universe II User Manual listed in Appendix B Related Documentation With a posted write transaction write data is written to a Posted Write Transmit FIFO TXFIFO and the PCI bus master receives data acknowledgment from the Universe II with zero wait states Meanwhile the Universe II obtains the VMEbus and writes the data to the VMEbus resource independent of the initiating PCI master Refer to the section entitled Posted Writes in the Universe II User Manual for a full description
282. ridge amp Multi Processor Interrupt Controller XFBR PPC Flush Before Read If set the PHB will guarantee that all PCI initiated posted write transactions will be completed before any PPC initiated read transactions will be allowed to complete When XFBR is clear there will be no correlation between these transaction types and their order of completion Please refer to the section titled Transaction Ordering for more information XBTx PPC Bus Time out This field specifies the enabling and PPC bus time out length to be used by the PPC timer The time out length is encoded as follows MBT Time Out Length 00 256 usec 01 64 usec 10 8 usec 11 disabled P64M 64 bit PCI Mode If set the PHB is connected to a 64 bit PCI bus Refer to the section titled PHB Hardware Configuration for more information on how this bit gets set OPIC OpenPIC Interrupt Controller Enable If set the PHB detected errors will be passed on to the MPIC If cleared PHB detected errors will be passed on to the processor 0 INT pin XIDx PPC ID This field is encoded as shown below to indicate who is currently the PPC bus master This information is obtained by sampling the XARBO thru XARB3 pins when in external PPC arbitration mode When in internal PPC arbitration mode this information is generated by the PPC Arbiter In a multi processor environment these bits allow software to determine which processor it is currently running
283. rogrammed to 2 us and the counter was programmed to 12 The watchdog timers are controlled by registers mapped within the PPC control register space Each timer has a WDTxCNTL register and a WDTXxSTAT register The WDTxCNTL register can be used to start or stop the timer write a new reload value into the timer or cause the timer to initialize itself to a previously written reload value The WDTxSTAT register is used to read the instantaneous count value of the watchdog timer Programming of the Watchdog Timers is performed through the WDTXCNTL register and is a two step process Step is to arm the WDTxCNTL register by writing PATTERN 1 into the KEY field Only the KEY byte lane may be selected during this process The WDTxCNTL register will not arm itself if any of the other byte lanes are selected or the KEY field is written with any other value than PATTERN 1 The operation of the timer itself remains unaffected by this write Step 2 is to write the new programming information to the WDTXCNTL register The KEY field byte lane must be selected and must be written with PATTERN 2 for the write to take affect The effects on the WDTxCNTL register depend on the byte lanes that are written to during step 2 and are shown in the following table http www motorola com computer literature 2 43 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 14 WDTxCNTL Programming
284. rrupts IPI channels The interrupts are initiated by writing a bit in the IPI dispatch http www motorola com computer literature 2 53 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller registers If subsequent are initiated before the first is acknowledged only one IPI will be generated The IPI channels deliver interrupts in the Direct Mode and can be directed to more than one processor 8259 Compatibility The MPIC provides a mechanism to support PC AT compatible chip sets using the 8259 interrupt controller architecture After power on reset the MPIC defaults to 8259 pass through mode In this mode if the OPIC is enabled interrupts from external source number 0 the interrupt signal from the 8259 is connected to this external interrupt source on the MPIC are passed directly to processor 0 If the pass through mode is disabled and the OPIC is enabled the 8259 interrupts are delivered using the priority and distribution mechanisms of the MPIC MPIC does not interact with the vector fetch from the 8259 interrupt controller PHB Detected Errors PHB detected errors are grouped together and sent to the interrupt logic as a singular interrupt source The interrupt delivery mode for this interrupt is distributed When the OPIC is disabled the PHB interrupt will be directly passed on to processor 0 INT pin For system implementations where the MPIC controller is not used the PHB Detected Error condition w
285. s and have to be converted to 60x clock periods for the Hawk Use the following table to convert SPD bytes 27 29 and 30 to the correct values for tras trp trcd and trc Do not actually update these bits in the Hawk at this time You will use the information from this step later Table 3 18 Deriving tras trp trcd and trc Control Bit Values from SPD Information Control Bits Parameter Parameter Expressed Possible Control Bit Values in CLK Periods 0 0 lt tRAS lt 4 0 tras 00 4 0 lt tRAS lt 5 0 tras 01 5 0 lt tRAS lt 6 0 tras 10 FEF800D 1 tRAS tRAS_CLK tRAS T 6 0 lt tRAS_CLK lt 7 0 tras 11 bits 2 3 SPD Byte 30 T CLK Period 7 0 lt Illegal tras in nanoseconds See Notes 1 2 and 9 0 0 lt tRP lt 2 0 FEF800D2 tRP tRP T 2 0 tRP 3 1 bit 3 SPD Byte 27 T CLK Period 3 lt tRP CLK Illegal trp in nanoseconds See Notes 3 4 and 9 3 78 Computer Group Literature Center Web Site Software Considerations Table 3 18 Deriving tras trp trcd and trc Control Bit Values from SPD Information Continued Control Bits Parameter Parameter Expressed Possible Control Bit Values in CLK Periods 0 0 lt lt 2 trcd 0 FEF800D2 tRCD tRCD tRCD T 20 lt tRCD lt 3 tred 1 bit 7 SPD By
286. s each at 66 67 MHz Uses 8 10 or PC100 SDRAMs Programmable base address for each block Built in Refresh Scrub 3 1 System Memory Controller SMC Error Notification for SDRAM Software programmable Interrupt on Single Double Bit Error Error address and Syndrome Log Registers for Error Logging Does not provide TEA_ on Double Bit Error Chip has no TEA_ pin ROM Flash Interface Two blocks with each block being 16 or 64 bits wide Programmable access time on a per block basis I2C master interface External status control register support Block Diagrams Figure 3 1 depicts a Hawk as it would be connected with SDRAMs in a system Figure 3 2 shows the SMC s internal data paths Figure 3 3 shows the overall SDRAM connections Figure 3 4 shows a block diagram of the SMC portion of the Hawk ASIC 3 2 Computer Group Literature Center Web Site Block Diagrams Data Parity 8 815 PowerPC 60x Bus PowerPC Address Parity 4 bits Figure 3 1 Hawk Used with Synchronous DRAM in a System http www motorola com computer literature 3 3 System Memory Controller SMC Egee SDRAM Si Egee Side Latched D 64 Bits 64 Bits T Q N 8 Bits X ols lt 9c o 8 Bits eo d Uncorrected Data 64 Bits e lt 0 7 4 Figure 3 2 Hawk s System Memory Controller Interna
287. s have been verified the information is subject to change without notice B 1 Related Documentation Table B 2 Manufacturers Documents Document Title and Source Publication Number LS PowerPC 750 RISC Microprocessor Technical Summary MPC750 D Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com PowerPC 750 RISC Microprocessor User s Manual MPC750UM AD Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail Idcformotorola 9 hibbertco com OR IBM Microelectronics Mail Stop A25 862 1 MPR750UMU 01 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 800 769 3772 FAX 1 800 POWERfax FAX 1 800 769 3732 B 2 Computer Group Literature Center Web Site Manufacturers Documents Table B 2 Manufacturers Documents Continued Document Title and Source Publication Number PowerPC Microprocessor Family The Programming Environments MPCFPE AD Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail ldcformotorola hibbertco com OR IBM Microelectronics Mail Stop A25 862 1 MPRPPCFPE 01 PowerPC Marketing 1000 River Street Essex Junction Vermont 05452 4299 Telephone 1 800 PowerPC Telephone 1 8
288. s is not acceptable the interrupt controller 2 64 Computer Group Literature Center Web Site Registers architecture should recommend that if the task priority register is not implemented with the processor the task priority register should only be updated when the processor enters or exits an idle state Only when the task priority register is integrated within the processor such that it can be accessed as quickly as the MSRee bit for example should the architecture require the task priority register be updated synchronously with instruction execution Effects of Interrupt Serialization external interrupt sources that are level sensitive must be negated at least N PCI clocks prior to doing an EOI cycle for that interrupt source where N is equal to the number of PCI clocks necessary to scan in the external interrupts In the example shown 16 external interrupts are scanned in N 16 Serializing the external interrupts cause s a delay between the time that the external interrupt source changes level and when MPIC logic actually see s the change Spurious interrupts can result if an cycle occurs before the interrupt source is seen to be negated by MPIC logic Registers This section provides a detailed description of all PHB registers The section is divided into two parts the first covers the PPC Registers and the second part covers the PCI Configuration Registers The PPC Registers are accessible only from t
289. sed to verify the integrity of the VPD content The size field contains the total number of bytes assigned to the VPD portion of the SROM Each packet begins with a unique identifier field that defines the content and data structure of the packet s data section The data length field contains the size of the data section in bytes This is also added to the data section base address to locate the starting address of the following VPD packet Different data section lengths are sometimes used to denote different revision levels or array sizes for packets of a particular identifier Packets must be contiguous but may be placed in any order The termination packet identifier marks the end of the VPD and must immediately follow the last valid packet Common VPD packets include assigned ethernet address board serial number processor internal external clock frequency processor identifier connector population and other packets Customers may add additional data packets which are assigned to the user range of packet identifiers and adhere to this specification Although the addition of user packets is discouraged one potential user packet application is the specification of customer installed hardware modules Additional information on VPD Data Definitions Product Configuration Options FLASH Memory Configuration Data L2 Cache Configuration Data and an Example of VPD SROM data can be found in Appendix A MVME2400 VPD Reference Information
290. ses the int bit to be set if it is not already When the int bit is set the Hawk s internal SMC INT signal to the MPIC is asserted http www motorola com computer literature 3 47 System Memory Controller SMC AN dpien When dpien is set the logging of a PPC60x data parity error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal SMC_INT signal to the MPIC is asserted sien When sien is set the logging of a single bit error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal SMC_INT signal to the MPIC is asserted mien When mien is set the logging of a non correctable error causes the int bit to be set if it is not already When the int bit is set the Hawk s internal SMC_INT signal to the MPIC is asserted int int is set when one of the SMC s interrupt conditions occurs It is cleared by reset or by software writing a one to it The Hawk s internal SMC_INT signal tracks int When int is set SMC_INT is asserted When int is cleared SMC_INT is negated mbe_me When mbe_me is set the detection of a multiple bit error during a PowerPC read or write to SDRAM causes the SMC to pulse its machine check interrupt request MCHKO true When mbe me is cleared the SMC does not assert its MCHKO pin on multiple bit errors Note SMC never asserts its MCHKO pin in response to multiple bit error detected during a scrub
291. set to 1 MPIC blocks interrupts from sources with equal or lower priority until an End of Interrupt is received for that interrupt source Interrupts from higher priority interrupt sources continue to be enabled If the interrupt source was the 8259 the interrupt handler issues an EOI request to the MPIC This resets the In Service bit for the 8259 within the MPIC and allows it to recognize higher priority interrupt requests if any from http www motorola com computer literature 2 61 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller the 8259 If none of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 device driver interrupt service routine associated with this interrupt vector is invoked Ifthe interrupt source was not the 8259 the interrupt handler issues an EOI request for this interrupt vector to the MPIC If the interrupt source was the 8259 and any of the nested interrupt modes of the 8259 are enabled the interrupt handler issues an EOI request to the 8259 Normally interrupts from ISA devices are connected to the 8259 interrupt controller ISA devices typically rely on the 8259 Interrupt Acknowledge to flush buffers between the ISA device and system memory If interrupts from ISA devices are directly connected to the MPIC bypassing the 8259 the device driver interrupt service routine must read status from the ISA device to ensure b
292. ssor 0 The interrupt is pointed to processor 0 PHB Detected Errors Vector Priority Register Offset 10200 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 I1 1 1 1 1 1 1 1 1 O 9 8 7 6 5 4 3 2 0 9 8 7 6 5 4 3 2 1 O of 8 76 54 32 10 Name PHB DETECTED ERRORS VECTOR PRIORITY gt PRIOR VECTOR 3 2 wI R mu m R W R R W z Reset gt 000 0 00 00 2 118 Computer Group Literature Center Web Site Registers MASK Mask Setting this bit disables any further interrupts from this source If the mask bit is cleared while the bit associated with this interrupt is set in the IPR the interrupt request will be generated ACT Activity The activity bit indicates that an interrupt has been requested or that it is in service The ACT bit is set to a one when its associated bit in the Interrupt Pending Register or In Service Register is set SENSE Sense This bit sets the sense for the internal PHB detected error interrupts It is hardwired to 1 to enable active low level sensitive interrupts PRIOR Priority Interrupt priority 0 is the lowest and 15 is the highest Note that a priority level of 0 will not enable interrupts VECTOR Vectory This vector is returned when the Interrupt Acknowledge register is examined upon acknowledgment of the interrup
293. st logging of a PPC60x data bus parity error by the Hawk It is updated only when dpelog goes from 0 to 1 3 60 Computer Group Literature Center Web Site Programming Model Data Parity Error Lower Data Register Address FEF80080 2 ERR RR DPE DL Operation READ ONLY Reset 0PL DPE DL DPE DL is the value on the lower half of the PPC60x data bus at the time of the last logging of a PPC60x data bus parity error by the Hawk It is updated only when dpelog goes from 0 to 1 I2C Clock Prescaler Register Address FEF80090 Bit ol alalenlslul ele cola SPS SPS an t a E a me aem eme Name I2 PRESCALE VAL Operation READ ZERO READ ZERO READ WRITE Reset X X 01F3 P D PRESCALE VAL I2 PRESCALE VAL is a 16 bit register value that will be used in the following formula for calculating frequency of the PC gated clock signal PC CLOCK SYSTEM CLOCK I2_PRESCALE_VAL 1 2 After power up I2 PRESCALE VAL is initialized to 1F3 which produces a 100KHz PC gated clock signal based 100 0 2 system clock Writes to this register will be restricted to 4 bytes only http www motorola com computer literature System Memory Controlle
294. t 00 00 0 00 00 Perspective from the PPC bus in Little Endian mode Offset CFC CFD CFE CFF Bit DL 1 1 1 1 1 1 11 1 1 2 2 2 2 2 2 2 2 2 2 3 3 012345678901 3 4 5 6 7 8 9 OF 1 2 3 4 5 6 78 90 1 Name CONFIG_ADDRESS BUS DEV FUN REG Operation R R W R W R W R W uu Reset 00 00 00 0 00 oo http www motorola com computer literature 2 101 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller The register fields are defined as follows REG Register Number Configuration Cycles Identifies a target double word within a target s configuration space This field is copied to the PCI AD bus during the address phase of a Configuration cycle Special Cycles This field must be written with all zeros FUN Function Number Configuration Cycles Identifies a function number within a target s configuration space This field is copied to the PCI AD bus during the address phase of a Configuration cycle Special Cycles This field must be written with all ones DEV Device Number Configuration Cycles Identifies a target s physical PCI device number Refer to the section on Generating PCI Cycles for a description of how this field is encoded Special Cycles This field must be written with all ones BUS Bus Number Configuration Cycles Identifies a targeted bus number If written with all zeros a Type 0 Configuration Cycle will be generated If written with any value o
295. t 3 34 General Control Register 3 40 I2C Transmitter Data Register 3 64 L2 cache support 3 14 refresh scrub 3 34 ROM A Base Size Register 3 53 ROM B Base Size Register 3 56 ROM Speed Attributes Register 3 58 ROM Flash initialization 5 15 ROM Flash Interface 3 17 Scrub Refresh Register 3 51 SDRAM Base Address Register 3 43 3 66 SDRAM Enable and Size Register 3 41 3 65 SDRAM Speed Attributes Register 3 68 Vendor Device Register 3 39 SMC Data Parity Error Address Register 3 60 SMC Data Parity Error Log Register 3 59 SMC Data Parity Error Lower Data Register 3 61 SMC External Register Set 3 72 SMC 12 Clock Prescaler Register 3 61 SMC 12 Control Register 3 62 SMC DC Receiver Data Register 3 65 SMC DC Status Register 3 63 SMC Scrub Address Register 3 52 SMC tben Register 3 73 soft reset MPIC 5 8 software considerations 3 74 software readable switch settings 1 26 sources of reset MVME2400 5 7 SPD 3 76 specifications IN 10 Computer Group Literature Center Web Site related 4 specifications related 4 Speculative PCI Request 2 47 spread I O addressing as function of PHB 2 31 Spurious Vector Register 2 112 SRAM base address 3 35 status bit descriptions 3 38 status bit definition x swen 3 51 switch 53 1 26 switches software readable 1 26 syndrome codes ordered by bit in error 3 86 System Configuration Information 1 23 T TA as used with PPC Slave 2 7 Table 2 10 Table 2 2 2 10 target initiated termi
296. t associated with this vector PHB Detected Errors Destination Register Offset 10210 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 I 1 1 1 H 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1098756254232 10 Name PHB DETECTED ERROR DESTINATION Ur c Operation R R R R Reset 00 00 00 00 co This register indicates the possible destinations for the PHB detected error interrupt source These interrupts operate in the Distributed interrupt delivery mode P1 Processor 1 The interrupt is pointed to processor 1 PO Processor 0 The interrupt is pointed to processor 0 http www motorola com computer literature 2 119 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Interprocessor Interrupt Dispatch Registers Offset Processor 0 20040 20050 20060 20070 Processor 1 21040 21050 21060 21070 Bit 3 3 2 2 2 2 2 2 2 2 222 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 21 1 OF of gt 76 5 4 3 21 10 Name IPI DISPATCH v UU S Operation R R R R Z 5 Reset 00 00 00 00 ojo There are four Interprocessor Interrupt Dispatch Registers Writing to an IPI Dispatch Register with the PO and or P1 bit set
297. t handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its Warning components To prevent serious injury or death from dangerous voltages use extreme Flammability Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Caution Attention Vorsicht Danger of explosion
298. t is used to initiate a single PCI Interrupt Acknowledge cycle Any single byte or combination of bytes may be read from and the actual byte enable pattern used during the read will be passed on to the PCI bus Upon completion of the PCI interrupt acknowledge cycle the PHB will present the resulting vector information obtained from the PCI bus as read data http www motorola com computer literature 2 83 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Address FEFF0030 Bit 1 1 1 1 1 1 1 11 1 112 2 2 2 2 2 2 2 2 2 3 3 ol 1 2 3 41 5167 8 9 OF 1 2 3 4 5 6 7 8 9 O 1 2 3 4 5 6 7 8 9 OF 1 Name PIACK Operation Reset 00000000 PPC Slave Address 0 1 and 2 Registers The PPC Slave Address Registers XSADDO XSADDI and XSADD2 contains address information associated with the mapping of PPC memory space to PCI memory io space The fields within the XSADDx registers are defined as follows Address XSADDO FEFF0040 XSADDI FEFF0048 XSADD2 FEFF0050 Bit gt DS ce xe EY col S Ni OY o oo 9 A NENT AT 0 01 0100 XSADDx START END Operatio
299. t must be supported since it is conceivable that bursting could happen For example nothing prevents the processor from loading up a cache line with PCI write data and manually flushing the cache line The following paragraphs identify some associations between the operation of the PCI Master and the PCI 2 1 Local Bus Specification requirements Command Types The PCI Command Codes generated by the PCI Master depend on the type of transaction being performed on the PPC bus Please refer to the section on the PPC Slave earlier in this chapter for a further description of PPC bus read and PPC bus write The following table summarizes the command types supported and how they are generated Table 2 8 PCI Master Command Codes Entity Addressed PPC TBST C BE PCI Command Transfer Type PIACK Read 0000 Interrupt Acknowledge CONADD CONDAT Write X 0001 Special Cycle PPC Mapped PCI Read 0010 T O Read 5 Write x 0011 Write Unsupported 0100 Reserved Unsupported 0101 Reserved PPC Mapped PCI Read 1 1 0110 Memory Read Space Write 1 0111 Memory Write http www motorola com computer literature 2 27 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Table 2 8 PCI Master Command Codes Continued Entity Addressed PPC TBST MEM C BE PCI Command Transfer Type Unsupported 100
300. t the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition Note In some places in this document an underscore following the signal name is used to indicate an active low signal xxiii this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes for MPC60x chips are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant a A half word is 16 bits numbered 0 through 15 with bit 0 being the least significant A word or single word is 32 bits numbered 0 through 31 with bit 0 being the least significant A double word is 64 bits numbered 0 through 63 with bit 0 being the least significant Refer to Chapter 5 Programming Details for Endian Issues which covers which parts of the MVME2400 series use big endian byte ordering and which use small endian byte ordering The terms control bit and status bit are used extensively in this document The term control bit is used to describe a bit in a register that can be s
301. te When the width status bit is set the block s ROM Flash is considered to be 64 bits wide where each half of the SMC interfaces with 32 bits In this mode the following rules are enforced c only aligned 4 byte writes should be attempted all other sizes are ignored and d all reads are allowed multiple accesses to the ROM Flash device are performed for burst reads More information about ROM Flash is found in the section entitled External Register Set in this chapter 3 18 Computer Group Literature Center Web Site Functional Description In order to place code correctly in the ROM Flash devices address mapping information is required Table 3 7 shows how PPC60x addresses map to the ROM Flash addresses when ROM Flash is 16 bits wide Table 3 8 shows how they map when Flash is 64 bits wide Table 3 7 PPC60x to ROM Flash 16 Bit Width Address Mapping PPC60x A0 A31 ROM Flash A22 A0 ROM Flash Device Selected XX000000 000000 Upper XX000001 000001 Upper XX000002 000002 Upper XX000003 000003 Upper XX000004 000000 Lower XX000005 000001 Lower XX000006 000002 Lower XX000007 000003 Lower XX000008 000004 Upper XX000009 000005 Upper XX00000A 000006 Upper XX00000B 000007 Upper XX00000C 000004 Lower XX00000D 000005 Lower XX00000E 000006 Lower XX00000F 000007 Lower XXFFFFF8 7FFFFC Upper XXFFFFF9 7FFFFD
302. te 29 T CLK Period 3 lt tRCD CLK Illegal trcd in nanoseconds See Notes 5 6 and 9 0 0 lt tRC_CLK lt 6 0 trc 110 6 0 lt lt 7 0 trc 111 7 0 lt lt 8 0 trc 000 8 0 lt tRC_CLK lt 9 0 tre 001 FEF800D0 tRC SIRE 0 bits 5 6 7 SPD Bytes 30 tRPyT 10 0 tRC_CLK lt trc 011 trc and 27 T CLK Period 110 in nanoseconds 11 0 lt tRC illegal See Notes 7 8 and 9 Notes 1 Use tRAS from the SDRAM block that has the slowest tRAS A QN A W NY tRAS is tRAS expressed in CLK periods tRP CLK is tRP expressed in CLK periods tRCD CLK is tRCD expressed in CLK periods tRC_CLK is tRC expressed in CLK periods Use tRP from the SDRAM block that has the slowest tRP Use tRCD from the SDRAM block that has the slowest tRCD Use tRC from the SDRAM block that has the slowest tRC http www motorola com computer literature System Memory Controller SMC 9 Determine the size for each block that is present Do not actually program the Hawk s size bits at this point You use this information to program them later Each block s size can be determined using the following algorithm a Calculate the number of rows in each device using SPD byte 3 If the number of rows is ROWS and the value in SPD byte 3 is R then ROWS 2F Calculate the number of columns in each device using SPD byte 4 If the number
303. tecting an interrupt qualified error condition The potential sources of SMC INT assertion are single bit error multiple bit error and single bit error counter overflow The SMC INT signal is internally connected to the MPIC Error Logging ECC error logging is facilitated by the SMC because of its internal latches When an error single or double bit occurs the SMC records the address and syndrome bits associated with the data in error Once the error logger has logged an error it does not log any more until the elog control status bit has been cleared by software unless the currently logged error is single bit and a new double bit error is encountered The logging of errors that occur during scrub can be enabled disabled in software Refer to the Error Logger Register section in this chapter ROM Flash Interface The SMC provides the interface for two blocks of ROM Flash Each block provides addressing and control for up to 64Mbytes Note that no ECC error checking is provided for the ROM Flash The ROM Flash interface allows each block to be individually configured by jumpers and or by software as follows 1 Access for each block is controlled by three software programmable control register bits an overall enable a write enable and a reset vector enable The overall enable controls normal read accesses The write enable is used to program Flash devices The reset vector enable controls whether the block is also enabled at FFF
304. tempt by a non locking master to access any PCI resource represented by the PHB results in the PCI Slave issuing a retry Parity The PCI Slave supports address parity error detection data parity generation and data parity error detection http www motorola com computer literature 2 25 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller PCI FIFO PCI Master Cache Support The PCI Slave does not participate in the PCI caching protocol 64 bit by 16 entry FIFO 4 cache lines total is used to hold data between the PCI Slave and the PPC Master to ensure that optimum data throughput is maintained The same FIFO is used for both read and write transactions A 52 bit by 4 entry FIFO is used to hold command information being passed between the PCI Slave and the PPC Master If write posting is enabled then the maximum number of transactions that may be posted is limited by the abilities of either the data FIFO or the command FIFO For example one burst transaction 16 dwords long would make the data FIFO the limiting factor for write posting Four single beat transactions would make the command FIFO be the limiting factor If either limit is exceeded then any pending PCI transactions are delayed TRDY is not asserted until the PPC Master has completed a portion of the previously posted transactions and created some room within the command and or data FIFOs The PCI Master in conjunction with the capabilities of t
305. tep 5 for this Only those blocks that exist should be enabled Also only those that exist should be programmed with a non zero size 13 Wait for at least one SDRAM refresh to complete A simple way to do this is to wait for the 32 bit counter to increment at least 100 times refer to the section on the 32 Bit Counter for more information Note that the refdis control bit must not be set in the ECC Control Register 14 SDRAM is now ready to use Optional Method for Sizing SDRAM Generally SDRAM block sizes can be determined by using SPD information refer to the previous section on SDRAM Control Registers Initialization Example Another method for accomplishing this is as follows 1 Initialize the SMC s control register bits to a known state Computer Group Literature Center Web Site Software Considerations a Clear the isa hole bit refer to the section titled Vendor Device Register for more information b Make sure the CLK Frequency Register matches the operating frequency c Wait for at least one SDRAM refresh to complete A simple way to do this is to wait for the 32 bit counter to increment at least 100 times refer to the section on 32 Bit Counter for more information Note that the refdis control bit must not be set in the ECC Control Register d Make sure that the SDRAM Speed Attributes Register contains its power up reset values If not make sure that the values match the actual characteristics of t
306. ter Set is ROM Flash Block C The differences between Blocks A B and C are that the following parameters are fixed rather than programmable for Block 1 The device speed for Block C is fixed at 11 Clocks 2 The width for Block C is fixed at 64 bits 3 The address range for Block C is fixed at FEF88000 FEFSFFF8 FEF98000 FEF9FFF8 when Hawk is configured for the alternate CSR base address 3 72 Computer Group Literature Center Web Site Programming Model 4 Block C is never used for reset vectors 5 Block C is always enabled unless the tben en bit is set 6 Writes to Block C cannot be disabled Note The fact that the assumed width is 64 bits does not require that all 64 bits have to be used The system designer can connect the needed width device to the bits desired for the application Devices less than 64 bits will cause holes for addresses corresponding to non connected bits tben Register Address FEF88300 Bit SI SI A en tf un ALO A A DYE I SE OY ER OD NY a a a a a ERI AI NIA AIA AIA AY we coe we Name da oO o 2 9 jal al Alolojojo Operation 2 READ ZERO READ ZERO READ ZERO c eA ec e Reset X X X P P lt a P lt P lt P lt P lt The tben Register is only enabled when the en bit in the Revisio
307. ter data register format Performing a configuration access is a two step process The first step is to place the address of the configuration cycle within the CONFIG ADDRESS register Note that this action does not generate any cycles on the PCI bus The second step is to either read or write configuration data into the CONFIG register If the CONFIG ADDRESS register is set up correctly the PHB will pass this access on to the PCI bus as a configuration cycle The addresses of the CONFIG ADDRESS and DATA registers are actually embedded within PCI I O space If the CONFIG ADDRESS register has been set incorrectly or the access to either the CONFIG ADDRESS or CONFIG DATA register is not 1 2 or 4 bytes wide the PHB will pass the access on to PCI as a normal I O Space transfer The CONFIG ADDRESS register is located at offset CF8 from the bottom of PCI I O space The CONFIG DATA register is located at offset CFC from the bottom of PCI I O space The PHB address decode logic has been designed such that XSADD3 and XSOFF3 must be used for mapping to PCI Configuration consequently I O space The XSADD3 XSOFF3 register group is initialized at reset to allow PCI I O access starting at address 580000000 The powerup location that is Little Endian disabled of the CONFIG_ADDRESS register is 30000CF8 and the DATA register is located at 80000CFC The ADDRESS register must be prefilled with four f
308. ter was not involved the PPC master ID cannot be determined When DFLT is set is used When DFLT is clear MCHKO_ will be used XBTOM PPC Address Bus Time out Machine Check Enable When this bitis set the XBTO bit in the ESTAT register will be used to assert the MCHK output to the current address bus master When this bit is clear MCHK will not be asserted XDPEM PC Data Parity Error Machine Check Enable When this bit is set the XDPE bit in the ESTAT register will be used to assert the MCHK output to the current address bus master When this bit is clear MCHK will not be asserted PPERM PCI Parity Error Machine Check Enable When this bit is set the PPER bit in the ESTAT register will be used to assert the MCHK output to bus master 0 When this bit is clear MCHK will not be asserted PSERM PCI System Error Machine Check Enable When this bit is set the PSER bit in the ESTAT register will be used to assert the MCHK output to bus master 0 When this bit is clear MCHK will not be asserted PSMAM PCI Signalled Master Abort Machine Check Enable When this bitis set the PSMA bit in the ESTAT register will be used to assert the MCHK output to the bus master which initiated the transaction When this bit is clear MCHK will not be asserted PRTAM PCI Master Received Target Abort Machine Check Enable When this bit is set the PRTA bit in the ESTAT register will be used to assert the MCHK output to the bus master which
309. terrupt processing to swap back and forth between processor 0 and 1 The first tie in external interrupt processing always goes to Processor after a reset When this register bit is set to 0 a tie in external interrupt processing will always go to Processor 0 Mode used on Version 02 of MPIC Table 2 21 Tie Mode Encoding T Mode 0 Processor 0 always selected 1 Swap between Processor s http www motorola com computer literature 2 109 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Vendor Identification Register Offset 01080 Bit 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 O 9 8 7 6 5 4 3 21 11 0 Name VENDOR IDENTIFICATION STP Operation R R R Reset 00 02 00 00 There are two fields in the Vendor Identification Register which are not defined for the MPIC implementation but are defined in the MPIC specification They are the vendor identification and device ID fields STP Stepping The stepping or silicon revision number is initially 0 Processor Init Register Offset 01090 Bit 3 3 2 2 2 2 2 2 2 2 2 2 1 I1 1 1 1 1 1111 1 0 9 87165 4312109876 5 4 3 2 1009876 5
310. tes 1 Interrupt from the PCI ISA Bridge 2 The mapping of interrupt sources from the VMEbus and Universe II internal interrupt sources is programmable via the Local Interrupt Map 0 Register and the Local Interrupt Map 1 Register in the Universe II ASIC 3 These interrupts also appear at the PIB for backward compatibility with older MVME1600 and PM603 4 modules 8259 Interrupts There are 15 interrupt requests supported by the PIB These 15 interrupts are ISA type interrupts that are functionally equivalent to two 82C59 interrupt controllers Except for IRQO IRQ1 IRQ2 IRQ8_ and IRQ13 each of the interrupt lines can be configured for either edge sensitive mode or level sensitive mode by programming the appropriate ELCR registers in the PIB There is also support for four PCI interrupts PIRQ3 PIRQO The PIB has four PIRQ Route Control Registers to allow each of the PCI interrupt lines to be routed to any of eleven ISA interrupt lines IRQO IRQ1 IRQ2 IRQS and 13 are reserved for ISA system interrupts Since PCI interrupts are defined as level sensitive software must program the selected IRQ s for level sensitive mode Note that more than one PCI interrupt can be routed to the same ISA IRQ line The PIB can be programmed to handle the PCI interrupts if the MPIC is either not present or not used 5 4 Computer Group Literature Center Web Site Interrupt Handling The following figure shows the interrupt structure
311. tes are allowed The SMC ignores other writes If a valid write is attempted and rom a we is cleared the write does not happen but the cycle is terminated normally See the following table for details of ROM Flash accesses Table 3 13 Read Write to ROM Flash Cycle Transfer Alignment rom x 64 rom x we Hawk Response Size write 1 byte X 0 0 Normal termination but no write to ROM Flash write 1 byte X 0 1 Normal termination write occurs to ROM Flash write 1 byte X 1 X No Response write 4 byte Misaligned X X No Response write 4 byte Aligned 0 X No Response write 4 byte Aligned 1 0 Normal termination but no write to ROM Flash write 4 byte Aligned 1 1 Normal termination write occurs to ROM Flash write 2 3 5 6 7 X X X No Response 8 32 byte read X X X X Normal Termination http www motorola com computer literature System Memory Controller SMC ROM B Base Size Register Address FEF80058 Bit 4 100 TS IS IS RI IR IG IS ISIS IRIN rt ES E 09 Name ROM B BASE 5 15 5 5 B 5 5 ccc 1 18 18 155 lt 7O Operation READ WRITE Amm mmm 55 S READ ZERO ZISIS Reset FF4 PL eee gt lt gt lt olo 91919 X uuu pp E rp Writes to this register must be en
312. th this interrupt One bit for each processor http www motorola com computer literature 2 59 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller Then one of these bits is delivered to each Interrupt Selector Since this interrupt source can be multicast each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor If one of the following sets of conditions are true the interrupt pin for processor 0 is driven active source ID in _0 is from an external source The destinaition bit for processor 1 is 0 for this interrupt The priority from IRR 0 is greater than the highest priority in ISR 0 The priority from IRR 0 is greater than the contents of task register 0 Set2 The source ID in IRR 0 is from an external source The destination bit for processor 1 is a 1 for this interrupt The source ID in IRR is not present is ISR 1 The priority from IRR 0 is greater than the highest priority in ISR 0 The priority from IRR 0 is greater than the Task Register 0 contents The contents of Task Register 0 is less than the contents of Task Register 1 Set3 The source ID in IRR 015 from an internal source The priority from IRR 0 is greater than the highest priority in ISR 0 The priority from IRR 0 is greater than the Task Register 0 contents 2 60 Computer Group Literature Center Web Site Multi Processor
313. the KEY field An incorrect sequence of patterns will cause the Control register to be in the unarmed state 2 88 Computer Group Literature Center Web Site Registers A value of all zeros will always be returned within the KEY field during read cycles ENAB ENAB This field determines whether or not the WDT is enabled If a one is written to this bit the timer will be enabled A zero written to this bit will disable the timer The ENAB bit may only be modified on the second step of a successful two step arming process ARM ARMED This read only bit indicates the armed state of the register If this bit is a zero the register is unarmed If this bit is a one the register is armed for a write RES RESOLUTION This field determines the resolution of the timer The RES field may only be modified on the second step of a successful two step arming process The following table shows the different options associated with this bit RES Timer Resolution Approximate Max Time 0000 us 64 msec 0001 2 us 128 msec 0010 4 us 256 msec 0011 8 us 512 msec 0100 16 us 1 sec 0101 32 us 2 sec 0110 64 us 4 sec 0111 128 us 8 sec 1000 256 us 16 sec 1001 512 us 32 sec 1010 1024 us min 1011 2048 us 2 min 1100 4096 us 4 min 1101 8192 us 8 min 1110 16 384 us 16 min 1111 32 768 us 32 min http www motorola com computer literature 2 89 Hawk PCI Host Bridge amp Multi Processor
314. ther than all zeros then a Type 1 Configuration Cycle will be generated Special Cycles Identifies a targeted bus number If written with all Zeros a Special Cycle will be generated If written with any value other than all zeros then a Special Cycle translated into a Type 1 Configuration Cycle will be generated EN Enable Configuration Cycles Writing a one to this bit enables CONFIG DATA to Configuration Cycle translation If this bit is a Zero subsequent accesses to DATA will be passed though as I O Cycles Special Cycles Writing a one to this bit enables DATA to Special Cycle translation If this bit is a zero subsequent accesses to CONFIG DATA will be passed though as I O Cycles 2 102 Computer Group Literature Center Web Site Registers CONFIG DATA Register The description of the DATA register is also presented in three perspectives from the PCI bus from the PPC Bus in Big Endian mode and from the PPC bus in Little Endian mode Note that the view from the PCI bus is purely conceptual since there is no way to access the CONFIG DATA register from the PCI bus Conceptual perspective from the PCI bus Offset CFF CFE CFD CFC Bit 3 3 2 2 2 2 2 2 2 2 2 2
315. tion Architectural Overview A functional block diagram of the Hawk s PHB is shown in Figure 2 1 The PHB control logic is subdivided into the following functions PCI slave PCI master PPC slave and PPC master The PHB data path logic is subdivided into the following functions PCI FIFO PPC FIFO PCI Input PPC Input PCI Output and PPC Output Address decoding is handled in the PCI Decode and PPC Decode blocks The control register logic is contained in the PCI Registers and PPC Registers blocks The clock phasing and reset control logic is contained within the PPC PCI Clock block The FIFO structure implemented within PHB has been selected to allow independent data transfer operations to occur between PCI bound transactions and PPC bound transactions The PCI FIFO is used to support PPC bound transactions while the PPC FIFO is used to support PCI bound transactions Each FIFO supports a command path and a data path The data path portion of each FIFO incorporates a multiplexer to allow selection between write data and read data as well as logic to handle the PPC PCI endian function All PPC originated PCI bound transactions utilize the PPC Slave and PCI Master functions for maintaining bus tracking and control During both write and read transactions the PPC Slave will place command information into the PPC FIFO The PCI Master will draw this command information from the PPC FIFO when it is ready to process the transaction During writ
316. tion mode is made by sampling an RD line at the release of reset Please see the section titled PHB Hardware Configuration on page 2 49 for more information PHB has been designed to accommodate up to four PPC60x bus masters including itself HAWK two processors CPUO CPUI1 and an external 60 master EXTL EXTL can be an L2 cache a second bridge chip etc When the PPC Arbiter is disabled PHB will generate an external request and listen for an external grant for itself It will also listen to the other external grants to determine the PPC60x master identification field XID within the GCSR When the PPC Arbiter is enabled PHB will receive requests and issue grants for itself and for the other three bus masters The XID field will be determined by the PPC Arbiter The PPC60x arbitration signals and their functions are summarized in the following table Table 2 6 PPC Arbiter Pin Assignments Pin Name Reset Internal Arbiter Pin Type XARBO BiDir Tristate External Arbiter Direction Output Function CPUO Grant Direction Input Function CPUO Grant XARBI BiDir Tristate Output CPUI Grant Input CPUI Grant XARB2 BiDir Tristate Output EXTL Grant Input EXTL Grant XARB3 BiDir Tristate Input CPUO Request Output HAWK Request XARB4 Input Input CPUI Request_ Input HAWK Grant_ 5 Input
317. to a Posted Write Receive FIFO RXFIFO and the VMEbus master receives data acknowledgment from the Universe II Write data is transferred to the PCI resource from the RXFIFO without the involvement of the initiating VMEbus master Refer to the section entitled Posted Writes in the Universe User Manual for a full explanation of this operation With a coupled cycle the VMEbus master only receives data acknowledgment when the transaction is complete on the PCI bus This means that the VMEbus is unavailable to other masters while the PCI bus transaction is executed Read transactions may be prefetched or coupled If enabled by the user a prefetched read is initiated when a VMEbus master requests a block read transaction BLT or MBLT and this mode is enabled When the Universe II receives the block read request it begins to fill its Read Data FIFO RDFIFO using burst transactions from the PCI resource The initiating VMEbus master then acquires its block read data from the RDFIFO rather than from the PCI resources directly Universe II as VMEbus Master The Universe becomes VMEbus master when the VME Master Interface is internally requested by the PCI Bus Slave Channel the DMA Channel or the Interrupt Channel The Interrupt Channel always has priority over the other two channels Several mechanisms are available to configure the relative priority that the PCI Bus Slave Channel and DMA Channel have over ownership of the VMEbus Master Inte
318. to another bus domain The PHB will assert this signal whenever it has determined that a transaction is being timed by its own PCI bus Any other bridge devices listening to this signal will understand that the current pending cycle should not be subject to a time out period During non PCI bound cycles PPC Timer will abort the timing of the transaction any time it detects XBTCLM has been assertedPCI Interface 2 18 Computer Group Literature Center Web Site Functional Description PCI Bus Interface The PCI Interface of the PHB is designed to connect directly to a PCI Local Bus and supports Master and Target transactions within Memory Space I O Space and Configuration Space PCI Address Mapping The PHB provides three resources to the PCI Configuration registers mapped into PCI Configuration space bus address space mapped into PCI Memory space MPIC control registers mapped into either PCI I O space or PCI Memory space Configuration Registers The PHB Configuration registers are mapped within PCI Configuration space according to how the system connects Hawk s DEVSEL pin PHB provides a configuration space that is fully compliant with the PCI Local Bus Specification 2 1 definition for configuration space There are two base registers within the standard 64 byte header that are used to control the mapping of MPIC One register is dedicated to mapping MPIC into PCI I O space and the other register is dedicate
319. torola com computer literature 4 7 Universe II VMEbus to PCI Chip Registers Universe Control and Status Registers UCSR The Universe II Control and Status Registers UCSR facilitate host system configuration and allow the user to control Universe II operational characteristics The UCSRs are divided into three groups PCI Configuration Space PCICS VMEbus Control and Status Registers VCSR and Universe II Device Specific Status Registers UDSR The Universe II registers are little endian The figure below summarizes the supported register access mechanisms VMEbus Configuration and Status Registers VCSR Universe DEVICE SPECIFIC REGISTERS UDSR PCI CONFIGURATION SPACE PCICS I A4Kbytes 1895 9609 Figure 4 2 UCSR Access Mechanisms 4 8 Computer Group Literature Center Web Site Registers Universe II Control and Status Registers UCSR Universe Register Map Table 4 1 below lists the Universe II registers by address offset Tables in the Universe II User Manual listed in Appendix B Related Documentation provide detailed descriptions of each register Address offsets in Table 4 1 below apply to accesses from the PCI bus and to accesses from the VMEbus side using the VMEbus Register Access Image refer to the section entitled Registers in the Universe II User Manual listed in Appendix B Related Documentation For register accesses
320. trol the use of an external 8259 pair for PC AT compatibility Following reset this mode is set for pass through which essentially disables the advanced controller and passes an 8259 input on external interrupt source 0 directly through to processor zero During interrupt controller initialization this channel should be programmed for mixed mode in order to take advantage of the interrupt delivery modes Current Task Priority Level Each processor has a separate Current Task Priority Level register The system software uses this register to indicate the relative priority of the task running on the corresponding processor The interrupt controller will not deliver an interrupt to a processor unless it has a priority level which is greater than the current task priority level of that processor This value is also used in determining the destination for interrupts which are delivered using the distributed deliver mode Architectural Notes The hardware and software overhead required to update the task priority register synchronously with instruction execution may far outweigh the anticipated benefits of the task priority register To minimize this overhead the interrupt controller architecture should allow the task priority register to be updated asynchronously with respect to instruction execution Lower priority interrupts may continue to occur for an indeterminate number of cycles after the processor has updated the task priority register If thi
321. tting filled A similar case exists with regards to PCI read cycles Having the bridge lock resolution associated with a particular PCI FIFO threshold would allow the PPC Master to get an early enough start at prefetching read data to keep the PCI Slave from starving for read data From the perspective of the PPC bus a selective FIFO threshold will make the PPC Slave release the PPC bus at an earlier time thereby reducing wasted PPC bus bandwidth PHB offers an option to have the PPC Slave remove a stalled transaction immediately upon detecting any PCI Slave activity This option would help in the case where distributing PPC60x bus bandwidth between multiple masters is of utmost importance The PHB is tuned to provide the most efficient solution for bridge lock resolution under normal operating conditions If further fine tuning is desired the WLRT RLRT Write Lock Resolution Threshold Read Lock Resolution Threshold fields within the HCSR can be adjusted accordingly Note that the FIFO full option exists mainly to remain architecturally backwards compatible with previous bridge designs 2 46 Computer Group Literature Center Web Site Functional Description Speculative PCI Request There is a case where the processor could get starved for PCI read data while the PCI Slave is hosting multiple PPC60xc bound write cycles While attempting to perform a read from PCI space the processor would continually get retried as a result of bridg
322. uential read operation and must remain cleared for all other C operations For PC sequential read operation this bit should be set for every single byte received except on the last byte in which case it should be cleared i2_enbl When set the master interface will be enabled for I2C operations If clear reads and writes to all PC registers are still allowed but no C bus operations will be performed 3 62 Computer Group Literature Center Web Site 31 12 enbl Programming Model I2C Status Register Address FEF800A0 Bit SD I A en tf un ALO A A a A en tf un SP a Sa a Sa Se A A A A oe A e ee Name 8 28 8538 Operation READ ZERO READ ZERO READ ZERO 04 04 04 04 4 Reset X X X Aaa 12 datin This bit is set whenever the master controller has successfully received a byte of read data from an PC bus slave device This bit is cleared after the IC Receiver Data Register is read i2_err This bit is set when both i2_start and i2_stop bits in the Control Register are set at the same time The master controller will then clear the contents of the C Control Register and further writes to the C Control Register will not be allowed until after the PC Status Register is read A re
323. uffers between the device and system memory are flushed Reset State After power on reset the MPIC state is Current task priority for all CPUs set to 15 All interrupt source priorities set to zero a All interrupt source mask bits set to a one a All interrupt source activity bits cleared Processor Init Register is cleared counters stopped and interrupts disabled Controller mode set to 8259 pass through 2 62 Computer Group Literature Center Web Site Multi Processor Interrupt Controller MPIC Functional Description Operation Interprocessor Interrupts Four Inter Processor Interrupt IPI channels are provided for use by all processors During system initialization the IPI vector priority registers for each channel should be programmed to set the priority and vector returned for each IPI event During system operation a processor may generate an IPI by writing a destination mask to one of the IPI dispatch registers Note that each IPI dispatch register is shared by both processors Each IPI dispatch register has two addresses but they are shared by both processors That is there is a total of four IPI dispatch registers in the MPIC The IPI mechanism may be used for self interrupts by programming the dispatch register with the bit mask for the originating processor Dynamically Changing Interrupt Configuration EOI Register The interrupt controller provides a mechanism for safely chan
324. up Literature Center Web Site Programming Model Table 1 7 PCI CHRP Memory Map Continued PCI Address Size Definition Notes Start End 00 0000 FC03 FFFF 256K MPIC 1 FC04 0000 16 256 PCI Memory Space FD00 0000 FDFF FFFF 16M PCI Memory Space or 1 System Memory Alias Space mapped to 00000000 to 00FFFFFF FE00 0000 FFFF FFFF 48M Reserved Notes 1 Programmable via the PHB s PCI Configuration registers For the MVME2400 series RAM size is limited to 256MB 2 To enable the CHRP io hole program the PHB to ignore the 0x000A0000 0x000FFFFF address range 3 Programmable mapping via the four PCI Slave Images in the Universe II ASIC 4 Programmable mapping via the Special Slave Image SLSI in the Universe II ASIC The following table shows the programmed values for the associated PHB PCI registers for the PCI CHRP memory map Table 1 8 PHB PCI Register Values for CHRP Memory Map Configuration Configuration Register Value Register Value Address Offset Register Name Aliasing OFF Aliasing ON 14 MPIC MBASE 00 0000 FC00 0000 80 PSADDO 0000 3FFF 0100 3FFF 84 amp PSATTO 0000 00FX 0000 00FX 88 PSADDI 0000 0000 FD00 FDFF http www motorola com computer literature 1 13 Board Description and Memory Maps Table 1 8 PHB PCI Register Values for CHRP Memory Map Continued Confi
325. upplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in subparagraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Manual Summary of CHANGES M Vii EEE IO Ol CAME BING WU m t o EET Comments and Suggesllofls oreet eee pap Feb O REDE FLU Uber WEE GENRE viii Nannal Termino RE ku pa RE IOS AURA PALM Gag RON UR A aa aps ix Conventions Used in This MEBEURI uris tiae e ebat qe ba roD UH e EE UK xi CHAPTER 1 Board Description and Memory Maps n cis eS 1 1 c E 1 1 SLE 1 2 2s EUER EDI 1 3 1 5 B ral E 1 5 Programming Model RT 1 6 Hir T 1 6 Processor Memory Maps uesa E RERUM
326. upt 0 can be either level or edge activated with either polarity The PHB interrupt request is an active low level sensitive interrupt The Interprocessor and timers interrupts are event activated If the OPIC is enabled the PHB detected errors will be passed on to MPIC If the OPIC is disabled PHB detected errors are passed directly to the processor 0 interrupt pin External Interrupt Interface The external interrupt interface functions as either a parallel or a serial interface depending on the EINTT bit in the MPIC Global Configuration Register If this bit is set MPIC is in the serial mode Otherwise MPIC operates in the parallel mode In the serial mode all 16 external interrupts are serially scanned into MPIC using the SI STA and SI DAT pins as shown in Figure 2 8 In the parallel mode 16 external signal pins are used as interrupt inputs interrupts 0 through 15 http www motorola com computer literature 2 51 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller ea AEN APP SI STA r E i SI DAT exu emen zem em jer Earliest possible assertion of SI STA jJ Figure 2 8 Serial Mode Interrupt Scan Using PCLK as a reference external logic will pulse 51 STA one clock period indicating the beginning of an interrupt scan period On the same clock period that SI STA is asserted external logic will feed the state of EXTO on the SI DAT pin External logic will continue to sequenti
327. urst transactions would make the data FIFO the limiting factor for write posting Four single beat transactions would make the command FIFO be the limiting factor If either limit is exceeded then any pending PPC transactions will be delayed and TA will not be asserted until the PCI Master has completed a portion of the previously posted transactions and created some room within the command and or data FIFOs The PHB does not support byte merging or byte collapsing Each and every single beat transaction presented to the PPC Slave will be presented to the PCI bus as a unique single beat transfer The PPC Master can transfer data either in 1 to 8 byte single beat transactions or 32 byte four beat burst transactions This limitation is strictly imposed by the PPC60x bus protocol The PPC Master will attempt to move data using burst transfers whenever possible If a transaction starts on a non cache line address the PPC Master will perform as many single beat transactions as needed until the next highest cache line boundary is reached If a write transaction ends on a non cache line boundary then the PPC Master will finish the transaction with as many single beat transactions as needed to complete the transaction Table 2 2 shows the relationship between starting addresses and 60 bus transaction types when write posting and read ahead are enabled Computer Group Literature Center Web Site Functional Description Table 2
328. us interrupt output pins VIRQ 7 1 When a software and hardware source are assigned the same VIRQn pin the software source always has higher priority Interrupt sources mapped to PCI bus interrupts are generated on one of the INT 7 0 pins To be fully PCI compliant all interrupt sources must be routed to a single INT pin For VMEbus interrupt outputs the Universe II interrupter supplies an 8 bit STATUS ID to a VMEbus interrupt handler during the IACK cycle and optionally generates an internal interrupt to signal that the interrupt vector has been provided Refer to the section entitled VMEbus Interrupt Generation in the Universe II User Manual listed in Appendix B Related Documentation Interrupts mapped to PCI bus outputs are serviced by the PCI interrupt controller The CPU determines which interrupt sources are active by reading an interrupt status register in the Universe II The source negates its interrupt when it has been serviced by the CPU Refer to the section entitled PCI Interrupt Generation in the Universe User Manual 4 6 Computer Group Literature Center Web Site Functional Description VMEbus Interrupt Handling A VMEbus interrupt triggers the Universe io generate a normal VMEbus IACK cycle and generate the specified interrupt output When the IACK cycle is complete the Universe II releases the VMEbus and the interrupt vector is read by the PCI resource servicing the interrupt output Software i
329. variable format data structure that contains static board configuration feature information based on your particular board build options This is a new approach to housing specific baseboard mezzanine and I O transition module local hardware configuration information and will be used as a standard information storage mechanism for future MCG products The serial EEPROM can be viewed as two separate and distinct 256 byte SROMS The first 256 byte portion of such a device contains the product s Vital Product Data VPD The second 256 byte portion contains the local memory configuration Serial Presence Detect SPD data The MVME2400 VPD SROM is located at address and the MVME2400 SPD SROM is located at I2C address 8 Vital product data contains static board build information that is typcially used for board initialization configuration and verification Each board has its own unique VPD SROM containing local hardware configuration information http www motorola com computer literature 1 23 Board Description and Memory Maps The VPD consists of a header section followed by contiguous formatted data packets The header section consists of eye catcher and size fields and the data packets consist of identifier data length and data content fields The header section begins with an eye catcher field that can be used to verify the existence of an initialized VPD SROM an optional EEPROM CRC packet may also be u
330. veloped by a period of time in which no accesses to ROM Flash Block B occur simple way to provide the envelope is to perform at least two accesses to this or another of the SMC s registers before and after the write BASE These control bits define the base address for ROM Flash Block B ROM B BASE bits 0 11 correspond to PPC60x address bits 0 11 respectively For larger ROM Flash sizes the lower significant bits of ROM B BASE are ignored This means that the block s base address will always appear at an even multiple of its size ROM B BASE is initialized to FF4 at power up or local bus reset Note Note that in addition to the programmed address the first 1 Mbyte of Block B also appears at FFF00000 SFFFFFFFF if the rom b rv bit is set Also note that the combination of ROM B BASE and rom b siz should never be programmed such that ROM Flash Block B responds at the same address as the CSR SDRAM External Register Set or any other slave on the PowerPC bus rom b 64 rom b 64 indicates the width of ROM Flash device devices being used for Block B When rom b 64 is cleared Block B is 16 bits wide where each half of the SMC interfaces to 8 3 56 Computer Group Literature Center Web Site Programming Model bits When rom b 64 is set Block B is 64 bits wide where each half of the SMC interfaces to 32 bits rom b 64 matches the value that was on the RD3 pin at power up reset It cannot be changed by software rom b siz The
331. will be invalidated discarded The PHB does not have a mechanism for snooping the PPC60x bus for transactions associated with the prefetched read data within the PCI FIFO Caution therefore caution should be exercised when using the prefetch option within coherent memory space The PPC Master will never perform prefetch reads beyond the address range mapped within the PCI Slave map decoders As an example assume PHB has been programmed to respond to PCI address range 10000000 http www motorola com computer literature 2 13 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller through 1001FFFF with an offset of 2000 The PPC Master will perform its last read the PPC60x bus at cache line address 3001FFFC or word address 3001FFFS The 60 bus transfer types generated by the Master depend on the PCI command code and the INV GBL bits in the PSATTx registers The GBL bit determines whether or not the GBL_ signal is asserted for all portions of a transaction and is fully independent of the PCI command code and INV bit A following table shows the relationship between the PCI command codes and the INV bit Table 2 5 PPC Master Transfer Types PCI Command Code INV Transfer Transfer Size 0 4 Memory Read 0 Read Burst Single Beat 01010 Memory Read Multiple Memory Read Line Memory Read 1 Read With Intent to Burst Single Beat 01110 Memory Read Multiple
332. www motorola com computer literature 2 37 Hawk PCI Host Bridge amp Multi Processor Interrupt Controller A special function is added to the PCI arbiter to hold the grant asserted through a lock cycle When the POL bit in the PCI arbiter control register is set the grant associated with the agent initiating the lock cycle will be held asserted until the lock cycle is complete If this bit is clear the arbiter does not distinguish between lock and non lock cycle Endian Conversion The PHB supports both Big and Little Endian data formats Since the PCI bus is inherently Little Endian conversion is necessary if all PPC devices are configured for Big Endian operation The PHB may be programmed to perform the Endian conversion described below When PPC Devices are Big Endian When all PPC devices are operating in Big Endian mode all data to from the PCI bus must be swapped such that the PCI bus looks big endian from the PPC bus s perspective This association is true regardless of whether the transaction originates on the PCI bus or the PPC bus This is shown in Figure 2 7 Computer Group Literature Center Web Site Functional Description a a a Cer o oe or ces D7 D6 D5 D4 D3 D2 D1 DO PCI x 86 9 9 8 8 8 8 9 B Y N 5 O a a lt lt xt 4 lt lt lt lt 8 8 9 X 8 8 g n eo a 2 I

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