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ADSP-2185 DSP Microcomputer

1. 420 400 380 360 1 E 340 a 320 5 300 5 280 260 240 220 200 28 29 30 31 32 33 34 Alte MHz POWER IDLE 2 95 90 85 80 E 1 75 E a 70 65 60 a 55 50 45 40 28 29 30 31 32 33 34 1 MHz POWER IDLE MODES IDLE 1 E d a 5 5 a IDLE 16 IDLE 128 28 29 30 831 32 34 1 MHz VALID FOR ALL TEMPERATURE GRADES 1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS IDLE REFERS TO ADSP 2185 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION DEASSERTED PINS ARE DRIVEN TO EITHER Vpp OR GND 3TYPICAL POWER DISSIPATION AT 5 0V Vpp AND 25 C EXCEPT WHERE SPECIFIED ipp MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL MEMORY 50 OF THE INSTRUCTIONS ARE MULTIFUNCTION TYPES 1 4 5 12 13 14 30 ARE TYPE 2 AND TYPE 6 AND 20 ARE IDLE INSTRUCTIONS Figure 8 Power vs Frequency 15 ADSP 2185 CAPACITIVE LOADING Figures 9 and 10 show the capacitive loading characteristics of the ADSP 2185 30 a N a RISE TIME 0 4 2 4 ns 0 50 100 150 200 250 300 pF Figure 9 Typical Output Rise Time vs Load Capacitance C at Maximum Ambient Operating Temperature NOMINAL VALID OUTPUT DELAY OR HOLD ns 2 4
2. 6 0 50 100 150 200 250 pF Figure 10 Typical Output Valid Delay or Hold vs Load Capacitance C at Maximum Ambient Operating Temperature TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state T he out put disable time tps is the difference of tu gAsungp and as shown in the Output E nable D isable diagram T he time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0 5 V from the measured output high or low voltage T he decay time tpecay 15 dependent on the capacitive load C and the current load on the output pin It can be approximated by the fol lowing equation C x0 5V iL from which tpis tm EASURED toecay 16 is calculated If multiple pins such as the data bus are dis abled the measurement value is that of the last pin to stop driving INPUT 1 5V 2 0V OUTPUT 1 5V 0 3V Figure 11 Voltage Reference Levels for AC Measure ments Except Output Enable Disable Output Enable Time Output pins are considered to be enabled when they have made atransition from a high impedance state to when they start driving T he output enable time tena is the interval from when a reference signal reaches a high or low voltage level
3. T his organization provides for two external 8K overlay segments using only the normal 14 address bits T his allows for simple program overlays using one of the two external segments in place of the on chip memory C are must be taken in using this overlay space in that the processor core i e the sequencer does not take into account the PM OVLAY register value F or example if a loop operation was occurring on one of the exter nal overlays and the program changes to another external over lay or internal memory an incorrect loop operation could occur In addition care must be taken in interrupt service routines as the overlay registers are not automatically saved and restored on the processor mode stack When M ode 1 booting is disabled and overlay memory is disabled PM OVLAY must be 0 Figure 5 shows the memory map in this configuration PROGRAM MEMORY ADDRESS Ox3FFF INTERNAL 8K PMOVLAY 0 MODE B 1 0x2000 0x1 FFF 8K EXTERNAL 0x0000 Figure 5 Program Memory Mode B 1 Data Memory The ADSP 2185 has 16 352 16 bit words of internal data memory addition the AD SP 2185 allows the use of 8K external memory overlays Figure 6 shows the organization of the data memory DATA MEMORY ADDRESS Ox3FDF 32 MEMORY MAPPED REGISTERS INTERNAL 8160 WORDS 0x2000 OxiFFF 8K INTERNAL DMOVLAY 0 OR EXTERNAL 8K DMOVLAY 1 2 0 0000 Figure 6 Data Memory T here a
4. If Go M 15 enabled the ADSP 2185 will not halt program execution until it encounters an instruction that requires an external memory access If the AD SP 2185 is performing an external memory access when the external device asserts the BR signal then it will not three state the memory interfaces or assert the BG signal until the processor cycle after the access completes T he instruction does not need to be completed when the bus is granted If a single instruction requires two external memory accesses the bus will be granted between the two accesses When the BR signal is released the processor releases the BG signal reenables the output drivers and continues program execution from the point where it stopped T he bus request feature operates at all times including when the processor is booting and when RESET is active The BGH pin is asserted when the AD SP 2185 is ready to execute an instruction but is stopped because the external bus is already granted to another device T he other device can release the bus by deasserting bus request Once the bus is released the AD SP 2185 deasserts BG and BGH and executes the external memory access Flagl O Pins The AD SP 2185 has eight general purpose programmable input output flag pins T hey are controlled by two memory mapped registers The register determines the direction 1 output and 0 input The PFDATA register is used to read and write the values on
5. 100 Lead TQFP Package Pin 9 sia 6 eza 014 dd 44 Iv oavi Lv ravyezv zavyev 92 22 82 62 08 18 8 8 v8 S8 98 28 88 68 06 16 26 6 v6 S6 96 26 86 66 001 E B m 15 D15 74 D14 73 D13 72 D12 71 GND 70 D11 69 D10 68 D9 67 VDD 66 GND 65 D8 IDENTIFIER 64 D7 IWR 63 D6 IR 19 N o a 62 D5 IAL w gt a E Not to Scale 61 04 15 60 GND 59 VDD 58 57 D2 IAD15 56 D1 IAD14 55 DO IAD13 N n 24 N73 SJd 010ul A4 IAD3 1 AS IAD4 2 GND AD5 4 AD8 7 AD9 8 10 A11 1AD10 9 A12 IAD11 10 A13 IAD12 11 GND 12 CLKIN 13 14 15 16 GND 17 VDD 18 ERE 5 REV 0 28 ADSP 2185 The ADSP 2185 package pinout is shown the table below Pin names bold text replace the plain text named functions when 1 separates two functions when either function can be active for either major 1 0 mode Signals enclosed in brackets are state bits
6. 9 max Vin 10 uA lu Lo L evel Input Current max Vn 20V 10 uA loz T hree State eakage C urrent max Vin Vppmax 10 uA lazi T hree State L eakage C urrent 9 Vpp max Vin 0 10 uA Supply Current Idle 9 Vpp 5 0 12 4 mA 65 Supply Current D ynamic Vpp 5 0 TAMB 25 tek 30 ns 63 Input Pin Capacitance 9 1 22 5 V fiy 1 0 MHz 8 pF Tame 25 C Co Output Pin C apacitance 12 13 22 5 V fin 1 0MHz T amg 25 C 8 NOTES 1 Bidirectional pins D0 D 23 RF 50 RFS1 SCLKO0 SCLK1 TFSO TFS1 A1 A13 PFO PF 7 nput only pins RESET BR DRO DR1 PWD nput only pins CLKIN RESET BR DRO DR1 PWD Output pins BG PMS DMS BMS IOMS CMS RD WR PWDACK A0 DT 1 CLKOUT FL2 0 Although specified for T T L outputs all AD SP 2185 outputs are CM OS compatible and will drive to pp and GND assuming no dc loads 9 Guaranteed but not tested 7Three statable pins A0 A13 D 0 D 23 PMS DMS BMS IOMS CMS RD WR DT1 5 SCLK1 TFSO TFS1 RFSO RSF1 PFO PF7 80V on BR CLKIN Inactive dle refers to AD SP 2185 state of operation during execution of IDLE instruction D easserted pins are driven to either V pp or GND 101DD measurement taken with all instructions executing from internal memory 50 of the instructions are multifunction types 1 4 5
7. Support for an externally generated TTL or CM OS proces sor clock T he external clock can continue running during power down without affecting the lowest power rating and 100 CLKIN cycle recovery Support for crystal operation includes disabling the oscillator to save power the processor automatically waits approxi mately 4096 CLKIN cycles for the crystal oscillator to start or stabilize and letting the oscillator run to allow 100 CLKIN cycle start up Power down is initiated by either the power down pin PWD or the software power down force bit nterrupt support allows an unlimited number of instructions to be executed before optionally powering down T he power down interrupt also can be used as a nonmaskable edge sensitive interrupt Context clear save control allows the processor to continue where it left off or start with a clean context when leaving the power down state The RESET pin also can be used to terminate power down Power down acknowledge pin indicates when the processor has entered power down ADSP 2185 Idle When the AD SP 2185 is in theldle M ode the processor waits indefinitely in a low power state until an interrupt occurs When an unmasked interrupt occurs it is serviced execution then continues with the instruction following the IDLE instruction In Idle mode IDM A BDMA and autobuffer cycle steals still occur Slow Idle TheIDLE instruction is enhanced on the ADSP 2185 to let
8. tion cycle time Every instruction can execute a single proces sor cycle T he ADSP 2185 s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera tions in parallel one processor cycle the AD SP 2185 can generate the next program address fetch the next instruction perform one or two data moves update one or two data address pointers perform a computational operation T his takes place while the processor continues to receive and transmit data through the two serial ports receive and or transmit data through the internal DM A port e receive and or transmit data through the byte DM A port decrement timer Development System TheADSP 2100 F amily D evelopment Software a complete set of tools for software and hardware system development sup ports the AD SP 2185 T he System Builder provides a high level method for defining the architecture of systems under develop ment T he Assembler has an algebraic syntax that is easy to program and debug T he Linker combines object files into an executable file T he Simulator provides an interactive instruction level simulation with a reconfigurable user interface to display different portions of the hardware environment A PROM Splitter generates PROM programmer compatible files T he C Compiler based on the Free Software Foundation s GNU C Compiler generates AD SP 2185 assembly source code T he source code debugg
9. reconfigure PF2 to bean input as the pull up or pull down will hold the pin in a known state and will not switch Active configuration involves the use of a three stateable exter nal driver connected to the M ode C pin A driver s output en able should be connected to the D SP s RESET signal such that it only drives the PF2 pin when RESET is active low After REV 0 ADSP 2185 RESET is deasserted the driver should three state thus allow ing full use of the PF 2 pin as either an input or output To minimize power consumption during power down configure the programmable flag as an output when connected to a three stated buffer T his ensures that the pin will be held at a constant level and not oscillate should the three state driver s level hover around the logic switching point Interrupts T he interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead The ADSP 2185 provides four dedicated external interrupt input pins IRQ2 IRQLO IRQLI and IRQE shared with the PF 7 4 pins In addition SPORT 1 may be reconfigured for IRQO IRQI FLAG IN and FLAG OUT for a total of six external interrupts T he AD SP 2185 also supports internal interrupts from the timer the byte DM A port the two serial ports software and the power down control circuit T he inter rupt levels are internally prioritized and individually maskable except power down and reset T he IR
10. 12 13 14 30 are type 2 and type 6 and 2096 are idle instructions Vin 0V and For typical figures for supply currents refer to Power Dissipation section 12 Applies to T package type Output pin capacitance is the capacitive load for three stated output pin Specifications subject to change without notice REV 0 13 ADSP 2185 ABSOLUTE MAXIMUM RATINGS Supply Voltage 0 3 V to 7 V Input 0 3 V to Vpp 0 3 Output Voltage Swing 0 3 V to Vpp 0 3 V Operating T emperature Range Ambient 40 C to 85 C Storage T emperatureRange 65 to 150 Lead Temperature 5 sec 280 Stresses above those listed under Absolute aximum Ratings may cause nent damage to the device T hese are stress ratings only functional operation of the device these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVITY The ADSP 2185 is an ESD electrostatic discharge sensitive device Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection Permanent damage may occur to devices subjected to high energy electrostatic discharges The ADSP 2185 feat
11. Address Range Wait State Register 0x000 0x1F F IOWAITO 0x200 0x3F F IOWAIT 1 0x400 0x5F F IOWAIT 2 0x600 0x7F F IOWAIT 3 Composite Memory Select CMS The ADSP 2185 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space T he CMS signal is generated to have the same timing as each of the individual memory select signals PMS DMS BMS IOMS but can combine their functionality When set each bit in the CM SSEL register causes the CMS signal to be asserted when the selected memory select is as serted F or example to use 32K word memory to act as both program and data memory set the PMS and DMS bits in the CM SSEL register and use the CMS pin to drive the chip select of the memory and use either DMS or PMS as the additional address bit T he CMS pin functions as the other memory select signals with the same timing and bus request logic A 1 in the enable bit causes the assertion of the CMS signal at the same time as the REV 0 ADSP 2185 selected memory select signal All enable bits except the BMS bit default to 1 at reset Byte Memory T he byte memory space is a bidirectional 8 bit wide external memory space used to store programs and data Byte memory is accessed using the BD MA feature he byte memory space consists of 256 pages each of which is 16K x 8 T he byte memory space on the AD SP 2185 supports read and wr
12. High to DT Disable 15 ns RFS Multichannel Frame Delay Zero to DT Valid 15 ns CLKOUT SCLK RFSout TFSour DT gt TFSout ALTERNATE FRAME MODE RFSout MULTICHANNEL MODE FRAME DELAY 0 MFD 0 TFSin ALTERNATE FRAME MODE RFSin MULTICHANNEL MODE FRAME DELAY 0 MFD 0 Figure 19 Serial Ports 22 REV ADSP 2185 Parameter Min Max Unit IDMA Address Latch Timing Requirements tate Duration of Address atch 3 10 ns tiasu IAD 15 0 Address Setup before Address Latch End 5 ns tian IAD 15 0 Address old after Address atch End 2 ns tika IACK Low before Start of Address Latch 0 ns tats Start of Write or Read after Address atch E nd 3 3 ns NOTES Start of Address Latch IS Low and IAL High Start of Write or Read IS Low and IWR Low or IRD Low 3End of Address Latch IS High or IAL Low IAL tiare 15 gt IAD 15 0 IWR Figure 20 IDMA Address Latch REV 0 23 ADSP 2185 Parameter Min Max Unit IDMA Write Short Write Cycle Timing R equirements kw IACK L ow before Start of Write 0 ns tiwp Duration of Write 2 15 ns IAD 15 0 D ata Setup before End of Write gt 4 5 ns tau IAD 15 0 D ata Hold after End of Write 2 ns Switching Characteristics kuw Start of Write to IACK H igh 15 ns NOTES 1Start of Write
13. IS Low and IWR Low of Write IS High or IWR High 31f Write Pulse ends before IACK Low use specifications tipsu If Write Pulse ends after IACK ow use specifications tiksu tiu tkw Ke gt D IAD 15 0 Figure 21 IDMA Write Short Write Cycle 24 REV ADSP 2185 Parameter Min Max Unit IDMA Write Long Write Cycle Timing R equirenents tw IACK Low before Start of W rite 0 ns tixsu IAD 15 0 Data Setup before Low 0 5 tc 10 ns IAD 15 0 Data H old after Low 2 ns Switching Characteristics tikLw Start of Write to Low 1 5 tex ns Start of Write to High 15 ns NOTES Start of Write IS Low and IWR Low 212 Write Pulse ends before IACK Low use specifications tipsy 31f Write Pulse ends after IACK Low use specifications tixsu T his is the earliest time for IACK Low from Start of Write For IDM A Write cycle relationships please refer to the ADSP 2100 Family User s M anual tkw c 4 likuw E cw P SENA ____ gt 0 IAD 15 0 Figure 22 IDMA Write Long Write Cycle REV 0 25 ADSP 2185 Parameter Min Max Unit IDMA Read Long Read Cycle Timing R equirements IACK Low before Start of Read 0 ns Duration of Read 15 ns Switching
14. OUT Low 0 25 tck 17 ns Switching Characteristics NENNEN tsp CLKOUT High to xMS RD WR D isable 0 25 tck 10 ns tsps xMS RD WR Disable to BG Low 0 ns tse BG High to xMS RD WR Enable 0 ns tsec xMS RD WR Enable to CLKOUT Hig 0 25 tck 7 ns tsp gn xMS RD WR Disable to Low 0 ns High to xMS RD WR Enable 0 ns NOTES xMS PMS DMS CMS IOMS BMS TBR is an asynchronous signal If BR meets the setup hold requirements it will be recognized during the current clock cycle otherwise the signal will be recognized on the following cycle Refer to the ADSP 2100 Family User s M anual for BR BG cycle relationships BGH is asserted when the bus is granted and the processor requires control of the bus to continue teH CLKOUT e CNN QS BR N tes CLKOUT PMS DMS BNS RD WR tsp gt tsec 7 B 5 tse Figure 16 Bus Request Bus Grant REV 0 19 ADSP 2185 Parameter Min Max Unit Memory Read Timing Requirements _ trop RD Low to Data Valid 0 5 9 ns taa A0 A13 xMS to D ata Valid 0 75 105 w ns trou Data H old from RD High 0 ns Switching Characteristics trp RD Pulse Width 0 5tck 5 w ns CLKOUT HightoRDLow _ 0 25 5 0 25 7 ns tasr A0 A13 xMS Setup before RD Low 0 25 tcx 6 ns A0 A13 xMS H old after RD D easserted 0 25 3 ns tRwR RD High to RD or WR L
15. grade specifications for the ADSP 2185 5 GENERAL DESCRIPTION The ADSP 2185 is single chip microcomputer optimized for digital signal processing DSP and other high speed numeric processing applications The ADSP 2185 combines the AD SP 2100 family base archi tecture three computational units data address generators and a program sequencer with two serial ports a 16 bit internal DMA port a byte DM A port a programmable timer Flag 1 0 extensive interrupt capabilities and on chip program and data memory The ADSP 2185 integrates 80K bytes of on chip memory con figured as 16K words 24 bit of program RAM and 16K words 16 bit of data Power down circuitry is also provided to meet the low power needs of battery operated portable equip ment The AD SP 2185 is available in 100 pin T QFP package In addition the AD SP 2185 supports new instructions which include bit manipulations bit set bit clear bit toggle bit test new ALU constants new multiplication instruction x squared biased rounding result free ALU operations 1 0 memory trans fers and global interrupt masking for increased flexibility One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 617 329 4700 World Wide Web Site http www analog com Fax 617 326 8703 Analog Devices Inc 1997 ADSP 2185 Fabricated in a high speed double metal low power 0 5 um CM OS process the AD SP 2185 operates with a 30 ns instruc
16. iming requirements guarantee that the proces sor operates correctly with other devices 14 MEMORY TIMING SPECIFICATIONS T hetable below shows common memory device specifications and the corresponding AD SP 2185 timing parameters for your convenience Memory ADSP 2185 Timing Device Timing Parameter Specification Parameter Definition Address Setup to tasw A0 A13 xMS Setup W rite Start before WR Low Address Setup to taw A0 A13 xMS Setup Write End before WR D easserted Address Hold Time twra A0 A13 xMS H old before WR D ata Setup T ime tpw Data Setup before WR High Data Hold T ime OE to Data Valid Address Access ime taa D ata Hold after WR High RD L ow to Data Valid A0 A13 xMS to Data Valid xMS PMS DMS BMS CMS IOMS FREQUENCY DEPENDENCY FOR TIMING SPECIFICATIONS is defined as 0 5tc x The AD SP 2185 uses an input clock with a frequency equal to half the instruction rate a 16 67 MHz input clock which is equivalent to 60 ns yields a 30 ns proces sor cycle equivalent to 33 MH tex values within the range of 0 5tcx period should be substituted for all relevant timing para meters to obtain the specification value Example 0 5 7 ns 0 5 30 ns 7ns 8ns REV 0 ADSP 2185 2185 POWER INTERNAL 3 4 ENVIRONMENTAL CONDITIONS Ambient T emperature R ating Tama T case PD x Oca T case Case T emperature in C PD Powe
17. 1 0 memory space also share the external buses Program memory can store both instructions and data permit ting the ADSP 2185 to fetch two operands in a single cycle one from program memory and one from data memory T he AD SP 2185 can fetch an operand from program memory and the next instruction in the same cycle When configured in host mode the AD 5 2185 has a 16 bit Internal DMA port IDM A port for connection to external systems ID port is made up of 16 data address pins and five control pins The DMA port provides transparent direct access to the DSPs on chip program and data An interface to low cost byte wide memory is provided by the Byte port BDM port The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off chip storage of program overlays or data tables The byte memory and 1 0 memory space interface supports slow memories and 1 0 memory mapped peripherals with programmable wait state generation External devices can gain control of external buses with bus request grant signals BR BGH and BG One execution mode Go M ode allows the AD SP 2185 to continue running from on chip memory N ormal execution mode requires the processor to halt while buses are granted The AD SP 2185 can respond to eleven interrupts T here can be up to six external interrupts one edge sensitive two level sensitive and three configurable and seven intern
18. 100 1 ead TQFP ST 100 AD SP 2185K ST 133 0 to 70 C 33 3 100 Lead TQFP ST 100 ADSP 2185BST 133 40 C to 85 C 33 3 100 L ead TQFP ST 100 ST Plastic T hin Quad Flatpack T QFP OUTLINE DIMENSIONS Dimensions shown in inches and millimeters 100 Lead Metric Thin Plastic Quad Flatpack TQFP ST 100 0 640 16 25 0 630 16 00 0 620 15 75 0 555 14 05 0 551 14 00 TYP SQ 0 547 13 90 0 476 12 10 0 063 1 60 MAX 0 474 12 05 RH 0 024 075 W 472 12 00 0 022 0 60 TYP 0 020 0 50 5 A 100 al SEATING 1 PLANE TOP VIEW PINS DOWN 0 004 0 102 MAX LEAD 25 51 COPLANARITY 2 50 0 gt e 0 007 0 177 0 020 0 50 0 010 0 27 0 005 0 127 BSC 0 009 0 22 TYP 0 003 0 077 LEAD PITCH 0 006 0 17 LEAD WIDTH 30 REV 31 161 01 6620 V S f1 NI GALNIdd 32
19. ANALOG DEVICES DSP Microcomputer ADSP 2185 FEATURES PERFORMANCE 30 ns Instruction Cycle Time 33 MIPS Sustained Performance Single Cycle Instruction Execution Single Cycle Context Switch 3 Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power Down Mode Featuring Low CMOS Standby Power Dissipation with 100 Cycle Recovery from Power Down Condition Low Power Dissipation in Idle Mode INTEGRATION ADSP 2100 Family Code Compatible with Instruction Set Extensions 80K Bytes of On Chip RAM Configured as 16K Words On Chip Program Memory RAM and 16K Words On Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU Multiplier Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution Programmable 16 Bit Interval Timer with Prescaler 100 Lead TQFP SYSTEM INTERFACE 16 Bit Internal DMA Port for High Speed Access to On Chip Memory Mode Selectable 4 MByte Byte Memory Interface for Storage of Data Tables amp Program Overlays 8 Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers Mode Selectable Memory Interface with 2048 Locations Supports Parallel Peripherals Mode Selectable Programmable Memory Strobe amp Separate I O Memory Space Permits Glueless System Des
20. Characteristics igh after Start of Read 15 ns IAD 15 0 Data Setup before IACK Low 0 5 tex 10 ns IAD 15 0 Data H old after End of Read ns kpp IAD 15 0 D ata Disabled after End of Read 10 ns IAD 15 0 Previous Data Enabled after Start of Read 0 ns IAD 15 0 Previous Data Valid after Start of Read 15 ns IAD 15 0 Previous D ata old after Start of Read DM 1 2tck 5 ns linapu2 15 0 Previous D ata old after Start of Read PM 2 5 ns NOTES 1Start of Read IS Low and IRD Low End of Read IS High or IRD High 3DM read or first half of PM read 4Second half of PM read TACK 5 IRD X A IAD 15 0 tirov lt lt Figure 23 IDMA Read Long Read Cycle 26 REV ADSP 2185 Parameter Min Max Unit IDMA Read Short Read Cycle Timing R equirenents IACK Low before Start of Read 0 ns Duration of Read 15 ns Switching Characteristics High after Start of Read 15 ns IAD 15 0 Data H old after End of Read 0 ns tikon IAD 15 0 Data Disabled after End of Read 10 ns IAD 15 0 Previous Data Enabled after Start of Read 0 ns IAD 15 0 Previous Data Valid after Start of Read 15 ns NOTES Start of Read IS Low and IRD Low End of Read IS High or IRD High IAD 15 0 Figure 24 IDMA Read Short Read Cycle REV 0 27 ADSP 2185
21. ODE C PF1 IS MODE B PFO IS MODE A Figure 14 Clock Signals REV 0 17 ADSP 2185 Parameter Min Max Unit Interrupts and Flag Timing R equirements tirs IRQx or PFx Setup before CLK OUT Low gt 4 0 25 15 ns tru IRQx or PFx Hold after CLKOUT Hight 34 0 25 tex ns Switching Characteristics trou Flag Output H old after CLKOUT Low 0 5 tc 7 ns trop Flag Output D elay from CLK OUT Low 0 25 tc 5 ns NOTES lf IRQx and F I inputs meet tirs and setup hold requirements they will be recognized during the current clock cycle otherwise the signals will be recognized on the following cycle Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP 2100 F amily U se s M anual for further information on interrupt servicing dge sensitive interrupts require pulse widths greater than 10 ns level sensitive interrupts must be held low until serviced IROx IRQO IRQI IRQ2 IRQLO IRQLI IRQE 4PFx PFO PF 1 PF2 PF5 PF6 PF 7 outputs PF x FLO FL1 FL2 Flag out CLKOUT FLAG OUTPUTS IRQx PFx trop tron gt FK4 try trs Figure 15 Interrupts and Flags 18 REV ADSP 2185 Parameter Min Max Unit Bus Request Grant Timing Requirements _ teu BR Hold after CLK OUT High 0 25 tc 2 ns tgs BR Setup before CLK
22. Q2 IRQO and IRQI input pins can be programmed to be either level or edge sensitive IRQLO and IRQLI level sensitive and IRQE is edge sensitive T he priorities and vector addresses of all interrupts are shown in T ablel Tablel Interrupt Priority amp Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address H ex Reset or Power U p with 21 0000 Highest Priority Power down N onmaskable 002C IRQ2 0004 IRQLI 0008 IRQLO 000C SPORTO T ransmit 0010 SPORT 0 Receive 0014 IROE 0018 BDMA Interrupt 001C SPORT 1 Transmit or IRO1 0020 SPORT 1 Receive or IRQO 0024 Timer 0028 Lowest Priority Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially Inter rupts can be masked or unmasked with the IM ASK register Individual interrupt requests are logically AN D ed with the bits IM ASK the highest priority unmasked interrupt is then selected T he power down interrupt is nonmaskable The ADSP 2185 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register T his does not affect serial port autobuffering or DMA transfers interrupt control register ICNTL controls interrupt nest ing and defines the IRQO IRQ1 and IRQ2 external interrupts to be either edge or level sensitive T he IRQE pin is an external edge sensit
23. T he following pins are also used by the EZ ICE BR BG RESET GND T he EZ ICE uses the EE emulator enable signal to take control of the AD SP 2185 in the target system T his causes the processor to use its ERESET EBR and EBG pins instead of the RESET BR and BG pins T he BG output is three stated T hese signals do not need to be jumper isolated in your system T he EZ ICE connects to your target system via a ribbon cable and a 14 pin female plug T he female plug is plugged onto the 14 pin connector a pin strip header on the target board REV 0 11 ADSP 2185 Target Board Connector for EZ ICE Probe T he EZ ICE connector a standard pin strip header is shown in Figure 7 You must add this connector to your target board design if you intend to use the EZ ICE Be sure to allow enough room in your system to fit the EZ ICE probe onto the 14 pin connector KEY NO PIN ELOUT TOP VIEW Figure 7 Target Board Connector for EZ ICE T he 14 pin 2 row pin strip header is keyed at the Pin 7 loca tion you must remove Pin 7 from the header T he pins must be 0 025 inch square and at least 0 20 inch in length Pin spac ing should be 0 1 x 0 1 inches T he pin strip header must have at least 0 15 inch clearance on all sides to accept the EZ ICE probe plug Pin strip headers are available from vendors such as McKenzie and Samtec Target Memory Interface For your target system to be
24. al interrupts generated by the timer the serial ports SPORT s the Byte DM A port and the power down circuitry T here is also a master RESET signal T hetwo serial ports provide a complete synchronous serial interface with optional companding in hardware and a REV 0 wide variety of framed or frameless data transmit and receive modes of operation Each port can generate an internal programmable serial clock or accept an external serial clock The ADSP 2185 provides up to 13 general purpose flag pins T he data input and output pins on SPORT 1 can be alternatively configured as an input flag and an output flag In addition eight flags are programmable as inputs or outputs and three flags are always outputs A programmable interval timer generates periodic interrupts A 16 bit count register T COU NT decrements every n processor cycle where n is a scaling value stored in an 8 bit register TSCALE When the value of the count register reaches zero an interrupt is generated and the count register is reloaded from a 16 bit period register T PERIOD Serial Ports The ADSP 2185 incorporates two complete synchronous serial ports SPORT 0 and SPORT 1 for serial communications and multiprocessor communication is a brief list of the capabilities of the ADSP 2185 SPORT s For additional information on Serial Ports refer to the AD SP 2100 F amily U ser s M anual SPORTsare bidirectional and have a separate doub
25. alge braic syntax for ease of coding and readability A comprehensive set of development tools supports program development POWER DOWN CONTROL PROGRAM SEQUENCER MEMORY PROGRAM FULL MEMORY e MODE PROGRAMMABLE Vo EXTERNAL ADDRESS DATA ADDRESS GENERATORS 16k x 24 PROGRAM MEMORY BUS EXTERNAL A BUS DATA MEMORY ADDRESS BYTE DMA CONTROLLER PROGRAM MEMORY DATA OR DATAMEMORYDATA T Awan EXTERNAL DATA BUS INTERNAL DMA PORT HOST MODE gt MEMORY ADDRESS Y ARITHMETIC UNITS ADSP 2100 BASE ARCHITECTURE Figure 1 Block Diagram Figure 1 is an overall block diagram of the AD SP 2185 T he processor contains three independent computational units the ALU the multiplier accumulator M AC and the shifter T he computational units process 16 bit data directly and have provi sions to support multiprecision computations The ALU per forms a standard set of arithmetic and logic operations division primitives are also supported T he M AC performs single cycle multiply multiply add and multiply subtract operations with 40 bits of accumulation T he shifter performs logical and arith metic shifts normalization denormalization and derive expo nent operations T he shifter can be used to efficiently implement numeric format control including multiword and block floating point
26. ap code from byte memory Space Full Memory Mode allows access to 2048 loca tions of 16 bit wide data It is intended to be used to communi cate with parallel peripheral devices such as data converters and external registers or latches Program Memory TheADSP 2185 contains a 16K x 24 on chip program RAM T he on chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle In addition the AD SP 2185 allows the use of 8K external memory overlays T he program memory space organization is controlled by the M ode B pin and the PM OVLAY register N ormally the ADSP 2185 is configured with M ode B 0 and program memory organized as shown in F igure 4 PROGRAM MEMORY ADDRESS Ox3FFF 8K INTERNAL PMOVLAY 0 MODE 0 OR EXTERNAL 8K PMOVLAY 1 or 2 MODE B 0 0x2000 Ox1FFF 8K INTERNAL 0 0000 Figure 4 Program Memory Mode 0 There are 16K words of memory accessible internally when the PM OVLAY register is set to 0 When PM OVLAY is set to some thing other than 0 external accesses occur at addresses 0x2000 through Ox3FFF T he external address is generated as shown in T able ll ADSP 2185 Tablell PMOVLAY Memory 1 A12 0 0 Internal Not Applicable Not Applicable 1 External 0 13 LSBs of Address Overlay 1 Between 0x2000 and Ox3FFF 2 External 1 13 LSBs of Address Overlay 2 Between 0x2000 and Ox3F F F
27. ations work normally T his mode allows more efficient implementation of bit specified algorithms that use biased rounding for example the GSM speech compression routines U nbiased rounding is preferred for most algorithms Note BIASRND bit is Bit 12 of the SPORT 0 Autobuffer Con trol register Instruction Set Description The ADSP 2185 assembly language instruction set has an alge braic syntax that was designed for ease of coding and readabil ity The assembly language which takes full advantage of the processor s unique architecture offers the following benefits The algebraic syntax eliminates the need to remember cryptic assembler mnemonics F or example a typical arithmetic add instruction such as AR AYO resembles a simple equation Every instruction assembles into a single 24 bit word that can execute in a single instruction cycle T he syntax is a superset AD SP 2100 Family assembly lan guage and is completely source and object code compatible with other family members Programs may need to be relo cated to use on chip memory and conform to the ADSP 2185 s interrupt vector and reset vector map Sixteen condition codes are available F or conditional jump call return or arithmetic instructions the condition can be checked and the operation executed in the same instruction cycle M ultifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write
28. compatible with the EZ I C E emulator it must comply with the memory interface guidelines listed below PM DM BM IOM and CM Design your Program M emory PM Data M emory DM Byte M emory BM 1 0 M emory IOM and Composite M emory CM external interfaces to comply with worst case device tim ing requirements and switching characteristics as specified in this D SP s data sheet T he performance of the EZ ICE may approach published worst case specification for some memory access timing requirements and switching characteristics 12 N ote If your target does not meet the worst case chip specifica tion for memory access parameters you may not be able to emulate your circuitry at the desired CLKIN frequency D epend ing on the severity of the specification violation you may have trouble manufacturing your system as D SP components statisti cally vary in switching characteristic and timing requirements within published limits Restriction All memory strobe signals on the AD SP 2185 RD WR PMS DMS BMS CMS and IOMS used in your target system must have 10 kQ pull up resistors connected when the EZ ICE is being used T he pull up resistors are necessary because there are no internal pull ups to guarantee their state during prolonged three state conditions resulting from typical EZ ICE debugging sessions T hese resistors may be removed at your option when the EZ ICE is not being used Target System Interfac
29. ct Input C hecked only During RESET PFO 1 0 Programmable1 O Pin During N ormal Operation CLKIN 2 Clock Quartz Crystal Input CLKOUT 1 Processor Clock Output SPORTO 5 I O Serial Port I O Pins SPORT 1 5 I O Serial Port I O Pins 0 Edge evel Sensitive Interrupts FI FO Flag Flag Out PWD 1 Power D own Control Input PWDACK 1 Power D own Control Output FLO FL1 212 3 Output Flags VDD andGND 16 Power and Ground EZ Port 9 For Emulation Use NOTES Interrupt F lag pins retain both functions concurrently If IM ASK is set to enable the corresponding interrupts the D SP will vector to the appropriate interrupt vector address when the pin is asserted either by external devices or set as a programmable flag SPORT configuration determined by the D SP System Control Register Soft ware configurable Memory Interface Pins The AD SP 2185 processor can be used in one of two modes Full M emory M ode which allows BDM A operation with full external overlay memory 1 0 capability or ost M ode which allows IDM A operation with limited external addressing capabilities T he operating mode is determined by the state of the M ode C pin during RESET and cannot be changed while the processor is running Full Memory Mode Pins Mode C 0 of Input Pin Pins Output Function A13 0 14 Address Output Pins Pro gram Data Byte an
30. d 1 0 Spaces D 23 0 24 1 0 Data 1 0 Pins for Program D ata Byte and 1 0 Spaces 8 M SBs Are Also Used as Byte M emory Addresses Host Mode Pins Mode 1 of Input Pins Output Function IAD 15 0 16 1 0 IDMA Port Address D ata Bus A0 1 Address Pin for External 1 0 Program Data or Byte Access D 23 8 16 1 0 Data 1 0 Pins for Program D ata Byte and 1 0 Spaces IWR 1 IDMA Write Enable IRD 1 IDMA Read Enable IAL 1 Address Latch Pin 15 1 IDMA Select TACK 1 IDMA Port Acknowledge Host ode external peripheral addresses can be decoded using the A 0 CMS PMS DMS and IOMS signals Setting Memory Mode M emory M ode selection for the AD SP 2185 is made during chip reset through the use of the M odeC pin T his pin is multi plexed with the DSP s PF 2 pin so care must be taken in how the mode selection is made T he two methods for selecting the value of M ode are active and passive Passive configuration involves the use a pull up or pull down resistor connected to the M ode C pin To minimize power consumption or if the PF2 pin is to be used as an output in the DSP application a weak pull up or pull down on the order of 100 can be used T his value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor s output driver For minimum power consumption during power down
31. e Signals When the EZ ICE board is installed the performance on some system signals change D esign your system to be compat ible with the following system interface signal changes intro duced by the 2 5 board EZ ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET signal EZ ICE emulation introduces an 8 ns propagation delay between your target circuitry and the D SP on the BR signal 2 emulation ignores RESET and BR when single stepping EZ ICE emulation ignores RESET and BR when in E mu lator Space D SP halted EZ ICE emulation ignores the state of target BR in certain modes As a result the target system may take control of the D SP s external memory bus only if bus grant BG is asserted the EZ ICE board s DSP REV 0 ADSP 2185 RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit Vis 4 5 5 5 4 5 5 5 V TAMB 0 70 40 85 oC ELECTRICAL CHARACTERISTICS K B Grades Parameter Test Conditions Min Typ Max Unit Vin H i L evel Input Voltage 2 9 max 2 0 V Vin Hi Level CLKIN Voltage max 2 2 V Vu Lo L evel Input Voltage 3 Vpp min 0 8 V Vou Hi Level Output Voltage gt min 0 5 mA 24 V Vop min 100 pA V VoL Lo L evel Output Voltage min lop 22mA 0 4 V liu Hi Level Input Current
32. er allows programs to be corrected in the C environment T he Runtime Library includes over 100 ANSI standard mathematical and D SP specific functions The EZ KIT Lite is a hardware software kit offering a complete development environment for the entire AD SP 21xx family an AD SP 218x based evaluation board with PC monitor software plus Assembler Linker Simulator and PROM Splitter software TheADSP 21xx EZ KIT Liteis a low cost easy to use hard ware platform on which you can quickly get started with your DSP software design T he EZ KIT Lite includes the following features 33MHz ADSP 2181 e Full 16 bit Stereo Audio 1 0 with AD 1847 SoundPort C odec RS 232 Interface to PC with Windows 3 1 Control Software Stand Alone Operation with Socketed EPROM EZ ICE Connector for Emulator Control DSP D emo Programs The ADSP 218x 2 Emulator aids in the hardware debugging of an AD SP 2185 system T he emulator consists of hardware host computer resident software and the target board connector T he AD SP 2185 integrates on chip emulation sup port with a 14 pin ICE PORT interface T his interface pro vides a simpler target board connection that requires fewer mechanical clearance considerations than other AD SP 2100 Family EZ ICE s T he ADSP 2185 device need not be removed from the target system when using the EZ ICE nor are any adapters needed D ue to the small footprint of the EZ I C E connector em
33. er itis a DM or PM access T he falling edge of the address latch signal latches this value into the IDM AA register Once the address is stored data can then be either read from or written to the AD SP 2185 s on chip memory Asserting the select line IS and the appropriate read or write line IRD and IWR respectively signals the AD SP 2185 that a particular transaction is required In either case there is a one processor cycle delay for synchronization T he memory access consumes one additional processor cycle Once an access has occurred the latched address is automati cally incremented and another access can occur T hrough the IDM AA register the D SP can also specify the starting address and data format for DM A operation Bootstrap Loading Booting The ADSP 2185 has two mechanisms to allow automatic load ing of the internal program memory after reset T he method for booting is controlled by the M ode A B and C configuration bits as shown in T able VI T hese four states can be compressed into two state bits by allowing an IDM A boot with M ode 1 H owever three bits are used to ensure future compatibility with parts containing internal program memory ROM BDMA Booting When the M ODE pins specify BDM A booting the ADSP 2185 initiates a MA boot sequence when RESET is released 9 ADSP 2185 Table VI Boot Summary T able MODE C MODE B MODE A Booting Method 0 0 0 BDMA feature is used to load
34. essor cycles SYSTEM INTERFACE Figure 2 shows typical basic system configurations with the AD SP 2185 two serial devices a byte wide EPROM and optional external program and data overlay memories mode selectable Programmable wait state generation allows the processor to easily connect to slow peripheral devices T ADSP 2185 also provides four external interrupts and two serial ports or six external interrupts and one serial port H ost M emory mode allows access to the full external data bus but limits addressing to a single address bit A0 Additional system peripherals can be added in this mode through the use of external hardware to generate and latch address signals HOST MEMORY MODE ADSP 2185 1 2x CLOCK OR CRYSTAL A0 A21 BYTE m pata MEMORY Hn cs VO SPACE PERIPHERALS CS 2048 LOCATIONS ADDR OVERLAY DATA MEMORY TWO 8K PM SEGMENTS SERIAL DEVICE ___ SERIAL DEVICE TWO 8K DM SEGMENTS 1 2x CLOCK OR CRYSTAL SPORT1 SCLK1 gt on IRGO SERIAL 3 7 RFS ORIRGO 51 OR iRQ1 DEVICE P I oR FO RFSO SERIAL DEVICE ___ SYSTEM INTERFACE OR IAL D5 HCONTROLLER mona IACK D3 1AD15 0 Figure 2 Basic System Configuration Clock Signals The AD SP 2185 can be clocked by either a crystal or aT TL compatible c
35. g page for the external byte memory space The BDIR register field selects the direction of the transfer Finally the 14 bit BWCOUNT register specifies the number of DSP wordsto transfer and initiates the BDMA circuit transfers accesses can cross page boundaries during sequential addressing A interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register TheBWCOUNT register is updated after each transfer so it can be used to check the status of the transfers When it reaches zero the transfers have finished and a interrupt is gener ated The BM PAGE and BEAD registers must not be accessed by the DSP during BDM A operations T he source or destination of a BDMA transfer will always be on chip program or data memory regardless of the values of M ode B PM OVLAY or DM OVLAY When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BM WAIT T hese accesses continue until the count reaches zero When enough accesses have occurred to REV 0 create a destination word it is transferred to or from on chip memory T he transfer takes one DSP cycle DSP accesses to external memory have priority over BDMA byte memory accesses TheBDMA Context Reset bit BCR controls whether the processor is held off while the BD MA accesses are occurring Setting the BCR bit to 0 allows the processor to contin
36. ign Mode Selectable Programmable Wait State Generation Two Double Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On Chip Program Memory from Byte Wide External Memory e g EPROM or Through Internal DMA Port is a trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM POWER DOWN CONTROL f DATA ADDRESS GENERATORS PROGRAM PAG 2 SEQUENCER FULL MODE PROGRAMMABLE E FLAGS EXTERNAL mus 1 16k x 24 16k x 16 PROGRAM DATA MEMORY MEMORY EXTERNAL DATA BUS iNTERNAL l DMA I PORT 1 L HOST DATA MEMORY DATA ARITHMETIC UNITS ADSP 2100 BASE ARCHITECTURE SERIAL PORTS Six Extemal Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE Port Emulator Interface Supports Debugging in Final Systems GENERAL NOTE T his data sheet represents production
37. ite operations as well as four different data formats T he byte memory uses data bits 15 8 for data T he byte memory uses data bits 23 16 and address bits 13 0 to create a 22 bit address This allows up to a 4 meg x 8 32 megabit ROM or RAM to be used without glue logic All byte memory accesses are timed by the BM WAIT register Byte Memory DMA BDMA Full Memory Mode The Byte memory DMA controller allows loading and storing of program instructions and data using the byte memory space TheBDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8 16 or 24 bit word transferred The BDM A circuit supports four different data formats which are selected by the BT Y PE register field T he appropriate num ber of 8 bit accesses are done from the byte memory space to build the word size selected T able V shows the data formats supported by the BDMA circuit TableV Internal BTYPE Memory Space WordSize Alignment 00 Program M emory 24 Full Word 01 D ata M emory 16 Full Word 10 D ata M emory 8 M SBs 11 Data 8 585 Unused bits the 8 bit data memory formats filled with Os TheBIAD register field is used to specify the starting address for the on chip memory involved with the transfer T he 14 bit BEAD register specifies the starting address for the external byte memory space T he 8 bit BM PAGE register specifies the startin
38. ive interrupt and can be forced and cleared T he IRQLO and IRQL1 pins are external level sensitive interrupts REV 0 heIFC register is write only register used to force and clear interrupts On chip stacks preserve the processor status and are automati cally maintained during interrupt handling T he stacks are twelve levels deep to allow interrupt loop and subroutine nesting T hefollowing instructions allow global enable or disable servic ing of the interrupts including power down regardless of the state of IM ASK Disabling the interrupts does not affect serial port autobuffering or DMA ENA INTS DIS INTS W hen the processor is reset interrupt servicing is enabled LOW POWER OPERATION The ADSP 2185 has three low power modes that significantly reduce the power dissipation when the device operates under standby conditions T hese modes are Power Down idle Slow Idle TheCLKOUT pin may also be disabled to reduce external power dissipation Power D own The ADSP 2185 processor has a low power feature that lets the processor enter a very low power dormant state through hard ware or software control H ere is a brief list of power down features Refer to the AD SP 2100 Family U se s M anual System Interface chapter for detailed information about the power down feature Quick recovery from power down T he processor begins executing instructions in as few as 100 CLKIN cycles
39. latched from the value of the pin at the deassertion of RESET TQFP Pin Configurations Number Name Number Name Number Name Number Name 1 A4 IAD3 26 IRQE PFA 51 EBR 76 D16 2 A5 IADA 27 IRQLO PF5 52 BR 77 D17 3 GND 28 GND 53 EBG 78 D18 4 A6 IAD5 29 IRQLI PF6 54 BG 79 D19 5 7 30 IRQ2 PF7 55 D 0 IAD 13 80 GND 6 A8 IAD7 3l DTO 56 D 81 D20 7 A9 IAD8 32 TFSO 57 D 2 IAD 15 82 D21 8 A10 IAD9 33 RFSO 58 D3 IACK 83 D22 9 A11 IAD 10 34 DRO 59 VDD 84 D23 10 12 11 35 SCLKO 60 GND 85 FL2 11 A13 IAD 12 36 VDD 61 D 415 86 FL1 12 GND 37 DT1 62 D5 IAL 87 FLO 13 CLKIN 38 TFS1 63 D6 IRD 88 PF3 14 XTAL 39 RFS1 64 D7 IWR 89 2 C 15 VDD 40 DR1 65 D8 90 VDD 16 CLKOUT 41 GND 66 GND 91 PWD 17 GND 42 SCLK1 67 VDD 92 GND 18 VDD 43 ERESET 68 D9 93 PF1 M ode B 19 WR 44 RESET 69 D 10 94 PFO ode A 20 RD 45 EMS 70 D11 95 BGH 21 BMS 46 EE 71 GND 96 PWDACK 22 DMS 47 ECLK 72 D12 97 0 23 5 48 ELOUT 73 D13 98 1 24 IOMS 49 ELIN 74 D14 99 A2 IAD1 25 CMS 50 EINT 75 D15 100 A3 IAD2 REV 29 ADSP 2185 ORDERING GUIDE Ambient Instruction Temperature Rate Package Package Part Number Range MHz Description Option ADSP 2185K ST 115 0 to 70 28 8 100 Lead TQFP ST 100 AD SP 2185BST 115 40 C to 85 C 28 8
40. le buff ered transmit and receive section SPORT s can use an external serial clock or generate their own serial clock internally SPORT s have independent framing for the receive and trans mit sections Sections run in a frameless mode or with frame synchronization signals internally or externally generated Frame sync signals are active high or inverted with either of two pulse widths and timings SPORT s support serial data word lengths from 3 to 16 bits and provide optional A law and u law companding according to CCITT recommendation G 711 SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer SPORT s can receive and transmit an entire circular buffer of data with only one overhead cycle per data word An interrupt is generated after a data buffer transfer SPORT 0 has a multichannel interface to selectively receive and transmit a 24 or 32 word time division multiplexed serial bitstream SPORT 1 can be configured to have two external interrupts IRQO and IRQ1 and the Flag and Flag Out signals T he internally generated serial clock may still be used in this con figuration PIN DESCRIPTIONS The ADSP 2185 will be available in a 100 lead T package In order to maintain maximum functionality and reduce pack age size and pin count some serial port programmable flag interrupt and external bus pins have dual multiplexed function ality T he external bus pin
41. lock signal TheCLKIN input cannot be halted changed during operation or operated below the specified frequency during normal opera tion T he only exception is while the processor is in the power down state For additional information refer to Chapter 9 ADSP 2100 Family User s M anual for detailed information on this power down feature If an external clock is used it should be T T L compatible signal running at half the instruction rate T he signal is con nected to the processor s CLKIN input When an external clock is used the XT AL input must be left unconnected REV 0 ADSP 2185 The ADSP 2185 uses an input clock with a frequency equal to half the instruction rate 16 67 M Hz input clock yields a 30 ns processor cycle which is equivalent to 33 M H z N ormally instructions are executed in a single processor cycle device timing is relative to the internal instruction clock rate which is indicated by the CLK OUT signal when enabled Because the AD SP 2185 includes an on chip oscillator circuit an external crystal may be used T he crystal should be con nected across the CLKIN and XTAL pins with two capacitors connected as shown in Figure 3 Capacitor values are dependent on crystal type and should be specified by the crystal manufac turer A parallel resonant fundamental frequency microproces sor grade crystal should be used A clock output CLK OUT signal is generated by the proces sor at the p
42. ow 0 5 tcx 5 ns w wait states x xMS PMS DMS CMS IOMS BMS CLKOUT A0 A13 _DMS PMS BMS IOMS MS RD Lge D WR Figure 17 Memory Read REV 0 20 ADSP 2185 Parameter Min Max Unit Memory Write Switching Characteristics tow Data Setup before WR High 0 5 tck 7 w ns toH Data H old after WR H igh 0 25 tex 2 ns twp WR Pulse Width 0 5 5 ns twoe WR Low to Data Enabled 0 ns tasw A0 A13 xMS Setup before WR Low 0 25 6 ns tppn Data Disable before WR or RD Low 0 25 7 ns tcwn CLKOUT Highto WRLow __ 0 25 tcx 5 0 25 7 ns taw A0 A13 xMS Setup before WR D easserted 0 75 tck 9 w ns twra A0 A13 xMS Hold after WR D easserted 0 25 tck 3 ns twwR WR High to RD or WR Low Q 5tck 5 ns w wait states x tcx xMS PMS DMS CMS IOMS BMS Figure 18 Memory Write REV 0 21 ADSP 2185 Parameter Min Max Unit Serial Ports Timing R equirements SCLK Period 50 ns tscs DR TFS RFS Setup before SCLK Low 4 ns DR TFS RFS Hold after SCLK Low 7 ns tscp SCLK y Width 20 ns Switching Characteristics tcc CLKOUT High to SCLK oyt 0 25 0 25 tc 10 ns SCLK High to DT Enable 0 ns tscpv SCLK High to DT Valid 15 ns tau TFS RF Sour Hold after SCLK High 0 ns tap TFS RF Sour Delay from SCLK High 15 ns tscpu DT Hold after SCLK High 0 ns TFS Alt to DT Enable 0 ns TFS Alt to DT Valid 14 ns SCLK
43. r Dissipation W Thermal Resistance ase to A mbient T hermal Resistance Junction to Ambient T hermal Resistance Junction to C ase Package Oca 50 C W 2 C W 48 C W POWER DISSIPATION determine total power dissipation in a specific application the following equation should be applied for each output C xV s xf load capacitance f output switching frequency Example In an application where external data memory is used and no other outputs are active power dissipation is calculated as follows A ssumptions External data memory is accessed every cycle with 5096 of the address pins switching External data memory writes occur every other cycle with 5096 of the data pins switching Each address and data pin has a 10 pF total load at the pin e Theapplication operates at Vpp 5 0 V and 30 ns Total Power Dissipation Pint x Vpp x f internal power dissipation from Power vs requency graph F igure 8 C x Vpp x f is calculated for each output of Pins x C Von xf Address DMS 8 x10pF x5 V 333 MHz 66 6 mW Data Output WR 9 x10pF x5 V 16 67 MHz 37 5 mW RD 1 x10 pF 52 x16 67MHz 4 2mW CLKOUT 1 x10 pF x5 V x33 3MHz 8 3 mW 116 6 mW otal power dissipation for this example is Pint 116 6 mW REV 0 440
44. re 16 352 words of memory accessible internally when the DM OVLAY register is set to 0 When DM OVLAY is set to something other than 0 external accesses occur at addresses 0x0000 through Ox1F FF he external address is generated as shown in T able III Tablelll DMOVLAY Memory 1 12 0 0 Internal Not Applicable N ot Applicable 1 External 13 LSBs of Address Overlay 1 0 Between 0x2000 and Ox3FFF 2 External 13 LSBs of Address Overlay 2 1 Between 0x2000 and Ox3FFF T his organization allows for two external 8K overlays using only the normal 14 address bits All internal accesses complete in one cycle Accesses to external memory are timed using the wait states specified by the DWAIT register Space Full Memory Mode The ADSP 2185 supports an additional external memory space called 1 space T his space is designed to support simple con nections to peripherals or to bus interface ASIC data registers 1 space supports 2048 locations T he lower eleven bits of the external address bus are used the upper three bits are unde fined T wo instructions were added to the core AD SP 2100 Family instruction set to read from and write to 1 0 memory space 1 0 space also has four dedicated 3 bit wait state registers IOWAIT 0 3 which specify up to seven wait states to be automatically generated for each of four regions T he wait states act on address ranges as shown in T able IV TablelV
45. representations REV 0 ADSP 2185 T he internal result bus connects the computational units so the output of any unit may be the input of any unit on the next cycle A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu tational units T he sequencer supports conditional jumps sub routine calls and returns in a single cycle With internal loop counters and loop stacks the AD SP 2185 executes looped code with zero overhead no explicit jump instructions are required to maintain loops T wo data address generators D AG s provide addresses for simultaneous dual operand fetches from data memory and pro gram memory Each DAG maintains and updates four address pointers Whenever the pointer is used to access data indirect addressing it is post modified by the value of one of four pos sible modify registers A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers Efficient data transfer is achieved with the use of five internal buses Program M emory Address PM A Bus Program M emory Data PM D Bus Data M emory Address DM A Bus Data M emory Data DM D Bus Result R Bus T hetwo address buses PM A and DM A share a single external address bus allowing memory to be expanded off chip and the two data buses PM D and DM D share a single external data bus Byte memory space and
46. rocessor s cycle rate T his can be enabled and disabled by the CLKODIS bit in the SPORT 0 Autobuffer Control Register CLKIN XTAL CLKOUT DSP Figure 3 External Crystal Connections Reset T he RESET signal initiates a master reset of the AD SP 2185 T he RESET signal must be asserted during the power up sequence to assure proper initialization RESET during initial power up must be held long enough to allow the internal clock to stabilize If RESET is activated any time after power up the clock continues to run and does not require stabilization time T he power up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid Vpp is applied to the processor and for the internal phase locked loop PLL to lock onto the specific crystal frequency A minimum of 2000 CLKIN cycles ensures that the PLL has locked but does not include the crystal oscillator start up time D uring this power up sequence the RESET signal should be held low On any subsequent resets the RESET signal must meet the mini mum pulse width specification The RESET input contains some hysteresis however if you use an RC circuit to generate your RESET signal the use of an external Schmidt trigger is recommended T he master reset sets all internal stack pointers to the empty stack condition masks all interrupts and clears the M ST AT register When RESET is released if there is no pending bus reque
47. s are configured during RESET only while serial port pins are software configurable during program execution Flag and interrupt functionality is retained concur rently on multiplexed pins In cases where pin functionality is reconfigurable the default state is shown in plain text alternate functionality is shown in italics 232 ADSP 2185 Common Mode Pins Input Pin of Name s Pins put Function RESET 1 Processor Reset Input BR 1 Bus Request Input BG 1 0 Bus Grant Output BGH 1 0 Bus Grant H ung Output DMS 1 Data Select Output PMS 1 Program emory Select Output TOMS 1 Memory Select O utput BMS 1 Byte Select Output CMS 1 0 Combined M emory Select Output RD 1 Memory Read Enable Output WR 1 Write Enable Output IRQ2 1 Level Sensitive Interrupt Request 1 0 I O Pin IRQLO 1 Level Sensitive Interrupt Requests 5 1 0 Programmable I O Pin IRQLI 1 Level Sensitive Interrupt R equests PF6 I O Programmable I O Pin IRQE 1 Edge Sensitive Interrupt equests PF4 1 0 Programmable I O Pin 1 Programmable I O Pin M ode C 1 ode Select Input C hecked only During RESET PF2 I O Programmable I O Pin During N ormal Operation M ode B 1 M ode Select Input C hecked only During RESET PF1 I O Programmable I O Pin During N ormal Operation M ode A 1 M ode Sele
48. s at address 0 TheADSP 2100 F amily development software Revision 5 02 and later fully supports the BDM A booting feature and can generate byte memory space compatible boot code TheIDLE instruction can also be used to allow the processor to hold off execution while booting continues through the M A interface For A accesses while ost M ode the ad dresses to boot memory must be constructed externally to the AD SP 2185 T he only memory address bit provided by the processor is 0 10 IDMA Port Booting TheADSP 2185 can also boot programs through its Internal DMA port If ModeC 21 ModeB 0 and M ode 1 the AD SP 2185 boots from the IDM A port IDM A feature can load as much on chip memory as desired Program execution is held off until on chip program memory location 0 is written to The ADSP 2100 F amily development software Revision 5 02 and later can generate ID M A compatible boot code Bus Request amp Bus Grant The ADSP 2185 can relinquish control of the data and address buses to an external device W hen the external device requires access to memory it asserts the bus request BR signal If the AD SP 2185 is not performing an external memory access it responds to the active BR input in the following processor cycle by Three stating the data and address buses and the PMS DMS BMS CMS IOMS RD WR output drivers Asserting the bus grant BG signal and Halting program execution
49. st and the chip is configured for booting the boot loading sequence is performed T he first instruction is fetched from on chip program memory location 0x0000 once boot loading completes REV 0 MEMORY ARCHITECTURE The ADSP 2185 provides a variety of memory and peripheral interface options T he key functional groups are Program M emory D ata Memory Byte M emory and 1 0 Program Memory is a 24 bit wide space for storing both instruction opcodes and data The ADSP 2185 has 16K words of Program M emory RAM on chip and the capability of access ing up to two 8K external memory overlay spaces using the external data bus Both an instruction opcode and a data value can be read from on chip program memory in a single cycle Data Memory is a 16 bit wide space used for the storage of data variables and for memory mapped control registers T he AD SP 2185 has 16K words on D ata M emory RAM on chip consisting of 16 352 user accessible locations and 32 memory mapped registers Support also exists for up to two 8K external memory overlay spaces through the external data bus Byte Memory Full Memory Mode provides access to an 8 bit wide memory space through the Byte DM A BDM A port T he Byte M emory interface provides access to 4 M B ytes of memory by utilizing eight data lines as additional address lines T his gives the BD M A Port an effective 22 bit address range On power up the D SP can automatically load bootstr
50. the processor s internal clock signal be slowed further reducing power consumption T he reduced clock frequency a program mable fraction of the normal clock rate is specified by a select able divisor given in the IDLE instruction T he format of the instruction is IDLE n where n 16 32 64 or 128 T his instruction keeps the proces sor fully functional but operating at the slower clock rate While itis in this state the processor s other internal clock signals such as SCLK CLKOUT and timer clock are reduced by the same ratio T he default form of the instruction when no clock divisor is given is the standard IDLE instruction When the IDLE n instruction is used it effectively slows down the processor s internal clock and thus its response time to in coming interrupts T he one cycle response time of the standard idle state is increased by n the clock divisor When an enabled interrupt is received the AD SP 2185 will remain in the idle state for up to a maximum of n processor cycles n 16 32 64 or 128 before resuming normal operation When theIDLE n instruction is used in systems that have an externally generated serial clock SCLK the serial clock rate may be faster than the processor s reduced internal clock rate U nder these conditions interrupts must not be generated at a faster rate than can be serviced due to the additional time the processor takes to come out of the idle state a maximum of n proc
51. the first 32 program memory words from the byte memory space Program execution is held off until all 32 words have been loaded Chip is configured in Full M emory M ode No Automatic boot opera tions occur Program execu tion starts at external memory location 0 Chip is config ured in Full M emory M ode BDMA can still be used but the processor does not auto matically use or wait for these operations BDMA feature is used to load the first 32 program memory words from the byte memory space Program execution is held off until all 32 words have been loaded Chip is configured in H ost M ode Additional interface hardware is required IDMA feature is used to load any internal memory as de sired Program execution is held off until internal pro gram memory location 0 is written to Chip is configured in Host M ode TheBDMA interface is set up during reset to the following de faults when BDM A booting is specified the BDIR BM PAGE BIAD and BEAD registers are set to 0 the BT YPE register is Set to 0 to specify program memory 24 bit words and the BWCOUNT register is set to 32 T his causes 32 words of on chip program memory to be loaded from byte memory T hese 32 words are used to set up the BDMA to load in the remaining program code T he BCR bit is also set to 1 which causes pro gram execution to be held off until all 32 words are loaded into on chip program memory Execution then begin
52. the pins D ata being read from a pin configured as an input is synchronized to the AD SP 2185 s clock Bits that are programmed as outputs will read the value being output The PF pins default to input during reset In addition to the programmable flags the AD SP 2185 has five fixed mode flags FLAG IN FLAG OUT FLO FL1 and FL2 FLO FL2 are dedicated output flags FLAG IN and FLAG OUT are available as an alternate configuration of SPORT 1 Note Pins PFO PF 1 and PF2 are also used for device configu ration during reset REV 0 ADSP 2185 BIASED ROUNDING A mode is available on the AD SP 2185 to allow biased round ing in addition to the normal unbiased rounding When the BIASRND bit is set to 0 the normal unbiased rounding opera tions occur When the BIASRND bit is set to 1 biased round ing occurs instead of the normal unbiased rounding When operating in biased rounding mode all rounding operations with M RO set to 0x8000 will round up rather than only rounding up odd M R1 values For example Table VII MR Value Biased Unbiased Before RND RND Result RND Result 00 0000 8000 00 0001 8000 00 0000 8001 00 0001 8001 00 0000 7FFF 00 0001 7FFF 00 0001 8000 00 0002 8000 00 0001 8001 00 0002 8001 00 0000 7FFF 00 0001 7FFF 00 0000 8000 00 0002 8000 00 0001 8001 00 0002 8001 00 0000 7FFF 00 0001 7FFF T his mode only has an effect when the M RO register contains 0x8000 all other rounding oper
53. to processor memory space during a single instruction cycle 1 0 Space Instructions T he instructions used to access the AD 5 2185 5 1 0 memory space are as follows Syntax addr dreg dreg 10 addr where addr is an address value between 0 and 2047 and dreg is any of the 16 data registers Examples 10 23 AR1 10 17 Description Thel O space read and write instructions move data between the data registers and the 1 0 memory space DESIGNING AN EZ ICE SYSTEM The ADSP 2185 has on chip emulation support and an ICE Port a special set of pins that interface to the EZ ICE T hese features allow in circuit emulation without replacing the target system processor by using only a 14 pin connection from the target system to the EZ ICE T arget systems must have a 14 pin connector to accept the EZ ICE s in circuit probe a 14 pin plug See the ADSP 2100 Family EZ Tools data sheet for complete information on ICE products ThelCE Port interface consists of the following AD SP 2185 pins EBR EBG ERESET EMS EINT ECLK ELIN ELOUT EE hese AD SP 2185 pins must be connected only to the EZ ICE connector in the target system T hese pins have no function except during emulation and do not require pull up or pull down resistors T he traces for these signals between the AD SP 2185 and the connector must be kept as short as possible no longer than three inches
54. to when the output has reached a specified high or low trip point as shown in the Output Enable D isable diagram If multiple pins such as the data bus are enabled the measurement value is that of the first pin to start driving REFERENCE SIGNAL Von MEASURED Von MEASURED MEASURED 0 5V 2 0V OUTPUT VoL MEASURED 0 5V VoL VoL a t MEASURED DECAY MEASURED OUTPUT STARTS ENG DRIVING HIGH IMPEDANCE STATE TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1 5V Figure 12 Output Enable Disable lo OUTPUT 1 5V PIN Figure 13 Equivalent Device Loading for AC Measure ments Including All Fixtures REV 0 ADSP 2185 TIMING PARAMETERS Parameter Min Max Unit Clock Signals and Reset Timing R equirenents tci CLKIN Period 60 150 ns CLKIN Width Low 20 ns CLKIN Width High 20 ns Switching Characteristics CLKOUT Width Low 0 5 7 ns CLKOUT Width High 0 5 tc 7 ns CLKIN High to CLKOUT High 0 20 ns Control Signals Timing R equirements tasp RESET Width Low 5 tex ns tus M ode Setup Before RESET High 2 ns Setup After RESET High 5 ns NOTE 1A pplies after power up sequence is complete Internal phase lock loop requires more than 2000 cycles assuming stable not including crystal oscillator start up time CLKIN CLKOUT PF 2 0 PF2 IS M
55. ue opera tions Setting the BCR bit to 1 causes the processor to stop execution while the accesses are occurring to clear the context of the processor and to start execution at address 0 when the BDM A accesses have completed Internal Memory DMA Port IDMA Port Host Memory Mode ThelDMA Port provides an efficient means of communication between a host system and the AD SP 2185 T he port is used to access the on chip program memory and data memory of the DSP with only one D SP cycle per word overhead IDM A port cannot however be used to write to the DSP s memory mapped control registers ThelDMA port has a 16 bit multiplexed address and data bus and supports 24 bit program memory T IDM A port is com pletely asynchronous and can be written to while the AD SP 2185 is operating at full speed T he D SP memory address is latched and then automatically incremented after each IDM A transaction An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block T his in creases throughput as the address does not have to be sent for each memory access IDMA Port access occurs in two phases he first is the IDM A Address Latch cycle When the acknowledge is asserted a 14 bit address and 1 bit destination type can be driven onto the bus by an external device T he address specifies an on chip memory location the destination type specifies wheth
56. ulation can be supported in final board designs trademarks are the property of their respective holders EZ ICE and SoundPORT are registered trademarks of Analog D evices Inc 2 92 T he EZ ICE performs a full range of functions including e n target operation e Up to 20 breakpoints Single step or full speed operation Registers and memory values can be examined and altered PC upload and download functions e nstruction level emulation of program booting and execution Complete assembly and disassembly of instructions C source level debugging See Designing An EZ ICE9 Compatible T arget System in the ADSP 2100 Family EZ Tools M anual AD SP 2181 sections as well as the T arget Board Connector for EZ ICE Probe sec tion of this data sheet for the exact specifications of the EZ I CE9 target board connector Additional Information T his data sheet provides a general overview of ADSP 2185 functionality For additional information on the architecture and instruction set of the processor refer to the ADSP 2100 F amily User s M anual For more information about the development tools refer to the ADSP 2100 Family D evelopment T ools D ata Sheet ARCHITECTURE OVERVIEW TheADSP 2185 instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions E very instruction can be executed in a single pro cessor cycle T he AD SP 2185 assembly language uses an
57. ures proprietary ESD protection circuitry to dissipate high energy discharges Human Body per method 3015 of MIL ST D 883 Proper ESD precautions recom WARNING ESD SENSITIVE DEVICE mended to avoid performance degradation or loss of functionality U nused devices must be stored in conductive foam or shunts and the foam should be discharged to the destination before devices are removed ADSP 2185 TIMING PARAMETERS GENERAL NOTES Use the exact timing information given D o not attempt to derive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases C onsequently you cannot meaningfully add up parameters to derive longer times TIMING NOTES Switching characteristics specify how the processor changes its signals Y ou have no control over this timing circuitry external to the processor must be designed for compatibility with these signal characteristics Switching characteristics tell you what the processor will do in a given circumstance Y ou can also use switching characteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied T iming requirements apply to signals that are controlled by circuitry external to the processor such as the data input for a read operation T

ADSP-2185 DSP Microcomputer

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