TQM8xxL Hardware Manual - TQ
Contents
1. 4 iux lax eu apaissonar uppupusq nz purs USUOYD 20p 00 0 T1XX8INO L sjueuoduio2 O L Aq Sunu 2004 by TQ Components GmbH TQM8xxL HWM 0300 doc OOP dS 185 PT ansfunuuprez 4 00 20 95 PRENDL 10 ansa ret mu lt sug nz Buss purs usuotipuuoju WSBIP u Sig 1 1 TEE ToT aec oot wo Loo Sq TT 99293559295299229859 8585359333353 8 usis g 1 Sunu unn I I I r4 I T spod Waa n 002092 PAR2. peal aid n 7 Illustration 7 8 Refresh and Exception CAN 7 2 Tools 7 2 1 Starter Kit STK8xxL Illustration 7 9 Starter Kit The STK8xxL can be procured from your sales partner All modules of the family 8 and TQM8xxM can be used with the STK8xxL starter kit The scope of delivery includes Adaptor Download cable Manuals Diverse Tool CDs la components The following types are available ex stock STK855L AA STK855L AB STK860L AA STK860L AB Starter kit STK8xxL with module TQM855LDBOA3 T80 Starter kit STK8xxL with module TQM855LDBOA3 T50 Starter kit STK8xxL with module TQM860LDBOA3 P80 Starter kit STK8xxL with module TQM860LDBOAS P50 XPC855TZP80 8MB Flash 16MB SDRAM No CAN With regulator With RS232 driver 80MHz Clock Temperature range 0 XPC855TZP50 8MB Flash 16MB SDRAM No CAN With regulator With RS232 driver 50MHz Clock Temperature range 0 XPC860PZP80 8MB Flash 16MB SDRAM no CAN with regulator with RS232 driver 80MHz Clock Temperature range 0 XPC860PZP50 8MB Flash 16MB SDRAM No CAN With regulator With RS232 driver 50MHz Clock Temperature range 0 70 C 70 C 70 70 sjueuoduio2 D L Aq 70078 20 0060 TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ
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4. to the embedded world 8 Hardware Manual la components 1 About This Manual This document encompasses the technical features of various Microcontroller modules of the TQM8xxL family The name MPC860 is often used synonymously for all Microcontrollers of the MPC8xx family Similarly TQM860L refers in most cases to all variants listed in Illustration 4 1 Variant Codes sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 1 1 0 components Terms and Conventions Symbol Tag Description This symbol represents the handling of electrostatic sensitive modules and or components These components are often damaged destroyed with the transmission of a voltage higher than about 50V Human body usually notices electrostatic discharges only above approximately 3 000V This symbol indicates the possible use of voltages greater than 24V Please note the relevant statutory regulations in this regard Non compliance with these regulations can lead to serious damage to your health and also cause damage destruction of the component This symbol indicates the possible source of danger Acting against the procedure described can lead to possible damage to your health and or cause damage destruction of the material used This symbol represents important details or aspects for working with TQ products Filenam
5. sjueuoduio2 D L Aq 70078 20 0060 TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH burst write offset 20 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA set set set set set set set set set DATA set set DATA set set set OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 01 0 4 000002120 OEEABBCOO 000002121 010 77 00 000002122 000002123 000002124 OEIBAFCOA 000002125 OlFF5FCA7 000002126 refresh offset 30 in UPMA RAM DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA exception offset 3c in UPMA RAM set set set set set DATA set set DATA set set set set set OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 O1FFD7C84 000002130 OFFFFFCOA 000002131 OFFFFFCOA 000
6. Pin Signal name Type Function 6 ENMON Switchover Monitor normal boot procedure 3 SMTXD1 TxD of the debugging interface SMC1 RS232 level 5 GND Ground 1 RESIN Reset input Master reset of the reset module 2 SMRXD1 RxD of the debugging interface SMC1 5232 level on the starter kit STK8xxL Illustration 3 20 Signals of the download interface la components The switchover signal ENMON is implemented on the module by means of the port lead PA15 and a discretely built CMOS switch This opens during the Reset phase so that a high impedance coupling of the port lead with ENMON becomes effective After the reset phase the CMOS switch closes the port lead with low impedance with a time delay of about 10 ms As a result of this the CPU has sufficient time to evaluate the level of the reset phase 3 1 6 3 Interface All leads of the Freescale BDM Interface Debugging Interface are brought out externally As in the case of the TQS Download Interface the leads of the BDM Interface are brought out exclusively to the connector of the motherboard It consist as of the following signals Pin Signal name Type Function 1 FRZ VFSLO Freeze CPU history buffer status 2 SRESET Soft reset 3 DGND Ground 4 DSCK TCK Clock 5 DGND Ground 6 FRZ VFLS1 0 Freeze CPU history buffer status 7 HRESET 8 DSDI T
7. Illustration 3 1 Block Diagram 3 1 2 System Components 7 CPU 8 Oscillator for the CPU Oscillator for the RTC Power fail Logic DC DC converter SDRAM Flash 2 Full CAN 2 0 B active controller 2 RS232 serial driver for SMC1 and SMC2 BDM JTAG Interface Board to Board connector system 240 Pins lead wire spacing 0 8 mm sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 3 1 2 1 CPU The module has been developed for the MPC860 however even an MPC855 MPC850 or MPC823 can be used Subject to adequate product qualification future derivatives could also be used as long as they are functionally compatible with the MPC860 The addresses for the control of the SDRAMs are multiplexed ote internally Hence an external bus master can not be connected H n to the bus e g PCI bridge Multiprocessor system 3 1 2 2 Permanent Memory Flash 16 bit 3 3V Flashes with BGA packages are used These are controlled directly by the CPU without a driver buffer 4to8MB e 2 banks with 32 bit e Access time 90ns e Signals used CS_FLASHO CS0 bootable and if available CS_FLASH1 CS1 OE GPL_AB1 WEO BS_BO WE2 BS_B2 e Control via GPCM recommended timing ACS 00 TRLX 0 CSNT 1 SCY 4 EHTR 1 Normal operation ACS 11 TRLX 1 CSNT 1 SCY 15 EHTR 0 Boot m
8. o BO Enable 0 pik B1 Enable 1 wp eurem mm B2 Enable 2 B3 Enable 3 CS_FLAS C3 Chip Select 0 Flash Boot 1 71 HO Chip Select CSO A2 CS_FLAS Chip Select 1 Flash X1 70 CS1 CS_SDRA Chip Select 2 SDRAM X1 69 MO CS2 CS3 CS4 A4 4 50X67 55 B4 ChipSelectS 50 1 66 ree 2 pe _B 1 Slot B iad e p _B 2 Slot B A jCardEnable 1SlotA 50 X1 54 Card Enable 2 50 Xt 55 OEZ GPL C6 Output Enable General 10 X1 e AP for SDRAM and FLASH General Purpose Line A2 3 X1 74 B2 used for SDRAM and General Purpose Line A3 40 X1 75 B3 used for SDRAM EB Me l Line AO m 72 von i GPL_A4 Purpose Line A4 used for CAN GPL_B4 Purpose Line B4 42 sjueuoduio2 D L Aq 90p 00 0 1XX8NOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH It components Signal No of Type Description Ext Load Module Pin Pins Cap max PF GPL_A5 General Purpose Line A5 45 1 62 used for rt Address Strobe Pull Up X2 69 4k7 BADDR28 M3 O Burst Address 28 X2 ss o BADDR29 O Burst Address 29 50 ____ 2 67 BADDR30 K4 Burst Address 30 Register 50 X2 66 REG PCMCIA WAIT_A R3 Wait Slot
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10. Module connector Pin Assignment Mechanical Specification General Information sjueuoduio2 D L Aq 70029 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH Dimensions Connector Tips on handling Variant codes Environmental Conditions Climatic Conditions and Areas of Application Installation Instructions Reliability and Life span Product Qualification Mechanical Environmental Influences Temperature Tests EMI EMC EMC Passive Radiation ESD UL Approval Safety requirements and Personnel Protection EMI EMC Requirements ESD Requirements Operational Safety and Personnel Protection Annexure Software Support Monitor Software Configuration of the SDRAMs Configuration of the CAN Controller Tools Starter Kit STK8xxL Module Extraction Tool MOZI8xxL Circuit Diagrams Starter Kit FETH8xxL Literature la components 48 50 50 51 53 53 53 53 53 53 54 54 54 54 54 54 54 55 55 56 56 56 57 62 65 65 67 68 68 75 77 la components 1 3 List of Figures Table Overview Illustration 1 1 Terminology nennen nnne nnne 7 Illustration 1 2 Revision 9 Illustration 2 1 8 10 Illustration 2 2 The Tera Term Serial Port dialog box is di
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12. 35 Illustration 3 16 Current Consumption from 5V 35 Illustration 3 17 Total Consumption at 5 36 Illustration 3 18 Battery 36 Illustration 3 19 Driver structure of the RS232 interfaces 37 Illustration 3 20 Signals of the download interface 37 Illustration 3 21 Signals of the 38 Illustration 3 22 Pin enne nnn 47 Illustration 3 23 of the 49 Illustration 3 24 PCB heights not to 49 Illustration 3 25 Overview of 50 Illustration 4 1 Variant 51 Illustration 4 2 Standard Types of 52 Illustration 7 1 Initializing 60 Illustration 7 2 Single read Burst read 61 Illustration 7 3 Single write and burst write SDRAM sse 61 Illustration 7 4 Refresh and Exception 62 Illustration 7 5 Configuration of
13. CAN Controllers 63 Illustration 7 6 Single read and burst read 64 Illustration 7 7 Single write and burst write 64 Illustration 7 8 Refresh and Exception 65 Illustration 7 9 Starter Kit acetic alas anna 65 Illustration 7 10 Standard types of the starter kit 67 Illustration 7 11 Module Extraction 67 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 1 4 Acronyms and Definitions The following terminology and abbreviations are used Acronym Full Form BDM Background Debug Mode CPU Central Processing Unit CAN Controller Area Network EEPROM an Programmable Read Only Memory Byte EMI EMC Electro Magnetic Interference Electro Magnetic Flash Electrically Erasable Programmable Read Only Memory Block Erase JTAG Joint Test Action Group MCU Memory Control Unit RTC Real Time Clock SDRAM Synchronous Dynamic Random Access Memory SMD Surface Mounted Device Illustration 1 1 Terminology 1 5 Tips on Safety Improper or incorrect handling of the product can substantially reduce its life span la components 1 6 Handling ESD Ti
14. JTAG BDM signal Illustration 3 9 Reset Configuration m la components 3 1 4 2 Reset Logic Since it is critical to maintain the reset thresholds components with low tolerances must be used accordingly and a step for calibrating this must be incorporated in the module test e Voltage monitoring for 33 V CPU memory other logic matching with a fixed resistance which if required is removed during test e Voltage monitoring for 5 V CAN controller e External Reset input e Reset status displayed using LED lights up if SRESET low The tolerances of the supply voltages and supervisory thresholds are displayed for each voltage in an appropriate diagram 3 1 4 2 1 Tolerances and Reset Thresholds for VCC3V3 The tolerance for the external power supply Pos A refer also to Illustration 3 12 VCC3V3 3 3 V 2 727 5 3 210 3 465 V The tolerance for the internal power supply regulator Pos B refer also to Illustration 3 12 VCC3V3 3 238 3 446 V standard temperature range MAX651CSA VCC3V3 3 222 3 463 V extended temperature range MAX651ESA The permissible operational range for the CPU and 3 3V logic Pos C refer also to Illustration 3 12 VCC3V3 3 3 5 3 135 3 465 V Tolerance of the supervisor circuit standard temperature range MAX816CSA Ureset Matching resistance fitted 3 161 E 3 287 V Ureset matching resistance removed 3 079 3 199 V Tolerance of the su
15. M WAT X RUE REM NEM ANE NAI o eo 9 o 76 TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 7 4 Literature 1 2 3 4 5 6 7 8 9 10 11 12 860 PowerQUICC User s Manual MPC860UM AD Rev 1 07 98 Errata to MPC860 PowerQUICC User s Manual Rev 1 MPC860UMAD D Rev 2 6 2001 MPC855T User s Manual Integrated Communications Microprocessor MPC855TUM D Rev 0 2 2001 AM29LV160D 16 Megabit 2 M x 8 bit 1 M x 16 Bit CMOS 3 0 Volt only Boot Sector Flash Memory Publication 22358 Rev A Amendment 1 Issue Date April 19 1999 256 MB x4 x8 x16 SDRAM 256MSDRAM C p65 Rev C Pub 4 01 82527 Serial Communications Controller Controller Area Network Protocol Order Number 272250 006 December 1995 Intel 1999 Packaging Data handbook MAX3222 MAX3232 MAX3237 MAX3241 3 0V to 5 5V Low power up to 1Mbps True RS 232 Transceivers Using Four 0 1uF External Capacitors 19 0273 Rev 5 3 99 MAX814 MAX815 MAX816 1 Accuracy Low power 3V and 5V uP Supervisory Circuits 19 0412 Rev 0 6 95 Anla Technology Co Ltd EMC EMI Component SMD Product Specification 108 5390 AMP FH 0 8 mm Pitch board to board connector AMP J 552 Rev Mar 91 Life cycle and reliability calculation Working instructions QMAA0704A05 Rev 109 TQ Systems GmbH
16. Voltage VCC3V3 Ripple Supply Output current Current external supply max current max regulator max capacity 3 210 3 465 40mV 548 670 Determined by value Guaranteed voltage range of the worst case current worst case consumption components and the foreseen supervisor threshold Illustration 3 13 3 3V Supply m la components 3 1 5 2 1 Current Consumption at 3 3V Current Current Current consumption consumption consumption Component Type 50 MHz 66 MHz 80 MHz max 4 201 160 write 3 2 MT48LC16M16A2TG 75 160 mA cont burst all banks active 100 MHz 5 MAX3222CAP 115 3 kW 1000 pF ly 8 wes mews oai duo2 p3 d 9 Hqu nsjueuo Illustration 3 14 Current consumption at 3 3V All values are valid in worst case scenarios 3 1 5 3 Regulator for 3 3 V This option must be selected only if there is no external 3 3V power supply available for the module A DC DC converter generates the operational voltage of 3 3 V from the external power supply 5 V for the CPU and all other 3 3 V modules e Current mode regulator with recovery diode e Conversion 5V gt 3 3 V e Design only for the module no external loads permissible e lout max 670 mA Variable Switching frequency 50 120 kHz Low ESR Tantalu
17. at 5V 3 1 5 7 Battery Buffering The design includes buffering of the RTC integrated in the CPU Current consumption 66 MHz max mA 150 512 662 Current consumption 80 MHz max mA 150 452 602 VBAT Voltage 20 3 6V Current Drawn 10 pA 20 mA Maximum Value Worst Case Illustration 3 18 Battery Buffering note This value is applicable to CPUs with the RTC Bug e g MPC860 up to and including C1 mask Information about the current mask versions is given Freescale in the Errata sheets of 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8WOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 3 1 6 Interfaces 3 1 6 1 Serial Interfaces Two internal UARTs Max 115200 Baud e Driver with RS232 compatible levels e All signals available even without the driver Standard configuration Driver 2 RxD TxD Illustration 3 19 Driver structure of the RS232 interfaces 3 1 6 2 Download Interface RxD and TxD e Reset via the RS232 interface RESIN e Additional input lead of 5232 ENMON can be read from the Port pin The Download Interface is an extension of the serial interface for control purposes It consists of five signals which are only available on the connector of the motherboard On the starter kit STK8xxL they are combined with the connector for SMC1
18. cm e Connect maximum one module e A series resistance directly on the connector typically 33 can improve the signal quality All these constraints can be overcome with the use of an external buffer In order to maintain synchronism with CLKOUT use of a zero delay buffer is recommended e g CY2305SC 1 Cypress note 3 1 3 2 RTC Pulse The oscillator integrated in the CPU generates the RTC clock pulse of 32 768 kHz with the help of external quartz This is used for the operation of the integrated RTC During start up of the 8 this is used as the reference clock pulse in order to determine the clock frequency of the CPU Tolerance of the RTC Pulse Nominal Output Tolerance Frequency Temperature Frequency coefficient change with Max shock max 0 04 ppm C 5 ppm 32 768 kHz Illustration 3 7 Tolerance RTC Pulse 50 ppm With certain CPU variants and masks an error of the CPU leads to a substantially increased consumption from VBAT if the main supply is switched off Please refer to the corresponding Errata sheets of Freescale note 7 sjueuoduio2 D L Aq 30P 00E0 WMH TIXX8WOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 3 1 3 3 CAN Pulse The oscillator integrated in the first CAN controller generates a clock pulse of 16 MHz with the help of external quartz The second controller derives it
19. following figure refer to blocked areas which should be kept free in the motherboard for the extraction tool MOZI8xxL The blocked areas are symmetric The positions shown are those in plugged in condition right and during plug in left 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH ni uiuit 0 components X1 X2 N Illustration 3 23 Top view of the PCB N l 77 ____ 77 7 Xt Vdd Illustration 3 24 PCB heights not to scale au Value mm Remarks a 5 0 0 2 Combination of module connector with counter part with other connectors on the motherboard even 6 7 and 8 mm are possible b 1 5 0 15 Printed Circuit Board 3 5 0 5 Memory choke 10 maximum height on the top side d 2 35 max CAN controller 7 maximum height on the bottom side la components 3 2 3 Connector Board to Board Module Distance Base Board Connector No of Qty Supplier Order No No of Supplier Order No Pins Pins 5mm 120 2 AMP 177983 5 120 AMP Berg 177984 5 61083 Berg 61082 121000 121000 6mm 120 AMP Berg 5 179029 5 61083 122000 7mm 120 AMP Berg 5 179030 5 61083 123000 8mm
20. necessary te I In order to avoid conflicts with the Reset configuration buffers with Bus Hold may not be used Internal External Address Internal Address Internal Flash SDRAM Driver CPU Driver if required Data Internal Data Internal Flash SDRAM Illustration 3 5 Bus Structure 3 1 3 1 CPU Clock The CPU clock is generated with an oscillator and multiplied if required The settings required for this are selected using the reset configuration word refer to Specification MON8xx without anything to be done in the hardware The tolerances include the output tolerance as also the frequency changes owing to temperature variation of the supply voltage ageing shock and vibration la components pens Oscillator Multiplication pisi Me T MHz zZ external bus external bus 50 100 ppm 50 100 ppm 1 1 50 100 ppm 80 100 ppm 16 100 ppm 5 2 40 100 ppm Illustration 3 6 Clock frequencies The central clock signal of the module is CLKOUT external bus clock The total timing of the 860 is synchronous with this signal It is also used to control the SDRAMs and is brought out on the wire strip Since the signal is not buffered on the module itself it must be handled with care and diligence on the baseboards so that there are no repercussions on the module SDRAMs e Very short lead lengths max 4
21. 0 8153 9308 134 Email info tqc de Web http www tq components com 1 9 Copyright Copyright protected 2004 by TQ Components GmbH This handbook may not be copied reproduced translated restructured or distributed either in whole or in part in electronic machine readable or other form without the explicit written consent of TQ Components GmbH 1 10 Limited Liability The TQ Components GmbH does not take over any guarantee for the currentness correctness or quality of the information provided in this manual as also its further use Claims lodged against TQ Components GmbH related to damages of material or intellectual nature arising out of the use or non use of information contained in this manual or out of the use of incorrect or incomplete information would not be entertained so long as there is no evidence of intentional or negligent fault on the part of TQ Components GmbH The TQ Components GmbH reserves the right to change or amend the contents of this manual or parts thereof without prior notice 1 11 Revision History Revision Version History Created Approved Rev Modification Date Cipher Date Cipher 300 Creation 2004 11 24 NIS 2004 12 06 ANW Illustration 1 2 Revision History la components 2 Introduction The TQM8xxL is a universal Minimodule equipped with the PowerPC CPU MPC8xx of Freescale Semiconductor dimension is 40x54 mm approximatel
22. 002132 OFFFFFCOA 000002133 OFFFFFC84 000002134 OFFFFFCO7 000002135 VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY DATA set OFFF0017C LONG O7FFFFCO7 VERIFY DATA set OFFF00168 LONG 00000213C VERIFY 0 components initialise machine mode a Register MAMR It components DATA set OFFF00170 LONG 0C3802114 VERIFY initialise memory periodic timer pre scaler MPTPR Preliminary pre scaler for refresh depends on number of banks This value is selected for four cycles every 62 4 us with two SDRAM banks or four Cycles every 31 2 us with one bank It will be adjusted after memory sizing DATA set OFFF0017A WORD 01000 VERIFY initialise memory address register MAR DATA set OFFF00164 LONG 000000088 VERIFY precharge all execute commands via Memory Command Register at Patch Offset 5 immediately thereafter from Patch Offset 7 the SDRAM Initialization is done Banks 0 and 1 DATA set OFFF00168 LONG 080004105 VERIFY DATA set OFFF00168 LONG 080006105 VERIFY 2x 4 times Refresh via Memory Command Register execute at Patch Offset 30 DATA set OFFF00168 LONG 080004130 VERIFY DATA set 0168 LONG 080004130 VERIFY DATA set 0168 LONG 080006130 V
23. 120 AMP Berg 5 179031 5 61083 124000 Illustration 3 25 Overview of Connector 3 2 4 Tips on handling To ensure elegant removal plug out of the module from the motherboard making use of the extraction tool MOZI8xxL which is supplied along with the starter kit is mandatory 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 4 Variant codes TQM a1 L v x 2 2 b t t Temperaturbereich blank 0 C 70 C 40 C 85 C b CPU Clock 50 50MHz 66 66MHz 80 80MHz a2 Microprozessor Derivat DE DEZP P PZP SR SRZP T TZP z Optionale Best ckung 0 ohne Optionen 1 mit Schaltregler 2 mit RS232 Treiber y Steckerbauh he A 5mm x CAN Ausstattung 0 ohne CAN Ausstattung 1 1 Controller best ckt 2 1 und 2 Controller best ckt w SDRAM Ausstattung B 16MByte C 32MByte D 64MByte E 128MByte v Flash Ausstattung C AMByte D 8MByte a1 Mikroprozessor Version 823 XPC823 850 XPC850 855 XPC855 860 XPC860 862 XPC862 Illustration 4 1 Variant Codes la components The following types are available ex stock TQM855L AA TQM855L AB TQM860L AA TQM860L AB TQM860L AD TQM862L AA TQM855LDBOA3 T80 XPC855TZP80 8MB Flash 16MB SDRAM kein CAN mit Schaltregler mit RS232
24. 5 10 4 5 5 5 V The minimum value of the lower operational voltage limit appears tolerable Matching is not necessary here 4 792 5V 4 160 5 5 5V power supply 4 488 4 792V Supervisor circuit 4 5V 5V 10 5 5V 3 1 4 2 3 External Reset Input The RESIN signal provides a debounced type low active reset input In order to prevent any backlash to the driver connected this signal should be driven actively only to the ground e g Open Collector Open Drain output push button towards ground or decoupling by means of a diode For this the Low level of the signals MR must be maintained as per the data sheet of the MAX816 9 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 3 1 5 Power Supply with different possibilities of the supply 3 1 5 1 Possibilities of Power Supply The power supply of the module is structured as follows Q gt VCC 5V CAN Controller 5V 5V VCC 3V3 3 3V Illustration 3 12 Structure of the power supply Depending on the module variant the following possibilities are available for supplying power to the module e With CAN controller Input voltage 5 V or 5 V and 3 3 V separate e Without CAN controller Input voltage 5 V or 3 3 V With only a 5V supply one has to use a DC DC converter from 5 V to 3 3 V 3 1 5 2 3 3V Supply
25. A Pull Up 4k7 X1 10 ALE_A K2 Address Latch Enable 50 1 11 Pull Up 4k7 T5 I InputPortA0 Pull Up 4k7 50 __ 1 12 IP A1 T4 I InputPortAt Pull Up 4k7 50 ___ 1 13 IAS 0 _______ Port A2 PullUp AKT 50 XI Input Port Pull UP 4k7 Va Port Pul Up ak s0 xi te 5 US 1 InputPortA5 Pull Up 4k7 50 ___ 1 17 A6 6 1 InputPortA6 Pull Up 4k7 0 X1 18 A7 T3 Input Port A7 Pul Up4k7 50 ___ 19 WAIT B Pul Up4k7 _ 50 1 24 a 50 buffer status 0 Pull Up 4k7 IP B1 VFL J3 Input Port B1 CPU history 50 X1 32 Sie 2 J2 I __ B2 Pull Up 4k7 50 X1 31 Bort Pulp ak feo Xt29 IP_B4 G2 Input Port Pull Up 4k7 50 X1 29 B5 J4 Input Port 5 Pull Up 4k7 50 1 28 IP B6 K3 Input Port B6 Pull Up 4k7_ 50 1 27 _ 7 H1 Input Port B7 Pul Up 4k7_ 50 1 26 t4 O Output Port 0 X12 __ 12 O _ Output Port 1 50 ____ 1 20 OP2 MOD L1 Port 2 Mode Clock 45 X1 22 CK1 OP3 MOD LAN output Port 3 Mode Clock X1 23 CK2 0 components Signal No of Type Description Ext Load Module Pin Pins Cap max pF Other CPU u Carrier Receive Sense Spare 1 Managem
26. AS 10 SA E L as SLT oo erin Pi odd aos LEE rer 1 OR T woos a en Pian 1 NEA T goss Ir or TC Piz 1 E gos BSL quesos T woos SL satan Toon PAREA T St real 565 6 wise nz BUBI purs WSBIP u 97 Phu mu 8505 679 XOU 7 SPI ter 7 ame goss gnat 505 EIA T 1 1 asmia uos on Par TOSS PAR 5 Io 5 2 i i a El H i ons Poon 5815057 6 hi 3 5 5 r OT 3 5 z E 3 90p 00 0 WMH 1XX8INO L 01 0020 2004 by TQ Components GmbH TQM8xxL HWM 0300 doc OOt dS I Xe s ausfunuuprez 951 G91 00 20792 PARIS 10 BG Quod NES woos HR et 30 non ea e lt
27. Components GmbH la components STK860L AD Starter kit STK8xxL with XPC860PZP50 module TQM860LDDBA3 8MB Flash P50 64 SDRAM CAN Controller 1 and 2 fitted With regulator With RS232 driver 50MHz Clock Temperature range 0 C 70 C STK862L AA Starter kit STK8xxL with XPC860SRZP80 module TQM862LDBOA3 8MB Flash SR80 16MB SDRAM No CAN With regulator With RS232 driver 80MHz Clock Temperature range 0 70 Illustration 7 10 Standard types of the starter kit 7 2 2 Module Extraction Tool MOZI8xxL Illustration 7 11 Module Extraction Tool To ensure elegant removal plug out of the module from the motherboard making use of the extraction tool MOZI8xxL which is supplied along with the starter kit is mandatory The MOZI8xxL can be procured from your sales partner ircuit Diagrams Starter Ki 73 7 3 1 2004 by TQ Components GmbH TQM8xxL HWM 0300 doc I I 3 I 002022 66 60 LzDuv TOR 662701 6609 004095 oor 10 9018 Sunwsusg unpa CELNI 53910509853 on TED FIX yx 2 8588488588 5999999989989 uj
28. DI Data input 9 VCC3V3 Power Supply 10 DSDO TDO Data output on Starter kit STK8xxL i alternative assignment in brackets Illustration 3 21 Signals of the BDM interface 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 3 1 7 Module connector 3 1 7 1 Pin Assignment e 32 Bit data bus e 32 Bit address bus e All port pins Signal No of Description Ext Load Module Pin Pins Cap max pF Address Bus IO TS Address A7 D15 iO TS Address AS oo A10 B15 IIO TS Address A10 10 X1 101 A13 B14 TS Address A13 20 X1 98 TS Address A14 A18 09 0 Address A18 __ 10 __ 1 93 0 components Signal No of Type Description Ext Load Module Pin Pins Cap max PF A31 Address A31 LSB Data Bus DO Wf4 1 0 TS Data 00 MSB X288 D1 W12 TS Data 01 gb X2 89 D2 W11 TS Data 02 9 X2 90 03 W10 TS 04 ____ W13 TS DataD4 9 292 05 W9 TS Data D5 9 X2 93 06 w7 15 DataD6 9 X X294 08 U13 15 25 X296 09 T11 O TS DataD9 _ 125 2 97 D16 U10 TS Data 016 30 X2 104 D19 U TS Data 019 30 X2 107 V D21 O 30 X2 109 231 T7 0 TS Data 031 L
29. ERIFY DATA set OFFF00168 LONG 080006130 VERIFY Illustration 7 1 Initializing SDRAM The following access types result therefrom Single read and burst read sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH Wave Editor CLKOUT GCLKI Illustration 7 2 Single read Burst read SDRAM 0 components ail Single write and burst write Wave Editor CLKOUT GCLKI 1515 NA NU _ ML m u A _ b iE T nm 1515 LIL U UU UU UU UU LI LU UL sam Xcol1 sam Illustration 7 3 Single write and burst write SDRAM m la components CLKOUT GCLKI sam X col 1 sam col 1 NA V ist aid 13 7 Illustration 7 4 Refresh and Exception SDRAM 7 1 3 Configuration of the CAN Controller In this example of control CMM file for Lauterbach debugger both the CAN controllers are configured for the address 0xC0000000 To achieve this the register of the memory controller the sequencer table of the UPM and the CAN controllers are configu
30. Edit Setup Control Window Help E8812A0000A16A0004E9 S 32500020E201D2903E87CE86214 7D8B4A14 7C6C 38508001000C7C0803 6382100084 800020 0 832500020E407C0802A690010004606C00001C6C00324E8000207C0802 690010004606C0000C8 S 32500020E601D6C0014 394003E87D685 396716 3FFFF4E8000204E8000 210000000000000000E9 S 30900020E8000020E84D2 570500020100 7 Application loaded Start address 00020100 ON gt After the download the relative start address 00020100 of the application is output Please note that an offset of 40000000 has to be added which yields the start address 40020100 Start the Demo application by entering the command go 40020100 Se File Edit Setup Control Window Help 6382100084 800020 0 532500020 407 0802 690010004 606C00001C6C00324E8000207C0802 690010004 606 0000 532500020 60106 0014 394003E87D6B53967163FFFF4E8000204E8000 Application loaded Start address 00020100 ON gt 40020100 Starting application at 40020100 You can check the correct functioning of the program by means of the lighting sequence on the LEDs V16 V31 of the starter kit la components 3 Technical Specification 3 1 Electronic Specification 3 1 1 Block Diagram RTC Oscillator CPU 32 Bit MMU CPM CPU Oscillator Power Fail Logic SDRAM Flash CAN Ports Download JTAG 32Bit 32Bit Interface BDM Bus 32Bit RS232 Board to Board connector
31. LONG 000002104 VERIFY SDRAM initialisation offset 5 DATA set OFFF0017C LONG O1FF5FC34 VERIFY DATA set OFFF00168 LONG 000002105 VERIFY DATA set OFFF0017C LONG OEFEABC34 VERIFY DATA set OFFF00168 LONG 000002106 VERIFY DATA set OFFF0017C LONG O1FB57C35 VERIFY DATA set OFFF00168 LONG 000002107 VERIFY burst read offset 8 in UPMA RAM DATA set OFFF0017C LONG O1FODFCOA VERIFY DATA set OFFF00168 LONG 000002108 VERIFY DATA set OFFF0017C LONG 4 VERIFY DATA set OFFF00168 LONG 000002109 VERIFY DATA set OFFF0017C LONG 010 7 04 VERIFY DATA set OFFF00168 LONG 00000210A VERIFY DATA set OFFF0017C LONG OFOAFFCOO VERIFY DATA set OFFF00168 LONG 00000210B VERIFY DATA set OFFF0017C LONG OFOAFFCOO VERIFY DATA set OFFF00168 LONG 00000210C VERIFY DATA set OFFF0017C LONG OF1AFFCOO VERIFY DATA set OFFF00168 LONG 00000210D VERIFY DATA set OFFF0017C LONG OEFBAFCOO VERIFY DATA set OFFF00168 LONG 00000210E VERIFY DATA set OFFF0017C LONG O1FF5FCA7 VERIFY DATA set OFFF00168 LONG 00000210F VERIFY Single write offset 18 in UPMA RAM DATA set OFFF0017C LONG 01 20 04 VERIFY DATA set OFFF00168 LONG 000002118 VERIFY DATA set OFFF0017C LONG OEEABBCOO VERIFY DATA set OFFF00168 LONG 000002119 VERIFY DATA set OFFF0017C LONG 001B27C04 VERIFY DATA set OFFF00168 LONG 00000211A VERIFY DATA set OFFF0017C LONG O1FF5FCA7 VERIFY DATA set OFFF00168 LONG 00000211B VERIFY
32. SB Bus Control IRQO 1 IRQ1 1 V14 EN Request 0 NMI Pull Up 4k7 BN Assis NN Ak7 IRQ2 RS H3 I O TS Interrupt Request 2 50 __ 1 H3 2 ES 4 7 sjueuoduio2 D L Aq 90p 00 0 NMH 1XX8NOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH It components Signal No of Type Description Ext Load Module Pin Pins Cap max pF Reservation Pull Up 4k7 4k7 V5 Interrupt Request 4 used 35 for CAN Interrupt connected to P2 6 INT of both AS82527 devices Pull Up 4k7 ee _ 4k7 IRQ6 Interrupt Request 6 Pull Up a 4k7 4k7 O TS Write E2 Bus Grant 50 X2 74 BURST TS Burst Transacilofi BDIPZ GP TS Burst Data In Progress gt B5 General Purpose Line B5 TS Burst Inhibit Pull Up 4k7 X2 81 TS Transfer Start Pull Up 4k7 X2 83 Acknowledge Pull Up 2k2 gue pw pos eese 5 G ITSIZ1 O TS Transfer Size 1 2 79 K1 TS Interrupt Request 4 Kill gt 2 72 Reservation Retry Pull Up 4k7 Interrupt Request 3 Memory Controller BS 0 08 O _ Select AO X1 56 BS_A1 C8 _ Select A1 BS 2 A7 Byte Select A2 X1 58 BS A34 B8 O Byte Select A3 X1 59 0 components Signal No of Type Description Ext Load Module Pin Pins Cap max pF por D
33. The module responds via the serial interface 18 Tera Term COM2 VT ON8xx 110 on TQM850L C TQ Systems 1998 2003 lock speeds ey f Bua MHz aximum 50 50 110 on TQM850L C TQ Systems 1998 2003 lock speeds EuS MHz urrent 50 50 Read write dump register s Define additional register Read memory Write memory bytes Read EEPROM Write EEPROM Erase FLASH memory Protect unprotect MON82xx code Load s record file into RAM FLASH Save s record dump Start program execution Switch echo on off display status Display memory sizes and write hardware info to flas write configuration info to flash Calculate check CRC Copy memory block to RAM FLASH Switch SYPCR initialization for application off dis Switch POST off display status This online help HELP for details sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components For further information on the 8 monitor program please refer to the enclosed software manual note 2 2 2 Downloading the Demo Application The prerequisite for this step is that a functional communication link should have been established via the serial interface refer to 2 2 1 1 Erase the Flash Bank 0 by entering the command erase bank O m T
34. Treiber 80MHz Takt Temperaturbereich 0 70 TQM855LDBOA3 T50 XPC855TZP50 Flash 16 SDRAM mit Schaltregler mit RS232 Treiber 50MHz Takt Temperaturbereich 0 C 70 C TQM860LDB0A3 P80 XPC860PZP80 8MB Flash 16MB SDRAM kein CAN mit Schaltregler mit RS232 Treiber 80MHz Takt Temperaturbereich 0 70 TQM860LDBOA3 P50 XPC860PZP50 8MB Flash 16MB SDRAM kein CAN mit Schaltregler mit RS232 Treiber 50MHz Takt Temperaturbereich 0 C 70 C TQM860LDDBA3 P50 XPC860PZP50 8MB Flash 64MB SDRAM CAN Controller 1 und 2 best ckt mit Schaltregler mit RS232 Treiber 50MHz Takt Temperaturbereich 0 70 TQM862LDBOA3 SR80 XPC860SRZP80 8MB Flash 16MB SDRAM kein CAN mit Schaltregler mit RS232 Treiber 80MHz Takt Temperaturbereich 0 70 Illustration 4 2 Standard Types of Modules sjueuoduio2 D L Aq 70078 20 0060 TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 5 Environmental Conditions 5 1 Climatic Conditions and Areas of Application e Ambient temperature 0 70 C optional 40 C 85 C e Storage temperature 20 100 C e Protection type IPOO no protection against dust and moisture 5 2 Installation Instructions The critical component with respect to heating is the CPU In open air condition natural co
35. all addresses 1 The memory controller is cleared after reset but is not activated Boot port size Defines the port size of the boot device as shown below 00 32 bit port size 01 size wwe Reserved for future use and should be allowed to float Initial internal space base select Defines the initial value of the IMMR bits 0 15 and determines the base address of the internal memory space 00 0 00000000 01 OxOOF00000 10 OxFF000000 11 OxFFFOOOOO DBGC Debug pin configuration See 4 1 for details Debug port pins configuration 01 00 01 00 01 00 Moea A A AL 7 sjueuoduio2 D L Aq 90p 00 0 1XX8NOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH m components See 4 1 for details Configuration for Debugging JTAG BDM 1 or open Configuration for JTAG Test JTAG BDM 0 0 0 1 13 14 EBDF External bus division factor Defines the frequency division factor between GCLK1 GCLK2 and GCLK1_50 GCLK2_ 50 CLKOUT is similar to GCLK2_50 The system interface unit and memory controller use GCLK2_50 and GCLK1_50 to interface with the external system 00 Full speed bus 01 Half speed bus 10 Reserved 11 Reserved 15 Core Little Endian Swap Defines core access operation following reset 0 Big Endian 1 Little Endian Depends on
36. by TQ Components GmbH m components 3 1 2 3 Synchronous Dynamic Random Access Memory SDRAM 16 bit SDRAM modules are used in the TSSOP54 housing e 16 64 MB e 1 memory bank with 32 bit e Clock 50 MHz 50 MHz module 66 MHz 66 MHz module 40 MHz 80 MHz module e Signals used CS SDRAMOZ CS2ft GPL A10 SDRAM OEZ GPL AB1 SDRAM GPL 2 RAS SDRAM GPL_AB3 CAS SDRAM BS 0 DQMU SDRAM Bits O 7 BS A12 DQML SDRAM Bits 8 15 BS A24 DQMU SDRAM Bits 16 23 BS 3 DQML SDRAM Bits 24 31 CLKOUT CKE only foreseen with Pull up e Control and refresh via UPMA CAS Latency 2 Depending on the memory capacity 2 chips each of 16 64 128 or 256 MBit are used The following access schematic is recommended refer to 5 Literature CLKOUT Single Burst Read Single Burst Write SDRAM type Read Write 66 MHz 4 1 4 1 1 1 1 3 1 3 1 1 1 1 133 50 MHz 4 1 4 1 1 1 1 3 1 1 1 1 1 PC100 40 MHz 4 1 4 1 1 1 1 3 1 13 1 1 1 1 PC100 Illustration 3 3 SDRAM Programming 3 1 2 4 CAN Controller Either one or two AS82527 Intel are used These are controlled by the CPU using the driver Addresses Chip Select and buffer Data It components Two fully compatible CAN 2 0b interfaces No CAN driver inputs and outputs at TTL level Clock pulses from the common 16 MHz Quartz on the first controller CLKOUT of the fir
37. dules After connecting a serial interface and the power supply the monitor program enables communication with the module with the help of a starter kit STK8xxL The MON8xx offers basic functions for commissioning the TQM8xxL These are divided into the following areas e Monitor functions Memory and register monitor to address the memory and the register of the 8 extension possibilities to address further also external memory mapped I Os It also offers simple functions such as memory editing dump change register as also the possibility to load S Record Files in RAM or Flash Automatic Application start After a reset either the monitor or an application an operating system can be started For this purpose the MONS8xx reads the port pin provided on the debugging interface Signal ENMON and passes control either to the monitor or starts an application or an operating system The specification and functionality of the is described in a special document 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 7 1 2 Configuration of the SDRAMs The SDRAMs are controlled by the UPMA The UPM is programmed for SDRAM operation with single and burst read and write CAS Latency 2 sequential operation no interleave and 4xburst The allocation of the sequencer table of the UPMA all other configurat
38. e ext This specification is used to state the complete file name with its corresponding extension Instructions Examples Examples of application e g e Specifying memory partitions e Processing a script Reference Cross reference to another section figure or table la components gt N gt gt gt Table of Contents About This Manual Terms and Conventions Table of Contents List of Figures Table Overview Acronyms and Definitions Tips on Safety Handling ESD Tips Registered Trademark Imprint Copyright Limited Liability Revision History Introduction Scope of Supply First Steps Board Setup Downloading the Demo Application Technical Specification Electronic Specification Block Diagram System Components CPU Permanent Memory Flash Synchronous Dynamic Random Access Memory SDRAM CAN Controller Bus Driver CPU Clock RTC Pulse CAN Pulse Reset Behavior Reset Configuration Reset Logic Tolerances and Reset Thresholds for VCC3V3 Tolerances and Reset Threshold for VCC5V External Reset Input Power Supply with different possibilities of the supply Possibilities of Power Supply 3 3V Supply Current Consumption at 3 3V Regulator for 3 3 V 5V Power Supply Current Consumption from 5 V Direct Total Consumption at 5 V Battery Buffering Interfaces Serial Interfaces Download Interface BDM Interface
39. ent Data 15 ee Spare 2 SPARE3 V15 Transmit Enable X2 85 MII TX E Spare 3 N MII COL _________ 2 External Clock X1 xs TEXP Timer Expired 50 ____ 1 36 oe R2 Power On Reset 7 1 35 connected to Voltage Supervisor output 3 3 and 5 V LED with 220 Q to oe RSTCONF Reset Configuration Pull Bown tk DSDI TDI Development Serial Data In 50 Test Data In baid BR Out Test Data Out ii T Test Clock Pull Down 1 G18 Test Mode Select Pull Up 50 X2 47 10k FRZ IRQ6 G3 Freeze Interrupt Request 50 X2 71 6 Pull Up 4k7 Port A sjueuoduio2 D L Aq 90p 00 0 IWMH 1XX8NOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH It components Signal No of Type Description Ext Load Module Pin Pins Cap max pF PA10 J17 Port A10 50 X2 38 Pot A11 PA12 F17 12 50 2 40 PA13 E17 1 50 2 41 PA14 PortA14 PA15 C18 Port 15 analog 10 X2 43 switch Port B PB15 R17 15 50 2 49 PortB16 J50 2 50 PB18 N17 18 50 2 52 PB19 Port B19 2 53 PB20 SMR 116 Port B20 used as 50 X2 54 XD2 SMRXD2 connected to RS232 Driver TTL Output via 4k7 resistor to allow other usage PB21 SMT K16 Port 21 used 55 XD2 SMTXD2 co
40. epubueq nz BUIS purs jueunoq WSBIP u essupiusy pun suisse 5 1875 956012 66 60 LE Duy 90 ansBunuypiez OL 021 Jeyoe s eoi 4 6610 91 002092 oornwy aran 669012 IN Bunwsusg unpa anano 7098791 Ze v 29641 sone 8 1 p Ae OIS lt B OE TEXTOS lt lt TO 915 ex a v TATUS s au H OSTATIC TOF 915 SEX ansa mt 7 n 66 8 d 091 unaa 96 e a ie ADP INASA 15 i ar zd ra as me 06 CUT ONTE non non 88 7 5 d 05 Peer a nie ss gr a 58 IVE 18 c a _ v EE s e a ar tr S b r T ec BI 3 zu lt 3 33 HN 3 o 92 se __ TSS TEM CSS IF 69 5 097
41. era Term COM2 VT E 10 xl File Edit Setup Control Window Help ON gt erase bank 0 Erasing FLASH bank 0 Please wait 2 Load the Demo file in the Module by entering the command load 40000000 f 0 File Edit Setup Control Window Help ON gt erase bank 0 Erasing FLASH bank 0 Please wait ON gt load 40000000 Ready for s record download to FLASH The time required to delete the flash memory is between a few seconds to a few minutes depending on the memory area te to be deleted no It components Select Send File from the File menu File Edit Setup Control Window Help New connection Log Transfer gt download to FLASH Select the TQM8xxL DEMO hex You will find this on your Tool CD I A A M Suchen in Tera Term Pro delpassw ttl readme dialup ttl login ttl readmej E IBMKEYB D macro TERATERM KEYBOARD fil keycode ABNTOSKEYB xL_DEMO HEX E Dateiname DEMO Dateityp all X Abbrechen Hilfe Option The Demo application is transferred on to the module ES sjueuoduio2 D L Aq 70029 20 0060 TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH la components W Tera Term COM2 VT File
42. ess and industrial areas as also small enterprises EN50081 5 4 4 EMC Passive Radiation Basic technical standard Interference susceptibility Part 2 Industrial area EN50082 5 4 5 ESD Basic technical standard Interference susceptibility Part 2 Industrial area EN50082 5 4 6 UL Approval A UL certification can be obtained if requried 6 Safety requirements and Personnel Protection 61 EMI EMC Requirements The conformance to the standards is fulfilled by using a reference design The starter kit STK8xxL with the corresponding external circuit is used as a reference design The module has been developed diligently and painstakingly to ensure conformance to electromagnetic interference compatibility EMI EMC requirements In spite of this depending on the target system certain radio interference suppression measures may be necessary to ensure that specific limit values are not violated for the complete system sjueuoduio2 D L Aq 70078 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components The following measures are recommended e Robust grounding measures sufficient ground surface on the PCB e With metal cabinets a good minimum with respect to HF connection of the PCB ground to the cabinet potential e Sufficient blocking condensors at all supply voltages e Leads carrying high frequency or continuous pulses e g Clock should be of short length avo
43. ffcc000 00080011A 07 004 00080011B Offfdcc05 00080011C VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY VERIFY DATA SET OFFF00100 LONG 000000000 VERIFY Configuration 82527 MCLK 8 MHz active 7 gt 2 6 fXTAL 16 MHz ISO low speed phys DATA SET 0C0000002 byte 045 VERIFY DATA SET 0C0000102 byte 045 VERIFY Illustration 7 5 Configuration of CAN Controllers 0 components layer INT CLKOUT active both CAN controllers This yields the following types of access the cycles pertaining to those introduced by the wait mechanism are not displayed Single read and burst read Single read and burst read la components Wave Editor BEE uu us jtd I MZ Illustration 7 6 Single read and burst read CAN Single write and burst write CLKOUT GCLK1 m T Dy Illustration 7 7 Single write and burst write CAN sjueuoduio2 D L Aq 20 0060 WMH IXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH la components Refresh and Exception Wave Editor CLKOUT GCLK1
44. id stray pick up in other signals by maintaining a distance and or appropriate shielding e Filtering of all signals which can be connected externally even slow and DC voltage signals can radiate HF indirectly 6 2 ESD Requirements It is meaningful to provide a good protection against electrostatic discharge directly at the inputs of a system so that there is no coupling in the path from the input to the protective circuit in the system Since these measures always have to be implemented on the motherboard no special protective measures have been incorporated in the module itself The modules used offer a certain degree of protection as per the specification which however in general is not adequate to comply with statutory requirements without additional measures The following measures are recommended e Generally applicable Shielding of the leads wires shielding on both sides connected firmly with ground body of the cabinet e For power supply Protection using supressor diode s e Slow signal leads wires RC filtering possibly Zener diode Fast signal leads wires Integrated protection modules suppressor diode arrays 6 3 Operational Safety and Personnel Protection A special test has not been performed owing to the voltages encountered lt 5 V DC la components 7 Annexure 7 1 Software Support 7 1 1 Monitor Software The monitor program 8 is the standard basic software delivered on TQM8xxL mo
45. ions for the operation of SDRAMs are illustrated in the following CMM file This can be executed directly with a Lauterbach debugger for other development environments the syntax must be adapted accordingly The initialization differs from that done by the monitor MON8xx in the following manner e Initialization for 8 column SDRAMs 16 and 64 MBit implemented SDRAMs with 9 columns 128 and 256 MBit are only half used e Refresh rate is permanently set to the maximum possible value Initialization BRO 1 and ORO 1 FLASH DATA set OFFF00100 LONG 040000001 VERIFY DATA set OFFF00104 LONG 0 0000 52 VERIFY DATA set OFFF00108 LONG 060000001 VERIFY DATA set OFFFO010C LONG 0 0000 52 VERIFY ab Rev 200 0EO0000F50 Initialization BR2 3 and OR2 3 SDRAM DATA set 0110 LONG 000000081 VERIFY DATA set OFFF00114 LONG 0 0000 00 VERIFY DATA set OFFF00118 LONG 020000081 VERIFY DATA set OFFFOO11C LONG 0 0000 00 VERIFY Single read offset 0 in UPMA RAM DATA set OFFF0017C LONG O1FODFCOA VERIFY DATA set OFFF00168 LONG 000002100 VERIFY DATA set OFFF0017C LONG 4 VERIFY DATA set OFFF00168 LONG 000002101 VERIFY DATA set OFFF0017C LONG 011 7 04 VERIFY DATA set OFFF00168 LONG 000002102 VERIFY DATA set OFFF0017C LONG OEFBAFCOO VERIFY It components DATA set OFFF00168 LONG 000002103 VERIFY DATA set OFFF0017C LONG 01 47 VERIFY DATA set OFFF00168
46. is oan PT la i aoe LL TOXIN aes SI Sd eui 5 d Sut Tar ans 1 te 1 IN uv un ausa z g romar as e awa wet a ud al 9 90141 Ulla DEN 4 B ons eu QW som sma orien en LIES 5 8 ASO 9 9941 3 je 3 Pirate H 9c Tatar T a r x EH 5 E uooi hz 9 3 a u T 3 2 ois H E un gt 5 3 z 4 2 3 8135 02 5291 91 faeSizam 4 7 9 m ix 1 3 5 i Sen al al al 8 aa E ASDA AS2O 2004 by TQ Components GmbH TQM8xxL HWM 0300 doc OOt dS 1 15 an sBunuypiez 661091 an oo core Ipiieuois NA on x 1 x TX ansa anaa ausa al aea 399 aea ELF d EB aea viand No 0925874 ae 062229724 ID
47. le X1 45 Pull Up 4k7 JTAG BDM Configuration X1 43 via Hard Reset Configuration Pull Up 10 1 Receive Data EE X1 52 SMRXD2 SMTXD2 _ 1 CAN1 VCC5V 3 V VCC3V3 VBAT LLL Illustration 3 22 Pin assignment RS232 level SMC1 Transmit Data 1000 X1 53 SMC2 Receive Data X1 50 RS232 level SMC2 Transmit ata 1000 1 51 85232 level 3 EN CAN 1 X149 CAN controller 2 ___ Xt 47 X1 116 X1 118 X1 120 X1 112 X1 113 X1 114 Battery Voltage connected X2 1 via Schottky Diode and RC combination 1 k 100 n to KAPWR 5 V Controller converter input 33 V Supply converter output CAN DC DC Supply DC DC Digital Ground For connection of the power supply refer to 3 1 5 1 47 la components 3 2 Mechanical Specification 3 2 1 General Information Two rowed high pole SMD connector with grid of 0 8 mm 2 120 pole The combination with different matching connectors facilitates different board heights in order to offer adaptibility to the assembly on the main board Double sided SMD assembly Multilayer PCB in Micro Via technique 3 2 2 Dimensions PCB dimensions 54 mm 44 mm PCB Height a b c 10 6 mm Free height under the module a d 2 6 mm The shaded areas in the
48. m 20 0060 WMH TIXX8INO L 7 TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 3 1 5 4 5V Power Supply Voltage Voltage VCC5V without CAN controller controller 4 792 5 5 V Determined by Determined by the Peak the voltage design of the Peak range of the regulator components and supervisor threshold the Illustration 3 15 5V Supply 10 Supply current max with regulator Maximum Worst Case 3 1 5 5 Current Consumption from 5 V Direct components Supply current max without regulator essy _ value Maximum value Worst Case Current Current Current consumption consumption consumption component 50 MHz max 66 MHz max 80 MHz max mA mA mA CAN 2 100 100 100 Controller AS82527 6 General 50 50 50 Logic Total 150 150 150 Illustration 3 16 Current Consumption from 5 direct la components 3 1 5 6 Total Consumption at 5 V If the module is supplied with 5 V power then the total current drawn is the sum of that drawn directly from the 5 V supply the input current of the DC DC converter which powers the 3 3 V logic Current consumption Component Type 50 MHz max mA 5 V Logic Refer to 3 2 3 1 150 Switching Input current 445 regulator Consumption 3 3 V 3 3 5 eta 0 80 Total 595 Illustration 3 17 Total Consumption
49. nnected RS232 Driver TTL Input PB22 PotB22 1 56 17 pon eee B23 50 X2 57 J18 Port B24 used as 50 X2 58 SMRXD1 or RXD3 connected to RS232 Driver TTL Output via 4k7 resistor to allow other usage PB25 SMT J16 Port B25 used as 50 X2 59 SMTXD1 or connected to RS232 Driver TTL Input 45 0 components Signal No of Type Description Ext Load Module Pin Pins Cap max pF Port C 50 X2 18 PC12 Port C12 X2 24 PC13 E18 lO C13 PC14 D18 lO C14 PC15 Port C15 W16 50 2 25 2 26 2 27 11 Port C11 X2 23 X2 8 lO D10 50 X2 10 Port D11 50 X211 16 PD13 Port D13 X2 13 PD14 Port D14 X2 14 PD15 Port D15 X2 15 Cap max pF Non CPU Signals Reset Input Master Reset Input of Voltage Supervisor Pull Up 4k7 y o Port D7 2 7 Port D8 HRESETF 1 Flash Reset Signal 12 V X1 44 may be applied without damaging the module however this is recommended 46 sjueuoduio2 D L Aq 90p 00 0 IWMH 1XX8NOL TQM8xxL HWM 0300 doc A fni 2004 by TQ Components GmbH No of Pins Signal Type ENMON It components Ext Load Module Pin Cap max pF Description JTAG BDM SMRXD1 SMTXD1 Monitor Enable enables X1 41 8 interactive Mode Pull Up 10 k SDRAM Clock Enab
50. nvection possible operation is possible over the complete ambient temperature range without any special cooling measures When mounting the module in a cabinet the following must be taken care of Within a closed cabinet in general there would be temperature rise What is important for the operational safety is the temperature in the vicinity of the module so that the maximum permissible temperature for the complete cabinet is reduced This can be improved e g by direct thermal connection of the module heat conducting sponge rubber to a heat sink or by forced cooling e Within the closed cabinet the module could also get heated by other sources of heat The remedy for this is as given above or by isolation of the heat source s 5 3 Reliability and Life span For the module a FIT Rate of 800 10 9 h has been calculated 12 For the connectors used a minimum of 100 connection cycles has been guaranteed 11 5 4 Product Qualification With respect to product qualification the PCBs have been tested as per the following standards or the tests are in progress 5 4 1 Mechanical Environmental Influences Vibration EN60068 2 6 Shock EN60068 2 27 la components 5 4 2 Temperature Tests Temperature change EN60068 2 14 Cold storage EN60068 2 1 Warm storage EN60068 2 2 Storage under moist conditions DIN IEC 68 2 3 5 4 3 EMI EMC Basic technical standard Interference emission Part 1 Living quarters busin
51. ode The address lead A29 Bit 31 is the least significant address lead is connected with AO of the Flash because of which the addresses and the command sequences have to be shifted left by two bits while programming or deleting i e multiplied by four la components Example Command sequence to program a 32 bit word 1 Bus cycle 2 Bus cycle Address Data Address Data Specification 0 0555 0x00AA 0x02AA 0x0055 AMD TQM860L 0x40001554 0x00AA00AA 0x40000AA8 0x00550055 3 Bus cycle 4 Bus cycle Address Data Address Data Specification 0 0555 0x00A0 PA 32 Bit Data AMD TQM860L 0x40001554 0x00A000A0 PA 32 Bit Data Illustration 3 2 Command Sequence for programming a 32 bit word The address to be programmed is identical in both cases The status signal RY BY of the Flash is not used i e the execution of the write and delete cycles must be monitored by polling the Flash status bits DQ7 Toggle Bits etc 4 Since each of the two 16 bit Flashes of a 32 bit bank has only one write enable signal only 16 or 32 bits can be written programmed Individual bytes can be programmed as follows 1 Read the data word from the Flash which contains the byte to be programmed 2 Replace the byte to be programmed in the data word 3 Write the data word back into the Flash 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004
52. pervisor circuit extended temperature range MAX816ESA Ureset matching resistance fitted 3 152 x 3 296 V Unese matching resistance removed 3 070 3 209 V 7 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH m components The matching resistance is removed if the reset threshold measured lies over 3 210 V 3 210 3 3 2 727 5 3 466 3 238V 3 341V 3 446V int Power supply Matching resistor 3 161V plugged in 3 287V Matching resistor Supervisor circuit 3 079V removed 3 199V 3 135V 3 3V 5 3 465V Illustration 3 10 Tolerances of 3 3V supply standard temperature range 3 210 3 3V 2 727 5 3 465V ext power supply int Power supply 3 222V 3 341V 3 463V Matching resistor 3 152V plugged in 3 296V Matching resistor Supervisor circuit 3 070V removed 3 209V 3 135V 3 3V 5 3 465V Operational range Illustration 3 11 Tolerances of 3 3V supply extended temperature range la components 3 1 4 2 2 Tolerances and Reset Threshold for VCC5V Tolerance of the power supply Pos D refer also to Illustration 3 12 VCC5V 5V 4 10 4 8 5 5 V Tolerance of the supervisor circuit UReset 4 638 V 3 27 4 488 4 792 V MAX816CSA MAX816ESA Permissible operational range of the CAN controller and 5V logic Pos E refer also to Illustration 3 12 5
53. ps General handling of your TQ products The handling and use of your TQ product may be done exclusively by qualified personnel Ensure that while using your TQ product particularly while plugging in out of modules changing jumper settings or connecting other external devices the power supply is not connected to your TQ product Violation of this guideline can result in damage destruction of the module and cause danger to your health Improper handling of your TQ product would render the guarantee invalid Proper ESD handling The ESD components must be used in workplaces which are apt for the handling them in order to avoid damage or destruction 1 7 Registered Trademark The TQ Components GmbH has strived to observe the copyright of the graphics and texts used in all publications and to use those created by them or those which are license free All brand names and trademarks contained in this publication are protected by copyright unless specifically stated otherwise of the corresponding owner or holder of the same The sheer mention cannot be used to conclude that brand names and registered trademarks are not copy protected by third parties sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 1 8 Imprint TQ Components GmbH Schulstrasse 29 D 82234 Wessling Tel 49 0 8153 9308 333 Fax 49
54. rder to ensure that the LEDs V16 V31 can be activated close the jumper X33 In order to check the configuration of the starter kit please proceed as follows 1 Start your PC Install the terminal program Tera Term Pro from the Tool CD on your PC 2 Start the program Tera Term 3 Select Serial port from the Setup Menu Tera Term 2 Illustration 2 2 The Tera Term Serial Port dialog box is displayed N Q R lt 4 3 5 5 a 3 c I Set the required parameters 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components Tera Term Serial port setup N x Port Baud rate z Data abit __ Stop __ Help Flow control gt FEL Transmit delay 0 msec char 0 msec line Illustration 2 3 The Tera Term Serial Port setup The pre requisite of the terminal program Tera Term Pro is that the Operating System of your PC is compatible with MS Windows For other Operating Systems e g Linux please use the appropriate alternatives 4 Connect the serial interface of your PC with the connector X19 of your starter kit using the download cable 5 Switch on the board using the adaptor 6 Press the Reset button S1 on your starter kit 7 Press the key Enter 5 times on your PC
55. red as follows Initialising BR2 and OR2 CAN 1 2 DATA SET OFFF00118 LONG 0C00004C1 VERIFY DATA SET OFFF0011C LONG OFFFF8500 VERIFY Initialising MBMR for the control of both the CAN controllers DATA SET OFFF00174 LONG 00001000 VERIFY DATA SET OFFF00174 LONG 00000000 VERIFY Activate SIUMCR GPL5 DATA SET 0 0000 long 001600040 verify Initialising the Micropatch for UPMB CAN single read DATA SET OFFF0017C LONG 004 VERIFY DATA SET OFFF00168 LONG 000800100 VERIFY DATA SET OFFF0017C LONG OO0fffd004 VERIFY DATA SET OFFF00168 LONG 000800101 VERIFY DATA SET OFFF0017C LONG 00 00 VERIFY DATA SET OFFF00168 LONG 000800102 VERIFY DATA SET OFFF0017C LONG 03fffc004 VERIFY DATA SET OFFF00168 LONG 000800103 VERIFY DATA SET OFFF0017C LONG Offffdc05 VERIFY DATA SET OFFF00168 LONG 000800104 VERIFY sjueuoduio2 D L Aq 70078 20 0060 TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH single DATA SET DATA SET DATA DATA SET SET DATA DATA SET SET DATA DATA SET SET DATA SET DATA SET disable global Chip Select 50 write OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 OFFF0017C OFFF00168 Offfcc004 000800118 Ocffcd004 000800119 00
56. s clock pulse from the CLKOUT of the first This is to be taken into account while initializing the CAN controllers The CAN controllers generate their respective clock pulses the baud rates for the CAN bus Tolerance of the CAN Pulse Nominal Temperature gt frequency Output tolerance coefficient max Ageing max 16 MHz 50 ppm 120 5ppm a Illustration 3 8 Tolerance CAN Pulse 3 1 4 Reset Behavior 3 1 4 1 Reset Configuration The system reads the reset configuration under normal circumstances from the bus RSTCONF 0 However if required even the default configuration RSTCONF 1 gt Bits 0 15 to 0 can be used for which a high signal is given at RSTCONF Bits Description 0 External arbitration If this bit is set external arbitration is assumed f it is cleared internal arbitration is performed 1 Initial interrupt prefix Defines the initial value of the MSR IP which defines the interrupt table location If is cleared default the MSR IP initial value is one if it is set the MSR IP initial value is zero 2 Boot Burst Enable 0 The boot device does not support bursting 1 The boot device does support bursting It components Edi pen ar putes 11 12 DPPC Boot disable If BDIS is set memory bank 0 is invalid i e BRO V is cleared 0 The memory controller is activated after reset so that it matches
57. splayed 14 Illustration 2 3 The Tera Term Serial Port setup 15 Illustration 3 1 Block Diagram nennen nnn 20 Illustration 3 2 Command Sequence for programming a 32 bit word 22 Illustration 3 3 SDRAM Programming esses eene 23 Illustration 3 4 Mapping the CAN 24 Illustration 3 5 Bus Structure 25 Illustration 3 6 Clock frequencies 26 Illustration 3 7 Tolerance RTC Pulse nemen nnne 26 Illustration 3 8 Tolerance CAN 27 Illustration 3 9 Reset Configuration 4 29 Illustration 3 10 Tolerances of 3 3V supply standard temperature 31 Illustration 3 11 Tolerances of 3 3V supply extended temperature 31 Illustration 3 12 Structure of the power 33 Illustration 3 13 3 3V 33 Illustration 3 14 Current consumption at 3 34 Illustration 3 15 SV
58. st controller is connected to XTAL1 of the second Accesss mode 8 bit non multiplexed Signals used CS_CAN CS3 GPL_AB2 R W CAN GPL 5 Buffer Enable Bus Transceiver for CAN A22 A23 Address decoding HRESET RESET CAN IRQ_CAN IRQ4 common Interrupt for CAN Control via UPMB adaptive timing Wait Signal Recommended settings Refer to 6 Literature The resultant mapping with respect to the base address of CS_CAN CS3z is as illustrated in Illustration 3 4 Mapping the CAN Controller The area shown is shadowed at the offsets 0 400 0x800 etc Access to the area 0x200 up to Ox3FF and their shadows lead to a Bus Timeout and should be avoided Common Base Adress CAN Controller 1 CAN Controller 2 unused don t access CAN Controller 1 Illustration 3 4 Mapping the CAN Controller z 7 0x0 0x100 0x200 0x400 sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 3 1 3 Bus Driver e No buffering of the address leads on the module The SDRAM and Flash are driven without additional delays e Unbuffered address bus brought out External peripherals can be connected by first switching on a driver The load capacity required for a driver input is available e Unbuffered data bus brought out Direct connection up to about 20 pF is possible beyond that external buffers would be
59. types for commissioning the processor are eliminated and the first taste of success is achieved in just a few minutes 2 1 Scope of Supply The following items are included in your starter kit box Module TQM8xxL Starter kit STK8xxL Power Supply 11 la components Download cable Tool CD T TheKey to the Embedded World sjueuoduio2 D L Aq 90p 00 0 IWMH 1XX8NOL TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH 0 components 2 2 First Steps 2 2 1 Board Setup Your STK8xxL is already configured for the module desired by you Note that all names of connectors refer to those of the starter kit The circuit diagrams of the starter kit are given in section 7 3 1 Circuit diagrams Starter kit te I For further information on the starter kit STK8xxL please refer to the enclosed hardware manual for the starter kit 5 1 Power supply X16 Closing the jumper X16 activates the 3 3V supply to the starter kit If your 8 has DC converter then this jumper must be closed X17 Closing the jumpers X17 activates the 5V supply to the starter kit This jumper must always be closed in order to ensure that the available interfaces are operational 2 ENMON Circuit The ENMON circuit can be activated by closing the jumper X34 so that during operation of the board commands can be sent and received via the serial interface 3 Activate LEDs In o
60. y half the size of a credit card The TQM8xxL represents a very compact powerful and universally applicable computer core which can sustain harsh industrial environments Illustration 2 1 TQM8xxL The pin assignment is compatible with one another for all modules of the TQM8xxL family Thus for example the pins of the TQM860L are a superset of the pins of the TQM850L In this manner based on the requirements modules with different computing capabilities and interfaces can be used on a main board All relevant pins of the microprocessor particularly all the port pins are brought out on the connector With this the system on the baseboard becomes transparent for the developer and all possibilities of the Hardware can be tapped to the full extent In particular the following facts contribute to the good industrial suitability of the module SMD population on both sides e Memory securely soldered on the board Flash and SDRAM Small PCB height effecting good mechanical characteristics mechanical vibration and shock Robust plug in system with a lead wire spacing of 0 8 mm Single source voltage supply of 5V sjueuoduio2 D L Aq 20 0060 WMH TIXX8INO L TQM8xxL HWM 0300 doc 2004 by TQ Components GmbH m components Short commissioning times of a developed system can be achieved by using the starter kit Plug and Play Time consuming wired board development proto
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