UEI Hardware
Contents
1. 3 1 6 Input Ranges A D Only The global range for all A D inputs is software settable using the Input Ranges dialog from the Configuration For the PG models the channel gains are set from the A D Settings dialog Jumper settable input ranges Input range 5 to 5V Min Max 3 1 7 Secondary Buffer A D Only a The secondary buffer allows large data sets to 5 be acquired This is especially important with Buttes size 2040 KB the high acquisition rates of the WIN 30 In order to acquire samples at full speed select a buffer large enough series boards The WIN 30 hardware driver to accommodate all the data It is possible to sample more data than the buffer size but the maximum sends data from the hardware to the buffer specified in the Secondary Buffer dialog first then from the secondary buffer to Snap Master sample rate will be reduced The default setting of 2048 KB or 2 MB works well for most data acquisition tasks If you receive a Buffer Memory Overflow error message in the Status Log the size of the Secondary Buffer should be increased File Name Hemwin30 File Date 10 20 94 11 35 AM UEI Hardware Page 9 3 1 8 Output Ranges D A Only The range of the D A board outputs is Bipolar 5V when set to the WIN 30 mode It is not necessary to select an output range for the hardware In Snap Master channels 0 and 1 are the 16 bit outpu2. Ground WIN 30 Digital Connections File Name Hemwin30 Page 11 File Date 10 20 94 11 35 AM
3. Hardware Page 5 4 Windows locates a dynamic link library by searching the same directories it searches to find an application module For Windows to the find the library it must be in one of the following directories which Windows searches in the order listed e The current directory e The Windows directory the directory containing WIN COM e The Windows system directory the directory containing such system files as GDLEXE e Any of the directories listed in the PATH environment variable e Any directory in the list of directories mapped in a network Microsoft recommends that DLL s be loaded into the Windows system directory This is where the default installation program places UEIDAQ DLL but any other valid position is acceptable In order for Windows to load the UEIDAQV Vxd the following line must appear in the 386ENH section of the Windows SYSTEM INI file device c uei ueidaqv 386 This assumes that the Vxd is in the default location the c UEI directory If it is not then the line should be modified accordingly Once again this is automatically done by the default installation program File Name Hemwin30 File Date 10 20 94 11 35 AM Page 6 Snap Master User s Manual 2 Analog Input A D 2 1 A D Settings 2 1 1 Pacing WIN 30 boards for Snap Master operate in burst mode also called block mode To use External Pacing the pacer must provide a pulse for each conversion period For example to sam
4. and information on the entire range of UEI hardware refer to the WIN 30 Reference Manual supplied with your board For information on the settings for each element please refer to the Data Acquisition section of the Snap Master User s Manual File Name Hemwin30 File Date 10 20 94 11 35 AM Page 4 Snap Master User s Manual 1 1 UEIDAQ operation There are three components to the UEIDAQ for Snap Master drivers 1 The UEIDAQ for Snap Master driver This is a DLL which translates Snap Master function calls to UEIDAQ functions 2 The UEIDAQ DLL All I O requests for any UEI board under Windows 3 1 go via this DLL It serves to synchronize all driver activity and allows full multi tasking 3 The UEIDAQV virtual device driver This driver handles all high speed I O operations as well as providing access Ring 0 access to the DLL Windows support is provided as follows 1 Windows 3 1 enhanced mode only is supported Operation under Windows 3 0 or earlier or in Windows 3 1 standard mode is not possible 2 A minimum configuration of a 386 processor and 4 MBytes of memory is required A 386DX or 486 processor and 8 Mbytes of memory are recommended 3 Windows 3 1 support is via a DLL Dynamic Link Library and a virtual device driver Vxd Both of these must be accessible to Windows for the driver system to operate The DLL is UEIDAQ DLL and the Vxd is UEIDAQV 386 File Name Hemwin30 File Date 10 20 94 11 35 AM UEI
5. Timer Inputs Analog Outputs Digital Outputs Analog Inputs Digital Inputs Counter Timer Inputs Analog Outputs Digital Outputs Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate File Name Hemwin30 WIN 30D 16 No 1 MHz 12 bits 24 S W WIN 30DS 16 Yes 750 000 Hz 12 bits No 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 30PGH 8 8 No 1 MHz 12 bits 1 2 4 8 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W Page 1 WIN 30DA 16 No 1 MHz 12 bits No 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 30DS 4 16 Yes 4 Chs 750 000 Hz 12 bits No 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 30PGL 8 8 No 1 MHz 12 bits 1 10 100 1000 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W File Date 10 20 94 11 35 AM Page 2 Analog Inputs Digital Inputs Counter Timer Inputs Analog Outputs Digital Outputs Analog Inputs Digital Inputs Counter Timer Inputs An
6. UEI Hardware Snap Master User s Manual UEI Hardware 1 Hardware Support ccccscccssssssscscsscsccsscscessscseessscseessssssseees 1 1 1 UEIDAQ operation resononrorenrenernrnernrnnnenvanenvanerenenvanernrnesnre 6 2 Analog Input A D eseeesvvvesveenvvveneneennneeesnnneennnnennnennnnenenneneneeneneneen 8 ZV CAI S Cte Sse an ean 8 21 1 Pacing na ctehis wala tele eis eee 8 21 2 Channel Last cicccccccecduncossgustevseeceacovsserseetuseeeovtesacsecness 8 3 Device Configuration and Hardware Settings sssesssees 9 3 1 WIN 30 Seriesusa kanske ale atdet 9 3 1 1 Available Modes rrrrnnnrnnrrrnrrnnrrrnrrrrrrrnrnnrrrrrrnnrernnnnsrr 9 3 1 2 Base Address ereire deseen eeen enean aep ee 9 3 1 3 DMA Channel usavssnrsveritvanssrsndsenvsv rnstrein 9 3 1 4 Interrupt bevel pinire 10 3 1 5 Time Base A D Only rrrrrrrrnnrrrnnrnnvrrrrnrrrrrnnrrrrnnnr 10 3 1 6 Input Ranges A D Only eeervrnennrnrvnrnnenverenvenenvnner 10 3 1 7 Secondary Buffer A D Only 10 3 1 8 Output Ranges D A Only eeronoronrovnvronrvrnrrnnvernrnr 11 3 1 9 8255 Setup Digital In Digital Out ee 11 3 1 10 Comnections ccecceeeecceeeeeseeeeseeeeeeeeseeeeeeeneeeeeeeee 11 File Name Hemwin30 File Date 10 20 94 11 35 AM UEI Hardware 1 Hardware Support Analog Inputs Digital Inputs Counter Timer Inputs Analog Outputs Digital Outputs Analog Inputs Digital Inputs Counter
7. alog Outputs Digital Outputs Analog Inputs Digital Inputs Counter Timer Inputs Analog Outputs Digital Outputs Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate File Name Hemwin30 Snap Master User s Manual WIN 30PGSH 8 8 Yes 750 000 Hz 12 bits 1 2 4 8 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 3016D 16 No 200 000Hz 16 bits No 24 S W 24 S W WIN 3016DS 16 Yes 200 000 Hz 16 bits No 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 30PGSL 8 8 Yes 750 000 Hz 12 bits 1 10 100 1000 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 3016DA 16 No 200 000Hz 16 bits No 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 3016DS 4 16 Yes 4 chs 200 000 Hz 16 bits No 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W File Date 10 20 94 11 35 AM UEI Hardware Analog Inputs Digital Inputs Counter Timer Inputs Analog Outputs Digita
8. l Outputs Analog Inputs Digital Inputs Counter Timer Inputs Analog Outputs Digital Outputs Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate Single Ended Differential Simultaneous Sampling Max Sampling Rate Resolution S W Program Gain Max Sampling Rate Max Output Rate Resolution S W Program Gain Max Output Rate WIN 3016PGH 8 8 No 200 000 Hz 16 bits 1 2 4 8 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 3016PGSH 8 8 Yes 200 000 Hz 16 bits 1 2 4 8 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W Page 3 WIN 3016PGL 8 8 No 200 000 Hz 16 bits 1 10 100 1000 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W WIN 3016PGSL 8 8 Yes 200 000 Hz 16 bits 1 10 100 1000 24 S W 4 S W 2 16 bit 2 12 bit No 24 S W The WIN 30 drivers for Snap Master can accommodate up to eight I O boards The maximum number of boards installed in one computer depends on the configuration of the hardware Each board must have its own unique setting for the Base Address and Interrupt Level These settings must also be different from all other components in the computer such as disk drives printers pointing devices etc This hardware section discusses only special operating instructions unique to the use of UEI hardware with Snap Master For detailed specifications
9. nap Master Configuration dialog For more detailed information on specific UEI boards consult the WIN 30 Reference Manual 3 1 WIN 30 Series AID Configuration F Hardware Settings Selection 1 WIN 30DA Time Base Available Modes Software Base Address 700 DMA Channel Interrupt IRQ 10 3 1 1 Available Modes A D Software Hardware D A Software Digital In Software Digital Out Software 3 1 2 Base Address The base address is set using switches 3 to 8 on the board s DIP switch The factory setting is 700 hex or H700 and takes 32 consecutive address locations from H700 H71F For more detailed information on the base address settings consult the WIN 30 Reference Manual 3 1 3 DMA Channel Snap Master does not use DMA with the WIN 30 boards so no setting is required and this control is disabled File Name Hemwin30 File Date 10 20 94 11 35 AM Page 8 Snap Master User s Manual 3 1 4 Interrupt Level The WIN 30 series of boards have a software programmable Interrupt Level The IRQ can be set to 2 3 5 7 10 11 12 14 or 15 Each board MUST have a unique IRQ Level Refer to Appendix E for information on the standard allocations for interrupts in a PC 3 1 5 Time Base A D Only The WIN 30 drivers for Snap Master make use of a 10 Mhz timer clock as shown in the Time Base dialog This setting is made automatically so no further input is required
10. ple two channels at 1000 Hz each the pacer must provide a 1000 Hz clock signal or a pulse every 1 1000th of a second Consult the WIN 30 Reference Manual for more detailed information on block mode operation and using an external clock Several boards in the WIN 30 series support simultaneous sampling DS DS 4 and PGS boards Under Snap Master simultaneous sampling is always enabled and no special action is required to select it The WIN 30 series hardware operates with its external trigger permanently enabled This allows for gated pacing using a digital input to the external trigger When the external trigger input is a logical high clock pulses are produced for pacing If the external trigger input goes to a logical low clock pulses are not produced and the conversions do not occur Consult the WIN 30 Reference Manual for more detailed information on external trigger operation 2 1 2 Channel List All of the WIN 30 series of boards except the PG models support 16 Single Ended analog input channels The PG models WIN 30PGL WIN 30PGL support 8 Differential analog input channels Selecting the correct model from the Configuration dialog automatically sets the correct number of inputs File Name Hemwin30 File Date 10 20 94 11 35 AM UEI Hardware Page 7 3 Device Configuration and Hardware Settings This section presents the hardware settings for the WIN 30 series of boards along with the corresponding setting in the S
11. t B7 Snap Master User s Manual Differential Single Ended A D 0 Low A D 8 A D 1 Low A D 9 Analog Ground A D 2 Low A D 10 A D 3 Low A D 11 Analog Ground A D 4 Low A D 12 A D 5 Low A D 13 Analog Ground A D 6 Low A D 14 A D 7 Low A D 15 Analog Ground D A 0 16 bit D A 1 16 bit D A 3 12 bit 12 Volts External Trigger Digital Ground STB Digital I O Port BO Digital Ground Digital I O Port B3 Digital I O Port B4 Digital I O Port B6 Digital Ground WIN 30 Analog Connections File Name Hemwin30 File Date 10 20 94 11 35 AM UEI Hardware Digital I O Port AO Digital I O Port Al Digital I O Port A2 Digital I O Port A3 Digital I O Port A4 Digital I O Port AS Digital I O Port A6 Digital I O Port A7 Digital I O Port BO Digital I O Port B1 Digital I O Port B2 Digital I O Port B3 Digital I O Port B4 Digital I O Port BS Digital I O Port B6 Digital I O Port B7 Digital I O Port CO Digital I O Port Cl Digital I O Port C2 Digital I O Port C3 Digital I O Port C4 Digital I O Port C5 Digital I O Port C6 Digital I O Port C7 5 Volts Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital Ground Digital
12. t channels and channels 2 and 3 are the 12 bit output channels 3 1 9 8255 Setup Digital In Digital Out lt The 8255 Setup dialog specifies which Be Gul digital ports are used as inputs Digital Betas ow input Coup In and which are used for outputs Pot B Bit8to15 input Coup Digital Out The 8255 Selection selects the 8255 chip being programmed for Port C Lower Bit 16 to 19 Input Output Port C Upper Bit 20 to 23 Input Output hardware with a single 8255 chip this is always 1 The corresponding digital bit numbers will be posted near each of the programmable port names A B C Upper or C Lower 3 1 10 Connections The WIN 30 series boards have two 50 pin connectors one for analog signals on the back plate of the board and one for digital signals on the board at a right angle to the back plate The following diagrams show the signal locations on the connectors in case you want to provide your own termination File Name Hemwin30 File Date 10 20 94 11 35 AM Page 10 Single Ended Differential A D 0 A D 0 High Analog Ground A D 1 A D 1 High A D 2 A D 2 High Analog Ground A D 3 A D 3 High AD 4 A D 4 High Analog Ground A D 5 A D 5 High A D 6 A D 6 High Analog Ground A D 7 A D 7 High no connection Analog Ground D A 2 12 bit Ground 12 Volts External Clock STB Digital Ground Digital I O Port B1 Digital I O Port B2 Digital Ground Digital I O Port BS Digital I O Por
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