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1. hl Substrate Height h2 Oxide Thickness h3 Spacer Height Nsub Substrate Doping xj S D Junction Depth the device simulation command file split cv des cmd which can also be downloaded here split cv des cmd It needs to be placed in the same directory as your other files presumably mosfetcv which was created earlier the inspect command file for plotting AC simulated CV curves cv_ins cmd which can also be downloaded cv_ins cmd 3 5 Video Tutorial First download all the files above place them in the mosfetcv folder Watch a 15 minute tutorial I prepared tonight Do not have my good mic with me So bare with the default laptop mic It is audible Follow the tutorial You should see CV curves pop up 3 6 Steps 3 6 1 Meshing To generate the mesh first edit structural parameters in the mosfet_fixed scm file If you are on command line working inside the mosfetcv folder already just run gedit mosfet_fixed scm After editing save the file You do not have to close the editor as it is running in background Next run sd 1 mosfet_fixed scm You will see sde working to generate the MOSFET mesh and tecplot displaying the end result You can examine the structure or doping etc inside tecplot No need to save anything when asked It has all been saved with commands inside the command file You can then close tecplot and sde programs 3 6 2 Simulating Examine split_c
2. 8 X Slice 1 Figure 2 14 Band diagrams all bands 2 7 Gate Bias Dependences 17 devices Documentation Release 1 0 8 X Slice 1 ConBanEne 1 Multi Multi X 0 12 ConBanEnetZ Multi Multi X Q 12 ConBanEnet 3 Multi Multi X Q 12 ConBanEnet4 Multi Multi X Q 12 ConBanEne 5 Multi Multi X Q 12 ConBanEnetbe Multi Multi X Q 12 ConBanEne 7 Multi Multi X 0 12 Figure 2 15 Band diagrams Ec 18 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 Also observe that there is indeed a noticeable potential drop inside the heavily doped N polysilicon gate which is responsible for the so called poly depletion effect That is one of the reasons why in most advanced CMOS metal gate replaced polysilicon gate Just for completeness let us look at the Ev diagrams shown figure 2 16 too 8 X Slice 1 ValBanEne 1 Multi Multi X 0 12 ValBanEne 2 M ulti Multi x 0 12 ValBanEne 3 M ulti Multi x 0 12 ValBanEne 4 M ulti Multi x 0 1 2 ValBanEne S M ulti Multi x 0 12 ValBanEne 6 Multi Multi X 0 12 ValBanEne 7 Multi Multi X Q 12 Figure 2 16 Band diagrams Ev 2 7 5 Inversion Charge and Space Charge From the band diagrams you should have expected the following inversion carrier density distributions in this case n vs depth plots of figure 2 17 The p vs depth plots look like that shown in figure 2 18 The net space charge density d
3. Pretty much at lower Vds the channel is like a resistor varying Vg simpy changes resistance but the lateral field is simply Vds L and thus indpendent of Vg 6 8 Lateral field and Velocity at Mid Channel Point 69 devices Documentation Release 1 0 600000 400000 200000 eVelocitu at Pos 0 0 0000001 cm s 0 0 5 1 Drain Yoltage Y Figure 6 13 eVelocity at mid channel point at surface versus Vd lgate 2um 70 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 The difference is at high Vd when saturation occurs With velocity saturation drain current saturation occurs at a smaller Vd which will then make the Ex inside the channel saturate too Recall much of the extra Vd beyond saturation will be drop over a very narrow region near the drain After saturation occurs the intrinsic channel s surface potential and hence lateral electric field will no longer change much This means the mid channel lateral field Ex will also stay pretty much saturated Think about these plots and see if they make intuitive sense to you For 2um lgate velocity saturation plays little role It is pretty much showing classic long channel behavior Velocity Saturation Region This high field region near the drain used to be called pinch off region As velocity saturation is a fact of life for these short channel devices and velocity saturation occurs before pin
4. However in practice we continue to use the long channel like equations so we continue to use these concepts like threshold voltage We should keep in mind that more complex nature of short channel device We have seen from figure 9 5 that with a high halo doping level of 1 5e18 the threshold voltage decrease with gate length scaling has been greatly reduced In other words halo doping is effective in suppressing short channel effect Next let us take a deeper look at how halo helps suppressing short channel effect 9 8 How Halo Helps Recall from Elec6700 that PN junction depletion thickness can be reduced by increasing doping The situation is similar The pocket halo doping placed near the source drain reduces the depletion thickness of the source drain to channel junctions Effectively the lateral distance over which the source drain have control is reduced or its impact is weaker for the same distance from source drain To illustrate this 2 D potential contours of 45nm and lum devices with and without halo doping are compared in figure 9 6 Biasing conditions are the same as above Vg 0V and Vd Vdd It takes some patience and efforts to have all the plots formatted in the right way with the right scale for x and y axes suitable for apple to apple comparison The following considerations went into formatting these plots 1 The same scale is used for the x and y axes for the same gate length 2 The y axis scale for all four plots is m
5. gave the simulator any information on the dimension along the 3rd dimension Real objects are 3D of course 30 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 Figure 4 1 Doping variation along MOSFET channel at the surface showing halo doping 4 7 l V Plotting and Unit of Current 31 devices Documentation Release 1 0 IdVd Lg 1 0 dVd Yg 1 20 id Vg 0 90 dVd Vg 0 60 dvd Vg 0 30 E 0 0006 2 S 0 0004 O E 0 0002 O 0 0 5 Drain Voltage V Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 By default the simulator assumes a lum width in the 3rd dimension In our MOSFET case it means the default channel width is lum This of course can be changed We will get to that later or you can look up the manually to quickly find out how to change this Note Think about what the unit of terminal resistance should be for a 2 D simulation 4 8 Probing Internal Physics for Understanding To probe internal physics in a terminal run tecplot_sv From reading the des cmd files you should know what all the tdr files are Make a y cut at y 0 001 0 strictly speaking see above for why the surface of Si We can plot out Ec Ev electrostatic potential Efn Efp phi_fn phi_fp etc along the cut 4 8 1 High Vg Recall the name
6. implemented using different doping levels Vtem 1e16 Vtem 1 5e18 Yt OD 1E 1 1E0 Gate Length Cum Figure 9 5 Vd 0 05V threshold voltage from peak gm extrapolation versus gate length Both halo and non halo devices are shown Without halo doping threshold voltage decreases with gate length as the source drain junction lateral field penetrates into the channel raising the surface potential As a result less gate voltage is required for the surface potential to 100 Chapter 9 Short Channel Effect and Reverse Short Channel Effect devices Documentation Release 1 0 reach the same threshold value Since 45nm is so short compared to the lateral depletion width of the source drain to channel junctions the whole channel is now under the influence of the source drain junctions With a high drain voltage of Vdd the situation is only worsened If you repeat the surface plot for multiple Vd you will find that the peak Ec point will move towards the source with increasing Vd and the barrier will be lowered with increasing Vd too I have shown you one such plot in class you can generate one yourself This of course is a way too simplified picture of reality which is inherently 2 D while threshold surface potential was a concept from 1 D MOS structure analysis When we have so much lateral surface potential variation most of the concepts such as threshold surface potential even threshold voltage lose its classic meanings
7. uguof physics Idvd n30 0003 0006 des tdr 0 0 Y 1e 07 eCurrentDensity 002 uguof physics Idvd n32 0003 0006 des tdr 0 0 Y 1e 07 2 5E 07 no velocily saturation 1 5E 07 Figure 6 18 Jn along channel lgate 2um 76 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 eDensity 001 uguof physics idvd_n30_0003_0006_des tdr 0 0 Y 1e 07 eDensity 002 uguofiphysics idvd_n32_0003_0006_des tdr 0 0 Y 1e 07 wih vsal no velocily saluratio Figure 6 19 Surface n along channel Igate 2um 6 9 Inspecting Internal Details 77 devices Documentation Release 1 0 eEnormal DO 1 uguof physics Id vd n30 0003 0006 des tdr 0 0 Y 1e 07 eEnormal 902 uguof physics Idvd n32 0003 0006 des tdr 0 0 Y 1e 07 200000 no velocily saturation wiih vsal 1 5E 06 Figure 6 20 E field normal to current flow along channel lgate 2um 78 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 eEparallel 001 uguof physics Idvd n30 0003 0006 des tdr 0 0 Y 1e 07 eEparallel 002 uguof physics Idvd n32 0003 0006 des tdr 0 0 Y 1e 07 200000 150000 100000 no velocily saturation wiih vsal Figure 6 21 E field parallel to current flow along channel lgate 2um 6 9 Inspecting Internal Details 79 devices Documentation Release 1 0 Surface eVelocity Other Plots 6
8. we find that mid channel velocity is affected more for shorter gate lengths At 65nm there is much more difference 6 8 Lateral field and Velocity at Mid Channel Point 71 devices Documentation Release 1 0 eVelocitu at Pos 0 0 0000001 cm s IdVd Lg 0 065 20000000 10000000 0 0 3 1 Drain Voltage V Figure 6 14 eVelocity at mid channel point at surface versus Vd lgate 65nm 72 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 Ex at Mid Channel Note that velocity saturation effect also has caused change of the e field as well so you cannot simply assume E will be the same when you turn on velocity saturation effect It is a self consistent solution of all equations in the end The Ex at mid channel at surface versus Vd for 65nm is shown below IdVd Lg 0 065 bOO00 40000 Ex at Hid Channel Y cm 20000 0 0 5 1 Drain Yoltage Y Figure 6 15 Ex at mid channel point at surface versus Vd lgate 65nm 6 9 Inspecting Internal Details Much of the above analysis is about the mid channel point Ideally you always want to probe the 2D distribution of internal physical quanities such as potential eDensity eVelocity etc 6 9 Inspecting Internal Details 73 devices Documentation Release 1 0 Comparing 2D plots e g eDensity distribution between with and without vsat however can be challenging You can put them side by
9. 0000001 eDensity 0 0 0000001 It is very important to use parentheses to specify the coordinate which is given as one to three depending on device dimensions numbers in parentheses In this case we are running 2 D simulation So we are asking the program to give us required quantities at x 0 y 0 0000001 The parentheses distinguish coordinates from node numbers which you can find out using tecplot_sv Do not worry about it for now Just use coordinates The advantage is that no interpolation is required When specifying coordinates the program will have to do interpolation using values at the nearby nodes in your grid mesh O01 mosteticonstmusid va nG 7 der pit drain TotalCurrent f dg n amp 7 des plt drain TotalCurrent Idv n57 des pit drain TotalCurrent Id v o n57 des plt aE o5 SE 05 4E 05 2E 05 Phumob Enormal 9 9 2 0 4 0 6 0 8 Quter valtage gate Outervaltage 1 Figure 5 1 Mobility effect on Id V g linear characteristics L 1um 5 6 Sdevice Commands 51 devices Documentation Release 1 0 amoeftet conestmush n erp lt 14090 1200 Pos 9 12 07 eMobility Idvg_n57_des plt Pos 9 12 97 eMobility Idvg_n57_des plt Pos 9 12 97 eMobility Idvg_n57_des plt 1900 Phumob aoo 600 400 200 Phumob Enormal 9 4 9 6 0 8 Quter valtage gate Outervaltage 1 Figure 5 2 Mobility Vg L lum Think about how this will affect Id Vg Does it ma
10. 2 9 Electrostatic potential for all gate biases Observe that for Vgs gt 0 4V the potential in the Si surface region changes very little Much of the further gate voltage increase is absorbed by the very thin gate oxide there is also a tiny but noticeable amount of potential drop in the heavily doped N poly gate near the gate oxide interface Why this is the case will become clear once we examine the band diagrams 12 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 2 7 2 Quasi Fermi Potentials electrons The electron quasi Fermi potential distribution for all gate biases are shown in figure 2 10 8 X Slice 1 eQuFerPot 1 Multi Multi X Q 12 eQuFerPot 2 Multi Multi X Q 12 eQuFerPot 3 Multi Multi X 20 1 2 eQuFerPot 4 Multi Multi X 0 1 2 eQuFerPot b Multi Multi X Q 12 eQuFerPot amp Multi Multi X Q 12 t eQuFer Pot 7 Multi Multi X Q 12 Figure 2 10 Electron quasi Fermi potential distribution for all gate biases Observe that the quasi Fermi potential is equal to zero in the silicon substrate body and equal to the gate voltage in the N polysilicon gate holes The hole quasi Fermi potential distribution for all gate biases are shown in figure 2 11 Observe that the quasi Fermi potential is equal to zero in the silicon substrate body and equal to the gate voltage in the N polysilicon gate 2 7 3 Quasi Fermi Energies
11. 5 Temperature dependence of CMOS transistors In my lab we can take on wafer measurements from 10C to 140C You need to let me know your topic of choice and discuss with me your written project plan by Friday the 18th 3 00pm It can be just a short list of simulation or measurement I will give you feedback 105 devices Documentation Release 1 0 10 3 Written Report Your final report is due 3 00pm Dec 2nd Please take into account my feedback to you on the mid term report in writing your final report Please use IEEE Transactions on Electron Device paper format Your report should be no longer than 10 pages Your Sentaurus simulation files should also be submitted with a readme file that explains how your files should be run 106 Chapter 10 Class Final Project and Exam CHAPTER ELEVEN FINAL EXAM SCOPE The class final exam will be open book open notes open computer and open Internet The problems will mainly come from our notes and homework assignments For instance you may be asked to explain how halo doping affects the threshold voltage versus gate length curve or how threshold voltage choice affects the Ion and Ioff of a MOS transistor or how multiple cores help with performance power trade off A list of topics are given below for you to prepare for the final exam You can refer to the journal and HTML notes posted on blackbaord and this HTML site respectively our text book and use IEEE explorer for exam
12. 65nm device is shown below 6 7 Id Vd Curves The Id Vd curves for each gate length obtained with and without turning on velocity saturation effect are overlayed so that we can see the impact of velocity saturation directly 60 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 001 uguol physics IdYd_n36_0003_0006_des idr 0 0 ation cm 3 E415 A7E418 Figure 6 4 65nm device mesh 6 7 Id Vd Curves 61 devices Documentation Release 1 0 Simulations were run for all the gate length from 45nm to 2um which produce the following Id Vd plots 6 7 1 2um IdVd Lg 2 3e 05 E 2 6e 05 c v a 3 4e 05 al D c e ze 05 O 0 5 1 Drain Voltage V Figure 6 5 Id Vd lgate 2um There is visible but small difference for 2um gate length 6 7 2 1um Note there is more difference compared to 2um lgate 6 7 3 0 5um or 500nm Vsat makes much more difference Id is smaller and Vdsat is smaller too as expected 62 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 IdVd Lg 1 Idvd Ve 1 20 Idvd Vg 0 90 IdVd Ve 0 60 Idvd Vg 0 20 IdWd Ve 1 20 Idvd Ve 0 90 Idvd Ve 0 60 Idvd Vg 0 320 0 00015 0 0001 Drain Current A um Se 05 0 5 1 Drain Voltage V Figure 6 6 Id Vd lgate lum 6 7 Id Vd Curves 63 devi
13. Objectives The objectives for this project are understand CMOS transistor electrical characteristics Id Vg Id Vd understand body effect extract threshold voltage subthreshold swing Ion loff quantify impact of mobility choices on Id Vg and Id Vd velocity saturation in particular quantify impact of gate length quantify impact of poly gate depletion quantify impact of gate oxide dielectric constant quantify NMOS and PMOS differences quantify the impact of halo doping on Id Vg and Id Vd Vth SS Ion Ioff understand drain induced barrier lowering through examining Id Vg for different Vds and internal details e g potential contours surface potential and electron current stream traces 7 2 Required Programs sde sdevice tecplot_sv inspect swb 83 devices Documentation Release 1 0 7 3 Basic Requirements Reduced Except for the halo doping part all other parts of this project have been done before When running the inspect programs in the terminal window you run inspect from extraction results such as Vth SS Ion Ioff are reported You can use swb to manage your project but you do not have to It is a powerful tool but also requires extra effort to be able to write new codes If it is a task not too different from the example swb I gave you you can try doing so I suggest that you start with just modifying the non swb codes you have been using for homework That will be our basic r
14. PEPE ee 7 3 Required Progratus AA A don b d Bh a ee mox ERO dub BS a 7 9 Basic Requirements Reduced 5 oaov XOU Oy Re S TA Explorer Further ss ia at peo e ORC e tho A eR tete BS ADAC a Bow a T2 REPOM 2 4 kot Rum mox RO hh eGR Ae Rom V eGR ee ECECRUR SN E Ro basa da Gate Length Scaling on Transistor Electrical Performance S l 3ODjJecHVes xl ESSE SMS Eum Uo dte RA eios OR EU ee ox ote d ne Lies 8 2 Required POSTAS o ss 554 lt n Row OR Ro h xU a qp eed dom EE Fui Sor Eo di MC CD UT ee Be ee See 8 4 GateLength Impact 4 Eb aes RA endo BU RE nde be ag a 85 Operating SWD lt 9x Uo eau a BER ERR AEE A RUE Vom AL d Short Channel Effect and Reverse Short Channel Effect 9l MOE omic EA TTL 92 REGIA s sas s x Ro 9 AS OME E E Oe O ee X ADR Rus 9 3 JR adinP ASSICNINENE kuu Aid Brae eae dde doe e A av aS i eRe ee 94 TCAD Simulati ns Required ers go Ss bee na e e he ee be ee Wa 9 2 D Potential Contours and EC 2 yi e eee bee b Row eM EEE PSEA Pos ot CS O AA 9 7 Threshold Voltage vs Gate Length 06 44 omo era eae Re DEG D RR 9 8 How Halo Helps pos a soping m enii Re ocn So ae Be Due Rhe BDA ae le e a 9 9 Reverse Short Channel Effect RSCE AA soe ee S 9 10 VIland DIBL effects 2 5600 uei oe REESE e eee amp Rene SO Bley Bow 8 9 11 Subthreshold SWINE isso 8 xoxo e 624 a RHE vor xm xen Dee bee OX OR T 9 12 TIOMEW ORK ect a doe Xu dies qa 9 ee dep siae e oe p qn s ae ups Class Final Project a
15. Potential below the surface also called sub surface is much higher in the 45nm device We cannot tell any laterally uniform region in the 45nm device A PD d The depletion boundary indicated by the white line is much deeper in the 45nm device for the same gate voltage This is an indication of lower threshold voltage in the 45nm device 6 At the surface the potential barrier faced by source electrons is much lower in the 45nm device As we have shown in previous classes this barrier lowering at short channel length is strongly dependent on the drain voltage and thus called drain induced barrier lowering DIBL 7 DIBL is non existent in the long channel device Explore yourself to look at about everything you can think of potential conduction band energy Ec eDensity n eCurrentDensity jn eVelocity vn Electron density is compared in figure 9 2 There are lot more electrons in the surface region of the channel in the 45nm device than in the lum device 001 nmos_physics IdWd_n327_0000_0006_des idr 0 0 002 nmos_physicsfidVd_n201_0000_0006_des idr 0 0 218417 1 6413 1 7E 08 158406 218417 ET 178408 158405 SEDI Daniy 00 nmos_physcedldYd_1M327_0000_0006_destdr 0 0 Y 1e07 00 nmos phy sce ldvd r 01 0000 0006 desidr 0 0 Y 1e07 eDensity em 3 Figure 9 2 2 D contours and 1 D surface plot of eDensity n along channel in 45nm and lum devices Vg 0V Vd Vdd 9 5 2 D Potential Contours and Ec 97 devic
16. Release 1 0 D00 l nmos_physics IdWd_n201_0000_0006_des idr 0 0 002 nmos physics ldvd n327 O0000 Q006 des ldr 0 0 Figure 9 6 2 D potential contour at Vg 0V and Vd Vdd for 45nm and lum MOSFETs with and without halo doping 102 Chapter 9 Short Channel Effect and Reverse Short Channel Effect devices Documentation Release 1 0 9 10 VTl and DIBL effects figure 9 7 shows current defined threshold voltages and DIBL versus gate length Both halo and non halo devices are shown For short lengths DIBL is stronger without halo However with halo DIBL is strong with halo in the long channel devices This is not an error It is real The exact physics on this is beyond the scope of this class I can recommend some recent research papers on this topic if interested DIBL is fortunately weak in long channel devices to begin with so some degradation due to halo does not present a big problem It is mainly a concern for analog circuits that often use long channel devices The consequence is an increase of the output conductance DIBL 1616 VtiSat 1e16 e Vtilin 1e16 DIBL 1 5818 VtiSat 1 5618 Vtilin 1 5e18 AAA wer 2977 Yt OD CAZA 14910 1E 1 1E0 Gate Length um Figure 9 7 Current defined threshold voltages and DIBL versus gate length Both halo and non halo devices are shown 9 10 VTl and DIBL effects 103 devices Documentation Release 1 0 9 11 Subthresho
17. estimate its 1 Ioff defined as Id at Vg OV and 2 subthreshold Id at Vg 0 15V Reviewing the journal note on subthreshold current should be sufficient 11 8 Short channel effect Explain how scaling gate length affects threshold voltage 11 9 DIBL Understand DIBL effect and its measure Use tecplot_sv to illustrate how DIBL effect varies with channel length and how it is affected by halo doping in short channel devices 108 Chapter 11 Final Exam Scope devices Documentation Release 1 0 11 10 Effect of Halo Doping Explain the effect of halo doping on transistor Id Vg Vth lgate using tecplot_sv Simulated potential contours with and without halo need to be well understood 11 11 Channel length scaling limit Minimum channel length one can achieve highly depends on gate oxide thickness or equivalent gate oxide thickness and device structure e g a tri gate vs traditional bulk Many of the Id Vg curves you see in textbooks show real bad short channel behavior at gate length of 0 25um While at the same gate length in the simulations you have been running the Id Vg is ideal and long channel like This is mainly because of the difference in oxide thickness Historically the short channel length limit was thought to be 500nm in the 70s 250nm in the 80s 100nm in the 90s when I was in grad school and now 22nm is in production So the channel length scaling potential was vastly underestimated primarily because our abi
18. idvglin_des cmd as an example File input files Grid n9 msh tar Parameter pp57_des par output files Plot n57 des tdr Current n57 des pit Output n57 des log Electrode Name source Voltage 0 0 Resistor 40 Name drain Voltage 0 0 Resistor 40 Name gate Voltage 0 0 Name substrate Voltage 0 0 Insert PhysicsSection_des cmd Insert PlotSection_des cmd Insert MathSection_des cmd CurrentPlot 48 Chapter 5 Physics Selection Effect on Electrical Characteristics and Tracking Position Data devices Documentation Release 1 0 eMobility 0 0 0000001 ElectricField Vector 0 0 0000001 evelocity 0 0 0000001 ElectrostaticPotential 0 0 0000001 eDensity 0 0 0000001 Solve Creating initial guess coupled Iterations 100 Poisson Coupled Poisson Electron Coupled Poisson Electron Hole x Ramp to drain to Vd Quasistationary InitialStep 1e 2 Increment 1 35 inStep 1e 5 MaxStep 0 2 Goal Name drain Voltage 0 05 Coupled Poisson Electron Hole Vg sweep NewCurrentFile IdVg Quasistationary DoZero InitialStep 1e 3 Increment 1 5 MinStep le 5 MaxStep 0 04 Goal Name gate Voltage 1 2 Coupled Poisson Electron Hole CurrentPlot Time Range 0 1 Intervals 30 plot FilePrefix n57 snap Time Range 0 1 intervals 6 NoOverwrite 5 6 1 Physics Selection The statemen
19. near the drain electron quasi Fermi potential follows the electronstatic potential surface potential roughtly is Vcb a constant We see this behavior in this plot eGradQuasiFermiPotential Gradient of eQuasiFermiPotential is driving force of current We see this clearly in the plot eQuasiFermiEnergy This is very much the opposite of eQuasiFermiPotential Recall that Vcb is equal to Vds at the drain eDensity This is a plot you really would like to not use the y 0 001 cut I recommend using the cut along boundary function Reason Even a 0 001um separation can make large difference in eDensity This however cannot be done automatically without using mouse to position the start and end points of the boundary Also I have not found a way to repeat the cuts on all biases loaded Below is a cut along boundary result for the Vg 1 2V and Vd 1 2V case Still we see a clear picture of how electron density varies along the channel that is it decreases from source to drain as we well expect from our 3 terminal MOS theory The amount of decrease is dependent on Vd which sets Vcb From source to drain gate voltage is the same but Vcb increases from 0 to Vds in this case Electron density thus decreases from source to drain This is a linear scale eDensity plot Electron Velocity and Pinch off Note that we are using a highly simplified mobility model with no velocity saturation So you see very high velocity particularly near the dra
20. notes amp physics 9 Picture Public E subdop 9 synopsy om tcadpro 3 tcadtoo Y Templati C tmp Q Videos 3 wmx220t ae 0 13 a 0010109 00 LJ 1 I I I I I eleie eeelie kai kai KA HA ee NS INS LES i oom 1 I 1 1 oo AR ala EY hone niu Y Bipolar cmos FinFET E FTPApp1 Y Getting Q Hetero C Memory Y Opto Y Power f a LL L Ne e Ies ele es es es es e BBS ERR e ons ls pos J a t Edit mode none queued ready pending running done BENI SSS virtual feruned ara a Figure 6 3 Velocity Saturation Physics swb project You are now in a position to examine the impact of vsat You can check out the Vds dependence Lg dependence etc You can also on the command line look at the plt and tdr files produced You can use tecplot_sv to look at those as well To save your disk space I have commented out the commands for saving tdr files during Vd sweep There however is still at least one tdr file which is saved in the very end that is for the highest Vgs and Vds Check your folder sort it by date you will see which files are new 6 6 Mesh Always examine your structure and mesh before running a lot of simulations A sample mesh for the
21. preparation We will address all of these issues in more depths next semester Spring 2012 in ELEC7710 Field Effect Transistor where we will also address physics based compact modeling TCAD in 6710 I have basically provided existing codes for you to use you will learn how to write your own codes including building 2d and 3d devices in 7710 RF and microwave properties including noise and linearity CMOS low noise amplifier design as well as on wafer characterization using automatic probe station and ICCAP which you have seen in my lab towards the end of the semester using state of the art CMOS and SiGe BiCMOS wafers As you may have noted from taking 6710 I generally emphasize hands on experience in my teaching and will work closely with you on derivation Matlab Python coding TCAD coding demonstration as well as Spice Ads Cadence tools 11 1 Band diagrams Draw PN junction as well as MOS capacitor band diagrams Should be able to identify accumulation depletion inversion strong inversion Reviewing relevant notes journal as well as HTML will be sufficient 11 2 Field Effect Draw surface potential total charge and inversion charge as a function of gate voltage Identify the different operation regions on all of these curves e g accumulation depletion inversion or strong inversion You can use existing homework matlab codes to draw these graphs instead of by hand 11 3 Threshold voltage Calculate both gate to body a
22. regions where Efn Efp Ef if Ef gt Ei it is n type If Ef Ei it is p type 2 6 Zero Bias 9 devices Documentation Release 1 0 Below is a band diagram showing Ei 2 X Slice 1 eQuFerEne t MultifMulti X 0 hQuFerEnett MultiMulti X20 ConBanEne t Multi ulti X Q ValBanEne t Multi Multi X Q YU Multi Multi Figure 2 7 Band diagram with Ei the intrinsic Fermi level Because of the doping difference between N poly gate and p body there is band bending at the silicon surface You can easily picture how electron concentration n and hole concentration p vary from this band diagram Sketch that yourself then compare with the following plots Observe how n increases towards the gate oxide Si interface and p decreases in the process The pn product is kept constant Can you explain why the pn product in the N poly gate is larger than in the Si body 2 7 Gate Bias Dependences Recall from Elec6700 that at ohmic contacts no deviation from equilibrium is allowed This means that both n and p values are kept at their equilibrium values determined by doping at the contacts Also recall that Efn and Efp must then be equal at the contact points In the MOS structure there is no gate current for ideal gate oxide Therefore Efp and Efn are spatially constant in the N poly gate The Ef difference between the gate and the body contact the contact points only is set by the applied bia
23. section 3 2 Short Channel MOSFET on page 175 There is not much discussion on halo doping other than a brief mentioning in passing in the later sections 9 4 TCAD Simulations Required You pretty much can take the existing tdr files and existing command files to practice this yourself To see obvious short channel effects try simulating Id Vg and Id Vd with the tdr files saved for the 45nm and lum MOSFETs Try varying the halo doping level A low halo doping of 1el6 is used as no halo in this chapter The default halo doping is 1 5e18 95 devices Documentation Release 1 0 Below I will focus on the 45nm and lum comparison at Vg 0V Vd Vdd 1 2V for both with and without halo doping 9 5 2 D Potential Contours and Ec Let us consider non halo devices first Launch tecplot_sv load in the tdr files for non halo 45nm and lum devices at Vg 0V and Vd Vdd 1 2V Choose your settings so that you can see the actions going on in the channel region Make x and y axis independent in axis settings so that we can maximize the screen space Most of the action is at the surface so we want to use our vertical space to show only the actions at the surface Similarly use different x axis range for short channel and long channel devices at least do this for the contour plots Then take a 1D cut along the surface Play with your settings for best visual effects The 2 D potential contours and surface conduction band energy plots for
24. sv inspect 4 3 Overview See lecture notes on 3 terminal and 4 terminal MOS devices 4 4 Files You Need Download the files from our class sites Use the large file which has more up to date contents If you home directory is small download it to a PC first and pick files you need You can take out the cmd files and par files and run them to generate all other files you need Once you download the file go to file browser then right click 1 Extract here Typically you should put it under your home folder for ease of access then do extraction 29 devices Documentation Release 1 0 4 5 Meshing To generate the mesh first edit structural parameters in the halomosfet_sde cmd file In a terminal cd to the source file folder just run gedit halomosfet_sde cmd amp For now you do not have to change anything You should find the script is written such that you can modify structural parameters easily After editing save the file You do not have to close the editor as it is running in background Next run sde 1 halomosfet_sde cmd You will see sde working to generate the MOSFET mesh You can then close the sde program At this point you can also use tecplot_sv to inspect the structure produced 4 5 1 Halo Doping One important feature to notice is the placement of halo doping a pocket of relatively high concentration p type dopants near the source and drain This is important to limit the depletion t
25. the 45nm and lum devices are shown in figure 9 1 Biasing conditions are Vg 0V and Vd Vdd which represent the worst case from a standby power standpoint in VLSI circuits 001 nmos_physics IdWd_n327_0000_0006_des idr 0 0 002 nmos physics ldvd n201 O000 O006 des ldr 0 0 003 Y Slice 1 001 nmos_physicsildVd_n327_0000_0006_des idr 0 0 Conduct ionBandE rergy 00 11 rm ce pnysce ldvd n327 0000 0006 desiur 0 01 Y 18 07 CorductionBeng 01_0000_0006_destdr 0 01 Y 12 07 92 92 YA 95 08 ConductionBandE nergy e V a 05 9 5 1 9 X um Figure 9 1 2 D potential and 1 D surface conduction band energy along channel comparison between 45nm and lum devices Vg 0V Vd Vdd You could of course also plot out conduction band contour plots I have indeed done so Personally I find it more visually pleasant to look at potential contours and surface conduction band energy plots 96 Chapter 9 Short Channel Effect and Reverse Short Channel Effect devices Documentation Release 1 0 I have forced tecplot_sv to use the same contour levels in both channel lengths to ease comparison This is not default setting so you want to keep this in mind in future comparisons A number of useful observations can be made 1 Surface potential in the lum device is well behaved uniform along the channel Potential contours are largely parallel to the surface Potential in the channel is much higher in the 45nm device
26. the electric field in the oxide and near the two interfaces in figure 2 7 6 2 7 Gate Bias Dependences 23 devices Documentation Release 1 0 EleFie 1 Multi Multi A2 O E field is discontinuous at oxide Si interfaces 24 Chapter 2 Semiconductor Fundamentals Illustration with TCAD CHAPTER THREE MOSFET SPLIT CV SIMULATION 3 1 Objectives learn the basic flows of running device TCAD perform split CV simulation vary parameters of MOSFET structure to see impact on CV using split CV to understand poly depletion effect get a feel of computing via command lines get to know various scripts 3 2 Required Programs sde sdevice tecplot sv inspect 3 3 Overview See lecture notes on mos capacitor and mosfet capacitors 3 4 Files You Need the structure specification and mesh generation command file There are two versions You have used the version with graphical user interface to input structural parameters which can also be downloaded here mos fet scm The other version does not use the GUI Instead you will use a text editor to change the parameters See the tutorial below That file can be downloaded here mosfet_fixed scm e In the mosfet fixed scm file an inspection of the program will quickly show that the variables have the following meanings wl Substrate Width 25 devices Documentation Release 1 0 w2 Gate Width w3 Spacer Width
27. wish but each person needs to produce plots and analysis by himself herself Olive George Wei chuang Jingshan Follow the notes above and repeat these plots and write down analysis as well as observations for Vg 0V and 0 6V Associate the plots with your understanding and theory in any way you can Save each plot as a png file as well Name each plot meaningfully Zhenzhen Kun Fang Ruocan Repeat these plots for the tdr files generated from running idvglin des ocmd and write down analysis e David Suraj Pingye Zhen Repeat these plots for the tdr files generated from running idvgsat des cmd and write down analysis Of course you can choose to work on all of them as well 46 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics CHAPTER FIVE PHYSICS SELECTION EFFECT ON ELECTRICAL CHARACTERISTICS AND TRACKING POSITION DATA 5 1 Objectives continue to develop physics understanding learn how to change physics models track internal physics quantities as a function of bias better understand how mobility changes affect I V understand low field mobility choices explore velocity saturation high field mobility impact go and find the manuals download a copy The directory is given below 5 2 Required Programs sde e sdevice tecplot_sv inspect 5 3 Overview See lecture notes on 3 terminal and 4 terminal MOS devices 5 4 Files You Need You can use the sam
28. 2 e c n 1F 8 a 1E 9 1E 10 1E 1 1E0 Gate Length um Figure 8 2 Ioff vs lgate from 30nm to lum 8 4 Gate Length Impact 89 devices Documentation Release 1 0 8 4 3 On State Currents and lon Press Ctrl C for next plot IdSat nMOS gt IdLin nMOS 0 0015 0 001 Drain Current A um 0 0005 Co e 1E 1 TED Gate Length um Figure 8 3 I vg vdd vs lgate from 30nm to lum I vg vdd vd vdd is called Ion 8 4 4 loff vs lon 8 4 5 Gm vs Igate 8 5 Operating swb You can refer to the swb user guide located in that same folder as sdevice swb_ug pdf for more information on using swb For your class project of IdVg_lin simulation you can modify the Vd used in the Vg sweep There are a few ways to do this L The simplest way is to just modify the value of the parameter Vdlin from 0 05V to say 0 5V To modify the value of Vdlin select it The right click Edit values as shown below Remember to preprocess and then run the IdVg lin swb nodes involved Hole control to select multiple nodes 90 Chapter 8 Gate Length Scaling on Transistor Electrical Performance devices Documentation Release 1 0 Press Ctrl C for next plot PEST 1E 6 1E 7 Ioff CA um 1E 8 1E 9 1E 10 1E 11 0 0005 0 001 0 0015 Ion A um Figure 8 4 Ioff vs Ion from 30nm to lum I vg vdd vd vdd is called Ion 8 5 Operating swb 91 devices Documentation Release 1 0 emSat nMOS eml
29. 9 2 65nm short channel Surface potential ElectrostaticP otential 001 uguof physics Idvd n36 0003 0006 des tdr 0 0 Y 1e 07 ElectrostaticP otential 902 uguof physics Idvd n38 0003 90996 des tdr 0 0 Y 1e 07 Figure 6 22 Surface potential along channel lgate 65nm Surface eVelocity Surface eCurrentDensity 6 10 Homework Play with the swb project save graphics and write up any analysis you come up on the impact of velocity saturation e g dependence on Lg Vd Vg You can look at internal velocity too even the tdr files This will get you ready for our mid term project 80 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 003 Y Slice 1 001 ugucl physics ldvd n36 00023 0006 des idr 0 0 ev elocity DO 1 uguofphysics Idvd n36 0003 0006 des tdr 0 0 Y 1e 07 eV elocity 002 uguof ahysics Id vd n38 0003 0008 des tdr 0 0 Y 1e 07 Figure 6 23 Surface evelocity along channel lgate 65nm 6 10 Homework 81 devices Documentation Release 1 0 eCurrentDensity 001 uguof physics Idvd n36 0003 0006 des tdr 0 0 Y 1e 07 eCurrentDensity 002 uguof physics Idvd n38 0003 0006 des tdr 0 0 Y 1e 07 2 5E408 1 5E408 Figure 6 24 Surface Jn along channel Igate 65nm 82 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um CHAPTER SEVEN MODERN CMOS TRANSISTOR PHYSICS USING PERFORMANCE PARAMETRIC ANALYSIS 7 1
30. CITY SATURATION EFFECT EXPERIMENTS 45NM 2UM 6 1 Objectives set up your bashrc to use Sentaurus tools 2011 9 learn how to load in Sentaurus Work Bench swb Project learn how to use swb examine effect of velocity saturation on Ids Vds Vdsat Idsat better understand what happens beyond saturation 6 2 Required Programs sde sdevice tecplot_sv inspect swb 6 3 Overview See lecture notes on 3 terminal and 4 terminal MOS devices 6 4 Getting the files First log on to niu003 eng auburn edu Then in a command terminal run cd 57 devices Documentation Release 1 0 This ensures you will change to home directory Then run scratch getfiles sh This will copy a file physics gzp to your home folder and update your bashrc so that you can now use the Sep 2011 version of the tcad tools As this is an existing window we need to source the bashrc file Just run source bashrc To launch swb run swb 6 5 Loading in a swb project To load in the physics gzp project first look for the file physics gzp as shown below in swb s file browser S untitled SWB niu003 eng auburn edu vF 2011 09 12 Project Edit Scheduler View Scenario Tool Parameter Experiments Nodes Variables Extensions Help eo HX 4 KA _ Project Scheduler Bj nsreco1 nsrec03 el nsrec99 No Tools No Variables 19 09 oldcapture EU paper Fa ihysics qzp 1 9 pic Pictures E
31. Curr nt e s p uoo s Ey o Rr RR SR S UR p EN 4 8 Probing Internal Physics for Understanding 49 HOMEWORK 403m a 4 Eck S ese ete RUSSES deum mum err xe Physics Selection Effect on Electrical Characteristics and Tracking Position Data Dil Objectives se eben os nom X y ee da ee E e voee a ec VOR eo e ale 3 4 lRequmed ProStreet a 33 sOVENVIEW a e a E a a E EE SA Files You ANA Se ede DAR ds E MEC M we Oe Bh ante AA Wa eae ao oe Aes eo eS Se ee 5 6 Sdevice Commands s 44 24 5205 2825 EGER AE EE RGR OE BASES SEH S m O RR OO UU tU j 25 25 25 25 25 26 26 10 11 3 7 E Be ak Ra es a we OR DAR RC US eee Bo Ab a ae Ae Velocity Saturation Effect Experiments 45nm 2um MB CUI IMP Oe dE a ee eee ee ee ee ee 6 2 CRequired POSTAS ttn dade ote a A Gop eine op A we Bice ee 03 OVERVIEW PED C DET 64 Getting the files S xo so de ROUES GEHE OE Phe bie bake eee es CR es 65 Loading m aswb project 4 5 seb i e egeco ko ink GE memo e Gh d A Be A expe d 6 6 Mesh fone cee E TIT 6T CS VA CUIVES o e io tek ro LILT TTTT 6 8 Lateral field and VelocityatMidChannelPoint 6 9 Inspecting Internal Details oos p ss Ro nm Ro eR eS eg m n 6 10 Homework es xu REOR em Re RO TEUER E SCR oe d oe e Rm E eux grecs Modern CMOS Transistor Physics Using Performance Parametric Analysis MEO TL 2 2 ei ee e Be Gees a RS ee BS Bs
32. Ene S Multi Multi X Q 12 hGuFerEnet B Multi Multi X Q 12 hQuFerEnet 7 Multi Multi X Q 12 Figure 2 13 Hole quasi Fermi energy distribution for all gate biases Observe that inverting quasi Fermi potential expressed in V gives quasi Fermi energy in eV 2 7 4 Band Diagrams Now let us look at the band diagrams for all biases shown below in figure 2 14 The nearly flat curves in the silicon substrate are the quasi Fermi energies of electrons and holes with a very small separation due to the small 0 05V Vds For all practical purposes just view them as spatially constant and equal to 0 eV the substrate terminal s applied voltage or its inverse strictly speaking Observe that for Vgs gt 0 4V just a little bit more band bending occurs with further increase of gate voltage This is because the surface electron density n is already very high any small increase produces enough negative electron charge to shield the vertical gate field Again recall the letter n means negative Much of the further voltage drop occurs now in the gate oxide as indicated by the increasing slope of the band bending inside the thin gate oxide A plot of Ec alone is shown in figure 2 15 You might better see the difference in band bending amount between the region inside the gate oxide and the region near the Si surface from the Ec plots 16 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0
33. F pictures 3 pisces2et eS Pout Pin zip C power Y pub 3 Public publication C gingging t E ram 3 reportjin zip 3 Reporttolntel zip t3 RF Roadmap zip 23 rfic zip t3 RFIC figure zip e rficfig zip rickey 3 rsd seema e o seu sic sige Y sige_spice sigec C3 sigehp C sigepaper Y simulation smart ftp i spara Ad e8 SParms zip EI gt spectre runi AAA T AA No project Create or open a project none queued ready pending running done ATEN aborted virtual pruned orphan Figure 6 1 locate project archive Right click the file select open you should see 58 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 untitled SWB niu003 eng auburn edu vF 2011 09 Project Edit Scheduler View Scenario Tool Parameter Experiments Nodes Variables Extensions Help B amp x x O IES Projects Gp nsreco1 C nsrec03 J nsrec99 4 oldcapture El 52 o m The file home tcad2 niuguof physics gzp contains packaged SWB projects pic Pictures Open Unpack a selected project into a temporary directory and open it pictures Save As Unpack and save selected projects directories piscesZet Extract All Unpack and save all projects direct
34. Release 1 0 Similarly we can determine Ev alignment between two material We need to account for the band gap difference in addition to electron affinity difference Electron affinity and band gap differences will also be used to determine band alignments at heterojunction interfaces as well So keep this in mind 2 X Slice 1 Ele Aff 1 MultiMultiX 0 Figure 2 4 Electron affinity 2 6 Zero Bias 2 6 1 Electrostatic Potential Consider zero bias at all terminals There is still built in potential The most convenient reference is a piece of intrinsic semiconductor in TCAD Hand analysis in textbooks however uses different reference This is very important to note so that you know precisely how to associate simulation results with first order theories in textbooks For example in the p body potential is 0 45 eV as its potential is lower than that of an intrinsic piece by 0 45 eV 2 6 2 Band Diagrams with Vacuum Level The quasi Fermi potentials at all contacts are simply equal to the applied voltages Since we are applying zero voltages at both gate and body the quasi Fermi potentials are zero 2 6 Zero Bias 7 devices Documentation Release 1 0 2 X Slice 1 ElePot 1 Multi Multi X Q Figure 2 5 Electrostatic potential Note reference is the potential of an intrinsic semiconductor under zero applied bias 8 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Docum
35. ade the same to allow comparison of depletion thickness 3 The x axis scale for the lum contours is set to a larger value than for the 45nm contours to make the whole channel visible Default is the same x axis scale for short and long channel which means you can only see the center portion of the longer device Without halo in the 45nm device the whole area between source and drain is flooded with high potential and the depletion region is much thicker as indicated by the white curve the depletion boundary Source drain s control over the channel is effectively reduced by the halo doping In the lum device depletion thickness is clearly reduced in the halo doping region The depletion boundary moves upward right where the halo doping is Note The increase of Vth with decreasing gate length is due to an increase of the average channel doping as well as the reduced short channel effect Again this is an approximate picture as the doping is not uniform along the whole channel laterally 9 9 Reverse Short Channel Effect RSCE An inspection of figure 9 5 immediately shows the signature of halo doping that is an increase of threshold voltage with decreasing channel length known as reverse short channel effect RSCE as it is opposite to short channel effect i e decrease of threshold voltage with decreasing gate length For shortest gate length Vth starts to decrease again 9 8 How Halo Helps 101 devices Documentation
36. ases first due to the rising average channel doping because of the halo doping but eventually decreases with further scaling down of Igate due to the increasing impact of the drain to channel junction on surface potential with decreasing gate length You can examine the tdr files as necessary for deeper insights 88 Chapter 8 Gate Length Scaling on Transistor Electrical Performance devices Documentation Release 1 0 I suggest that you plot out the surface doping or near surface doping along the channel It is a 2D effect yes But a 1D plot along the channel at the surface will allow you to better see the numbers and how the doping along the channel changes as you scale down lgate Once you are in tecplot_sv and have made the cuts it is easy to quickly inspect other variables like potential and n Save some plots you should then be able to link what happens microscopically inside your device with its electrical characteristics at the terminals Such insights will also be very useful later on in our next semester s Elec7710 class on more advanced topics including device design and compact modeling You can also change halo doping level or make 1t very low compared to substrate doping and then see how your results change Below are more plots from running the Roll off node I am going to leave analysis to you for now 8 4 2 Off State Current loff Press Ctrl C for next plot ail 1E 5 S 1E 6 M c gt 4E 7
37. ces Documentation Release 1 0 IdVd Lg 0 5 VYe 1 20 0 0003 Vg 0 90 Ve 0 60 Ye 0 30 Vg 1 20 Vg z0 90 Ye 0 60 Ve 0 30 e 2 0 0002 S c D ra 5 o c hu c a 0 0001 0 5 1 Drain Yoltage Y Figure 6 7 Id Vd lgate 0 5um 64 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 Velocity saturation occurs at a smaller Vd than drain end channel pinch off therefore Id starts to saturate earlier with velocity saturation Now pay attention to the Vds at which saturation starts to occur or Vdsat for the same gate voltage as gate length varies further 6 7 4 0 35um or 350nm IdVd Lg 0 35 0 0004 0 0003 0 0002 Drain Current um 0 0001 0 0 5 1 Drain Yoltage Y Figure 6 8 Id Vd Igate 0 35um 6 7 Id Vd Curves 65 devices Documentation Release 1 0 IdVd Lg 0 18 VYe 1 20 Ve 0 90 0 0006 Vg 0 60 Ye 0 30 Vg 1 20 Vg z0 90 Ye 0 60 WYe 0 30 0 0004 Drain Current A um 0 0002 0 0 5 1 Drain Yoltage Y Figure 6 9 Id Vd Igate 0 18um 66 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 6 7 5 0 18um or 180nm 6 7 6 0 13um or 130nm IdVd Lg 0 13 0 0006 0 0004 Drain Current A um 0 0002 0 Dag 1 Drain Yoltage Y Figure 6 10 Id Vd lgate 0 13um 6 7 7 0 065um or 65nm Now you can summarize how the impact of velocity sa
38. ces Documentation Release 1 0 008 Y Slice 11001 ample mostetd Vd nibb 0003 0000 des idr 0 0 Figure 4 5 Surface potential along channel Vg 1 2V Vd from 0 to 1 2V 36 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 008 Y Slice 1 001 ample mostetd Vd nibb 0003 0000 des idr 0 0 Figure 4 6 Ec along channel Vg 1 2V Vd from 0 to 1 2V 4 8 Probing Internal Physics for Understanding 37 devices Documentation Release 1 0 Conduction Band Energy Journey of Electron This pretty much correspond to the surface potential plots Electrons in the N source move from the source to the channel and drift down hill towards thee drain Note the sharp band bending near the drain after Vd is above 0 8V The Ec in the active channel region no longer changes much after saturation Channel Length Modulation The point at which we see rapid change of Ec moves towards the source a little bit wiht increasing Vd This is known as channel length modulation Electrical channel length decreases a bit with further increase of Vd after saturation causing the drain current to increase slightly In circuits this will cause some output conductance or a finite amount of output resistance limiting the so called open loop voltage gain of a transistor amplifier eQuasiFermiPotential Recall that at strong inversion which is the case for the whole channel except for
39. ch off this high field region near the drain is more properly called velocity saturation region VSR eVelocity vs Ex Can you think about why the Ex plot does not have exactly the same shape as the eVelocity plot Hint think about mobility and how mobility changes with increasing Vg Note Answer The decrease of mobility with increasing Vg recall the surface roughness effect and the Enormal dependence we investigated earlier caused this difference See also if you can correlate the velocity plot to the Id Vd plot shown above for 2um Does it make sense to you The eVelocity in the linear operation region is clearly higher for lower Vgs but Id in the linear region is still higher for higher Vgs can you think of a possible reason Note Inversion charge density increases with increasing Vg This increase dominates over the decrease of eVelocity so the net result is still increase of drain current with increasing gate voltage 6 8 2 65nm At 2um velocity saturation is not significant for most part of the channel if you use tecplot_sv to look at the velocity vs x plot Let us look at the mid channel point eVelocity at Mid Channel We now clearly see the strong impact of velocity saturation on the electron velocity at mid channel point that is velocity at higher Vds is much reduced with velocity saturation compared to without velocity saturation If we repeat the plots for other gate lengths as we did for Id Vd above
40. cumentation Release 1 0 8 X Slice 1 5E 19 1E 20 1 5E 20 2E 20 2 5E 20 3E 20 SpaChar Multi MultiX 20 12 SpaChar Z Multi Multi X 20 12 SpaChar 3 Multi Multi X 20 12 SpaChar 4 Multi Multi X 20 12 SpaChar 5 Multi Multi X Q 12 SpaChar B Multi Multi X 20 12 SpaChar 7 Multi Multi X 20 12 Figure 2 19 Space charge density distribution for all gate biases 22 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 2 7 6 Electric Field The e field distribution should not be surprising Once surface is heavily inverted the surface e field increases strongly however near the surface only so that there is large surface e field increase but little surface potential increase as shown below in figure 2 20 8 X Slice 1 Figure 2 20 Vertical electric field distribution for all gate biases At this point I would like to remind you of the boundary condition for electric field at the gate oxide Si interfaces Assuming there is no interface charge i e the interface is clean and free from interface charges fixed or variable the normal component of electric field should be continuous across the interface As dielectric constant of oxide is 3 9 while that of Si is 11 7 there is approximately a 3 times difference between the oxide field and the Si surface or interface field To show this I have made a zoomed in plot of
41. devices Documentation Release 1 0 Guofu Niu December 06 2011 Overview Ld Objectives 2 45204 8a eR eS ER eS SR Ee OR EA ENS 12 NOES ice es 3 we RS Bie A a SS IU ESAE Sis CONTENTS Semiconductor Fundamentals Illustration with TCAD 2 1 2 2 2 3 2 4 2 5 2 6 2 7 ODIECHIVES TEL Required Protams os o ee AREA Xm ERA ee xe e OR ee s OVEIVICW voe or utat dex uve oes ae Mi EI p d d ees M eR M Ue di Device SHUCHITE x Lecce t exe REA UR EIE RUE S Ru EIE MR Aa RU x d Material ParameltetS s sop ao edo mele Er ie La Re Sere beni e Deae eS i ZETO Blas uo doro Xt SP SOR SENE TE XB edu ITE He ae EE MOSFET Split CV Simulation Sill Objec yes ike a a e e MUR RUE oko RU Re b Re a Ed 3 2 Required Protams oco 4s no ro oom o koe oe ec ocv op y pes s 33 COVEIVISW as iso heise ds He he beh So ae TRITT 3 4 les YouNeed 52 64 44 2884 eL ROB 29844 e ew eke Ser S E E CR GS 3 39 Video Tutorial use duh Aree week dea SU due eae es bc Be eK DE IS T r MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics ALO 3ODbJectves soo moms Romo xs Ro ome RO RU bw domo e EORR E MU EC eG be eed os 42 Required Programs uoce eeu mo eem Er RT RC ED ee ee eddie es GO EORR 43 JOVCIVIEW x nos Ex RAO oe OE REESE RM Ee d eo eee ee A SE 44 Files YowNeed a de RO RC Ge RA i RG RR LS 45 Meshing oc 3 cea bee ee eA Ron EORR RUE ee ba eae eA he o Rs 4 6 Simulatm o yss aa Pe BE a Se e a AA 47 TY Plotting and Unit of
42. dr 0 01 1 2 td 0 0 Y 10 15 Y 1e 15 0 9 Y21e 15 eQuasiFermiPotential 99 11 2d mosex ample mostet n155_de eQuasiFermiPotential 9021 mosfet pnumotb n165 des tdr 9 eQuasiFermiPatential 9031 mosfet muvertical n 155 des t 9 5 1 o x um Figure 5 6 eQuasiFermiPotential vs x comparison L lum Think about why 5 7 Homework Start with this We will turn this into a midterm project next week Try a 45nm 65nm or 90nm device with the mobility choices given above Keep high field saturation turned off for now Compare Id V g linear saturation and Id Vd curves Turn on and off the two high field saturation switch with all other options in Mobility section turned on Do this for 90nm and lum Compare Id Vd curves by overlaying them Do this one gate voltage at a time Try to track lateral field Ex and velocity at the center of channel at surface as a function of Vd at the highest gate voltage 54 Chapter 5 Physics Selection Effect on Electrical Characteristics and Tracking Position Data devices Documentation Release 1 0 phumob enormal phumob 0 0006 0 0004 TotalCurrent A 0 0002 0 0 5 1 OuterVoltage V Figure 5 7 Mobility effect on Id Vd characteristics L 1um 5 7 Homework 55 devices Documentation Release 1 0 56 Chapter 5 Physics Selection Effect on Electrical Characteristics and Tracking Position Data CHAPTER SIX VELO
43. e BEA BR He eR Mee eR SOR ee Ee ee 109 Ua Nia AMPM e 2 B lt 2 4d bes A BG E Sees d Ae Bene 110 11 17 Dram Current Thermal NOISE i ue al e Ra OE SUR RAS ae Bee a 110 CHAPTER ONE OVERVIEW 1 1 Objectives To provide an overview of the history and recent development in semiconductor devices with emphasis on Five imperfections underlying the usefulness of semiconductors The two letters P and N Diffusion and drift of carriers Bipolar and field effect transistors Scaled sub 100nm devices Bandgap engineering 1 2 Notes l overview devices Documentation Release 1 0 2 Chapter 1 Overview CHAPTER TWO SEMICONDUCTOR FUNDAMENTALS ILLUSTRATION WITH TCAD 2 1 Objectives Understand quantitatively how fundamental material parameters vary in semiconductor e g band gap electron affinity dielectric constant Understand relationships between various potentials and energies important for understanding device operation Understand how biasing affects various potentials and energies at device terminals ohmic contacts ntroduce essential concepts of surface charge modulation 2 2 Required Programs tecplot sv 2010 version 2008 version may work as I use latest features of Sentaurus I did not check this The cmd files did not work with sdevice 2008 As of 8 21 2011 there is issue with running tecplot sv on the engineering Linux workstations I have reported the problem and hopefully the issu
44. e a new folder or sub folder for different options as files with the same names will be overwrit ten Instead of changing all file names in your command files you can simply create a new folder with names like muvertical or phumob to indicate what the folder is about 50 Chapter 5 Physics Selection Effect on Electrical Characteristics and Tracking Position Data devices Documentation Release 1 0 Of course do not forget about changing the content after you create or duplicate the folder content via copy and paste 5 6 2 Tracking Data at a Position Varying with Bias A very advanced option in running TCAD simulation is to track how the internal physics data e g mobility or velocity at a given position changes with bias This can be very useful for insight For instance one can look at how eVelocity changes with high field saturation on and off at different points along the channel One will see different degree of velocity saturation In our case let us plot out a few quantities at the center of the channel between source and drain at the surface As y 0 is not so good a choice because it can be treated as inside the oxide by the simulator let us use y 1e 7 instead It ensures we are going to be looking at a point really close to surface but inside Si This is achieved above by these lines CurrentPlot eMobility 0 0 0000001 ElectricField Vector 0 0 0000001 evelocity 0 0 0000001 ElectrostaticPotential 0 0
45. e files used previously for Id Vd and Id Vg If you do not have them download them We will modify them a little bit as we demoed in class 47 devices Documentation Release 1 0 Download the files from our class sites Use the large file which has more up to date contents If you home directory is small download it to a PC first and pick files you need You can take out the cmd files and par files and run them to generate all other files you need Once you download the file go to file browser then right click Extract here Typically you should put it under your home folder for ease of access then do extraction 5 5 Meshing To generate the mesh first edit structural parameters in the halomosfet_sde cmd file In a terminal cd to the source file folder just run gedit halomosfet_sde cmd amp For now you do not have to change anything Default gate length is 1 0um You can change it to another value e g 90nm to look at impact of gate length You should find the script is written such that you can modify structural parameters easily After editing save the file You do not have to close the editor as it is running in background Next run sde 1 halomosfet_sde cmd You will see sde working to generate the MOSFET mesh You can then close the sde program At this point you can also use tecplot_sv to inspect the structure produced 5 6 Sdevice Commands Recall that we have three des cmd files Let us take the
46. e will be resolved soon I will then supply you with the necessary files and give you a live tutorial on how to inspect TCAD simulation outputs To keep it manageable we will focus on using existing codes provided so that you can use TCAD to understand devices without having to spend a lot of time putting together working TCAD input decks or coding 2 3 Overview There have been many good books on semiconductors and devices you can refer to for theories In this lecture we will look at a concrete numerical example using TCAD with a 1D cut done on a 2D MOSFET structure By design we will simulate the polysilicon gate as polysilicon rather than a piece of ideal metal gate with an artificially adjusted work function This is a much better approximation to reality and allows the important polysilicon gate depletion effect to be correctly accounted for This choice has a unique advantage of allowing easy visualization of effects of bias on quasi Fermi potential energies and potentials at device terminals The easiness is a result of zero current flowing vertical through the MOS struc ture The quasi Fermi potentials or energies are therefore spatially constant in the polysilicon gate and thus easy to visualize For similar reasons we can see the impact of bias on potentials clearly this way Let us first look at structure and material parameters devices Documentation Release 1 0 2 4 Device Structure 1 jeaching 2dmosexampleinS7_des_
47. efined by p n NdPlus NaMinus is shown in figure 2 19 A linear y axis scaled is used by design here to make the point that a high spike of positive charge density exists near the gate oxide interface These positive charges are due to depletion of the N dopants in the N poly gate Even with an extremely heavy 1e20 gate doping we are still seeing quite a bit poly depletion As we will learn later and some of you might intuitively expect just by inspecting the above plot the thickness of poly depletion is comparable to the very thin gate oxide thickness This effectively degrades the gate capacitance as the depletion layer is in series with the gate oxide 2 7 Gate Bias Dependences 19 devices Documentation Release 1 0 8 X Slice 1 eDet1 Multi Multi X Q 12 eDe 2 Multi Multi X 0 12 eDe 3 Multi Multi X 0 12 eDelt4 Multi Multi X Q 12 eDe S Multi Multi X 0 12 eDet5 Multi Multi X Q 12 eDe 7 Multi Multi X Q 12 Figure 2 17 Electron density distribution for all gate biases 20 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 8 X Slice 1 hDett Multi Multi X Q hDe 2 Multi M ulti X 0 hDe 3 Multi M ulti X 0 t hDe S Multi M ulti X 0 hDe 6 Multi M ulti X 0 hDe 7 Multi M ulti X 0 hDe 4 Multi Multi X Q Figure 2 18 Hole density distribution for all gate biases 2 7 Gate Bias Dependences 21 devices Do
48. electrons The electron quasi Fermi energy distribution for all gate biases are shown in figure 2 12 Observe that inverting quasi Fermi potential expressed in V gives quasi Fermi energy in eV 2 7 Gate Bias Dependences 13 devices Documentation Release 1 0 8 X Slice 1 hQuFerPot 1 Multi Multi X Q 12 hQuFerPot 2 Multi Multi X 20 1 2 hQuFerPot 3 Multi Multi X Q 1 2 hQuFerPot 4 Multi Multi X 20 12 t t t hQuFerPot 5 Multi Multi X 20 1 2 hQuFerPot amp Multi Multi X Q 1 2 hQuFerPot 7 Multi Multi X 0 1 2 Figure 2 11 Hole quasi Fermi potential distribution for all gate biases 14 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 8 X Slice 1 eQuFerEnet t Multi Multi X 20 12 eQuFerEne 2 Multi Multi X Q 12 eQuFerEne G Multi Multi X Q 12 eQuFerEne 4 Multi Multi X Q 12 eQuFerEne 5 Multi Multi X Q 12 eQuFerEnet6G Multi Multi X Q 12 eQuFerEne 7 Multi Multi X Q 12 Figure 2 12 Electron quasi Fermi energy distribution for all gate biases 2 7 Gate Bias Dependences 15 devices Documentation Release 1 0 holes The hole quasi Fermi energy distribution for all gate biases are shown in figure 2 13 8 X Slice 1 hGuFerEne t Multi Multi X 0 12 hGuFerEne Z Multi Multi X Q 12 hGuFerEne Multi Multi X Q 12 hQuFerEne 4 Multi Multi X Q 12 hQuFer
49. entation Release 1 0 Quasi Fermi energy is simply the inverse of quasi Fermi potential if you use eV for energy and V for potential There is built in potential between the N polysilicon gate and the p body Potential is higher in the N poly gate lower in the p body Therefore the Ec at the gate is lower than the Ec deep in the body I have also calculated the vacuum energy level which is simply equal to Ec affinity The vacuum energy level is no longer spatially constant because of the built in electric field The gradients of Ec Evac Ev are all the same determined by electric field Electron affinity and band gap differences will also be used to determine band alignments at heterojunction interfaces as well So keep this in mind 2 X Slice 1 oo eQuFerEne t Multi MultiX Q hQuFerEnett MultifMulti X 0 ConBanEne t Multi ulti X Q ValBanEne Multi Multi X Q Y M Multi Multi X 20 Figure 2 6 Band diagram with Evac the vacuum energy level 2 6 3 Band Diagrams with Intrinsic Fermi Level Often we do not draw the vacuum energy level despite its great importance described above We draw only Ec Ev Efn and Efp That is enough information as we know n p and electric field from gradient of band edges However often we also draw the intrinsic Fermi level or Ei particularly in hand analysis The reason is simple It allows easy visualization of whether a region is n type or p type In
50. equirement Consider using 65nm or 90nm as your nominal short gate length 180nm or 250nm as mid gate length and then lum or 2um as your long gate length Make 3 folders one for each gate length Use Phumob Enormal and turn on high field saturation of velocity For each gate length required simulate Id Vg at several Vds e g 50mV 250mV 500mV 1 2V You can use more Vds values as needed Plot out Id Vg on both linear and log scales Make observations and give explanations analyze relevant tdr files using tecplot sv as we have done in the past to support your explanations Surface plots i e y cut made at say y le 7 are useful For instance you can compare surface potential plots at all Vg s simulated overlayed at VdzV dd for all 3 gate lengths to explain why SS at Vd Vdd is larger in short gate length transistor Use the currentplot commands to plot out the mid channel point s potential lateral and vertical field eVelocity eDensity etc The subthreshold swing is a good parameter to take notice when examining Vds dependence of Id Vg Look at how your Vth use Vdz50mV SS at Vdz50mV and Vd Vdd Ion and Ioff note for Ion and Ioff Vg Vdd and 0 Vd Vdd change with gate length changed to optional simulate Id Vd Include Vg OV Make observations on the slope of Id Vd particularly in saturation region changed to optional repeat all simulations analyze a selected number of tdr files with velocity saturation
51. es Documentation Release 1 0 As you go along with your exploration save some screen shots for later use I have generated tons of such plots in preparation for this year s lecture alone You likely will need to redo your plots a few times before you are satisfied with its looks 9 6 Id Vg figure 9 3 shows Id Vg at Vd 0 05V and Vdd in lum and 45nm devices with a low halo doping level that is much smaller than substrate doping level We will refer to this as without halo for all practical purposes IdVe Lg 1um and 45nm No Halo 1E 3 seslgsi Vd 1 2 Halo 1016 Lg 1 Vd 0 05 halo 1e16 Lg 0 045 Vd 1 2 Halo 1e16 1E 4 Lg 0 045 Vd 0 05 halo 1e16 1E 5 m Na L 1E 6 D fa 5 o 1E z 3 c 5 1E 3 1E 9 1E 10 0 0 5 1 Gate Voltage V Figure 9 3 Id Vg at Vd 0 05V and Vdd in lum and 45nm devices without halo realized with a low halo doping level Note that in subthreshold region Id is about the same for Vd 0 05V and Vdd in the lum device as expected from ideal long channel transistor subthreshold theory In the 45nm device the Id at Vd 0 05V in subthreshold region shows very weak gate control The situation is even worse at Vd Vdd With a high halo doping level the gate control over in the 45nm device Id is much improved as can be seen from figure 9 4 Id turns off with decreasing Vg much more effectively The drain voltage still has much more impact on subthreshold current than in the lum d
52. evice but gate control is still quite obvious 98 Chapter 9 Short Channel Effect and Reverse Short Channel Effect devices Documentation Release 1 0 IdVg Lg 1um and 45nm Lg 1 Yd 1 2 Le 1 Yd 0 05 Lg 0 045 Vd 1 2 220 045 Yd 0 05 Drain Current A um 1 1 1 1 1 1 4 1 1 1 1 1 i tens oneal 0 0 5 1 Gate Yoltage Y Figure 9 4 Id Vg at Vd 0 05V and Vdd in lum and 45nm devices with a high halo doping level 9 6 Id Vg 99 devices Documentation Release 1 0 Let me point out in passing that in the lum halo device the subthreshold Id at Vd Vdd is higher than at Vd 0 05V by a larger amount than in the lum device without halo This cannot be explained by long channel transistor theory and is unique to halo doping Intuitive explanations were proposed in recent years interested students are encouraged to read relevant research papers 9 7 Threshold Voltage vs Gate Length Historically short channel effect SCE is mainly used to refer to the decrease of threshold voltage with decreasing gate length There are many other physical effects at short gate length of course There were numerous publications on the topic at one time I personally also published several papers on the topic back in the early 90s as a grad student figure 9 5 shows the linear region threshold voltage obtained from peak gm extrapolation as a function of gate length for devices with and without halo doping
53. gnal delay 11 10 Effect of Halo Doping 109 devices Documentation Release 1 0 11 16 Analog Amplifiers How does the gm Rout product change with scaling What is the typical gm Rout number in 45nm and 32nm CMOS 11 17 Drain Current Thermal Noise What is the PSD of drain current noise of a MOSFET in sub threshold region How does it compare to 2qIDS with IDS being the dc biasing current Above threshold voltage in saturation region is the drain current noise smaller or larger than 2qIDS 110 Chapter 11 Final Exam Scope
54. hickness of the lateral n source drain to p channel junction to reduce electrostatic coupling between the source and drain Inside tecplot_sv do a 1D cut of the y axis specify a y location at the surface then observe the plot Due to numerical issues with tecplot_sv you likely will run into trouble with not getting the entire distance along the x axis plotted So I suggest that you use either cut along boundary or simply just give a point right below surface e g y 0 001 The doping variation along the cut line should look like 4 6 Simulating Examine the idvd_des cmd file first As we explained in class for better convergence we do a Vg sweep at zero Vd first save them Then we load each Vg with zero Vd solution and ramp up Vd In this example the source and body are both at zero so you do not see body bias effect at the source end This can be easily changed by modifying the body bias Then run sdevice idvd_des cmd You should see reporting of solution process 4 7 l V Plotting and Unit of Current Examine idvd_ins cmd file first You do not have to completely understand it but just a quick look will give you some useful idea about what it does You may modify it for your purpose You are not required to write such programs Then run inspect f idvd_ins cmd You should see a nice Id Vd plot as follows You might wonder why the unit of current is A um not A Good question indeed This is a 2D simulation we never
55. in at high Vd Again we should understand that electron density does not go to zero anywhere along the channel If it does or it does pinch off completely at any point it would be an open circuit and block current flow 38 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 008 Y Slice 11001 ample mostelAdVd_n165_0003_0000_des dr 0 0 Figure 4 7 eQuasiFermiPotential along channel Vg 1 2V Vd from 0 to 1 2V 4 8 Probing Internal Physics for Understanding 39 devices Documentation Release 1 0 008 Y Slice 1 001 ample mostetd Vd nibb 0003 0000 des idr 0 0 200000 150000 100000 Figure 4 8 Gradient of eQuasiFermiPotential along channel Vg 1 2V Vd from 0 to 1 2V 40 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 008 Y Slice 11001 ample mostetd Vd nibb 0003 0000 des idr 0 0 Figure 4 9 eQuasiFermiEnergy along channel Vg 1 2V Vd from 0 to 1 2V 4 8 Probing Internal Physics for Understanding 41 devices Documentation Release 1 0 008 Y Slice 1 001 ample mostetd Vd nibb 0003 0000 des idr 0 0 Figure 4 10 eDensity along channel Log scale Vg 1 2V Vd from 0 to 1 2V 42 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 _ eDenesily 007 ample
56. in nMOS 0 0015 m o v on Y 0 001 c o e 0 c 5 a _ 0 0005 1E 1 1E0 Gate Length um Figure 8 5 Gm in linear and saturation vs lgate from 30nm to lum 92 Chapter 8 Gate Length Scaling on Transistor Electrical Performance devices Documentation Release 1 0 d Wil nMOS Idvg lin Plc VINA Add Ins Delete Del Properties Cut Ctrl X Copy Ctrl C Add Values Edit Values Remove Value Freeze Rows Columns Unfreeze Rows Columns Hide Show Figure 8 6 Editing parameter value 8 5 Operating swb 93 devices Documentation Release 1 0 Then you should preprocess and run the inspect nodes as well Finally update the variables in swb manually if it has not been set to auto update 94 Chapter 8 Gate Length Scaling on Transistor Electrical Performance CHAPTER NINE SHORT CHANNEL EFFECT AND REVERSE SHORT CHANNEL EFFECT 9 1 Objectives visualizing short channel effects understanding short channel effect understanding reverse short channel effect explore halo doping s impact understand halo doping s impact learn to formatting 2 D contours to make meaningful comparisons between structures 9 2 Required Programs sde e sdevice tecplot_sv inspect 9 3 Reading Assignment Read
57. ld Swing The benefits of halo also show up as much reduced subthreshold swing at shorter gate length as can be seen from figure 9 8 The improvement for Vd Vdd is even more obvious SSsat 1e16 SSlin 1e16 SSsat 1 5618 gt SSlin 1 5e18 Subth Swing mY dec 1E 1 1E0 Gate Length um Figure 9 8 Subthreshold swing SS versus gate length for linear and saturation operation Both halo and non halo devices are shown The physics is similar to how halo reduced short channel effect 9 12 Homework As we have just had a midterm project we do not have any official new homework this week Think a bit more about what you did the doubts you have and how you can better organize your data and plots to support your conclusions Use the suggestions I made during today Nov 4 s lecture I also encourage you to reproduce figure 9 5 yourself I will address issues you may experience next class Read section 3 2 Short Channel MOSFET on page 175 104 Chapter 9 Short Channel Effect and Reverse Short Channel Effect CHAPTER TEN CLASS FINAL PROJECT AND EXAM 10 1 Final Exam The class final exam will be open book open notes open computer and open Internet The problems will mainly come from our notes and homework assignments For instance you may be asked to explain how halo doping affects the threshold voltage versus gate length curve or how threshold voltage choice affects the Ion and loff of a MOS transistor o
58. lity which results in less drive current for the same set of voltages That difference will also change with channel length due to velocity saturation Keep in mind all voltages in your codes need to be multipled by 1 You can plot out 1 Id too as the Id for PMOS will be negative Current going into a terminal is positive in the simulator 7 4 7 High K gate dielectric You can also vary the gate oxide material or simply use silicon diode but modify the dielectric constant value in the parameter file A higher epsilon means stronger vertical field effect which will give you better SS better Ioff and better Ion 7 4 Explorer Further 85 devices Documentation Release 1 0 7 5 Report Use as many pages as you need but think about the best figures to use to support your analysis as well Every figure you put in the report should serve a purpose Always make observerations add analysis use tdr plots as necessary Save all your images as png files You can use word latex or any of your favorite word processor We will devote this week to this project You should have a zipped folder for all your simulations files ready to run Submit your report to me next Monday class time 86 Chapter 7 Modern CMOS Transistor Physics Using Performance Parametric Analysis CHAPTER EIGHT GATE LENGTH SCALING ON TRANSISTOR ELECTRICAL PERFORMANCE 8 1 Objectives The objectives for this project are use swb to manage large co
59. lity to make transistor quality thin oxide was underestimated 11 12 Metal gate high K Why metal gates and high K gate dielectric are used in modern CMOS 11 13 FinFETs Tri gate Nanowire FETs Such structures are all aimed at increasing gate control over the whole Si channel volume which help keeping sub threshold swing SS close to ideal DIBL is minimized and sub surface leakage found in bulk even regular SOI MOSFETs are suppressed 11 14 Vdd Scaling and Multi core Processing Power consumption in CMOS is primarily due to switching P C Vdd 2 f A key point to take away from this equation we derived is that power consumed is not linearly proportional to Vdd rather it is proportional to the square of Vdd This may sound counterintuitive at first but is satisfying if you think about the capacitive nature of the load in CMOS logic circuits The charging current dQ dt on average is also proportional to Q which is CVdd leading to the square of Vdd dependence Instead of running 1 core at full Vdd and full speed f we could run multiple cores at a reduced Vdd and a corre spondingly reduced frequency You should be able to quantify the advantages of such approach in power consumption as well as throughput Multi core processing also facilitates power management as individual cores can be turned on and off See the journal notes for a numerical example 11 15 CMOS Layout Basics Multi finger layout for reducing gate resistance and si
60. mostel idVd_ni65_C003_0006_des 1dr 0 0 0 4 0 6 0 8 1 Distance um Figure 4 11 eDensity along channel obtained using cut along boundary Log scale Vg 1 2V Vd from 0 to 1 2V 4 8 Probing Internal Physics for Understanding 43 devices Documentation Release 1 0 008 Y Slice 11001 ample mostelAdVd_n165_0003_0000_des dr 0 0 Figure 4 12 eDensity along channel Linear scale Vg 1 2V Vd from 0 to 1 2V 44 Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 008 Y Slice 11001 ample mostetd Vd nibb 0003 0000 des idr 0 0 3E 08 2 5E408 2E 08 1 5E 08 1E 08 Figure 4 13 Electron velocity along channel Linear scale Vg 1 2V Vd from 0 to 1 2V 4 8 Probing Internal Physics for Understanding 45 devices Documentation Release 1 0 The so called pinch off is just a crude way of saying surface is no longer in strong inversion Even in weak inversion there are finite electrons A small amount of electrons can travel at very high velocity to still support a large current Again note the high velocity and hence high kinetic energy of electrons near the drain which can hit the oxide and create damages of the gate oxide Si interface 4 9 Homework Pick one of the 3 problems below that is assigned to you and complete it before Oct 14 class time Bring your plots files on a flash drive for sharing You can work in groups if you
61. mplex experiments understand impact of gate length on Vth SS Ion Ioff DIBL etc 8 2 Required Programs sde sdevice tecplot sv inspect swb nmos_physics gzp 25 MB so large from scratch folder 8 3 Get Files To get the swb project file log on to niu003 run cd scratch getfiles sh Then in a terminal run swb Load in the nmos_physics gzp and extract all into a folder of your choice 87 devices Documentation Release 1 0 8 4 Gate Length Impact 8 4 1 Threshold Voltage Roll off and Reverse Short Channel Effect RSCE As gate length scales down from lum to 30nm run all the Id Vg simulations then run the very last Roll off node only the last is meaningful it is a trick to make plots of extracted variables versus lgate You can always open up a spreadsheet move your mouse over one of the icon that says spreadsheet if you wish to do so Follow on screen instruction The 2nd screen plots out the current defined threshold voltage at low Vd and high Vd 50mV and 1 2V vti and DIBL defined as the amount of vti change per voltage change in Vd as a function of Igate Press Ctrl C for next plot DIBL nMOS VtiSat nMOS DA Vtilin nMOS 0 2 0 08 oS H m iv gt p gt 0 06 lt gt M 0 1 0 04 0 02 1E 1 1E0 Gate Length um Figure 8 1 Vti linear Vti saturation and DIBL vs lgate from 30nm to lum We see clearly with decreasing lgate the Vt s incre
62. nd Exam 10 1 Final Exam Ae e ae ih eee medo Eo do uec A Bes eee 10 2 Final Project s sxe e wee hoe Xo 49 eh ee eA RENE ue rome eee RADO b RO ONU E ROAD 10 3 Written Report ese eie mde RR TUR RC DRG Rae ES DUREE TR IRL TUR Rn Final Exam Scope ILI Banddlagrams 23223 A Ae ee ee ERAS E Y EA SO ee ROS Kos ROS She gredi 13 2 Field Effect zooms eode exu MSHS oa RE Ape we EE e e ees 11 3 Threshold voltage i 22 seh kn ped Se ba ea qoem do RU ERES 11 4 Internalspotentialand fields uuo ok de BRAS RNS EA AGS xev s ox e E S BAS S 11 5 Velocity saturation is eoe ku n hib Eo eo b ede Re eC Qood aig de me DAMES dede om i 11 6 Subthreshold swing SS 4 4 qe par UO CUR A ea Re Y 11 7 Toncand Io ss cuc uo doe Rex Boke eth ARS Bel rci RR o e Rte Zoe oS PUR DAR SRL d t ten 57 57 57 57 57 58 60 60 69 73 80 83 83 83 84 84 86 87 87 87 87 88 90 95 95 95 95 95 96 100 101 101 103 104 104 105 105 105 106 11 8 Short chamel effect leer AA 108 1L9 DIBL o io eoe d 6b A REG bw eee Sede bea 108 11 10 Effect of Halo Doping ius cb e wore BO PA eS eS hohem Be eS Red eec 8 109 11 11 Channel length scaling mit ux E HAY Ae See RY CS ee ee oe 109 11 12 Metalicate high ay o goo foe E ke aoe NS Re een os 109 11 13 FinFETs Tri gate Nanowire FETS os e 4 545 beh BG 9 des Oe ba RS RESORT eS 109 11 14 Vdd Scaling and Multi core Processing zb o YR Sx 109 11 15 CMOS Layout Basics cht e
63. nd gate to channel or source threshold voltage for given gate material substrate doping and oxide thickness at different channel to body bias Vcb Reviewing the notes on 3 terminal MOS should be sufficient 107 devices Documentation Release 1 0 11 4 Internal potential and field For a long channel MOSFET sketch how surface potential inversion charge density depletion thickness lateral electric field and electron velocity vary from source to drain at the following biases 1 Vg lt lt Vth Vds 0 2 Vg gt Vth Vds lt Vdsat 3 Vg gt Vth Vds gt Vdsat You only need to sketch the region from source to the pinch off point Velocity saturation can be neglected 11 5 Velocity saturation How does it affect electron velocity along the channel How does it impact Id Vd curves Why is velocity saturation more important in shorter channel devices 11 6 Subthreshold swing SS Understand its definition and how it affects the choice of threshold voltage to achieve a given off current e g Id at Vg 0 has to be less than 1nA if S 100 mV decade what value of Vth should you need in transistor design What is the smallest SS one can achieve For an ideal long channel MOSFET if the surface potential increases by 0 9mV per 1mV gate voltage increase what will the SS be 11 7 lon and loff Understand what determines Ion and Ioff For instance for a transistor with Vt 0 3V SS 90mV decade W 90nm L 45nm
64. ories Pout_Pin zip Cancel Do not unpack the content power pub p Public publication gingging q radhard LULLGLLLLGL SA NA e e DER a 2 5 ES reportjin zip t3 Reporttointel zip 3 RF Roadmap zip t3 rfic zip tS RFIC figure zip t3 rficfig zip Y rickey seema D E 2 B a 5 seu sic Y sige Y sige_spice 3 sigec A C3 sigehp Y sigepaper 9 simulation Y smart ftp spara Ha SParms zip spectre runi No project Create or open a project none queued ready pending running done ed aborted virtual pruned orphan BE Be BE H Hi I I P Figure 6 2 extract project archive 6 5 Loading in a swb project 59 devices Documentation Release 1 0 Select extract all then create new folder or just use default to place the project Wait a little while It is about 25 MB zipped so big You shall see JRome niuguof physics Research Configuration SWBQux200 vF 2011 09 Project Edit Scheduler View Scenario Jool Parameter Experiments Nodes Variables Extensions Help Projects EH hone niu Y 2dmosex C BandDia HE cos ph E CMOSsca INSPECT E Copu of A Desktop sde sdevice inspect 3 Docunen Y Downloai Y Dropbox halo Y Music niuguof A niuguof nmos_ph HE nmos phi ta nmos_ph LE nmos sc 0
65. r how multiple cores help with performance power tradeoff 10 2 Final Project You need to do some literature search and find a topic in the general area of semiconductor devices including but not limited to physics modeling fabrication measurement or simulation of either field effect or heterojunction bipolar transistors Your project should not be just about literature survey and should have a practice component It can be either Sentaurus TCAD simulation or experimental measurement or both You could also choose to expand your mid term project on scaled CMOS physics and characterization and address several additional requirements Below are a few new topics we have touched on recently you may consider 1 Quantum Effect on CMOS Performance You can simulate CMOS performance with and without quantum effects analyze simulations details to support your observations as we have done throughout the semester There are multiple options for simulating quantum effects Look for QuantumPotential and Density Gradient in the sdevice user manual 2 FinFET or Tri gate CMOS There are some examples in the Application Library folder under the installation directory You may choose to use 2 D double gate MOSFET for simplicity 3 Nano wire MOSFETs I had sent you a couple of links earlier by email 4 Low frequency Noise Measurement This can be done with a time domain sampling measurement with a semi conductor parameter analyzer
66. reliability of transistors and CMOS ICs in general 4 8 Probing Internal Physics for Understanding 33 devices Documentation Release 1 0 Tecplot 360 2008 File Edit View Frame Axis Plot Data Slicer adco JAHTA EEEN ALACION mE Read Synopsys File M Filter Name Search 1guof 2dmosexample mosfet bgtdpi dnrealiv rdntf l T Directories zi Se File to be Added 003 0005 des tdr Idvd ni65 0003 0006 des tdr Selected File s 3 Add Remove OK Filter Cancel Figure 4 3 Loading high Vg 1 2V tdr files for different Vd Chapter 4 MOSFET Id Vd Output Curves Simulation and Probing of Internal Physics devices Documentation Release 1 0 a Tecplot 360 2008 J n Ix File Edit View Frame Axis Plot Data Slicer Help adoug a 3 001 ample moslelAdVd_n165_0003_0000_des 1 002 ample mostelAdVd_n165_0003_0001_des 1 KSEE j TE fa ad SIN AACN KX um ji i bd stan xum 004 ample mostelAdVd nib 0003 0003 des 005 ample mostet ld Yd nib amp 0003 0004 desi 006 Fi i AA pe d eae es A a Cut at mouse position dave 14 Number of Cuts 1 LI First Cut At A Last Cut At Merge Zones in t y Cut Zone By Zor Create cul a ET Click to Select Drag to Select Group Figure 4 4 Making y cut at desired location 4 8 Probing Internal Physics for Understanding 35 devi
67. s of the highest Vg tdr files Load them in tecplot_sv as follows Remember to Add the files selected Then OK Then go to slicer gt Orthogonal Cut Select Y as normal direction Deselect Cut at mouse position Set first cut at to desired value e g 0 001 here Then create cut Click on the rearrange frames icon in the tool bar in the top left area of your tecplot window to focus on the cut plot Disable the legends by clicking the legends on off icon Too busy a plot with them By default you see the doping Now you can select other quantities of interest Let us look at a few of them Potential and Field As Vg is high well over threshold voltage with a Vds current flows potential drop varies along the channel The amount of variation is equal to Vds Vd here as Vs is zero At Vd 0 2V 0 4V 0 6V and 0 8V all the Vds drops over the channel region We can see an increase of lateral field with increasing Vd as expected At Vd 1 0V and 1 2V the potential in the channel barely changes and stays about the same as at Vd 0 8V Hot Electrons and Reliability The extra Vd drops in a vary narrow region near the drain a sharp change of potential in a narrow region means high field So keep this in mind ateral field is strongest near the drain after the so called pinch off occurs This also leads to hot electrons which can hit the oxide Si interface causing damages over time This is one of the important considerations for long term
68. s voltage difference 10 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 2 X Slice 1 eDe t Multi Multi X Q hDe t MultiMulti X Q Figure 2 8 n and p at zero bias 2 7 Gate Bias Dependences 11 devices Documentation Release 1 0 If we simply set the Ef at the contacts to the applied bias voltage we can prove that the electrostatic potential at a contact must then be equal to the applied voltage the built in potential of that contact with respect to an intrinsic reference I ll leave the proof to you Stop by if you have trouble doing so The quasi Fermi potentials at the contacts are therefore simply equal to their applied voltage values Now let us keep the body grounded i e at zero bias and vary the gate voltage from 0 to 1 2 V in 0 2 V step Analytical treatment of the ID MOS structure will be made in a few lectures Below we show the internal distribution of physical quantities as a function of gate biases from TCAD A small Vds of 0 05V is applied while the gate bias increases 2 7 1 Electrostatic Potential The electrostatic potential distributions for all gate biases are shown below in figure 2 9 8 X Slice 1 ElePot t Multi Multi X Q 12 ElePot Z Multi Multi X Q 12 ElePot 3 Multi Multi X Q 12 ElePot 4 Multi Multi X Q 12 ElePot S Multi Multi X Q 12 ElePot amp Multi Multi X Q 12 ElePot 7 Multi Multi X Q 12 Figure
69. side and observe their differences Ideally you want to overlay them this is impossible if we make contour plots We might make 3D surface plots instead of 2D countour plots Even this can be hard For MOSFETs a particular 1 D cut of the y axis at the Si surface can be used instead Essentially this shows a cut along the channel from source to drain We can load in the tdr files corresponding to the same Vg and Vd simulated with and without vsat effect make y cut at the surface then compare about everything we are interested in We have in fact made reference to insights gained from such 1D cuts A number of plots are given below to assist understanding 6 9 1 2um long channel Surface potential ElectrostaticP otential 001 uguof physics ldvd n30 Q003 0006 des tdr 0 0 Y 1e 07 ElectrostaticP otential 902 uguoffphysics idvd_n32_0003_0006_des tdr 0 0 Y 1e 07 no velocily saturation wiih vsai Figure 6 16 Surface potential along channel lgate 2um 74 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 eVelocity 001 uguof physics Idvd n30 Q003 0006 des tdr 0 0 Y 1e 07 eVelocity 002 uguof physics Idvd n32 9903 0006 des tdr 0 0 Y 1e 07 no velocily saturation wiih vsal Figure 6 17 Surface evelocity along channel lgate 2um 6 9 Inspecting Internal Details 75 devices Documentation Release 1 0 eCurrentDensity 001
70. t Insert PhysicsSection des ocmd inserts the file PhysicsSection des ocmd whose content is Physics EffectivelntrinsicDensity OldSlotboom Physics Material Silicon 5 6 Sdevice Commands 49 devices Documentation Release 1 0 Mobility PhuMob eHighFieldSaturation GradQuasiFermi hHighFieldSaturation GradQuasiFermi Enormal x Recombination SRH DopingDep Band2Band Note that the at the line beginning is for commenting out the line So by default in the mobility section none of the options is active So default simulation will use a constant mobility We can remove the one by one to produce difference combinations For now let us still keep the high field saturation turned off We will turn on Phumob only and then turn on Phumob and Enormal Physics Material Silicon Mobility PhuMob eHighFieldSaturation GradQuasiFermi hHighFieldSaturation GradQuasiFermi Enormal x Recombination SRH DopingDep Band2Band and Physics Material Silicon Mobility PhuMob eHighFieldSaturation GradQuasiFermi hHighFieldSaturation GradQuasiFermi Enormal x Recombination SRH DopingDep Band2Band We talked about the meanings of these choices in class You can find more information in the sdevice ug pdf manual under linux_apps synopsys v2 5 sentaurus tcad E 2010 12 manuals PDFManual data You may want to creat
71. t RSCE With halo turned on repeat the Id Vg at 50mV simulations for many gate lengths e g 32nm 45nm 65nm 90nm 130nm 180nm 250nm 0 5um lum 2um and Sum Plot out Vth vs lgate Vth will first increase with decreasing Igate and ultimately decrease again at very short gate length You may even vary the halo doping level and see how this vth Igate curve changes 7 4 4 Body Effect So far we have set the body bias to zero You can vary this and see how your Id Vg is changed See how Vth is changed in particular 7 4 5 Poly Depletion Effect Poly depletion effect is real and degrades performance by decreasing the effective gate to channel capacitance Vary the poly gate doping level entry in the sde command file Look up our text book or IEEE explorer for poly gate doping found in real CMOS technologies Try a few values from practical levels to very high e g 1e20 5e20 and see how your Ion and Gm are affected Ultimately you can also use an ideal metal gate in your sde sdevice command files 7 4 6 PMOS While much of our in class discussions simulations have used NMOS we should have equally good understanding of PMOS transistor as CMOS requires both NMOS and PMOS By swapping all the doping types in the sde command file you will get a PMOS transistor You can then repeat simulations You want to compare the hVelocity in PMOS with eVelocity in NMOS to understand the difference Hole mobility is lower than electron mobi
72. tch the Id Vg difference between different mobility choices Why Hint also look at the lateral variation of mobility as we discussed in class Phumob Phumob Enormal Pas 9 18 97 ElectrostaticPotential Idvg_n57_des plt Pos 9 18 097 ElectrostaticPotential Mena Tios an Pas 9 12 097 ElectrostaticPotential Idvg_n57_des plt o 9 2 9 4 0 6 0 8 Quter vaoltage gate Outervaltage 1 Figure 5 3 Phi s Vg linear characteristics L 1um 52 Chapter 5 Physics Selection Effect on Electrical Characteristics and Tracking Position Data devices Documentation Release 1 0 OO rmmosfet constmu Id vg nb7 der pit 1979 Consi Phumob m Phumob Enormal 19 Pos 9 12e 97 eDensity Idvg_n57_des plt Pos 9 1e 097 eDensity TE M aga pit y 1B 19 Pos 9 12e 07 eDensity Idvg_n57_des plt 10 19 5 o 9 2 9 4 0 6 0 8 Cutervoltage gate Outervaltage 1 Figure 5 4 Mobility effect on n_s Vg linear characteristics L 1um eMobjiity 0011 2dmasexamplefmostet m1565_des td 0 0 v21e 15 aoo eMabjlity 0021 mosfet phumot n165 des tdr 0 9 Y 1e 15 eMobjlity 0031 mosfet muvertical n165 des tdr 9 0 Y 1e 15 600 499 200 Figure 5 5 Mobility vs x comparison L 1um Think about how this will affect Id 5 6 Sdevice Commands 53 devices Documentation Release 1 0 004 Shee 1 001s 2dmosessmple mostetini BE des t
73. turation changes with gate length Think about these questions 1 Does the impact on Idsat and Vdsat become stronger with gate length scaling 2 For the same gate length why is the effect stronger at higher Vd 3 For the same high Vd Vdd at the same lgate is the impact on Id stronger at higher Vg or lower Vg Why Consider only the higher Vg values above threshold when the channel is inverted This is a pretty challenging question without a simple answer But I encourage you to think about it and try to make some observations 6 7 Id Vd Curves 67 devices Documentation Release 1 0 IdVd Lg 0 065 0 001 0 0005 Drain Current A um 0 0 5 1 Drain Yoltage Y Figure 6 11 Id Vd lgate 65nm 68 Chapter 6 Velocity Saturation Effect Experiments 45nm 2um devices Documentation Release 1 0 6 8 Lateral field and Velocity at Mid Channel Point Velocity saturation is a high lateral field effect So let us look at how the lateral field in the channel varies with Vd You should turn on the tdr file saving to see position dependence Below are some mid channel point plots made using the CurrentPlot technique 6 8 1 2um Lateral field and eVelocity The lateral field at mid channel for 2um lgate is shown below IdVd Lg 2 2000 1000 Ex at Mid Channel Y cm 0 0 5 1 Drain Yoltage Y Figure 6 12 Ex at mid channel point at surface versus Vd lgate 2um The corresponding eVelocity is
74. turned off Compare results and explain the difference Discuss how velocity saturation affects Ion Ioff Id Vd Idsat and Vdsat in particular SS Vth 7 4 Explorer Further With some changes to the codes provided you can investigate more modern CMOS transistor physics For instance you can look into a selected number of topics that may interest you at your choice 7 4 1 Halo Doping We have seen halo doping s importance from the simulation results I showed with and without halo doping You can do this by varying the concentration of halo doping and run your simulation for 3 gate lengths An extreme case will be to set halo doping to a level that is negligible compared to substrate doping level The sde command file provided has an entry on halo doping level just modify that and you can do this yourself Examine the tdr files as necessary for deeper insights 84 Chapter 7 Modern CMOS Transistor Physics Using Performance Parametric Analysis devices Documentation Release 1 0 7 4 2 Threshold voltage roll off With halo turned off you can run the Id Vg at 50mV simulations at many gate lengths from 45nm to lum record your Vth and SS plot them out as a function of gate length You shall see Vth decrease with gate length due to the increasing impact of the drain to channel junction on surface potential with decreasing channel length Examine the tdr files as necessary for deeper insights 7 4 3 Reverse Short Channel Effec
75. v_des cmd file first Set all voltages to desired values For vp dc make it stop at 3V if you are using thin oxide just a few nm thick You could modify the start gate voltage to say 3V too Then run 26 Chapter 3 MOSFET Split CV Simulation devices Documentation Release 1 0 sdevice split_cv_des cmd You should see reporting of solution process It should take about 1 minute cpu time to finish 3 6 3 Plotting Examine cv_ins cmd file first You do not have to completely understand it but just a quick look will give you some useful idea about what it does You may modify it for your purpose You are not required to write such programs See our notes about how and why we need to take the absolution values of certain capacitances We talked about this in class too For thin gate oxide set the vdd parameter to a value consistent with the vp dc set above in the split_cv_des cmd file Then run inspect f cv_ins cmd You should see some nice split CV plots 3 6 Steps 27 devices Documentation Release 1 0 28 Chapter 3 MOSFET Split CV Simulation MOSFET ID VD CHAPTER FOUR OUTPUT CURVES SIMULATION AND PROBING OF INTERNAL PHYSICS 4 1 Objectives perform Id Vd simulation learn how to save and load solutions for better convergence examine internal physics particularly at the surface better understand what happens beyond saturation 4 2 Required Programs sde sdevice tecplot
76. zero idr 0 0 2 X Slice 1 DopConoet 1 Multi Multi X 0 DopingConcentration cm 3 1 1E 20 12E417 13E 14 1 7E 12 1 7E 15 1 6E 18 Figure 2 1 2D MOSFET simulated and 1D cut at x 0 showing the N poly gate doping level and p substrate doping level 2 5 Material Parameters 2 5 1 band gap Narrowing BGN 2 5 2 Effective band gap band gap in the gate oxide is much larger than in Si 2 5 3 Electron affinity The amount of energy it takes to free an electron at the bottom of the conduction band i e the Ec level is called electron affinity You can also consider this to be the difference between the so called vacuum energy level and Ec Electron affinity can be used to determine the Ec alignment or offset between two different material regions e g between the gate oxide and N polysilicon gate between the gate oxide and the silicon substrate 4 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation Release 1 0 2 X Slice 1 BanNar 1 Multi Multi X Q Figure 2 2 BGN is observed in N polysilicon gate because of heavy doping 2 5 Material Parameters 5 devices Documentation Release 1 0 2 X Slice 1 EffBanGap t Multi Multi X Q Figure 2 3 Effective band gap is smaller in N polysilicon gate because of heavy doping induced band gap Narrowing BGN 6 Chapter 2 Semiconductor Fundamentals Illustration with TCAD devices Documentation

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