User Manual for C²I² Systems 2-Channel Serial I/O PMC Adapter
Contents
1. note that P14 is only for the rear panel configuration Pin INTB INTC E 16 BUSMODE1 1 8 DEVSEL LOCK SDONE aon PAR 44 LAD O2 AD Ot 60 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 6 of 33 Signal Name in 2 Ground 6 j 10 12 14 16 AD 26 22 24 26 28 38 46 AD 10 PMC RSVD PMC RSVD 60 62 TX A TX DGPS A 2 5 input RX A RX DGPS DSRA inut 6 7 Input CTSA RIA Jint 8 Output s 10 12 15 lnpt CISB RIB Input 16 17 Output GPS Pulse Per GPS Battery Input 18 Second Backup NOT USED Dmm ES Ground Ground p Note P14 Signals are all RS 232 level compliant signals Furthermore the signals are configured such that the Adapters are DTE s This implies that TX lines are outputs and RX lines are inputs with respect to the PMC Adapters CCII LCP 6 MAN 001 2003 09 11 W LCP TECH MAN CLCMAN0O1 WPD 5 Serial Interface 5 1 Overview The PMC Adapters have either one GPS PMC Adapter or two 2 Channel Serial PMC Adapter asynchronous RS 232 serial ports Programming registers for these ports are compatible with the 16C550 UART The ports are configured as below PMC Bus Configuration EEPROM Port B RS232 Serial en Level a Converte2. CT Systems CCII Systems Pty Ltd Registration No 1990 005058 07 Communications Computer Intelligence Integration g User Manual for C212 Systems 2 Channel Serial I O PMC Adapter and GPS PMC Adapter 212 Document No CCII LCP 6 MAN 001 Document Issue Issue Date 2003 09 11 Print Date 2003 09 11 File Name W LCP TECH MAN CLCMANO1 WPD Distribution List No 2 2 Systems The copyright of this document is the property of C I Systems The document is issued for the sole purpose for which it is supplied on the express terms that it may not be copied in whole or part used by or disclosed to others except as authorised in writing by C2I Systems Completed by Accepted by L5 0 cwn Accepted by X Keu CCII LCP 6 MAN 001 W LCP TECH MAN CLCMANO1 WPD Signature Sheet Project Engineer LCP C I Systems Pty Ltd Project Manager LCP C Systems Pty Ltd a ASkurance R amp presentative 9 Systems Pty Ltd 2003 09 11 Issue 1 1 Page ii of vi Amendment History Issue Description Date ECP No Revised according to review 2002 07 17 a Updated to reflect schematic changes for EXAR IC 2002 09 18 CCII LCP 6 ECP 001 Added NMEA sentences and updated as per WRM review 2002 12 02 Reviewed NMEA sentences 2002 12 18 Updated to include conduction cooled board 2003 09 11 CCII LCP 6 ECP 007 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W
3. Draft 2 0 1995 04 04 2 1 2 NMEA 0183 Standard for Interfacing Marine Electronic Equipment Version 3 01 2002 01 01 2 1 3 NMEA 0183 HS High Speed Addendum to NMEA 0183 Interface Standard Version 3 01 2002 01 01 2 1 4 PCI Local Bus Specification Revision 2 1 1995 06 01 5 PMC P1386 1 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards Revision 2 0 1995 04 04 2 1 6 RTCM Special Committee No 104 RTCM Recommended Standards for Differential NAVSTAR GPS Service Version 2 1 1994 01 01 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 2 of 33 3 System Overview The block diagrams of the PMC Adapters are shown below PMC Bus Configuration EEPROM RS232 Serial J Level b Converter Dual UART with PCI Interface RS232 Serial I O A Level d Converter Bus Mode PAL Figure 1 2 Channel Serial I O PMC Adapter PMC Bus Configuration EEPROM Port B Rs232 gSeri ll O 4 Level Ap Converter Dual UART Port A DGPS Input PCI Interface o npu GPS di RS232 du Level Backup Battery PPS Receiver PPS Converter lt Bu Mode GPS Antenna PAL Figure 2 GPS PMC Adapter The two systems are essentially the same However when the GPS receiver is installed as on the GPS PMC Adapter the second R
4. LCP TECH MAN CLCMANO1 WPD Page iii of vi Contents 1 SCOPE E 1 1 1 BtrOdUCctlon ecu e ete prebere aee PE oet sien e e Cep md 1 2 Referenc s EE 2 2 1 ferreo We REEL 2 3 System Overview ccc hn opu bie Eo ete heehee DEG DA Roe LX FS D etu dup Poet 3 4 PMC PCI Interface 4 4 1 OV CIVIOW i 4 4 2 Configuration Space 0 tenet eee 4 4 3 eic ma d n e aa ida ea 5 4 4 PMG GODnHSctors eco adress aaa a doe Guidi 5 4 5 PMC Pin Assignments moie sanasa eiia i area i tne tenes 6 5 Serial Interface NE 8 5 1 OVENISW I HE A AN TE 8 5 2 Memo Map 3 akaa a AN a a S E E cies it D EE Qe dy 10 5 3 UART Register Descriptions 0 0 cee tees 11 5 3 4 Transmitter Holding Register THR 11 5 3 2 Receive Holding Register 11 5 3 3 Interrupt Enable Register 11 5 3 4 Interrupt Identification Register IIR 12 5 3 5 FIFO Control Register FCR 00 0 cece hne 14 5 8 6 Line Control Register LCR lslisslsessessesel nn 15 5 3 7 Modem Control Register MCR 17 5 3 8 Line Status Register LSR 0 00 c
5. Parity Even Parity 1 0 1 Forced Parity 1 LCR Bit 6 0 Normal operation Break condition is disabled and has no effect on the transmitter logic Force a break condition A condition where TX is forced to the space low state LCR Bit 7 0 Normal operation 1 Divisor latch enable Must be set to 1 to access the divisor latches of the baud generator during a read or write Bit 7 must be reset to 0 during a read or write to the receiver holding the transmitter holding register or the interrupt enable register CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 16 of 33 5 3 7 Modem Control Register MCHR The modem control register is an 8 bit register that controls an interface with a modem data set or peripheral device that is emulating a modem MCR Bit 0 0 Sets the DTR output pin to the mark high state 1 Sets the DTR output pin to the space low state MCR Bit 1 0 Sets the RTS output pin to the mark high state 1 Sets the RTS output pin to the space low state MCR Bit 2 0 Sets the OP1 to the mark high state during loop back mode 1 Sets the OP1 to the space low state during loop back mode MCR Bit 3 0 Disables UART interrupt Sets the OP2 to mark high during loop back mode 1 Enables UART interrupt This bit is gated with IER Bits 0 3 Sets the OP2 to the space low state during loop back mode MCR Bit 4 0 Normal
6. cette eee 19 5 3 9 Modem Status Register 5 21 5 3 10 Scratch Pad Register SPR 0 00 cect ttt tees 22 5 3 11 Programmable Buad Rate Generator 23 5 3 12 FIFO Interrupt Mode Operation 24 5 3 13 Register Reset lt 25 6 GPSIhIerfaeB ooo etes Volt be ere eee Dados det os Olona 26 6 1 Overview of GPS 26 6 2 GPS Receiver Specifications 0 0 ccc hern 26 6 3 Architecture of GPS Receiver Module 27 6 4 Default Configuration lisse rre 28 6 5 Configuration 2 3 Hie hay ES needs kate eed de ee ee Reed es au 28 6 6 External Backup Battery 0 0 0 28 6 7 Pulse Per Second Signal 00 0 28 6 8 Suported NMEA Sentences dessei ect tenet ete 28 6 8 1 GGA Global Positioning System Fix 29 6 8 1 1 Description es ew eden ege sagen ree pee obe de seamed 29 6 8 1 2 Sentence Structure ria meaa a e pa aaa len 29 0 9 1 3 Data Fields zaour etel ted A aiid Baa bee ade a e S 29 6 8 2 GLL Geographic Position Latitude Longitude 30 06 8 2
7. into the design is the u blox TIMA B001 The table below summarises the specifications of the GPS receiver module CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 26 of 33 GPS Receiver Module Specifications Receiver Type L1 frequency C A Code 12 Channel GPS Data Format NMEA DGPS Correction Data RTCM Format Accuracy Position 4mCEP SA off Accuracy Position 2m CEP DGPS Accuracy off Acquisition Cold Start 45 s typical Typical Receive Transmit Baud 4800 9600 19200 38400 Rates Dynamics Operating Limits Altitude 18000 m Velocity 515 m s Either limit may be exceeded but not both COCOM restrictions Backup Battery 1 85 V to 3 6 V with a typical current consumption of 4 5 pA NMEA allows using baud rates down to 4800 depending on the messages used 6 3 Architecture of GPS Receiver Module The diagram below shows the block diagram of the GPS receiver module incorporated in the system 1PPS Serial Ports and B CCII LCP 6 MAN 001 2003 09 11 W LCP TECH MAN CLCMANO1 WPD 6 4 6 5 6 6 6 7 6 8 Default Configuration The GPS receiver module has the following default configuration Data read is in the NMEA format The following sentences are generated by default GLL GGA RMC VTG GSV GSA Position fixes are generated at the maximum update rate Differential Configuration Data received from the DGPS port i
8. 1 Descriptions he E eh Oe A a NEL a ie 30 6 8 2 2 Sentence 30 6 8 2 3 Data Fields unn o moet onus AEAEE mdi dog 30 6 83 GSV GNSS Satellites in View liliis 31 CCII LCP 6 MAN 001 2003 09 11 W LCP TECH MAN CLCMAN0O1 WPD 6 8 4 6 8 5 CCII LCP 6 MAN 001 RMC Recommended Minimum Specific GNSS Data 32 6 9 4 1 Descriptioriz sibi up E oie der da bU ERIT ER REI HR IANUE 32 6 8 4 2 Sentence Structure 32 6 84 33 Data Fields Nu ocn IRE tage OA eee tecti a RS IM irem d 32 VTG Course Over Ground and Ground Speed 33 6 9 5 1 IDesctiptiorrz seek se ete ay vd NL SES exe ve ee od d usted ed ce DS Gy 33 6 8 5 2 Sentence Structure 1 0 ee eee eee 33 6 8 5 3 Data Fields se oo al ee ese ye eden aa Be eae tis a oe td 33 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page v of vi ASCII dB BIST CCII CD CS CTS DTE DGPS DSR DTR FIFO GPS Hz IRQ LSB MSB NMEA PCI PMC RI RTCM RTS RX SNR SV TX UART UTC Abbreviations and Acronyms American Standard Code for Information Interchange deciBel Built In Self Test Register CCII Systems Pty LTD Carrier Detect Chip Select Clear to Send Data Terminal Equipment Differential GPS Data Set Ready Data Termina
9. 2 signal on the rear panel connector P14 and the front panel connector JP2 This signal has a pulse width of no more than 100 ms Furthermore the PCI based dual channel UART bridge used to implement the PCI interface can be programmed to generate an interrupt on reception of the Pulse Per Second Signal Suported NMEA Sentences The GPS receiver module supports the following NMEA sentences GLL GGA RMC VTG GSV GSA ZDA A brief overview of these sentences fol lows consultthe NMEA 0183 Interface Standard for further information on these sentences CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 28 of 33 6 8 1 GGA Global Positioning System Fix Data 6 8 1 1 Description Time position and fix related data for a GPS receiver 6 8 1 2 Sentence Structure GPGGA hhmmss ss IlIl Il a yyyyy yy a X o6 Xxx X Mjx x Mx xxoxx hh 6 8 1 3 Data Fields hhmmss ss UTC latitude of position a NorS yyyyy yy longitude of position a EorW x GPS quality indicator O no fix 1 GPS fix 2 Dif GPS fix xx number of satellites in use 0 12 horizontal dilution of precision antenna altitude above mean sea level metres M units of antenna altitude metres x x geoidal separation metres M units of geoidal separation metres x x age of Differential GPS data seconds XXXX differential reference station ID 0000 1023 hh checksum The absolute value c
10. ALCP TECH MAN CLCMANO1 WPD Page 11 of 33 5 3 4 IER Bit 5 0 Standard 16C450 550 mode Power down mode is disabled 1 Enables the power down mode Power down mode functions similar to Sleep mode except oscillator section IER Bits 6 7 These bits are not used always set to 0 Interrupt Identification Register IIR The UART has an on chip interrupt generation and prioritization capability IIR Bit O 0 An interrupt is pending Used either in a hardware prioritized or polled interrupt system 1 No interrupt is pending IIR Bits 1 2 The UART provides four prioritized levels of interrupts Priority 1 Receiver line status highest priority Priority 2 Receiver data ready Priority 2 Receiver character time out Priority Transmitter holding register empty Priority 4 Modem status lowest priority When an interrupt is generated the interrupt identification register indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits bits 0 1 and 2 Interrupt Priority decode Interrupt source Receive Data Error Receive Data Ready Receive Time Out Transmit Holding Empty Modem Status Change These bits are used to identify the highest priority interrupt pending IIR Bit 0 will clear to 1 when no interrupt is pending To clear the interrupts it is necessary to perform reads from the following registers as required Receive Data Err
11. S 232 port is dedicated to GPS functionality CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 3 of 33 4 1 4 2 PMC PCI Interface Overview Both the 2 Channel Serial PMC Adapter and the GPS PMC Adapter conform to the PMC interface specification which is based on the PCI bus interface standard The PMC interface standard defines the physical and environmental aspects of the PCI mezzanine card interface The PMC Adapters implement a single width module that can provide I O through either a DB25 front panel connector or through the back plane connector The PCI interface standard defines the electrical aspects of the interface The PMC Adapters provide a PCI compliant slave interface allowing the host board to transfer data to and from the serial interface controller The PCI interface is implemented using a PCI based dual channel UART bridge Configuration Space The PCI interface defines a standard programming model for the configuration of PCI devices This interface is defined as the Configuration Space The table below shows the Configuration Space as defined by the PCI bus specification Device ID 0x0152 Vendor ID 0x13A8 0x00 Class Code 0x070002 Revision ID 0x01 BIST Header Type Latency Timer Cache Size 08 Memory Base Address Register BAR Unimplemented Base Address Register Unimplemented Base Address Register Unimplemented Base Address Register Unimplemented Base Address Reg
12. XX XX XXX XX 4th SV hh checksum refer to 6 6 1 CCII LCP 6 MAN 001 2003 09 11 W LCP TECH MAN CLCMANO1 WPD Issue 1 1 Page 31 of 33 6 8 4 RMC Recommended Minimum Specific GNSS Data 6 8 4 1 Description Time date position course and speed data provided by a GNSS navigator receiver 6 8 4 2 Sentence Structure GPRMC hhmmss ss A lIII Il a yyyyy yy a x xX x x ddmmyy x x a hh 6 8 4 3 Data Fields hhmmss ss UTC of position A status A valid V invalid latitude of position a NorS yyyyy yy longitude of position a EorW X X Speed over ground knots X X course over ground degrees True ddmmyy date x x magnetic variation a EorW hh checksum refer to 6 6 1 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 32 of 33 6 8 5 VTG Course Over Ground and Ground Speed 6 8 5 1 Description The actual course and speed relative to the ground 6 8 5 2 Sentence Structure GPVTG x x T X x Mx x N x x K hh 6 8 5 3 Data Fields X X course over ground degrees True X X course over ground degrees Magnetic X X Speed over ground knots X X Speed over ground km hr hh checksum refer to 6 6 1 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 33 of 33
13. a character is placed in the receiver holding register and the received data available interrupt is enabled IER 021 an interrupt is generated This interrupt is cleared when the data is read out of the receiver holding register In the FIFO mode the interrupts are generated based on the control setup in the FIFO control register Interrupt Enable Register IER The interrupt enables register enables each of the five types of interrupts and INT pin response to an interrupt generation The interrupt enable register can also be used to disable the interrupt system by setting bits 0 3 to logic 0 The contents of this register are described below IER Bit O 0 Disable the received data available interrupt 1 Enables the received data available interrupt IER Bit 1 0 Disable the transmitter holding register empty interrupt 1 Enable the transmitter holding register empty interrupt IER Bit 2 0 Disables the receiver line status interrupt 1 Enables the receiver line status interrupt IER Bit 3 0 Disables the modem status interrupt 1 Enables the modem status interrupt IER Bit 4 0 Standard 16C450 550 mode Sleep mode is disabled 1 Enables Sleep mode The UART is always awake when there is a byte in the transmitter activity on the RX or either Delta CTS Delta DSR Delta CD Delta RI is are set to logic 1 or when the device is in the loopback mode CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W
14. alculated by exlusive OR ing the 8 data bits no start or stop bits of each character in the NMEA sentence between but excluding and The hexadecimal value of the most significant and least significant 4 bits of the result are converted to two ASCII characters 0 9 A F upper case for transmission The most significant character is transmitted first CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 29 of 33 6 8 2 GLL Geographic Position Latitude Longitude 6 8 2 1 Description Latitude and longitude time of position fix and status 6 8 2 2 Sentence Structure GPGLL IIII II a yyyyy yy a hhmmss ss A hh 6 8 2 3 Data Fields latitude of position a NorS yyyyy yy longitude of position a EorW hhmmss ss UTC A status A valid V invalid hh checksum refer to 6 6 1 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 30 of 33 6 8 3 6 8 3 1 6 8 3 2 6 8 3 3 GSV GNSS Satellites in View Description Number of satellites in view satellite ID numbers elevation azimuth and SNR value Sentence Structure 5 QXXX XXx xx hh Data Fields X total number of messages 1 9 x message number 1 9 xx total number of Satellites in View SV Xx Satellite ID number xx elevation degrees azimuth degrees True 000 359 xx SNR C No 00 99dB Hz 2nd 3rd SV
15. ble 0x300 UART B Read FIFO Read Only 64 bytes of RX FIFO 0x300 UART B Write FIFO 64 bytes of TX FIFO CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 10 of 33 5 3 5 3 1 5 3 2 5 3 3 UART Register Descriptions Transmitter Holding Register THR The transmitter section consists of a transmitter holding register THR and a transmitter shift register TSR The THR is actually a 16 byte FIFO Transmitter section control is a function of the UART line control register The UART THR receives data off the internal data bus and when the shift register is idle moves it into the TSR The TSR serializes the data and outputs it at TX In the 16450 mode if the THR is empty and the transmitter holding register empty THRE interrupt is enabled IER 1 1 an interrupt is generated This interrupt is cleared when a character is loaded into the register In the FIFO mode the interrupts are generated based on the control setup in the FIFO control register Receive Holding Register RHR The receiver section of the UART consists of a receiver shift register RSR and a receiver Holding register RHR The RHR is actually a 16 byte FIFO Timing to receive holding register is supplied by the 16xreceiver clock Receiver section control is a function of the UART line control register The UART RHR receives serial data from RX The RSR then concatenates the data and moves it into the RHR FIFO In the 16C450 mode when
16. ed MSR Bit 4 Complement of the clear to send CTS input When the UART is in the diagnostic test mode this bit is equal to RTS MSR Bit 5 Complement of the data set ready DSR input When the UART is in the diagnostic test mode this bit is equal to DTR MSR Bit 6 Complement of the ring indicator RI input When the UART is in the diagnostic test mode this bit is equal to OP1 MSR Bit 7 Complement of the data carrier detects CD input When the UART is in the diagnostic test mode this bit is equal to OP2 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 21 of 33 5 3 10 Scratch Pad Register SPR The scratch pad register is an 8 bit register that is intended for programmer use as a scratch pad in the sense that it temporarily holds the programmer data without affecting any other UART operation CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 22 of 33 5 3 11 Programmable Buad Rate Generator Each UART has its own Baud Rate Generator BRG with a prescaler for the transmitter and receiver The prescalar is controlled by a software bit in the MCR register The MCR register bit 7 sets the prescalar to divide the on board clock 14 7456 MHz by 1 or 4 The output of the prescalar clocks the BRG The BRG further divides the clock to a programmable divisor between 1 and 2 1 to obtain a 16X or 8X sampling clock of the serial data rate The sampling cloc
17. ion 1 It indicates that the received data input was held in the logic space low state for longer than a full word transmission time A full word transmission time is defined as the total time to transmit the start data parity and stop bits Bl is reset every time the Host reads the contents of the line status register In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the Host when its associated character is at the top of the FIFO When a break occurs only one 0 character is loaded into the FIFO LSR Bit 5 0 At least one byte is written to the transmit FIFO or transmit holding register CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 19 of 33 1 Transmitter holding register is empty indicating that the UART is ready to accept a new character If the THRE interrupt is enabled when THRE is set to 1 an interrupt is generated THRE is set to 1 when the contents of the transmitter holding register are transferred to the transmitter shift register LSR Bit 6 0 When either the transmitter holding register or the transmitter shift register contains a data character 1 Transmitter holding register and the transmitter shift register are both empty LSR Bit 7 0 In the 16C450 this bit is always reset to 0 1 In the FIFO mode at least one parity framing or break error in the FIFO It is cleared when the micr
18. ister Unimplemented Base Address Register Reserved Subsystem Vendor ID Reserved Reserved Reserved Max Latency 0x00 Min Grant 0x00 Interrupt Pin 0x01 Interrupt Line The location of the configuration registers is defined by the host board The host board assigns a specific address line to the module interface by connecting it to the IDSEL pin on the PMC interface To determine the configuration registers locations refer to the manual of the host board 2008 00 11 W LCP TECH MAN CLCMANO1 WPD Page 4 of 33 4 3 PCI Interrupts The PMC Adapters supports interrupts on the INTA pin only This is reflected in the nterrupt Pin Register of the Configuration Space as defined in section 4 2 4 4 PMC Connectors The PMC Adapters are fitted with two connectors P11 and P12 to implement the 32 bit PMC interface The board may be fitted with a either connector P14 required for back plane connection to the interface signals or the front panel connector JP2 J1 is the connector for the GPS antenna on the GPS PMC Adapter The front and rear panel configurations are shown below GSM Module Optional Figure Front Panel I O Configuration GSM Module Optional Figure 4 Rear Panel I O Configuration CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 5 of 33 4 5 PMC Pin Assignments The PMC Adapters have the following PMC connections
19. it 1 0 Normal operation 1 Clears all bytes in the receiver FIFO and resets its counter logic to 0 The shift register is not cleared The one that is written to this bit position is self clearing FCR Bit 2 0 Normal operation 1 Clears all bytes in the transmit FIFO and resets its counter logic to 0 The shift register is not cleared The one that is written to this bit position is self clearing FCR Bit 3 0 Mode 0 Supports single transfer DMA 16C450 mode in which a transfer is made between Host bus cycle 1 Mode 1 Supports multi transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied FCR Bit 5 4 These bits are not used FCR Bits 6 7 These bits are used to set the trigger level for receive FIFO interrupt Receive Trigger Levels Bytes Bit RX FIFO Trigger Level ENESE ENS ESENE CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 WALCP TECH MAN CLCMAN01 WPD Page 14 of 33 5 9 6 Line Control Register LCR The system programmer controls the format of the asynchronous data communication exchange through the line control register In addition the programmer is able to retrieve inspect and modify the contents of the line control register this eliminates the need for separate storage of the line characteristics in system memory LCR Bits 0 1 These two bits specify the number of bits in each transmitted or received serial characte
20. k is used by the transmitter for data bit shifting and receiver for data sampling The BRG divisor DLL and DLM registers defaults to a random value upon power up Therefore the BRG must be programmed during initialization to the operating data rate Baud Rate Generator Programming 152k 460 8 002 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 23 of 33 5 3 12 FIFO Interrupt Mode Operation When the receiver FIFO and receiver interrupts are enabled FCR 0 1 IER 0 1 IER 2 1 a receiver interrupt occurs as follows The received data available interrupt issued to the microprocessor when the FIFO has reached its programmed trigger level It is cleared when the FIFO drops below its programmed trigger level The IIR receive data available indication also occurs when the FIFO trigger level is reached and like the interrupt it is cleared when the FIFO drops below the trigger level The receiver line status interrupt has higher priority than the received data available interrupt The data ready bit LSR 0 is set when a character is transferred from the shift register to the receiver FIFO It is reset when the FIFO is empty When the receiver FIFO and receiver interrupts are enabled FIFO time out interrupt occurs when the following conditions exist Atleast one character is in the FIFO The most recent serial character was received more than four continuous character times ag
21. l Ready East First In First Out memory structure Global Positioning System Hertz Input Output Interrupt Interrupt Request Least Significant Bit Most Significant Bit North National Marine Electronics Association Peripheral Component Interconnect PCI Mezzanine Card Ring Indicator Radio Technical Commission for Maritime Services Request To Send Receive South Signal to Noise Ratio Satellites in View Transmit Universal Asynchronous Receiver Transmitter Coordinated Universal Time West CCII LCP 6 MAN 001 2003 09 11 W LCP TECH MAN CLCMANO1 WPD Issue 1 1 Page vi of vi 1 Scope This document serves as a user manual for the 212 Systems 2 Channel Serial PMC Adapter and GPS PMC Adapter 1 1 Introduction The 2 Channel Serial I O PMC Adapter provides two full duplex asynchronous serial ports Both ports are capable of transmitting and receiving data using RS 232 standards Only one of the serial ports is available on the GPS PMC Adapter The other serial port is used to interface to another GPS module for the purposes of implementing Differential GPS DGPS These PMC Adapters adhere to the electrical requirements of the PCI interface specification and to the mechanical requirements of the PMC interface standard CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 1 of 33 2 References 2 1 Specifications 1 CMC P1386 Draft Standard for a Common Mezzanine Card Family
22. l reaches a trigger level of 1 4 8 and 14 RTS is de asserted mark state RTS is automatically reasserted once the receiver FIFO is empty by reading receive holding register The transmitter circuitry checks CTS before sending the next data byte When CTS is active space state the transmitter sends the next byte To stop the transmitter from sending the next byte CTS must be released before the middle of the last stop bit that is currently being sent MCR bits 6 7 These bits are not used CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 18 of 33 5 3 8 Line Status Register LSR The line status register provides information to the Host concerning the status of data transfers The line status register is intended for read operations only writing to this register is not recommended Bits 1 4 are the error conditions that produce a receiver line status interrupt LSR Bit 0 0 No data in receive holding or FIFO 1 Data ready indicator for the receiver This bitis setto 1 whenever a complete incoming character has been received and transferred into the receiver holding register or the FIFO It is reset to 0 by reading all of the data in the receiver holding register or the FIFO LSR Bit 1 0 Normal operation No overrun error 1 It indicates that before the character in the receiver holding register was read it was over written by the next character transferred into the register OE is re
23. o if two stop bits are programmed the second one is included in this time delay The most recent microprocessor read of the FIFO occurred more than five continuous character times ago When a time out interrupt has occurred it is cleared and the timer is reset when the microprocessor reads one character from the receiver FIFO When a time out interrupt has not occurred the timeout timer is reset after a new character is received or after the microprocessor reads the receiver FIFO When the transmitter FIFO and THRE interrupt are enabled FCR 0 1 IER 1 1 transmit interrupts occur as follows The occurrence oftransmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time the transmitter FIFO was empty It is cleared as soon as the transmitter holding register is written to 1 to 64 characters may be written to transmit FIFO while servicing this interrupt or the IIR is read The first transmitter interrupt after changing FCR is immediate if it is enabled The transmitter empty indicator is delayed one character time when there has not been at least two bytes in the transmitter FIFO at the same time since the last time that TEMT 1 TEMT is set after the stop bit has been completely shifted out The transmitter FIFO empty indicator works the normal way in this mode and is not delayed Character timeout and
24. operation 1 Internal loop back mode Provides a local loop back feature for diagnostic testing of the UART When LOOP is set to 1 the following occurs The transmitter TX pin is set to the mark high state The receiver RX pin is disconnected The output of the transmitter shift register is looped back into the receiver shift register input The four modem inputs CTS DSR CD and RI pins are disconnected The four modem outputs DTR RTS OP1 OP2 pins are internally connected to the four modem inputs The four modem outputs are forced to the mark high state In the diagnostic mode data that is transmitted is immediately received This allows the processor to verify transmit and receive data paths to the UART The receiver and transmitter interrupts are fully operational The modem control interrupts are also operational but the modem control interrupt sources are now the lower four bits of the modem control register instead of the four modem control inputs All interrupts are still controlled by the interrupt enable register CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 17 of 33 MCR Bit 5 0 16C450 550 mode Hardware flow control is disabled 1 Enable hardware flow control RTS CTS Flow Control Bii Flow Control Auto RTSICTS TE Auto CTS only Disabled RTS becomes active space state when the receiver is empty or the threshold has not been reached When receiver FIFO leve
25. oprocessor reads the LSR and there are no subsequent errors in the FIFO CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 20 of 33 5 3 9 Modem Status Register MSR The modem status register is an 8 bit register that provides information about the current state of the control lines from the modem data set or peripheral device to the Host Additionally four bits of this register provide change information when input from the modem Changes State the appropriate bit is set to 1 All four bits are reset to 0 when the Host reads the modem status register MSR Bit 0 0 Nochange to CTS input 1 Indicates that the CTS input has changed state since the last time it was read by the Host When interrupt is enabled a modem status interrupt is generated MSR Bit 1 0 Nochange to DSR input 1 Indicates that the DSR input has changed state since the last time it was read by the Host When interrupt is enabled a modem status interrupt is generated MSR Bit 2 0 No change to RI input 1 Indicates that the RI input has changed from the space low state to the mark high state When RI is set to the mark high state and the modem status interrupt is enabled a modem status interrupt is generated MSR Bit 3 0 No change to CD input 1 Indicates that the CD input has changed state since the last time it was read by the Host When interrupt is enabled a modem status interrupt is generat
26. or Reading LSR register will clear this interrupt User should save LSR value after reading the register to maintain the error condition e Receive Data Ready Reading RHR register till FIFO becomes empty Receive Timeout Reading entire characters from RHR Transmit Holding Empty Writing a character into THR register or reading IIR register if source of interrupt Modem Status Change Reading MSR register will clear this interrupt CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 12 of 33 IIR Bit 3 0 In the 16C450 mode In FIFO mode this bit is set along with bit 2 to indicate that a time out interrupt is pending IIR Bit 4 This bit is not used always reset at 0 IIR Bit 5 0 16C450 550 mode 16 byte FIFO mode 1 Enhance FIFO mode 64 byte FIFO mode enabled IIR Bits 6 7 0 In the 16C450 mode 1 When FCR 0 is equal to 1 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 13 of 33 5 3 5 FIFO Control Register FCR The FIFO control register FCR is a write only register The FCR enables and clears the FIFO sets receive FIFO trigger level and selects the type of DMA signaling FCR Bit 0 0 16C450 mode disables the transmitter and receiver FIFO 1 Enables the transmitter and receiver FIFO This bit must be set to 1 when other FCR bits are written to or they are not programmed Changing this bit clears the FIFO FCR B
27. r Word Length Bii Bit 0 Word Length olof sum __ Cei 1 CERTE LCR Bit 2 This bit specifies 1 1 1 2 or 2 stop bits in each transmitted character When bit 2 is reset to 0 one stop bit is generated in the data When bit 2 is set to 1 the number of stop bits generated is dependent on the word length selected with bits 0 and 1 The receiver clocks only the first stop bit regardless of the number of stop bits selected The number of stop bits generated in relation to word length and bit 2 Stop Bits Bit 2 Word Length Stop Bit s LCR Bit 3 0 Parity is disabled No parity is generated or checked 1 Parity bit is generated in transmitted data between the last data word bit and the first stop bit In received data parity is checked LCR Bit 4 0 ODD parity select bit When parity is enabled by bit 3 a 1 in bit 4 produces odd parity an odd number of 1 s in the data and parity bits 1 Even parity select bit When parity is enabled by bit 3 a 1 in bit 4 produces even parity an even number of 1 s in the data and parity bits CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 15 of 33 LCR Bit 5 0 Stick parity is disabled 1 Stick parity bit When bits 3 5 are set to 1 the parity bit is transmitted and checked as a 0 When bits 3 and 5 are 1 s and bit 4 is a 0 the parity bit is transmitted and checked as 1 Parity Selection Parity Type No Parity Odd
28. r PCI to Dual UART Bridge Port A RS232 Serial lt Level M Converter Bus Mode PAL Figure 5 Serial Interface One the Rear panel PMC Adapter the signals are available at P14 as detailed in section 4 4 On the front panel PMC Adapters the signals are available at JP2 a DB25 connector as shown in section 4 4 The pinout is as show in the table below CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 8 of 33 Direction Signal Name __ GND 2 Output TRB 3 Oupt TXB 4 input J RXB 5 Input CCB 19 7 GND es GPS Pulse Per Second GPS Battery Backup TX_A RX_DGPS RX_A TX_DGPS RIB CTS B RTS B DSR B O NOTUSED ___ O 1 1 NOTUSED X J Note J2 Signals are all RS 232 level compliant signals Furthermore the signals are configured such that the Adapters are DTE s This implies that TX lines are outputs and RX lines are inputs with respect to the PMC Adapters CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 9 of 33 5 2 Memory Map The memory map for the UART registers are given in the table below 0x000 0x00F UART channel A registers 16C550 compatible 0x100 UART A Read FIFO Read Only 64 bytes of RX FIFO 0x100 UART A Write FIFO Write Only 64 bytes of TX FIFO 0x200 0x20F UART channel B registers 166550 compati
29. receiver FIFO trigger level interrupts have the same priority as the current received data available interrupt CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 24 of 33 5 3 13 Register Reset Conditions The value of the registers at reset is given below Reset Conditions RHR X X X X X X X THR X X X X X X X IER 0 0 0 0 0 0 0 EA FCR 0 0 0 0 0 0 0 EA IIR 0 0 0 0 0 0 0 LCR 0 0 0 0 0 0 0 EX MCR 0 0 0 0 0 0 0 kA LSR 1 1 0 0 0 0 0 ES MSR X X X X 0 0 0 ES SPR 1 1 1 1 1 1 1 CCII LCP 6 MAN 001 2003 09 11 Issue 1 1 W LCP TECH MAN CLCMANO1 WPD Page 25 of 33 6 GPS Interface 6 1 Overview of GPS Interface On the GPS PMC Adapter Port A is dedicated to GPS functionality Hence Port A is no longer available for user communication purposes The ports are configured as below PMC Bus Configuration EEPROM Serial Port B RS232 g lt Level mt Converter Dual UART with PCI Interface POA DGPS Input lt gt RS232 cre Level Backup Battery DURUM Ries Converter Bus Mode GPS Antenna PAL Figure 6 GPS PMC Adapter DGPS I O signals can be found on connector JP2 a DB25 connector as shown in section 4 4 The pinout is as shown in section 5 1 The GPS antenna is connected to connector J1 as shown in section 4 4 6 2 GPS Receiver Specifications The GPS receiver module incorporated
30. s according to the RTCM SC 104 standard Transfer protocol is 9600 baud 8 data bits no parity 1 stop bit Configuration The GPS receiver module is connected to Port A Hence Port A should be configured with the same parameters ie baud rate number of stop bits parity etc as the GPS receiver module The GPS receiver module communicates using the NMEA protocol consult the NMEA 0183 Interface Standard DGPS Correction Data is received using the RTCM protocol consult the RTCM SC 104 Standard External Backup Battery Use of an external backup battery is recommended to reduce the acquisition time of the GPS module If an external backup battery is connected the module keeps the internal Real Time Clock running and holds the SRAM data ephemeris and almanac during power supply interruption This enables warm and hot start However under good visibility conditions cold and warm start times do not differ significantly Connection of an external backup battery is made via the rear panel connector P14 pin 18 or the front panel connector JP2 pin 8 The external backup battery must be capable of delivering 1 85 V to 3 6 V with a typical current consumption of 4 5 pA Should an external backup battery not be connected the user must ensure that this signal is grounded either on P14 or JP2 Pulse Per Second Signal The GPS module outputs the Pulse Per Second signal at a precise time interval of one second It is available as an RS 23
31. set every time the Host reads the contents of the line status register If the FIFO mode data continues to fill the FIFO beyond the trigger level an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register An overrun error is indicated to the Host as soon as it happens The character in the shift register is overwritten but it is not transferred to the FIFO LSR Bit 2 0 Normal operation No parity error 1 It indicates that the parity of the received data character does not match the parity selected in the line control register PE is reset every time the Host reads the contents of the line status register In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the Host when its associated character is at the top of the FIFO LSR Bit 3 0 Normal operation No framing error 1 Itindicates that the received character did not have a valid stop bit FE is reset every time the Host reads the contents of the line status register In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the Host when its associated character is at the top of the FIFO The UART tries to re synchronize after a framing error To accomplish this it is assumed that the framing error is due to the next start bit LSR 4 0 Normal operat
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