RF2TTC manual (V5.0) - TTC Upgrade
Contents
1. Description This register allows setting the period of the internally generated orbit signal in units of 25 ns The default value is OXDEC which corresponds to 3564 bunch clocks between two orbits ORBx INT PERIOD COUNTER Access ORBI INT PERIOD COUNTER Ox7FB50 ORB2 INT PERIOD COUNTER Ox7FB10 ORBmain INT PERIOD COUNTER Ox7FADO Description This register is provided for debugging purposes It holds the value of the BC counter that is used to generate the internal orbit signal This can be reset by the ORB INT RESET register ORBx COUNTER Offset Size Access ORB1_COUNTER Ox7FBAC 32 bits ORB2 COUNTER Ox7FBOC COUNTER Ox7FACC Description This register holds the number of orbit pulses that have been received since the counter was reset enabled At an orbit period of 89 us this counter will overflow after approximately 106 hours and will be reset ORBx PERIOD RD Size ORBI PERIOD Ox7FB48 ORB2_PERIOD_RD 0 7 8 ORBmain PERIOD RD Ox7FAC8 Description This register holds the time in units of 25 ns BC ticks that has elapsed between the last two orbit output pulses The number of steps given is always 1 more than the real number of steps between 2 orbits Page13 ORBx PERIOD FIFO STATUS Offset Size Access ORBI PERIOD FIFO STATUS 0 7 44 PERIOD STATUS 0 7 42. ECL AC coupled signal Should be connected to the BC1 output of the Rx D BC INPUTS BC2 ECL AC coupled signal Should be connected to the BC2 output of the Rx D BC INPUTS BC REF ECL AC coupled signal Should be connected to the BCref output of the Rx D ORB INPUTS ORBI ECL AC coupled signal Should be connected to the ORBI output of the Rx D ORB INPUTS ORB2 ECL AC coupled signal Should be connected to the ORB2 output of the Rx D BC OUTPUTS ECL AC coupled signal NIM copy is also available for oscilloscope monitoring for example BC OUTPUTS BC2 ECL AC coupled signal a NIM copy is also available BC OUTPUTS BC REF ECL AC coupled signal a NIM copy is also available BC OUTPUTS BCmain ECL AC coupled signal a NIM copy is also available ORB OUTPUTS ORBI ECL AC coupled signal a NIM copy is also available ORB OUTPUTS ORB2 ECL AC coupled signal a NIM copy is also available ORB OUTPUTS ORBmain ECL AC coupled signal a NIM copy is also available Page28 2 5 OUTPUT SIGNAL AMPLITUDE INFORMATION The typical outputs ECL amplitude that we have after 2m of cables on 50Ohm terminated ends are o 670mV amplitude o POSITIVE ORBIT NEGATIVE ORBIT 570mV These values have been set to fit the various needs of all the users but could need to be adju
3. Phase QPLL MAIN BC COUPLING 800mV swing Adjust d ECL Driver ECL OUT Diff LVPECL E PLL amp LVPECL QUARTZ Ns 1 LVPECLALVUS VCXO ap 80 158MHz INTERNAL 8 E MAIN BC CLOCK Step 500ps range 25ns NIM OUT MAIN BC lock 2 LVDS2ECL CONVERSION Orbit Orbi det MAIN B USING BSR17A detect TRANSISTORS DELAY25 ORBIT1 Stretch 40ns LVPECL Fine i BC1 lock BC2 lock BCref lock MAIN BC lock Sine puls Orb2 dej 1V peak 9 RF2TTC BOARD 5ns width Orbit1 BLOCK DIAGRAM V1 7 Orbit2 Sine2 Stretch 5 20 2009 MAIN BC Square er BC2 Bcref ORBIT2 MAIN ORBIT 1 0 2 FROM RE Br aL Int RECE comparator BCsel 1 0 E Lock TTCready 40 ns LVPECL Machine Mode Run No SS VME access VME Berr z Mc10EP89ECL BST_ready BC1 clock coax cable E 1 dri BC amp ORBIT SOURCES 12C interface BOARD STATUS rivers SELECTION DACs adjustment for Orbit ORBIT1 comparators IND NECLIOUT C1 CLOCK ECL Driver INTERNAL Multiplexer DACs am
4. BC2_NOBEAM_SELECT Ox7FBC4 BCref_NOBEAM_SELECT Ox7FBA4 BCmain MAN SELECT Ox7FB8C BCmain BEAM SELECT 0 7 88 NOBEAM SELECT Ox7FB84 Description These registers select the sources of the BC outputs Only one set of registers is active at a time The BCx MAN SELECT registers are active when the is operating in manual mode defined in WORKING MODE register The BEAM SELECT registers are active when is defined by WORKING MODE register to be automatic and the current LHC beam mode decoded BST is declared by BEAM_NO_BEAM_DFF to be with beam The BCx_NOBEAM_SELECT registers are active when BCx 15 defined by WORKING MODE register to be automatic and the current LHC beam mode decoded in BST is declared by BEAM NO BEAM DEF to be without beam Page8 The MAN SELECT and the SELECT registers are set to INTERNAL 0 by default and BEAM SELECT register to EXTERNAL 1 Bit definition for BC2 and BCref registers Description 0 Output taken from internal 40 078 clock INTERNAL 1 Output follows respective BC input EXTERNAL Bit definition for BCmain registers Description 0 Output taken from internal 40 078MHz clock 1 Output follows BCref input 2 Output follows BC2 input 3 O
5. ORB2 MAN SELECT Ox7FB2C ORBI BEAM SELECT Ox7FB68 ORB2 BEAM SELECT Ox7FB28 NOBEAM SELECT Ox7FB64 ORB2 NOBEAM SELECT 0 7 24 ORBmain MAN SELECT Ox7FAEC ORBmain BEAM SELECT Ox7FAE8 ORBmain_NOBEAM_SELECT Ox7FAE4 Description These registers select the sources of the orbit outputs Only one set of registers is active at any time The ORBx_MAN_SELECT registers are active when the RF2TTC is operating in manual mode If the card is in automatic mode and the beam is on the orbit outputs are controlled by the ORBx_BEAM_SELECT registers The ORBx NOBEAM SELECT registers control the orbit outputs when the RF2TTC is in automatic mode and the beam absent The MAN_SELECT and NO_BEAM registers are set to INTERNAL by default The BEAM register to EXTERNAL Bit definition for ORB1 and ORB2 registers Value Description 0 Output follows the respective orbit input EXTERNAL 1 Output from internal BC synchronized orbit generator Bit definition for ORBmain registers Value Description 0 Output follows the orbit 1 input 1 Output follows the orbit 2 input Output from internal orbit generator synchronized to BCmain 11 ORBx POLARITY Offset POLARITY Ox7FB60 Access ORB2 POLARITY Ox7FB20 ORBmain POLARITY Ox7FAEO Description If set this bit inverts the polarity of the orbit output with respect to t
6. ORBmain PERIOD FIFO STATUS Ox7FACA Description This register holds the status of the FIFO that contains the most recent 256 orbit periods of the respective orbit output channel Bit definitions Value Description 0 Fifo not empty 1 Fifo empty 0 Fifo not full 1 Fifo full Note Bit 14 of the ORBx_PERIOD_FIFO_RD register also gives the empty flag of the fifo ORBx PERIOD FIFO RD ORBI PERIOD FIFO RD 0 7 40 16 bits ORB2 PERIOD FIFO RD 7 ORBmain PERIOD FIFO RD Ox7FACO Description These registers provide access to three 256 word deep FIFOs which contain the most recent 256 orbit periods of the respective orbit output channel in bits 0 13 Reading the last period stored in the FIFO or from an empty FIFO results in reading a 1 in bit 14 FIFO empty For the moment it is not possible to read these FIFOs with a constant address block transfer The first value stored in the Fifo immediately after a reset or an enable is not significant because the counter does not begin with an orbit pulse but with an enable or a reset command If the fifo is read with a period smaller than 89us it is possible to have a continuous monitoring of the orbit period ORBx DAC ORBI DAC Ox7FB3C ORB2 DAC Ox7FAFC Description These registers allow setting the threshold voltage of the orbit input comparator in a range from 1 25 V to
7. The two first ones a and b are mandatory The according to the choice you made for the orbmain bcmain you have to pick up one of the 4 c or d or e or f If you plan to use several configurations you have to calibrate for example c AND d This is not a problem as the working window is very large To be conservative you may do the 6 cycles of calibration 3 per orbit input and you will be sure they will always be safely latched The calibration procedure is similar to the threshold adjustment described above 1 2 Connect your board to the Rx modules outputs Adjust the phase of the clocks BC1 BC2 BCref and BCmain according to your detector requirements use the BCdelay25 registers ORBI out Calibrate case a mandatory a Set your board to have MAN SELECT BCI and MAN SELECT external Set ORBIN DELAY25 ORBI to 0x40 enabled 0 delay Reset the Orb fifo PERIOD COUNTER RESET Read 1000 times PERIOD FIFO RD While ORBIN DELAY25 ORBI 50 lt 0 4 ORBIN DELAY25 1 lt ORBIN_DELAY25_ORB1 1 and go back to c Pay attention to keep the ORBIN DELAY25 1 6 1 chip enabled You should get a window called here Orb1 Wa of about 40 consecutive steps for which the 1000 periods are all 2564 OxDEC Page26 4 2 out Calibrate case b a Set your board to have BC2 MAN SELECT BC2 and ORB2 SELECT external Set ORBIN DELAY25 to 0x40 e
8. 2 3 4 2 1 2 2 Table of Contents Introduction RF2TTC Hardware Standards and power supplies VMEbus interface 2 2 1 Reset registers BSET Board Set Register assignment BCLEAR User defined BCLEAR Register assignment 2 2 2 Board Identification read only registers 2 2 3 Board configuration registers 2 3 BCx MAN SELECT BCx SELECT amp BCx SELECT BCx QPLL MODE BCx QPLL STATUS ORBx SELECT ORBx BEAM SELECT amp ORBx SELECT ORBx POLARITY ORBx COARSE DELAY ORBx LENGTH ORBx INT PERIOD SET ORBx INT PERIOD COUNTER ORBx COUNTER ORBx PERIOD RD ORBx PERIOD FIFO STATUS ORBx PERIOD FIFO RD ORBx DAC TTCrx status BST Beam Mode BEAM NO BEAM DEF WORKING MODE ORB INT ENABLE COUNTER ENABLE PERIOD COUNTER ENABLE COUNTERS RESET registers DELAY25_REG TTCrx_REG BC DELAY25 x ORBIN DELAY25 x ORBOUT DELAY25 x TTCrx REGISTERS Calibration procedures 2 3 1 Threshold adjustment ORBx DAC 2 3 2 Orbit inputs delay adjustment 2 4 2 5 2 6 2 7 2 8 4 1 Fibre cable connections Output signal amplitude information Front panel LEDs Improvements made on the production version V3 2 4 1 Initialisation procedure Registers Summary List of firmware updates RF2TTC common software Introduction 4 1 1 H W Environment 4 1 2 S W Environment 4 2 4 3 Test programs The user library Page2 1 INTRODUCTION T
9. not very practical Page34 19 05 2009 24 06 09 changes the definition of BSET and BCLEAR registers to allow individual reset of QPLL chips bits 5 3 Change on the reset n of the qpll registers previously reset by qpll reset now by the general reset init ctrl new constant begin init delay 1000000 x 25ns 25ms simple I2C sophie2 new version of simple i2c sophie with a corrected scl sca 84 bits instead of 80 for scl and a new alignment of sda to have the edges in the middle of low ctrl update the WRn only when iDTACK is released to avoid a change of WR n in the middle of a transaction especially when the transaction is long as with the Page35 4 RF2TTC COMMON SOFTWARE 4 1 INTRODUCTION Even though the RF2TTC performs the same task in each of the four LHC experiments it will be operated in H W and S W environments that are specific to the respective experiment Therefore the common S W is limited to the lowest level which consists of some diagnostic programs and a user library This S W is implemented in the rf2ttc package and can be found in CERN CVS repository at http isscvs cern ch cgi bin viewcvs all cgi rf2ttc cvsroot rf2ttc For direct access from Unix use e g setenv CVSROOT kserver isscvs cern ch local reps rf2ttc 4 1 1 H W Environment In the ATLAS and ALICE experiments the RF2TTC is controlled by a VMEbus SBC from Concurrent Technologies eit
10. Delay25 chips on 041 and orb2 inputs They are set to 0x40 by default which means that they are enabled bit6 with a delay of 0x00 The delay go from 0 Ons to Ox3F 31 5ns by steps of 0 5ns As you can see on the diagram below the orbit once stretched to 40ns pulse is latched by its corresponding Bunch Clock e fororbl BC2 for orb2 and BCmain for orbmain with BCmain BCI BC2 or BCref We do not consider the case of internal bunch clocks as it wouldn t make much sense latching an external orbit with an internal 1e not synchronous clock MAIN BC lock Orbit Orb1 det detect ORBITI Sine2 TL stretch Lene erect Square er Sine pulse Rm baud Orb2 det 1V peak 0 1V lete 5ns width A RF2TTC BOAF BLOCK DIAGRAN a Stretch Lene tier 5 20 2009 ORBIT2 I FROM RF OPTICAL RECEIVERS conbparatqr BCsel 1 0 f TTCready 96685 Adjust d Coarse Stretch C inte BOARD STATUS Delay DACs SEI ECTION DACE amp Ref anne Voltage MACHINE MODE 1 Coarse r Delay BST SIGNAL OPTICAL TTC FRAMES FINE DELAYS Adjust
11. Dout bus of the TTCrx which contains the broadcast data and hence the Machine Mode Register access protocol The TTCrx chip needs to be ready ie the optical fibre needs to deliver a correct encoded 40MHz clock in order to access the internal registers The way to access the registers is described in the manual p30 2 pointer register and 12 data register The I2C pointer register is five bits wide and contains the address of the internal register as defined in Table 3 page 16 When reading the I2C data register the content of the TTCrx register being addressed by the pointer register is transferred Conversely writing a byte to the 2 data register in fact writes to the TTCrx register addressed by the I2C pointer register Hence each I2C access is performed in two steps 1 Write the register number in the I2C pointer register 2 Read or write the 12 data register According to the I2C bus specification each device on the bus is addressed by a 7 bit wide I2C device address Each TTCrx chip occupies two consecutive positions in the 7 bit I2C address space Hence it is possible to address 64 devices in the system The 7 bit I2C address is derived from the content of the ID I2C 5 0 base address register in the following way I2C access register name Resulting 7 bit I2C address ID 12 lt 5 0 gt 2 12 data ID_I2C lt 5 0 gt 2 1 Table 12 I2C address calculation The registers ac
12. ORBI PERIOD FIFO STATUS 0 7 44 2 R ORB1_PERIOD_FIFO_RD 0x7FB40 16 R ORB1_DAC 0x7FB3C R W ORB2_MAN_SELECT 0x7FB2C R W ORB2_BEAM_SELECT 0x7FB28 R W ORB2_NOBEAM_SELECT 0x7FB24 R W ORB2_POLARITY 0x7FB20 R W ORB2_COARSE_DELAY 0x7FB1C ORB2_LENGTH 0x7FB18 ORB2_INT_PERIOD_SET 0x7FB14 ORB2_INT_PERIOD_COUNTER 0x7FB10 ORB2_COUNTER Ox7FBOC ORB2 PERIOD RD Ox7FBOS ORB2 PERIOD FIFO STATUS 0 7 4 PERIOD FIFO RD 7 DAC Ox7FAFC ORBmain MAN SELECT Ox7FAEC ORBmain BEAM SELECT Ox7FAE8 ORBmain_NOBEAM_SELECT Ox7FAE4 ORBmain_POLARITY Ox7FAEO ORBmain COARSE DELAY Ox7FADC ORBmain LENGTH Ox7FAD8 ORBmain_INT_PERIOD_SET Ox7FAD4 ORBmain_INT_PERIOD_COUNTER Ox7FADO ORBmain COUNTER Ox7FACC ORBmain PERIOD RD Ox7FAC8 ORBmain_PERIOD_FIFO_STATUS Ox7FAC4 ORBmain_PERIOD_FIFO_RD Ox7FACO TTCrx status Ox7FAAO BST_Beam_Mode Ox7FA9C BEAM NO BEAM DEF Ox7FA7C Page32 WORKING MODE Offset Ox7FA78 Size bits 7 Access R W ORB INT ENABLE Ox7FA6C R W ORB COUNTER ENABLE Ox7FA68 R W PERIOD COUNTER ENABLE Ox7FA64 R W ORB INT RESET Ox7FA4C W PERIOD COUNTER RESET Ox7FA48 ORB_COUNT
13. RegOFFSET 0xE000 the Data read has no meaning VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x000XYOURDATA with X 0 if the fIFO is not empty X 1 if you are reading the last word stored in a FIFO Successively read fine delay registers 1 and 2 I2C address and 2 VME WRITE 0 09 RegOFFSET 0xE000 Data 0x1 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x2 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x0000YOURDATA VME READ AM 0x09 RegOFFSET 0xE200 Data should be 0x0001 YOURDATA Page23 2 3 CALIBRATION PROCEDURES For a proper operation of the RF2TTC in its environment a number of registers have to be tuned by the user delays thresholds length The purpose of adjusting the delay of the Bunch Clock outputs is easy to understand as well as delaying the orbit output signals finely with 0 5ns steps or coarsely with 25ns steps However finding the right values for the orbit in delay and threshold registers is not so easy The following calibration procedure may help you to optimize these settings 2 3 1 Threshold adjustment ORBx DAC The orbit is arriving at the board input as a 5ns sinusoidal pulse with 1V amplitude on 50 Ohm termination To be converted to a digital pulse it is first compared to an adjustable threshold set by the ORBx DAC register t
14. Stretch er Coarse Delay N T VME BACKPLANE ERNAL CLOC MAIN BC CLOCH WTERIAI As the phase between the orbit and its relative BC is not known when it enters the latch in the FPGA we may face a problem of metastability if the rising edge of the orbit pulse occurs close to the rising edge of the BC This metastability window is in a range of setup time hold time of internal FPGA flipflops which should be of the order of max 1ns 1ns see graph below Although very unlikely to happen this situation must be avoided and a calibration is recommended Orb in delayed BC Page25 Thereby a b d e f Orb1 must be calibrated to match BC1 Dflipflop 1 on the diagram Orb2 must be calibrated to match BC2 Dflipflop 2 But it is not enough You have also to ensure that your Orbmain is matching BCmain The duo Orbmain BCmain can be made of Orb1 BC1 Dflipflop3 if Orbmain Orb1 and BCmain BC1 or Orb1 BCref Dflipflop3 if Orbmain Orb1 and BCmain BCref or Orb2 BC2 Dflipflop4 if Orbmain Orb2 and BCmain BC2 or Orb2 BCref Dflipflop4 if Orbmain Orb2 and BCmain BCref or Note that if c and e look similar to a and b the flipflop is different and the clock is following another path so the phase between Orb and BC may be different A minimal calibration procedure would include at least 3 of the above points
15. procedures are proposed Page3 CAPACITIVE CREVENIN MC10EP89 ECL TERMINATION FOR QPLL coax cable Diff LVPECL DC LEVEL OF 1 2V ner drivers VJ Sine2 Dif LVPEGL ws PLL amp 5 i Square Sb BC1 ECL OUT Sinusoidal frequencies Diff LVPECL 800mV swing VCXO PECL ECL Driver gt 40 07XX MHz A BCisel LVPECL2LVDS BC1 lock varying V compt ce LVDS2ECL gt 0 6 pk pk 8 Diff LVPECL_ 7 BC NIM OUT or 0 6V pk pk CMS PECL2NIM Sine2 Diff LVPECL 4 1 08 Square i 800mV swing 2 CLOCK PLL amp CEN LVPECL2LVDS 1 4 ECL Driver BC2 ECL OUT V comp2 Es BC2 lock Bis LVPECL A gt LVDS2ECL f N 4 Sine2 Diff LVPECL LVDS BC ref bo X Square AC mM g00mV swine PECL2NIM 2 COUPLING 7 CLOCK P Sinusoidal frequency ECL i LVPECL2LVDS PLL amp BCref 40 07XX MHz comparat P3 BCref sel VCXO FANS PECL ECL ECL OUT fixed AD96685 0 6V 8 BCreflock i x or 0 6V pk pk CMS LVDS2ECL BCref emp NIM OUT DELAY25 j _Diff LVPECL ii 1 4 S
16. 0 1 place Delay25 chips in reset mode Delay25 chips in reset mode 0 no effect Delay25 chips not in reset mode 1 X X X X place BC1 QPLL chip in reset mode QPLL chip in reset mode no effect BCI QPLL chip not in reset mode place BC2 QPLL chip in reset mode BC2 QPLL chip in reset mode no effect BC2 QPLL chip not in reset mode place BCref QPLL chip in reset mode BCref QPLL chip in reset mode no effect BCref QPLL chip not in reset mode place BCmain QPLL chip in reset mode BCmain QPLL chip in reset mode no effect BCmain QPLL chip not in reset mode place TTCrx chips in reset mode TTCrx chips in reset mode no effect TTCrx chips not in reset mode place board in reset mode Board in reset mode no effect Board not in reset mode Note When the QPLL are reset using bits 2 to 5 the BCx QPLL MODE registers are NOT reset So the QPLLs are remaining in the mode to which they were previously configured ie autorestart after reset or relock Page6 BCLEAR User defined BCLEAR Register assignment Description This register is declared in the VME64x as a User defined Bclear register It is used here to remove partial reset functions QPLL only Delay25 chips only TTCrx only The bit definition is as follows Bit Value Write Read 0 1 remove Delay25 chips from reset mode Delay25 c
17. 1 25 V The threshold is linked to the value of the register by the formula Threshold V 1 25 value 2 5 255 The default value of the threshold is OxAA 14 TTCrx status Offset Size Access TTCrx status Ox7FAAO0 1 bit R Description This register reflects the status of the on board TTCrx chip Bit definitions Value Description 0 TTCrx not ready 1 TTCrx ready BST message is correctly decoded at least 40MHz clock is sent over the optical fibre connected to the TTCrx BST Beam Mode Offset Size Access BST_Beam_Mode Ox7FA9C 32 bits R Description This register holds the LHC machine mode as decoded from the BST messages received by the TTCrx Each number corresponds to one machine mode as transmitted by the BST Value Dec Value Hex Description No mode Setup Injection probe beam Injection setup beam Injection physics beam Prepare ramp Ramp Flat top Squeeze Adjust Stable beams Unstable beams Beam dump Ramp down Recovery Inject and dump Circulate and dump Abort Cycling Beam dump Warning No beam j O 0 NID Aa e 5 W P fy 1 lo la lw gt A J nN N oo N 95 m P N UA Page15 BEAM NO BEAM DEF A
18. B1 nu 0 o o o o 0 0 Reset State DELAY25 GCR register The general control register GCR controls the operation of the Delay Locked Loop DLL and allows to reset the DLL or the ASIC via the DC interface The bit allocation for this register is given in Table 4 General Control Register GCR bit allocation with their state after reset B7 6 5 4 B3 B2 B1 BO 0 9 1 LI _ Nor cleared Reset State The ASIC can operate with for different clock frequencies 32 40 64 and 80 MHz For this application the M 0 and M 1 bits must be set to 0 40MHz IDLL bit IDLL is used to force the resynchronization of the DLL without resetting the chip Writing a 1 to this bit forces the resynchronization of the DLL This bit always reads as a 0 At power up an internal routine in the RF2TTC sets lt 1 gt and lt 0 gt to 0 Page20 ORBIN DELAY25 x Offset Size Access ORBIN DELAY25 GCR 0 70034 ORBIN DELAY25 0x7D024 ORBIN_DELAY25_ORB1 0x7D020 Description These registers control the configuration of the Delay25 chips for the orbit input signals Finely adjusting the delay of the orbit inputs with steps of 0 5ns allows moving the rising edge of the orbit pulse away from the rising edge of the corresponding bunch clock to ensure a good synchronisation of the 2 signals basically to avoid the metastability generated if th
19. Class VME Function RF2TTC scc cd Created 11 10 2006 Page Page 1 of 27 PH ESS 24 06 2009 Modified 24 06 2009 Rev No USER MANUAL 4 User Manual V5 0 RF to TTC VMEbus Interface Card and S W Summary This document describes the functionality of the RF2TTC card as well as the generic S W that has been developed for it Document Revision 4 o 12 03 07 the CR CSR space has been transposed to the User Space o 16 05 07 geographical address modified information on orbit period counter results initialisation procedure section 2 7 1 last firmware version output signals amplitude adjustments section 2 6 etc o 24 06 09 Information about DAC registers for clock input has been removed does not exist since V1 of the board BSET and BCLEAR register definition changed to allow individual resetting of QPLLs Last firmware version is 19052009 Default values of QPLL modes Ifan error occurs the QPLL status remains at 1 until having been read o Precisions about orbit delays o Correction on TTCrx read control register example Prepared by Checked by Approved by Markus Joos PH ESS for information Tel you can contact Fax E Mail Sophie Baron 41 22 7677339 41 22 7678925 sophie baron cern ch Markus Joos 41 22 7672364 41 22 7678925 markus joos cern ch Stephane Detraz 41 22 7679702 41 22 7678925 Stephane detraz cern ch Pagel 1
20. ENG Offset Size Access BEAM_NO_BEAM_DEF Ox7FA7C 32 bits R W Description The BST system is sending every orbit an update of the beam mode between 1 and 21 This mode is decoded in previous register BST BEAM MODE For each mode the NO BEAM DEF registers defines if it is considered as a mode with beam 1 or without beam 0 If for example selection is in automatic mode set in WORKING MODE register allthe beam modes with beam will apply the BEAM SELECT settings all the modes without beam will apply the NOBEAM SELECT settings If the is in manual mode this register is ignored and SELECT settings are being applied The NO BEAM is set by default to 0 1 00 Mode description Default XXXXXXXXXXXXX 0 No mode 0 lt no beam Setup 0 Injection probe beam Injection setup beam Injection physics beam Prepare ramp Ramp Flat top Squeeze Adjust Stable beams Unstable beams Beam dump Ramp down Recovery Inject and dump Circulate and dump Abort Cycling Beam dump Warning No beam O ojo NID t JW e 1O 5 nN oo N 5 JO JO JO IO X X 16 WOR
21. ERFACE The VMEbus interface of the RF2TTC cards is implemented in its FPGA and based on VME interface developed by Peter Lichard for the TRT TTC board ATLAS It provides 2 types of VMEbus addressable resources as described in Table 1 Resource VMEbus access mode Description Control and status A32 D32 with 19 0 and AM code These are the registers that control the registers 0x09 behaviour of a RF2TTC card and provide information about its current status EPROM A32 D32 with 19 1 and AM code access to the EPROM is reserved for in 0x09 crate reconfiguration Table 1 VMEbus resources of the 2 the registers of the board are accessible using 0x09 AM A32 D32 The board address is the geographical address of the module if the manual rotary switches are set to 0x00 The address used to access the user space is hence defined as follows ADDRESS SWITCHES A31 A28 27 24 A23 A20 SW1 SW2 0x00 0 GEOG ADD SW1 0x00 or SW27z0x00 0 SW2 3 0 MSB SW1 7 4 LSB This picture shows a board numbered 0 000000 5 2 2 1 Reset registers Register Offset Purpose Access BSET Board Set Register assignment Description This register is declared in the VME64x as User defined Bset register It is used here to define partial reset functions QPLL only Delay25 chips only TTCrx only The bit definition is as follows Bit Value Write Read
22. ER_RESET Ox7FA44 TTCrx_REG FIFO 0 7 200 TTCrx_pointer to data 0 7 004 TTCrx_pointer to register 0 7 000 DELAY25 REG FIFO 0x7D200 ORBOUT DELAY25 GCR 0 70054 ORBOUT DELAY25 ORBmain Ox7D048 ORBOUT DELAY25 ORB2 0x7D044 ORBOUT DELAY25 ORBI Ox7D040 ORBIN DELAY25 GCR 0x7D034 ORBIN_DELAY25_ORB2 0x7D024 ORBIN_DELAY25_ORB1 0x7D020 BC_DELAY25_GCR 0x7D014 BC DELAY25 BCmain 0x7D00c BC_DELAY25_BCref 0x7D008 BC_DELAY25_BC2 0x7D004 BC DELAY25 BCI 0 70000 BCLEAR 0x00014 BSET 0x00010 A BR wo oO WY O0 WW W O2 WY WY C2 0 0000 o2 5 REVISION ID 0x00008 o2 5 0 00004 o2 5 MANUFACTURER ID 0x00000 o2 N Page33 03 10 06 27 02 07 19 04 2007 20 04 2007 30 04 07 08 05 07 29 10 2007 08 09 2008 13 09 2008 10 09 2008 08 10 2008 14 01 2009 19 01 2009 13 02 2009 3 LIST OF FIRMWARE UPDATES VERSION 0 01 0 1 AUTHOR BARON BARON DESCRIPTION first VHDL entity definition clock selection feature remove CR CSR space and use only User space inversion of orb int ext encoding in register to be like BC initial value for DAC AA Initial valu
23. KING MODE Name Offset Size WORKING MODE Ox7FA78 7 bits R W Description The bits in this register control the operational modes of the outputs of the RF2TTC Each bit corresponds to one signal Bit number Related output Bit Selected mode value Manual Automatic Manual Automatic Manual Automatic BCmain Manual Automatic Manual Automatic Manual Automatic ORBmain Manual Automatic ORB INT ENABLE Offset Size Access ORB_INT_ENABLE Ox7FA6C 3 bits R W Description This register controls the status of the BC counters that generate the internal orbit pulses Bit number Related orbit Bit value Counter mode Orbit 1 counts ticks Ec Disabled Orbit 2 counts BC2 ticks 711 Disabled Main orbit counts BCmain EE X Disabled ticks 17 ORB COUNTER ENABLE Offset Size Access ORB_COUNTER_ENABLE Ox7FA68 3 bits R W Description This register controls the status of the orbit pulse counters Once a channel has been enabled the registers ORBx_COUNTER count the orbit pulses of that channel number Related orbit Bit value Counter mode D PERIOD COUNTER ENABLE Offset Size Access PERIOD_COUNTER_ENABLE Ox7FA64 3 bits R W Description This register controls the status of the orbit period counters Once a cha
24. TERS SUMMARY MAN SELECT Offset Ox7FBFC Size bits 1 Access R W BEAM SELECT Ox7FBF8 1 R W 5 Ox7FBF4 R W BC1_QPLL_MODE Ox7FBFO R W BC1_DAC Ox7FBEC R W BC1_QPLL_STATUS 0x7FBE8 R BC2_MAN_SELECT Ox7FBCC R W BC2 BEAM SELECT Ox7FBCS8 R W BC2 NOBEAM SELECT Ox7FBC4 R W BC2_QPLL_MODE Ox7FBCO R W BC2 DAC Ox7FBBC R W BC2 QPLL STATUS Ox7FBB8 R BCref_MAN_SELECT Ox7FBAC R W BCref BEAM SELECT Ox7FBA8 R W BCref_NOBEAM_SELECT Ox7FBA4 R W BCref_QPLL_MODE Ox7FBAO R W BCref DAC Ox7FB9C R W BCref QPLL STATUS Ox7FB98 R BCmain MAN SELECT Ox7FB8C R W BCmain BEAM SELECT 0 7 88 R W NOBEAM SELECT Ox7FB84 R W BCmain QPLL MODE Ox7FB80 R W BCmain QPLL STATUS Ox7FB7C R W MAN SELECT Ox7FB6C R W ORBI BEAM SELECT Ox7FB68 R W NOBEAM SELECT Ox7FB64 R W ORBI POLARITY Ox7FB60 R W COARSE DELAY Ox7FB5C R W ORBI LENGTH Ox7FB58 R W ORBI INT PERIOD SET Ox7FB54 R W ORBI INT PERIOD COUNTER Ox7FB50 ORBI COUNTER Ox7FB4C Page31 PERIOD RD Offset 0x7FB48 Size bits 12 Access R
25. TTCrx in charge of receiving and transmitting the BST message to the FPGA ON TTCrx ready received frame is consistent and can be decoded OFF no consistent BST message Flashes when the RF2TTC generates a BERR Not implemented yet Flashes if the RF2TTC has replied to a VMEbus cycle Page29 2272 IMPROVEMENTS MADE ON THE PRODUCTION VERSION V3 2 7 1 Initialisation procedure The state of the Delay25 chips after a power up was not satisfactory as the outputs were all disabled The same for the TTCrx which does not allow by default the transmission of the broadcast words Finally the DAC in charge of the threshold adjustments are set to 1 25V by default after power up Hence the Delay25 TTCrx and DAC chips need to be initialised first and it requires using some internal protocols I2C or other controlled by VME accesses A solution was provided to ensure the board initialisation after power up sys reset or reconfiguration without using a crate processor This initialisation ensures that All the delay25 chips are enabled i e transmit the signals present at their inputs 0x40 is written in all of their delay registers the DACS are configured correctly to allow latching the input orbits if any set to OXAA The TTCrx chips is configured to transmit the BST message to the FPGA control register is set to OxFF the signals are set to INTERNAL by default Page30 2 8 REGIS
26. cessible via I2C are the following I2C reg address Register name Default decimal content After reset Fine Delay 1 00000000 Fine Delay 2 00000000 Coarse Delay 00000000 Control 10010011 Single error count 7 0 00000000 Single error count 15 8 00000000 Double error count 7 0 00000000 SEU error count 15 8 00000000 0 lt 7 0 gt 00000000 MasterModeA lt 1 0 gt ID 13 8 00000000 MasterModeB lt 1 0 gt I2C ID 5 0 00000000 Config 1 00011010 Config 2 10000100 Config 3 10100111 Status 11100000 Bits 7 0 00000000 Page22 Bits 15 8 00000000 Bits 7 0 00000000 Bits 15 8 00000000 Bits 23 16 00000000 Example of registers read and write via VME access Read control register I2C address 3 1 VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x3 register I2C address 2 VME READ AM 0x09 RegOFFSET 0xE000 the Data read has no meaning 3 VME READ AM 0x09 RegOFFSET 0xE200 Data should 0x000000FF after initialisation Write Fine Delay Register address 1 l VME WRITE AM 0x09 RegOFFSET 0xE000 Data 0x1 register I2C address 2 VME WRITE AM 0x09 RegOFFSET 0xE004 offset of the data register 0x0000YOURDATA Read fine delay register address 1 VME WRITE 0 09 RegOFFSET 0xE000 Data 0x1 VME READ AM 0x09
27. e for TTCrx control register is Oxff V3 of the hardware gt Manual LSB and MSB addresses are inverted signal tap removed after timing pbs with the delay25 read back data_o latched by clock in simple_I2C was not sync before modif to have consistency between orbit period register real orbit period and measured orbit period modif of the BST decoding to follow the 2 bytes of machine modes according to LHC OP ES 0005 v 1 0 bytes 26 and 27 previously only 27 compilation of files from may 08 for real time orbit reading and improvement of orbit length amp delay modification of machine mode mgr to have a latching of the Beam Mode register only after the 2 bytes have been transmitted to the TTCrx Adding of the orbit reading modification to allow a real time reading and storage in the FIFO plus an improvement of orbit length and delay correction on orb sel mgr on period fifo wr ena modif per fifo status reg to memorize every full empty until next read modif on mach mode mgr on mmode decode process to sync it with clock40des1 instead of clock modif on the qpll status registers keeps unlock and error active until next read action of the register modif on Orb sel mgr following a request from Markus the empty status given by a fifo rd is now latched only when rdreq is active to ensure that reading 0x4XXX means that the fifo is really empty Previously it meant that last word was being read
28. e rising edge of the orbit is in the setup time or hold time of the latch The window in which the orbit will be stably synchronized is of the order of 20ns out of 25 The way to choose the good value for these registers is described in 2 3 Calibration Procedures For details about the read protocol see above Bit definition see BC DELAY x register ORBOUT DELAY25 x Name Offset Access ORBOUT DELAY25 GCR 0 70054 8 bits R W ORBOUT_DELAY25_ORBmain 0 70048 ORBOUT DELAY25 ORB2 0x7D044 ORBOUT DELAY25 ORBI 0x7D040 Description These registers control the configuration of the Delay25 chips for the orbit output signals This adjustment is to allow the experiments fine tuning the orbit for its use in their trigger electronics For details about the read protocol see above Bit definition see BC DELAY x register Page21 TTCrx REGISTERS Offset Size Access TTCrx pointer to the register 0 7 000 8 bits R W 0 7 004 8 bits W TTCrx pointer to the data Description These are the two registers used to read and write all the internal registers of the TTCrx used to receive the BST message see TTCrx user manual Only one register requires to be accessed for the purpose of receiving BST message the control register internal address 0x03 Its value should be instead of 0x93 its default value The 17 added on bit 5 allows enabling the
29. for the Bunch Clocks They are then lengthened to more than 25ns finely delayed with 0 5ns steps before going into an FPGA grey block of the diagram where they are synchronized to their corresponding clock multiplexed with an internal orbit and coarse delayed Their length and polarity can be adjusted and they are then again finely delayed before being transmitted by the ECL drivers A global multiplexer also allows selection between the two orbits and an internal one synchronized to the Main Bunch Clock This orbit signal is called Main Orbit and can as well be finely delayed before being transmitted The BST Beam Synchronous Timing optical signal on the bottom left part of the diagram is received decoded and analyzed to recover the machine mode This mode is useful to know when the timing signals are stable and can be used In deed neither the Bunch Clocks nor the Orbit signals are fully guaranteed out of the physics modes flat top of the LHC energy curve It is thus advised to use internal signals when the machine mode indicates that there is no beam the adjustments are done using VME registers Many status registers are available as well as special configurations for stand alone or debugging work This document contains a description of all accessible registers of the 2 card as well as description of the generic S W that has been developed for this card At the end of this document some basic examples of configuration
30. he RF2TTC RF to TTC VMEbus Interface Card is an interface card between the optical receiver modules receiving timing signals coming from the SR4 building in Echenevex and the TTC electronics within the experiments ROPER extat 427 1228 88 The timing signals treated by the 2 are three 40 078MHz Bunch Clocks BC1 2 and BCref and two orbit signals Orb1 and Orb2 necessary to drive the 2 beam lines of LHC The RF2TTC module converts them into ECL signals and performs various adjustments on each signal before making them available for the in detector TTC electronics The three Bunch Clocks represented on the top part of the following diagram are all treated in the following way A comparator with an adjustable threshold first converts the input signal into a PECL signal before being multiplexed with an internal 40 078 clock in case of absence of the Bunch Clock on the front panel The signal is then shifted by an adjustable delay with 0 5ns precision before being cleaned by a QPLL and transmitted on the front panel via an ECL 50 Ohm coaxial cable driver with an AC coupled output A global multiplexer allows selection between the three Bunch Clocks and the internal clock to generate a fourth Bunch Clock output called Main BC which can also be delayed The two orbit signals middle and bottom right parts of the diagram are first converted using the same adjustable comparator stage as
31. he orbit input i e the orbit output is negative active ORBx COARSE DELAY Offset COARSE DELAY 0x7FB5C 12 bits Access ORB2_COARSE_DELAY Ox7FBIC ORBmain COARSE DELAY Ox7FADC Description This register allows the orbit output signal to be shifted by multiples of 25 ns with respect to the input It is set to O by default If set to O or 1 the output is shifted by the minimum intrinsic delay induced by the board itself about 194ns if the orbit out fine delay is O too If the coarse delay is set to C and the orbit out fine delay is set to F the total delay will be Total orbit delay 194 C 1 25 F 0 5 ns Values above OxDEB 3563 are illegal because they would result in a shift longer than the LHC orbit period 88 93 us ORBx LENGTH Offset Access LENGTH 0 7 58 ORB2 LENGTH Ox7FB18 ORBmain LENGTH Ox7FADS Description This register allows the orbit pulse to be stretched in steps of 25 ns It is set to O by default If set to O or 1 the width of the orbit pulse is 75 ns If set to L the width of the output pulse will be Orbit length lt 75 L 1 25 ns The largest pulse width with all 8 bits set to 1 is 6 4 us The default width of the internally generated orbit pulse is 75ns Page12 ORBx INT PERIOD SET Offset Access ORBI INT PERIOD SET 0x7FB54 12 bits ORB2_INT_PERIOD_SET Ox7FB14 ORBmain_INT_PERIOD_SET Ox7FAD4
32. hen stretched to 40 5 and then finally latched by one of the Bunch Clocks PECL Stretcher Delay 25 123 Orbit signal at the Comparator input of the board 5 5 m LORBx DAC 1 25V sinusoidal pulse V ORBx 0 416V 5 waORBx 0 00 1 25V Output 5ns Output 40 ns PECL pulse PECL pulse 0x00 The threshold is adjusted via the ORBx_DAC register according to the formula Threshold 1 25 value 2 5 255 ORBIN DELAY25 x 0x31 24 5ns 3 5 3 q The ORBx DAC registers are set to OxAA by default which corresponds to 0 416V This value should match perfectly with the level of the input signals However if you have any doubt or you want to adjust it better we advise you to respect the following procedure x 417 or 2 1 Set your board to receive BCx and Orbx from a reliable external source synchronised BC and Orbit with orbit period 3564BC Set the ORBx DAC to 0 Reset the Orbx fifo Read 100 times ORBx PERIOD FIFO RD While ORBx DAC lt OxFF ORBx DAC lt ORBx DAC 1 and go back to 3 You should get a window of threshold values of for example 0x09 0xF0 for which the 100 periods are all 2564 Then pick up one value in the middle of the range and set the DAC with it Page24 2 3 2 Orbit inputs delay adjustment ORBIN DELAY25 are 2 registers configuring the
33. her a VP110 or a VP315 CMS uses a PCI VMEbus link from CAEN and LHCb a USB VMEbus link from the same manufacturer In all four experiments the crate that houses the RF2TTC should be VME64X compatible as otherwise it is not possible use geographical addressing 4 1 2 S W Environment On the low end ATLAS and ALICE will use the vme rcc driver developed by ATLAS to communicate with the RF2TTC CMS and LHCb will use S W packages provided by CAEN for the respective interface The common S W will be programmed in a way that it is compatible with any of these bus access packages At the top end each experiment has to develop appropriate secondary libraries and applications to interface the RF2TTC to their respective control systems The development of the interface to the DIP server is also up to the experiments TEST PROGRAMS Currently there exists one program that comes in three flavours rf2ttcscope atlice for ATLAS and ALICE rf2ttsscope cms and rf2ttcscope Ihcb This interactive application can be used to read decode and write any register of the RF2TTC in a hopefully intuitive way If a users feels that some functionality is lacking he is welcome to contact the developer M Joos It is e g possible to extend rf2ttcscope by additional command line parameters such that certain tests can be executed from scripts A tcltk graphical user interface rf2ttc tcl is also available for test purpose It has been written for SBCs from Co
34. hips in reset mode 0 no effect Delay25 chips not in reset mode 1 remove BC1 QPLL from reset mode BCI QPLL chip in reset mode no effect BCI QPLL chip not in reset mode remove BC2 QPLL from reset mode BC2 QPLL chip in reset mode no effect BC2 QPLL chip not in reset mode remove BCref QPLL from reset mode BCref QPLL chip in reset mode no effect BCref QPLL chip not in reset mode remove BCmain QPLL from reset mode BCmain QPLL chip in reset mode no effect BCmainQPLL chip not in reset mode remove TTCrx chips from reset mode TTCrx chips in reset mode no effect TTCrx chips not in reset mode remove Board from reset mode Board in reset mode no effect Board not in reset mode Page7 2 2 2 Board Identification read only registers Register Address Value MANUFACTURER ID 0x00000 0x00080030 CERN BOARD ID 0x00004 0x0000016B REVISION ID 0x00008 Hardware version Prototype 0x2 Production 0x3 PROGRAM ID 0x0000C Firmware date number ol Last 19052009 19 May 2009 2 2 3 Board configuration registers BCx MAN SELECT BCx BEAM SELECT amp BCx NOBEAM SELECT Offset MAN SELECT Ox7FBFC 1 bit BC2_MAN_SELECT Ox7FBCC BCref MAN SELECT Ox7FBAC BEAM SELECT Ox7FBF8 BC2_BEAM_SELECT Ox7FBC8 BCref_BEAM_SELECT Ox7FBA8 5 Ox7FBF4
35. nabled 0 delay Reset the Orb fifo PERIOD COUNTER RESET Read 1000 times ORB2 PERIOD FIFO RD While ORBIN DELAY25 ORB2 5 0 Ox4F ORBIN DELAY25 ORB2 ORBIN_DELAY25_ORB2 1 and go back to c You should get a window called here Orb2 Wb of about 40 consecutive steps for which the 1000 periods are all 2564 OxDEC 5 ORBmain out Calibrate case c or and d or and e or and f Example of case c below a Set your board to have BCmain MAN SELECT BCI and ORBmain MAN Set ORBIN DELAY25 ORBI to 0x40 enabled 0 delay Reset the Orb fifo PERIOD COUNTER RESET Read 1000 times ORBmain PERIOD FIFO RD While ORBIN DELAY25 ORBI 5 0 lt Ox4F ORBIN DELAY25 lt ORBIN_DELAY25_ORB1 1 and go back to c You should get a window called here 1 Wo of about 40 consecutive steps for which the 1000 periods are all 2564 OxDEC Do the same procedure for d e and f You will get Orbl Wd Orb2 We Orb2 Wf 6 Finally find the best match a b For ORBIN DELAY25 ORBI between Wa Orbl Wc and 1 Wd see example below For ORBIN DELAY25 ORB2 between Orb2 Wb Orb2 We and Orb2 Wf 30 delay in ns ORBI Wc Page27 2 4 FIBRE CABLE CONNECTIONS Connector name To be connected to BST TTC encoded signal One of the BST optical fibres two are normally available one per ring The optical power level should be between 5dBm and 25dBm BC INPUTS
36. ncurrent Technologies VP110 and VP315 THE USER LIBRARY This library consists of a common source file that implements the access to the registers of the RF2TTC in a generic way and a number of files to implement glue layers to the VMEbus access libraries from ATLAS and CAEN respectively Page36
37. nnel has been enabled the FIFOs and ORBx PERIOD FIFO RD start measuring and storing the duration of orbit signals Bit number Related orbit Bit Counter mode value cece oe Page18 COUNTERS RESET registers Name Offset Function ORB_INT_RESET Ox7FA4C Reset the three counters that generate the internal orbits 1 2 and Main One bit per counter Same definition than the ORB_INT_ENABLE register PERIOD COUNTER RESET 0x7FA48 Reset the counters that measure the period of the orbit pulses 1 2 and Main At the same time the period FIFOs are cleared One bit per counter Same definition than the PERIOD COUNTER ENABLE register ORB COUNTER RESET 7 44 Reset orbit pulse counters 1 2 Main Description A reset is triggered by writing a 1 to the address of the respective register The 3 bits of the counter reset register can reset the counters of ORBI ORB2 and or ORBmain by writing various patterns Bit number Related orbit counter Bit value Counter mode e DELAY25_REG TTCrx_REG Offset Size Access DELAY25 REG 0x7D200 TTCrx REG Ox7E200 Description These registers are required to read values from the TTC and Delay25 registers described below Due to delays introduced by the I2C bus it is not possible to read these registers directly Instead a sequence of three steps is required 1 Read a dummy data word from the address of
38. p Ref Voltage Multiplexer sel LVDS2ECL 2 ORBITI INTERNAL Adjust NIM OUT ONT Stretch ECL2NIM be CUD MACHINE MODES BST E AD SIGNAL lt 2 TIC FRAMES BC2 clock Fs ORBIT2 M BST decoder NECL OUT ECL Driver Fine H BC2 CLOCK Delay REMOTE CONTROL LVDS2ECL ORBIT2 NIM OUT MACHINE gt ECL2NIM FINE DELAYS CONTROL INTERNAL Multiplexer 0 MAIN ORBIT NECL OUT BUS E n ECL Driver VME INTERFACE ES LVDS2ECL Z STATUS REGISTERS di MAIN ORBIT NIM OUT ECL2NIM VME BACKPLANE 2 b ECL2NIM i Orbit sel If INTERNAL CLOCK MAIN BC CLOCK jf CONVERSION USING BSR17A TRANSISTORS INTERNAL FPGA M f CLOCK MAIN BC RF2TTC module diagram RF2TTC HARDWARE 2 1 STANDARDS AND POWER SUPPLIES The RF2TTC board is a VME64x 6U board It requires the following power supplies 3 3 2 5 5 03 12 14 Total power 26W 2 2 VMEBUS INT
39. sted for a special need ex increase the negative orbit amplitude It is possible to increase or decrease all these amplitudes just by changing the value of one resistor per output Please contact Stephane DETRAZ or Sophie BARON if you want to do it 2 6 FRONT PANEL LEDS LED Description LOCK Displays the state of the QPLL chip connected to the selected BCI signal ON locked OFF not locked BC2 LOCK Displays the state of the QPLL chip connected to the selected BCI signal ON locked OFF not locked BCREF LOCK Displays the state of the QPLL chip connected to the selected BC1 signal ON locked OFF not locked BCmain LOCK Displays the state of the QPLL chip connected to the selected BCI signal ON locked OFF not locked ORBI OK Monitors the presence of the external orbit after the comparator ON signal present OFF no signal When OFF it can mean either that the orbit is not present or that the DAC setting the threshold at the input does not deliver an adapted threshold ORB2 OK Monitors the presence of the external orbit after the comparator ON signal present OFF no signal When OFF it can mean either that the orbit is not present or that the DAC setting the threshold at the input does not deliver an adapted threshold BEAM Monitors if the current machine mode corresponds to a mode or a NO BEAM mode ON BEAM OFF NO BEAM BST ready Monitors the state of the
40. the TTC or Delay25 register that is to be read out 2 Wait for at least 2 ms 3 Read the data value from the DELAY25 REG or REG FIFO contents of the read access to delay25 and TTCrx chips Page19 If multiple registers are to be read one can group dummy reads step 1 and data reads step 3 such that they are only separated by one 2 ms delay This pipelining however works for up to 256 read requests BC DELAY25 x Offset Used Size Access BC_DELAY25_GCR 0 70014 8 bits RYW BC DELAY25 BCmain 0x7D00c BC_DELAY25_BCref 0 70008 DELAY25 2 0x7D004 BC DELAY25 0 70000 Description These registers control the configuration of the Delay25 chips for the BC signals These chips ensure the BC signal to be shifted by steps of 0 5ns with a jitter lower than 19ps rms For details about the read protocol see above Bit definition from Delay25 manual BC DELAY25 registers The bit allocation of each channel control register is as given in the following table Bits Del lt 5 0 gt control the delay for each channel and the Enable bit enables the channel output Upon a reset bit Enable and bits lt 5 0 gt are cleared The delay chip must be manually re enabled At power up however an internal routine in the RF2TTC fpga enables all the delay25 chips Control registers CRO to 4 bit allocation with their state after reset 7 B6 B5 B4 B3 B2
41. utput follows input BCx QPLL MODE Offset Access QPLL MODE Ox7FBFO BC2 QPLL MODE Ox7FBCO BCref QPLL MODE Ox7FBAO QPLL MODE 0 7 80 Description These registers define the QPLL locking mode Description 0 Re lock only after a reset 1 Re lock automatically if lock gets lost autorestart Oplls are all set to autorestart 1 by default More information about the QPLL locking procedure and how to handle it within an experiment http ttc upgrade web cern ch ttc upgrade Study for OPLL on 2 during RF resynchronization pdf Page9 BCx QPLL STATUS STATUS Offset Ox7FBES8 Access BC2 QPLL STATUS Ox7FBB8 BCref_QPLL_STATUS Ox7FB98 BCmain QPLL STATUS Ox7FB7C Description These registers contain the status of the QPLLs of the BC channels Bit 1 indicates that the QPLL detected an error and bit O indicates the locking status These error and unlocked bits are latched and if an error or a loss of sync briefly occurs will remain at 1 until the register has been read 1 Description 0 QPLL OK 1 QPLL has error 0 QPLL not locked 1 QPLL locked a o0 e A ORBx MAN SELECT ORBx SELECT NOBEAM SELECT EPI Offset Size Access ORB1_MAN_SELECT Ox7FB6C bit R W
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