User Manual
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1. AD484 User manual February 2007 www 4dsp com 12 HOS AD484 user manual 3 3 Clock tree The AD484 clock architecture offers an efficient distribution of low jitter clocks In addition to the PCI Express bus the MGT reference clocks of 106 25MHz and 125MHz Epson EG2121CA make it possible to implement several standards over the MGT I Os connected to the optical transceivers Both FPGAs receive a low jitter 125MHz clock A low jitter programmable clock able to generate frequencies from 62 5MHz to 255 5MHz in steps of 0 5MHz is also available This clock management approach ensures maximum flexibility to efficiently implement multi clock domains algorithms and use the memory devices at different frequencies Both clock buffer devices CDM1804 and the frequency synthesizer I1CS8430 61 are controlled by the Virtex 4 device A 16MHzZ PCI PCIax Tel Low jitter 66 1 S3SMHz T E eae DDR A TOL ow jir T MGT clocks Virtex 4 fr device B device A 106 25MHz LVPECL LVEMOS 31o HE CPLD synthesizer Virtex 4 Figure 7 Clock tree 3 4 Memory resources 3 4 1 QDR2 SRAM Four independent QDR2 SRAM devices are connected to the Virtex 4 device B The QDR2 SRAM devices available on the AD484 are 2M words deep 8Mbytes per memory device Please note that only three QDR SRAM devices are available to the user if the XC4VLX40 XC4VLX60 or XC4VSX55 FPGA device is mounted on board 3 4 2 DDR2 SDRAM Two2. The Virtex 4 device B interfaces to four 8Mbytes QDR2 SRAM devices with 32 bit data bus Please note that the four QDR2 SRAM devices are only available with the LX80 LX100 and LX160 devices For smaller Virtex 4 FPGAs LX40 LX60 and SX55 only three QDR2 SRAM devices are connected to the FPGA AD484 User manual February 2007 www 4dsp com 9 amp AD484 user manual OS V1 2 3 2 FPGA devices configuration 3 2 1 Flash storage The FPGA firmware is stored on board in a flash device The 128Mbit device is partly used to store the configuration for both FPGAs In the default CPLD firmware configuration the Virtex 4 devices A and B are directly configured from flash if a valid bitstream is stored in the flash for each FPGA The flash is pre programmed in factory with the default firmware example for both FPGAs 929GL126M 128Mbit Flash 8 bit parallel configuration CoolRunner ll CPLD Virtex 4 device A XC2C256 CP132 Figure 3 Configuration circuit 3 2 2 CPLD device As shown on Figure 2 a CPLD is present on board to interface between the flash device and the FPGA devices It is of type CoolRunner ll The CPLD is used to program and read the flash The data stored in the flash are transferred from the host motherboard via the PCI bus to the Virtex 4 device A and then to the CPLD that writes the required bit stream to the storage device A 31 25 MHz clock connects to the CPLD and is used to generate the configuration
3. Pm 023 24 25 Pn4 1024 P16 mie Pm 1035 26 27 Pn4oze Ris Pig Pm 0277 28 29 Pn4 1028 P21 P20 Pn4 1029 30 31 Pn4i030 R7 R6 Pm 1031 32 33 P 032 L9 m5 Pmio33 34 35 Pn4 1034 15 aD Pn4 1035 36 37 Pn4 1036 aDbio L4 Pn 1037 38 39 Pn4 1038 13 AB11 Pn4 1039 40 41 Pn4 1040 acii m Pmion 42 43 Pnm 042 N4 T9 Png tas 44 45 Pn4 1044 78 P5 Pd 1045 46 47 Pm 046 R5 amo Pm 1047 48 49 Pn4 1048 aB10 P4 Pm 1049 50o 51 Pn4io50 R3 wio Pm 1051 52 53 Pn4 1052 y10 Na Pm io53 54 55 Pn4 1054 P3 ue P i055 56e 57 Pn 1056 u5 T4 Pm 1057 58 59 Pn4 1058 73 u7 Pn t059 6o 61 Pn4 i060 ve u4 Png toi 62 63 Pn4_ 1062 V4 Ug Pn4 1063 64 Table 2 Pn4 pin assignment AD484 User manual February 2007 www 4dsp com 8 HOS AD484 user manual 3 1 2 Virtex 4 device B 3 1 2 1 Virtex 4 device B family and package The Virtex 4 device B is dedicated to interfacing to the A D circuitry and can also perform Digital Signal Processing algorithms It is available in the Virtex 4 SX or LX family devices and is packaged in a 1148 ball Fineline Ball Grid array In terms of logic and dedicated DSP resources The FPGA B can be chosen in 5 different sizes SX55 LX40 LX60 LX80 LX100 and LX160 3 1 2 2 Virtex 4 device B external memory interfaces
4. 16 bit DDR2 SDRAM devices of 128MBytes each are connected to Virtex 4 device A The two memories share the same address and control bus and have their own data bus This memory resource can be accessed by the PowerPC processor in the Virtex 4 device A or can be used as a data buffer for custom user logic AD484 User manual February 2007 www 4dsp com 13 amp AD484 user manual oS V1 2 3 5 A D inputs and outputs main characteristics Analogue inputs AC coupled option 2 4 Vp p 11 5 dbm 50 Ohm Full scale AC coupled via RF transformer DC coupled option 1 15 Vp p Gain amplifier 6dB centered around 0 DC coupled via amplifier Gain can be adjusted to a required input amplitude centered around 0 Minimm gain 6dBs which should allow input swing 0 575V as full scale ADC single ended inputs are to be connected to a 50Q source Source impedance matching implemented between RF transformers poof and ADE Bandwidth ADC bandwidth 750 MHz External Trigger inputs Format DC coupled and Single ended Termination implemented at the connector Differential on option 3 3 V PECL Input Voltage range 1 5 3 3 Volts peak to peak Impedance 50 ohm Frequency range 62 5MHz maximum ADC Output Output Data Width 14 bit 2 s Compliment or offset binary Changeable via control register 82dBs maximum manufacturer SFDR 70dBs maximum manufacturer SNR Table 6 A
5. amp AD484 user manual OS V1 2 AD484 User Manual 4DSP Inc 955 S Virginia Street Suite 214 Reno NV 89502 USA Email support 4dsp com This document is the property of 4DSP Inc and may not be copied nor communicated to a third party without the written permission of 4DSP Inc 4DSP Inc 2007 amp AD484 user manual oS V1 2 Revision History Date Revision Version 02 03 07 First release ao 03 29 07 Corrected typos 1 1 04 12 07 Added more details regarding clock synchronization 1 2 AD484 User manual February 2007 www 4dsp com AD484 user manual V1 2 Table of Contents 1 Acronyms and related documents cccceeeseeeeseseeeseeeeseeeeseeeeseeeeeseseeneeeeneeseesenoenees 4 1 1 PAC ORY NG sco cere a E seco radere E agen E 4 1 2 Related DOCUMEMS ssacciccececesecedeccaeuesncnssatacdtdssnedan bachemhedatsdatumeees poseseceeneceadanttssereiedd 4 k3 GENCY al GOS CHOON assesseer delve EE EEEE E 5 2 WAS CANNON E E E E E A E E 6 2 1 Requirements and handling instructions cccceeecseeeceeeeeeeeceeeeseeeseeeeseeseeeeneeess 6 2 2 Firmware and SO TW A ac chee ctoscietetenctenso acter sigeiaeistestra secs ecievaciad oactteatbans lt idedeaiseslceeieemekereesegneueiaien 6 3 DESO acess sc eet ce sees ett er ine oe ee A A 6 3 1 FE PCV GSS ccc sot e esau aqeuiee sone E A 6 3 1 1 VINEX A re s e ay ere ener ner eee ee ante E e nee ee eae aero eee aan rer 6 3 1 2 Nh iC D casera oases esse
6. clock sent to the FPGA devices At power up if the CPLD detects that an FPGA configuration bitstream is stored in the flash for both FPGA devices it will start reading programming the devices in SelecMap mode Do NOT reprogram the CPLD without 4DSP approval The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from a host computer via the JTAG connector The FPGA devices configuration can also be performed using the JTAG 3 2 2 1 DIP Switch A switch J1 is located next to the JTAG programming connector J6 see Figure 4 The switch positions are defined as follows AD484 User manual February 2007 www 4dsp com 10 AD484 user manual Figure 4 switch J1 location HOS Switch 1 ital SAITI Swi OFF ON Sw2 Sw3 Sw4 Default setting The Virtex 4 device A configuration is loaded from the flash at power up used only if the Virtex 4 device A cannot be configured or does not perform properly with the switch in the OFF position Reserved Reserved Reserved Virtex 4 device A safety configuration loaded from the flash at power up To be Table 3 Switch description 3 2 2 2 LED and board status Four LEDs connect to the CPLD and give information about the board status LED 0 Flashing FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA A not configured OFF FPGA A config
7. D484 A D characteristics AD484 User manual February 2007 www 4dsp com 14 amp AD484 user manual OS V1 2 3 5 1 Analog inputs The module is built around four Tl ADS5500 14 bit sampling analog to digital ADCs Analog data enters the module via four SMA connectors on the front panel one for each channel Both signals are then conditioned AC coupling as standard via RF transformers DC optional via Texas Instrument amplifier THS4509 before being digitized 3 5 2 Clock input and reference clock distribution The ADC devices get their own sampling clock which can be either on board generated or from an external reference or an external clock common to all ADCs via an SMA connector on the front panel All samplings clocks are generated by the same chip It allows having them all synchronized to a single reference clock The on board clock uses the VCXO locked on an on board 10MHz reference The reference clock also can be external In that case the VCXO is still used It is also possible to input an external clock that is directly used to sample the analog signals In all cases all sampling clocks are synchronized to the same clock source 3 5 3 Multi module Synchronization Several AD484 cards can be cascaded and still be synchronized since either the external reference or the external clock can be passed to the next module in the chain The external reference goes through a 0 delay buffer and is then output via an SMA connector on t
8. dequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system 9 Warranty B n a a a y Basic Warranty included 1 Year from Date of Shipment 90 Days from Date of Shipment AD484 User manual February 2007 www 4dsp com 20
9. e 1 2V 12A QDR2 DDR2 SDRAM core and 1 8V 10A O banks Virtex 4 devices I O banks Virtex 4 device B WO bank 1 8V 2 5 3 3V 1 5A AD484 User manual February 2007 www 4dsp com 17 HOS AD484 user manual PMC XMC connectors 12V 12V 5V 3 3V E Low noise 2 5V regulator Switching 1 8V regulator Switching 1 2V regulator Switching 0 9V regulator 12V SV 3 3V 12V External Power connector Figure 9 Power supply An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature The ADT 7411 data are constantly passed to the Virtex 4 device A Measurements can be accessed from the host computer via the PCI bus A software utility delivered with the board allows the monitoring of the voltage on the 2 5V 1 8V 1 2V and 0 9V rails It also displays the Virtex 4 device B junction temperature 4 1 External power connector for stand alone mode An external power connector J2 is available on side 2 of the PMC next to the PMC connectors It is used to power the board when it is in stand alone mode This is a right angled connector and it will be mounted on board only if the card is ordered in its stand alone version AD484 SA The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board Do no
10. g low jitter clock and special routing are used to achieve the performances required by this standard Please refer to the Front Panel Optical transceivers section of this document for more details 3 6 3 1 1 5 LED Four LEDs are connected to the Virtex 4 device A In the default FPGA firmware the LEDs are driven by the Virtex 4 device B via the Virtex 4 device A Virtex 4 device B interface The LEDs are located on side 2 of the PCB in the front panel area o FPGA LED3 5 Me eE 3 Seki FPGA LED1 a On J Syed FPGA LEDO Figure 2 FPGA LED locations AD484 User manual February 2007 www 4dsp com 7 amp AD484 user manual OS V1 2 3 1 1 6 Pn4 user I O connector The Pn4 connector is wired to the Virtex 4 device A The 32 lower bits are available only if an XC4VFX60 device is mounted on board The 32 higher bits are available only if PCI 32 bit is used and only if specified at the time of order All signals are user defined 3 3V LVTLL LVCMOS Signal ae FPGA Signal 1 Pn4ioo mo mo Pmio 2 3 Paio2 nu m1 Pmio3 4 5 Paio4 n7 Nag S Pmt 05 6 7 Paio ne Pe Pmio7 8 9 Pn4ios Pio Pu Pmio9g 10 11 Pn4toto po ng Pmion 12 13 Pn 012 R8 Pa P4013 14 15 Pn 014 Re R7 Png 015 16 17 Pa016 Nn2 ma Pm1017 18 19 Pn4 018 m20 m9 Pn 1019 20 21 Pn4 1020 P19 m9 Png 1021 22 23 Pn4 1022 N18 m7
11. he front panel Please note that synchronisation is in frequency and not in phase AD484 User manual February 2007 www 4dsp com 15 HOS AD484 user manual 3 6 Front Panel optical transceivers Four 2 5Gb s optical transceivers LTP ST11M are available on the AD484 in the front panel area They are connected to the MGT I Os of the Virtex 4 device A Infiniband protocols as well as Gigabit Ethernet and Fibre channel SFPDP can be implemented over the transceivers Lower rate optical transceivers 2 125Gb s and 1 0625Gb s are available in the same form factor Two low jitter clocks 106 25MHz and 125MHz are directly connected to the MGT clock inputs so multi rate applications can be implemented on the AD484 The MGT banks have power supplies independent from the digital supply provided to the FPGAs in order to insure low noise and data integrity The LT1963 device will be used to generate the 1 2V 1 5V and 2 5V necessary for the MGT to operate The power filtering network includes a 220nF decoupling capacitor and ferrite bead MP21608S221A per power pin The signal differential pairs are routed on a specific inner layer with one reference GND plane on each side of the layer stack up The optical transceivers are an ideal communication link to transfer digitized and processed data to a remote system eg storage system by offering an aggregate bandwidth of 1 25GBytes s PMC edge Front Panel Low jitter MGT clocks O
12. her an XC4VFX20 or XC4VFX6O0 in a Fineline Ball Grid array with 672 balls FF672 3 1 1 2 Power PC embedded processor Up to two IBM PowerPC RISC processor cores are available in the Virtex 4 device A This core can be used to execute C based algorithms and control the logic resources implemented in the FPGA 3 1 1 3 Virtex 4 device A external memory interfaces The Virtex 4 device A is connected to a 128Mbytes SDRAM bank with a 32 bit data bus width This memory resource can be used by the PowerPC core or can serve as data buffer AD484 User manual February 2007 www 4dsp com 6 HOS AD484 user manual 3 1 1 4 PCI interface The Virtex 4 device A interfaces directly to the PCI bus via the PMC Pn1 Pn2 and Pn3 connectors or to the PCl e bus via the Pn5 An embedded PCI core from Xilinx is used to communicate over the PCI bus with the host system on the motherboard PCl e 4 lanes PCI X 64 bit 66MH2 133MHz PCI 64 bit 66MHz and PCI 32 bit 33MHz are supported on the AD484 The bus type must be communicated at the time of the order so the right Virtex 4 device A firmware can be loaded into the flash prior to delivery The following performances have been recorded with the AD484 transferring data on the bus gt PCI X 64 bit 133MHz 750Mbytes s sustained gt PCI X 64 bit 66MHz 425Mbytes s sustained gt PCI 32 bit 33MHz 112Mbytes s sustained The PCl express 4 lane is using the MGT I Os on the Virtex 4 device A Power filterin
13. l ING nesei e E E ET A E 19 6 3 ONGC HON COON eepe E e E E E E E E EEY 19 E E E E OO EA E E EEN E E E E E 19 I E ce acc A E A A E A T 20 NVA NAY e E E sescegeceenscectiosecsscuneuede 20 AD484 User manual February 2007 www 4dsp com 3 amp AD484 user manual oS V1 2 1 Acronyms and related documents 1 1 1 2 Acronyms JTAG Join Test Action Group LED Light Emitting Diode PCI Peripheral Component Interconnect PCl e PCI Express PLL Phase Locked Loop SDRAM Synchronous Dynamic Random Access memory SRAM Synchronous Random Access memory Table 1 Glossary Related Documents IEEE Std 1386 1 2001 IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC ANSI VITA 32 2003 Processor PMC ANSI VITA 39 2003 PCI X for PMC and Processor PMC ANSI VITA 42 0 2005 XMC Switched Mezzanine Card Auxiliary Standard IEEE Std 1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family Xilinx Virtex 4 user guide Xilinx PCI X core datasheet Xilinx Virtex 4 Rocket I O guide AD484 User manual February 2007 www 4dsp com 4 HOS AD484 user manual 1 3 General description The AD484 is a high performance PMC XMC digitizer module dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements The AD484 can interface to a PCl express PCI X and or PCI bus In addition to four 125MSPS A D channels the AD484
14. nce erent eee sede ecieamioas ematineees eeeeetinceseaetonieeanmanaes 9 3 2 FPGA devices CO MNIG UAT O Meecssnczeesee5s ccezcenunesdetooaeicsSaonansereoadensdenduanspszabagedoietonccect 10 3 2 1 ESARETTE E E E 10 3 2 2 WB 0 2 6 ee eee e A ee E ee eee eee 10 3 2 3 UTP Go exces te cccen neces senesccecqnaaweneee E E 12 3 3 RO capes Ne scree stent E EE ce sees hie cpeeceseeene 13 3 4 Memory resources eat onesonle axndaprestenasaiuenntsdavussenasesanans nee veudtorsaennactaseucustosssesoanmnnsedates 13 3 4 1 ID S RANE sncessocaezescenetovsesencentere concussteestessanboceeeseceneaessacaceecuasseoneeesietenccoss 13 3 4 2 PORZ SDRAM eeeee ee ee meen E eee cee een nee tee eae 13 3 5 A D inputs and outputs main ChAaractePiStiCS ccccceeeeceeeeseeeeeeeeeeeeseeeeeeeeneeeenees 14 3 5 1 AOT ADUS cers tse tchstei ts cormsouia E E T A 15 3 5 2 Clock input and reference clock distribution cece eececeeeeeeeeceeeeeeeeeeeeeees 15 3 5 3 Multi module Synchronization ccccceccceeeeeecceeeeeceeeeecsaeeeeeaeeeeesaeeeesaaeeeesaes 15 3 6 Front Panel optical transceivers ccccecccseecseeceeeeceeeeceeeceeeeceeeceueeceeeceeeeeeeeseeees 16 4 Pow rrteguiemenis soseri EAE 17 4 1 External power connector for stand alone mode cccceceeeeeeeeeeeeeeeseeeeeaeeeeeees 18 5 SVSlemM Slde VIC eosin EEE aE EAA aE EA EE 19 6 ENVronNMEM sisine aE aa Esana aaa 19 6 1 TONDE U e E E E E sonueetsomsouuee tes 19 6 2 JON SCHON CO O
15. offers fast on board memory resources and two Virtex 4 FPGAs Up to 4x 2 5Gbps optical transceivers for serial FPDP or gigabit Ethernet applications are available for communication with external systems The AD484 is mechanically and electrically compliant to the standard and specifications listed in section 1 2 of this document The AD484 implements a comprehensive clock circuitry that allows synchronisation among the converters and cascading modules for multiple receiver systems as well as the use of an external reference clock It provides a complete conversion solution and stands as a platform that can be part of a receive base station fee ee External External EFAA triggers Analog inputs clocks transceivers ji G DE i i 6 if 6 l Gigabit Ethernet Ei cour ae Clocks oscillator distribution 125MHz QDR2 SRAM QDR2 SRAM p ji Configuration circuit XC4VLX40 60 GE XC4VLX80 100 160 XC4VSX55 Not on LX40 60 or SX55 xd 88 VIRTEX s D 2 FPGA A XC4AVEX20 60 ee Pil bus MGT ee Power supply DC DC converters p y User VO PCI X PCI 66 33MHz 64 32 bit PCI Express Figure 1 AD484 block diagram AD484 User manual February 2007 www 4dsp com 5 amp AD484 user manual oS V1 2 The AD484 converts 4 analogue signals into four 14 bit resolution digital data flows with a sampling frequency up to 125MHz The clock source can be set to external or internal u
16. ptical 4 Trancer Virtex 4 Virtex 4 i 1275MH Optical vi ee device B do ae O MGT GT Optiesl a as Trance ver Optical XMC Traniceinver PCl axprass Figure 8 Optical transceivers AD484 User manual February 2007 www 4dsp com 16 amp AD484 user manual OS V1 2 4 Power requirements The power is supplied to the AD484 via the PMC and or XMC connectors Several DC DC converters generate the appropriate voltage rails for the different devices and interfaces present on board The AD484 power consumption depends mainly on the FPGA devices work load By using high efficiency power converters all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm After power up the AD484 typically consumes 5W of power For precise power measurements it is recommended to use the Xilinx power estimation tools for both FPGA A and B The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case resources are used to their maximum level connected to the front panel daughter card Virtex 4 device A I O bank 3 3V 4A connected to the PCI bus Flash CPLD front Panel I O daughter card A D circuitry MGT power supply 1 2V 1 5V 2 5V 1 7A 0 5A 0 01A respectively Table 7 Power supply Device Interface Voltage Maximum current rating DCI and memory reference 0 9V 5A voltage Virtex 4 device A amp B cor
17. sing the software and firmware settings available to users Please note that the clock generation on board is using low jitter clock synthesizers 2 Installation 2 1 Requirements and handling instructions e The AD484 must be installed on a motherboard compliant to the IEEE Std 1386 2001 standard for 3 3V PMC or on a motherboard compliant to the XMC Switched Mezzanine Card Auxiliary Standard e Do not flex the board e Observe SSD precautions when handling the board to prevent electrostatic discharges e Do not install the AD484 while the motherboard is powered up 2 2 Firmware and software Drivers API libraries and a program example working in combination with a pre programmed firmware for both FPGAs are provided The AD484 is delivered with an interface to the Xilinx PCI core in the Virtex 4 device A and an example VHDL design in the Virtex 4 device B so users can start digitizing and performing data manipulation right out of the box For more information about software installation and FPGA firmware please refer the AD484 Get Started Guide and to the Programmer s guide available online 3 Design 3 1 FPGA devices The Virtex 4 FPGA devices interface to the various resources on the AD484 as shown on Figure 1 They also interconnect to each other via 86 general purpose pins and 2 clock pins 3 1 1 Virtex 4 device A 3 1 1 1 Virtex 4 device A family and package The Virtex 4 device A is from the Virtex 4 FX family It can be eit
18. t connect an external power source to J2 if the board is powered via the PMC connectors Doing so will result in damaging the board The external power connector is of type Molex 43045 1021 Each circuit can carry a maximum current of 5A The connector pin assignment is as follows Pin Signal Signal Pin 41 33vV 33av 2 Fo 3 5v 5v 4 Table 8 External power connector pin assignment AD484 User manual February 2007 www 4dsp com 18 HOS AD484 user manual 5 System Side view The following diagram shows a side view of the AD484 mounted a motherboard RF Daughtercard PCB Inter PCB Connector vm Loo AS AKA TS EE See Figure 10 System side view 6 Environment 6 1 Temperature Operating temperature e 0C to 60 C Commercial e 40 C to 85 C Industrial Storage temperature e 40C to 120C 6 2 Convection cooling 600LFM minimum 6 3 Conduction cooling The AD484 can optionally be delivered as conduction cooled PMC The AD484 is compliant to ANSI VITA 20 2001 standard for conduction cooled PMC 7 Safety This module presents no hazard to the user AD484 User manual February 2007 www 4dsp com 19 J SS AD484 user manual 8 EMC This module is designed to operate from within an enclosed host system which is build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an a
19. ured LED 1 Flashing FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA B not configured OFF FPGA B configured LED 2 Flashing The Virtex 4 device A has been configured with the safety configuration bitstream programmed in the flash at factory Please write a valid Virtex 4 device A bitstream to the flash ON Flash is busy writing or erasing OFF Flash device is not busy LED 3 ON CRC error Presumably a wrong or corrupted FPGA bitstream LED 3 has been written to the flash Once on this LED remains on OFF No CRC error detected Table 4 LED board status February 2007 AD484 User manual www 4dsp com 11 HOS AD484 user manual CPLD LED3 CPLD LED2 CPLD LED1 aaa CPLD LEDO las MELEE SEEPS cf Figure 5 CPLD LED locations 3 2 3 JTAG A JTAG connector is available on the AD484 for configuration purposes The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope The JTAG connector is located on side 1 of the PCB in front see Figure 6 tck tdo JTAG connector k ean a N AILE ga i bat 4 5 f 5 A a 4 am l z F aa 1 i on EH IR g j fi A pmm Co Rs ng La les an tj i 1 AA 7 a De g arla H asta 1 A Y 4 bys rl Figure 6 JTAG connector J6 location The JTAG connector pinout is as follows Table 5 JTAG pin assignment
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