Home

Acquitek CH Series - Egmont Instruments

1. CH Series Product Line CH 3160 CH 3150 CH 3161 CH 3151 CH Series User Manual 4 analog inputs O analog outputs 50 Ohms 2 analog inputs 2 analog outputs 50 Ohms 4 analog inputs 0 analog outputs 75 Ohms 2 analog inputs 2 analog outputs 75 Ohms Page 7 A ACQUITEK WwW Installation CH Series Installation To install the CH Series hardware and software complete the following steps Install the Acquitek Data Acquisition Hardware e Turn off your computer and disconnect the power cord e Locate a free PXI expansion slot e Carefully remove the card from its packaging e Insert the card into the PXI expansion slot and activate the latch e Reconnect the power cord Connect the Cables e Connect the IO cables to your external devices or breakout board Install the Windows Device Drivers e Turn on the computer e When Microsoft Windows boots it should discover the new device and launch the New Hardware Wizard e Insert the Acquitek Data Acquisition Setup CD into your CD ROM drive e Direct the New Hardware Wizard to search the CD ROM drive for the device drivers e Windows may warn that the drivers are not authenticated Proceed with installation e After the drivers are installed remove the CD and reboot your computer CH Series User Manual Page 8 A AE Install the Application Software and Third Party Drivers Insert the Acquitek Data Acquisition Setup CD into your CD ROM drive Run Setup exe from the
2. conjunction with an Acquitek CH or XH Series high speed analog I O board The signal path is passive so the mux is bi directional i e it can be used on either the inputs or outputs of the CH or XH board The control interface utilizes a non volatile configuration identity so that up to eight B 1250s can be controlled by a single CH or XH board The low loss and excellent gain flatness allow cascading of several B 1250s with no significant signal degradation Architecture A block diagram of the B 1250 is shown in figure 9 1 below Four bi directional mux terminals can be connected to a single common terminal Mux terminals not connected to the common terminal are resistively terminated Nominal termination resistance is 50 Ohms Contact the factory for a 75 Ohm version Switching elements are mechanical relays for low loss and excellent gain flatness They are non latching relays so while powered down on power up and prior to the first software switch command all mux terminals are terminated and the common terminal is open A ACQUITEK CH Series User Manual Page 72 VI DB 9 Control Interface Figure 9 1 B 1250 Block Diagram Connection Up to eight B 1250 multiplexers can be controlled by one CH board In the tree configuration shown in figure 9 2 this allows up to 26 inputs to be muxed into the CH 3150 board Note also that the B 1250 is bi directional The same type of tree configuration allows expansion for drivin
3. terminated load i e up to 20Vpp or 10V Be sure that this voltage will not damage the load The output amplifier has a very low noise voltage level of 1 7 nV sqrt Hz It operates at a gain of 10 At low signal levels when the 2nd stage 20 dB attenuator is active the CH analog output delivers only 140 dBm Hz into a 50 Ohm load excluding D A quantization noise At higher levels when the 20 dB attenuator is not active the noise level increases to approximately 130 dBm Hz In addition to the two analog outputs there are sixteen DIO s which can be driven as outputs The DIO s must be set as input or output The DIO pins are divided into two 8 bit ports All pins in each port must be set for the same direction Pins can be written in two ways A simple single write mode which is asynchronous to the D A clock is useful for outputs which do not change quickly A clocked mode in which the DIO s are driven synchronously with the D A clock is also available In this mode the DIO s share the output data with the Analog Output 1 channel D A converter The DIO output is driven through a 47 Ohm source termination resistor to improve signal integrity of high speed switched signals ACQUITEK CH Series User Manual Page 16 Ai Triggers The CH and XH series of boards support a variety of triggering options Trigger sources are Analog Input 0 Analog Input 1 External Digital The XH board also supports additional PXI triggers See the X
4. M ISA Bridc 12 82371AB EB MB PIIX4 E M EID 8 82371AB EB MB Pllx4 E M USE 8 82371MB PlIX4M Power Manage MA Crystal 054281 SoundFusion PCI BE Unknown 29 3C905C TX Fast Etherlink for PC b 5 Inspiron 2100 Laptop Integrated N Rage P M Mobility AGP 2x Ea Acquitek DAD Board Demo BE Software BEAcquitek 18 Acquitek Enumerator FS Acquitek Control Center FS Acquitek Bench BE System 18 Windows NT 2000 XP Thid party Info Configure Test Serial Number DR123456789 Device Number 1 The information displayed on the Info Tab varies according to the device or module selected in the System Tree Selected Acquitek hardware devices display their serial number and the configured device number Other hardware devices display PCI configuration data Software modules display version resource information if available along with file date and size CH Series User Manual Page 29 A ACQUITEK WwW Configuration Tab Acquitek Control Center File Edit View Help Device Number Giro PA MEE ioi 82443BX ZX 440BX Zx CPU to PCI Bridge AGP Im 82443BX 2 440BX ZX PCI to AGP Bridge 182371EB MB PIIX4E M ISA Bridge 182371AB EB MB PIIX4 E M EIDE Controller EXI Configuration WA 92371AB EB MB PIIX4 E M USB Controller 1182371MB PIIX4M Power Management Controller p Lab koca Bar Lra Cutout E nbin Crystal C54281 SoundFusion PCI Audio Accelerator a U z 7 4 5 Unknown ae d fee l i dr I3C905C TX Fas
5. id Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software Note Additional configuration options can be accessed by right clicking on the instrument CH Series User Manual Page 38 A fr Volt Meter Volt Meter AC Bane Auto In to 10 00 Mode EEE Analog In Channel o E Device Number nm E or The Volt Meter is used to measure voltages on analog input channels AC Enable RMS AC signal measurement Range Voltage range of signal under test Selecting Auto will cause the volt meter to automatically determine the smallest range which encompasses the measured voltage thereby yielding the highest precision Mode Analog input type differential 2 wire single ended 1 wire or non referenced single ended 1 wire Coupling Analog input coupling and impedance A ACQUITEK W CH Series User Manual Page 39 Analog In Channel Zero based analog input channel number Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software A ACQUITEK y CH Series User Manual Page 40 Oscilloscope Dscilloscope Jime Base SEC DIV m Position 0 0 ak Pre Capture oniy Post
6. is only available when an Acquitek hardware device is selected in the System Tree Pane This page is used to test functionality of the selected device Select a device channel for analog IO or configure direction for digital IO then activate the panel by clicking its On button Correct installation and operation can be verified for all analog and digital channels CH Series User Manual Page 31 A ske Acquitek Bench Acquitek Bench File Edit Instrument Window Help About Acquitek Bench KIBS CQUITEK Acquitek Bench Version 1 4 3 0 Copyright c Exacq Technologies Inc 2003 2004 Acquitek Bench is a collection of tools that enables a PC equipped with an Acquitek data acquisition device to function as a DC voltage source a logic analyzer a digital multimeter an oscilloscope a spectrum analyzer a strip chart recorder and an arbitrary wave form generator CH Series User Manual Page 32 A ee Menu and Toolbar Acquitek Bench File Edit Instrument Window Help 9 The menu and toolbar are used to open and close the various instruments windows and arrange the display of those windows File Exit Close Acquitek Bench Edit Preferences Set application specific preferences View DC DC Source Open or close the DC Source window Logic Analyzer Open or close the Logic Analyzer window Meter Open or close the Meter window ES Oscilloscope Open or close the Oscilloscope window m Spectrum Analyzer Open o
7. name thermal noise The noise can also be from interference leaking into a signal from other circuitry In particular high speed digital circuitry is prone to corrupt analog signals Quantization is another type of noise imparted by the conversion between analog and digital signal In general it is good for the noise to be small Since noise is generally a random process it is best measured in terms of an RMS voltage Statistically the peak value of random noise is unlimited but the likelihood of such peaks is infinitesimally small The likelihood of a noise magnitude exceeding two times the RMS value is less than 5 CH Series User Manual Page 85 A i Nyquist Frequency Nyquist s Sampling Theorem states that an analog signal can be exactly reconstructed from a periodic sampling of that signal if the sampling rate is greater than twice the highest frequency contained in the analog signal Therefore the Nyquist Frequency is the sampling rate Fs 2 Any frequencies contained in the analog signal above the Nyquist Frequency will be aliased into the band 0 Fs 2 by the sampling process PGIA Programmable Gain instrumentation Amplifier An instrumentation amplifier in which the scaling coefficient which multiplies the difference between the input voltages to produce the output voltage can be changed via control signals In an instrumentation amplifier which is not programmable the scaling coefficient is typically set by a res
8. 1050 to B 1250 or to daisy chain B 1250 Available in Im and 2m lengths The complete line of breakout boxes and cables is as follows Breakout Boxes amp Connector Boards B 1050 B 1055 B 1250 B 1255 B 1350 B 1410 B 1420 Cables L 4201 L 4202 L 4211 L 4212 L 4221 L 4222 L 4230 L 4700 L 4801 L 4802 L 4861 L 4862 L 4891 L 4892 CH Series User Manual 37 pin breakout Breaks out digital I O for CH boards Requires L 4700 37 pin header and either L 480x cables or L 482x cables Same as above but without enclosure 4 to 1 RF multiplexer for use with CH boards Requires L 4700 37 pin header and either L 480x cables or L 482x cables Same as above but without enclosure Header bracket with screw terminals breaks out digital I O for CH boards Can be used instead of B 105x 37 pin breakout units Rackmount kit front panel and 2 empty hole covers use with any of the boxes above BNC termination panel for B 1410 Rackmount kit BNC 50 Ohm 1m BNC 50 Ohm 2m BNC 75 Ohm 1m Use with 75 Ohm CH boards BNC 75 Ohm 2m Use with 75 Ohm CH boards BNC to clip 1m BNC to clip 2m BNC to Scope Probe DB37 Bracket to Header Used in conjunction with L 480x cables or L 482x cables to connect B 105 37 pin breakout units and or B 125x RF multiplexers to CH and CM series boards DB37 Ext 1m Connects from DB37 connector on L 4700 to one B 105x 37 pin breakout unit or one B 125x RF multiplexer unit D
9. 1x 10x or 100x probe for scaling of display values Record Activate logging of data to disk File Name of data log text file Each line of the file contains a time offset value followed by a tab then the sample value and a carriage return Analog In Channel Zero based analog input channel number Samples Second Input sampling rate Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software Note Additional configuration options can be accessed by right clicking on the instrument CH Series User Manual Page 47 A fr Wave Form Generator Strip Chart ajaj Halal cw Range ROMER cy Range MET gt ar cronne s Mode ATTE gt Mode PAT gt I Disable strip plot scrolling Coupting EI Coupting ETS Probe Probe I Ignore buffer overwrite errors le Tx 10x 100x le Tx 10x 100x NIE Samples Second File gt File Device Number i Analog In Channel o B 22 Analog In Channel i EN The Waveform Generator is used to output analog waveforms including sine square triangle DC and arbitrary Wave Type Selects sine square triangle DC or arbitrary File waveform Amplitude Sets the amplitude of the generated waveform Offset Sets a DC offset for the generated waveform UITEK CH Series User Manual Page 48 A m d WF
10. 37148 EB MB PIlX4 E M USE ME 82371MB Pllx4M Power Manage ME Crystal CS4281 SoundFusion PCI SE Unknown ME 3C905C TX Fast Etherlink for PC L S28 Inspiron 2100 Laptop Integrated N Rage P M Mobility AGP 2x SS Acquitek DAQ Board Demo ETE Software EBAcquitek FS Acquitek Enumerator FS Acquitek Control Center FS Acquitek Bench ow System 8 Windows NT 2000 xP TET hird party Ready The System Tree Pane displays a graphical representation of the hardware and software discovered during the last system scan This information can be updated by selecting View Refresh from the main menu There are separate branches on the tree representing Acquitek hardware devices system and third party hardware devices Acquitek software components OS software components and third party software components The leaves on the branches can be selected to display additional information in the Configuration Pane CH Series User Manual Page 27 A re Configuration Pane The Configuration Pane displays one or more tabbed pages with additional information about the hardware device or software module currently selected in the System Tree CH Series User Manual Page 28 avo Info Tab Acquitek Control Center File Edit View Help ejes BE Local System BE Hardware EE Acquitek EPOC PxI Acquitek DAQ Board Demo BE System EPCI Axl BE 82443BX ZX 440BX ZX CPU to F BE 92443BX 2 440BX ZX PCI to Al Ms 82371EB MB PIIX4E
11. 64MB option local capture memory shared with output memory 32 bit 33 MHz Bus Mastering Continuous full speed capture of 2 chan at 20MSps per chan 80 MB s to PC memory is supported CH 3160 0 CH 3150 2 synchronous 50 Ohm 75 Ohm available DC 7th Order Butterworth 8 MHz 3 dB Frequency 12 Bits 50mV 100mV 200mV 500mV 1V 2V 5V Software Selectable 0 1 dB relative to full scale at 100kHz 0 1 of range 1mV at DC lt 1 LSB monotonic 1 LSB 72 dB 500 kHz output 1 Vpp range 55 dB 1Vpp range Any Ain Channel Ext S W Dig I O 4V 256 Steps or 4V 100k Ohm Zin 50 ns min Pulse width 1Hz 20MHz 1Hz resolution dual channel Up to 40 MHz single channel Software Selectable Independent from input clk Must be gt 4x sample rate 100k Ohm Zin 80 MHz max A ACQUITEK y Page 66 Memory Operating Modes Sync Output Digital I O Number of I O Input High Input Low Output High Output Low Power Up State Counter Timers Number Clock Speed Modes Physical Environmental Dimensions Power Consumption Operating Temperature Storage Temperature Connectors CH Series User Manual up to 16 MB 64 MB option local waveform memory Arbitrary Waveform with Automatic looping Function sine square triangle Software enabled TTL compatible 50 Ohm Zout 1 sample duration at segment boundary 16 two 8 bit ports Each port select
12. Acquitek CH Series High Speed Data Acquisition Boards for PCI Bus User Manual September 2006 Information in this document is subject to change without notice O Copyright 2006 Acquitek SAS All rights reserved ACQUITEK WW Acquitek is a trademark of Acquitek SAS Other trademarks and trade names may be used in this document to refer to either the entities claiming the marks and names or their products Acquitek disclaims any proprietary interest in trademarks and trade names other than its own Acquitek makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Acquitek shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing performance or use of this manual Acquitek SAS 1 bis rue Marcel Paul 91300 Massy France Acquitek CH Series High Speed Data Acquisition Boards for PCI Bus TABLE OF CONTENTS _ _ _ ASS 5 Feature A O NO 6 CH Series ad ET 7 _ _ _ _ _ ARSS A 8 CH Series Installation 0 A UA A AE NATE 8 3 HARDWARE ASS 10 TOU DAE E 1 AT E AA E A A E a 12 Output Architecture rmrrrvnnnnvrnnnvrnnnvvnnnvenanvenonvenn nnn ken Enn verst nerven vern nennn EEEN vern ANEREN 15 10 EEE ER 17 Auxiliary CONTECUONS orrainn AAA AAA A Ss 18 Data EEE EEE a a 23 4 ACQUITEK CONTROL CENTER ASS 25 Menu and Toolbar Sv 26 System
13. B37 Ext 2m Connects from DB37 connector on L 4700 to one B 105x 37 pin breakout unit or one B 125x RF multiplexer unit DB37 to DB9 1m Connects from DB37 connector on L 4700 to one B 125x multiplexer DB37 to DB9 2m Connects from DB37 connector on L 4700 to one B 125x multiplexer DB9 to DB9 1m Connects from DB9 connector on B 105x breakout unit to one B 125x multiplexer or to daisy chain between two B 125x multiplexers DB9 to DB9 2m Connects from DB9 connector on B 105x breakout unit to one B 125x multiplexer or to daisy chain between two B 125x multiplexers Page 82 A nang Glossary Aliasing The term used to describe the observed effect of sampling an analog signal at a sampling frequency less than two times the highest frequency content of the signal Signal processing theory specifically Nyquist s Theorem states that an analog signal can be exactly reconstructed from a periodic sampling of that signal if the sampling rate is greater than twice the highest frequency contained in the analog signal With the exception of some specialized undersampling applications it is important to prevent aliasing before 1t happens through the use of high sampling rates and or anti aliasing filters Once a signal has been corrupted by aliasing it can no longer be exactly reconstructed from its samples Anti Aliasing filter A filter with a frequency cutoff below one half the sampling rate It is used to prevent aliasing during the sampling of a
14. Bandwidth Resolution Full Scale Input Range Absolute Max Common Mode Range CMRR Gain Accuracy Zero Accuracy DNL INL SNR SFDR Triggering Source Levels Slope External Sample Rate Internal Clock CH Series User Manual CH 3150 CH 3160 4 synchronous 1M Ohm or 50 Ohm 75 Ohm available Software Selectable AC or DC Software Selectable 70 MHz 3 dB 12 Bits 50mV 100mV 200mV 500mV 1V 2V 5V Software Selectable 12 V 35 V 46 dB at DC 0 1 dB relative to full scale at 100kHz 0 1 of range 1mV at DC lt I LSB monotonic lt 4LSB 64 dB 500 kHz input 1Vpp range 60 dB 1Vpp range 2 synchronous Any Ain Channel Ext S W Dig I O 4V 256 Steps or 4V 100k Ohm Zin 50 ns min Pulse width 10kHz 10MHz 1Hz resolution quad channel 10kHz 20MHz 1Hz resolution dual channel 10kHz 40MHz 1Hz resolution single channel Software Selectable Independent from output clk ACQUITEK Page 65 Ai External Clock Memory PCI Interface Analog Outputs Number of Outputs Impedance Coupling Analog Filters Resolution Full Scale Output Range into matched load Gain Accuracy Zero Accuracy DNL INL SNR SFDR Triggering Source Ext Level Ext Slope Ext Input Sample Rate Internal Clock External Clock CH Series User Manual Must be gt 4x sample rate 100k Ohm Zin 80 MHz max 16 MB
15. Capture ODIV BEI Channels R lt Source Auto S ja CH2 DC Volts DIV Y Visible CHI Mode DEME 22 mode DEAT cannes Coupling IS Coupling IS Probe Probe e 1x 10x 100x 1x 10x 100x Analog In Channel o B won Analog In Channel i E On Ref Line Device Number mn E The Oscilloscope is used to provide a two dimensional visual display of an analog signal Most commonly it is used to show signal amplitude versus time displaying the waveform of the signal being monitored SEC DIV Specify the number of seconds per division on the Horizontal Axis Display Position Time Base Specify the vertical offset of the entire channel in percent of the Display K CH Series User Manual Page 41 A dd Pre Capture Specify how much data to capture before the beginning of the display The value is specified in divisions of the horizontal axis Post Capture Specify how much data to capture after the end of the display The value is specified in divisions of the horizontal axis Level Specify the level where the trigger mechanism will trigger a new frame to be displayed Source Specify the channel index used as the data source by the Trigger Slope Specify whether a positive or negative slope is used when triggering Auto Specify whether the Trigger is Automatic or Manual If this value is FALSE then you must manually evaluate the Trigger by pressing the trigger bu
16. File When File wavetype is chosen selects the file containing waveform data Each line of the file should contain a time offset value followed by a tab then the sample value and a carriage return Analog Out Channel Zero based analog output channel number Frequency Output cycles per second Waveform files are assumed to be 1024 points per cycle Range Waveform amplitude min and max values Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software ACQUITEK CH Series User Manual Page 49 A Third Party Drivers LabVIEW The Acquitek Data Acquisition LabVIEW VIs provides a LabVIEW interface for all calls available through the Acquitek Data Acquisition API The names and parameters are identical to those exported by XDADAQ DLL CH Series User Manual Page 50 A l L e Cheek Fa ots leave Pee f IS 183 Check Copy Raw Volts ix ex en ES esi Start Stop If the installation application was able to locate a LabVIEW installation on your computer the Acquitek VIs have been installed into the LabVIEW directory and can be accessed from the LabVIEW function palette by choosing the Acquitek Data Acquisition palette view If a LabVIEW installation was not detected manual installation can be completed by copying the XDADaqLV and Menus di
17. Freq and period countReg clockFreq being generated while gate is active Mode 3 Square Wave Generator Out is high Gate high enables down counting When count reaches count 2 out goes low When count expires out goes high Count is reloaded and down counting continues This results in a square wave of approximately 50 duty cycle and period countReg clockFreq being generated while gate is active Mode 5 Retriggerable Strobe Out is high Rising edge on gate triggers down counting to start Out stays high until count expires at which point out goes low for one clock then high again CH Series User Manual Page 20 A ad Digital 1 O via L 4700 Cable With the optional L 4700 cable the Digital 1 Os are brought out to a DB 37 female connector as a header in a PCI slot pinout B 1250 SD 37 5V Fused 0 75A 36 Gnd 35 Gnd 34 Gnd 33 Gnd 32 Gnd 31 Gnd 30 Gnd 29 Gnd 28 Gnd 27 Gnd 26 Gnd 25 Gnd 24 Gnd 23 Gnd 22 Gnd 21 Gnd 20 CH Series User Manual The L 4700 connector has the following 19 B 1250 CS 18 B 1250 SC 17 Digl O 15 16 Digl O 14 15 Digl O 13 14 Digl O 12 13 Digl O 11 12 Digl O 10 11 Digl O 9 Cntr1 Out 10 Digl O 8 CntrO Out 9 5V Fused 0 75A 8 Digl O 7 7 Digl O 6 6 Digl O 5 5 Digl O 4 4 Digl O 3 3 Digl O 2 2 Digl O 1 Cntr1 Gate D jes igl O O CntrO Gate Figure 3 7 DI O DB 37 Pag
18. H Series PXI Implementation section of the manual The Ain and External triggers support rising or falling edge triggering There is also a hardware noise reject filter which requires the trigger to exceed the threshold for approximately one half microsecond before signaling the trigger event This mechanism will introduce a delay in the trigger point of approximately one half microsecond which may be an appreciable number of samples at high sample rates Digital triggering supports either a pattern match mode where all of the enabled digital trigger bits up to 16 must match a predefined pattern or edge mode where a selectable rising or falling edge on any of the enabled digital trigger bits generates a trigger Trigger sources are selected by software See the Acquitek Data Acquisition SDK manual documentation for the set trigger functions It should be noted that in addition to triggering an input capture outputs can also be triggered from the above sources 1 e analog output triggered by an analog input signal crossing a threshold Not all possible combinations of functionality are possible For example the external clock and external trigger share a connector and circuitry so it is not possible to use both simultaneously CH Series User Manual Page 17 A Auxiliary Connections Auxiliary BNC Connector An auxiliary BNC connector is available for several functions Only one of these functions is operable at any time Software can sel
19. H board are assigned a unique configuration ID This step automatically stores the configuration ID in the B 1250 non volatile memory Test the connection by switching the mux position with the Channel radio button Exit the B1250Cfg application CH Series User Manual Page 78 A iii B 1250 Specifications DC Parameters Maximum UO Voltage Maximum T O current On resistance Termination resistance AC Parameters Insertion loss Gain Flatness Off Isolation Physical Switching time Switch cycles Power consumption Size Connectors CH Series User Manual 30 V max 0 5 A max 100 mOhms 50 Ohms 1 Contact factory for 75 Ohm version lt 0 05 dB at I MHz lt 0 1 dB DC to 10 MHz gt 55 dB at 10 MHz 10 ms max 300 000 operations while meeting full electrical specs 1 000 000 operations mechanical lifetime 20 mA at 5V No terminals enabled 70 mA at 5V One terminal enabled 7 2x 5 528 x 1 52 inches in box with connectors 183 x 141 x 39 mm 7 2 x 5 28 x 0 58 inches board only with connectors 183 x 134 x 15 mm 4 BNC bi directional multiplexed terminals 1 BNC bi directional common terminal DB 9 for power and control input DB 9 for power and control daisy chaining A ACQUITEK Page 79 y Cables 8 Connectors Optional Acquitek offer a wide array of breakout boxes connector panels cables and cable assemblies to assist in making analog and digital I O connections to the CH Series boards Ava
20. IO lines SEC DIV Specify the number of seconds per division on the Horizontal Axis Display Position Time Base Specify the vertical offset of the entire channel in percent of the Display Pre Capture Specify how much data to capture before the beginning of the display The value is specified in divisions of the horizontal axis A ACQUITEK CH Series User Manual Page 36 WwW Post Capture Specify how much data to capture after the end of the display The value is specified in divisions of the horizontal axis Level Specify the level where the trigger mechanism will trigger a new frame to be displayed Source Specify the channel index used as the data source by the Trigger Slope Specify whether a positive or negative slope is used when triggering Auto Specify whether the Trigger is Automatic or Manual If this value is FALSE then you must manually evaluate the Trigger by pressing the trigger button in the Trigger section of the Scope Panel Volts DIV Specify the number of volts per division on the vertical axis display Position Channel Specify the vertical offset of the entire channel in Percent of the Display Coupling Specify the signal coupling of this channel Visible Specify whether the channel trace line is visible Digital In Lines Digital inputs which will be sampled and displayed Only the first 8 DIOs can currently be used Samples Second Input sampling rate CH Series User Manual Page 37 A
21. Tree LE 27 Configuration Pall ooniicniicncinionicconnccncc rn 28 mo Tab 29 CONTIGUA EE EEE 30 bale ib 31 _ SSA 32 Menu and AJ EN 33 BES ERE 35 LOGIG A AA A E E A E O RR O 36 VOM A isn ean 39 OSCINOSCOPE E E E A A mm 41 OPOCIUIM ANALY ZO Piti A A AA AAA 44 Sip Chan OOE iii R aa ara n Tar 46 Wave Form EEE EA 48 T RSS 50 LaOVIEW ia ya A A Ai tia 50 MATLAB ii oi 52 Fr e AP NN 54 ExcelDA Microsoft Excel AdOd Jn seene 56 PASYLAD ARA OEA O vets cise ats ates ee eee 61 A ACQUITEK CH Series User Manual Page 3 WwW IS eee 65 8 B 1350 CONNECTOR BOARD OPTIONAL sss ss sss sse 68 9 B 1250 1255 RF MULTIPLEXER OPTIONAL ocococococconococcccoconononononnnnnnno 72 Eeee lei TTT 72 CONNGCHON TTT 73 Ora T 77 IC OMMGUIAUON ito 77 10 CABLES amp CONNECTORS OPTIONAL ss ss sees essen eee 80 1 GC OSSA EN i n 83 _ xxo o o o SSA 88 ACQUITEK CH Series User Manual Page 4 A Introduction The Acquitek CH Series of High Speed Data Acquisition Boards was designed to provide superior high speed functionality and performance at a low price All CH Series Boards utilize 16 MB of onboard memory a local processor and PCI bus mastering to provide glitch free capture and or playback of analog signals of length limited only by host RAM size even with a non realtime PC operating system With multiple simultaneous inputs dual simultaneous outputs and excellent dynamic specifications the CH Series boards are idea
22. able as input or output 2 0 V 5 V max 0 8 V 0 V min 2 4 V min O 24 mA 0 4 V max O 24 mA Input High Impedance 2 24 bits Internal from A D or D A clk 80 MHz Max 8254 modes 1 2 3 5 7 15 in x 4 20 in 182 mm x 107 mm 1 75A at 5V 0 5A at 12V 0 C to 55 C 20 C to 70 C 5 BNC Female CH 3130 40 50 2 In 2 Out 1 Ext trig clk sync out CH 3160 4 In 1 Ext trig clk 40 Pin Header digital I O 32 Bit PCI Page 67 A B 1350 Connector Board Optional The Acquitek B 1350 is an easy to use accessory which simplifies user connection to the sixteen digital input output DI O pins on the CH Series PCI data acquisition boards The B 1350 plugs into an empty expansion slot in a computer chassis It makes no connection to the slot connector so the slot can be either PCI or an ISA The included 40 conductor ribbon cable connects from the CH board to the B 1350 via 40 pin 0 100 spaced headers The B 1350 has multiple headers for use with a variety of Acquitek boards when using with a CH Series board connect to the header labeled CH DI O as shown in Figure 1 below The conductor labeled as Pin 1 on the ribbon cable usually marked in red should be connected to Pin 1 of the header marked with a large dot on the B 1350 board This same conductor should be connected to Pin 1 of the DI O header on the CH Series board shown in Figure 2 below CH Series User Manual ACQUITEK Page 68 A Screw Terminal Pl
23. air The absolute voltage between either signal and ground should not affect the differential measurement In practice voltages between the differential signals and ground can distort the differential measurement Common mode rejection ratio CMRR is a measure of how much the voltage between the differential pair and ground distorts the differential measurement The common mode range defines how large the voltage between either signal and ground can be before the differential inputs no longer function D A Digital to analog converter A component which produces an analog output signal which is proportional to a digital input value Typically a D A will hold the same analog output voltage for a period of time called the sample time and be updated periodically with digital input values at a rate called the sample frequency dB A decibel or dB is 10 logl10 power ratio between to signals Since power is proportional to voltage squared when dealing with voltages a dB is 20 log10 voltage ratio dBfs dB relative to a full scale A D or D A signal dBV dB relative to one Volt dBm dB relative to one milliWatt dBmV dB relative to one milli Volt Differential Input An input through which the difference of two signals at the positive and negative inputs is measured rather than the difference between a signal and system ground There is a limit to how far the two signals can be from the system ground before the input is no long
24. anual Page 75 A re Control Out Control In 00008 4 COM Aino Aint B 1250 ID 0 CH 3150 Aoutd CH 3151 Aout1 A L 420x L 421x Notes X denotes length in meters CH 3151 is 75 Ohm version L 421x 75 Ohm coaxial cables recommended with CH 3151 Figure 9 5 B 1250 Connection to CH with B 1050 DIO Breakout Aino CH 3150 AoutO CH 31 51 Aout1 L 420x L 421x Notes B 1250 ID 1 X denotes length in meters L 420x CH 3151 is 75 Ohm version L 421 x L 421x 75 Ohm coaxial cables recommended with CH 3151 Figure 9 6 B 1250 Connection to CH without B 1050 DIO Breakout K CH Series User Manual Page 76 A Operation The mux position can be set via software command from the Acquitek Data Acquisition SDK See the Acquitek Data Acquisition SDK manual for details of the software commands A visible LED indicates a currently active BNC connector Because the switching elements are mechanical relays designed for low loss switching of RF signals no calibration data is required to be read from or stored in the B 1250 Also due to the mechanical nature of the switching the switching time and switch lifetime specifications should be considered as a part of the system integration of the B 1250 Configuration Before using multiple B 1250s in a system a configuration step must be performed All B 1250s are shipped with a factory default configuration ID of 0 Up to ei
25. ata acquisition hardware CH Series User Manual Page 84 A ad Floating Source A voltage source in which the voltage at the positive or negative terminal is referenced only to the other terminal not to an absolute reference or ground Batteries and thermocouples are common floating sources Gibbs Phenomena Signals with sharp edges in their time domain response such as square waves require high frequency content in their frequency domain response to produce the rapid time domain changes If such a signal is passed through a low pass filter which removes the high frequency energy there may be substantial ringing at the time domain edges This is known as Gibbs Phenomena Careful design of the lowpass filter transition band can greatly reduce the amount of time domain ringing Harmonic distortion Typically expressed in dB this is the ratio of power at the fundamental signal frequency to the power at N times the fundamental frequency where N is an integer The largest distortion typically occurs at N equal two or three Non linearities in components through which a signal passes change the characteristics of the signal Typically these changes are best observed in the frequency domain through the use of tools such as the Fast Fourier Transform FFT Harmonic distortion results in energy in a signal being increased at integer multiples of the fundamental frequency of the input signal Instrumentation Amplifier A electrical
26. circuit with two inputs and one output An ideal instrumentation amplifier presents no load to the two inputs and the output voltage with respect to ground is proportional to the difference between the two input voltages In practice an input bias current must flow through the instrumentation amplifier inputs The input bias current is a measure of the extent to which the instrumentation amplifier will disturb the inputs to be measured with a smaller bias current causing less disturbance A practical instrumentation amplifier will also have an offset voltage which is present at the output when the difference between the inputs is zero Calibration of this offset voltage along with external nulling circuitry can eliminate this offset prior to analog to digital conversion Multiplexer A device with several inputs and one output External controls cause the desired input to be connected to the output In a multifunction board the multiplexer can operate at high speed to allow many inputs to be measured with a single instrumentation amplifier and analog to digital converter Mux Multiplexer Noise Any undesired modification of a signal is called noise Unfortunately everything adds noise to a signal but some components or systems add more than others The noise can be thermal noise which is caused by the random motion of charge carriers in conductors or semiconductors This random motion increases as temperature increases hence the
27. e Ip cutaaperejDeno n M file 25 Jun 2003 10 46 AM CHI D ciororseDeno a N file 24 Jun 2003 05152 TR CM Using Toolbox Path Cache Type help toolbox_path_cache for mores To get started select MATLAB Help from the Help menu gt gt CloiseDemo Instialized Execq Technologies Board Pwasing for comection to external instrument Press key to go on lol Fle Edt View Insert Tools Window Help lIOSAS RA77 1220 5 B 8 CHNos seDexo Relative Power Spectnam dB o 8 E AStart Paused Press any key Acquitek currently provides access to its data acquisition API in MATLAB via MEX files These functions are contained in dll files in the Acquitek ThirdPary MATLABMEX directory Their help text documentation is contained in m files with filenames that correspond to the dll files To see this documentation type help XXX at the MATLAB prompt where XXX is the part of the filename before the dll extension such as XDA Ain Volts The functions can be called just as any M function is called For example to read a sequence of 5000 input voltages between 5V and 5V from analog input channels 0 and 1 of device 1 at 10000 Hz type the following at the MATLAB prompt chO ch1 XDA_Ain_Volts 1 0 1 5 0 5 0 10000 5000 A ACQUITEK CH Series User Manual Page 52 NIT The Acquitek ThirdPary MATLABMEX directory currently contains MEX files for analog input and output digital i
28. e 21 A ACQUITEK y Digital I O Header There is also an external peripheral bus which uses pins on the 40 pin DIO header This bus is only available to control Acquitek multiplexers via the Acquitek software toolkit Up to eight external muxes which can be used to mux the analog inputs or outputs can be connected at one time See Section 9 of this manual B 1250 1255 RF Multiplexer This DIO header has the following pinout Reserved 40 39 Reserved Reserved 38 37 B 1250 CS B 1250 SD 36 35 B 1250 SC 5V Fused 0 754 34 33 Digl O 15 Gnd 32 31 Digl O 14 Gnd 30 29 Digl O 13 Gnd 28 27 Digl O 12 Gnd 26 25 Digl O 11 Gnd 24 23 Digl O 10 Gnd 22 21 Digl O 9 Cntr1 Out Gnd 20 19 Digl O 8 CntrO Out Gnd 18 17 5V Fused 0 75A Gnd 16 15 Digl O 7 Gnd 14 13 Digl O 6 Gnd 12 11 Digl O 5 Gnd 10 9 Digl O 4 Gnd 8 7 Digl O 3 Gnd 6 5 Digl O 2 Gnd 4 3 Digl O 1 Cntr1 Gate Gnd 2 1 Digl O 0 CntrO Gate Figure 3 8 40 Pin Header ACQUITEK CH Series User Manual Page 22 A Data Flow The input data flow of the CH board is depicted in figure 3 9 The output data flow is depicted in figure 3 10 There are two performance features to note from these figures First when the input is set for triggered capture the A D converters are continually capturing data into the local SDRAM When an enabled trigger event occurs the local processor records the current sample n
29. e channel or when you wish to use the frequency specified by Sample Rate Range The maximum voltage of the input signal Valid values for this parameter depend on the particular hardware device being used Please see the hardware reference manual for a list of valid values CH Series User Manual Page 58 A oo Polarity Input signal polarity Bipolar or Unipolar Coupling Input signal coupling AC DC or DC Terminated Mode Input signal mode Differential Single Ended or Pseudo Differential Trigger Channel Analog channel used to trigger acquisition Trigger Level Voltage level at which data acquisition will trigger Trigger Type Trigger mode Falling Rising External or None To begin acquisition as soon as the Acquire toolbar button is clicked set this value to none Trigger Noise Reject Enable Trigger Noise Reject to avoid triggering on noise from the trigger input signal CH Series User Manual Page 59 A fr Acquisition Ed Microsoft Excel lol x Ele Edit view Insert Format Tools Data Window Help Acrobat JOSE S6RY sBOS o o Br A AMB ara rv B I HIS gt o Securty RA IMS Q mia BAe AAA x Configure l Acquire VY 8 configure 5 Once all data acquisition parameters have been set using the configuration dialog simply click the Acquire button on the Acquitek Data Acquisition toolbar to acquire data directly into your Excel spreadshe
30. e final output such as 0 1 0 01 or 1LSB CH Series User Manual Page 86 A i Single Ended Input An input whose voltage is measured with respect to system ground SNR Signal to noise ratio Typically expressed in dB this is the ratio of the desired signal power to the undesired noise power SFDR Spur free dynamic range Typically expressed in dB this is the ratio between the power in an input signal and the largest spurious signal either harmonically related to the input signal or not Successive Approximation An analog to digital converter architecture capable of high resolution conversion at moderate speed Unlike pipelined converters and sigma delta converters the input sampling rate does not need to be periodic and the start and end of a conversion are well defined making it the most suitable architecture for multiplexing inputs CH Series User Manual Page 87 A sie Technical Support Acquitek is committed to providing exceptional technical and engineering support When you need help with your Acquitek CH Series product please have the following information available e A complete description of the problem including any error messages or instructions on re creating the error e Your computer configuration including brand processor speed memory and other hardware installed e Description of what is connected to the CH Series boards e Operating System Environment Windows Linux etc e Information on t
31. ect one of these modes external analog trigger input D A waveform sync output external clock input for the analog I O channels or external clock output synchronous with the A D clock or D A clock The circuitry driving the auxiliary BNC connector is shown in figure 3 5 Output Enable D A Sync Pulse Int Mx D A Clk Int Nx A D Clk A D Clk D A Clk Ext Trig 100k Ohms Figure 3 5 Aux BNC Architecture In input modes the input is a high impedance input As can be seen from figure 3 5 the input signal first passes through a high speed comparator When set for external clock input the comparator threshold is set for 1V The input signal can be a square wave or sine wave bipolar or unipolar It should be limited to the range of 5V When set for external trigger input the comparator voltage is set to the external trigger level The external trigger level is limited to 4V CH Series User Manual Page 18 aor In output modes the signal is terminated in 50 Ohms and will drive a D A sync pulse or square wave clock at approximately 0 2 V into a 50 Ohm load or 0 4 V into a high impedance load The on board circuitry for both analog input and analog output is clocked at an integer multiple of the actual sample rate The external clock port on the board whether taking in or driving an external clock operates at the multiplied clock rate The actual integer multiple varies When using the internal clock the multiple is co
32. entire name including the xls extension if one is present Target Worksheet The worksheet to which data will be acquired This sheet must already be present in the specified workbook Target Column Starting Column for data acquisition Data for a single channel will be captured to the specified column Data for multiple channels will be captured to consecutive columns Target Row Starting row for data acquisition Samples for each channel will be captured in consecutive rows starting with the specified row CH Series User Manual Page 57 A re Analog In Configuration ExacqXL Settings x General Analog In Channel Count 1 Polarity Bipolar Sample Count 10 Coupling DC be Sample Rate Hz 10000 Mode Pseudo Diff Scan Rate Hz Trigger 0 5 Channel 0 E Level 2 5 Type Falling Range T Noise Reject Display the Analog In Configuration tab on the configuration dialog by clicking Configure on the Acquitek Data Acquisition toolbar then choosing the Analog In tab Channel Count The number of channels from which data will be acquired Sample Count The number of samples to acquire from each channel Note that Excel limits this value to about 65000 Sample Rate The sampling clock frequency to be used for the acquisition Scan Rate The time between channel sample sets when using hardware that does not support simultaneous sampling Set this value to 0 when acquiring on
33. er able to measure simply the difference between the two inputs but instead is distorted by the difference between the signals and ground This limit is called the common mode voltage range Elliptic Filter A type of filter which has excellent frequency domain cutoff properties but poor time domain distortion properties i e pulse response with excessive ringing This filter characteristic can be implemented in either the analog or digital domain FFT Fast Fourier Transform A mathematical tool for analyzing the frequency content of a signal FIFO First In First Out A temporary storage memory with no addressing in which data is stored and retrieved in first in first out order On a data acquisition board a FIFO is used to free the host processor from servicing the data acquisition hardware on a periodic interval Typically the hardware accesses one side of the FIFO at the periodic sample rate or a multiple of it The host accesses the other side of the FIFO to either fill it with data for output or read the input data The host can do so in burst mode which is much more efficient For example a burst transfer across the host PCI bus can reach nearly 132 Mbytes sec whereas non burst transfers are a small fraction of that rate With a non realtime operating system such as Windows it is important for the FIFO to hold enough data to sustain periodic data acquisition during intervals when the processor is not available to service the d
34. estPoint is installed e Edit the TestPoint ini file found in the TestPoint directory Replace the entire ADO section with this text ADO manufacturer AUTO MODE Bipolar TYPE Pseudo COUPLING DC DACOUPLING DC e Edit the TPAD ini file found in the TestPoint directory Find the ADDRIVERS32 section and add this line ACQUITEKWDM TPACQUITEK DLL The Acquitek data acquisition board assigned logical device number one using Acquitek Control Center can now be accessed in TestPoint as AD device zero To use multiple boards or change the logical device that will be used copy the board configuration information added for ADO into another section ADn The Acquitek device number will always be one greater than the TestPoint AD number Notes You must run Acquitek Control Center to assign logical device numbers to all Acquitek devices and verify basic functionality before using the devices with TestPoint The TestPoint driver will be copied to the AcquitekInstallDirectory ThirdParty TestPoint directory by Acquitek Setup You must complete the installation as documented above A sample TestPoint application called AD_DA tst is copied to AcquitekInstallDirectory NThirdPartyTestPointisamples by Setup This application can be used to verify basic functionality ACQUITEK CH Series User Manual Page 55 A ExcelDA Microsoft Excel Add In ExcelDA is a Microsoft Excel Add In that enables data acquisition from within Excel using any Acqu
35. et If you have specified a non existent target for acquisition or your configuration parameters are otherwise incorrect an error message will be displayed You can then click Configure again to display the configuration dialog and correct the problem CH Series User Manual Page 60 amp iii DASYLab DASYLab7 Net ain dsb Worksheet File Edit Modules NI DAQ Experiment View Options Window Help KIS Dj le Sor Ge tle ea oa jell Exa Saal Yit Chart00 Es PA ap 279 t AR Y t Chart00 Z SENKER Bla HEER 21 1 20 FB e 53 Ex DA le 23 va S K OF s BE EG EE A a A TE MM TE YA Chart 0 YA Chart 1 E OE 4184102 PM DASYLab is an easy to use Windows based graphical data acquisition software package with which you build data acquisition and control applications more quickly By using an icon based flowchart you develop your application with point and click ease no programming required Installing the Acquitek DASYLab Driver 1 Copy XDADASY dll from the installdir ThirdParty DAS YLab folder most likely C Program Files Acquitek ThirdParty DAS Y Lab to DASYLab s root folder most likely C Program Files DAS YLab CH Series User Manual Page 61 Ra 2 Open DASYLab 3 Choose Select Driver from the Experiment menu in DASYLab 4 Find XDADASY dll in this dialog box Highlight it and click OK If XDADASY dll does no
36. g up to 26 outputs from a CH 3150 as shown in figure 9 3 With a CH 3160 board up to 28 inputs can be muxed into the CH board as shown in figure 9 4 ACQUITEK CH Series User Manual Page 73 A B 1250 ID 0 00009 B 1250 ID 3 B 1250 ID 4 eae B 1250 ID 7 B 1250 ID 1 00009 OOOO 4 CO B 1250 ID 5 ee 00000 K 2 3 4 COM B 1250 ID 2 eine B 1250 ID 6 eee CH 3140 50 L Figure 9 2 CH 3140 50 Expansion to 26 Inputs Using Multiple B 1250 B 1250 ID 0 99999 B 1250 ID 3 B 1250 ID 4 eee B 1250 ID 1 00009 B 1250 ID 2 Mee B 1250 ID 6 me CH 3130 50 L Figure 9 3 CH 3130 50 Expansion to 26 Outputs Using Multiple B 1250 CH Series User Manual Page 74 A ACQUITEK NIT B 1250 ID 0 B 1250 ID 1 B 1250 ID 2 CH 3160 L B 1250 ID 3 B 1250 ID 4 B 1250 ID 5 B 1250 ID 6 B 1250 ID 7 Figure 9 4 CH 3160 Expansion to 28 Inputs Using Multiple B 1250 The control signals for the B 1250 are located on the 40 pin DIO header on the CH board Connection of the B 1250 to the CH board depends upon whether the B 1050 DIO breakout board will be used in the system Figures 9 5 and 9 6 illustrate the cables and connections required to use the B 1250 with and without the B 1050 digital I O breakout board The figures show a CH 3150 but the cable requirements are common to the entire CH board family CH Series User M
37. ght B 1250s can be controlled from a single Acquitek CH or XH board Each of the B 1250s controlled by the same board must have a unique configuration ID The configuration step entails a one time operation of connecting a single B 1250 to a CH or XH board and running a simple program to store the configuration ID in the B 1250 non volatile memory This program is called B1250Cfg exe and is included in the root directory of the Acquitek Data Acquisition Setup installation Acquitek Util directory Procedure NOTE Only a single B 1250 can be connected to the CH or XH board during the configuration step Connect a SINGLE B 1250 to the CH board as shown in either figure 9 4 or 9 5 depending upon whether a B 1050 DIO breakout board is used The cable MUST be connected to the DB 9 connector on the B 1250 labeled Control In Start the B1250Cfg application It should appear similar to the screen shot in figure 9 7 below ACQUITEK CH Series User Manual Page 77 Ai Exacq B 125x Configurator Iof x B 125x 1D Test not stored Ss y Channel gg y re 9 se c CH Device Number E a AS Using Exacq Device Number 1 Y Figure 9 7 B1250Cfg Main Screen Use the CH Device Number spin edit control to select the CH or XH board to which the B 1250 is connected Assign the configuration ID by selecting the appropriate B 1250 ID radio button Ensure that all B 1250s to be connected to the same CH or X
38. he compiler you are using if applicable e Sample code if applicable Technical support can be contacted as follows Acquitek SAS 1 bis Rue Marcel Paul 91300 Massy France Phone 33 1 60 13 52 73 Fax 33 1 60 13 03 68 e mail support acquitek com Web http www acquitek com Technical Support Hours Monday Friday 9 00 am 6 00 pm GMT 1 Saturday Sunday amp Holidays Closed ACQUITEK CH Series User Manual Page 88 Ai
39. he configuration and test of data acquisition products from Acquitek ECC is used to assign logical device numbers to Acquitek hardware devices so that those devices can be accessed from other software applications ECC can also be used to specify default configuration parameters for Acquitek hardware devices and to verify correct installation and operation of those devices CH Series User Manual Page 25 A i Menu and Toolbar Acquitek Control Center File Edit View Help ale File Load Profile Loads a previously saved set of configuration data making those settings active File Save Profile Save the current configuration settings for all Acquitek devices to a named file File Exit Exit Acquitek Control Center Edit Preferences Set general application preferences including whether to scan hardware and software each time Acquitek Control Center is started View Refresh Scan the system for installed hardware and software Help Contents View help for Acquitek Control Center Help Acquitek Web Site Open the Acquitek home page in a default browser window Help About Display version and copyright information for Acquitek Control Center ACQUITEK CH Series User Manual Page 26 A System Tree Pane ETE Hardware EE Acquitek EPC PXI SSR Acquitek DAA Board Demo ae System EPC PXI ME 82443BX ZX 440BX ZX CPU to F 92443BX ZX 440BX ZX PCI to Al 5192371EB MB PIIX4E M ISA Bride 923714B EB MB PlIX4 E M EID 5192
40. ilable connectivity options include B 1050 Breaks out digital I O channels for CH Series Requires L 4700 37 pin header and L 480x series cable B 1055 Same as above but without enclosure B 1250 Four to One RF multiplexer for CH Series Also available without enclosure B 1255 Requires L 4700 37 pin header and L 486x series cable or B 105x and L 489x series cable B 1410 B 1420 B 1410 is the Rackmount kit and termination panel for CH Series B 1420 is the BNC termination panel for the B 1410 CH Series User Manual ACQUITEK Page 80 Ai B 1350 PCI board providing easy screw terminal header access to the 16 Digital I O channels of the CH Series Can be used instead of B 1050 breakout unit L 4700 DB37 bracket to header connector Used in conjunction with L 480x series cables to connect B 105x digital I O breakout units and or B 125x RF multiplexers to CH Series board L 4801 L 4802 Connects from DB37 connector of L 4700 to B 105x Available in 1M L 4801 and 2M L 4802 lengths L 420x L 421x BNC to BNC cables available in 50 Ohm L 420x and 75 Ohm L 421x configurations and in 1m and 2m lengths L 422x BNC to clip cables available in Im and 2m lengths L 486x DB37 to DB9 Used to connect from L 4700 to B 1250 Available in Im and 2m lengths CH Series User Manual Page 81 A re L 489x DB9 to DB9 Used to connect from B
41. ing frequency Fs A reconstruction filter smoothes the D A output in the time domain or attenuates the undesired replicas of the output signal at higher order multiples of the D A sample rate A second effect of the zero order hold architecture of the D A is that within the desired signal range i e from 0 Hz up to Fs there is an amplitude rolloff proportional to sin T f Fs T f Fs This ratio is known as the sinc function and results from the rectangular stair step shape of the D A converter time domain output The sinc response causes the output of a D A converter to be attenuated by 3 9 dB at the Nyquist Frequency Fs 2 Some reconstruction filters will have sinc or sin x x compensation In this case the filter not only attenuates signals outside the 0 Fs 2 frequency band but also provides an inverse sinc amplitude response within the O Fs 2 band Referenced Source A voltage source in which not only the difference in voltage between the positive and negative terminal is defined but also the difference between either terminal s voltage and a reference voltage such as ground Settling Time The time taken for a system to respond to a transient event such as a voltage step when switching from one input to the next in a multiplexed data acquisition system Settling time is typically measured in microseconds from the transient input event until the measurement output is within some small tolerance of th
42. istor Pseudodifferential Input A differential input in which the negative input is intended as a voltage reference only not to carry signal information The negative input is isolated from the system ground and the pseudodifferential input is therefore useful for preventing ground loops In a multichannel system many pseudodifferential inputs may share the same reference input while it is common to the inputs it is still isolated from system ground Quantization noise Because of the limited number of bits available in a practical A D the digital output of the A D does not exactly represent the input analog voltage In an ideal A D the quantization noise is on average equal to the voltage represented by 1 2 of the least significant output bit Quantization noise can usually be effectively modeled as flat frequency spectrum between 0 and the sampling frequency i e the Nyquist Frequency Quantization noise improves by 6 dB for every bit in an A D Reconstruction filter Also known as a smoothing filter A D A converter typically operates by generating a voltage proportional to a digital value and holding that voltage constant for a time period equal to the l sample rate This operation known as a zero order hold has consequences in the frequency spectrum of the analog signal output from the D A converter Specifically the desired frequency spectrum of the D A output is replicated at every integer multiple of the D A sampl
43. itek hardware device It is included with all Acquitek products and installed into the ThirdParty directory when Acquitek Data Acquisition Setup is run Installation To Install ExcelDA follow these steps e Start Microsoft Excel e Choose Add Ins from the Excel Tools menu e Click the Browse button on the Add Ins dialog e Navigate to AcquitekInstallDirectory ThirdParty ExcelDA e Double click ExcelDA xla e Click the OK button on the Add Ins dialog e Choose ToolBars from the Excel View menu e Select Acquitek Data Acquisition from the ToolBars list Once you have completed these steps the Acquitek Data Acquisition toolbar will be available for use with any workbook within Excel You can drag and dock the toolbar to a convenient spot on the Excel toolbar or let it float within the work area as you prefer CH Series User Manual Page 56 A A General Configuration ExacqXL Settings x General Analog In Device Number 1 Target workbook Book1 Worksheet Sheet Column A Row 1 Display the General Configuration tab on the configuration dialog by clicking Configure on the Acquitek Data Acquisition toolbar then choosing the General tab Device Number Logical device number of the Acquitek hardware device that will be used for acquisition This number must be assigned in Acquitek Control Center Target Workbook The workbook to which data will be acquired You must provide the
44. l for communications applications such as IQ modulation and demodulation With 12 bit resolution high speed precision and flexible triggering options they are ideal for high speed control applications The onboard DSP coprocessor can offload intensive processing steps such as FFTs to free the host program for higher level algorithms and applications The outputs are full featured arbitrary waveform generators with both waveform playback capability and function generation mode and analog reconstruction filters on board The board is PCI Plug and Play and digitally calibrated so there are no jumpers or potentiometers to manually adjust CH Series User Manual Page 5 A i Features e Up to 4 input channels e Separate 40 MS s A D Converter per Channel e 12 Bit A D Resolution e Up to 16 MB Local Acquisition Memory e Analog Digital Software Triggering Modes e 1 Hz A D Sample Clock Resolution from onboard DDS e Up to 2 Output Channels with Arb Function Generation Modes e Up to 40 MS s D A Converter per Channel e 12 Bit D A Resolution e Analog Reconstruction Filtering e Up to 16 MB 64 MB optional Local Waveform Memory e 1 Hz D A Sample Clock Resolution from onboard DDS e 16 Digital I Os Synchronous with Analog I O e 2 Counter Timers e PCI Bus Mastering Transfers at gt 80 MB s sustained e Onboard 143 MHz 32 Bit DSP for Numerical Coprocessing e Windows 98 ME 2000 XP Linux Compatibility CH Series User Manual Page 6 A ii
45. lock which is 2x or 4x the D A clock depending upon whether one or two output channels are enabled The gate source is either from a software register or from an input pin shared with the digital I O The output goes to a software register and can be directed to an output pin shared with digital I O See the digital I O pinout drawings figures 3 7 3 8 for the specific pin information A ACQUITEK CH Series User Manual Page 19 WwW The Acquitek Data Acquisition SDK has documentation on the functions used for programming the counter timers Use the SDK functions for setting the Ain and Aout clock to set the CTO and CT1 frequencies respectively Note that the DIO port which contains the counter timer output pins must be set to output mode for the counter timer output to be driven on the pins The DIO port which contains the counter timer gate pins must be set to input mode for the gate signal to be read from the pins Count is up to 24 bits and is programmed with the number of clocks to be counted The operating modes are Mode I Retriggerable One Shot Out is high Rising edge on gate triggers out to go low and down counting to start Out stays low until count expires at which point out goes high Mode 2 Rate Generator Out is high Gate high enables down counting When count expires out goes low for one clock cycle then high again Count is reloaded and down counting continues This results in a sequence of negative pulses of width 1 clock
46. mpletely handled by the Acquitek driver software transparently to the user In external mode it can not be completely transparent Typically the analog output clock runs at 4 times the sample rate in single channel mode or 2 times the sample rate in dual channel mode The analog input clock typically runs at a high frequency and the divide ratio is increased as the desired sample rate is decreased In all cases 80 MHz is the maximum frequency of the external clock Refer to the Acquitek Data Acquisition SDK manual for details on setting the frequency when using external clock modes Note that the signals on the CH board auxiliary BNC are high speed and should be treated as such Typically 50 Ohm coaxial cable should be used to connect the output of the auxiliary BNC to its load If it is being connected to another board or boards auxiliary BNC input which is high impedance BNC T connectors should be used and the cable should be terminated in 50 Ohms after connection to the last auxiliary BNC in the chain Counter Timers The CH board has two hardware based counter timers These counter timers are based upon the 8254 functionality and take in a clock and gate signal and generate an output signal On the CH board the clock sources are fixed CTO takes its clock from the analog input sample clock i e not the integer multiple of sample clock as described in the auxiliary BNC section while CT1 takes its clock from the analog output c
47. n analog input signal of 10 Vpp Following the variable gain stage is a buffer amplifier which drives the A D Note that there is no anti aliasing filter preceding the A D This gives the user maximum flexibility with the signal input There is a single pole noise limiting filter with a cutoff frequency of approximately 70 MHz just preceding the A D With that exception there is no restriction on exceeding the Nyquist bandwidth at the selected sampling rate The rest of the signal chain will operate up to 90 MHz although harmonic distortion will be increased at higher input frequencies The A D converter is 12 bits The A D data format is two s complement as the CH family always operates in bipolar signal mode In addition to the analog inputs there are sixteen digital input output DIO pins which can be sampled The DIO s must be set as input or output The pins are divided into two 8 bit ports All pins in each port must be set for the same direction If a port is set as an output the output state will be returned when the port is read The DIO port can be sampled in two ways A simple single reading mode which is asynchronous with the A D clock is useful for signals which are not expected to change quickly A clocked mode in which the DIO s are sampled synchronously with the analog inputs and the data is streamed to host memory is also available Due to data rate limitations this mode is not available when the sample clock is over 10 MH
48. n analog signal A D Analog to digital converter A component which produces a digital representation of the voltage of an input analog signal at an instant in time called the sample time Typically an A D will sample an input signal periodically at a rate called the sample frequency Bessel filter A type of filter which has excellent time domain distortion properties i e pulse response with very little ringing but poor frequency domain cutoff properties This filter characteristic can be implemented in either the analog or digital domain Butterworth filter A type of filter which has a good compromise between frequency domain cutoff properties and time domain distortion such as ringing This filter characteristic can be implemented in either the analog or digital domain Charge Injection An undesirable property of a multiplexer in which a small amount of electrical charge is injected into the selected multiplexer input when the multiplexer switches A voltage error is introduced which is equal to the injected charge divided by the input capacitance The voltage error decays over time as a function of the source resistance Lower source resistance results in faster decay of the voltage error CMRR Common Mode Rejection Ratio See common mode range CH Series User Manual Page 83 A ed Common Mode Range With a differential voltage the relevant measurement is the difference in voltage between the two signals in the p
49. nput and output and counter timer functions The analog input functions can be found in the following files XDA_Ain_Coupling dll XDA Ain Raw dll XDA Ain Volts dll Analog output functions can be found in the following files XDA Aout Func dil XDA Aout Raw dll XDA Aout Volts dll Digital input and output functions can be found in the following files XDA Din Read dil XDA_Dout_Write dll Counter timer functions can be found in the following files XDA_CT_Config dll XDA_CT_Gate dll XDA_CT_Read dll Example M functions that use these MEX files can be found in the Acquitek ThirdPary MATLABMEX Samples directory ACQUITEK CH Series User Manual Page 53 AG TestPoint Capital Equipment Corporation s TestPoint is software for designing test measurement and data acquisition applications The Acquitek TestPoint driver enables the use of all Acquitek hardware with TestPoint to simplify data acquisition ioi xi File Edit View Utilities Mode Run Debug Window Help D Interactive A D testing App 1 AD_DA TST EE S Interactive A D testing MOS amp R Z 5 amp E This program Graphi Rate Hz V r delta t points E Channels SZ Acquire amp Graph ed Set A D board modes P Modes E Sample once L Single value Foc ow D A D A1 CH Series User Manual Page 54 A Installation e Copy the file TPAcquitek dll from AcquitekInstall Directory ThirdParty TestPoint to the directory where T
50. nsmission medium such as twisted pair wire a differential input will also reject noise picked up on the transmission medium due to the symmetry of the noise between both differential inputs However with the coax connection typical for the CH input noise will couple onto the coax shield not the center conductor and therefore the differential input may increase the amount of noise picked up on the transmission medium If ground loops are not an issue in the CH application and excessive noise is being picked up on the coax please contact the factory A switchable termination resistor can be enabled to terminate the input 50 Ohms is the nominal termination impedance 75 Ohm termination for video applications is available Please contact the factory for this option CH Series User Manual Page 13 aor An AC coupling capacitor can also be switched in line The AC coupling can block up to 25 VDC However be extremely careful when measuring such signals with large DC offsets If the AC coupling capacitor is switched out when connected to a signal with a large DC offset the large voltage could damage the CH input circuitry Signals larger than the 12V from the board ground are potentially damaging to the CH board A variable gain stage follows the input instrumentation amplifier This stage provides sufficient low noise gain to allow a full scale A D input from an analog input signal of 100 mVpp and attenuation to allow full scale A D input from a
51. oltage range of signal under test Mode Analog input type differential 2 wire single ended 1 wire or non referenced single ended 1 wire Coupling Analog input coupling and impedance K CH Series User Manual Page 44 A dd Analog In Channel Zero based analog input channel number Samples Second Input sampling rate Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software ACQUITEK CH Series User Manual Page 45 A Strip Chart Recorder Acquitek Bench File Edit Instrument Window Help Strip Chart ala alas cH Range MOMENT gt cyz nans BONN gt as channeis Mode PEE Mode ECCS Coupling LS Coupling LS Probe Probe Ignore buffer overwrite errors Disable strip plot scrolling 1x 10x C 100x fo ix 10x 100x Samples Second A MESEN lt File E File Ml Device Number mn E Analog In Channel o E Analog In Channel 0 E one The Strip Chart Recorder is used to capture and save voltage levels from the analog input channels Range Voltage range of signal under test Mode Analog input type differential 2 wire single ended 1 wire or non referenced single ended 1 wire Coupling Analog input coupling and impedance A ACQUITEK WwW CH Series User Manual Page 46 Probe Specifies a
52. r close the Spectrum Analyzer window CH Series User Manual Page 33 A i Strip Chart Open or close the Strip Chart window Waveform Generator Open or close the Waveform Generator window Window Cascade Cascade all open child windows Tile Tile all open child windows Minimize All Minimize all open child windows Close Close the currently selected child window Help Contents Display help contents Acquitek Web Site Launch the default browser and direct to www Acquitek com About Display version and copyright information ACQUITEK CH Series User Manual Page 34 A DC Source Analog Out Channel o E Device Number i E The DC Source is used to output a constant voltage on an analog output channel Analog Out Channel Zero based analog output channel number Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software CH Series User Manual Page 35 A A Logic Analyzer Logic Analyzer Time Base SEC DI Position Trigger Source META gt Pre Capture Auto El Mi Post Capture Channels voltszDIV PEN Position 440 Eu Coupling oca Y Visible Ref Line oo Device Number 0 B Digital in Lines Samples Second The Logic Analyzer is used to capture and inspect logic level OV 5V signals using the digital
53. rectories from the installdir ThirdParty LabVIEW directory into the main LabVIEW installation directory the directory containing LabVIEW exe A number of sample VIs are included and can be found in the installdir ThirdParty LabVIEW Samples directory These samples demonstrate wiring of the API level VIs and can also be used as higher level building blocks within new LabVIEW applications The first time you attempt to open one of the samples from the _ installdir ThirdParty LabVIEW Samples subdirectory LabVIEW will not be able to find the XDADaqLV VIs used by the sample You can either browse to the correct LabVIEW_Install XDADagLV directory using the find vi dialog displayed by LabVIEW while loading the sample or you can permanently fix the problem for all samples by opening the LabVIEW Tools Options menu selecting Paths and VI Search Path then entering LabVIEW Install XDADaqLV and clicking Insert Before Note LabVIEW Install should be replaced by the actual name of the directory where LabVIEW is installed on your system Also note that the V after XDADaqLV is needed so that LabVIEW will search the subdirectories under XDADaqLV A ACQUITEK CH Series User Manual Page 51 NIT MATLAB lol Fle Edt View Web Window H EN DF R 0 amp Current Directory D Frog am Fier xaca TtwdParty MA TLABMEXGangles zj fri vrrogran Files Exacq ThirdParty MATLA y J Oa A11 Files Fite Type Last moditied D
54. root directory of the CD Follow the onscreen instructions to install the application and driver software It is recommended that you leave installation options unchanged to perform a full installation of all software components After the installation completes remove the CD and reboot your computer Configure the Data Acquisition Hardware Run Acquitek Control Center from the Acquitek program group on the Windows Start menu The new data acquisition device should appear as a node in the Local System Hardware Acquitek PCI PXI branch of the System tree Click on the node The serial number and logical device number will display in the Configuration pane The logical device number is the tag that all application software uses to specify which hardware device will be used To change the assigned device number click on the configuration tab and select a new number using the device number edit control Click the save button to make the change permanent Test the Data Acquisition Hardware If Acquitek Control Center is not still running re run the application from the Acquitek program group on the Windows Start menu and select the System tree node for the data acquisition device Select the Test tab in the Configuration pane The displayed test panels can be used to test all analog input channels and analog output channels as well as the digital IO lines Connecting an analog output to an analog input then turning on both panels can be u
55. ry and streamed to the D A converters from there As the waveform repeats the D A waveform sync can be driven out the auxiliary BNC connector This frees the entire PCI bandwidth to support the 80 MByte sec stream from the analog input channels This mechanism is typical because a deterministic repetitive output waveform is often sufficient to stimulate a test or measurement setup while it is often desired to capture large amounts of input data for analysis With the described implementation a waveform stimulus of up to 8 million samples can be stored in the onboard memory and input samples captured up to the amount of free RAM in the host computer system ACQUITEK CH Series User Manual Page 24 AG Acquitek Control Center Acquitek Control Center EEK File Edit View Help BE Acquitek BEPC PXI W Acquitek DAQ Board Demo BE System OPCI PXI w 92443BX 2X 440BX ZX CPU to F 0 824438 X ZX 4408 X ZX PCI to Al 818237 1EB MB PIIX4E M ISA Bride 219237148 EB MB PIIX4 E M EID 82192371AB EB MB PIIX4 E M USE w982371MB PIIX4M Power Manage Crystal CS4281 SoundFusion PCI CQ U I I EK Unknown SN 3C905C TX Fast Etherlink for PC L 5 Inspiron 2100 Laptop Integrated N Rage P M Mobility AGP 2x E3 Acquitek DAQ Board Demo ows oftware EME Acquitek FS Acquitek Enumerator FS Acquitek Control Center Bl Acquitek Bench ie System 18 Windows NT 2000 XP Third party Acquitek Control Center ECC provides a central location for t
56. s outputs triggering and to implement algorithm acceleration and real time execution The CH 3150 board is shown in figure 3 la with the major sections and connectors identified A CH 3150 1 is fully populated with two inputs and two outputs The CH 3160 board is shown in figure 3 1b A CH 3160 1 features four inputs and no outputs The control hardware onboard processor memory and software interface are identical for the entire family of CH boards 175 Ohms on CH 3131 41 51 61 boards CH Series User Manual Page 10 aor A Ge Pin 1 Aino I DIO Header A ss A 8 Aux gt C DSP SDRAM Interface Aoun C Aino gt C DIO Header Aint gt C Analog Input Section DSP PCI Interface Figure 3 1b CH 3160 Board There are no manual adjustments or switches on the CH board Calibration is performed at the factory and the calibration settings are stored in an on board EEPROM The calibration settings are used to set digital gain and offset trimming potentiometers Therefore the calibration is performed in the analog domain preserving the full dynamic range of the A D and D A converters and eliminating any processing overhead for software calibration CH Series User Manual Page 11 A Input Architecture Two identical analog input chains drive a two channel 12 bit analog to digital converter A D on CH boards equipped with analog inputs There is one clock for the A D ensuring that bo
57. sed as a quick check to verify basic operation Run Application Software Installation and configuration of the Acquitek data acquisition hardware and software is now complete Y 0u can run the included Acquitek Bench application software to use the device in a wide range of test and measurement tasks Remember that all application software will refer to the data acquisition hardware using the logical number assigned by Acquitek Control Center A ACQUITEK CH Series User Manual Page 9 WwW Hardware Overview Hardware Overview The Acquitek CH family of PCI data acquisition cards has the functionality of an oscilloscope logic analyzer function generator and arbitrary waveform generator The oscilloscope features two channels with software selectable high impedance inputs for light circuit loading or 50 Ohm inputs for minimum noise on small signals The logic analyzer samples up to 16 inputs synchronously with the analog inputs The signal generators can drive low distortion signals up to 10 Vpp into a 50 Ohm load A memory controller with a large bank of onboard memory buffers both input and output signals from the PCI bus This is critical since even though the board can sustain bus master transfers at nearly 100 MBps across the bus the net throughput of the board is up to 160 MBps and PCI activity could cause interruptions in the data streaming Finally an onboard digital signal processor DSP is used for real time control of input
58. set up digital trigger mode click the Set up digital trigger button and specify a port mode and which lines to enable If you select Edge trigger the bottom row of checkboxes allows you to specify which ports require a rising edge and which ports require a falling edge If you select Pattern trigger you can specify which ports will be logic high in the pattern and which ports will be logic low CH Series User Manual Page 63 ACQUITEK UI Setting Input Channel Options 7 DASYLab7 Net ain dsb Worksheet File Edit Modules NI DAQ Experiment View Options Window Help KIS 0 50 Sei et Jel Heel 11 18 ork Analog Input 330 11 12 13 L 15 SYSE 9999999 Hardware Exacq Demo Board Channel Name Exacq CH AI 0 r Input Range e 10 00 y DK Channel Setup m Coupling Channel Scaling ac DE Channel Setup C DE Temi m Input Mode Differential Single Ended Pseudo Differential To set coupling or input mode double click on an analog input module In the dialog box that opens select the channel you wish to set up and click Channel Setup Specify options for each of these and click OK For More Information For more information please consult the DASYLab User Guide CH Series User Manual Page 64 oe Technical Specifications Analog Inputs Number of Inputs Impedance Coupling Analog
59. t Etherlink for PC Management NIC d Inspiron 2100 Laptop Integrated Modem Rage P M Mobility AGP 2x icquitek DAQ Board Demo BB Sottware EE Acquitek E Acquitek Enumerator Fight Local Bue Lre Output Ensbla U U 2 3 3 8 Windows NT 2000 4P Third party The Configuration Tab is only available when an Acquitek hardware device is selected in the System Tree Pane This page is used to set the logical device number for Acquitek devices to be used by other software applications CH Series User Manual Page 30 A re Test Tab Acquitek Control Center File Edit View Help Configuration 8 8 Local System Info Configure Test BE Hardware EIR zouet Analog Input SPC PXI Channel 0 Range 10 00 to 10 00 y Mode Differential EE System EPCI Axl BE 82443BX ZX 440BX ZX CPU to F BE 92443BX 2 440BX ZX PCI to Al ME 82371EB MB PIIX4E M ISA Bride 9 823714B EB MB PIIX4 E M EID 8 82371AB EB MB PIlX4 E M USE 8 82371MB PlIX4M Power Manage MA Crystal 054281 SoundFusion PCI BE Unknown ME 3C905C TX Fast Etherlink for PC L M3 Inspiron 2100 Laptop Integrated N Rage P M Mobility AGP 2x Analog Output SB Acquitek DAG Board Demo BE Software Channel 0 j Polarity Bipolar y DC Volts 0 0000 BEAcquitek IS Acquitek Enumerator FS Acquitek Control Center FS Acquitek Bench ystem 18 Windows NT 2000 XP E Third party Digital 10 The Test Tab
60. t show up in this dialog the file may be in the wrong place Make sure you have completed step 1 correctly 5 DASYLab will inform you that you must restart DASYLab for the changes to take effect Restart DASYLab The Acquitek DASYLab Driver should now be installed and can be accessed from the Input Output item in the Modules menu Adding Acquitek Driver Modules to your DASYLab Worksheet To add modules using the Acquitek DASYLab driver to your worksheet select Analog Input Analog Output Digital Input or Digital Output from the Input Output submenu of the Modules menu Selecting a Device To choose a device select Hardware Setup from the Experiment menu Choose a device number as defined in Acquitek Control Center and click OK ACQUITEK CH Series User Manual Page 62 A Setting up Triggering DASYLab7 Net ain dsb Worksheet File Edit Modules NI DAQ Experiment View Options Window Help Analog Input Triggering Trigger Type Analog Trigger Channel o Trigger Volts 0 000 FalingEdge Rising Edge Klnlsl Djesa Save Be Fle 8 Hee el L Cancel Analog Output Triggering Trigger Type None y Trigger Channel T TriggerVots T FalingEdge Risng Edge Set up digital trigger To set up analog input triggering CM XM or CH XH or analog output triggering CH XH select Hardware Setup from the Experiment menu Select trigger options from the dialog box To
61. th channels are sampled simultaneously The input channel is shown in figure 2 12 Bit A D Converter Gain Offset Trim Figure 3 2 CH Input Architecture The signal is connected to the board through a BNC connector into a high speed instrumentation amplifier This is a differential input amplifier allowing the signal reference to be electrically isolated from the board ground The purpose of this isolation is to prevent ground loops from occurring in the measurement setup A typical ground loop setup is depicted in figure 3 3a As can be seen from the figure the measured voltage is in error by the amount of ground potential difference between the source and measurement device This can be a major problem preventing accurate measurements particularly when the signal source is a long distance away from the measurement point or the source and measurement devices are powered from different electrical circuits In figure 3 3b the CH differential input is shown However the voltage difference from the input reference to the local computer ground Vena from figures 3 3a and 3 3b should not exceed 3 5 V Any voltage difference will limit the available input range of the CH board CH Series User Manual Page 12 A V signal Vand Figure 3 3a Ground Loop Figure 3 3b CH Differential Input Eliminates Ground Loop NOTE The differential input structure of the CH is only intended to eliminate ground loops With a balanced tra
62. tton in the Trigger section of the Scope Panel Volts DIV Specify the number of volts per division on the vertical axis display Position Channel Specify the vertical offset of the entire channel in Percent of the Display Coupling Specify the signal coupling of this channel Visible Specify whether the channel trace line is visible CH Series User Manual Page 42 A id Mode Analog input type differential 2 wire single ended 1 wire or non referenced single ended 1 wire Coupling Analog input coupling and impedance Probe Specifies a 1x 10x or 100x probe for scaling of display values Analog In Channel Zero based analog input channel number Device Number Data acquisition device number as configured in Acquitek Control Center You must assign a device number to the acquisition board before it can be used in Acquitek Bench or other application software Note Additional configuration options can be accessed by right clicking on the instrument ACQUITEK CH Series User Manual Page 43 A Spectrum Analyzer Spectrum Analyzer alal 4 Bela Channel 2 20 0 25 0 30 0 35 0 45 0 50 0 Frequency Khz CHI CH2 Ali Channels Range GOR gt Range HOT gt Coupiino LT gt Mode ETT Mode EES Samples Second ooo Analog In Channel o E On Analog In Channel i E On ME E The Spectrum Analyzer is used to measure the frequency spectrum of a signal on an analog input channel Range V
63. ugs Pin 1 Location CH Digital UGO Header Loop Out Header O O O O O Q O O G G O O Q O Figure 1 B 1350 Layout If you plan to also use an Acquitek B 1250 external RF multiplexer with the CH Series board you will have received a L 4700 DB 37 Bracket to Header assembly with the B 1250 After the steps above connect the header of the L 4700 to the Loop Out header on the B 1350 then connect the B 1250 multiplexer as always to the L 4700 s DB 37 connector ACQUITEK CH Series User Manual Page 69 A DI O Header Pin 1 Location DI O Header Aino gt Aint C da aca Aux gt El A Aout0 gt PCL Interface Aout gt Figure 2 CH Board Layout A ACQUITEK CH Series User Manual Page 70 WwW The pinout of the screw terminal plugs is shown below Note that the screw terminal plugs are removable to simplify the connection of wires DIO 0 DI O 1 S DIO 2 oo G DIO 3 I Do4 gt Doos Dos gt 0 Do7 0 Dos gt o Dos 1 DI O or DI O a 2 DIO 12 Tr DI O 13 ss Q DI O 14 DI O 15 NC Gnd 5V W Figure 3 B 1350 Pinout CH Series User Manual Page 71 aor B 1250 1255 RF Multiplexer Optional The Acquitek B 1250 is a 4 1 high frequency analog multiplexer demultiplexer the B 1255 is the same unit without a physical enclosure It is intended to operate under software control in
64. umber at the time when the trigger occurred Until this happens data is not transferred across the PCI bus A large pre trigger buffer is supported by the large bank of onboard SDRAM memory Triggering is available from the following sources analog level from either analog input channel or the external trigger with positive and negative slope or on logical combinations of up to all sixteen DIO s Software can also trigger data capture or place the analog inputs into free run mode FPGA Local PCI Bus Host SDRAM SDRAM Analog Trigger Ext Trigger DIO Trigger S W Trig free run Figure 3 9 Input Data Flow Host PCIB Local FPGA D A SDRAM SDRAM OR Figure 3 10 Output Data Flow ACQUITEK CH Series User Manual Page 23 Ar Also note that input and output data is transferred as 16 bit words This minimizes processor overhead which would be required to separate 12 bit A D and D A words if they were packed into 3 bytes However with 20 MHz 2 bytes sample 2 channels 80 Mbytes sec on both the input and the output net data throughput required of the CH board is 160 Mbytes sec The theoretical maximum for the PCI bus is only 132 Mbytes sec and even with a bus mastering controller on the CH 100 Mbytes sec is difficult to sustain due to other activity on the bus In this case the large onboard SDRAM memory bank is used to ease the PCI throughput bottleneck In most cases the output waveform will be loaded into onboard memo
65. y waveform is desired digital interpolation can be used prior to loading the waveform At the output of the reconstruction filter are two banks of switched attenuators The first bank provides attenuation of 0 dB 6 dB 14 dB and 20 dB The second bank provides attenuation of 0 dB or 20 dB Following the attenuation is the output high power amplifier This amplifier is source terminated in 50 Ohms 75 Ohm source termination for video applications is available Please contact the factory for this option The high power amplifier is capable of driving 10 Vpp into a 50 ACQUITEK CH Series User Manual Page 15 Ai Ohm load or 20 Vpp into a high impedance load NOTE The CH output amplifier depends upon the PC power supply for its 12V supply While the PC 12V power is filtered before it is used to power the output amplifier it is not stepped up with a switching supply If the PC power supply does not provide 12V the CH output may be clipped slightly below the 10V maximum output Pay careful attention to the PC power supply if it is intended to operate the CH output at its maximum level as some supplies may only provide 11 5V or less With this maximum output drive capability and the analog attenuation ranges the following full scale output ranges are possible all assuming a 50 Ohm load 100 mVpp 200 mVpp 500 mVpp 1 Vpp 2 Vpp 5 Vpp 10 Vpp CAUTION With an unterminated load the voltage delivered to the load will be twice that delivered to a
66. z In input mode the DIO s are pulled to 5V through a 10 K Ohm resistor There is also a 100 Ohm software switchable termination resistor which can be used to improve signal integrity on high speed digital switching signals A ACQUITEK CH Series User Manual Page 14 y Output Architecture There are two identical output channels on CH boards equipped with analog outputs The output chain is depicted in figure 3 4 The analog output starts with a 12 bit digital to analog converter D A The D A on the CH board always operates bipolar mode therefore the data input format is two s complement 0 20 dB 0 6 14 20 dB 50 Ohms Filter 12 Bit D A Converter Offset Trim Gain Trim Figure 3 4 CH Output Architecture Following the D A output buffer amplifier is an analog reconstruction anti aliasing filter This filter is a 7 order Butterworth low pass filter with cutoff frequency of 8 MHz A Butterworth response was chosen as the best compromise between frequency domain cutoff properties and time domain transient response In the Acquitek software library square and triangle waveforms are implemented Their frequency is limited to 1 MHz so that the ringing which results from Gibbs Phenomena is kept to a minimum In arbitrary waveform mode it is recommended that the user keep the sample clock close to the maximum rate of 20 MHz in order to maximize the benefit of the onboard reconstruction filter If a low frequenc

Acquitek CH Series - Egmont Instruments

Contents

Download Pdf Manuals

Related Search

Related Contents