CMS Front-End Driver PMC
Contents
1. CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 4 Foreword This document is intended for the general user of the CMS Front End Driver PMC It should contain sufficient information to install and operate the FED PMC Mk2 and Mkl cards This document together with additional FED PMC documentation and software can be obtained from the following web site http hepwww rl ac uk cms_fed default htm Please send any comments on the contents of this document to the editor J Coughlan rl ac uk Please Note This is a working document and is subject to revision 5 Contacts amp Ordering Information Further information concerning the FED PMC can be obtained from the following web site http hepwww rl ac uk cms_fed default htm All queries concerning the operation of the FED PMC and its associated software should be addressed to Dr John Coughlan CLRC Rutherford Appleton Laboratory Chilton Didcot Oxfordshire OX11 0QX UK email J Coughlan rl ac uk Orders for FED PMC s from the CMS Tracker community should be addressed to Prof Geoff Hall at Imperial College London contact g hallOic ac uk All other orders should be addressed to the RAL Instrumentation group contact R Halsall rl ac uk The Mk1 version of the PMC is described in Appendix A FED PMC Mk1 Version 4 0 5 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 6 Getting Started The FED PMC is delivered in a box pla2. Bridge Local 10 0200 20 0000 AA iex il Y VES ES TE A E A E TE Sl i a E RA A EA E E ARE O E Figure 7 FED Address Map as set up by User Library routines Feb 2000 19 Version 4 0 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 10 3 1 PCI Configuration The first step is to set the PCI Memory base address registers for the FED These registers are located in standard PCI configuration space FED library routines expect a specific mapping which is set up in the following routine fedpmc config memory should continue be used with CES RIO or Motorola PPC carriers For carriers employing the Tundra Universe VME PCI bridge chip e g MIDAS20 see section N long fedpmc config memorv long pci cfg base long abs pci mem base long carrier long device number pci cfg base Base address in PCI configuration space for PMC slot as seen bv HOST abs pci mem base Base address chosen for PCI memory space for FED ABSOLUTE address 1 Carrier Carrier board type 1 CES RIO2 RTPC 2 Motorola PPC MVME2600 series device number PCI device number Carrier amp PMC slot dependent return value 0 OK 1 The corresponding address as seen by HOST fedpmc_base is passed to all other FED_PMC routines IMPORTANT The USER must ensure this space is not used by any other PCI devices Example CES RIO2 RTPC lower PMC slot pci_cfg_base 0x80802000 assumes processor has direct h w acces
3. 1 Value should agree with value set in fedpmc_init 2 Useful for removing empty samples around APV frame and hence speeding up readout This routine reads out the next event in the DPM putting the readout data at address dest It can be called inside OR outside a digitisation run NB The act of reading out a buffer frees the DPM memory occupied by that event Version 4 0 23 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 10 3 4 Miscellaneous These routines may be useful for testing FED PMC status amp debugging user code long fedpmc status long fedpmc base long clock source long clock delay long ext trigger source long trigger mode long adc chan mask long adc sample freq long event size long trigger throttle enable long trigger throttle threshold fedpmc base FED base address in PCI memorv space as seen bv HOST clock source 0 gt PCI internal 2 gt Front Panel clock_delay 0 10 ext trigger source 0 gt Front Panel trigger mode 0 gt Start Digitisation adc_chan_mask 0 ff 1 adc sample freq 0 No downsampling sample every clock 1 Downsample sample every 2 clock adc_samples 16 32K Number of ADC samples to readout per event trigger throttle enable 0 Throttle signal disabled 1 Throttle signal enab led trigger throttle threshold Number of occupied buffers at which throttle signal appears This routine simply gives the sta
4. CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 CMS Front End Driver PMC User Manual Version 4 0 Jan 2000 DRAFT VERSION CLRC Rutherford Appleton Laboratory Version 4 0 1 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 1 Contents Ti CONTENTS ci is 2 2 FIGURES sin nn had i al dia tai 0 said o ad he h dh irie s iaasa sarees iiie iniata 4 3 TABLES i ii b a A Ow Soe A 4 4 FOREWORD i ieled d i 5 5 CONTACTS amp ORDERING INFORMATION essssssseseccscescococoscsesecescesoossceeseceeceeceoo 5 6 GETTING STARTED ii g ia ai aa a ibid S l oe h dd T SEEN bia lab a 6 6 1 INSTALLATION amp JUMPER SETTINGS ccccccccececececeseececeeeeeeseseseesueeeeeeesescesteeeeeeseseesteeeaeeserseseteaenees 6 6 2 CARRIER CONFIGURATIONS o Did 7 7 INTRODUCTION ie sa ek ibs cidad sk b d v d d 8 7 1 GENERAL DESCRIPTION td 8 7 2 ARCHITECTURE da 8 8 FED PMC HARDWARE ois isiiceis ia ala sis do v vo dd nde 85 608 0d da d S v i n 10 8 1 FRONT PANEE LA YOU i A A a e he ed det A 10 8 2 FORM FACTOR a e 10 8 3 ANALOGUEJINPUTS iio 10 8 4 CLOCK amp TRIGGER FRONT PANEL INPUT S A aa AKP A EE ERE RERE Re Rei brek eee eke beat er ekietekeses 11 8 5 DON A IE 11 8 6 PL A a A baka A di 11 8 7 BRGA MS ria 11 8 8 JUMPERS EIA ICE a A A A 11 8 9 EDS a O oa seas sees 12 9 FED PMC FUNCTIONALITY puc die ccc eks sse ki wa er s dri ae Ad bla de pede a de 13 9 1 MEMORY REQUIREM
5. CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 SIGNAL NAME PMC 2 VME64 PMC 1 VME64 J4 JN24 P2 J4 JN14 P2 CLK_J4 33 oD SCS VIRIGJETT 9 e Jo poe 7 FONDA pe Ja 26A EJ Version 4 0 46 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 21 References 1 2 3 4 5 6 7 8 9 Version 4 0 PMC IEEE P1386 Draft 2 0 PCI Mezzanine Card Specification FED 9U User Manual ftp ftp te rl ac uk cms fea FED UM 2 0 paf LVDS htip www national com appinfo lvds ADC SPT7861 htip www spt com datasheets datasht1 html PLX PCI 9080 httip www plxtech com products prodset htm XILINX 4036 XL http www xilinx com products xc4000xl htm CES RIO2 RTPC htip www ces ch Products Products html Motorola PPC SBC http www motorola com APV6 User Manual ftp ftp te rl ac uk apv6 user_manual apv6_user_manual_2 0 ps 47 Feb 2000
6. CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 12 Examples of using Carriers The great advantage of the PMC format is that it can be placed on a great variety of carrier boards The great disadvantage of the PMC format is that is can be placed on a great variety of carrier boards Here are a few hints on how to get going with various carriers Please also refer to the documentation of your own carrier board and OS 12 1 CES RIO2 RTPC running Lynxos Either Mk1 or Mk2 cards will run on RIO2 RTPC 7 Check the jumper settings for Mk2 card section 6 1 An example main routine and make file are available on the web server together with the standard FED source files The main routine is located in the file fedpmc example c The make file is fedpmc_example_lynx mkk Set up some directories on vour Lvnx area as follows fedpmc src put the header and source files here fedpmc make put the make file here fedpmc obj the object files will be made here fedpmc bin the executable program fed_lynx will be made here fedpmc output the output files should go here Modify the makefile to compile all files with the following flags defined define FEDPMC CARRIER CESRIO2 RTPC define FEDPMC LVNX Rebuild Run the executable fedpmc This simple example program initialises the FED and does a simple event loop generating software triggers and reading out the events to a file The user can tailor it to use external tri
7. clock sources and delavs are changed so as to minimise the likelihood of unpredictable behaviour 10 Exit clock configuration mode De asserts FPGA reset and enters runtime mode Maintain LRESETO low after this command has been executed 11 Load FPGA from Flash EEPROM Executing this command will enable the automatic load of the FPGA from the Flash EEPROM If this command is not executed the FPGA will need to be loaded directly via the serial interface Table 10 Serial Sub commands The status register gives some information as to the configuration state of the FPGA it is recommended that this register is read after the execution of each FPGA configuration write command Status Register 2 bits shifting LSB first Field Description Read Write Reset Value INIT pin value from FPGA value of 0 indicates that there Yes No has been an FPGA configuration error 1 DONE pin value from FPGA value of 1 indicates that Yes No FPGA configuration has been completed successfully Table 11 Serial Status Register Version 4 0 34 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 13 1 4 FPGA The FPGA performs all of the runtime functions memory interface registers buffer management etc 13 1 4 1 1960 Interface A conventional i960 compatible burst capable slave interface has been implemented The FPGA holds i960 bus mastership following reset although all that the arbitration logic wi
8. 2 MBytes PCI I O Space None Used 9 2 ADC The 8 ADC channels are grouped into 4 pairs The outputs of each pair can be enabled or disabled Normally ALL channels should be enabled 9 3 Trigger There are 2 possible Trigger sources section External Front Panel LVDS Trigger pulse width 25 nsec Software only available in Test Mode After a PCI reset external triggers are ENABLED The only Trigger mode presently implemented is Start Digitisation In this mode a trigger pulse either external or software during a digitisation run causes a pre set number of samples to be digitised and stored in the DPM Version 4 0 13 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 IMPORTANT If N further triggers arrive during the data capture period from the first trigger the data from these N later trigger will be LOST What actually happens is that the data from the first trigger is stored in DPM 1 N times E g If sample size is 512 and clock frequency is 40 MHz then minimum separation of triggers should be approx 512x25 nsec 12 8 usec 9 4 Clock There are 2 possible clock sources Front Panel LVDS PCI clock internal 33 MHz After reset the internal PCI clock is ENABLED NB The selected clock is used to drive all the logic circuits of the FED and must ALWAYS be running i e if external clock is selected it must never be interrupted A delay can be introduced into the clock signal pat
9. APV 9 channels Carrier 2 x RIO2 running LynxOS FED PMC was interfaced to APV via the TRI card from Perugia FED PMC inputs were configured for Differential inputs 0 75V with an internal amplifier gain of 2 Clock frequency 40 MHz Therefore APV frame running at 20MHz was double sampled Trigger source external via TTC system Sample size 1024 necessary to capture APV frame arriving much later than external trigger FPGA firmware used version 0 revision 2 original scope mode Version 4 0 44 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 20 Appendix C PMC J4 Aux Connector NB The J4 Interface signals are NOT yet implemented in the Mk2 PMC FPGA Firmware The PMC Aux connector J4 is used to optionally receive the TTC signals 6 from a VME transition module mounted on the VME backplane The following signals are provided Trigger LVDS Trigger TTL Clock LVDS Additionally there is an optional output fast warning signal so called trigger throttle to the DAQ system to signal that the buffers are becoming full When the PMC is mounted on a suitably equipped VME module the PMC standard routes the 64 Pins of the J4 PMC Auxiliary connector to the VME J2 spare pins The pin out of the PMC J4 and mapping to the VME J2 on CES RIO2 RTPC 7 is given in Appendix A Connectors PMC J4 on CES RIO2 RTPC 7 CLK J4 LVDS TRIG JA LVDS Other Signals CMOS Version 4 0 45 Feb 2000
10. EE cece cece KEE eee EE TE EE DID eG rr rtrtrtrnininrnrnrn EE EES 41 17 2 FED HANGS AFTER ENABLING EXTERNAL CLOCK cccccecececesecececececeeecneeeneneenenenea ease ee eaeeeeeeeeeeenenenees 41 17 3 EVENT amp BUNCH CROSSING COUNTERS DON T RESET FOR A NEW RUN 2 aaa aaa aaa nanen ede eee pe ve ve ve ererat al 17 4 BUFFER OVERFLOWS OR NUMBER OF FILLED BUFFERS IS NOT AS EXPECTED 2 aaa aaa aaa aaa enen e eee deveve 42 17 5 NO SOFTVARE TRIGGERS idad ed dd ASE 42 17 6 SAME EVENT IS READOUT MORE THAN ONCE aaa aaa 42 17 7 NO HARDWARE TRIGGERS li sa tkis sie is db dd R dt As 42 17 8 THE DPM IS FULL OF VALUES LIKE 256 257 OR 0 42 17 9 THE EVENT COUNTER DOUBLE COUNTS 7 eee pete pete petet 42 17 10 SPURIOUS TRIGGERS RECEI VEDI 43 18 APPENDIX A FEDEPMC MK h san os da dans da deh de actos 44 19 APPENDIX B CERN TEST BEAM SETUDBP cccccccccscccceccccccccecccsccncecscsccsceceeans 44 20 APPENDIX PMC J4 AUX CONNECTOR 6 6 ia i ca nd r de nd n e dra 45 21 REFERENCES a Seeds ea see spa be 47 Version 4 0 3 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 2 Figures FIGURE L JUMPERS PLTO amp PLI e events enes dt A ii 6 FIGURE 2 PHOTOGRAPH SHOWING BOTH SIDES OF THE FED PMC MK2 cccccececceceeeeceeeeeeeececeeeeeneeeeneaeeeenenees 8 FIGURE 3 BLOCK DIAGRAM OF THE FED PMC 1 0 0 0 ccc cece ccc cece ec ec ee nono nono nono nono nono ne nono EE EE ED EIT EI DEI EEI tEnEnE tin n tn nt nti 9 F
11. Write Reset gt EIN ES e DON 3 2 TR SRC front panel J4 LVDS trigger J4 TTL trigger TR MODE Start Digitisation Reserved Reserved Reserved SAMPLE FREQ LASIBA 03 FED_CTRL 0 must be clear to enable writing to this register Version 4 0 36 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Number of clock cycles between samples On receiving trigger wait for this number of clock cycles before capturing first sample leave this number of clock cycles between subsequent samples TRIG_THROT_THRESH LASIBA 04 Field Description Read Write Reset Value Trigger throttle threshold Value above which the buffer Yes Yes occupancy must rise for the trigger throttle output to be asserted FED TEST LAS1BA 08 Field Description Read Write Reset jo 7 3 Reserved A KT Writing 1 to E bit causes a software reset of the bunch crossing counter when FED_CTRL A is set 1 BX_CR Writing 1 to this bit causes a software reset of the No event counter when FED_CTRLJ 4 is set TRIG Writing 1 to this bit causes a software trigger if the FED is in start digitisation trigger mode and FED_CTRL 4 is set FLASH PORT LASIBA 09 Field Description Read Write Reset gt CP_SDI Connection to serial data input of Flash EEPROM via CPLD Can be used to program Flash EEPROM in conjunction with CP_SCLK when CP_FLASH is set CP_SDO Connection to serial dat
12. channel you should read 0 17 9 The event counter double counts If running with external triggers the trigger pulse width should be set to the clock period E g If clock freq 40MHz Trigger pulse width should be 25nsec If pulse width 50nsec event counter will count twice on each trigger If pulse width 75nsec event counter will count 3 times on each trigger etc Version 4 0 42 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 17 10 Spurious triggers received The FED PMC triggers on rising edge of any signal on trigger line i e including APV resets and calibration signals Only send genuine event triggers to the FED Version 4 0 43 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 18 Appendix A FED PMC Mk1 IMPORTANT The Mk1 FED PMC serial numbers 1 12 does NOT have the option of an on board 3 3 V supply NB There are no Jumpers on Mkl card Therefore it cannot be operated on carriers which do not provide 3 3V such as VMETRO MIDAS 20 NB Mk1 cards CAN be used on CES RIO2 RTPC and Motorola PowerPC SBC s In ALL other respects the Mk1 card is functionally IDENTICAL to the Mk2 card 19 Appendix B CERN Test Beam Setup The FED PMC was first commissioned during the October 1998 Tracker test beam run at CERN in T9 area FED PMC s were used during the 1999 T9 and X5 test beam runs under the following conditions Total of 4 x FED PMC Mk2 providing a total of 32
13. is thus intended to provide a cost effective solution to the prototyping requirements of the Tracker community The FED PMC package also includes all the necessary software for FED set up and readout 7 2 Architecture A diagram indicating the basic functional units of the FED PMC is shown in Figure 3 The card has 8 electrical input channels which can be configured at assembly for either differential or single ended inputs Each channel utilises a commercial ADC and is capable of digitising 9 bits at clock speeds from between 2 and 40 MHz The data is stored in contiguous blocks inside a Dual Ported Memory DPM The DPM is implemented as 4x 64K x 18 bit synchronous memories and is capable of buffering the raw data from approximately 250 APV frames The data is read out can be done in parallel with ADC capture over the PCI bus via a 32 bit 33 MHz commercial bridge interface A FIFO provides storage for event buffer pointers and event counter information 1 ADC s are 10 bit devices LSB is not readout Version 4 0 8 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 A CPLD implements the clock and trigger control Trigger and clock LVDS signals are brought in on the front panel The fine adjustment of the clock phase with respect to the data can be set under software control in order to obtain the optimum sampling point at the ADC For testing purposes triggers can be generated internally by software and t
14. mm 8 3 Analogue Inputs The Analogue Inputs can be configured as either differential or single ended at assembly NB By default all cards are delivered with the same configuration as those used in the CMS Tracker test beam in April 1999 i e Differential inputs 0 75V with an internal amplifier gain of 2 to match full ADC range 0 3V Alternative assembly instructions can be implemented on request Version 4 0 10 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Number 8 Connector type LEMO part no FGG 00 302 CLAD35 supplied with PMC delivery Differential range 0 75V max Single Ended Range 0 75V typ 1 50 V max5 Termination 1000 differential stp 500 singleended co ax 8 4 Clock amp Trigger Front Panel Inputs Connectors LEMO part no FGG 00 304 CLAD35 supplied with PMC delivery Levels LVDS 3 CLK 2MHz to 40MHz TRIG synchronous to CLK 8 5 ADC Device used SPT 7861 4 Conversion rate 2MHz 40MHz continuously sampling Max Resolution 9 Bit 10 Bit Converter LSB is not used 8 6 PCI Connector PMC J1 J2 Clock Speed lt 33MHz Switching regime 5V Bus width 32 bit Bridge PLX PCI 9080 5 PCI Specification v2 1 PCI Configuration Space 64 bytes standard configuration header PCI Memory Space 2 MByte occupied as one contiguous block PCI I O space None The FED PMC is configured as a PCI Target i e Slave access only 8 7 FPGA XILINX XC4036XL 6 8 8 Jumpers amp Switc
15. once FPGA is loaded long fedpmc init long fedpmc base long clock source long clock delav long ext trigger source long trigger mode long adc chan mask long adc sample freq long adc samples long trigger throttle enable long trigger throttle threshold fedpmc base FED base address in PCI memorv space as seen bv HOST clock source 0 gt PCI internal 2 gt Front Panel 1 clock_delay 0 10 for corresponding delay values see Table 2 ext_trigger_source 0 gt Front Panel trigger_mode 0 gt Start Digitisation adc_chan_mask 0 f bit 0 1 0 enables disables ADC pair 0 amp 1 bit 1 1 0 enables disables ADC pair 2 amp 3 bit 2 1 0 enables disables ADC pair 4 amp 5 bit 3 1 0 enables disables ADC pair 6 amp 7 adc sample freq 0 No downsampling sample everv clock 1 Downsample sample every 275 clock adc samples 16 32K Number of ADC samples to readout per event 2 trigger throttle enable 0 Throttle signal disabled 1 Throttle signal enab led trigger throttle threshold Number of occupied buffers at vyhich throttle signal appears return code 0 OK 8 error invalid number of ADC samples 2 11 error can t initialise during digitisation run 1 NB User must ensure the Front Panel clock is running BEFORE selecting it or FED will hang up 8 adc samples parameter should be adjusted accordingly Version 4 0 21 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC
16. the clock generated by the download cable This will enable stepping of the clock to the FPGA and the local interface of the PCI 9080 13 4 Board Set up There are several steps required to configure the FED Some are only relevant to production some constitute part of the boot up sequence 13 4 1 PCI 9080 configuration The PCI configuration registers must be set up in software from PCI during the boot sequence 13 4 2 FPGA Configuration As the FPGA is implemented in SRAM technology it will require configuring as part of the boot sequence 13 4 2 1 PCI space Using the serial configuration interface built into the CPLD the FPGA can be configured by software using the PCI bridge local registers 13 4 2 2 Flash EEPROM The Flash EEPROM can be used for FPGA configuration For this mode the FPGA will have had to be configured as described in 13 4 1 and then the EEPROM port in the FPGA registers used to program the EEPROM by bit stuffing Reference INI gives details of commands for reading and writing the Flash EEPROM The FPGA configuration should be stored starting at address 0 To start FPGA configuration from Flash EEPROM a suitable serial command is issued Version 4 0 39 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Note that memory in Flash EEPROM that is not used for FPGA configuration data can be used for serial numbers or any other miscellaneous information areas other than that occupied by
17. 004 2000 2 ONLY certain values are permitted see Table 3 This routine should be called to configure the FED PMC registers prior to readout It should be called OUTSIDE of digitisation run 10 3 3 Readout void fedpmc_reset_counters long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST This routine resets the event and bunch crossing counters NB It should only be called DURING a digitisation run long fedpmc purge buffers long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST return value Number of buffers that were purged This routine clears all pending events in the DPM It does this bv flushing the FED FIFO The buffer occupancv counter is not reset to 0 until the start of the next run In order to ensure clean buffer situation it is recommended it be called before each new digitisation run It can also be called during a digitisation run void fedpmc start digitisation long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST This routine turns the digitisation run ON Note The ADCs run continously This routine enables the capture of ADC output in the DPM void fedpmc_stop_digitisation long fedpmc_base fedpmc_base FED base address in PCI memory space as seen by HOST This routine turns the digitisation run OFF Note The ADCs run continously This routine disables the capture of ADC output in the DPM void
18. DC samples to capture etc 5 Clean up from anv previous runs This step checks for and purges any pending buffers from the previous run i e triggers which have not been readout fedpmc purge buffers if purged buffers 0 warning some buffers were not readout from previous run 7 Start a digitisation run Note In the current firmware the event and bunch crossing counters can only be reset when the run is ON Therefore we must disable external triggers before starting the run After the run is started we reset the counters and immediately re enable triggers to continue fedpmc enable test mode disables external triggers fedpmc start digitisation start run fedpmc reset counters fedpmc disable test mode re enables external triggers 8 Poll on pending events readout and process event data while run ON Version 4 0 27 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 fedpmc occupied buffers check for events if occupied buffers gt 0 copy DPM contents to specified address fedpmc readout event user s own code to process readout data Note that readout can continue in parallel with the arrival of new triggers 9 Stop the run disabling further triggers fedpmc stop digitisation stop run Now we are ready for another run e g go back to step 4 change conditions and start another run Version 4 0 28 Feb 2000
19. ENTS i ie ine s ti dhene ii 13 9 2 ADE IO A 13 9 3 TRIGGER 2 a i aa b ng E A A E ida 13 9 4 ol IA 14 9 5 EOOD ji N EA eL E EEEE A a 14 9 6 TRIGGER THROTTLE ase yes nise de nse EEDEN 14 9 7 TEST MODE i ss B B E DA eee ee 14 9 8 READOU Pi e A haw do iia idos 15 9 9 FIRMWARE ses 15 10 FED PMC SOFTWARE ii sia asi ane ba kd iris 17 10 1 SOURCE FILES is diss dt ee oe dod pew e rc 18 10 2 USERILEVEEROUTINES API e a ede a a A oa 18 10 3 PCI CONFIGURATION AND ADDRESS MAP aaa akne ESE E RERE RERE ERE RERE RERE ER eterik pere ek rete ven ietekeses 18 10 3 1 PCI Configura Omeia LA A AA e 20 10 3 2 IG SALON taa A NDS A A NA 21 10 3 3 e E EE 22 10 3 4 PN 24 11 EXAMPLE PSEUDO CODE ia i civ ois n n or isis 0 ele v K n ee sie 26 12 EXAMPLES OF USING CARRIERS 1 ad aa aaa na nene nene re sere rne reper rere Dere rro rere re rere cc me 29 Version 4 0 2 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 12 1 CES RIO2 RTPC RUNNING LYNXOS iii iia ver E or dd 29 12 2 MOTOROLA MV ME2600 SERIES RUNNING LYNXOS EEA EE en nr seen ease ease ease eeeeeeeeenenenees 29 12 3 CARRIERS USING UNIVERSE VME PCI BRIDGE cccccceecececececececececeeeeeeeenen ease ease ease ease sees esse seen seen 30 13 HARDWARE LEVEL DESCRIPTION 000 a dies 31 13 1 DIGITAL A RE Miata LNT 31 13 1 1 Dual Port Memo A ce bi biet nm 31 13 1 2 POL BAGG is ven i A a awn A dt md de Le seh d aw dem n fe Sive eyes 31 13 1 2 1 PCE Configuration Re
20. FPGA configuration data are only accessible for read and write in software 13 5 Board Operation 13 5 1 Boot up Configure FPGA Configure Clocks Enter Runtime 13 5 2 Runtime Set up trigger mode and source Enable appropriate channels Set up event size Set up sample frequency Set up trigger throttle threshold Enable FED Capture Data 14 APV Header Finding Mode To be completed Version 4 0 40 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 15 Debugging Tools A monitor debugger program fedmon which provides a set of low level tools for expert FED debugging and FPGA development is available from the web server This program only runs on CES RIO2 RTPC carriers and is at present the only means of updating the contents of the Flash EEPROM and hence the FPGA firmware A LabView application has also been developed to aid FED PMC testing Note These specialist tools are NOT required by the general FED user The standard User Libraries should be sufficient for normal operation of the FED PMC 16 Web Server FED PMC Documentation Software and latest News can be obtained from the following web site http hepwww rl ac uk cms_fed default htm 17 Trouble Shooting Here are a few hints on what might go wrong and what to look for 17 1 LED does not come on at Power on The single red LED location top right of visible side of PMC when mounted should come on when the FED PMC is powered
21. IGURE 4 FED PMC FRONT PANEL LAYOUT 1 10 FIGURES EVENT FORMATIN DPM l iben a dono isa edh de poetes siste tds 16 FIGURE 6 LAYERED SOFTWARE DESIGN llli KEEA ee ee EE EEA EEA ee ee nr rr rro nene nono ED ED ED ED rn EM rra nano nn nana nanonanononons 17 FIGURE 7 FED ADDRESS MAP AS SET UP BY USER LIBRARY ROUTIN S aaa aa aaa aaa aa aaa aaa anen rere 19 3 Tables TABLE 1 EXAMPLE JUMPER SETTINGS FOR VME PMC CARRIERS aa aaa 6 TABLE 2 CLOCK DELAY SETTINGS A acia 14 TABLE3 READOUT SAMPELESIZES coreo B deseo tnees steed ps nd i tA 15 TABLE 4 PCI BRIDGE CONFIGURATION REGISTERS ocococccncncncncocncocononononono nooo nono nono nono nono ED EEI EM EI EEI tititiniti nt nn nn nt 31 TABLE 5 LOCAL BRIDGE CONFIGURATION REGISTERS ocococccncncncocococononononono nono nono nono nono nono EIT ED ED ED IE tEtitinE ninni nn nn nn 32 TABLE 6 SERIAL CONFIGURATION COMMANDS aaa 33 TABLE 7 SERIAL CONFIGURATION REGISTERS ococococncncncncncncncncncncncnnn ee eens Ea ee EE Er rro nono nono ED ED ED ED rn rra nono nono nananananononons 33 TABLES CLOCK DELAY SETTINGS ici 34 TABLE 9 CLOCK SOURCE SELECTION vs pn S ho dd dar 34 TABLE 10 SERIAL SUB COMMANDS 11 ia aa nana 34 TABLE 11 SERIAL STATUS REGISTER sine vesin den dd Sen 34 TABLE12 DPM ADDRESS MAP sened din os den dd k t dvd od e e sd 35 TABLE 13 FED REGISTER MAP size doku kendet pe dre T dd dr ne pen ere ND R od 36 TABLE 14 FIFO CONTENTS ind pordhe vd e dd dr 38 Version 4 0 4 Feb 2000
22. MS FED PMC User Manual DRAFT CMS FED PMC 004 2000 13 1 2 2 Local Configuration Registers Local configuration registers offset relative to PCIBARO Register PCI Value Comments Name address offset DPRAM LASOBA 00000001 Maps base of DPRAM window to local address 0 030300C3 Ignore expansion ROM bus region descriptor Enable BTERM input enable prefetch enable bursting enable extra long serial EEPROM load LBRDO LASIRR F0 FFFFFE0O Value copied into PCIBAR2 to specify size of window to FED specific registers LASIBA F4 00100001 Maps base of FED specific registers window to local address 00100000 LBRD1 F8 00000243 J Disable BTERM input disable prefetch disable bursting Table 5 Local Bridge Configuration Registers 13 1 3 CPLD The CPLD performs configuration sequencing functions implements a serial configuration interface and provides an easy means of hard wiring several PCI 9080 configuration pins 13 1 3 1 Configuration Sequencing The CPLD takes the PCI RST signal as an input and distributes reset signals to the PCI 9080 and the FPGA as appropriate When RST is released the CPLD releases the PCI side reset input to the PCI 9080 and awaits a command from the serial interface as to how the FPGA is to be configured from the Flash EEPROM or the serial interface Once the FPGA has been configured The CPLD expects to receive a command from the serial interface to enter runtime m
23. Write a single data block of FPGA configuration bitstream to FPGA The length of this data accompanying this command is specific to the XC4036XL See Xilinx Data book for further details Write footer portion of FPGA configuration bitstream to FPGA See Xilinx Data book for further details Table 6 Serial Configuration Commands Registers available through the serial interface have the following structure Configuration Register 8 bits shifting LSB first Value BEI KT oo SES EC es Table 7 Serial Configuration Registers The following table shows the correlation between the clock delay value and the actual approximate clock delay All delays are to an accuracy of 1 0ns Clock Delay Clock Delay Comments Value 0011 0100 0110 0111 1000 Bypass delay line Bypass delay line Version 4 0 33 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Disable clock Disable clock Disable clock Disable clock Table 8 Clock Delay Settings The following table details the clock source selection options Clock Source Clock Source Comments Value Isb mao OJ Prov Penet poa ooo Table 9 Clock Source Selection The write only sub command field is used to perform configuration state transitions Note that a write to the sub command field is a write to the whole register Sub command Description Isb 01 Go into clock configuration mode In this mode the FPGA is held reset whilst
24. a output of Flash EEPROM via CPLD Can be used to read Flash EEPROM in conjunction with CP_SCLK when CP_FLASH is set CP_SCLK Connection to serial clock input of Flash EEPROM via CPLD CP_FLASH Connection to enable input of Flash EEPROM via CPLD EVENT SIZE LAS1BA 0C FED_CTRL 0 must be clear to enable writing to this register Field Description Read Write Reset Value 15 0 Number of samples to capture after each trigger Permitted Yes Yes values are shown in Table 3 BUFFER_OCC LASIBA 10 Field Description Read Write Reset Value 15 0 Number of events pending readout in DPM Yes No 0 Version 4 0 37 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 FIRMWARE VERSION LAS1BA 7C Field Description Read Write Reset Value 31 20 Firmware fed magic number 5 Firmware version id es No EZ E EIN COI QO DOI JI 13 1 4 4 Trigger and Buffer Management The only trigger mode implemented on the FED version 1 0 is Start Digitisation In this mode a trigger pulse causes the number of samples given in register EVENT_SIZE to be digitised after a latency of number clock cycles Additionally these samples may be separated by the number of clock cycles given by register SAMPLE FREQ Samples from each trigger are stored in dual port memory in consecutive contiguous buffers 13 1 4 5 Event Counters and Event FIFO The FED incorporates two event counters for eventua
25. been tailored to specific PMC carriers where necessary This routine arranges the 3 spaces to be contiguous as shown in Figure 7 All other routines depend on this memory mapping and are passed a single base address to allow access to the FED resources 7 Note that the Mk1 and Mk2 PMC s are not equipped with a serial EEPROM attached to the PCI bridge Therefore all the configuration information including address space sizes required by the host must also be explicitly set up Some special handling may be necessary for certain BIOS s Version 4 0 18 Feb 2000 CMS FED PMC 004 2000 CMS FED PMC User Manual DRAFT The address path between the host processor and the FED will also depend on the precise configuration of the carrier Hence the configuration rout dependent ines are carrier Local Bus Address PCI Address 00 0000 FED Base PCIBAR2 0 0080 10 0000 a TRS makna aa aa Pe e T Pe T aa Te Ta az aa aa aa aa ATA TA ATA ATA A A 0 0 00 a TATI i MEMINI M M Pa T e T Pe e T T e Ta Se Te aa e a Te Ala TA TA TA ATA ATA 00 aaa 00 0 0 0 a TA a A a TAI aa Tea Da Ta aa Ta aa aa a a a a al MEMINI M T aa T T T e Te Ta Sa aa aa a LA A kl FR Q gt ot PCIBAR3 BAR2 10 LEM FO FED E AVILA 0000 TA PC ters 1S FED Reg 128 Bytes 10 1000 PCIBARO PCIBAR2 10 1000 SS Registers 256 Bytes
26. crossing number is related to be made available A suggested algorithm to read out data from memory is given below Read BUFFER OCC IF 0 then events are stored in memory Read FIFO to get pointer to buffer in which next available event is stored Version 4 0 38 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Read FIFO to get event number of data in this buffer Calculate address of buffer and read data from it multiply buffer number by EVENT_SIZE and add base address of memory window Read FIFO to get bunch crossing number and thus to free the buffer Note that events received when all buffers are occupied will over write previous events it is recommended that the trigger throttle output be used to prevent this scenario occurring 13 2 CPLD configuration 13 2 1 Lattice download cable The lattice CPLD is configured using the software and cable supplied by Lattice it will be necessary to modify the standard lattice cable to have connectors compatible with the SMOX test points that are used for CPLD configuration Note The CPLD is configured at RAL prior to distribution It s firmware is fixed c f FPGA contents which can be updated for firmware releases The CPLD cannot be reconfigured without the appropiate Lattice tools 13 3 FPGA Read back Interfaces are incorporated to allow the use of the Xilinx XCHECKER system for FPGA download and readback The readback mode supported is Synchronous with
27. edpmc base FED base address in PCI memorv space as seen bv HOST xilinx version Returns FPGA load version gt 1 Undefined 1 xilinx revision Returns FPGA load revision gt 1 Undefined 1 xilinx prototype Returns FPGA load prototype flag 0 1 This routine returns version information on the firmware loaded in FPGA void fedpmc read lib version long fedpmc_base long lib version fedpmc base FED base address in PCI memorv space as seen bv HOST lib version Returns software librarv revision as packed characters This routine returns version information on the software librarv Version 4 0 25 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 11 Example Pseudo code The following pseudo code indicates the use of the software routines described in the previous section to set up and readout a FED PMC assuming an external trigger source Real examples of working FED PMC code are available from the web server It assumes that the carrier board is set up to enable memory mapped access to the PMC slot of the FED Note also that no error checking handling is shown in this example The following headers should be included include fedpmc defs h routine declarations include fedpmc h fed register definitions 1 After power on or a PCI reset the first step is to set up the memory mapping fedpmc config memorv This step sets the FED base address for subsequent routi
28. fedpmc_occupied_buffers long fedpmc_base long filled_buffers fedpmc_base FED base address in PCI memory space as seen by HOST filled_buffers Returns number of occupied buffers This routine returns the number of occupied buffers i e number of pending events for readout The buffer occupancy is reset to 0 at the start of each run Version 4 0 22 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 long fedpmc_readout_event long fedpmc base long dest long size long event long bunch_crossing long number_samples long buffer_address long format_flag long dma_flag long skip begin long skip end fedpmc base dest size event bunch_crossing number_samples buffer_address dma_flag format flag skip begin skip end return code FED base address in PCI memorv space as seen bv HOST Destination address for readout data as seen bv HOST Returns total number of bvtes readout including formatting data Returns event number counter Returns bunch crossing number counter Returns number of samples requested for this event 1 Returns buffer address in DPM for debugging purposes 0 gt DMA is NOT implemented yet 0 gt Formatting is NOT implemented yet Number of samples to skip in readout at beginning of data 2 Number of samples to skip in readout at end of data 2 0 OK 11 No events pending 22 Event FIFO empty 33 Error Illegal buffer pointer
29. fedpmc_pci9080 h PCI bridge specific definitions fedpmc_carrier h PMC carrier specific definitions Source files fedpmc c high level user routines fedpmc_regs c low level FED register routines fedpmc_fpga c FPGA specific routines fedpmc_pci9080 c PCI bridge specific routines fedpmc_util c utility routines fedpmc_carrier c PMC carrier specific routines 10 2 User Level Routines API The routines described in this section should be sufficient for normal user operation of the FED PMC An example of their use in a simple readout system is given in section 10 3 PCI Configuration and Address Map The FED PMC has a wide community of users employing a diverse range of PMC carriers host processors and Operating Systems The User Libraries have therefore been written to be as simple and portable as possible The core routines required to setup and readout the FED are written in ANSI C and do not rely on processor OS specific calls or even on the C library functions Where ANSI C library functions are used this is clearly indicated Access to the FED is via a simple memory map Drivers have not yet been implemented and no attempt has been made to use interrupts The FED PMC resources are located in 3 distinct PCI memory spaces section 13 1 2 1 Before the FED routines can be used the memory mapping to these spaces has to be set up on the bridge chip of the FED PMC The routine described in section 10 3 1 used to configure the PCI bridge has
30. ggers by changing the define switches in fedpmc_example c 12 2 Motorola MVME2600 series running Lynxos Either Mk1 or Mk2 cards will run on Motorola PPC 8 Same instructions as for CES RIO2 RTPC section 12 1 except Modify the makefile to compile all files with the following flags defined define FEDPMC CARRIER MOTOROLA define FEDPMC LVNX Version 4 0 29 Feb 2000 CMS FED PMC User Manual DRAFT 12 3 Carriers using Universe VME PCI bridge To be completed Version 4 0 30 CMS FED PMC 004 2000 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 13 Hardware Level Description This section is optional and is intended for those users who wish to understand the FED PMC at the detailed hardware register level 13 1 Digital The digital portion of the design comprises 5 parts dual port memory PCI Bridge PLX 9080 FPGA CPLD and clock selection and distribution Each of these parts will be described separately 13 1 1 Dual Port Memory The dual port memory is implemented as 4 Motorola MCM69D618 64K x 18 bit 3 3V synchronous memories The X data port of each of these memories is connected to two ADCs by means of registered buffers Bits 9 1 of even numbered ADCs are connected to bits 8 0 of memories bits 9 1 of odd numbered ADCs are connected to bits 17 9 The Y data port of each of the memories is connected to the FPGA 1 The X address bus is common acros
31. h in 10 steps of 25 nsec which allows the phase of the clock relative to the data to be adjusted Delay Setting Delay register nsec Table 2 Clock delay settings 9 5 Counters During the digitisation run the following counters are enabled Event counter gt counts Triggers Bunch Crossing counter gt counts Clocks i e wraps around After a PCI reset the counters are zeroed 9 6 Trigger Throttle If the number of occupied buffers exceeds a programmable limit a hardware signal line FAST_WARN see Appendix C PMC J4 Aux Connector routed via J4 connector can be generated to inhibit further triggers 9 7 Test Mode If Test Mode is enabled triggers can be generated by software NB external triggers are disabled After a PCI reset Test mode is DISABLED as passed to fedomc_init routine Version 4 0 14 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 9 8 Readout On receipt of a trigger either external or software the data from a pre set number of samples is captured in the DPM IMPORTANT Only certain sample sizes are permitted see Table 3 Illegal sample sizes will result in unpredictable readout values 4K A RR Table 3 Readout sample sizes Eo EAS EE ae po S R al e E EA EA NIK a II fz aki K K K 12 56 28 4 2 6 2 16 32 64 128 256 512 1K 2K 4K 8K 16K 2K The data from triggers are stored in the DPM in consecutive contiguo
32. he card can run from the internal PCI clock 33 MHz Channel 0 gt screen L m CK Xilinx interface FK PLX Channel 7 A XC 4036 AN address Tt ws EA receiver ZI Trigger Clock alki iene CPLD Figure 3 Block diagram of the FED PMC At the heart of the FED PMC design is an FPGA This permits a large fraction of the card s functionality to be re configurable in firmware and thereby maintains a flexible hardware architecture The basic firmware design configures the FED PMC to provide raw data capture in a digital scope mode VHDL blocks implement the following functions Local data and address bus slave DPM interface Event buffer management FIFO and counters control Register interface Test functions During normal operation the FPGA is loaded on power up under software control from an on board Flash memory Version 4 0 9 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 8 FED PMC Hardware 8 1 Front Panel Layout The arrangement of the analogue and trigger clock inputs with polarities is shown in Figure 4 TOP And guelnpu 7 Andcguelnput 6 Andqguelnpu 5 1 Invertg irput 2 Nonirvering irput And quelnpu 4 Cok amp Trigger Inpu Andqguelnpu 3 And qguelnpu 2 1 CLK_FP 2 CLK_FP Anduelnpu 1 3 TRIG_P 4 TRG _FP Andguelnput 0 Figure 4 FED PMC Front Panel Layout 8 2 Form Factor Single PMC 75 x 150
33. hes See section Installation amp Jumper Settings Single ended input range is controlled by the gain of the input amplifier which is set during assembly Version 4 0 11 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 8 9 LEDs The FED PMC has a red LED located at the top right of the side without connectors i e the side still visible when plugged on the carrier The LED should go ON when the card is powered up It should go OFF after the FPGA has been loaded Version 4 0 12 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 9 FED PMC Functionality The use of FPGA devices means that the FED PMC functionality is re configurable in firmware This section describes the functionality of the FED PMC with the following FPGA firmware Version 0 Revision 2 This is the so called Scope mode In order to guard the user from future modifications in the firmware the provided librarv of C routines should be used to configure and readout the FED 9 1 Memory Requirements The precise arrangement of registers in memory is subject to change All access should be made using the software routines provided The card has the following PCI space requirements PCI Configuration Space 64 bytes PCI Bridge see 5 for configuration registers description PCI Memory Space 1 MByte DPM 256 bytes Registers amp FIFO s 256 bytes PCI Bridge 1 MByte 512 bytes reserved TOTAL
34. istetsu Dv Kini e rs dt A an RAA 31 13 1 2 2 Local Contiguration Registers a E a A a 32 13 1 3 CRED Ser 55 ease e E ns is se 32 13 1 3 1 Contisuration SEguen in Di A iii pt A a cies Cth St PASC ANA va Si aa 32 13 1 3 2 Serial Configuration Interface comia eee hee Ad nd 32 13 1 4 GA de id ta o id Wena Nee 35 13 1 4 1 SS a e da rebis 35 13 1 4 2 DPRAM Interfac i ist idet ish a es tl ba b dh te a e aie 35 13 1 4 3 REGISTETS 24 i et ip A dd T R da UA N tet 35 13 1 4 4 Trigger and Buffer Mana Medi cats ols cave add shales As dr Sharr sod 38 13 1 4 5 Event Counters and Event FIFO ui het g an i ib bi Subs ed ob cake dt de ne 38 13 2 EPLP EONFIGURATION esa deve Gai der de d ri 39 13 2 1 Batti idownload CAD A e E dendi 39 13 3 EPGA READBACR en pr e e ve nisuadeeeds 39 13 4 BOARD SETUP esse ph e ud dare dd ia 39 13 4 1 PET 9080 coni guration is sissa vs a p be 39 13 4 2 EPGACONTIZUTA TONA sive vedi di dt t 39 13 4 2 1 POL PACO dendi bi e ne n nt ne ser 39 13 4 2 2 Flash EEPROM unida atados 39 13 5 BOARD OPERATION a dh re don 40 13 5 1 BOOEUD it AR A NS AR A ka E ERE 40 13 5 2 RURTIME da se 40 14 APV HEADER FINDING MODE 1 an s vereni n s n das series ass d mi ke fa dd 40 15 DEBUGGING TOOLS ia i ard sh e e d 41 16 WEB SERVER A A wie nd ois We Whi wwe ded n Slee da Need Sew oon peewee 41 17 TROUBLE SHOOTING ia i i er de n t r dine lars sible de nde ndi rn 41 17 1 LED DOES NOT COME ON AT POWER ON LEAP KEEP
35. its upgrades to the firmware to be transparently implemented The firmware contains a version identifier permitting the software to recognise the design currently installed and operate accordingly 1 GUI l Future Extensions Network Layer 1 Calling Sequence A Network Layer 1 Entry Level User ri GUI High Level Vis Programmer gt C Librarv Low Level Vls Low Level C Primitives Expert Platform Dependent Primitives BErr Block Move l Front End Driver PMC Figure 6 Layered Software Design The software is implemented by a comprehensive library of open source C routines which allow for all aspects of card configuration and readout operation This allows the FED PMC to be integrated into a custom system without first having to understand all the aspects of the hardware The software assumes the FED PMC is memory mapped onto the host processor s address space A high level graphical user interface for the FED PMC implemented using LabView has also been developed for the test bench at RAL Version 4 0 17 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 10 1 Source Files All the necessary source and header files are available from the web server All files are written in ANSI C Header files fedpmc_defs h routine declarations fedpmc h register definitions fedpmc_xilinx h FPGA definitions
36. l compatibility with the CMS TTC system The Bunch Crossing Counter counts clock cycles the Event Number Counter counts triggers On detection of a trigger both counters a copied to a temporary register a few clock cycles later the counters are copied into the Event FIFO when the trigger is qualified Trigger qualification is necessary when header detection is implemented so as to ensure that the whole digital header from the APV6 is captured In addition to the two counters a pointer to the buffer in which the current event is being stored is also copied to the FIFO The FIFO is 9 bits wide data is copied bytewise into the 8 least significant bits The order of the data copied is as follows Write Buffer Number 15 8 Write Buffer Number 7 0 Event Number 15 8 Event Number 7 0 Bunch Crossing Number 15 8 Bunch Crossing Number 7 0 For the first five bytes the MSB of the FIFO data is written 0 for the last the MSB is written 1 The interface between the Read port of the FIFO and the internal bus is 32 bits wide The FIFO is located at address LASBIR offset it is a non prefetchable read only resource attempted writes to this address will be ignored The structure of the 32 bit word read is given 0 If set FIFO is empty and data on bits If set FIFO is nearly Data 15 0 is invalid empty Table 14 FIFO Contents A read of the bunch crossing number causes the buffer in which the data to which the bunch
37. ll do is grant bus mastership unconditionally to the PCI 9080 Various address lines are latched internally for memory access and resource decoding control signals are latched on input and relayed to the various internal interfaces for modularity The slave state machine controls the READVif output to the PCI 9080 indicating that data written by the PCI 9080 to the FPGA has been latched successfully and that data read from the FPGA by the PCI 9080 is valid Each internal interface to the i960 bus has its own connection to this state machine thus facilitating the addition of extra internal interfaces without the necessity for significant redesign of existing ones 13 1 4 2 DPRAM Interface The DPRAM interface provides a highly pipelined interface from the 32 bit internal data bus to a 72 bit memory port divided into four blocks of 18 bits The DPRAM interface is a longyvord only port byte and halfword accesses to DPRAM will produce undefined results Only bits 8 0 and 24 16 of the internal data bus are mapped onto memory bits in other locations will be ignored during a write to DPRAM a read returns all zeros on unimplemented bits Mapping of the internal bus onto the memory port is as follows E EL S pa gt EUA CU EC pesedbe 30 w s pa as e 30 gt est Pl 24 16 71 63 Table 12 DPM Address Map 13 1 4 3 Registers The FED incorporates the following registers which are mapped with a granularity of one byte LASIBA B
38. ne access NB The mechanisms for accessing PCI configuration space are carrier dependent 2 Configure the PCI bridge fedpmc config bridge This step sets up various options for access to FED PMC register space 3 Load the FPGA The FPGA is loaded from the firmware file permanentiv stored in Flash EEPROM Itis only necessary to load the FPGA once after power up i e contents are not lost after PCI reset The loading takes about 5 seconds so poll on the FPGA status until it s readv Once the FPGA is correctly loaded the LED which came on at Power up will go OFF if fedpmc status fpga 0 FPGA is already loaded else fedpmc config fpga start load of FPGA do timer while fedpmc status fpga 0 amp amp timer lt 10 secs Version 4 0 26 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 if timer gt 10 secs error loading FPGA l reset PMC and try again 4 After the FPGA is loaded we can access the internal registers of the FED E g we can now check the FED PMC configuration to verify that we have latest firmware and software fedpmc read serial number which card are we using fedpmc read xilinx version which firmware is loaded fedpmc read lib version which software is being used 4 Initialise the FED fedpmc init This step selects the running conditions of the FED i e selects clock amp trigger source number of A
39. nsure the external trigger is correctly set up Restart the run NB One common cause of overflow is caused by a missing external trigger If a run is started with external triggers selected and the external trigger is missing e g cable removed a large number of spurious triggers are received which immediately overflows the FED buffers 17 5 No software triggers Test mode must be enabled and a run must be on before software triggers can be generated 17 6 Same event is readout more than once On receipt of a trigger pulse a pre set number of samples S is digitised and stored in the DPM This storage operation takes S x clock periods to complete However if N further triggers arrive during the data storage period of the first trigger the data from these N later trigger will be LOST It will appear as if the data from the first trigger has been stored 1 N times in the DPM Vetoing subsequent triggers avoids this problem E g If sample size is 512 and clock frequency is 40 MHz then minimum separation of triggers should be approx 512x25 nsec 12 8 usec 17 7 No hardware triggers Check triggers arriving at front panel Test mode must be disabled and a run must be on before triggers can be received 17 8 The DPM is full of values like 256 257 or 0 If inputs are differential and no input is connected to a channel you should read half full scale i e 0 5 x 512 256 If inputs are single ended and no input is connected to a
40. ode a command which may be preceded by commands to configure the clock sources and delays 13 1 3 2 Serial Configuration Interface The serial configuration interface is designed to be used for clock source and delay configuration and for control of FPGA configuration It takes advantage of the fact that there are two output pins and one input pin on the PCI 9080 that are connected directly to a register The input pin is USERI the output pins are USERO and LRESETo the register to which they are connected is CNTRL at PCI address PCIBARO 6C Usage of LRESETo in this manner is justified as the software reset clears the Local Configuration and DMA registers leaving the PCI Configuration and Shared Runtime registers unaffected CNTRL 16 USERO corresponds to clock for the serial interface CNTRL 30 LRESETO corresponds to serial data out CNTRL 17 USERI to serial data in The commands available from this interface are as follows shifting LSB first 1 These registers must therefore be re initialised after each use of the serial interface Version 4 0 32 Feb 2000 CMS FED PMC User Manual DRAFT Code Function Isb 100 Write FPGA Configuration Header 101 Write FPGA Configuration Data 1 1 110 Write FPGA 16 i Centura footer register 3 010 Read Configuration register CMS FED PMC 004 2000 Write header portion of FPGA configuration bitstream to FPGA See Xilinx Data book for further details
41. on Possible reason is missing 3 3 V supply Verify that your carrier supplies 3 3 V If it DOESN T e g VMETRO MIDAS 20 If you have a Mk2 card remove the jumper PL1 If you have a Mkl card you cannot use it with this carrier without patching a 3 3 V supply 17 2 FED hangs after enabling external clock The FED circuitry relies on selected clock ALWAYS running Check that external clock is running 17 3 Event amp Bunch crossing counters don t reset for a new run The event counter counts triggers received during a run must be explicitly reset This can only be done DURING a run It is planned in later versions of the firmware to allow resets outside of runs too Version 4 0 41 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 17 4 Buffer overflows or number of filled buffers is not as expected The FED is designed to be readout in parallel with data capture If the readout stops there are 2 limits to the number of events that can be stored in the FED before it fills The DPM will overflow if the number of pending events exceeds the maximum permitted for a given sample size see Table 3 In this case old events will simply be overwritten in memory A FIFO which stores internal pointers to the event data will overflow after approx 680 events If the FIFO overflows the buffer management breaks down and the run must be stopped and restarted Recovery procedure Stop the run Purge the buffers E
42. p right of visible side of PMC when mounted On power up the LED should come ON If the LED fails to come on it is likely the PMC is not receiving the 3 3 V supply NB after the FPGA is loaded the LED goes OFF 6 2 Carrier Configurations The FED PMC is capable of being used on all standard VME PMC carrier boards At the time of writing it has been operated with the following Carrier OS configurations CES RIO2 RTPC PowerPC SBC running LynxOS or VxWorks Motorola MVME2600 series PowerPC SBC running LynxOS VMETRO MIDAS 20 Dumb Carrier Interphase 6200 Dumb Carrier ESD Caddy Dumb Carrier Refer to section 12 for examples of how to use these carriers with the FED PMC MIDAS 20 does not supply 3 3 V 3 Interphase 6200 does not supply 3 3 V Version 4 0 7 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 7 Introduction 7 1 General Description The FED PMC is an 8 channel ADC on a 32 bit at 33 MHz PCI Mezzanine Card 1 It represents the next generation FED following the earlier 9U VME prototype board 2 It incorporates on board data transfer and buffering circuitry and outputs data over PCI bus The Mk2 version of the card is described in this document Figure 2 Photograph showing both sides of the FED PMC Mk2 The choice of the PMC format which interfaces via the popular PCI bus allows the FED prototype to be used on a wide variety of commercial off the shelf VME carrier boards The FED PMC
43. s abs_pci_mem base 0x01000000 located in unused pci space on RIO2 RTPC Carrier 1 device number 0 unused This routine initialises the PCI bridge configuration registers It sets up the memory mapped base addresses for all subsequent routine calls It MUST be the first call after a reset of the card NB This is the ONLY routine which accesses PCI configuration space i e all other routines access PCI memory space only long fedpmc config bridge long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST return code 0 OK This routine completes the configuration of the PCI bridge local bridge registers It should be called immediately after fedpmc_config_memory Version 4 0 20 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 10 3 2 Initialisation long fedpmc status fpga long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST return code 0 FPGA IS alreadv Loaded 1 FPGA is NOT vet Loaded This routine returns the load status of the FPGA NB After loading the contents in FPGA are only lost again when power is turned OFF i e they are NOT lost after a Reset void fedpmc config fpga long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST This routine causes the firmware permanentiv stored in Flash EEPROM to be loaded into the FPGA The operation takes about 5 seconds The LED should go OFF
44. s all the memories as is the Y address bus both are generated by the FPGA Each memory has individual connections to the FPGA for enable X port write enable and pass through Y port output enable and write enable 13 1 2 PCI Bridge The PLX PCI 9080 PCI bridge has been chosen to simplify the design of the PCI interface 13 1 2 1 PCI Configuration Registers The PLX PCI 9080 incorporates a standard set of PCI configuration registers Please note that there is no serial EEPROM attached to the PCI Bridge on Mk1 or Mk2 PMCs Therefore the following registers must be explicitly programmed at each power on Registers that need programming and their required values are detailed in the table below Register PCI CFG Value Comments Name address PCIIDR 00 10B5 RAL is not currently a member of PCISIG and thus does not have a PCI Vendor ID The default Vendor ID 10B5 will be read PCICR 0007 Card needs to respond to PCI memory space accesses and needs eee e PCI master capability for DMA Base Address Register for PCI memory space accesses to PCI9080 Bridge local registers PCIBAR2 18 Base Address Register for PCI memory space accesses to FED DPRAM ae MUNDO PCIBAR3 The base addresses used by the FED User library routines are described in section 10 3 Base Address Register for PCI memory space accesses to FED Registers Table 4 PCI Bridge Configuration Registers Version 4 0 31 Feb 2000 C
45. stic bag with protection from electrostatic discharge It is recommended to observe ESD protections when handling the FED PMC and associated carrier boards The reference number printed on the card is PC3109M 1 amp PC3109M 2 for Mk1 amp Mk2 cards respectively A label showing the serial number should also be clearly visible Sufficient LEMO connectors for all front panel inputs are supplied with each card 6 1 Installation amp Jumper Settings The FED PMC Mk2 is capable of being plugged on to all standard VME PMC carrier boards Before placing the PMC on the carrier please check the following 2 static options 1 Jumper PL1 the single jumper If the VME carrier does NOT supply 3 3 V this jumper should be OFF in order to enable the onboard supply 2 Jumpers PL10 amp P111 If the VME carrier does NOT supply VCCIO both jumpers should be ON jumpers should be placed VERTICALLY see Figure 1 Figure 1 Jumpers PL10 amp PL11 NB If your FED PMC does NOT have these 3 jumpers then you have a Mk1 card see Appendix A MEUS Jumpers PIO PLT interphase 20 fo fox Table 1 Example Jumper settings for VME PMC carriers Version 4 0 6 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Table 1 shows some standard carrier configurations For other cases please refer to the documentation provided with your carrier The PMC is delivered with all 3 jumpers on The PMC has one indicator red LED location to
46. tus of the fed settings set up in fedpmc_init 1 adc_chan_mask returns contents of physical register and will NOT agree with value set in fedpmc_init void fedpmc enable test mode long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST This routine enables Test Mode This ENABLES software triggers and DISABLES External triggers void fedpmc software generate trigger long fedpmc base fedpmc base FED base address in PCI memory space as seen by HOST This routine generates a software trigger Test Mode must first be enabled and the digitisation run must be ON void fedpmc disable test mode long fedpmc base fedpmc base FED base address in PCI memorv space as seen bv HOST 9 adc samples parameter should be adjusted accordingly Version 4 0 24 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 This routine disables Test Mode void fedpmc_read_serial_number long fedpmc_base long serial number fedpmc base FED base address in PCI memorv space as seen bv HOST serial number Returns hardware serial number gt 1 Undefined This routine returns the PMC serial number stored in Flash EEPROM Value should agree with label on PMC Please note that some of the first PMC s delivered did not have this information stored void fedpmc read xilinx version long fedpmc base long xilinx version long xilinx revision long xilinx prototype f
47. us buffers Note The data from the 8 ADC channels of each sample are interleaved Therefore it is NOT possible to suppress the readout from individual ADC channels The format of an event with 512 samples in the DPM is shown in Figure 5 9 9 Firmware The contents of the FPGA are stored permanently in a Flash EEPROM The version of the firmware stored can be read back by software The FED PMC hardware serial number can also be read back Version 4 0 15 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Bit Sample 0000 0004 0008 e z 0010 0014 0018 2 001C 1FFO 1FF4 1FF8 mie 1FFC Next Event starts at 2000 DPM Address Figure 5 Event Format in DPM Version 4 0 16 Feb 2000 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 10 FED PMC Software The FPGA based open hardware architecture is complemented by the design of the software architecture which forms an integral part of the delivered FED PMC package The software design follows a layered approach from the lowest level drivers right up to a full graphical user interface A layered design Figure 6 has several advantages for the end user It abstracts the details of the hardware implementation At the simplest level a handful of routine calls are required for card configuration and readout operation It removes the need to rewrite code which has already been debugged in parallel with the hardware It perm
48. yte Register Comments byte offset enable oo FED CTRL AAA i ADC_CHAN CIRE SSCS 2 TRIG MODE AAA 3 SAMPLE_FREO AAA To TRIG TAROT TARESH SSCS BA Reserved D oo moms Write Only ET Tras PORT 2222222222 Version 4 0 35 Feb 2000 1 2 3 1 0 3 2 00 04 08 CMS FED PMC User Manual DRAFT CMS FED PMC 004 2000 Reeva p EVENT SIZE ee po y BA E A 0c fro po SBA Reserved O oy n8 810 fro JBUFFEROOCC Read Only as a Sc fo FIRMWARE_VERSION Read Only Fixed at FPGA load time Table 13 FED Register Map FED CTRI LAS1BA 00 Field Description Read Write Reset gt Reserved ECU 5 TT EN Enables trigger throttling If this bit is set and the buffer occupancv register BUFFER OCC is greater than the value in TRIG THROT THRESH the trigger throttle output is asserted TEST EN Enables test mode If this bit is set TTC signals can be mimicked in software through register FED TEST If this bit is not set writing to FED TEST has no effect fire Bc ji CA es Yes FED_EN Enable FED Setting this bit enables digitisation Yes mode and prevents the modification of certain other registers ADC_CHAN_CTRL LASIBA 01 FED CTRLIOI must be clear to enable writing to this register Field Description Read Write Reset Value m robe core e e TRIG MODE LAS1BA 02 FED CTRLIOI must be clear to enable writing to this register Field Description Read
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