WEBENCH Altium Connector User`s Manual
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1. Yes e Ignore Error Flag No Yes e Ignore Sync Pin No Yes e Ignore Vout2 0 v lout2 0 A Vout 3 0 V lout3 0 A Coupon Code Show Recommended Power Management ICs Show Al Switching Regulators Linear Regulators Site Map About Cookies See Dur Disclaimer Privacy Security Statement Contact Us Feedback RSS Feed Site Terms amp Conditions of Use Subscribe to our newsletter Copyright 1995 2014 Texas Instruments Incorporated All rights reserved System Design Compiler Instruments Shortcuts gt e e Netlist for the project HIDXP File Edit View Project Place e Netlist for the document WEBENCH Simulation Engine Menus amp Browse Library 4 Add Remove Library Make Schematic Library Make Integrated Library Project Templates General Templates Configuration Templates gt Set Template from Vault Update Current Template Remove Current Template Design Tools WEBENCH Simulator Reports Window Help Create Sheet Symbol From Sheet or HDL Create Component From Sheet Rename Child Sheet Synchronize Sheet Entries and Ports RAD Netlist For Document gt Verilog File Simulate gt VHDL File Create Sheet From Sheet Symbol Create HDL File From Sheet Symbol gt XSpice Document Options B Browse Library 4 Add Remove Library Netlist For Document gt Make Schematic Library Ma2. and want to maintain the same LTE tolerance you will also need to decrease LTERATIO MAXITERS WBSE usually takes less than 3 iterations to converge at any time point gt 0 If MAXITERS iterations are reached without convergence at any time point the time step size will be reduced and convergence attempted again at an earlier time point In other words the transient analysis backs up Backups due to reaching this iteration limit usually indicates other problems in the circuit or models MAX_LIMITING_ITERS Maximum iteration allowed during transient with devices enter limiting mode default value is 200 UIC This parameter tells WBSE to bypass the traditional initial transient convergence flow and just use the provided Initial Conditions as the time 0 solution The IT values if specified are ignored If not used carefully UIC can cause serious non convergence problems at the first time point of the transient analysis This is especially true if at the very first time point voltages in the circuit have sharp changes from zero or the initial conditions provided 15 Overview AC Analysis AC AC analysis An ac analysis determines the response of a linearized small signal model of your circuit to the frequency of ac sources in your circuit Typically in an ac analysis you sweep the frequency of the ac sources while your circuit is biased at the same operating point WBSE allows you to Sweep other variables as well in an ac
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4. analysis Prerequisites for AC analysis To perform an ac analysis there should be at least one independent ac source in the circuit If there are multiple ac sources WBSE will write a warning but continue the simulation The effect will be a superposition of all the ac sources in the circuit 16 AC Analysis Parameters POINTS Number of points through the AC sweep Definition depends on TYPE of SWEEP SWEEP TYPE Types of Sweep LINEAR Linear Size will be stop start points 1 DECADE Logarithmic by octaves Points specified are per decade OCTAVE Logarithmic by decades points specified are per octave START FREQ Start value of frequency sweep STOP FREQ Stop value of frequency sweep 17 Overview DC Analysis DC DC analysis A dc analysis determines a series of dc solutions of the circuit while one or more circuit variables are swept Originally as the name implies this analysis was designed to sweep the dc value of an independent voltage or current source and watch the circuit response WBSE computes the dc solution at the first point of the sweep variable s starting from zero or the specified initial conditions All subsequent points of the sweeps are solved by taking the previous solution as the initial guess The assumption here is that the step size of the sweep is small and so the solution will change very slightly Two situations invalidate this assumption First is the case of nested s
5. computed first Next WBSE performs iterations to propagate the dc values of all independent sources in the circuit to all other nodes and devices in the circuit Iterations continue until a steady state is achieved In the steady state voltage on nodes charge on capacitors flux in inductors and currents through resistors become constants DC domain analyses include OP operating point analysis DC dc transfer curve analysis Time domain In time domain WBSE first computes the time 0 steady state solution Then time is increased and the value of time varying independent sources change As a result node voltages change capacitors charge or discharge and currents through devices change WBSE takes appropriately small time steps and re computes the stable state This process is repeated until the end of the time domain simulation Time domain analysis includes TRAN transient analysis Small Signal Frequency domain These analyses work on a stable operating point of the circuit At the operating point WBSE generates the linearized small signal model of the circuit In small signal frequency domain the circuit s behavior is analyzed at different real or complex frequencies Frequency domain analyses include AC ac analysis The operating point for small signal analyses can either be a stable dc solution where all independent sources are set to their dc values or it can be a converged time point solution during a
6. from Altium Designer using this extension and optimize your design You can export that design from WEBENCH to Altium and then simulate offline in Altium You can simulate any circuit using fast WEBENCH Simulation Engine integrated in Altium This manual will take you through the steps on how to use WEBENCH O Altium Connector Menus and Toolbar WEBENCH Altium Connector Menus and Toolbar e Anew WEBENCH menu in menubar will appear H DXP File Edit View Project Place Design Tools WEBENCH Simulator Reports Window Help WEBENCH Designer WEBENCH Power Architect WEBENCH LED Architect TI E2E Help Central Open WEBENCH Design v WEBENCH Altium Connector User Guide Cee e You can click on any of the WEBENCH Design Tools to launch it from Altium e g WEBENCH Designer ai xP File View Project Window Help ing emuwu amp WEBENCH Designer Release Date Fri Jan 10 16 48 56 2014 971610 bytes i3 Texas INSTRUMENTS My Designs Projects BAS Bh MPR Z0 Pycciatit H3bik Portugu s Deutsch Simplified View Welcome Guest 7 seuesgqn pueogdi saquoAey New Solutions Visualizer Assistant ENTER REQUIREMENTS Power LED LEDArchitect Power Architect FPGAJgP HotSwap Simple Switcher Filters Basic Selection pe Cac Vin Min v VinMax 22 V Voutt 33 V luti 2 A Op Ambient Temp Choose Additional Features Optional Show Alternate Topologies e Show Only Modules On Off Pin No
7. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing Address Texas Instruments Post Office Box 655303
8. H Design Center in TI E2E forum from WEBENCH Menu 10 WEBENCH Simulation Engine Reference Guide Introduction to WBSE WEBENCH Simulation Engine WBSE is a general purpose circuit simulation program that analyzes electronic circuits using direct method circuit simulation techniques These techniques provide precise waveforms for voltages currents and charges in the circuit WBSE simulates circuits containing a range of devices including Resistors Capacitors Inductors and mutual inductance A variety of independent and dependent voltage and current sources Lossy and lossless transmission lines Range of non linear devices include Bipolar junction transistors Junction field effect transistors MOS field effect transistors WBSE uses built in models for these non linear semiconductor devices and you need to specify only the pertinent model parameters WBSE requires at least one file as input The input file should contain the circuit description in the form of a netlist of primitive circuit components the models used for all non linear devices in the circuit the analyses that need to be performed on the circuit the options to be used for the analyses and finally the outputs that need to be saved 11 Overview Overview Analyses performed by WEBENCH Simulation Engine WBSE can be grouped into 3 domains DC domain These analyses compute the stable dc state of the circuit All device parameters are
9. I3 TEXAS INSTRUMENTS WEBENCH Altium Connector User s Manual SZZU007A Version 1 1 April 7 2014 WEBENCH Design Center Copyright 2013 2014 Texas Instruments Incorporated Contents VEPOCUIGUIOMN RE C cen oS cen eh Sey oe salen ce de a cae ce de ces eee ce eee 3 Men s and Toolbar ccc reote taser ener eet ever eneee etat tentet eee Setene tenete Setet ESEE 4 WEBENCH Altium Connector Menus and Toolbar ccccccccceeeeeeeeeeeeeeeeeees 4 Using WEBENCH Simulation Engine e 7 Installing License for WEBENCH Simulation Engine 7 Running WEBENCH Simulation Engine e 8 WBSE Model EnGCrypllons nocte orti thee eoe EH Lehre EE het hee Hehe three Eres 9 DUD OM qu SEM JUS correr PEOR AEA EN REE e TUE 9 WEBENCH Simulation Engine Reference Guide ssssss 11 Introduction WEBENCH Design Environments from Texas Instruments are unique and powerful software tools that deliver customized power lighting filtering clocking and sensing designs in seconds These easy to use tools help you generate optimize and simulate designs that conform to your unique specifications They allow you to make value based tradeoffs at a design system and supply chain level before your design is committed to production WEBENCHO Altium Connector is an interface to online WEBENCH Design Center as well as offline WEBENCH Simulation Engine WBSE You can access WEBENCH
10. Parameters V Advanced Options Available Signals Active Signals V V3itbranch yap e WEBENCH O Simulation Engine Toolbar e Mapping of toolbar icons to the function is shown in below figure WEBENCH Simulation Engine Toolbar Y ER I Run WEBENCH Simulation Engine a a View Log File Setup Webench Simulation Engine View Log File Generate WEBENCH Netlist Using WEBENCH Simulation Engine Installing License for WEBENCH Simulation Engine e When you run the WEBENCH simulation engine for first time on a design it will ask for a node license e Attach the logfile showing the WBSE license not found and send an email to wbse ti com for a license This file is needed for generating a WEBENCH Simulation Engine license e Once license is received rename the license file as node_license if not already done and place it in lt WEBENCH Extension Installation Directory gt WBSE e Usually you will find it in c ProgramData Altium Altium Designer 2F259E6B E4FF 4EB4 9ABC 063D5507D841 Extensions WEBENCH WBSE node_license e You are ready to use the WEBENCH Simulation Engine Note The received license file may have some extension associated with it The license file must be renamed to node license removing any extension if present Running WEBENCH Simulation Engine 1 To simulate a design in WEBENCH Simulation Engine go to Design gt Simulate gt WEBENCH Simulation Engine or yo
11. ce e Current controlled voltage source e Diode e Independent current source e Independent voltage source e Inductor e Mutual Inductor e Junction FET e MOSFET e Resistor e Subcircuit instantiation e Transmission line e Voltage controlled switch IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed TI assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using Tl components To minimize th
12. e risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Buy
13. eneration At 6 09 11 PM 1 24 2014 2 2 S 7 E Gro Outp Name WEBENCH Simulation Engine Ty 1 24 2014 3 54 TLV70715 TRANSIENT SIMULATION g E Hi PAGELSch WBSE XU1 Model found in C ProgramData m 1 24 2014 4 E Hi PAGEL Sch WBSE Model found in C ProgramData Altium 6 1 m 1 24 2014 5 F E Hi PAGEL Sch WBSE Model TLV70715 not found in file CAPro 1 24 2014 6 g Gt utp TLV70715 nti 1 24 2014 7 Li ri Outp Finished Output Generation At 6 09 11 P 1 24 2014 8 Gon TLV70715 tis WESE Connecting to WBSE 1 24 2014 9 E pn TLV70715 tis WBSE Parsing netlists 1 24 2014 10 fn TLV70715 tis WBSE Walking AST m 1 24 2014 11 T an oV z ii In TLV70715 tis WBSE Checking Analyses 1 24 2014 12 p F E fn TLV70715 tis WBSE Expanding circuit 1 24 2014 13 k E 1 pn TLV70715 tis WESE Setting up simulation 1 24 2014 14 GB In TLV70715 tis WBSE Running simulation m 1 24 2014 15 E fn TLV70715 tis WBSE Simulation Completed Successfully 6 09 15 1 24 2014 16 Editor PAGEL 2 VY Mask Level Clear m E V vin d gt 2 0 400m 0 600m 0 800m 1 000m time 2000 1750 E _ l vou z 1500 Sg 1250 5 1 000 EA 0 750 0500 0250 E ooo tit 0 000m 0 200m 0 400m 0 600m 0 800m 1 000m time Projects Messages WBSE Transient Analysis Mask Level Clear X 5 in Y 5 2in Grid 0 1in ystem Design Com
14. er acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitate safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments
15. ill make WBSE take bigger time steps This will finish the transient simulation sooner at the cost of inaccuracies in the results Tighter error tolerances will keep the time steps smaller The results will then be more accurate at the cost of longer run times 13 Transient Analysis Parameters Simulation Time amp Interval Parameters TSTEP Defines the time step size for fixed time step controlling methods It may also be used as default values of some parameters on some independent sources An example is the rise time of a pulse source TSTART If the waveform output of a transient analysis is not interesting from time 0 to a certain time value the size of the waveform files written by WBSE can be reduced by setting TSTART to the time value from which you want to see the waveforms This does not save simulation time because the transient analysis always starts from time 0 TSTOP Stop time value at which transient analysis stops TMAX For variable time step methods step size can become large if there is no activity in the circuit Specifying TMAX will not allow WBSE to take a step size larger than that value The default 1 20 of TSTOP can be too large for oscillator circuits For accurate results on such circuits be sure to set TMAX to no more than 1 20t of the period of oscillation TRES Certain devices can cause discontinuous events at their output during a transient analysis Discontinuous events include instantaneous switch
16. ing PWL and math expression types of controlled sources can exhibit such behavior Truncation error becomes large when this happens and it can make WBSE take very small time steps Reducing time step to TMIN to locate the exact corner and recovering to larger time steps can be inefficient TRES allows you to set a higher threshold than TMIN to resolve such transitions Usually TRES is significantly larger than TMIN Accuracy amp Convergence Parameters LTERATIO Local truncation error LTE is the error in integration over time This represents the difference between the computed solution and the predicted solution derived from an extrapolation of the solutions at the previous few time points LTE needs to be controlled in a transient analysis to avoid inaccuracies in results due to very large time steps Tolerance for LTE or Tolerance te is defined as a constant multiple of Tolerance NR 14 LTERATIO Tolerance LTE Tolerance NR RELTOL and ABSTOL parameters control the accuracy of the solution to within the specified tolerance at any given time This tolerance is called the Newton Raphson tolerance or Tolerancenr It is defined by the equation ToleranceNR ABSTOL RELTOL x REF In other words LTERATIO is defined as To reduce LTE while keeping error tolerance for voltages and currents the same you can make LTERATIO smaller To reduce them both you can make RELTOL and or ABSTOL smaller If you make RELTOL and or ABSTOL larger
17. ke Integrated Library Project Templates General Templates Configuration Templates Set Template from Vault Update Current Template Remove Current Template DXP File Edit View Project Place Design Tools WEBENCH Simulator Reports Window Help Netlist For Project Simulate gt Create Sheet From Sheet Symbol Create HDL File From Sheet Symbol PCAD Verilog File VHDL File WEBENCH Simulation Engine XSpice Create Sheet Symbol From Sheet or HDL Create Component From Sheet Rename Child Sheet Synchronize Sheet Entries and Ports Document Options e Simulate H DXP File Edit View Project Place Design Tools WEBENCH Simulator Reports Window Help amp Browse Library Add Remove Library Make Schematic Library Make Integrated Library Project Templates General Templates gt Configuration Templates gt Set Template from Vault Update Current Template Remove Current Template Netlist For Project Netlist For Document Mixed Sim Create Sheet From Sheet Symbol Create HDL File From Sheet Symbol Create Sheet Symbol From Sheet or HDL Create Component From Sheet Rename Child Sheet Synchronize Sheet Entries and Ports Document Options e WBSE Analyses Setup J General Setup V Transient Analysis Seis p RBS E DC Sweep Analysis SimView Setup E AC Small Signal Analysis 7 Global
18. n xml am m m E m C N Ny i v e om Tt dt A Back New Solutions Visualizer BOM harts Schematic Optimize OpVals Sim Edit MEBENCHO Export Optimization Tuning Schematic Board Layout BETA Lowest Q Altium Designer Altium Designer BOM Cost O Cadence OrCAD Capture CIS Cadence Allegro 16 0 16 5 Smalles Highest Mentor Graphics Xpedition xDX Designer D CadSoft Eagle PCB v6 4 or newer pnr Efficiency P gt CadSoft Eagle Schematic Capture v6 4 or newer Design Spark Footprint BOMCost Efficiency Qo CAD qj Meetor rapi cs PADS HCE so 141 91 DesignSpark Advanced Options Soft Start Time ms Simulation Export 0 135ms lt 0 135 ms lt 100r e Altium Designer Tina TI CAD export completed successfully 144 s Click Download to proceed Name TPS62130RGTR 3 3V 6 0V to Open the design in Altium using Open WEBENCH Design from WEBENCH menu bar You can simulate design using WEBENCH Simulation Engine l I s TPS62130 Transient Simulation Exported from WEBENCH Designer Ea WEBENCH Design Center Tile TPS62139 Startup Transient Simulation WEBE WEBENCH De Date of WEBENCH Export Time of WEBENCH Export 772014 eed PM Support For reporting bugs or any other help regarding WEBENCH Altium Connector please post your queries to WEBENC
19. or RELTOL is the relative error component RELTOL Default 1e 3 Relative error tolerance VABSTOL Default 1e 6 Absolute voltage error tolerance IABSTOL Default 1e 9 Absolute current error tolerance GMIN Default 1e 12 mhos This option sets the minimum conductance value allowed for any of the elements in your circuit A gmin conductance between a pair of nodes in the circuit is nearly an open circuit The current through this conductance should be several orders of magnitude smaller than other currents through those nodes Generally a gmin conductance should not change your simulation results If there are real conductances in your circuit that are close to gmin you can reduce the value of this option 20 Model Convergence Options CHECK_DCMAX Default true If set to false this option turns off the checking of currents and voltages at a de operating point against the values of CURMAX Default 1 amp and VOLTMAX Default 1 amp options TRAN_LIMITING Default false Enable device limiting during the transient critical for behavior model or control source with abrupt transitions OPTSTEP Default off Enable TI proprietary optimal time stepping algorithm still in beta 21 Supported Devices List of devices that are supported by WEBENCH Simulation Engine e Bipolar Junction transistor e Capacitor e Voltage controlled voltage source e Voltage controlled current source e Current controlled current sour
20. piler SCH Instruments Shortcut WBSE Model Encryption e WBSE Encrypted Library for the component is supported e The above example is provided with your installation of this extension and can be found in lt WEBENCH Extension Installation Dir WBSEYExamples directory of your system The example uses WBSE encrypted model Exporting Design from WEBENCH Designer In order to export a design first open a design in WEBENCH e g TPS62130 je a Exjetm c 53 le e J Back New Solutions Visualizer BOM Charts Schematic Optimize Op Vals Sim Edit Export Print Share Design Assistant SCHEMATIC 4s 15 2 20 uH VinMin 3 3 V 47 0 mOhm VinMax 6V Rload Click on CAD export button and choose Altium Designer in Simulation Export panel else ENERO ET WEBENCH Export Schematic Board Layout BETA i Altium Designer Altium Designer ha Cadence OrCAD Capture CIS J Cadence Allegro 16 0 16 5 Mentor Graphics Xpedition xDX Designer CadSoft Eagle PCB v6 4 or newer CAD Expo rt Cad Soft Eagle Schematic Capture v6 4 or newer Design Spark gt P CAD Mentor Graphics PADS PCB Design Spark Simulation Export Altium Designer J Tina TI Export Cancel 4 Click on Export to download simulation export file On successful completion of export process Q click on download file and save the simulatio
21. transient analysis where all time varying independent sources are set to their time values 12 Overview Transient Analysis TRAN Transient analysis A transient analysis performs a time domain analysis of your circuit over a specified time interval Before starting the transient analysis WBSE computes the operating point of the circuit using the time 0 values of all independent sources that have a time function Other independent sources get their dc values at time 0 This is an operating point analysis that results in an initial transient solution of the circuit After the time 0 solution is obtained WBSE starts to increment time in steps The voltages of all time dependent sources are updated Capacitive components in the circuit are allowed to charge and discharge and flux through inductors is allowed to change Currents through devices can change WBSE recomputes the solution of the circuit at the new time point It does so by starting from the previous timepoint solution The process repeats until time reaches the specified stop time for the transient analysis Time stepping WBSE can take a fixed time step for the entire transient analysis More commonly WBSE computes a new time step size at every time point The step size is based on circuit characteristics and the rate of change of voltages and currents in the circuit Accuracy Accuracy parameter settings also determine the time step size Loser error tolerance settings w
22. u click on Run toolbar button 2 It will open simulation settings UI Analysis setup window contains mainly of three parts 1 Enable Analysis Options These options allow to enable disable the required analysis Currently AC DC and Transient simulations are available Global parameters and advanced options can also be edited here 2 Data Collection Viewing and Netlisting These options enable user to control netlisting data saving and Sim View setup options 3 Signal Selection The active signals can be selected from a list of available signals Active signals are plotted when the simulation is running 3 If you want to make changes to the settings click on respective analysis name on the left pane and edit the options 4 If you want to specify some simulation parameter it can be defined in the Global Parameter options 5 The project is ready for simulation Click on OK to run simulation It will start simulation and a plot window will be opened A Eee a Hox File Edit View Project Place Design Tools WEBENCH Simulator Reports Window Help CAProgramDataVltiumMAltium De er yanm i 2 1 9o9 8W BREA IERI FICER E Fey xf gt dix doce LC o dE DEP i omBoX OX F No Variations B Messages X 2 PAGELSchDoc 7 Class Document Source Message Date N g E fn TLV70715 Comp Compile successful no errors found m 1 24 2014 1 Gist utp Start Output G
23. weeps when the inner loop variable switches back to its starting value while the outer loop variable takes the next step The second case is when the circuit switches states very abruptly due to high gains of some circuit components Default iteration count limits and step sizes can be adjusted to solve non convergence problems that such situations can cause 18 DC Analysis Parameters POINTS Number of points through the DC sweep Definition depends on TYPE of SWEEP SWEEP TYPE Types of Sweep LINEAR Linear Size will be stop start points 1 DECADE Logarithmic by octaves Points specified are per decade OCTAVE Logarithmic by decades points specified are per octave SWEEP VARIABLE Name of the variable to be swept START VALUE Start value of sweep variable STOP VALUE Stop value of sweep variable 19 Tolerance Parameters Tolerance parameters control the accuracy of a computed value while iterating to a converged solution In other words they limit the error to within the desired tolerance for accuracy These parameters are optional and can be specified on all of the analyses described above Accuracy parameters are described in the table below The equation that uses these parameters to compare two values Vali and Val of a variable is Val Val2 lt ABSTOL RELTOL x min Val1 Valz Here ABSTOL VABSTOL for voltages or IABSTOL for currents is the absolute error component of the err
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