SRS Slow Control Manual
Contents
1. ADDRESS IN HEX 015 D14 D13 012 D11 D10 D9 06 D5 D4 D3 D2 D1 DO NAME DESCRIPTION DEFAULT 00 X RST Self clearing software RESET Inactive lt 1 gt Channel specific ADC Inactive power down mode X PDN PARTIAL Partial power down mode fast inacive recovery from power down 0 X PDN COMPLETE Register mode for complete power down slower recovery X PDN PIN CFG Configures the PD pin for partial Complete power down mode power down LVDS current drive X X X ILVDS_LCLK lt 2 0 gt programmability for LCLKy and 3 5mA drive LCLKp pins LVDS current drive 11 X X mus programmability for ADCLKy and 3 5mA drive pins LVDS current drive X X X ILVDS DAT 2 0 programmability for OUTy and 3 5mA drive OUT pins Enables internal termination for Termination 5 disabled Programmable termination for Termination 2A BI disabled 2 1 X X X TERM FRAME Programmable termination for Termination 2 0 ADCLKy and ADCLKp buffers disabled Programmable termination for Termination 23 EXE TERM_DAT lt 2 0 gt and OUTe buffers disabled 14 XI xix xl xix LFNS CHeg Channel speciiic lowdrequency inactive noise suppression mode en2. ADCCARD REGISTERS ADCCARD 6519 35 3 0 ADCC CARDEADC SPLCONTROL 36 3 6 1 Extract of the TI 4055281 37 4 APPENDIX A SLOW_CONTROL LINUX 2 40 5 APPENDIX B SDC SCALABLE DETECTOR CONTROL SOFTWARE 1 41 List of tables TABLE L 5 at sams Canad ae 21 LABEE 2 pn ehe tu bitrate 23 SOV SEV REGISTER 24 TABLES APY APPLICATION REGIS 25 TABLE 5 APZ WITH ZERO SUPPRESSION CODE APPLICATION REGISTERS 26 TABLE MODE Bb MAP 27 TABLE ZSEVBED CHENABLE BITMAP sa ea edt R 28 TABLE 8 EVENT BUILDER MODES EVBLD MODE
3. See the User Manual for more information on the APV s readout modes and synchronisation sequence threshold for the zero suppression This register is only used when bit 4 threshold mode register APZ ZEROSUPP PRMS 15 0 Name Zero suppression threshold APZ ZEROSUPP THR Controls the threshold multiplier for signal detection The value is given Integer part of the threshold Fractional part of the threshold Table 12 APZ_ZEROSUPP_THR bitmap Description APZ_ZEROSUPP_PRMS address 0x15 Configuration register for the zero suppression unit Bitje 4 3 122 10 Disabl destal HE Threshold mode Force signal Mind ii in Peak find mode correction auto No channel is Pedestal value is Data is further reduced 1 2 2 suppressed All 128 forced to 0 for channels are acquired channels therefore peak sample its in APZ format uncorrected data is relative sample acquired position Table 13 APZ ZEROSUPP PRMS bit map by acquiring only the reserved reserved 3 3 Pedestal and pedestal sigma calibration memory APZ fw APZRAM PORT 6040 Subaddress LSB selector 0 15 This port allows read and write access to the calibration memory holding the values of the pedestal and pedestal variations sigma corresponding to each APV channel present in the zero suppression APZ firmware variant The calibration routines store the result
4. Slave 11 0 Example OxXXXXFFO3 gt all APVs OxXXXXFFOO gt all PLLs X anything hex internal Register address 2 LATENCY 5 4 value Default value address value hex Power on 32 One hot value Preamplifier current WN b00011001 28 D gt V LATENCY 0000010x MUXGAIN 0000011x PV IMUXIN 0010110x APV APV APV APV CSEL 0011101x Table 16 APV registers 200000100 V V APV APV V V APV QJ D QJ Output buffer pedestal gt 70 N e FR TR ITP TPIT TP i ITRP IRTP Iolo gt o In tr I e o N O ININININIBRINGEG gt O 2 ct Em 2 Calibration pulse strength O UJ Calibration channel mask Calibration fine phase 3 125ns One hot value b11101111 gt 0 lt lt 011110111 12C binary address This number is given only to facilitate the cross reference with the APV User Manual Recommended values for normal operation Users are encouraged to use the APV User Manual and other APV related literature for further reference See above Register Default Power address w hex Default value value value Description hex
5. Bit 3 0 CLK fine phase adjustment value lt 11 CSR1_FINEDELAY r w 01 b00100000 Bit 4 CLK phase flip Bit 5 enables access to TRG DELAY register 0 PLL TRG DELAY 00 Trigger delay clock cycles Table 17 Relevant PLL25 registers APV MODE register description see APV User Manual for more information Bitnumber Function Value 1 7 NetUsd 6 X NotUsed 4 Read out Frequency 20MHz 3 ReadoutMode Deconvolution Peak _ Calibration Inhibit OFF JON 0 AnalogueBias OFF LON Table 18 MODE bit Example 00011001 hex 19 gt 40 MHz peak mode 3 samples per trigger with calibration pulse test mode 00011101 hex 1D same without calibration pulse running mode For more information on the APV registers please refer to the APV User Manual 3 5 ADC C Card ADCCARD registers ADCCARD PORT 6519 Subaddress not used anything Address Byte T Power Description default KU EX on value Reset pin for each HDMI channel ide HYBRID EN low for the APV hybrid PWRDOWN CHO circuitry for the master path for x00 each HDMI channel Power down control of the analog PWRDOWN CH1 02 1 circuitry for the slave path for each x00 HDMI channel EQ LEVEL 0 03 1 Equalization control bit 0 for each x00 HDMI channel Equalization control bit 1 for each TRGOUT ENABLE 0
6. 1 0 0 0 1 0 0 1 1 0 1 0 10 1 0 1 1 11 1 1 0 0 124 1 1 0 1 Do not use 1 1 1 0 Do not use 1 1 1 1 Do not use Page 39 4 Appendix slow_control Linux program Usage control fa Lent xe Contents of file txt Destination FEC IP address re A Peripheral port number 6039 SC Request Frame Data in 4 byte hex format Request ID MSb 1 80000000 Subaddress 00000000 Command Write pairs AAAAF FEE Command info don t care for Write pairs 00000000 Register address 00000000 Data to be written 00000004 Register address 00000001 Data to be written 00000004 Page 40 5 Appendix SDC Scalable Detector Control software Refer to https twiki cern ch twiki bin view AtlasPublic SDC Page 41
7. 5 28 TABLES APZ CMD TABLE Ed ot ups OP issu ter ooot M 29 TABLE TOS APZ STATUS BITMAP cirera D 30 TABLE EL APZ STATUS DESCRIPTION SO RUE astro em amu Uu Se nu etna Qu Mele mun a eua En Uomo 30 TABLE S2 APZ ZEROSUPP aa eau ioo bed pron 31 TABLE L3 APZ ZEROSUPP PRIVIS BIT WIA ise sate uus Detto tv a a mi epu o Deos eeu tts Dr iti e euge 31 TABLE ADDRESS BIEMA P ui ru uie e Ei 32 TABLE LS APZRAM ADDRESS MAPPING INI En REPE PU 32 TABLE T5 APA REGISTERS inb ev a bras Dra tto a 33 TABLE LZ REEEVAN T PEEZ SIRE GS ME RS austin e Re ER ER Uh Cut ea 34 FABLE I5 MODE BITMAP 34 TABLETO AADC CARD REGISTERS auis iri pedbqiav A vade Quat Rep EN OE tes nude adeunt DNE 35 TABLE 20 CHANNEL MAPPING ON THE 2 ON THE ADC C CARD eese 36 1 Overview slow control of the SRS system is carried out using UDP over IP protocol on the available Gigabit Ethernet por
8. amp data pairs Write Burst Ox AA OxBB First address Followed by data fields to be written at to write to consecutive addresses starting with the address in CMD INFO field Read Burst OxBB OxBB First address Followed by dummy data fields The to be read peripheral will read data for as many consecutive registers as dummy fields are in the request mu 77 2 2 SCReply UDP The ID of the request we are a to 31 MSb 0 a identifier Request ID SubAddress Cmd Field 1 error code from the individual write read Field 2 generally O if command executed ok Error EK 4 Data reply from the individual write read Data read cmd data read from register write cmd data written to the register For I2C data is readback from the bus during transaction does not necessarily mean that the I2C register Data was written correctly Error Figure 4 SC Reply Format SC Reply fields e Request ID copy of the corresponding request ID MSb is set to SubAddress copy from the request CMDField 1 amp 2 copy from the request Error error code generated for the read write operation on the corresponding register syntax of this field depends on the peripheral Generally value of indicates no error For 2 peripherals for instance the acknowledge bits are shifted into this field Data data that has been written to the register write or data read from
9. does not reset for each event TS 3 byte timestamp tag attributed to each event 3 2 3 APV Processor and zero suppression APZ Register map for the APV zero suppression FW variant third revision beta release APZ CMD address Ox1F Command register for the processor Note This register was revised and moved from address 0 11 for the alpha release to Ox1F This register is used to trigger different calibration routines of the APZ processor Calibration commands are can be run on single channels identified by APZ APVSELECT register or on multiple channels enabled channels in EVBLD CHENABLE register Warning When phase calibration is run on multiple channels if both MASTER and SLAVE hybrids of the same HDMI slot are enabled in the EVBLD CHENABLE register the optimal phase for the MASTER hybrid will be overwritten by the one for the SLAVE this is due to the fact that the MASTER SLAVE pair shares a single PLL device Generally this does not pose a problem but it may lead to the situation when a faulty SLAVE can disturb the operation of both hybrids emen RUN ABORT Default run mode Any other can be aborted by writing O CAL PHASE SINGLE Calibrate phase single channel APZ APVSELECT 0x02 CAL PED SINGLE Calibrate pedestal and sigma single channel APZ APVSELECT CAL PULL SINGLE Calibrate both phase and pedestal land sigma values APZ APVSELECT single channel BYPASS Bypass oe proces
10. Access to the control registers of the APV Application UO UO e lt 3 1 System Registers 5 5 6007 Subaddress not used anything Address Byte tela eem VERSON o Firmware version Firmware version identifier Reserved si Reserved GAMACID 2 3 device identifierpt recap 4 tata 00000 6 2 00 reeves _ semos 2 sewcwweconvlrepse Reend mam A 4 4 n RSTREG ee FFFFOOO1 Warm init Table 3 System registers FPGAMAC VENDORID FPGAMAC _ID FPGA_IP local MAC and IP address of the FEC card The values are read from the EEPROM at startup Writing to this registers will have immediate effect but the FEC will revert to the EEPROM values after reboot Default IP address is 10 0 0 2 DAQPORT destination UDP port used by the FEC card to transmit DAQ frames Default is 6006 SCPORT UDP port used for slow control transactions If this value is changed all port numbers assigned to all peripherals will scale accordingly This port number is also used for the System Registers port Default is 6007 DAQ_IP the IP address the FEC will send DAQ data to Default is 10 0 0 3 SYS_RSTREG register used to send reset commands Setting bit 15 will reboot the FPGA Setting bit 0 will initiate a warm initialization of the card Upon warm init all registers will
11. of this calibration in this memory The values can be read or overwritten using this port Address The most significant bit of the address field is used as a sigma 1 pedestal 0 selector The lest significant byte of the address field contains the APV channel position in transmission order Bit 3 3 4 7 0 0 pedestal reserved APV channel number 1 sigma 0 127 Table 14 APZRAM address bit map The correspondence between the physical APV channel number and the transmission order is given by the following formula for more details see the APV User Manual Channel No 32 n MOD 4 8 INT n 4 31 16 Data Unsigned integer value for the pedestal or the sigma The effective number of bits in the data field is 12 Address Bescipion 002 0 00000000 Pedestal channel 0 0 00000001 Pedestal channel ord 1 0 00000002 Pedestal channel ord 2 0x0000007F Pedestal channel ord 127 Pedestals __ reserved S O 0 80000000 Pedestal variation sigma channel ord 0 0x80000001 Pedestal variation sigma channel ord 1 0 80000002 Pedestal variation sigma channel ord 2 0 8000007 Pedestal variation sigma channel 127 Table 15 APZRAM address mapping 3 4 Hybrid Registers 6263 Subaddress XX XX Chamelmak Device channel mapping RJ RJR R R R Reserved 0 Master APV 0 1
12. out raw data from channel APZ_APVSELECT 7 APZ_ENABLED APZ code enabled Reading out zero suppressed data 11 8 CALIB ALL CRT When Calibrate All command is active this field indicates the current channel being treated Indicates channels that were successfully calibrated by either calibrate all or calibrate single commands When channels are 31 16 APZ CHANNEL STATUS calibrated one by one the corresponding bit is updated each time calibrate single command is executed All bits are cleared by a APZ reset command Table 11 APZ STATUS description APZ APVSELECT address 0x12 Selects the APV for the pedestal calibration clock phase calibration calibrate single command and raw data monitoring in APZ bypass mode Valid range O 15 APZ NSAMPLES address 0x13 Tells the APV processor how many time samples to process for each trigger If set to O the register is set internally using the TRGBURST value using the n 1 x 3 formula The register is provided to allow the user to limit the acquisition to a specific number of time samples from the APV output stream Note Experimental use only use with care If the register is set toa higher number of samples than the APV the data processor may hang APZ ZEROSUPP THR address 0 14 Optional threshold register for the zero suppression operation The value of the register is multiplied with the sigma value of each channel and the result is used as
13. revert to default values i e System registers will be read from EEPROM Default practice with DATE is to define separate LAN network segments for each FEC card in the system therefore the IP addresses are set as follows FPGA_IP 10 0 x 2 10 0 x 3 where x is from 0 to the total number of FECs minus 1 3 2 Application Registers port 6039 Subaddress used anything c gt Address f default 5 6 Description hex g amp c APV TRIGGER CONTROL REGISTERS 0x04 Controls the trigger sequencer for the APV See controls how many time slots the APV chip is aoM cil ar BEES reading from its memory for each trigger a 40000 02 2 0x9C40 RW Period of the trigger sequencer 256 Delay between the external internal trigger and AE 0x100 128 Delay between the external internal trigger and Se 0x80 300 Delay between the external internal trigger and uen nenne 12 the start of data recording 1 0 debug info Status of the ADC deserialization 2 06 EVENTBUILD REGISTERS Channel enable mask for the data transmission EVBLD CHENABLE OxFFFF RW Even bits are masters and odd bits are slaves If bit is set corresponding channel is enabled EVBLD DATALENGTH 2500 RW Length of the data capture window Builder mode register default use frame of event counter 8 bit EVBLD MODE use frame of run counter 32 bit 2 05
14. the register read Error and Data fields are repeated for as many registers are read or written 2 3 SC Error pir Payload The ID of the request we are replying to 31 5 0 reply identifier Request ID Error code Figure 5 SC Error reply format Frame receiver errors fatal errors causing frame to be dropped bit 31 destination port unavailable bit 30 illegal source port 6007 default SC source port the value can be changed in the system port bit 29 buffer full bit 28 illegal length incomplete 32 bit word bit 27 illegal length 4 words bit 26 reply id error Frame decoder errors fatal errors causing frame to be dropped bit 19 command unrecognized bit 18 illformed command bit 16 checksum error Peripherals Table 2 List of available peripherals same grew ees dec type aspom mine ree System registers Dynamic control of SYS PORT 1777 6007 runtime reg IP address MAC address GbE parameters debug Access to the I2C line B Used to Access to the FEC I2C line A Used to FEC AI2C PORT 1788 6024 debug I2C read program the A C card EEPROM setup and access the monitoring devices voltage current temperature sequencer and event builder Access to the pedestal and sigma firmware p REC PLL registers 2 registers of the ADC CCARD power equalization ch reset clk enable runtime
15. these two power down modes through either the PDN PARTIAL or PDN COMPLETE bits respectively the PD pin itself can be configured as either a partial power down pin or a complete power down pin control For example if PIN 0 default when the PD pin is high the device enters complete power down mode However if PIN 1 when the PD pin is high the device enters partial power down mode LOW FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 07 06 05 D4 D3 D2 D1 DO NAME 14 X X X X X X lt 8 1 gt The low frequency noise suppression mode is specifically useful in applications where good noise performance is desired in the frequency band of OMHz to 1MHz around dc Setting this mode shifts the low frequency noise of the ADS528x to approximately f 2 thereby moving the noise floor around dc to a much lower value LFNS lt 8 1 gt enables this mode individually for each channel ANALOG INPUT INVERT ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 07 06 05 4 D3 D2 D1 DO NAME 24 X X X X X X INVERT lt 8 1 gt Normally the INp pin represents the positive analog input pin and represents the complementary negative input Setting the bits marked INVERT lt 8 1 gt individual control for each channel causes the inputs to b
16. 5 1 Enables TRGOUT buffer for each x00 HDMI channel BCLK ENABLE 1 Enables BCLK buffer for each HDMI channel Register Bit 7 s J2 a o Corresponding HDMI channel 4 5 6 7 0 1 2 3 Table 19 ADCCARD registers 3 6 ADC C Card ADC SPI control Subaddress X X R R R R R R Reserved ADC selector Reserved None invalid ADCO ch0 7 0 1 1 8 15 1 0 The two ADCs on the ADC C Card be controlled using the registers listed the ADC datasheet http www ti com lit ds symlink ads5281 pdf The interface to the ADCs is write only so data cannot be read Address Field the 8 bit register address corresponding to the ADC register see ADS5281 datasheet Data Field 16 bit data field Some of the ADC registers control the ADC channels independently The mapping between the ADC channel number as in the ADCs datasheet and the system channel as recorded by the system eg APV channel etc is as follows ADCO ADC1 ee 0 1 2 3 4 5 6 7 01 2 3 4 5 67 system 7 e s 4 s 2 1 o 1s sm Corresponding Homi plug 3 3 2 2 1 1 o o 7 7 e e HDMI sub channel M S Table 20 Channel mapping the 2 ADC on the ADC C Card 3 6 1 Extract of the TI ADS5281 datasheet SERIAL REGISTER MAP SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE 2 3 4
17. Cards 1191 Identified by IPs Identified by UDP port number type 7 and sub address field location Figure 2 SRS slow control components All SC nodes on the network FECs and SC clients have an unique IP address and MAC address used to identify them using the Ethernet IP infrastructure SC peripherals behave like services residing on individual FEC cards They are therefore identified by 3 numbers 1 The UDP port number which identifies the type of peripheral eg System Registers ADC Card registers APV Hybrid etc 2 address of the FEC which hosts the individual peripheral 3 The sub address field part of the SC frame format see next chapter for details which identifies the location of the peripheral within the host FEC card The SC client can address a specific peripheral by sending SC requests either directly to the IP address of the FEC card which hosts the peripheral or using a broadcast address always using the UDP port assigned to the peripheral type If the FEC addressed either by an individual IP address or by a broadcast address does not host a peripheral identified by the specific UDP port address the action will have no consequences on the register space hosted by the specific FEC card By default the FEC card will reply with an error reply This behavior can be disabled to avoid unnecessary traffic 2 Slow control Format 2 1 SC Request UDP Payload Request reply mat
18. GAIN_CH8 lt 3 0 gt Programmable gain channel 8 gain 1 The unused bits in each register identified as blank table cells must be programmed as 0 2 X Register bit referenced by the corresponding name and description default is 0 3 Bits marked as should be forced to 0 and bits marked as 1 should be forced to 1 when the particular register is programmed 4 Multiple functions in a register should be programmed in a single write operation Registers in the shaded sections of the table should not be used POWER DOWN MODES ADDRESS IN HEX D15 D14 D13 012 Dii 0 D6 D5 D3 D1 DO NAME X X X X X X X X CH 8 1 X PDN PARTIAL E 0 X PDN COMPLETE X 0 PDN PIN CFG Each of the eight channels can be individually powered down PDN lt gt controls the power down mode for the ADC channel lt gt addition to channel specific power down the ADS528x also has two global power down modes partial power down mode and complete power down mode Partial power down mode partially powers down the chip recovery from this mode is much quicker provided that the clock has been running for at least 50 s before exiting this mode Complete power down mode on the other hand completely powers down the chip and involves a much longer recovery time In addition to programming the device for either of
19. SRS Slow Control Manual https espace cern ch rd51 wg5 srs Documentation SRS Slow Control Manual pdf Contents SRS SLOW CONTROL MANUAL 6556 Ya a EN 16 eng p 16 LST OF TABLES 255550 17 OVERVIEW 18 2 SEOWSCONTROLEORMA 20 NE MW OU 20 21 ESSI 22 3 PERIPHERALS E 23 3 1 SYSTEM REGISTERS SYS PORT 6007 cccccsseccccsecccccsecceenscsceecseessseeeessseuecsseueceseeueseneueseteuaceeeeness 24 3 2 APPLICATION REGISTERS PORT 6039 25 Jo APY TOT COn 5 27 222 28 3 2 3 APV Processor zero suppression 2 2 000000001200000000005500040000 nnne nnne nnns 29 3 3 PEDESTAL AND PEDESTAL SIGMA CALIBRATION MEMORY APZ Fw APZRAM_ PORT 6040 32 3 4 HYBRID REGISTERS APV_PORT 6263 cccccsccescnavaresnscscevavavenavareuaceusavacaravavaranaeusapacasavavaranauans 33 3 5 ADC
20. able Swaps the polarity of the analog pis 24 X X INVERT_CH lt 8 1 gt positive input pins electrically Input X 0 0 EN RAMP Enables a repeating full scale inactive ramp pattern on the outputs Enables the mode wherein the 0 X 0 output toggles between two Inactive PAT defined codes Enables the mode wherein the 0 0 X SL NG Ine output is a constant specified Inactive 25 _PAT code 2MSBs for a single custom Xx BITS CUSTOM pattern and for the first code of Insee 11 10 the dual custom pattern 11 is the MSB SUE BITS CUSTOM2 2MSBs for the second code of 11 10 the dual custom pattern 10 lower bits for the single BITS custom pattern and for the first 26 x 2 x A lt 9 0 gt code of the dual custom pattern 0 is the LSB 27 X X X X X X X X X X USE 10 lower bits for the second lt 9 0 gt code of the dual custom pattern X X X X GAIN_CH1 lt 3 0 gt Programmable gain channel 1 OdB gain n GAIN_CH2 lt 3 0 gt Programmable gain channel 2 OdB gain 2 X X X X GAIN CH3 3 0 Programmable gain channel OdB gain X X X X GAIN 4 lt 3 0 gt Programmable gain channel 4 OdB gain X X X X GAIN CH5 3 0 Programmable gain channel 5 OdB gain X X X X GAIN_CH6 lt 3 0 gt Programmable gain channel 6 OdB gain 2 X X X X GAIN CH7 3 0 Programmable gain channel 7 gain
21. ching mechanism MSb 1 request identifier 31 0 The reply will contain this ID Request ID ee ____ SubAddress Field 1 eee 0 cmd Field 7 Tewo sve Data CMD INFO Figure 3 SC request format Data SC Request fields Request ID The SC client has to set this field with a unique request identifier MSb must be set to 1 to signal a request valid values 0 80000000 OxFFFFFFFF The reply will contain the same Request ID with the MSb set to 0 SubAddress This field is used to identify the location of the peripheral to be programmed The syntax of this field is defined differently for each peripheral type port Peripherals without multiplicity will ignore this field CMD Field 1 This field determines the type of request read write etc See table below for details CMD Field 2 Additional data required by the CMD Field see below DATA fields For write commands these can be either an array of valid data to be written ina write burst or a succession of address and data fields for a write pairs command For read commands this fields contain either dummy data read burst or a list of addresses read list CMD FIELD 1 CMD TYPE CMD_LENGTH CMD FIELD 2 CMD INFO reserved Set to Table 1 SC commands Command CMD CMD CMD INFO Description TYPE Command is followed by address
22. e swapped IN now represents the positive input and INp the negative input PROGRAMMABLE GAIN ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 07 D6 D5 D4 D3 D2 D1 DO NAME GAIN 1 lt 3 0 gt X X X GAIN 2 lt 3 0 gt 2A X X X X GAIN CH3 3 0 X X X X GAIN 4 lt 3 0 gt X X X X GAIN 5 lt 3 0 gt X X X X GAIN 6 lt 3 0 gt 2B X X X X GAIN 7 lt 3 0 gt X X X X GAIN 8 lt 3 0 gt In applications where the full scale swing of the analog input signal is much less than the 2Vpp range supported by the ADS528x a programmable gain can be set to achieve the full scale output code even with a lower analog input swing The programmable gain not only fills the output code range of the ADC but also enhances the SNR of the device by utilizing quantization information from some extra Page 38 internal bits The programmable gain for each channel can be individually set using set of four bits indicated as GAIN CHN 3 0 for Channel The gain setting is coded in binary from OdB to 12dB as shown in Table 6 Table 6 Gain Setting for Channel 1 GAIN_CH1 lt 3 gt GAIN_CH1 lt 2 gt GAIN_CH1 lt 1 gt 1 lt 0 gt CHANNEL 1 GAIN SETTING 0 0 0 0 OdB 0 0 0 1 1dB 0 0 1 0 2dB 0 0 1 1 3dB 0 1 0 0 4dB 0 1 0 1 5dB 0 1 1 0 6dB 0 1 1 1
23. of the internal generated trigger BCLK TRGDELAY address 0x03 The FPGA delays the trigger for this number of clock cycles 25ns until propagating it to the chip When used with the APV25 front end ASIC the effective latency of the trigger is the difference between APV PORT APV LATENCY and APVAPP PORT BCLK TRGDELAY 3 2 2 Event builder registers EVBLD_CHENABLE address 0x08 Channel enable mask for the data transmission Even bits are masters and odd bits are slaves If bit is set corresponding channel is enabled Channel mapping Bit 15 a3 a2 11 10 9 8 7 6 5 4 32110 pHoMichannel 7 5 4 3 2 1 14 Table 7 EVBLD_CHENABLE bit EVBLD_DATALENGTH address 0x09 Length of the data capture window in words 16 bit in raw data ADC mode or bypass mode of the APZ code Maximum allowed value without exceeding the UDP jumbo frame limit is 4000 EVBLD_MODE address Event Builder mode register Controls the format of the FRAME COUNTER field of the SRS data format EVBLD_MODE FRAME COUNTER field value O 5 mode default e Multiple FECmode 15 Table 8 Event Builder modes EVBLD MODE register frame of event counter 1 byte starts from 0 for a new event and increases for every frame of the same event frame of run counter 4 byte global frame counter which starts from 0 at the beginning of the run and and counts continuously
24. rmware variant 3 2 1 Trigger control registers BCLK_MODE address 00 bit description Bit 74 2 1 20 Descr reserved TRGIN polarity TRIGGER mode APV Test Pulse APV Reset V 0 NIM Internally generated Test pulse disabled Disabled Default continuous loop for run mode V 1 Inverse NIM External Controlled by Test pulse enabled Enabled Used with TRGIN the test pulse Do not use in run mode Table 6 BCLK_MODE bit map Example 3 500000011 gt continuous loop with test pulse and reset test mode 4 500000100 gt triggered externally test pulse no reset running mode acquisition controlled by external trigger BCLK_TRGBURST address 0x01 controls how many time slots the APV chip is reading from its memory for each trigger The formula is n 1 x 3 Setting this to 4 means a number of 15 time slots The maximum is 30 time slots n 9 BCLK_FREQ address 0x02 PORT BCLK MODE TRIGGER MODE 1 When trigger source is set to external this parameter controls the deadtime introduced by the FPGA After accepting a trigger the FPGA will ignore all triggers incoming for Bclk freq x 64 x 25ns time 40000 means 1ms This time should not be lower than the total acquisition time of one event which is about 222 us with default parameters b APVAPP PORT BCLK MODE TRIGGER MODE When the trigger source is set to internal this parameter controls the repetition rate
25. sor Data is readout in raw format APZ APVSELECT from a single channel 0x10 CAL FULL ALL Calibrate all channels enabled by EVBLD CHENABLE full i g calibration Channels are treated sequentially current channel being treated is displayed in CALIB_ALL_CRT EVBLD CHENABLE field of APZ_STATUS register Return to run mode APZ_CMD 0 after this command is compulsory CAL_PHASE_ALL EVBLD_CHENABLE CAL_PED_ALL As above pedestal and sigma only EVBLD_CHENABLE ox RESET Table 9 2 table APZ SYNC DET address 0x10 Detects if front end ASIC is present at each ADC channel is correctly configured for 40MHz acquisition Each of the 16 bits of the register corresponds to channel with the same mapping as for the EVBLD CHENABLE register see Table 7 APZ STATUS address 0x11 status of the processor RESERVED APZ ENABLED BYPASS CMD DONE CALIB ALL DONE PHASE ALIGNED PEDCAL BUSY PHASECAL BUSY 5143210 jl lt 5 WATCHDOG_FLAG Table 10 APZ_STATUS bitmap 0 PHASECAL BUSY Clock phase calibration running __ _ 2 PHASE ALIGNED 7 calibration routine completed successfully 3 WATCHDOG FLAG Last pedestal calibration terminated by a watchdog reset 4 CALIB_ALL_DONE Calibrate All commandfinished o 5 CMDDONE Command finished 0 BYPASS Bypassing APZ code Reading
26. t of the FEC cards When using a SRU unit to bundle many FEC cards together the SRU will act as a packet switch forwarding the slow control frames to the FEC cards via the DTC links SC IP UDP Request Data forwarded to peripherals SC IP UDP Reply Error Figure 1 Overview of the SRS slow control flow The components of the slow control system are the slow control PC SC PC the network point to point connection network switch SRU the FEC card and the peripherals that need to be configured Peripherals can be either virtual devices usually residing in the FEC firmware or real hardware objects which are connected to the FEC FPGA located on the FEC card the A B C Module Card or on the front end hybrids Generally the real peripherals have a logic interface located in the FEC firmware which translates the slow control commands in the format that the external device understands The slow control protocol assures that from the user point of view the real or virtual attribute of a peripheral is transparent The slow control transactions use a request reply protocol between the SC PC and the peripherals The network and the FEC card guarantee the communication between the two In particular the FEC Card can filter out ill formed requests and issue error response packets The reply packets are generated by the peripheral logic and travel back to the IP address which generated the request Peripherals Slow control PCs Network FEC
27. use timestamp 24 bit and frame of event EVBLD EVENTINFOTYPE 1 0 RW Controls the data format EVBLD_EVENTINFODATA the optional info filed in the data RUN CONTROL Readout Enable register bit 0 Triggers are 2 01 ee o ow accepted for acquisition when this bit is 1 Reset register 2 02 Table 4 APV application registers Address hex Byte count APZ APZ REGITERS APZ SYNC DET Presence of the APV sync pulses on each channel Read only APZ APZ STATUS 00 Status of the APZ processor Read only APZ APVSELECT Ex dal Selects one APV channel for single channel commands Overrides the number of samples parameter If APZ NSAMPLES 13 1 RW set to O default the parameter is calculated internally from BCLK TRGBURST Zero suppression threshold APZ ZEROSUPP THR 14 2 RW Byte 0 fractional thr part 6 bits msb Byte 1 integer thr part 6 bits Isb Low threshold for the sync pulse detection APV_SYNC_LOWTHR 1D 2 RW If set to default the threshold is internally hard wired 1100 High threshold for the APV sync pulse detection APV_SYNC_HIGHTHR 1E 2 RW If set to 0 default the threshold is internally hard wired 3000 APZ CMD 1 of Rw Command register for the APZ processor Table 5 APZ APV with zero suppression code application registers These registers are only present in the Zero suppression APZ fi
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