6502 Kit User`s Manual - Build Your Own Microcontroller Projects
Contents
1. PO PD SO SO SO Page 28 of 282. PRINT TEXT FROM STRING ENTRY X POINTED TO OFFSET PSTRING LDA TEXT1 X CMP 0 BNE PRINT IT RTS PRINT IT JSR SEND BYTE INX JMP PSTRING CR EQU LF EQU EOS EQU 0 NEW LINE PRINT CR LF NEW LINE LDA 0DH JSR SEND_BYTE LDA 0AH JSR SEND_BYTE RTS WRITE NIBBLE TO TERMINAL OUT1X AND 0FH CLC ADC 30H 3AH OUT1X1 CLC ADC 7 OUT1X1 JSR SEND_BYTE RTS OUT2X PHA LSR A LSR A LSR A LSR A STA 1 JSR OUT1X PLA JSR OUT1X RTS INCREMENT HL INC INC HL CLC LDA HL ADC 41 STA HL LDA HL 1 ADC 0 STA HL 1 RTS PRINT LI OF MEMORY POINT PRINT LINE JSR NEW LINE LDA 16 STA REG C LDA HL 1 JSR OUT2X REA REMENT 16 BIT POINTER FOR 16 BIT MEMORY ACCESS ED TO HL Page 4 of 28 MONITOR LST 8 10 2015 6 21 PM 0305 0306 0307 0308 0309 031 031 031 031 031 031 031 031 031 0319 0320 0321 0322 0323 0324 0325 0326 0327 0328 0329 0330 0331 0332 0333 0334 0335 0336 0337 0338 0339 034 034 034 034 034 034 034 034 034 034 0350 0351 0352 0353 0354 0355 0356 0357 0358 0359 0360 0361 0362 0363 0364 0365 0366 0367 0368 0369 0370 0371 0372 0373 0374 0375 0376 0377 0378 0379 0380 C
3. 18 MONITOR PROGRAM LISTINGS eene 22 OVERVIEW The 6502 Microprocessor kit is a new design single board computer using the G65SC02 as a CPU This single board computer is a basic learning tool for programming the 6502 with low level instructions hex code The board has hex keypad and 7 segment display for entering the instruction hex code and test it directly Students will learn basic of the computer hardware and software of the 6502 easily The manual also provides monitor program listings the method to modify or write your own monitor program 6502 KIT FUNCTIONAL BLOCK DIAGRAM Addres i Bus i TNIRZ CLK 1 E P R M EN gt Data Bus 100Hz tick 4 decode 1 decader 74 573 74HC573 74 541 Address Data ies Pit titi _ C D E F E Fun ction LI TEE NN UL 4 1 5 7 T 1 12 3 HB 1 UART is software control for low speed asynchronous communication 2 The kit provides 8 bit LCD module interfacing bus 3 100Hz Tick generator is for interrupt experiment 4 Ports for display and keypad interfacing were built with discrete logic IC chips 5 Memory and Port decoders are made with Programmable Logic Device PLD HARDWARE LAYOU
4. CD CODF COE1 COE4 COE4 COE6 COE9 COE9 COEB COED COED COFO COFO COF2 COFS 5 8 8 COFC COFC COFD COFD COFD COFD COFD COFE A5 20 A9 20 0 1 20 A9 20 20 C6 DO E 60 C100 C102 C104 C106 C107 C109 C109 C10A C10A C10A C10A C10A C10D C11 CIL CTI C11 CIT C11 C11 C11 C11 C11 11 C120 C122 C122 E123 C123 2123 123 E1238 C126 C127 C12A C12B C12E C12F C130 C131 C132 C132 C135 C135 C137 C137 C13A C13B Hj o xo 1 d 0 oO 20 20 0A 0A 0A 0A 8D 85 20 20 18 65 60 20 48 20 20 0A 0A 0A 0A 8D 85 20 20 30 10 05 DF 07 54 FD 00 88 54 FD 88 54 FD 00 88 54 CO CO 80 80 CO CO JSR O LDA JSR S END BYTE LDA HL UT2X PRINT LINE2 0 LDA HL Y JSR OUT2X LDA JSR SEND BYTE JSR INC HL DEC REG C BNE PRINT LINE2 RTS CONVERT ASCII TO HEX ENIRY TO HEX EC BC 7 C B AND 11 S S ZERO NINE CONVERT TWO ASCII LETTERS P 10H CC ZERO NINE SEC SBC 30H 011111B RTS SINGLE BYTE
5. LDA 5 TIL OAE STATE LDA 0 FLAG L ADDRESS H 2 Wa WH ER 1 5 FOR R ELATIVE BYTE CALCULATION EY ADDR LDA STA LDA 1 STA STATE 0 ZERO STILL ADDRESS JSR READ MEMORY FLAG ER 5 ER 5 R 4 4 ER 3 LDA BUFFER 2 40 ER 2 LDA BUFFER 1 BUFF 40 ER 1 R RTS STATE 1 FOR ADDRESS MODE EY DATA LDA STA STILL DATA LDA 2 STA STATE 0 ZERO FLAG JSR READ MEMORY STATE 2 Page 15 of 28 MONITOR LST 8 10 2015 6 21 PM a B Asie SES 000 10 0145 Co ho ES Ne Oro Us o N 1210 1211 1212 1213 1214 1215
6. 0 0 0 OBDH RON BYTE 030H Poa BYTE 09BH Pts BYTE FM BYTE 036H gona BYTE OAEH 5 BYTE 038 PSU BYTE OBFH 8 BYTE 7 BYTE O8DH PROS BYTE D BYTE S E BYTE 00 rp Key posistion code to key internal code conv rsion table Page 27 of 28 lt o ITOR LST 8 10 2015 6 21 PM 053 C8FF 054 C8FF KEYTAB 055 C8FF 03 KO BYTE 03H HEX 3 056 C900 07 BYTE 07H 7 057 C901 OB K2 BYTE HEX B 058 C902 OF BYTE HEX 059 C903 20 BYTE 20H NOT USED 060 C904 21 5 BYTE 21H NOT USED 061 C905 02 K6 BYTE 02H 2 062 C906 06 K7 BYTE 06H 6 063 C907 0A K8 BYTE OAH A 064 C908 OE K9 BYTE OEH E 065 C909 22 BYTE 22H N USED 066 C90A 23 KOB BYTE 23H NOT USED 067 C90B 01 KOC 01H HEX 1 068 90 05 05H HEX 5 069 C90D 09 KOE BYTE 09H HEX 9 070 90 OD KOF BYTE ODH HEX D 071 C90F 13 K10 BYTE 13H STEP 072 C910 1
7. BNE Q JSR BIT D LDA REG RTS HK BIT RX ELAY CENT delay one bit 8 data bit wil be sent FROM 2400 BIT S TERMINAL ER OF STOP BIT Page 3 of 28 MONITOR LST 8 10 2015 6 21 PM 0229 0230 0231 0232 0233 C091 0234 C093 0235 C095 0236 C096 0237 C096 0238 C099 0239 C09A 0240 C09D 0241 CO9D 0242 CO9D 0243 C09D 0244 CO9D 0245 C09D 0246 C09D 0247 CO9D 0248 C09D 0249 0250 C0A2 0251 4 0252 7 0253 COA8 0254 COA8 0255 COA8 0256 COA8 0257 COAA 0258 COAB 0259 COAD 0260 COAF 0261 1 0262 0263 0264 COB7 0265 0266 0267 0268 COB9 0269 COB9 0270 COBA 0271 0272 COBC 0273 0274 0275 0276 0277 0278 1 0279 COCA 0280 5 0281 5 0282 5 0283 5 0284 5 0285 5 0286 6 0287 0288 0289 COCC 0290 COCE 0291 CODO 0292 COD2 0293 C0D3 0294 C0D3 0295 C0D3 0296 0297 COD3 0298 COD6 0299 COD8 0300 CODA 0301 CODA 0302 CODA 0303 CODA 0304 CODC BD C9 DO 20 4C A9 20 A9 20 60 48 4A 4A 4A 4A 20 A9 85 A5 20 Ed p pd QU OF 30 3A 03 A8 A8 84 01 84 85 85 9D 10 83 85 B8 E CO E
8. K EG B ROW Page 10 of 28 MONITOR LST 8 10 2015 6 21 PM 0761 0762 0763 0764 0765 0766 0767 0768 0769 0770 0771 0772 0773 0774 0775 0776 0777 0778 0779 0780 0781 0782 0783 0784 0785 0786 0787 0788 0789 0790 0791 0792 0793 0794 0795 0796 0797 0798 0799 0800 0801 0802 0803 0804 0805 0806 0807 0808 0809 rS CD C2E6 C2E7 C2E7 C2E7 C2E9 C2bEA C2EC C2ED C2ED C2ED C2ED C2F0 C2F2 2 4 C2F6 C2F6 C2F9 C2FB C2FD C2FD C2FD C2FF C301 C301 C304 C306 C308 C308 C308 C30A C30C C30C C30C C30F C30F C30F C30F C31 C31 C31 C31 C31 C31 C31 60 0 88 DO 20 A5 C9 FO AD 29 DO A9 85 20 C6 DO A2 86 20 20 A5 C9 FO 20 20 5 BD 60 AA BD 48 20 85 68 4A 4A 4A 4A C8 FD 96 93 FF 16 01 40 FO 20 7 96 7 F9 00 92 96 93 FF F7 96 93 FF OF 25 86 G2 80 C2 2 C2 C2 C8 C8 5 DEBOUNCE LDY 200 DELAY4 DEY BNE DELAY4 RTS SCANKEY JSR 5 1 LDA KEY EASED 1 KEY REL PORTO 40H SCANKEY IF REPEAT KEY WAS PR DISPLAY4 LDA 20H STA REPDELAY JSR 5 1
9. DEC REPDELAY BNE DISPLAY4 LDX 0 STX INVALID EASED E BOUNCE JSR DEBOUNCE JSR KEY 1 TIL_PRESS KEY TAX KEYTAB X ES SED SLOW DOWN IT TRE REP EAT KEY PR ESS RESET INVALID FLAG STA GPIO1 OPEN TABLE H RTS EST NOW A IS INT ERNAL CODE CONVERT LOW NIBBLE IN ACCUMULATOR TO 7 5 ENTRY A EXIT A NIBBLE 7SEG TAX SEGTAB X RTS TO 7 SEGMENT PATTERN CONVERT BYTE TRY A EXIT DE BYTE 7SEG PHA AND JSR NIBBLE STA DE PLA LSR A LSR A LSR A LSR EGM ENT PATTERN Page 11 of 28 MONITOR LST 8 10 2015 6 21 PM 0837 C337 20 25 JSR NIBBLE 7SEG 0838 C33A 85 87 STA DE 1 0839 C33C 60 RTS 0840 C33D 0841 C33D CO
10. 80 80 C8 80 C8 ORA 10 STA HL 1 OK2 JSR ADDRESS DISPLAY LDA 1 STA 1 LDA 437H STA BUFFER RTS CHK REG6 10 BCS NOT HEX NOW DISPLAY PAGE ZERO BYTE FROM 0 TO 9 SEC SBC 6 NOW A IS LOCATION IS PAGE Z TAX LDA 0 STX SAVE X JSR DATA DISPLAY LDX SAVE X ERO 0 9 TXA STA HL 1 JSR ADDRESS DISPLAY LDA 482H STA BUFFER 3 LDA 40 STA 2 RTS NOT HEX RTS PRODUCE BEEP WHEN KEY PRESSED CALIBRATED TO 523Hz BEEP LDA PORTO AND BEQ NO BEEP CHECK IF REPEAT KEY IS PRESSED THEN NO BEEP LDX 40H BEEP2 LDA STA 1 JSR DELAY LDA 0 STA 1 JSR DELAY DEX BNE BEEP2 NO BEEP RTS DELAY 0BBH j LOOP DEY BNE BEEP LOOP RTS DISPLAY COLD BOOT MESSAGE COLD MESSAGE LDA 10 STA REG D LDA 8 STA REG B Page 25 of 28 MONITOR LST 8 10 2015 6 21 PM 1901 1902 1903 1904 1905 1906 1907 1908 1909 191 191 191 191 191 191 191 191 191 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 194 194
11. EXIT GET HEX JSR CIN JSR TO HEX ASL A ASL A ASL A ASL A STA STA REG A JSR CIN JSR TO HEX CLC ADC REG A RIS CONVERT TWO ASCII LETTERS IO SINGLE BYTE EXIT A GET HEX2 JSR CIN PHA JSR SEND BYTE PLA JSR TO_HEX ASL A ECHO TO TERMINAL ASL A ASL A ASL A STA GPIO1 STA REG_A JSR CIN PHA JSR END BYTE Page 5 of 28 MONITOR LST 8 10 2015 6 21 PM 0381 C13E 68 0382 C13F 20 FD 0383 C142 18 0384 C143 65 88 0385 C145 0386 C145 60 0387 C146 0388 C146 0389 C146 0390 C146 0391 C146 20 1E 0392 C149 A2 1C 0393 C14B 20 8E 0394 14 20 23 0395 C151 85 85 0396 153 20 23 0397 C156 85 84 0398 C158 60 0399 C159 0400 C159 18 0401 C15A 65 8A 0402 C15C 85 8A 0403 C15E 60 0404 C15F 0405 C15F 0406 C15F 0407 C15F 0408 C15F A9 00 0409 C161 85 89 0410 C163 0411 C163 20 54 0412 C166 C9 3A 0413 C168 FO 07 0414 C16A 0415 C16A C9 0416 16 DO F5 0417 16 0418 16 4C ED 0419 C171 0420 C171 0421 C171 0422 C171 0423 C171 A9 00 0424 C173 85 8A 0425 C175 0426 C175 20 0A 0427 C178 85 83 0428 1 0429 17 20 59 0430 C17D 0431 C17D 20 OA 0432 C180 85 85 0433 C182 0434 C182 20 59 0435 C185 0436 C185 20 OA 0437 C188 85 84 0438 C18A 0439 C18A 20 59 0440 C18D 0441 C18D 20 OA 0442 C190
12. 10 a 31 02 10ms Tick A2 4155 ps 30 D3 OUT 1MHz_ UG 5 1 12 29 04 3 1 TICK 13 D4 8 05 214 4 IRQ vss 137 A4 55 25 pg B QB 5 06 D7 OSC14 ac x 1 A6 D7 28 KIS QD 6 2 AT 15 14 SYNC 8 A8 14 513 4 A9 A13 A12 QG Hex IRQ 45V AT A10 A12 SA 0 A11 vss 74HC164 5 16 gt IRQ test switch do 65C02 CMOS CPU U7A R6 NMI 1 U7B 10k syy3 1 4 3 54 PHI2 741514 741514 c2 741514 10 TEST POINT RESET2 4 U8 J1 LM2490 5 0 03 h p Vout vin H 2 4 2 10uF 16V amp c em i 2 i 1N4007 DC Input IAS OAUE oiu C10 C11 ox Designed by Wichit Sirichote kswichit kmitl ac th 2014 TPS i 0 1uF 0 1uF 1000uF25V user np 6502 7 Size Document Number Rev B lt Doc gt Date Saturday January 03 2015 Sheet 1 of 3 DO 51 D1 D2 Da D3 ti ug U10 D5 D6 D5 E A A 57 06 10 1Q HH A ED e D p 07 2D
13. C1B2 C1B2 C1B5 C1B5 C1B8 C1B8 1 0 C1C3 C1C5 C1C5 C1C5 C1C8 C1C8 C1CA 1 0 0 0 0 0 C1D3 C1D3 C1D3 C1D3 C1D3 C1D3 C1D6 C1D8 C1DB C1DD C1E0 1 0 1 2 1 5 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 6 1 1 1 6 8D 60 20 0 91 20 8D 20 C6 DO A5 49 18 69 85 20 C5 FO A9 85 4C 20 A5 20 A5 20 A2 20 60 00 0A 00 84 59 00 C5 83 EC 8A FF 01 8A 0A 8A 04 01 63 9D 85 84 B8 80 CI CI 80 CO CI CT CO E 1 6 20 54 1 9 C9 3B NOERROR DATA RECORD SHOW ERROR ON JSR OUT OFF RANGI STA 1 RTS JSR GET HEX LDY 0 STA HL Y JSR ADD_BCC STA 1 1 JSR INC_HL DEC REG_C LDA EOR 0FFH CLC ADC 1 STA BCC JSR GET_HEX EQ 5 11 LDA 1 STA ERROR 5 11 40 4 gt LED Fl WRITE TO MEMORY BNE DATA_RECORD UNTIL C 0 BCC ONE S COMPLE TWO S COMPLE ENT GET BYTE CHECK SUM CHECK SUM ERROR FLAG 1 JM
14. 8 3D D 4D 4o 48 Hp Hp 50 E am 6D 6Q iE gt DP 5 70 7Q D prH G pp H G 8D sa 12 L pp L pp _ PORT2 2 E 8 8 5 L23 H x 8 5 23 H x a a a a a a a a vcc LTC 4727JR LTC 4727JR N d c A co J2 74HC573 7 7 segment tes 2 gment test E 3 U12 CONS 19 8 3D 502 4D 49 68 ar 15 50 59 14 5 10k RESISTOR SIP9 7 vec 6D 6Q 13 PCG PCO 2 4 7D 12 gt gt BREAK 80 8Q PC2 PORT LE qu 5 vec PC4 74 573 PC2 PC1 FCD R8 s1 s2 53 54 55 56 SPEAKER 2 at T F cm 82327 U13 PD A ae As 4 4 7k 4 2 M ala PAT 5 57 S8 9 2510 81 512 Y3 T I p I I ii D4 15 Hi Ld Xa A 4 D 4 i Mz 1 1 1 1 4 330 A 8 PA6 513 514 15 16 17 18 SPEAKER 519 T I I T T I ES d P e ot D d Dev PORTO X 4 19181 820 521 522 523 824 525 10 L i Br _ gt 74 541 lt 7 T 1 10kRESISTOR 11 717 100 2 1 9 4 326 527 s28 i 529 1 T T T D 4 gt 30 531 82 533 5V T 1 P fe 4 4 4 Designed by Wichit Sirich
15. 0443 C190 C9 00 0444 C192 0445 C192 14 0446 C194 0447 C194 20 54 0448 C197 C9 OD 0449 C199 DO F9 0450 19 0451 19 8D 00 0452 19 0453 19 5 89 0454 1 0 9 01 0455 1 2 DO 03 0456 1 4 CO CO CO CI CT CO CT CT CI CI CT CI CO 80 PLA JSR TO HEX CLC ADC REG A RTS H Z I D RESS JSR SEND fPROMPT amp OOFFH JSR PSTRING HEX2 LDX JSR STA JSR STA RTS HEX2 BCC CLC ADC BCC STA BCC RTS GET RECORD READS INTEL HEX FILE AND SAVE TO MEMORY GET RECORD LDA 0 STA ERROR GET RECORD1 JSR CIN RECORD2 53 Wet BNE RECORDI JMP GET MOS2 GET RECORD2 LDA STA 0 BCC Tj jam J EG C GET NUMBI HL 1 HL GET LOAD ADD_BCC JSR GET_HEX 0 BEQ DATA_RECORD _ JSR 0DH WAIT CR CIN STA 1 LDA ERROR CMP BNE NOERROR ER OF BYTE ADDRESS Page 6 of 28 MONITOR LST 8 10 2015 6 21 PM 1 4 1 4 1 4 1 4 1 7 1 7 1 7 C1A8 C1A8 C1A8 C1A8 1
16. 094 009C USER Y BLOCK 1 095 009D USER S BLOCK 1 USER STACK POINTER 096 009E USER P BLOCK 1 PROGRAM STATUS REGISTER 097 009F SAVE SP BLOCK 1 SAVE SYSTE STACK 098 00A0 099 00A0 START ADDRESS BLOCK 2 100 00A2 DESTINATIO BLOCK 2 FOR OFFSE BYTE CALCULATION 101 0044 OFFSET_BYTE BLOCK 2 BY DESTINATION START ADDRESS 102 00A6 COLD BLOCK 1 COLD BOOT OR WARM BOOT 103 00A7 104 00A7 REPDELAY BLOCK 1 105 00A8 SAVE X BLOCK 1 106 00A9 SAVE Y BLOCK 1 107 00AA 108 00AA DEBUG BLOCK 2 FOR PROGRAM DEBUGGING 109 00AC 10 00AC 11 00AC 12 00AC CSEG 13 00AC 14 C000 ORG 0C000H START ADDRESS FOR ROM 15 C000 ORG 1000H START ADDRESS FOR CODE TESTING IN RAM 16 C000 17 000 A9 BF LDA 5 turn off break signal 18 C002 8D 02 80 STA PORT1 119 C005 A9 00 LDA 0 120 C007 8D 03 80 STA PORT2 turn of 7 segment 21 C00A 122 C00A power up delay E23 COOA 124 COOA A2 00 LDX 0 125 00 CA POWER_UP_DELAY DEX 126 DO FD BNE POWER_UP_DELAY 27 COOF 128 COOF jump to main code 129 COOF 130 COOF 4C 72 C8 JMP MAI 31 C012 32 C012 2400 BIT S SOFTWARE UART E 33 one bit delay for 2400 bit s UART 34 C012 35 C012 AO 4C BIT DELAY LDY 76 1190 Hz TEST AT 1MHZ OSCILLATOR 36 014 88 LOOP DEY 37 C015 DO FD BNE LOOP 138 CO17 60 RTS 139 C018 140 C018 1 5 bit delay 141 C018 142 CO18 AO 72 BIT1 5 DELAY LDY 4114 DELAY 1 5 BIT 143 88 DEY
17. 144 BNE 1 145 D RTS L46 E L47 SEND ASCII LETTER TO TERMINAL 148 149 150 SEND BYTE STA REG SAVE ACCUMULATOR 151 152 LDA Start bit is zero ICD ICD ODI ODED HD O29 OOO IOS Page 2 of 28 MONITOR LST 8 10 2015 6 21 PM 0153 C022 0154 C025 0155 C028 0156 C028 0157 C02A 0158 C02C 0159 2 0160 CO2E 0161 C030 0162 C032 0163 C032 0164 C034 0165 C037 0166 C037 0167 C03A 0168 C03A 0169 C03A 0170 0171 0172 C042 0173 C042 0174 C045 0175 C045 0176 C047 0177 C049 0178 C04B 0179 C04B 0180 C04D 0181 C050 0182 C053 0183 C054 0184 C054 0185 C054 0186 C054 0187 C054 0188 C054 0189 C057 0190 C059 0191 C05B 0192 CO5B 0193 COSE 0194 COSE 0195 C060 0196 C062 0197 C064 0198 C066 0199 C066 0200 C066 0201 C066 0202 C069 0203 C06B 0204 0205 C06D 0206 0207 071 0208 C073 0209 C076 0210 C076 0211 C078 0212 0213 C07C 0214 0215 0216 C082 0217 C082 0218 C084
18. 194 194 194 194 194 194 194 194 1950 1951 1952 1958 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1 C rS CD C85D C85D C85F C85F C85F C862 C862 C864 C866 C866 C867 C867 C869 C86B C86C C86C C86C C86C C86C C86C C86C C86C C86C C86F C872 C872 C872 C872 C872 C874 C876 C878 C87A C87A C87A C87A 87 2 20 C6 DO CA C6 DO 60 6 6 A9 85 85 85 A9 85 07 66 81 F9 82 F4 00 8C 8D 92 C87E A9 C880 C882 C884 C886 C888 C88A C88A C88A C88A C88A C88A C88C 85 A9 85 A9 85 A9 85 C88E 85 C890 C890 C892 C894 C896 C896 C898 C899 C89B C89D C89D C89E C89F C89F C8A1 C8A3 C8A5 C8A5 7 9 C8AD C8AF 1 1 9 85 85 2 9 A9 85 D8 78 A9 85 85 A9 85 85 A9 85 85 FF 9 C2 00 00 LDX 7 DISPLAY2 JSR SCAN2 DEC BNE REG D DISPLAY2 REG B NMI are called via RAM vector DISPLAY2 to insert his own routines This enables the programmer NMI JMP SFA IRQ JMP SFE MAIN LDA 40 STA BUFFER STA BUFFER 1 CLEAR INVALID FLAG STA INVALID INSERT 65
19. 4 4 4 4 4 C 723 C123 C723 C123 C725 C727 C729 C729 C72B C72B C72E C73 P 0 C732 C734 C736 C738 C73A C73C C73D C73D C73D C73F C74 C74 C74 C74 C74 C74 C74 C74 C74 C74 C75 152 C754 C755 C755 C757 C759 C759 C75B C75B C75B C75E C76 p P 0 C762 C764 C766 C768 C76A C76C C76D C76D C76D C76F C771 C771 CATS C773 C773 C776 C778 C77A C77C CTTE C78 E 0 782 784 C785 C785 C787 C789 C789 C78B C78D C78F A5 C9 DO A5 20 A9 85 A9 85 A9 85 60 c9 DO A5 20 A9 85 A9 85 A9 85 85 60 C9 DO A5 20 A9 85 A9 85 A9 85 60 Co DO 5 20 A9 85 A9 85 A9 85 85 60 C9 DO A9 85 85 OW D XO WOW CO CO CO o w XO CO CO O OO OO CO roor s BENY XO XO UJ WwW 03 14 XO XO OW roor miming A N 00 85 23 DISPLAY USER REGSITERS HEX REG LDA REG C CMP 0 BNE DA USER A STA 1 LDA 82H STA BUFFER 2 LDA 3FH STA BUFFER 3 LDA 0 STA BUFFER 4 STA BUFFER 5 CHK_REG1 CMP 1 BNE CH
20. CLC ADC BCC STA BCC LDA 0 1 STA 1 RTS END UART CODE SCAN DISPLAY ONLY ENTRY X POINTED TO NEXT MESSAGE BYTE FIX MESSAGE LOCATIO SCAN2 STX REG C LDA j to the active column KCOL2 LDA REG E EOR COMPLEMENT IT AND BREAK MUST BE LOGIC 0 TO DISABLE STA DIGIT LDA START MSG X STA SEG7 LDY 55 DELAY5 DEY BNE DELAY5 LDA 0 TURN LED OFF STA SEG7 INX ASL A STA REG_ DE HL BNE KCOL2 iX REG C RTS Page 9 of 28 MONITOR LST 8 10 2015 6 21 PM 0685 0686 0687 0688 0689 0690 0691 0692 0693 0694 0695 0696 0697 0698 0699 0700 0701 0702 0703 0704 0705 0706 0707 0708 0709 071 071 071 071 071 071 071 071 071 0719 0720 0721 0722 0723 0724 0725 0726 0727 0728 0729 0730 0731 0732 0733 0734 0735 0736 0737 0738 0739 074 074 074 074 074 074 074 074 074 074 0750 0751 0752 0753 0754 0755 0756 0757 0758 0759 0760 296 296 296 296 296 296 296 296 296 296 296 298 298 29 C29C C29C C29E C2A0 C2A0 C2A2 C2A4 C2A4 C2A6 C2A8 C2A8 C2A8 C2AA C2AA C2AC C2AE C2AE 2 1 2 1 C2B3 C2B6 C2B
21. aomu o C4 C4 NO RESPONSE A AC EY INS LD EY INS1 RTS EY DEL RTS insert byte shift down 1kB to current 1 1 1 256 bytes S K 2 5 JSR RESP 1 ONSE RTS LDA STA LDA STA DE 1 CLC LDA 40 STA DE 1 5 DISPLAY DE DISPLAY 1 DE 1 DE DE 400 EY_SEND_HEX LDA 7 ERO TIL OAE 7 FOR SENDING HEX FILE STATE F Bop LDA 0 FLAG L ADDRESS H 2 m Wa WH YN 1 EY DOW LDA 08 STA BUF LDA 85 LOAD HEX 3H PRINT LOAD FER 5 LDA STA BUF LDA STA BUF LDA 08 STA BUF LDA 0 0A3 FER 5 nj ER 4 R43 m pH R42 STA BUF FER 1 ral W LINE JSR NE Page 14 of 28 lt 8 10 2015 6 21 Bj B BB B B i p i i i i p ITOR
22. 0219 C084 0220 C086 0221 C088 0222 C088 0223 C08B 0224 C08B 0225 C08D 0226 C08D 0227 0228 8D 20 A9 85 A5 29 FO A9 8D 4C A9 8D 4C 20 46 C6 DO A9 8D 20 60 AD 29 DO 20 A9 85 A9 85 AD 29 DO A5 29 85 4C A5 09 85 4C 20 46 C6 DO 20 A5 60 02 12 08 81 80 08 BF 02 42 3F 02 42 12 80 81 1 02 12 01 F9 18 07 81 00 80 00 1 OO OO 80 CO 80 CO 80 CO 80 80 80 STA 1 STA REG D JSR BIT DELAY LDA 8 CHK BIT LDA REG AND 1 SEND 2 ERO LDA STA 1 JMP NEXT BIT SEND ZERO NEXT JS LDA STA 1 JMP NEXT BIT R BIT DELAY R REG STA 1 JSR BIT DI RTS LDA E CHK BIT ELAY CHK BIT RX BNI LDA REG_E DI RTO 80H ELAY LDA PORTO AND 80H E BIT IS ONE AND 7 STA REG F JMP NEXT BIT RX BIT IS ONE LDA REG STA REG ORA 80 NEXT BIT JSR DELAY LSR REG JMP NEXT BIT RX D EC REG D
23. 021B 021E 0220 0223 0224 0224 0226 0229 022B 022 0231 0233 0235 0238 0239 0239 0239 0239 0239 4 48 29 DO 60 5A 02 80 F9 03 00 03 01 02 90 02 90 02 90 02 02 02 02 02 02 LCD test program for 6502 KIT BUSY EQU 80H below LCD s registers are mapped into memory space command write EQU 9000H data write EQU 9001H command read EQU 9002H data read EQU 9003H cseg org 200h jmp main wait until LCD ready bit set LcdReady PHA ready LDA command read AND BUSY BNE ready loop if busy flag 1 PLA RTS LCD command write JSR LcdReady STA command write RTS LCD data write JSR LcdReady STA data write RTS screen JSR LcdReady LDA 1 JSR LCD command write RTS InitLcd LDA 38H JSR LCD command write LDA 0CH JSR LCD command write JSR clr screen LDX 0 LDY 0 JSR goto xy RTS goto xy x y entry y position 5 x position 14 0062 0063 0064 0065 0066 0067 0068 0069 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 tasm 0239 0239 023A 023 02 023 0240 0242 0245 0246 0246 0248 024A 024B 024C 024E 0251 0252 0252 0253 0253 0253 0253 0253 025
24. 1546 C697 1547 C697 1548 C697 1549 C697 1550 C697 1551 C697 1552 C699 1553 C69B 1554 C69D 1555 C69F 1556 C6A2 1557 C6A5 1558 C6A5 1559 C6A6 1560 C6A8 1561 C6AA 1562 C6AC 1563 C6AC 1564 C6AE 1565 C6BO 1566 C6B2 1567 C6B2 1568 C6B2 1569 C6B2 1570 C6B2 1571 C6B2 1572 C6B2 1573 C6B4 1574 C6B6 1575 C6B8 1576 C6B8 1577 C6B8 1578 C6B8 1579 C6BA 1580 C6BC 1581 C6BE 1582 C6BE 1583 C6C1 1584 C6C1 1585 C6C1 1586 C6C3 1587 C6C5 1588 C6C5 1589 C6C5 1590 C6C5 1591 C6C7 1592 C6C9 1593 C6CB 1594 C6CD 1595 C6DO 1596 C6DO 85 A5 29 FO A5 C9 DO 4C A5 DO A5 85 A5 85 20 A5 9A 96 97 0 84 1 85 5 C5 A2 84 4 85 5 4 80 09 5 28 C5 A5 21 0 84 1 85 C5 4 C6 CO LDA 5 STA 1 NOP NOP NOP NOP NOP LDA USER A RTI 7 KEY GO WITH RELATIVE ER INSTRUCTION IS 8TH FETCHING BREAK MUST BE LOGIC HIGH TO FIND OFFS GO STATE6 STA DESTINA LDA DISPLAY 1 STA DES INATION 1 CALCULATION ET BYTE LDA DISPLAY ION DI NOW COMPUTE OFFSET_BYTE THE REAL PC WILL BE N LDA START_ADDRESS STA HL LDA START_ADDR STA HL 1 JSR INC_H JSR INC_H L L SEC INA SBC A DES HL OFFSE IO BY ESS 1 DE
25. 85 A5 C5 DO A5 F9 00 8A 8B 0A 83 00 16 5A 0A 85 5A 0A 84 5A 26 54 OD F9 00 89 01 03 00 0A 00 84 5A 00 C5 83 EC 0A 85 0A 84 8B 85 09 8A CT C2 CT c2 CTI C2 C2 CO 80 80 CT C2 80 CO GI CI BNE GET 51 ET MOS2 LDA 0 STA BCC STA BCC 1 JSR GET HEX STA REG C CMP 0 MOS uses 16 bit checksum GET NUMBER OF BYTI END RECORD JSR GET HEX R GET HEX STA HL EN JSR ADD BCC MOS STA HL 1 JSR ADD BCC MOS GET LOAD ADDRESS JSR ADD BCC MOS JMP DATA RECORD2 D RECORD JSR CIN NOI DA P 0DH STA 1 LDA ERROR CMP 41 BNE NOERROR2 D RECORD SHOW ERROR ON LED STA 1 ERROR2 RTS TA RECORD2 JSR GET HEX LDY 0 STA HL Y WRITE TO MEMORY JSR ADD BCC MOS STA 1 JSR INC HL DEC REG C now get 16 bit JSR GET HEX LDA 1 HL 1 BNE error mos LDA BCC BNE DATA RECORD2 UNTIL C 0 check sum GET 16 bit CHECK SUM check sum now stored in HL 1 and HL STA DEBUG Page 8 of 28 MONITOR LST 8 10 2015 6 21 PM 0609 061 061 061 061 061 061 061 061 0
26. FFH Stack space is 100 1FFH User space is from 200H to 7FFFH The 6502 CPU uses memory space from 8000H BFFFH for port The monitor ROM is located at COOOH FFFFH 64kB Memory Memory mapped I O a 8000H GPIO1 32kB RAM 8001H PORTO 7EFFH 8002H 1 8000 8003H PORT2 9000H 9000H LCD command WR C000H 16kB Monitor ROM 9001H LCD data WR FFFFH 9002H LCD command RD 9003H LCD data RD GPIO1 LED The 6502 kit provides a useful 8 bit binary display It can be used to debug the program or code running demonstration The I O address is 8000H 01415 8 bit data latch Logic 1 at the output will make LED lit 1Q 4Q 5Q 74HC573 The LED can be used to display accumulator register easily Let us take a look sample code below Address Hex code Label Instruction comment 0200 A9 01 MAIN LDA 1 Load register A with 1 0202 8D 00 80 STA 8000 Write to 8000H The test code has only two instructions The first instruction has two bytes machine code A9 and 01 The second instruction has three bytes 8D 00 and 80 Enter the hex code to memory from 0200 to 0203 Then press PC and execute the instruction with single step by pressing key STEP 2 press STEP key that executes instruction STA 8000 will make the GPIO1 LED showing the content of register A Try change the load value to regis
27. HEX ADDR LDA 08FH STA BUFFER STA BUFFER 1 HEX_REL JSR HEX_ADDR LDA STA BUFFER LDA 2 STA 1 RTS HEX_REL6 JSR HEX_ADDR LDA 0B3H STA BUFFER LDA 2 STA 1 Page 16 of 28 8 10 2015 6 21 MONITOR LST 120157 C51B 1218 C51C 1219 C51C 1220 0516 1221 C51C 1222 0516 1223 5 1224 520 1225 C522 1226 C522 1227 C524 1228 C526 1229 C528 1230 C52A 1231 C52C 1232 C52C 1233 C52D 1234 C52F 1235 C531 1236 C531 1237 C532 1238 C534 1239 C536 1240 C536 1241 C537 1242 C539 1243 C53B 1244 C53B 1245 C53C 1246 C53E 1247 C540 1248 C540 1249 C542 1250 C544 1251 546 1252 546 1253 546 1254 546 1255 549 1256 549 1251 54 1258 54 1259 54 1260 54 1261 C54C 1262 C54E 1263 C550 1264 C550 1265 C552 1266 C554 1267 C554 1268 C556 1269 C558 1270 C55A 1271 C55A 1272 C55C 1273 C55E 1274 C55F T2305 C560 1276 C561 1277 C562 1278 C564 1279 C566 1280 C566 1281 C566 1282 C569 1283 C56A 1284 C56A 1285 C56A 1286 C56A 1287 C56A 1288 C56C 1289 C56E 1290 C570 1291 C570 1292 C572 60 A5 DO A9 85 A9 85 85 18 26 26 18 26 26 18 26 26 18 26 26 A5 05 85 20 60 A5 C9 DO A9 85 A9 0 91 0 Bl OA OA OA OA 05 91 20 60 A5 C9 FO C9 FO 96 97 96 97 96
28. s 8 data bit no parity no flow control one stop bit Tera Term Serial port setup Port K Baud rate Data Parity Stop Help Flow control Transmit delay 1 msec char 0 msec line Press key LOAD then key GO The kit will wait for the data stream from terminal On PC Click file gt Send File gt LED HEX The kit will read the hex file write to memory when completed the start message will be displayed The kit accepts for both Intel or MOS hex files EXPANSION BUS HEADER JP1 40 pin header provides CPU bus signals for expansion or I O interfacing Students may learn how to make the simple I O port interfacing to Analog to Digital Converter interfacing to stepper motor or AC power circuits CPU expansion connector V dj D2 D BE v B C1 05 06 4 22uF _ 7 AU 1MHz x S 7 4 E A5 RESET2 2 1 O 7 R A8 A15 A9 A A14 A 0 AIS 20 2 USER KEY User key S19 is one bit active low key switch connected to bit 6 of Port 0 To test the logic of S19 we can use instruction LDA 8001 and check bit 6 of the accumulator with test bit instruction PORTO gt 10ms TICK GENERATOR SW1 is a selector for interrupt source between key IRQ or 105 tick produced by 89C2051 microcontroller Tick generator is software controlled
29. 02 TEXT LDA STA 5 STA BUFFER 4 LDA 0BDH STA BUFFER 3 9BH STA BUFFER 2 STORE VEC LDA STA STA LDA STA STA LDX TXS OR SERVICE amp OFFH INTERRUPT FA FE NMI SERVI gt gt 8 FF SFF S LDA 57 STA USER S CLD SEI LDA 4 STA S NMI MUST B EFORE DISABLE IRQ 0 TATE STA 2 STA D STA P LDA 4 STA D STA P ERO FLAG LDA 0 ISPLAY C USER 02H ISPLAY 1 C_USER 1 INITIAL STATE ET SYSTEM STACK TO 1FFH AND USER STACK TO 17FH USING SINGLE 5 Page 26 of 28 MONITOR LST 8 10 2015 6 21 PM 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 01 02 03 04 05 06 07 08 09 C 26 36 46 CIL CIC CIC CC CC C C029 rS C BO BO BO BO PD DN PD 1 C8B3 C8B5 C8B7 C8B9 C8B9 C8B9 C8B9 C8B9 C8BB C8BD C8BD C8BD C8BF C8C1 C8C3 C8C3 C8C5 C8C7 C8C7 C8C7 C8C9 C8CC C8CC C8CF C8D2 C8D2 C8D
30. 0928 C3AA 0929 C3AA 60 RTS 0930 C3AB 0931 C3AB PEFFFEFFFFFFFFFFFFFFFFFF FUNCTION KEY FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF 0932 C3AB 0933 C3AB FUNCTION KEY 0934 C3AB 0935 C3AB C9 19 CMP 19 KEY ADDR 0936 C3AD DO 03 BNE CHK_FUNC1 0937 C3AF 4C 79 C4 JMP KEY_ADDR 0938 C3B2 0939 C3B2 C9 14 FUNC1 14H KEY DATA 0940 C3B4 DO 03 BNE CHK FUNC2 0941 C3B6 4C A9 C4 JMP KEY DATA 0942 C3B9 0943 C3B9 C9 10 CHK FUNC2 CMP 10H KEY 0944 C3BB DO 03 BNE CHK FUNC3 0945 C3BD 4C 6A C5 JMP KEY INC 0946 C3CO 0947 C3CO C9 11 CHK FUNC3 CMP 1H KEY 0948 63262 00 03 BNE CHK FUNCA 0949 4 4C C5 C5 JMP KEY DEC 0950 C3C7 0951 6326 3297 18 CHK_FUNC4 CMP 18H 0952 C3C9 DO 03 BNE CHK 5 0953 C3CB 4C DE C5 JMP KEY PC 0954 C3CE 0955 C3CE C9 1B CHK_FUNC5 CMP 1BH 0956 C3DO DO 03 BNE CHK 6 0957 C3D2 4C F2 C5 JMP KEY REG 0958 C3D5 0959 C3D5 C9 12 CHK FUNC6 12H 0960 C3D7 DO 03 BNE CHK_FUNC7 0961 C3D9 4 43 C6 JMP KEY_GO 0962 C3DC 0963 C3DC C9 1D CHK FUNC7 CMP 1DH 0964 C3DE DO 03 BNE CHK_FUNC8 0965 0 4 65 C4 JMP KEY_REL 0966 C3E 0967 C3E3 C9 1F CHK_FUNC8 CMP 1FH 0968 C3E5 DO 03 BNE CHK_FUNC9 0969 C3E7 4C 36 C4 JMP KEY_DOWNLOAD_HEX 0970 C3EA 0971 9 13 FUNC9 13H 0972 DO 03 CHK FUNC10 0973 C3EE 4C 67 C6 JMP KEY STEP 0974 C3F1 0975 C3F1 0976 1 C9 16 CHK FUNC10 16H 0977 C3F3 DO 03 BNE CHK_FUNC11 0978 C3F5 4 03 C4 JMP KEY_
31. 0H STA HL NEXT_BI 5 LDA USER_P AND 40H BEQ NEXT_BIT6 LDA HL 1 RA 1 TA HL 1 no NEXT_BIT6 LDA USER_P AND 80H BEQ OK2 LDA HL 1 Page 24 of 28 MONITOR LST 8 10 2015 6 21 PM 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 184 184 184 184 184 184 184 184 184 184 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 CD C801 C803 C805 C805 C808 C808 C80A C80C C80 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C81 C820 C820 C822 C822 C823 C825 C828 C828 C82A C82C xo OO OO O O1 O1 O1 O pH 38 AA B5 86 20 A6 10 85 4B 1 8D 357 8 10 1C 06 00 A8 3D A8 C82E C830 C831 C831 C831 C832 C832 C832 C832 C832 C835 C837 C839 C839 C83B C83D C84 C84 C84 C84 C84 C84 C84 nj nj pi 1 0 UJ 0 01 AD 29 FO A2 A9 8D 20 A9 8D 20 CA DO E 60 0 88 DO 60 A9 85 A9 85 gt AMAA BB FD 0A 81 08 82
32. 0K 5V c19 100 a lt Designed by Wichit 51 1 kswichit kmitl ac th 2014 6502 MICROPROCESSOR KIT Size Document Number Rev B Doc lt gt Date Saturday January 03 2015 Sheet 3 of 3 PARTS LIST Semiconductors 4 4 D D Gee Gee GO eee 1 27C256 32kB EPROM 2 HM62256B 32kB Static RAM 3 AT89C2051 20 pin DIP microcontroller 4 GALI6V8D programmable logic device 5 65SC02 CMOS CPU 6 74HC164 shift register 7 741 514 inverter 8 LM2490 5 0 voltage regulator 10 09 LTC 4727JR seven segment LED 11 U12 U14 74HC573 data latch 13 74 541 tristate buffer 15 232 RS232 level converter 1 D5 D6 D7 D8 D9 D10 3mm LED 11 D12 C4 1000uF25V electrolytic C5 C6 C7 C8 C9 0 1uF disc ceramic C10 C11 O 1uF disc ceramic C12 10uF 10V electrolytic C19 C18 100nF disc ceramic Additional parts JJP1 HEADER 20X2 JR1 CONN RECT 16 text LCD connector J1 DC Input J2 CON3 3 pin header 151 SPEAKER SW ESP switch SW2 IRQ SW3 RESET D2 55 500123 transient voltage suppressor SW4 user D D D Q 3 1N4007 rectifying diode 4 LED 13 1N5236A 1 BC327 PNP transistor Resistors all resistors are 1 8W 5 R 1 680 R2 R3 R5 1k R8 R4 4 7k R R 13 R6 10k 11 R7 10k RESISTOR SIP 9 R9 330 R 12 10 10 apacitors 1 22uF electrolytic C2 C13 C14 C15 C16 C1
33. 1 02 03 04 05 06 07 08 09 C 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 4 4 4 4 4 4 4 4 4 4 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 CD C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C61 COE C61 D2 D4 D6 D6 D8 DA DC Di DI DI Ed pd pH EA E C6E 2 6 4 C6F6 C6FA C6FC C6FC 6 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C C71 C C C71 C C71 C Cd C71 C71 C71 C71 0 C C Fi es as oe as pas eS Ras nj Hj Hj Hj OQ Q P 0 d 2 C722 C722 0 91 5 85 5 85 20 9 85 60 9 85 9 85 9 85 9 85 9 85 85 9 85 60 85 9 8D A6 9A 60 00 84 84 96 85 97 1 02 94 9 02 96 98 97 99 9 9B 9D 79 9 4 80 4 LDY STA LDA STA LDA STA JSR LDA 0 HL Y HL DISPLA
34. 1216 4 4 4 4 4 4 4 4 C4BC C4BE 4 0 4 0 C4C2 4 4 C4C6 C4C6 4 CACC CACC C4CE C4D0 C4D2 C4D2 C4D4 C4D6 C4D8 C4D8 C4D9 C4D9 C4D9 C4D9 C4D9 C4D9 C4D9 C4DB C4DD C4DF 4 4 4 4 4 4 4 4 4 4 4 4 5 29 85 5 29 85 5 29 85 5 29 85 5 85 5 09 85 60 5 85 5 20 0 Bl 96 84 97 85 4B 00 84 3D C4F1 C4F3 C4F5 4 7 C4F8 C4F8 C4FB C4FD 501 C503 C504 C504 C504 C504 C507 C509 C50B C50D C50F C51 C51 C51 C51 C51 C51 C51 e521 20 A9 85 A9 85 60 20 A9 85 A9 85 8F 8C 02 8D 1C B3 8C 02 8D CS 5 5 5 LDA BUFFER 5 STA BUFFER 5 FER 4 FER 4 FER 3 FER 3 LDA BUFFER 2 40H ER 2 n PU UJ Hy Ay LDA BUFFER 1 1 LDA BUFFER A BUFFER RTS READ MEMORY READ MEMORY LDA DISPLAY STA HL LDA DISPLAY 1 STA HL 1 JSR ADDRESS DISPLAY LDY 0 LDA HL Y STA GPIO1 JSR DATA DISPLAY RTS HEX SEND FILE JSR HEX ADDR LDA STA BUFFER STA BUFFER 1 HEX SEND FILE2 JSR
35. 2 0889 C372 0890 C372 A5 83 LDA REG C 0891 C374 4C 1C C5 JMP HEX ADDR 0892 C377 0893 CITI C902 CHK_STATE2 CMP 2 0894 C379 DO 03 BNE CHK_STATE3 0895 C37B 4C 4A C5 JMP HEX DATA 0896 C37E 0897 C37E C9 03 CHK STATE3 CMP 43 0898 C380 DO 03 5 5 0899 C382 4C 23 C7 JMP HEX REG 0900 C385 0901 C385 C9 05 5 5 45 0902 C387 DO 03 5 6 0903 C389 4C 04 C5 JMP HEX REL 0904 C38C 0905 C38C C9 06 CHK STATE6 CMP 46 0906 8 DO 03 BNE STATE 0907 C390 4C 10 C5 JMP HEX REL6 0908 C393 0909 9 C907 CHK STATE7 7 0910 C395 DO 03 BNE STATES 0911 C397 4C EC C4 JMP HEX SEND FILE 0912 C39A Page 12 of 28 MONITOR LST 8 10 2015 6 21 PM 0913 C39A C9 08 STATE8 CMP 8 0914 C39C DO 03 BNE 5 9 0915 C39E 4C F8 4 JMP HEX SEND FILE2 0916 C3A1 0917 1 A5 83 CHK STATE9 lda REG 0918 C3A3 8D 00 80 sta 1 0919 C3A6 A9 01 LDA 1 INVALID KEY PRESSED 0920 C3A8 85 92 STA INVALID 0921 C3AA 0922 C3AA 0923 C3AA 0924 C3AA 0925 C3AA 0926 C3AA HEX KEY WAS PRESSED 0927 C3AA
36. 2 C8D4 C8D7 C8D7 C8DA C8DD C8E4 C8E5 C8E6 5 85 5 85 0 B1 A5 C9 FO A9 85 C8E7 C8E C8EE C8EF C8EF C8EF 1 2 4 5 C8F6 C8F7 C8F8 C8F9 C8FA C8FB C8FC C8FD C8FE C8FF C8FF C8FF C8FF OOooooopmPuUuuoo s UJ gt C0 UJ UJ gt D CO 96 97 85 00 84 99 OF 99 A6 FF 55 32 00 00 66 32 D7 80 C8 C8 80 C2 CS C8 C8 STA HL LDA DISPLAY 1 STA HL 1 7 JSR ADDR LDA JSR DAT LDA DI LDY 0 HL Y LDA 99H STA COLD STA JSR BE WARM_BOOT STA G LDA 1 JSR COLD MESSAGE EP LDA 0 01 SPLAY ESS DISPLAY A DISPLAY LDA COLD 99 BEO WARM BOOT FF TEST 6 101 LOOP3JSR SCANKEY JSR JSR YEXE EP JMP LOOP3 START MSG BYTE E 0 BYTE 0 BYTE 9BH 0 0 0
37. 294 C574 A9 02 LDA 42 1295 C576 85 94 STA STATE STATE 2 FOR DATA MODE 1296 C578 1297 C578 A9 00 LDA 40 1298 C57A 85 95 STA ZERO FLAG 1299 CSTE 1300 CSTE 1301 C57C 18 CLC 1302 C57D A5 96 LDA DISPLAY 1303 C57F 69 01 1 1304 C581 85 96 STA DISPLAY 1305 C583 A5 97 LDA DISPLAY 1 1306 C585 69 00 ADC 0 1307 C587 85 97 STA DISPLAY 1 1308 C589 JSR READ MEMORY 1309 C589 20 B1 C4 JSR STILL DATA 1310 C58C 60 RTS 1311 C58D 1312 C58D EL KEY PRESSED 1313 C58D 1314 C58D Save start address 1315 C58D 1316 C58D A5 96 LDA DISPLAY 1317 C58F 85 STA START ADDRESS 1318 C591 A5 97 LDA DISPLAY 1 1319 C593 85 Al STA START_ADDRESS 1 1320 C595 1321 C595 A9 06 LDA 46 1322 C597 85 94 STA STATE 1323 C599 A9 00 LDA 40 1324 C59B 85 95 STA ZERO FLAG 1325 C59D 1326 C59D 20 81 C4 JSR STILL ADDRESS 1327 C5A0 9 LDA 40B3H 1328 C5A2 85 8C STA BUFFER 1329 C5A4 A9 02 LDA 42 1330 C5A6 85 8D STA BUFFER 1 1331 C5A8 60 RTS 1332 C5A9 1333 C5A9 1334 C5A9 Save start address 1335 C5A9 1336 C5A9 A5 96 LDA DISPLAY 1337 C5AB 85 STA START ADDRESS 1338 C5AD A5 97 LDA DISPLAY 1 1339 C5AF 85 Al STA START_ADDRESS 1 1340 5 1 1341 C5B1 9 08 LDA 8 1342 C5B3 85 94 STA STATE 1343 C5B5 A9 00 LDA 40 1344 C5B7 85 95 STA ZERO FLAG 1345 C5B9 1346 C5B9 20 81 C4 JSR STILL ADDRESS 1347 C5BC A9 8F LDA 408FH 1348 C5BE 85 8C STA BUFFER 1349 5 0 A9 02 LDA 42 1350 C5C2 85 8D STA BUFFER 1 1351 5 4 60 RTS 1352 C5c5 1353 C5C5 1354 C5C
38. 3 0253 0256 0259 025A 025A 025A 025A 025D 025F 0262 0264 0267 0269 026C 026E 0271 0273 0276 0278 027B 027D 0280 0282 0285 0285 0286 0286 0286 0286 0286 0286 0286 0286 Number of errors 00 08 80 0 01 03 02 02 02 02 02 02 02 02 02 02 02 02 02 goto xy TXA CMP 0 BNE casel TYA CLC ADC 80 JSR LCD command write RTS casel CMP 1 BNE case2 TYA CLC ADC 0 JSR LCD command write RTS case2 RTS write ASCII code to LCD at current position entry putch lcd JSR LcdReady JSR LCD data write RTS main JSR InitLcd LDA 6 JSR putch lcd LDA 5 JSR putch lcd LDA 0 JSR putch lcd LDA 2 JSR putch lcd LDA JSR putch lcd LDA JSR putch lcd LDA 1 JSR putch lcd LDA JSR putch lcd brk END 0 15 LOGIC PROBE POWER SUPPLY The kit provides test points TP4 5V and TP5 GND for using the logic probe Students may learn digital logic signals with logic probe easily The important signals are RESET TP2 and PHI2 clock TP3 Tick signal however indicated by D1 LED blinking Logic probe can test it at P3 7 of the 89C2051 microcontroller directly Red clip is for 5V Black clip for GND 5V at TP1 GND at TP1 WRITE YOUR OWN MONITOR PROGRAM The monitor ROM is 01 27C256 Source code of the monitor program is available for download Students can learn and modify the source code b
39. 5 1355 C5C5 1356 C5C5 1357 C5C5 1358 C5C5 1359 C5C5 DECREMENT CURRENT ADDRESS BY ONE 1360 C5C5 1361 C5C5 1362 C5C5 A9 02 Y DEC LDA 42 1363 C5C7 85 94 STA STATE STATE 2 FOR DATA MODE 1364 C5C9 1365 C5C9 A9 00 LDA 40 1366 C5CB 85 95 STA ZERO FLAG 1367 C5CD 1368 C5CD Page 18 of 28 MONITOR LST 8 10 2015 6 21 PM 1369 5 38 SEC 1370 C5CE A5 96 LDA DISPLAY 1371 5 0 E9 01 SBC 1 1372 C5p2 85 96 STA DISPLAY 1373 504 A5 97 LDA DISPLAY 1 1374 5 6 E9 00 SBC 0 1375 5 8 85 97 STA DISPLAY 1 1376 C5DA 2 JSR READ MEMORY 1377 C5DA 20 B1 C4 JSR STILL DATA 1378 C5DD 60 RTS 1379 5 1380 C5DE KEY PC SET CURRENT USER ADDRESS 1381 5 1382 C5DE A9 02 KEY PC LDA 2 1383 C5E 85 94 STA STATE STATE 2 FOR DATA MODE 1384 CSE 1385 5 2 A9 00 LDA 0 1386 5 4 85 95 STA ZERO FLAG 1387 CSE 1388 C5E6 A5 98 LDA PC USER 1389 C5E 85 96 STA DISPLAY 1390 LDA PC_USER t 1 1391 STA DISPLAY 1 1392 JSR READ MEMORY 1393 C5EE 20 B1 C4 JSR STILL DATA 1394 5 1 60 RTS 1395 5 2 1396 C
40. 5F2 KEY REGSITER 1397 C5F2 SET STATE TO 3 FOR REGISTER INPUT WITH HEX KEY 1398 5 2 1399 5 2 9 03 KEY REG DA 3 1400 C5F4 85 94 STA STATE STATE 3 FOR REGISTER DISPLAY 1401 5 6 1402 C5F6 9 03 LDA 3 1403 C5F8 85 91 STA BUFFER 5 1404 C5FA A9 LDA 8FH 1405 5 85 90 STA BUFFER 4 1406 C5FE A9 LDA OBEH 1407 C600 85 8F STA BUFFER 3 1408 C602 A9 02 LDA 42 1409 C604 85 8E STA BUFFER 2 1410 C606 A9 00 LDA 0 IST C608 85 8D STA BUFFER 1 1412 C60A 85 8C STA BUFFER 1413 C60C 1414 60 60 RTS 1415 C60D 1416 C60D 1417 60 5 8 1418 60 1419 C60D 5 96 LDA DISPLAY 1420 C60F 85 A2 STA DESTINATION DESTINATION IS NOW ENDING ADDRESS 1421 C611 A5 97 LDA DISPLAY 1 1422 C613 85 A3 STA DESTINATION 1 1423 615 1424 C615 NOW COMPUTE NUMBER OF BYTE DESTINATION START ADDRESS 1425 C615 A5 AO LDA START ADDRESS 1426 C617 85 84 STA HL 1427 C619 A5 A1 LDA START ADDRESS 1 1428 6 85 85 STA HL 1 1429 C61D 1430 6 38 SEC 1431 6 A5 A2 DESTINATIO 1432 C620 E5 84 SBC HL 1433 C622 85 4 STA OFFSET BYTE 1434 C624 1435 C624 A5 A3 DESTINATION 1 1436 C626 E5 85 SBC HL 1 1437 C628 85 A5 STA OFFSET 1 OFFSET NUMBER OF BYTE 1438 C62A 1439 C62A DEVIDE NUMBER OF BYTE WITH 16 TO GET NUMBER OF RECORD TO BE SENT 1440 62 1441 C62A 46 A5 LSR OFFSET 1442 C62C 66 A4 ROR OFFSET BYTE 1443 62 1444 62 46 5
41. 6 C2B8 C2B9 C2BB C2BB C2BD C2C0 C2C0 C2C2 C2C3 265 C2C5 C2C5 C2C7 C2C9 C2C9 C2CC A2 A9 85 A9 85 A9 85 A9 85 A5 49 29 8D B5 8D 0 DO A9 8D 0 88 DO A9 85 AD 85 46 BO A5 85 A5 0A 85 C6 DO 00 00 83 FF 93 01 80 06 84 80 FF BF 02 8C 30 FD 00 03 32 FD 06 82 01 81 81 04 83 83 82 F2 80 80 84 C2 80 80 80 80 ENTRY SCAN DISPLAY AND KEYBOARD DISPLAY BUFFER IN PAGE 0 EXIT Ne Ne Ne KEY 1 NO KEY PRESSED KEY gt 0 KEY POSITION REGSITERS USED X A Y 5 1 LDX 0 LDA 0 LDA 1 STA KEY LDA 1 LDA 6 STA HL to the KCOL active column LDA REG E EOR COMPLEMENT IT AND MUST BE LOW FOR BREAK STA DIG STA SEG LDY 53 DELAY3 IT LDA BUFFER X j 0 DEY LDA 0 STA SEG LDY 450 DELAY10 BNE TURN LED OFF j DEY BNE DELAY10 LDA 6 STA RE KROW LS G D D Rotate D 1 bit right bit 0 BCS NOK of D will be rotated into EY carry flag LDA REG C STA KEY NOKEYINC REG C lncrease current key code by 1
42. 61 0619 0620 0621 0622 0623 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 0636 0637 0638 0639 064 064 064 064 064 064 064 064 064 064 0650 0651 0652 0653 0654 0655 0656 0657 0658 0659 0660 0661 0662 0663 0664 0665 0666 0667 0668 0669 0670 0671 0672 0673 0674 0675 0676 0677 0678 0679 0680 0681 0682 0683 0684 C C24C C24E C250 C250 253 6258 6253 255 C257 C257 C257 C257 C257 C25A C25A C25A C25A C25A C25A C25A C25B C25D C25F C261 C263 C265 C266 C266 C266 C266 C266 C266 C266 C266 C266 C266 C268 C26A C26C C26C C26E C270 C270 C270 C272 C272 C274 C274 C276 C279 C279 27 C27F 2 C281 C282 C284 C284 C286 C289 C289 C289 C289 C289 E C28A C28A C28C C28D C28F C28F C291 C293 C293 C295 C295 C296 C5 DO 4 9 85 4C E 18 65 85 A9 65 85 60 86 A9 85 A9 85 A5 49 29 8D BD 8D 0 DO A9 8D A5 0A 85 C6 DO A6 60 84 03 57 01 89 8A 8A 00 8B 8B 83 01 80 06 84 80 FF BF 02 03 05 FD 00 03 80 80 84 DD 83 C2 CI 80 C8 80 CMP HL BNE error mos JMP SKIP12 error mos LDA 1 STA ERROR ERROR FLAG 1 SKIP12 JMP GET MOS1 NEXT LINE add 16 bit check sum stores in 1 and BCC ADD BCC MOS
43. 6502 Microprocessor User s Manual dao 5 8 HI B3 B2 BO 05 D8 be See Or sue 506 _ 407 508 809 NM _ 02 03 504 505 E ae NV_B DIZC 00 ADDR GO USER IRQ REP 2 Microproc essor Kit 6502 MICROPROCESSOR KIT CONTENTS OVERVIEW epp T c NIE 3 FUNCTIONAL BLOCK 22 4 4 4 4 3 HARDWARE LAY QUT ii cerrar nia ausi e eade Inh Pd naui CE eu aa dni 4 KEYBOARD LAYOUT 5 HARDWARE FEATURES 6 MEMORY AND 6 T 7 CONNECTING TO TERMINAL eene 8 EXPANSION 5 22252255550 LE EORR 9 10ms TICK GENERATOR usan abd eR 10 RS232C iiic chaton heb iie da ica ev lain rd daa uu 11 DATA FRAME for UART 11 CONNECTING LCD MODULE 5353 2 13 LOGIC PROBE POWER SUPPLY tir dri us is cR d 16 WRITE YOUR OWN MONITOR 17 HARDWARE SCHEMATIC
44. 7 10uF electrolytic C3 10uF 16V electrolytic 51 52 53 54 55 56 57 58 59 510 511 512 513 514 switch 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 TP1 TP2 TP3 TEST POINT 4 5 5 GND SUB D 9 Male cross cable Y1 OSC 1M MEC1 OSC14 PCB double side plate through hole LED cover Clear RED color acrylic plastic Keyboard sticker printable SVG file MONITOR PROGRAM LISTINGS MONITOR LST 8 10 2015 6 21 PM 0001 0002 0003 0004 0005 0006 0007 0008 0009 1 CO c 225252525252 525252525252 52 Ne Ne 44 Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Ne Monitor program source code for 6502 Microprocessor Kit Written by Wichit Sirichote 2015 Copyright c kswichit kmitl ac th Source code was assembled with tasm assembler Example of using tasm d tasm tasm 65 monitor asm The object fi
45. 7D3 1795 C7D5 1796 C7D5 I397 C7D7 1798 C7D7 1799 C7D7 1800 C7D9 1801 C7DB 1802 C7DD 1803 CIDE 1804 C7E1 1805 C7E1 1806 C7E3 1807 C7E5 1808 C7E7 1809 C7E9 1810 C7EB 1811 C7ED 1812 C7ED 1813 1814 1 1815 1816 1817 C7F5 1818 1819 C7F9 1820 C7F9 1821 C7FB 1822 C7FD 1823 1824 5 29 FO 5 09 85 5 29 FO 5 09 85 5 29 FO 5 85 5 29 FO 5 09 85 20 A9 85 A9 85 60 C9 DO A9 85 85 A5 29 FO 5 09 85 5 29 FO 5 85 5 29 FO 5 09 85 5 29 FO 5 1 8D 85 8C USER P STA 1 AND 1 BEQ NEXT LDA HL ORA 1 STA HL NEXT BIT1 LDA USER P AND 42 NEXT BIT2 LDA HL ORA 10H STA HL NEXT BI 2 LDA USER P AND 44 BEQ NEXT BIT3 LDA HL 1 ORA 1 STA HL 1 OK1 CHK REG5 NEXT BIT3 LDA USER P AND 8 1 LDA ORA STA HL 1 10H HL 1 JSR ADDRESS_DISPLAY LDA 1FH STA BUFFER 1 LDA 085H STA BUFFER RTS CMP 4 BNE CHK_REG6 LDA 0 RESET HL STA HL STA HL 1 TO 0000 LDA 051 STA G ER_P 1 1 4 1 x _BIT4 LDA USER AND 20H BEQ NEXT_BIT5 LDA HL ORA 1
46. 97 81 95 00 0A 01 95 00 96 00 96 83 96 B1 94 05 1D 07 35 C4 C4 RTS T EX_ADDR CMP HEX KEY FOR ADDRESS LDA ZERO_FLAG 0 LDA STA N STA D STA D SHIFT_ADDRESS ROL D ROL D CLC ROL D CLC ROL D LDA D ORA RI STA D JSR RTS HIFT_ADDRESS 1 ERO_FLAG LDA 0 ISPLAY ISPLAY 1 CLC ROL DISPLAY ISPLAY 1 CLC ROL DISPLAY ISPLAY 1 ROL DISPLAY ISPLAY 1 ROL DISPLAY ISPLAY 1 ISPLAY EG C ISPLAY JSR READ MEMORY STILL ADDRESS T EX_DATA CMP BNE LDA STA N LDA LDY STA SHIFT_DATA ASL A ASL A ASL A ASL A ORA R STA JSR READ JSR STILL_DATA RTS HEX KEY FOR DATA MODE LDA ZERO FLAG 0 HIFT DATA 1 ERO FLAG 0 0 DISPLAY Y 0 LDA DISPLAY Y EG C DISPLAY Y EMORY INCREMENT CURRENT ADDRESS BY ONE KEY INC LDA STATE CMP 5 wW 10 W EL KEY PRESSED 7 5 w IO U END_INC1 Page 17 of 28 MONITOR LST 8 10 2015 6 21 PM 1293 C574 1
47. INS 0979 0980 C3F8 C9 17 CHK_FUNC11 17H 0981 C3FA DO 04 BNE CHK_FUNC12 0982 C3FC 4C 02 C4 JMP KEY_DEL 0983 60 RTS 0984 C400 0985 C400 CHK FUNC12 0986 C400 0987 C400 60 RTS 0988 C401 Page 13 of 28 MONITOR LST 8 10 2015 6 21 PM 0989 C401 0990 C401 0991 C401 0992 C402 0993 C402 0994 C402 0995 C403 0996 C403 0997 C403 0998 C403 0999 C403 1000 C403 1001 C405 1002 C407 1003 C409 1004 40 1005 C40D 1006 C40D 1007 C410 1008 C411 1009 C411 1010 C413 1011 C415 1012 C417 1013 C419 1014 C419 1015 41 1016 41 1017 1018 420 1019 420 1020 420 1021 420 1022 420 1023 421 1024 421 1025 421 1026 421 1027 421 1028 421 1029 421 1030 421 1031 421 1032 421 1033 423 1034 425 1035 425 1036 427 1037 429 1038 42 1039 C42E 1040 C430 1041 C432 1042 C434 1043 C435 1044 C435 1045 C436 1046 C436 1047 C436 1048 C436 1049 C436 1050 C436 1051 C438 1052 C43A 1053 C43C 1054 C43E 1055 C440 1056 C442 1057 C444 1058 C446 1059 C448 1060 C44A 1061 C44C 1062 1063 450 1064 450 60 60 5 C9 FO C9 FO 20 5 85 5 85 18 5 85 60 A9 85 A9 20 A9 85 A9 85 60 60 A9 85 A9 85 A9 85 A9 85 A9 85 A9 85 85 94 01 08 02 04 01 87 28 87 B3 91 85 A3 OO UJ OO w
48. IRQ pin to logic low used for experimenting with interrupt process Monitor function keys REP Repeat the key that pressed must be pressed together with REP key INS N A DEL N A STEP Execute user code only single instruction and return to save CPU registers GO Jump from monitor program to user code Decrement current display address by one Increment current display address one PC Set current display address with user Program Counter Display user registers flags or page zero 00 to 09 with HEX key DATA Set entry mode of hex keys to Data field ADDR Set entry mode of hex keys to Address field COPY N A REL Compute relative byte used with key for Start Destination and key GO SEND N A LOAD Load Intel or MOS hex file at 2400 bit s using serial port Note N A not available for the current version of monitor program HARDWARE FEATURES The hardware features are as follows e CPU 655 02 CMOS 8 bit Microprocessor 1MHz clock Memory 32kB RAM 16 EPROM Memory and I O Decoder chip Programmable Logic Device GAL16V8D Display 6 digit 7 segment LED Keyboard 36 keys RS232 port software controlled UART 2400 bit s 8n1 Debugging LED 8 bit GPIO1 LED at location 8000 Tick 10ms tick produced by 89C2051 Text LCD interface direct CPU bus interface text LCD Expansion header 40 pin header MEMORY AND MAPS The first 32kB is RAM space from 0000 7FFFH Zero page is location 00
49. K11 1FH TAPERD 073 C911 00 K12 BYTE OOH HEX 0 074 C912 04 K13 BYTE 04H HEX 4 075 C913 08 K14 08H HEX 8 076 C914 0C K15 BYTE OCH HEX C 077 C915 12 K16 BYTE 12H GO 078 C916 1E K17 TAPEWR 079 C917 1A K18 BYTE 080 C918 18 K19 BYTE 18H PC 081 C919 1B K1A BYTE 1BH REG 082 C91A 19 K1B 19H ADDR 083 C91B 17 17H DEL 084 C91C 1D K1D BYTE RELA 085 C91D 15 1 15H SBR 086 C91E 11 BYTE 11H 087 91 14 K20 BYTE 14H DATA 088 C920 10 K21 BYTE 10H 089 C921 16 K22 BYTE 16H INS 090 C922 VE K23 BYTE 1CH MOVE 091 C923 092 C923 PAGE FOR CONSTANT STRINGS AREA 093 C923 094 EFOO OEFOOH ROM MONITOR 095 EFOO ORG RAM TEST 096 EFOO 097 EFOO 098 EFOO 6502 TRAINER KIT V1 0 ROM 10 13 0 099 EFOO 363530322054 1 BYTE 6502 TRAINER KIT V1 0 RAM 10 13 O0 099 EF06 5241494E4552204B49542056312E302052414D0A0D00 100 EF1C 101 EF1C 102 EFIC 00 PROMPT BYTE gt gt 0 103 104 105 106 107 VECTOR AND IRQ 108 109 10 FFFA ORG OFFFAH 11 FFFA 12 FFFA 6C C8 WORD NMI 13 FFFC 00 CO WORD 0 000 RESET VECTOR 14 FFFE 6F C8 WORD IRQ IRQ VECTOR T5 0000 16 0000 17 0000 18 0000 19 0000 END L20 0000 0000 22 0000 asm Number of errors 0 CF
50. K_REG2 USER X STA 1 LDA 82H STA BUFFER 2 LDA 7 STA BUFFER 3 LDA 0 STA BUFFER 4 STA 5 CHK_REG2 CMP 2 BNE CHK_REG3 USER Y STA 1 LDA 82H STA BUFFER 2 LDA 0B6 STA BUFFER 3 LDA 0 STA BUFFER 4 STA 5 d CHK REG3 CMP 3 BNE 4 USER S STA 1 LDA 82 STA 2 STA BUFFER 3 LDA 40 STA BUFFER 4 STA 5 RTS CHK_REG4 5 JSR DATA_DISPLAY REGISTER A JSR DATA_DISPLAY REGISTER X JSR DATA_DISPLAY REGISTER Y JSR DATA_DISPLAY REGISTER 5 BNE REG5 LDA 0 STA HL STA HL 1 RESET HL TO 0000 Page 23 of 28 MONITOR LST 8 10 2015 6 21 PM 1749 C78F 1750 C791 List C791 1752 C493 1758 C795 1754 C797 1755 C799 1756 C79B 1757 C79B 1758 C79D 1759 C79F 1760 1761 1762 C7A3 1763 C7A5 1764 1765 1766 C7A9 1767 C7AB 1768 C7AD 1769 C7AD 1770 1771 C7B1 1772 C7B3 1773 C7B3 1774 C7B5 1775 C7B7 1776 C7B9 ETIA C7B9 1778 C7BB 1779 C7BD 1780 C7BF 1781 C7C2 1782 C7C2 1783 7 4 1784 C7C6 1785 C7C8 1786 C7CA 1787 C7CB 1788 C7CB 1789 C7CB 1790 C7CD 2 2024 C7CF 1792 C7CF 1793 1 1794 C
51. LSR OFFSET Page 19 of 28 8 10 2015 6 21 MONITOR LST 1445 C630 1446 C632 1447 C632 1448 C634 1449 C636 1450 C636 1451 C638 1452 C63A 1453 C63A 1454 C63C 1455 C63F 1456 C63F 1457 C640 1458 C640 1459 C640 1460 C643 1461 C643 1462 C643 1463 C643 1464 C643 1465 C645 1466 C647 1467 C649 1468 C649 1469 C64B 1470 C64D 1471 C64D 1472 C64F 1473 C651 1474 C651 1475 C652 1476 C654 1477 C654 1478 C654 1479 C654 1480 C656 1481 C657 1482 C657 1483 C659 1484 C65A 1485 C65C 1486 C65D 1487 C65F 1488 C660 1489 C662 1490 C664 1491 C666 1492 C667 1493 C667 1494 C667 1495 C667 1496 C667 1497 C668 1498 C66A 1499 C66A 1500 C66A 1501 C66A 1502 C66C 1503 C66D 1504 C66D 1505 C66D 1506 C66D 1507 C66F 1508 C671 1509 C673 1510 C675 ESNE C675 1512 C675 1513 C675 1514 C677 1515 C678 1516 C67A 1517 C67B 1518 C67D 1519 C67E 1520 C680 4C A5 C9 FO C9 FO C9 FO SPP Ps Ps gt gt 86 9 5 85 5 85 5 48 5 48 5 48 4 4 5 4 5 4 4 00 55 94 06 46 08 CO 0A EF 9 9 97 96 9B 9 9 9 9 9B 9 80 C4 ROR ROR LSR ROR RTS SHORT GO STATE10 OFFSET BYTE LSR OFFSET 1 OFFSET BYTE OFFSET 1 OFFSET BY
52. LST 065 C450 066 C450 067 C450 068 C452 069 C454 070 C455 071 C455 072 C457 073 C45A 074 C45A 075 C45A 076 C45D 077 C45D 078 C45F 079 C461 080 C464 081 C464 082 C465 083 C465 084 C465 085 C465 086 C467 087 C469 088 C469 089 46 090 C46D 091 470 092 C472 093 C474 094 C476 095 C478 096 C479 097 C479 098 C479 099 C479 100 C47B 101 C47D 102 C47D 103 C47F 104 C481 105 C481 106 C481 107 C484 08 C484 09 C486 10 C488 14 48 12 C48A 19 48 14 48 15 C490 16 C490 17 C492 18 C494 19 C496 120 C496 121 498 122 49 123 49 124 49 25 49 126 C4A0 27 4 2 128 C4A2 129 4 4 130 4 6 131 C4A8 132 C4A8 33 C4A9 134 4 9 E35 C4AB 136 37 C4AD 138 539 4 1 40 4 1 9 85 60 9 8D 20 A9 85 20 60 A9 85 A9 85 20 A5 09 85 A5 85 A5 09 85 A5 09 85 A5 29 85 A5 29 85 60 A9 85 A9 85 20 0A 94 55 00 5F 02 94 B1 01 94 00 95 D9 nm o n LE o p 8C 02 94 00 95 D9 80 CTI C4 C4 C4 C4 8 pds STA STATE RTS R NE W_LINE R NE W_LINE GO_STATE10 STA JSR LDA GPI LDA 10 LDA 55 01 2 STA JSR RTS STATE STI LL DATA RECORD G ET INTEL HEX FILE
53. NVERT BYTE TO 7 SEGMENT PATTERN AND SAVE TO DISPLAY BUFFER DATA FI 0842 C33D ENIRY A 0843 C33D 0844 C33D 48 DATA DISPLAY PHA SAVE ACCUMULATOR 0845 C33E 20 2A C3 JSR BYTE 7SEG 0846 C341 A5 86 DE 0847 C343 85 8C STA BUFFER 0848 C345 A5 87 DA DE 1 0849 C347 85 8D STA BUFFER 1 0850 C349 68 PLA 0851 C34A 60 RTS 0852 C34B 0853 C34B CONVERT 16 BIT ADDRESS IN HL AND SAVE IT TO ADDRESS FILED DISPLAY BU 0854 C34B ENTRY HL 0855 C34B 0856 C34B ADDRESS DISPLAY 0857 C34B 0858 C34B A5 84 LDA HL 0859 C34D 20 2A C3 JSR BYTE 7SEG 0860 C350 A5 86 DE 0861 C352 85 8E STA 2 0862 C354 A5 87 DA DE 1 0863 C356 85 8F STA BUFFER 3 0864 C358 A5 85 LDA HL 1 0865 C35A 20 2A C3 JSR BYTE_7SEG 0866 C35D A5 86 DE 0867 C35F 85 90 STA BUFFER 4 0868 C361 A5 87 DA DE 1 0869 C363 85 91 STA BUFFER 5 0870 C365 60 RTS 0871 C366 0872 C366 PERRO RGR Ga UK co Renae AA EAR AYR Ae AANA TA aUe 0873 C366 0874 C366 EXECUTE FUNCTIONS OR HEX KEY ENTERED 0875 C366 CHECK HEX KEY OR FUNCTIONS KEY 0876 C366 ENTRY A 0877 C366 0878 C366 C9 10 KEYEXE CMP 410H 0879 C368 BO 41 BCS FUNCTION KEY 0880 C36A 0881 C36A 0882 C36A HHHHHHHHHHHHHHH KEY HEX ENTERED 0883 C36A 0884 C36A 85 83 STA REG C SAVE HEX KEY 0885 C36C A5 94 LDA STATE 0886 C36E 0887 C36E C9 01 CMP 1 0888 C370 DO 05 BNE CHK STATE
54. P GET_RECORD1 NEXT L END PROMPT JSR N LDA JSR OUT2X LDA HL JSR OUT2X INE EW LINE HL 1 LDX PROMPT amp OOFFH JSR P RTS STRING get MOS recor sample MOS re d cord 718 0200 A9018500182600A5008D0080A200A00088D0FDCADOF84C05 09B3 701 0218 02 001D 00 gt gt gt Q 18 is number 0200 is load 954 09B3 is 16 bi ET MOS1 JSR 538 of byte address data byte t check sum CIN Page 7 of 28 MONITOR LST 8 10 2015 6 21 PM 0533 0534 0535 0536 0537 0538 0539 054 054 054 054 054 054 054 054 054 054 0550 0551 0552 0553 0554 0555 0556 0557 0558 0559 0560 0561 0562 0563 0564 0565 0566 0567 0568 0569 0570 0571 0572 0573 0574 0575 0576 0577 0578 0579 0580 0581 0582 0583 0584 0585 0586 0587 0588 0589 0590 0591 0592 0593 0594 0595 0596 0597 0598 0599 0600 0601 0602 0603 0604 0605 0606 0607 0608 C1EB C1ED C1ED C1ED C1ED CIEL CIES C1F6 C1F8 C1F8 ClFA CLEF C202 C204 C204 C207 C207 C20A C20C C20C C20F C20F C21 C21 C21 C21 C21 C21 DO A9 85 85 20 85 C9 FO C 4C 20 C9 DO 8D A5 C9 DO 8D 60 20 0 91 20 8D 20 C6 DO 20 85 20
55. STINATIO SBC HL 1 A OFFSE BY E 1 CHECK IF THE OFFSET BYTE WAS BETWE EN IF IT 7 OE HE OFFSET BYTE IS 0 1 HE OFFSET BY Tode IF BIT 7 OF OTHERWISE OFFSET BYTE D 80H CHK OFFSE gt CHI EC LDA OFFSET BY LDA OFFSE K HIGH BYT T_BYTE HIGH E MUS 1 BNE OUT OFF RA JMP IN RANGE CHK BNE OUT OFF RA GE OFFSET HIGH LDA OFFSET 1 GE STORE OFFSET 2ND BYTE TO THE IN RANGE LDA S STA HL LDA START ADDR STA HL 1 JSR INC HL ART ADDRESS ESS 1 LDA OFFS ET BYTE EXT INTSRUCTION ADDR F E m 128 HIGH BY HIGH BY RANGE ENABLE ESS IT WILL JUMP TO NMI SERVICE FF8 2 ESTINATION START ADDRESS ROM BRANCH INSTRUC 0 TO 127 007F E MUS BE ZERO S E MUS dum E FE ERROR THEN HOW OF BRANCH INSTRUCTION Page 21 of 28 MONITOR LST 8 10 2015 6 21 PM 15 15 15 16 16 16 16 16 16 16 16 16 16 161 16 16 161 16 16 161 16 16 16 19 97 98 99 00 0
56. T RS232C connector DB9 DC jack 9VDC 5V 014 6ND Fe GAL16VB ot 7805 276256 EPROM 8 12 74 514 Rizr 2 C10 zai 7 164 TICK 2 9 2051 m 42 Sur 74 573 s B7 BS B4 B3 B2 BO OOOO C17 DS 06 07 08 09 010 011 012 6 101 1 P 20 pin Text LCD header Selector for 10ms tick or IRQ key Important Notes 1 Plugging or removing the LCD module must be done when the kit is powered off 2 AC adapter should provide approx 9VDC higher voltage will cause the voltage regulator chip becomes hot 3 The kit has diode protection for wrong polarity of adapter jack If the center pin is not the positive the diode will be reverse bias preventing wrong polarity to feed to voltage regulator KEYBOARD LAYOUT 06 07 08 09 INS RESET 02 03 04 05 REG CBR DEL USER 8 ES ES NV DIZC 00 01 DATA STEP IRQ x 5 o8 ADDR GO REP 6502 Microprocessor Kit HEX keys Hexadecimal number 0 to with associated user registers flag bits and page zero memory 00 to 09 use with key REG CPU control keys RESET Reset the CPU the 6502 will get reset vector from location FFFC and FFFD USER User key for lab test active low IRQ Make
57. TE LDA OFFSET BYTE CHECK RESULT 1 JMP GO STATE10 KEY GO WRITE USER REGISTERS TO STACK AND USE RTI TO JUMP TO USI A STX EY LDA STATE CMP 6 GO 5 6 CMP 8 BEQ GO STATES CMP 10 SHORT GO STATE10 TSX SAVE SP SAVE SYSTEM STACK NOW SWITCH TO USER STACK TXS LDA PHA LDA PHA LDX USER 5 DISPLAY 1 DISPLAY PHA DX iDY USER RTI SINGLE STEP KEY STX TXS STEP TSX SAVE SP SAVE SYSTEM STACK NOW SWITCH TO USER STACK DX USER S LOAD CURRENT PC TO DISPLAY STA LDA STA PHA LDA PHA LDA USER DISPLAY PC_USER 1 DISPLAY 1 LDA DISPLAY 1 DISPLAY USER_P PHA iDX USER_X iDY USER_Y ER PRC Page 20 of 28 MONITOR LST 8 10 2015 6 21 PM A9 FF 8D 02 80 EA EA EA EA EA A5 40 A5 85 A5 85 A5 85 A5 85 20 38 A5 5 85 5 5 1521 682 1522 682 1523 684 1524 C687 1525 C687 1526 C688 1527 C689 1528 C68A 1529 C68B 1530 C68C 581 C68E 1532 C68F 1533 C68F 1534 C68F 1535 C68F 1536 C68F 1537 C68F 1538 C68F 1539 C68F 1540 C68F 1541 C68F 1542 C68F 1543 C691 1544 C693 1545 C695
58. Thus to send receive serial data correctly all interrupts must be disabled CONNECTING LCD MODULE is 20 pin header for connecting the LCD module The example shows connecting the 16x2 lines text LCD module R12 is a current limit resistor for back light R13 is trimmer POT for contrast adjustment The LCD module is interfaced to the 6502 bus directly The command and data registers are located in I O space having address from 9000H to 9003H Be advised that plugging or removing the LCD module must be done when the kit is powered off Text LCD module accepts ASCII codes for displaying the message on screen Without settings the LCD by software no characters will be displayed The first line will be black line by adjusting the R18 for contrast adjustment 13 Here is the example program that prints text 6502 Kit on the LCD screen 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 0060 0061 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0200 0200 0200 0203 0203 0203 0203 0203 0204 0207 0209 020B 020C 020D 020D 020D 020D 0210 0213 0214 0214 0214 0217 021A 021B 021B
59. Y HL 1 DISPLAY 1 DISPLAY LOCATION OF OFFSET STILL_DATA 2 STA RTS OUT_OFF_RANGE STATE LDA 2 BUFFER 5 8FH BUFFER 4 Co C BUFFER 3 Ww C BUFFER 2 C BUFFER 1 BUFFER NMI SERVICE ROUTINE BYTE SAVE CPU REGISTERS TO USER REGISTERS FOR PROGRAM DEBUGGING NMI_SERVICE STA USER_A STA 1 8 BIT DISPLAY WILL SHOW CONTENT OF ACCUMULATI LDA 5 STA 1 TURN OFF BRK SIGNAL STILL WITH USER STACK PLA STA PLA STA STA PLA STA STA USER P DISPLAY PC USER DISPLAY 1 PC_USER 1 USER_Y USER_X JSR USER_S KEY_ADDR DISPLAY LOCATION THAT BRE RESTORE SYST EM STACK LDX TXS RTS SAVE_SP AKE Page 22 of 28 MONITOR LST 8 10 2015 6 21 PM 1673 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 17 171 171 171 4 7 171 TET 171 T3 171 171 74 7 5 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 00 01 02 C 9 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1738 1734 1735 1736 LEST 1738 1739 17 17 17 157 17 17 17 17 17 4 4 4 4
60. ion connector 5 u1 u2 00 00 51 0 o0 D 0 ao Do 5 593 2 Porxo Pio ANO 12 2 o 1 y P1 2 A1 01 D NS 2 A1 01 X P34AIXD M LED 1 NS A2 02 D NS A2 D2 D 84 P3 2IINTO P1 2 TEST POINT x 3 Ad 03 54 Ad 03 54 1 p13 5 Gt 04 18 5 1 5 8 P3AITO 14 6 7 Ns 2 A5 05 Ns A5 05 2 6 x H psig P1 5 ETE 9 AT 6 2 5 AT A6 15 5 P1 6 49 11 x is n is 18 9 4 9 4 UU A9 UU A9 0 44 2 17 AT A10 AT A10 RESET2 1 11 TICK 19 AT 11 15 11 35V RSTIVPP P3 7 21 13 2 12 13 2 12 T 20 23 AU A13 Ad A13 vec 25 14 14 27 ROM RAM _20 29 _ 2 22 AT89C2051 2 1 HIE RAM WR _ 27 om 35 L 5V __ PLD decoder logic 37 27C256 62256 39 814 U4 HEADER 20X2 PHI2 2 2 ROM_CE 00 RW 3 Di Do Am 1 A AN 5 12 n lt GPIO1 03 TEST POINT 12 6 16 D U5 18 LCD E 5 04 45V 4 1 8 PORTO 02 55 da 1 vss RES 40 22521 C PORT2 TVS5V 500123 D7 RDY 2183 aks PHIZ 3 38 18 3 IRQ 50 1MHz 7 VDD 4 11 yog 1k 5 36 BE ABA NMI 6 NC R4 GAL16V8D 5V NMI NC 1k SYNC RW vec 5 SYNC RW 33 DO Y1 OSC 1M MEC1 0 9 32 DiI 5V ESP switch
61. le will b The physical location is the 2nd block of 64kB space Intel hex fil ready for EPROM programmer 00 TO 09 to get back current ac To program the 32kB EPROM we must move it to the 156 block 26 DECEMBER 2014 27 DECEMBER 2014 ADD OUT OF RANGE CHECK FOR RELATIVE BYTE CALCULATION ADD DOWNLOAD HEX FILE TO MONITOR SOURCE 29 DECEMBER 2014 ADD START ESSAGE ON COLD BOOT 30 DECEMBER 2014 TEST SINGLE STEP WITH 7415164 ADD REPEAT KEY LOWER REPEAT SPEED REMOVE ACCUMALATOR DISPLAY ON BREAK 2 JANUARY 2015 REMOVE BINARY DISPLAY IN REGISTER MODE ADD REGISTER MODE DISPLAY FOR 10 BYTES ZERO PAGE 3 JANUARY 2015 PROVIDE PROGRAM COUNTER SAVING FOR SINGLE STEP RUNNING now user may change display address data press PC key to restore it then press step 27 February 2015 lower brightness of the 7 segmen calibrate beep frequency to 523Hz 2 March 2015 add hex file download using MOS hex now the board can accept both In no error 21 March fix cold boot message HH Hd Hi od d LOCATION 00 TO 7F ARE 128 BYT the will display 0 mak tel CR format and MOS hex file format if error it will show 01 he I O ports zero register defi
62. nition ES FOR Tested beep on cold boot USER PROGRAM TESTING zero page memory definitions for monitor use address of t GPIO1 EQU 8000 PORTO EQU 8001 1 EQU 8002 2 EQU 8003 DIGIT EQU 8002 SEG7 EQU 8003 KIN EQU 8001 pag DSEG ORG 80H REG F BLOCK 1 REG D BLOCK 1 REG B BLOCK 1 REG C BLOCK 1 HL BLOCK 2 DE BLOCK 2 REG A BLOCK 1 Page 1 of 28 lt ITOR LST 8 10 2015 6 21 PM 077 0089 078 0089 ERROR BLOCK 1 ERROR FLAG FOR INTEL HEX FILE DOWNLOADINC 079 008A BCC BLOCK 2 BYTE CHECK SUM 080 008C BUFFER BLOCK 6 8BH 90H PAGE ZERO DISPLAY BUFFER 081 0092 INVALID BLOCK 1 INVALID KEY HAS BEEN PRESSED FLAG BIT 082 0093 0 VALID 083 0093 1 INVALID 084 0093 085 0093 KEY BLOCK 1 086 0094 STATE BLOCK 1 087 0095 ZERO FLAG BLOCK 1 ZERO WHEN HEX KEY PRESSED FOR ADDRESS OF 088 0096 089 0096 DISPLAY BLOCK 2 display address 090 0098 091 0098 PC USER BLOCK 2 FOR SAVING CURRENT PC ON RESET IT SETS TO 092 009A USER A BLOCK 1 093 009B USER X BLOCK 1
63. ote kswichit kmitl ac th 2014 Title 6502 MICROPROCESSOR KIT Size Document Number Rev B Doc 1 Date Saturday January 03 2015 Sheet 2 of 3 Di 01 02 53 02 03 5 05 05 u14 D7 De D7 0 10 2 20158 3b 4p 4018 sb sa 8D 80 lag cc H 9 20 05 06 07 08 D9 Did 014 012 74HC573 wv X YR SS ROR 16x2 text LCD interface D13 6 1N5236A JR LAG 5 L7 4 2 49 7 8 bit Binary display LED x8 16 15 15 aa by 14 13 Do 13 12 D5 5 12 Mi D4 11 D3 9 02 jour 10V 10uF DT C12 8 7 00 f 015 6 8 LCD E E 5 R W A1 2 c H 5 RS AD lt mo VB1 amp 3 1 4 2 2 C2 H 1H i ets 8 o _ tour o TOUT I TD CONN RECT 16 1 5 1 E 190 TUN 2 2 1 3 OF X R13 SUB D 9 Male cross cable MAX232A 1
64. ter A Another sample is with JUMP instruction The JUMP instruction will change the Program Counter to 0200 to repeat program running Now we use zero page at location 0 to be the byte to be incremented After incrementing we load it to register A then write to location of GPIO at 8000H And with JMP LOOP instruction the program will be repeated Address Hex code Label Instruction comment 0200 00 LOOP INC 0 Increment location O 0202 A5 00 LDA 0 Load A with location O 0204 8D 00 80 STA 8000 Write A to 8000H 0207 AC 00 02 JMP LOOP Jump back to loop Again enter the hex code to memory and test it with single step Now press key STEP and key REP together Every time when instruction STA 8000 was executed did you see the binary number counting We will learn more the use of GPIOI with 6502 Programming Lab Book CONNECTING 6502 TO TERMINAL For LOAD key we can connect the 6502 kit to a terminal by RS232C cross cable You may download free terminal program teraterm from this URL http ttssh2 sourceforge jp index html en RS232C cross cable VT100 Terminal 6502 Kit The example shows connecting laptop with COMI port to the RS232C port of the 6502 kit New laptop has no COM port we may use the USB RS232 adapter for converting the USB port to RS232 port To download Intel or MOS hex file that generated from the assembler or c compiler set serial port speed to 2400 bit
65. using timer0 interrupt in 89C2051 chip The active low tick signal is sent to P3 7 For tick running indicator P1 7 drives D1 LED ESP switch SW1 11 Tick is 108 periodic signal for triggering the 6502 IRQ pin When select SW1 to Tick the 6502 CPU can be triggered by a maskable interrupt The 100Hz tick or 10ms tick can be used to produce tasks that executed with multiple of tick The 6502 kit lab look will show how to use 10ms tick to make a digital timer gt 10ms 10ms 10ms RS232C PORT The RS232C port is for serial communication We can use a cross cable or null MODEM cable to connect between the kit and terminal or kit 1 to kit 2 for sending or receiving hex file The connector for both sides are DB9 female We may build it or buying from computer stores For new PC or laptop computer with USB port we may have the RS232C port by using the USB to RS232 converter DATA FRAME for UART COMMUNICATION Serial data that communicated between kit and terminal is asynchronous format The 6502 kit has no UART chip instead it uses software controlled to produce bit rate of 2400 bit s The data frame is composed of start bit 8 data bit and stop bit For our kit period 1 2400 417 microseconds period 1 Baud Rate Stat Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit Stop Bit Eb msb Bit Since bit period is provided by machine cycle delay
66. y adding more function keys utility subroutines The monitor program can be tested in RAM and the move to ROM chip by using the EPROM programmer The procedure of modifying the monitor program is as follows 1 Set the code segment to 1000h so the hex file can be tested in RAM 2 Use TASM with command d 6502 tasm 65 monitor asm 3 The object file will be hex file download to the kit and test run 4 If it works fine then change code segment to 0c000h for ROM 5 The physical address will occupy last block of 64kB space 6 Our EPROM is 32kB so we must move the hex code from 2nd block to the first block Then program the EPROM ogical space Physical space OO000H O00 0H 4 27 C256 32kB EPROM Reset vector 8000H 5000 Reset vector 17 HARDWARE SCHEMATIC and PARTS LIST GND D 0 7 77 gt A O 7 Ri 0xC000 0xFFFF 0x0000 0x7FFF 32kB Programmable system tick 680 Monitor Program 5 rd 1 expans
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