Logic Analyzer
Contents
1. 7 Each frame begins with a start bit which is Active High m Data Shift Offsets Discard 0 bit s of data before beginning to interpret Each value Discard 0 bits of data after Each value has been interpreted Mode 0 CPOL 0 CPHA 0 Clock active High Data sampled on Rising edge Glitch filter clock pulses with a duration of less than 1 000E 6 seconds Setup e Should look like this EE Intronix LogicPort Logic Analyzer C Program Files LogicPort Projects MSP430_SPI LPF i f x File Options Setup Acquisition View Help EENE State List Notes D Gd amp itt ES pa Tk Rk a QQ Al Butter Postion el cd Sample Rate M 500KHz x Logic Threshold x 1 40v Pre Trigger Buffer isa 50 Kil i fiz 4 4 Eil e Notice the Edge A has already been set as the rising edge of SDO Data0 Hardware Setup Attach wires to appropriate pins b xsd 3 J bien i S A single Acquisition e Click on the little green arrow and hopefully you get something like this Sianal Wire Wire Pattern Edge Cursor igna ID Status A A A iia SPI spo vo T x f scik o T X ss v2 ex CLK1 Freq OHz D3 Period 2 94351us Interval T gt C 0 D1 Transitions A gt B 0 MSP430_SPI_LPF 12 9 2011 2 17 40 PM e Happily this is what expected Use the cursors e f place the c2. Logic Analyzer Intronix Logicport 34 Channel Logic Analyzer LogicPort Setup e You will need e Intronix LogicPort logic analyzer from now on referred to just as the logic analyzer e LogicPort software installed on your computer http www pctestinstruments com downloads htm e Something to test microcontroller simple logic chip Information from Intronix e Main Website e http www pctestinstruments com e Help in the LogicPort software e Super helpful most of the time e Tutorials and specifics of all the menus options etc e Help gt Contents or just hit F1 or the question mark icon e Example setups signals groups pretty colors e File gt Open gt C Program Files LogicPort Projects Examples LogicPort Basics Logic Analyzer Intro e 38 total wires e 34 data channels rainbow wires e 2 clock channels white wires e 4 ground channels grey wires e Up to 500MHz sampling rate e Input impedance 200K ohms e The box holds an FPGA which does all of the sampling Logic Analyzer Intro e Alogic analyzer only works on digital signals HIGH or LOW e It is good for debugging logic circuits including microcontrollers logic chips ADC converters etc e Most logic analyzers work in the following manner e Set up the voltages for high and low states e Set up a the trigger situation e g a signal going from high to low a parallel bus being
3. as Sample Mode Setup om Trigger Setup Measurement Setup 7 Acquisition Modes e Single acquisition wait for trigger then take one acquisition e Continuous acquisition wait for trigger then keep taking samples e Stop to get out of continuous acquisition e Trigger immediate take a full sample buffer now regardless of trigger situation k x 4 Quick Travel a Zoom In Out Fit Software Views e Two main views waveforms and state list EE Intronix LogicPort Logic Analyzer C Program EE Intronix LogicPort Logic Analyzer C Program File Options Setup Acquisition View Help File Options Setup Acquisition View Help fae State List Notes D0 Egg i Waveforms State List Notes D E amp i SampeRae 100MHz Relative to Reference Data0 Datal Data2 Di 32 049 090ns 1 0 1 4 gt peace aj OO 30 044 470ns 0 Signal Wire Wire Pattem Edge 30 044 465ns 0 D Status A A 30 044 460ns 0 Clock1 CLK1 L x 30 044 450ns 0 Clock2 wA L xX Aii an aa 30 044 430ns Data 31 0 30 044 420ns 0 Data bo bt xX Ft 28 037 275ns Hm Datal D aaa 18 029 455ns ee Ras Data2 D2 L x 16 024 830ns 1 Data3 D3 L x 16 024 825ns 1 Data4 D4 L x C 14 020 200ns oe A A 14 020 195ns 0 Dated D a _ 714 020 130ns 0 Data6 DG L x 14 020 185ns 0 e Same data one is in graphical format one is a table format Waveform View Columns e You can add remo
4. say OK e You can now see the interpreter and its associated signals Cursors e Useful for the measurements time between two events or looking at the data at certain times Cursor A column shows the data where cursor A is located e You can click and drag any of the six cursors e Right click in the waveform or state list window gt place cursor or scroll to cursor e Note hit A to go to the A cursor or T to go to the trigger event Getting Data Out e Couple of options e Image Ctrl I File gt Print to Clipboard e CSV file Ctrl D File gt Export Data e Print Ctrl P File gt Print Troubleshooting e The analyzer is not triggering e Is the voltage level set correctly for your signal e Do you actually have a trigger setup on the correct signal s e Is your sample rate high enough e The analyzer is triggering but nothing shows up e Is you sample rate high enough or is it too high e The sample rate could be to high and you are just not seeing enough time to see the result after the trigger Troubleshooting e The interpreter shows nothing or it is wrong e Are all the signals appropriately assigned to their interpreter counter part Right click interpreter edit interpreter e Is your frame synchronization method appropriate for the setup For example if your enable never changes always enabled you should not use the Enable signal
5. going to call mine MSP430_ SPI e We don t neea al of meee signals so remove them all E 7 Example e The code has SCLK on pin P1 5 and SDO data out on pin P1 6 e So need 3 signals the default names will be used until rename them e Data0 gt SDO e Data1 gt SCLK e GND gt GND e Since the interpreter also expects an enable signal will also connect Data2 gt GND just so it isn t doing weird things but it won t be used Example e So in my window want to setup a couple of things e Setup the sample mode e Setup the trigger mode e Sampling rate e Logic threshold e Add an interpreter sample Mode e Timing Mode will be fine for this application Sample Mode Setup E Timing Mode Internal Sample Clock State Mode External Sample Clock Sample data on the Rising edge of T Sample only when qualifier CLK2 is High 7 Base time scale on a clock J Frequency Pre Fill Time Limit 0 5sec 7 Post Fill Time Limit 05sec Apply J Enable Compression Trigger Mode e will be letting the edge of a clock be the trigger mechanism so can set up the following conditions Trigger When level is satisfied D Prequalify Pattem Value Terms Level conditions IV Edge A o
6. more useful e Put signals groups in a reasonable order Don t put stuff in strange order data 5 data 0 data 6 Signal Wire Wire Pattern Edge Cursor 200ns 151 ID Status A A S mm ool bon ee Datat D1 C 0 BAD 2e D2 Data Daas 0 pata D3 Daas D5 Data6 DE Data D7 Ca c a a a al X X X X X XX xX You can reorder stuff by just click and draging on the signal or group Reordering and Renaming e Acouple of things will make your setup more useful e Rename your signals groups to something more useful If one of you signals is an enable signal rename it EN to make it easier to figure out what is going on instead of trying to remember if Data3 or Data4 is the enable signal e Right click on the signal or group and click on Edit J Sig nal Penn Sianal Wire Wire Pattern Edge Cursor ID Status A A A Data DO L Datal Di l Date Insert Signal 7 Insert Group Insert Interpreter z Remove Signal Waveform Color gt Group Settings e If you right click on a group you will see some group settings e Format How the signals will be interpreted Number base such as binary hex or decimal 2 s compliment or not Switch MSB or LSB order e Order Which bit is displayed at the top of the group This only changes the way it is displayed not the way it is interpreted e Style Interpret the
7. bits as a analog value See the examples for examples Slide 3 e Color You can change the color Woo ata D7 L x ital7_ 01 Insert Signal Insert Group Insert Interpreter Edit Group Remove Group Data Format Binary Display Order gt Decimal Waveform Style gt yw Hex Waveform Color gt Signed 2 s Compliment y Wire MSB gt Data MSB Wire LSB gt Data MSB software Setup e Every time you intend to make a set of measurements you need to set up e sample mode e triggering condition e sample rate e logic threshold e Optional e Measurement setup e Pre trigger buffer sample Mode e Select one of two different modes e Timing mode Use the internal clock sampling rate is chosen using the sample rate drop down menu on the main screen e State mode Use an external line to say when to sample this doesn t have to be a clock necessarily Sample Mode Setup Timing Mode Internal Sample Clock C State Mode External Sample Clock Sample data on the K I Sample only when qualifier CLK2 is cLKi z v Rising edge of High Enable Compression Pre Fill Time Limit 0 5sec Post Fill Time Limit 0 5sec Apply sample Mode e Timing Mode e Sampling is driven by an internal clock 100kHz gt 100K samples per second e That sampling sp
8. ccurs 1 time s T Pattern A is True z F For duration Greater than Level B conditions IV Edge B occurs 1 time s T Pattern B is True z F Value of Data 15 0 is to 100h For duration Less than Sampling Rate and Logic Threshold e know my SPI clock will be going at about 100KHZz so need at least a sampling rate of 200KHz e set it to 500KHz just to be safe e am on a 3 3V system so will set the logic threshold to about 1 2 of that 1 4V Sample Rate 7 500KHz Logic Threshold 7 1 40 uj gt KI J gt e The standard 50 Pre Trigger buffer will be fine for now e m not going to mess with any of the measurements now Add an Interpreter e want SPI so will make a new interpreter for SPI which has the following settings Notice the Frame Synchronization Method and the Mode Since my enable signal will always be low can t use enable signal enters active state also renamed the signals to make it easier to read Name cC Data Signal soo et Clock Signa SCLK its Enable Signal ss o Enable Signal is ActiveLow Data is transferred MSB Fist gt Interpret 3 bits as Hex Synchronous Serial SPI Interpreter Settings m Frame Synchronization Method Enable Signal enters active state Clock is inactive for a duration of atleast 1 000E 5 seconds Position of Cursor
9. eed is chosen in the main window under using the Sample Rate drop down box see sample rate slide pr of every signal will be taken at this predefined rate e State Mode e Sampling is driven by user defined settings and an external signal e The signal can only be from the CLK1 wire or the CLK2 wire e Which one you choose depends on what you are looking for sample Mode Compression e The compression feature allows the buffer to hold more useful data e When compression is enabled the buffer will only hold data when transitions are detect and fill in the static data in between later e The suggestion is to always have this on Triggering Setup Lele e The trigger determines when the buffer is sent to the computer e Lots of choices e The default is usually enough Trigger Setup Signal ye Pde A Edge Trigger When level A is satisfied Prequalify Pattem Value Terms Clock1 iam L o0 Clock2 oreg L Ee Ess Data sl eae Semel pa a e o Datal D1 L Se rr Data2 D2 L Ez EE ee paea o ef x y o paas os if xi o Data6 De EE gt Ss Data p7_ _L SS a Dated coq E Naena 1 n Trigger Setup e You have two sets of conditions that you can specify A and B e Each condition can be a edge of a signal a state of a bus or timing of a bus e Additionally you can say now the two conditions will effect the trigger Trigger When le
10. en interpreted Mode 0 CPOL 0 CPHA 0 Clock active High Data sampled on Rising edge J Glitch filter clock pulses with a duration of less than 1 000E 6 seconds Interpreter Example e Rename the signals click on the signal ana C m Frame Synchronization Method n a m e t h e n n th e Paoi Mso Enable Signal enters active state n ew WI n d OW rl g ht Tet Sirk sek Clock is inactive for a duration of cl ick O n th e S j g n al Enable Sinat sS at least 1 000E 5 seconds Position of CursorA gt o The SPI bus will be Enable Signalis ActiveLow ae TET O e r ati n g j n m O d e Data is transferred MSB First wi j all a start bit p Interpret 8 bits as Hex Z jii s Saaana A Ji SO change the mode m Data Shift Offsets at th e botto m of th e Discard o bits of data before beginning to interpret Each value Wi n d OW Discard o bit s of data after Each value has been interpreted e O u r fra m e Mode 1 CPOL 0 CPHA 1 Clock active High Data sampled on Falling edge Sy n C h ro n l Z ati O n T Glitch filter clock pulses with a duration of less than 1 000E 6 seconds method should be fine so leave it as is Interpreter Examples e Click OK to go back to the interpreter selection window e Note you can delete an interpreter by right click on a selected interpreter e Click on the newly created SPI interpreter and
11. enters active state for the synchronization method e Do you have the correct settings such as active low high enable signal MSB or LSB transfer order baud rate number of bits etc This changes drastically for the different protocols Other Resources e ECEN 5613 LogicPort Introduction e http ecee colorado edu mcclurel LogicPortAnalyz erNotes 4 30 2011 pdf SPI Example with MSP430 Example e Using e LogicPort analyzer and software e MSP430 LaunchPad which has the MSP430G2231 e CodeComposer v4 Example e From the code example we are going to just program the master Slave Master MSP430G2x21 G2x31 MSP430G2x21 G2x31 Pf ee tiene ec XIN XIN XOUT RST XOUT RST NMI lt P1 2 LED lt P1 0 P1 4 lt gt P1 4 P1 0 gt LED SDI P1 7 lt P1 6 SDO SDO P1 6 gt P1 7 SDI SCLK P1 5 lt P1 5 SCLK Example e Step 1 think about what you expect e The code am working with will generate a SPI communication packet at something around 100KHz e The signal will be a OV 3 3V signal e The SPI will be in mode 0 and have no chip select slave select signal e Knowing these lets set up out environment Example e Since will want to use this setup again I m going to make a new file File gt New e m
12. equal to 0x40 etc e When the trigger situation occurs display the buffer e In a logic analyzer samples are being taken at certain rate which fill up a buffer This buffer is then displayed for the user to look at Ground Channels e 4 ground channels grey wire with black tip e You should always use a ground channel e General rule use one ground wire per 8 data wires e Not grounding the logic analyzer will usually give you crappy results e The reference voltage for the sampling is in effect floating Data Channels e 32 data channels e The grey and white wires are NOT data wires e The wires colors and tip colors match with the wire ID colors displayed in the software e Black wire with a white tip is DO the black letters with white background Signal bt Pah Borat a Cursor A Clock1 CLK1 L x 0 Clock2 CLK2 L x 0 Data 31 0 Oh DataD L x t 0 Datal D1 L x 0 Data2 D2 L x 0 Data3 D3 L x 0 Data4 D4 L x 0 Data5 D5 L x 0 Data6 DG L x 0 Data D7 L x 0 Data8 L x 0 aa 1 v n Clock Channels e 2 Clock Channels white wires CLK1 CLK2 e Used for two main reasons e Determine a clock frequency using the logic analyzer e OR e Use the external clock source to decide when to sample see the sampling section for more information e You don t always need a clock source the logic analyzer has an internal clock source Software Overview Software Tool Bar
13. r CAN interpreters e Similar to groups you can e Have multiple interpreters but not two of the same exact one but you can have two of the same kind e g two RS232 interpreters you just need to make another one so RS232_A and RS232_B e Create new interpreters Interpreter Example e Lets make a new interpreter e Right click gt Add Interpreter gt Create gt SPI e Rename it to useful SPI or MSP430 SPI e You can change the signals assigned to the interpreter signals just click on the names e For any interpreter always check all these setting to make sure they match up with what your protocol should be doing e Synchronization is very important or else the interpreter will get confused on when to start interpreting this is a usual area of trouble Name Newlnterpreter7 Data Signal Datad tits Clock Signal Daal ts Enable Signal Daa2 Enable Signal is ActiveLow Data is transferred MSB Fist gt Interpret 3 bits as Hex iv Synchronous Serial SPI Interpreter Settings m Frame Synchronization Method Enable Signal enters active state Clock is inactive for a duration of atleast 1 000E 5 seconds Position of Cursor Each frame begins with a start bit which is Active High m Data Shift Offsets Discard 0 bit s of data before beginning to interpret Each value Discard 0 bit s of data after Each value has be
14. re and a group a set of wires can be added or taken away by right clicking in the open area below the signals e Agroup or signal can be taken away by right clicking on the signal or group Data Signal Clock1 Clock2 Data 7_ 0 Add Column gt Add Signal Add Interpreter Signal Column Only Expand All Collapse All Remove All Sianal Wire Wire Pattern Edge Cursor gna ID Status A A A Clock1 H Clock2 H Insert Signal Insert Group Insert Interpreter Edit Group Data Format Display Order Waveform Style Waveform Color Signals and Groups e Default groups are 8 bit 16 bit and 32 bit groups Starting from the DataO signal and going up e You can create your own group if you for example needed a 12 bit bus Add Group gt Create button e You can have multiple groups which use the same signals but not the same group twice e You can use a group that has signal DataO and then also have Data0 be its own signal 8 bit parallel bus which is looked at using the Data 0 7 group You can collapse the group by clicking the little minus sign Groups e Groups are useful when looking at parallel data buses because the software will interpret the data for you you don t have to do the bit to hex conversion Reordering and Renaming e Acouple of things will make your setup
15. stem Measurement Setup aE e You have four different measurements you can use which are displayed at the bottom of the window CLK1 Freq OHz D3 Period gt 100ms Interval T gt C 500ns D1 Transitions gt B 0 e You can change what they are and how they are calculated by using the measurement setup screen e The in software help is useful if you want to know more Measurement A Frequency From Hardware Counter Measurement B Period From Hardware Counter Pre Trigger Buffer e What portion of the buffer should be viewable before and after the trigger event Pre T rigger Buffer r 50 E e f the pre trigger buffer is 50 the buffer displayed will have the trigger event in the middle of the buffer data e If itis at 7 7 of buffer data will be before the trigger e Note compression will significantly change how this works though since buffer usage Is calculated after compression Interpreters Interpreters e Interpreters are e Awesome things which will save you lots of time e The software is able to look at the data and interpret it using certain communication protocols e To use one right click on the area under your signals Add Column gt Add Signal Add Group Signal Column Only Expand All Collapse All Remove All Interpreters e You have a couple of options e 12C SPI RS232 o
16. ursor A at a rising edge of a clock and cursor B at the next rising edge can figure out what the SPI clock frequency is Measurement Frequency From Hardware Counter Measurement B Period From Hardware Counter CLK1 Freq OHz D3 Period 2 93669us Interval T gt C 0 Rate A gt B 71 4285KHz MSP430_SPI LPF 1279 2011 2 20 05 PM
17. ve columns by right clicking on the column names e Useful for more advanced triggering looking at cursor values etc EE Intronix LogicPort Logic Analyzer C Program Files LogicPort Projects New LPF File Options Setup Acquisition view Help Waveforms State List Notes 0E 4 it eB gt Ga T k k Sample Rate 100MHz 7 Logic Threshold I 4 mm Ue Er 1 Wire Wire Pattern Edge 5 ignal iD Pale Tire A oUUns bUUn Reference so Clock1 CLK1 H x Set Column gt Pattern gt Clock2 nem H X Remove Column a gt Data 31_ 0 ES cee cioe ua Baa DataD DO H x Wire ID Datal 1 ae 0 poise Data2 D2 H x 0 setting Up an Acquisition software Setup e Creating a new file e Adding taking away signals e Adding taking away groups e Renaming signals groups e Group settings e Format e Order MSB LSB e Analog Digital e Color New Setup e You will want to create a new setup which is called a new file e This file if you save it will keep all of your settings logic threshold number and choices of signals groups interpreters and interpreter settings colors etc e You can then reload the file when you want to get the same setup back e Usually you will want to remove the standard group Data 31 0 and the clock signals and then add back only what you want Signals and Groups e Asignal a single wi
18. vel A is satisfied v J Prequalify Pattern Value Terms i uisiti Trigger Setup e Edge and patterns are defined in the waveform view by click on the related cell e Pattern 0 1 or don t care X e Edge falling rising either or none e Edges are logically OR d so a trigger would occur if the analyzer saw DataO go low OR Data1 go high OR Data2 e ange at all AAA B Clockt m z EJ H Wire Status V ow re eG Trigger When level A is satisfie v T Prequalify Patten Value Terms e Ly Sampling Rate e Since the buffer is a fixed size higher sampling rate gt less actual time is measured e The sampling rate is selected when in timing mode with the use of the drop down box Sample Rate 100MHz Logic Threshold 1 40 E E J gt e Remember Nyquist e Always think about what signal you expect and set the sampling rate accordingly Logic Threshold e The logic threshold determines where the analyzer will detect a high binary 1 at and where it will detect a low binary 0 at e If you set it to 1 4V anything above 1 4V will be 1 any thing below will be 0 Sample Rate 100MH2 gt Logic Threshold r 1 40 4 _ 4 e Again always think about what you expect your signal to be and set the threshold accordingly e g this 1 4V threshold would be terrible for a 5V sy
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