EB420 Converting DSP56001-Based Designs to
Contents
1. voltage NMI is a 10 V high signal BR EXTAL m om IO IO IO 2 2 WT VccC GNDC DSCK OS1 DR DSO DSI OSO BS 0 2 Qe DD DC NMI DCK KOUT Z lt lt lt 2 Qn PLOCK PINIT ground active also acts as WI DSP560PCMDK PRODUCT INFORMATION low and 1001 1002 002 001 002 Signal 132 92 144 88 132 0 53 60 83 M11 K9 A1 54 61 84 N11 L9 A2 5 63 86 N10 M9 A3 58 64 87 M9 L8 A4 60 65 88 N9 M8 A5 61 68 92 M8 M7 A6 65 71 95 N8 L7 7 67 72 96 7 6 8 68 3 97 N6 L6 A9 70 74 98 M6 M5 A10 71 76 00 N5 L5 A11 7 5 L7 01 M5 K5 12 76 78 02 N4 M4 1 77 80 04 N3 L4 14 79 82 06 N2 K4 15 80 83 07 M3 J4 BG 43 43 64 K12 K12 BN 41 62 H13 BR 45 44 65 113 112 BS 43 54 77 K12 N11 CKOUT 123 8 C5 CKP 126 11 B4 DO 81 84 110 1 N2 D1 82 85 L11 M2 M3 D2 85 87 113 12 M2 D3 86 88 114 1 13 04 87 90 116 11 12 D5 88 91 L17 K2 K3 D6 92. zero written as zero Host Vector MSB This bit should always be written as zero on the 001 Setting this bit on the DSP56002 permits selection of one of the second group of 32 Interrupt Vectors MOTOROLA DSP560PCMDK PRODUCT INFORMATION 2 5 The DSP56002 embodies numerous improvements to the DSP56001 design Users migrating from DSP56001 may wish to take advantage of these enhancements in their new designs 21 Hardware Layout 2 1 1 Clock Speed Performance The DSP56001 is available in 20 5 MHz 27 MHz and 33 MHz versions There are no planned speed improvements beyond 33 MHz The DSP56002 is available in 40 MHz and 66 MHz versions Faster speeds are planned 2 1 2 Power Consumption The DSP56002 consumes less power than the DSP56001 In addition a low voltage version of the DSP56002 is available the DSP56L002 operates from 3 3 volt power sources Refer to the DSP56002 L002 Technical Data Sheet 2 1 3 Fully Static Operation The DSP56002 is a fully static device capable of operation down to DC 2 1 4 Clock Out Pin CKOUT The CKOUT pin of the DSP56002 provides the user with a clock source which can be driven by either the core clock or the output of a Low Power Divider LPD This signal has been designed to minimize skew between external peripheral clocks and the core 2 1 5 Phase Locked Loop PLL The PLL is a new feature that has been added to the DSP56002 It all
3. FW WwW 5 7 25 B8 C9 1 2 6 24 A8 9 2 1 4 22 9 6 8 26 9 10 8 10 28 10 B10 HR W 9 12 30 All D9 HREQ 10 13 31 B10 C10 123 121 6 B5 121 120 5 4 2 123 121 6 B5 121 120 5 4 C2 MODC 119 4 D5 NMI 121 119 4 4 D5 050 53 76 11 051 50 71 N12 PBO 25 24 44 D12 Ell 22 23 43 C13 D11 2 20 21 41 12 CEL PB3 19 19 39 B13 E10 4 16 18 38 12 D10 5 15 17 35 A13 B12 PB6 14 15 33 A12 A11 PB7 11 14 32 B11 B11 PB8 5 7 25 B8 9 9 2 6 24 8 9 PB10 1 4 22 9 11 9 12 30 11 9 PB12 8 10 28 10 10 PB13 10 13 31 B10 C10 14 6 8 26 9 10 27 25 45 D13 C12 1 28 26 46 13 012 2 29 28 48 13 12 31 29 49 F12 F11 40 35 56 K13 G12 PC5 37 32 52 H13 F13 PC6 32 31 Su G13 F12 42 38 59 912 G13 PC8 39 33 53 J13 G11 PCAP 128 13 B6 PINIT 131 16 C7 PLOCK 130 15 B7 PS 52 59 82 N12 M10 RD 47 47 68 112 10 RESET 124 125 10 5 B3 RXD 2 25 45 D13 C12 SCO 31 29 49 F12 Fil 22 DSP560PCMDK PRODUCT INFORMATION MOTOROLA SGL 40 SC2 37 SCK 32 SCLK 29 SRD 42 STD 39 TLO TXD 28 VccC VccCK VccD 100 VccD 101 VccD VccH 12 VccH T3 VccN 63 VccN 64 VccN VccQ 35 VccQ 36 128 129 Vecs
4. MOTOROLA ory EBA20 D Rev SEMICONDUCTOR mmm ENGINEERING BULLETIN EB420 Converting DSP56001 Based Designs to the DSP56002 This document details the differences between the DSP56001 and DSP56002 that need to be taken into consideration when redesigning a system based on the DSP56001 to use the DSP56002 The differences fall into two major categories changes which must be addressed by the user and enhancements which the designer may elect to implement Please refer to the DSP56001 and DSP56002 Technical Data Sheets and their associated documentation for complete information A list of all associated documents is contained in Appendix A 1 REQUIRED CHANGES 11 Hardware Layout 1 1 1 Pinout The physical pinout of the DSP56001 is different from the DSP56002 This means that it is not possible to directly replace a DSP56001 with a DSP56002 without changing the board layout Please refer to the DSP56002 Technical Data Sheet for details of the device pinout For comparison purposes Appendix B of this document contains a table comparing the pin assignments of the DSP56001 packages to the DSP56002 packages 1 1 2 Packaging The DSP56001 is available in 3 package types PGA 88 pin 132 pin 132 pin The DSP56002 is also available in 3 package types PGA 132 pin 132 pin TOFP 144 pin Note that the PQFP has plastic tabs located at each corner The layout must accommodate these tabs and avoid p
5. 84 37 85 87 113 D2 86 88 114 D3 87 90 116 D4 88 91 117 D5 89 nc 90 99 125 GNDD 91 92 118 GNDD 92 93 119 D6 93 94 120 D7 94 95 121 D8 95 nc 96 96 122 D9 97 100 126 010 98 99 101 128 011 100 113 140 VCCD 101 102 129 VCCD 102 103 130 D12 103 nc 104 104 131 D13 105 106 133 D14 106 107 134 D15 107 nc 108 108 135 D16 109 109 136 D17 110 nc 111 105 132 GNDD 112 110 137 GNDD 113 111 138 D18 114 112 139 D19 115 114 141 020 116 117 118 115 142 021 119 117 2 022 120 118 3 D23 121 120 5 MODB IRQB NMI 122 nc 123 121 6 MODA IRQA 124 125 10 RESET 125 nc 126 132 17 XTAL 16 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 127 1 19 EXTAL 128 97 123 VCCQ 129 66 89 VCCQ 130 67 90 GNDQ 131 98 124 GNDQ 132 nc 5 23 GNDH 11 29 GNDH 27 47 GNDS 30 50 VCCS 34 54 GNDS 39 60 TIO 41 62 BN 42 63 WT 45 66 VCCC 48 69 GNDC 50 71 DSCK OS1 51 74 DR 52 75 DSO 53 76 DSI OSO 54 77 BS 56 79 GNDN 58 81 VCCN 86 112 GNDD 89 115 VCCD 116 143 GNDD 119 4 MODC NMI 122 7 GNDCK 123 8 CKOUT 124 9 VCCCK 126 11 CKP 127 12 VCCP 128 13 PCAP 129 14 GNDP 130 15 PLOCK 131 16 Notes indicates the signal is asserted when the voltage ground active low NMI is a 10 V high signal on the 56001 only nc no connection 001 002 002 PV 132 132
6. H7 11 14 32 B11 B11 HAO 5 7 25 B8 C9 HA1 2 6 24 A8 B9 HA2 1 4 22 A7 A9 HACK 6 8 26 A9 A10 HEN 8 10 28 A10 B10 HR W 9 12 30 11 09 HREQ 10 13 31 10 10 IRQA 123 121 6 85 IRQB 121 120 5 A4 C2 MODA 123 121 6 B5 C3 MODB 121 120 5 4 2 MODC 119 4 D5 NMI 121 119 4 A4 D5 050 53 76 M11 OS1 50 71 N12 PBO 25 24 44 D12 E11 PB1 22 23 43 C13 D11 PB2 20 21 41 C12 C11 19 19 39 B13 E10 PB4 16 18 38 B12 D10 PB5 15 17 35 A13 B12 PB6 14 15 33 A12 A11 PB7 11 14 32 B11 B11 PB8 5 7 25 B8 c9 PB9 2 6 24 A8 B9 PB10 1 4 22 A7 A9 PB11 9 12 30 A11 D9 PB12 8 10 28 A10 B10 PB13 10 13 31 B10 C10 PB14 6 8 26 A9 A10 PCO 27 25 45 D13 C12 PC1 28 26 46 E13 D12 PC2 29 28 48 F13 E12 31 29 49 12 11 40 35 56 K13 G12 PC5 37 32 52 H13 F13 6 32 31 51 G13 12 DSP560PCMDK PRODUCT INFORMATION 11 PC7 42 38 59 412 G13 PC8 39 33 53 J13 G11 PCAP 128 13 B6 PINIT 131 16 C7 PLOCK 130 15 B7 PS 52 59 82 M10 RD 47 47 68 12 10 RESET 124 125 10 5 B3 RXD 27 25 45 D13 12 SCO 31 29 49 F12 F11 SC1 40 35 56 K13 G12 SC2 37 32 52 H13 F13 SCK 32 31 51 G13 F12 SCLK 29 28 48 F13 E12 SRD 42 38 59 12 G13 STD 39 33 53 J13 G11 TIO 39 60 11 TXD 28 26 46 E13 D12 VCCC 45 66 M13 VCCCK 124 9 B2 VCCD 100 89 115 G3 C1 VCCD 101 102 129 J1 VCCD 113 140 M1
7. WR 46 WT 45 X Y 48 XTAL 126 nc 3 nc 4 nc 7 nc 17 nc 18 nc 21 nc 26 nc 30 nc 38 nc 41 nc 44 nc 50 nc 51 nc 59 nc 62 nc 66 nc 69 nc 72 nc 78 MOTOROLA 35 32 31 28 38 33 39 26 45 124 89 102 113 20 58 69 79 127 37 66 97 30 46 42 55 132 40 49 56 52 51 48 59 53 60 46 66 115 129 140 27 40 81 93 103 T2 20 58 89 123 50 67 63 78 T3 18 36 37 55 61 70 72 73 91 108 109 127 144 DSP560PCMDK PRODUCT INFORMATION at aa Ra M WwW Ww G3 29 18 C6 G12 M13 L13 N13 A6 E 0 2 40 w w gt W N WN ON N 23 83 84 89 95 98 103 107 110 116 117 122 125 132 Notes indicates the signal is asserted when the voltage ground NMI is a 10 V high signal on the 56001 only no connection 24 DSP560PCMDK PRODUCT INFORMATION active low MOTOROLA is a trademark of Motorola Inc All product and brand names appearing herein are trademarks or registered trademarks of their respective holders Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular pur
8. 144 MOTOROLA Signal 001 FC FI 132 002 1002 E FC PV Signal 132 144 DSP560PCMDK PRODUCT INFORMATION 17 Name Name CQFP CQFP Pin Pin Pin Pin Pin Pin 1 4 22 2 10 84 37 2 6 24 1 9 85 87 113 2 3 40 61 86 88 114 D3 4 49 70 ne 87 90 116 D4 5 7 25 88 91 05 6 8 26 HACK PB14 89 7 91 90 99 125 GNDD 8 10 28 HEN PB12 94 92 118 GNDD 9 12 30 HR W PB11 92 93 119 D6 10 13 31 HREQ PB13 93 94 120 D7 11 14 32 H7 PB7 94 95 121 D8 12 20 40 VccH 95 nc 13 9 21 VccH 96 96 122 D9 14 15 33 H6 PB6 97 100 126 D10 15 17 35 H5 PB5 98 16 18 38 4 4 99 101 128 D11 17 108 100 143 140 VccD 18 109 nc 101 102 129 VccD 19 19 39 H3 PB3 102 103 130 D12 20 21 41 H2 PB2 103 21 127 104 104 131 D13 22 23 43 105 106 133 014 23 16 34 GNDH 106 107 134 D15 24 22 42 GNDH 107 25 24 44 108 108 135 D1 26 73 109 109 136 D1 27 25 45 RXD PCO 110 28 26 46 TXD PC1 111 105 132 GNDD 29 28 48 SCLK PC2 112 110 137 GNDD 30 18 113 111 138 018 31 29 49 SCO PC3 114 112 139 019 31 SCK PC6 115 114 141 D20 33 3 21 GNDQ 116 34 36 57 GNDQ 117 35 37 58 118 115 142 D21 36 2 20 119 117 2 022 37 32 52 5 2 5 120 118
9. 3 D23 38 55 na 121 120 5 MODB IRQB NMI 39 33 53 STD PC8 122 40 35 56 SC1 PC4 T3 121 6 MODA IRQA 41 72 124 125 10 RESET 42 38 59 SRD PC7 125 nc 43 43 64 BG BS 126 132 17 XTAL 18 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 44 45 44 46 46 47 47 48 55 49 57 50 T 51 52 59 53 60 54 61 55 70 56 62 5 7 63 58 64 59 60 65 61 68 62 63 79 1 64 69 65 71 66 67 72 68 73 69 70 74 71 76 1 T2 73 75 74 81 75 77 76 78 77 80 78 79 82 80 83 81 84 82 85 83 Notes On the 56001 MOTOROLA 65 67 68 78 80 44 82 83 84 94 85 86 87 88 92 03 93 95 96 97 98 00 99 105 101 102 104 106 107 110 36 only BG also acts as BS no connection nc BR WT WR RD X Y DS nc nc PS 0 1 GNDN A2 A3 nc A4 A5 nc VccN VccN A6 nc 7 8 9 10 GNDN Q Og gt CORRS 3 1 27 128 129 130 131 132 1 97 66 67 98 11 27 30 34 39 41 42 45 48 50 5il 52 53 54 56 58 86 89 116 119 122 123 124 126 127 128 129 130 134 indicates the signal is asserted when th 19 123 89 90 124 23 29 47 50 54 60 62 63 66 69 71 74 75 76 77 79 81 112 TILS 143 C1 4 gt
10. 56002 supports bootstrapping from the SCI 2 1 12 Demultiplexed Bus Control Signals As mentioned above BR BG BS and WT no longer share pins On the DSP56002 the bus arbitration function and the external wait state generation function are no longer mutually exclusive In addition a new pin Bus Needed BN has been added 2 2 Software Application 2 2 1 MOVEP Timing Refer to the discussion above regarding enhanced performance of the MOVEP instructions 2 2 2 Double Precision Multiply Refer to the DSP56000 Family Manual Section 3 Data Arithmetic Logic Unit 2 2 3 Wrap Around Addressing Mode Refer to the DSP56000 Family Manual Section 4 Address Generation Unit and Addressing Modes 2 2 4 Block Floating Point Refer to the DSP56000 Family Manual Section 5 Program Control Unit Section 5 4 2 Status Register 2 2 5 Increased Vector Table Size The DSP56001 supports 32 interrupt vectors P 00 P 3F while the DSP56002 supports 64 vectors P 00 P 7F MOTOROLA DSP560PCMDK PRODUCT INFORMATION 2 2 6 Host Command Register The Host Vector portion of the Host Command Register HCR has been extended to 6 bits in order to support the increased vector table size 2 2 7 Instruction Set Enhancements The following Instructions have been added INC DEC DEBUG DEBUGcc Immediate versions of MPY MPYR MAC MACR Refer to the DSP56000 Family Manual Appendix A Instruction Set Details APPENDIX A Related Documents Com
11. HR W PB11 10 13 31 HREQ PB13 11 14 32 H7 PB7 12 20 40 VCCH 13 9 27 VCCH 14 15 33 H6 PB6 15 17 35 H5 PB5 16 18 38 H4 PB4 17 108 nc 18 109 nc 19 19 39 H3 PB3 20 21 41 H2 PB2 21 127 nc 22 23 43 H1 PB1 23 16 34 GNDH 24 22 42 GNDH 25 24 44 26 73 27 25 45 RXD PCO 28 26 46 TXD PC1 29 28 48 SCLK PC2 30 18 nc 31 29 49 SCO PC3 32 31 51 SCK PC6 33 3 21 GNDQ 34 36 57 GNDQ 35 37 58 VCCQ 36 2 20 VCCQ 37 32 52 SC2 PC5 38 55 nc 14 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 39 33 53 STD PC8 40 35 56 SC1 PC4 41 72 nc 42 38 59 SRD PC7 43 43 64 BG BS 44 nc 45 44 65 BR WT 46 46 67 WR 47 47 68 RD 48 55 78 X Y 49 57 80 DS 50 144 nc 51 1 nc 52 59 82 PS 53 60 83 AO 54 61 84 Al 55 70 94 GNDN 56 62 85 GNDN 57 63 86 A2 58 64 87 A3 59 nc 60 65 88 A4 61 68 92 5 62 63 79 103 VCCN 64 69 93 VCCN 65 71 95 A6 66 nc 67 72 96 7 68 73 97 8 69 70 74 98 9 71 76 100 10 72 73 75 99 GNDN 74 81 105 GNDN 75 77 101 11 76 78 102 12 77 80 104 13 78 79 82 106 14 80 83 107 15 81 84 110 00 82 85 111 D1 MOTOROLA DSP560PCMDK PRODUCT INFORMATION 15 83 36
12. Note that throughout this document is used to indicate that the signal is asserted when the voltage ground active low 2 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 1 1 9 AC Electrical Characteristics The timing specifications of the DSP56002 differ from those of the DSP56001 This is due in part to the superior performance inherent in the design of the DSP56002 The user should evaluate the impact of these differences on a case by case basis The DSP56002 has been designed to operate at higher frequencies than the DSP56001 As a result many DSP56002 signals exhibit faster rise and fall times than the same signals on the DSP56001 These faster edges may generate more radiated noise and EMI and may require more attention to these issues e g the DSP56002 based circuit may require better decoupling Use of the PLL however may reduce the actual radiated noise and EMI Please refer to the DSP56002 documentation 12 Software Application The DSP56002 instruction set is upwardly compatible with the DSP56001 This means that software written for the DSP56001 will generally run unmodified on the DSP56002 There are however certain differences which result from the DSP56002 s enhanced functionality and increased level of performance Users should consider the impact these differences may have on each application 1 2 1 MOVEP to Rn Nn Mn Registers On the DSP56001 there is a pipeline delay when using the MOVEP instruction to change th
13. VCCH 12 9 27 C9 B13 VCCH 13 20 40 D13 VCCN 63 58 81 L8 N4 VCCN 64 69 93 7 VCCN 79 103 9 127 12 5 VCCQ 35 2 20 C6 A2 VCCQ 36 37 58 G12 A4 VCCQ 128 66 89 VCCQ 129 97 123 A8 VCCS 30 50 K13 WR 46 46 67 M13 J11 WT 45 42 63 L13 J12 X Y 48 55 78 N13 K10 XTAL 126 132 17 A6 B8 nc 3 40 1 H12 nc 4 49 18 M12 nc 7 36 nc 17 37 nc 18 55 nc 21 61 12 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 26 70 30 72 38 73 41 91 44 108 50 109 51 127 59 144 62 66 69 72 78 83 84 89 95 98 103 107 110 116 117 122 125 132 Notes indicates the signal is asserted when the voltage ground active low On the 56001 only NMI is a 10 V high signal BR also acts as and BG also acts as 5 nc no connection MOTOROLA DSP560PCMDK PRODUCT INFORMATION Table 5 Pinout to DSP56001 and DSP56002 Signal Name Cross Reference DSP56001 DSP56002 FC DSP56002 PV Signal Name FC or FE 132 pin PQFP 144 pin TQFP 132 pin PQFP Pin Pin or CQFP Pin 1 4 22 HA2 PB10 2 6 24 HA1 PB9 3 40 61 nc 4 49 70 nc 5 7 25 6 8 26 HACK PB14 7 91 nc 8 10 28 HEN PB12 9 12 30
14. 2 93 9 K1 K2 D7 93 94 20 J2 J3 D8 94 95 2 2 D9 96 96 22 H H3 D10 97 100 26 G H2 D11 99 101 28 1 H1 D12 102 103 30 2 G3 D13 104 104 31 E G2 014 105 106 33 G1 20 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 915 016 D17 D18 D19 D20 D21 D22 D23 DR DS DSCK DSI DSO EXTAL DC ZZ ZZZ Hi oe GP t c6 2 ZZZ L Z Z OO 9 59 55 OO EJ OS 2224222422424 Jg UY 106 108 109 113 114 115 118 119 120 49 127 90 91 111 112 23 24 29 56 73 74 33 34 130 131 25 22 20 19 16 15 14 11 107 108 109 57 50 53 52 48 122 86 92 99 105 110 116 11 16 22 56 62 70 75 81 129 36 67 98 27 34 24 23 21 19 18 17 15 14 134 135 136 138 139 141 142 74 80 71 76 75 19 69 14 2 118 125 132 137 143 23 29 34 42 79 85 94 99 105 14 21 57 90 124 47 54 44 43 41 39 38 35 33 32 DSP560PCMDK PRODUCT INFORMATION CL D2 Bl G2 Al B2 A2 A3 B4 M12 B6 D3 J3 E11 L6 L9 B7 G11 PN H w nN H CN gt UE UO t OQ UO t t C gt
15. 9 K1 K2 D7 93 94 120 J2 J3 D8 94 95 121 J1 J2 D9 96 96 122 H1 H3 D10 97 100 126 G1 H2 MOTOROLA DSP560PCMDK PRODUCT INFORMATION 011 99 101 128 F1 H1 D12 102 103 130 F2 G3 D13 104 104 131 E1 G2 D14 105 106 133 D1 G1 D15 106 107 134 C1 F1 D16 108 108 135 D2 F2 D17 109 109 136 B1 F3 D18 113 111 138 C2 E2 D19 114 112 139 A1 ES D20 115 114 141 B2 D2 D21 118 115 142 A2 D3 D22 119 117 2 A3 E4 D23 120 118 3 B4 04 DR 51 74 K11 DS 49 57 80 M12 L10 DSCK 50 71 N12 DSI 53 76 M11 DSO 52 75 L11 EXTAL 127 1 19 B6 C8 GNDC 48 69 N13 GNDCK 122 7 C4 GNDD 90 86 112 D3 B1 GNDD 91 92 118 J3 D1 GNDD 111 99 125 E1 GNDD 112 105 132 K1 GNDD 110 137 L1 GNDD 116 143 N1 GNDH 23 5 23 E11 A12 GNDH 24 11 29 A13 GNDH 16 34 C13 GNDH 22 42 E13 GNDN 55 56 79 L6 N10 GNDN 56 62 85 L9 GNDN 73 70 94 N5 GNDN 74 75 99 N6 GNDN 81 105 N8 GNDP 129 14 C6 GNDQ 33 3 21 B7 A1 GNDQ 34 36 57 G11 GNDQ 130 67 90 5 131 98 124 7 5 27 47 13 5 34 54 L13 HO 25 24 44 012 11 10 DSP560PCMDK PRODUCT INFORMATION MOTOROLA H1 22 23 43 C13 D11 H2 20 21 41 C12 C11 19 19 39 13 10 H4 16 18 38 Bi2 010 H5 15 17 35 13 B12 H6 14 15 33 A12 A11
16. e Port A memory access Read Written as control pins Not required on the 002 as Zero the bus control pins have been de multiplexed 1 2 7 X Memory Mapped Peripheral Registers In order to support the new peripherals present on the DSP56002 some of the reserved X I O addresses which were reserved on the DSP56001 have been redefined as peripheral control registers It is important to ensure that the new definitions of these previously unused addresses do not conflict with any software developed for the DSP56001 Many of the peripheral control registers within the DSP56001 and DSP56002 have reserved bits Reads from these reserved bits will return zero In order to guarantee compatibility with future products these bits should be written as zero On the DSP56002 some of the previously reserved bits in these registers have been redefined in order to support enhanced funtionality DSP560PCMDK PRODUCT INFORMATION MOTOROLA Table 2 shows all the differences between the DSP56001 and DSP56002 memory mapped peripheral registers Table 2 Summary of Memory Mapped Register Differences Register Bit DSP56001 Definition DSP56002 Definition Explanation of Difference PLL Control All read Control the This address should not have been Register as random write operation of the used on the 001 Users will have to X FFFD care PLL ensure that this
17. e contents of an address register Mn Nn or Rn The new contents of the destination address register will not be available for use during the following instruction i e there is a single instruction cycle delay On the DSP56002 this pipeline delay has been removed If an address register Mn Nn or Rn is directly changed with a MOVEP instruction the updated contents will be available for use during the following instruction DSP56001 software which depends on this pipeline delay must be modified when moved onto the DSP56002 1 2 2 MOVEP to from Data ALU Registers MOVEP Instructions to from Data ALU Registers take 2 instruction cycles on the DSP56001 On the DSP56002 these instructions take only 1 instruction cycle DSP56001 software which is dependent on the timing of this form of the MOVEP instruction must be modified when ported to the DSP56002 1 2 3 MOVEP Immediate MOVEP Immediate instructions take 3 instruction cycles on the DSP56001 On the DSP56002 these instructions take only 2 instruction cycles DSP56001 software which is dependent on the timing of this form of the MOVEP instruction must be modified when ported to the DSP56002 1 2 4 Stop Wait Timing Wake up from the Stop and Wait operating modes with IRQn is longer on the DSP56002 by one Tc period 1 2 5 SCI SSI Initialization Timing On the DSP56002 the SCI and SSI clocks are stopped when the peripherals are not enabled in order to save power Asa result the initial
18. is the case OnCE GDB All Reserved read the This address should not have been Register as random write of used on the 001 Users will have to X FFFC care OnCE commands ensure that this is the case SCI Interface 14 Written as zero STIR Timer On the 001 this bit should be written as Control Register the manual interrupt rate zero If this bit has been written as 1 it SCR X FFFO will increase the timer resolution on the 002 by 32 times Port B Control 1 Written as zero in Offers additional If written as zero as described in the Register PBC manual options for host manual will cause no problems If X FFEO interface written as 1 either the HACK pin will be GPIO or the register will contain an invalid value depending on the state of bit 0 Timer Control All Reserved read Control Registers These addresses should not have been Registers as random write ifor the Timer used on the 001 If they have it may X FFDF as care effect the operation of the timer on the X FFDE 002 1 3 Host Command Vector Register The DSP56002 supports 64 Interrupt Vectors compared to the 32 Interrupt Vectors supported by the DSP56001 Table 3 Summary of Host Command Vector Register Differences Register Bit DSP56001 Definition DSP56002 Definition Explanation of Difference Host Command Vector Register CVR Reserved read
19. ization time of the SCI and SSI is longer on the DSP56002 MOTOROLA DSP560PCMDK PRODUCT INFORMATION 1 2 6 Control Registers The DSP56002 has been improved to support Block Floating Point Double Precision Arithmetic additional bootstrap modes NMI and other features In order to support these improvements the OMR and the Status Register have been altered as outlined in Table 1 Table 1 Summary of Control Register Differences Register Bit DSP56001 DSP56002 Explanation of Difference Definition Definition Status Register 7 Reserved S Scaling bit On the 002 this bit can be read as 1 Read Written as depending on the contents of 51 50 zero and the accumulators It is a sticky bit 13 mode T Trace mode The 002 manual states that trace mode should be used 14 iReserved DM Double In the 002 if the DM bit is set the Read Written gt multiply operations performed by the MPY and zero MAC instructions change Operating 0 1 4 0 MA 0 These three bits control the operating Register 1 MB 1 mode of the device The 4 Reserved 4 MC pins are latched in on reset Completely different for 001 and 002 3 Reserved YD internal Y If this bit is set all Y memory data Read Written as memory disable addresses are considered to be zero external 7 EA External Reserved Controls the definition of th
20. lacing components in areas occupied by these tabs 1 1 3 Phase Locked Loop PLL The 56002 has a Phase Locked Loop on chip which permits operating the device from low frequency external clock sources precluding the need for additional high frequency clocks exclusively for the high speed DSP Tying the PINIT to GND disables the PLL upon power up Although not necessary the PCAP pin should be tied to Vec or GND This document contains information on a product under development Motorola reserves the right to change or discontinue this product without notice MOTOROLA INC 1995 1 1 4 OnCE The OnCE Port has been added to permit unobtrusive access to the core for debugging and testing Tying the Debug Request DR 1 pin to will disable the OnCE port It is recommended that DSCK be tied to GND through a 56k ohm resistor 1 1 5 Bus Control There have been several changes made to the bus control pins The BR WT and BG BS pins on the DSP56001 have been demultiplexed on the DSP56002 and an additional control signal Bus Needed BN has been added DSP56001 DSP56002 input BR WT input BR input WT output BG BS output BG output BS output BN DSP56001 based designs should be simplified due to the presence of individual signal pins for all bus arbitration functions Both BR and WT require pull up resistors to Vcc or they must be connected to external logic which assures
21. ows the DSP56002 to be driven by a low frequency external clock which is multiplied up on chip to allow full frequency operation There are 9 pins dedicated to the PLL DSP56002 PLL supply GNDP input PCAP input output PLOCK supply GNDCL input PINIT output CKOUT 2 1 6 OnCE Port The On Chip Emulator OnCE interface has been added to the DSP56002 This is a debug feature that allows access to all registers There are 4 pins dedicated to the OnCE interface 6 DSP560PCMDK PRODUCT INFORMATION MOTOROLA 5 56002 OnCE in out DSCK OS1 in out DSI OSO input DR output DSO 2 1 7 Host Acknowledge HACK The HACK pin may now be used as a general purpose I O pin GPIO independent of the other Host Interface pins Bits 0 and 1 of the Port B Control Register PBC now work in concert to define the function of HACK and the remaining Host Interface Pins 2 1 8 Timer TIO Pin A 24 bit timer event counter has been added to the DSP56002 Refer to the DSP56002 User s Manual Section 7 Timer and Event Counter 2 1 9 I O Buffer Drive Most DSP56002 buffers are capable of sinking 3 2 mA compared to the 1 6 mA buffers of the DSP56001 Refer to the DSP56002 Technical Data Sheet 2 1 10 SCI Timer Interrupt Rate Bit 14 in the SCI Control Register now controls a divide by 32 in the SCI Timer interrupt generator This bit was reserved on the DSP56001 2 1 11 SCI Bootstrap The
22. plete technical information on the DSP56001 and DSP56002 is contained in the following documents which can be ordered from your Motorola Literature Distribution Center using the reference numbers shown DSP56001 Technical Data Sheet DSP56001 D DSP56000 1 Users Manual DSP56000UM AD DSP56002 Technical Data Sheet DSP56002 D DSP56000 Family Manual DSP56KFAM D DSP56002 Users Manual DSP56002UM AD 8 DSP560PCMDK PRODUCT INFORMATION MOTOROLA APPENDIX Comparison of DSP56001 to DSP56002 Pin Assignments Table 4 Signal Name to DSP56001 and DSP56002 Pinout Cross Reference Signal Name DSP56001 DSP56002 FC DSP56002 PV DSP56001 RC DSP56002 RC FC or FE 132 pin 144 pin 88 pin 132 pin 132 pin Pin Pin Pin Pin or CQFP Pin AO 53 60 83 M11 K9 A1 54 61 84 N11 L9 A2 57 63 86 N10 M9 A3 58 64 87 M9 L8 A4 60 65 88 N9 M8 A5 61 68 92 M8 M7 A6 65 71 95 N8 L7 A7 67 72 96 N7 M6 A8 68 73 97 N6 L6 A9 70 74 98 M6 M5 A10 71 76 100 N5 L5 A11 75 77 101 M5 K5 A12 76 78 102 N4 4 1 77 80 104 L4 A14 79 82 106 N2 K4 A15 80 83 107 4 BG 43 43 64 K12 K12 BN 41 62 H13 BR 45 44 65 L13 L12 BS 43 54 77 K12 N11 CKOUT 123 8 C5 CKP 126 11 B4 DO 81 84 110 N1 N2 D1 82 85 111 M2 02 85 87 113 L2 M2 D3 86 88 114 M1 L3 04 87 90 116 L1 L2 D5 88 91 117 K2 06 92 93 11
23. pose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typical must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for sur gical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunit
24. that their quiescent state is a logic high 1 1 6 Bootstrap The DSP56002 has an extra Mode Select MODC NMI which also serves as the Non Maskable Interrupt The Mode Select pins are read as the processor comes out of reset and are used to define the chip s operating mode Refer to the DSP56002 documentation for specific details on the various bootstrap selections available via the MODA MODB MODC pins The reset circuitry will need to be modified for the DSP56002 so that the device will enter the correct operating mode after exiting reset For the DSP56002 bit 23 of the data bus no longer serves to select between EPROM and Host Interface Boot modes 1 1 7 Non Maskable Interrupt A Non Maskable Interrupt NMI function was previously accessible on the DSP56001 by applying 10 Volts to the MODB IRQB pin DSP56002 supports non maskable interrupt NMI through the MODC NMI pin which is TTL CMOS compatible DO NOT APPLY 10 VOLTS TO ANY PIN OF THE DSP56002 including MODB Subjecting any pin of the DSP56002 to voltages in excess of the specified TTL CMOS levels will permanently damage the device 1 1 8 DC Electrical Characteristics The supply voltage and logic level specifications of the DSP56001 and DSP56002 are the same Most DSP56002 buffers are capable of sinking 3 2 mA compared to the 1 6 mA buffers of the DSP56001 Please refer to the DSP56001 and DSP56002 Technical Data Sheets for specific details 1
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