1.3inch OLED User Manual
Contents
1. sa soa cm V1 4 1 Feb 26 2015 1 3inch OLED User Manual Waveshare Table 5 12C bus Interface SH1106_V2 3 pdf Chap I2C bus Interface Note pin must always be HIGH or LOW D7 D2 is recommended to connect the Von or Vss It is also allowed to leave D7 D2 unconnected CS signal could always pull low in 12C bus application The 2C bus is for bi directional two line communication between different ICs or modules The two lines are a serial data line SDA and a serial clock line SCL Both lines must be connected to a positive supply via a pull up resistor Data transfer may be initiated only when the bus is not busy Note The positive supply of pull up resistor must equal to the value of Vpp Bit Transfer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal SDA SCL Data line stable Change data Data valid allowed Figure 3 Bit Transfer SH1106_V2 3 pdf Chap I2C bus Interface Start and Stop conditions Both data and clock lines remain HIGH when the bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P SCL START condition STOP condition Figure 4 Sta2. 1 3inch OLED User Manual Waveshare 1 3inch OLED User Manual 1 Key Parameters Driver Chip SH1106 Interface 3 wire SPI 4 wire SPI 12C Resolution 128 64 Display Size 1 3 inch Dimension 29mm 33mm Colors Yellow Blue Visible Angle gt 160 Operating Temp C 20 70 Storage Temp C 30 80 Table 1 Key Parameters 2 Operation Description We will illustrate the usage of the module with an example of 4 wire SPI mode default working mode by connecting Waveshare Open103R development board STM32F103R MCU on board 1 Hardware configuration This module provides 3 kinds of driver interfaces they are 3 wire SPI 4 wire SPI and I2C interface In its factory settings BSO BS1 pins are set to 0 0 and 4 wire SPI is selected as default Different working mode and pin function of the module can be set by hardware selection on BSO BS1 pins Notice In this operation welding is required Any changes under no guidance from Waveshare will be considered as a waiver of warranty Table 2 Working mode setting 2 Software configuration Open the project file IDE OLED uvproj in Keil navigate to the following text delete the Double slash before define INTERFACE _4WIRE_ SPI 1 4 1 Feb 26 2015 1 3inch OLED User Manual Waveshare define INTERFACE 3WIRE SPI 3 wire SPI define INTERFACE 4WIRE SPI 4 wire SPI f define INTERFACE IIc fric After compiling successfully download the project to Open 10
3. 3R development board Note You should delete the Double slash corresponding to the mode selection 3 Hardware connections Connect module to the SPI2 interface of Open103R development board power up OLED displays information as Figure 1 shows Figure 1 OLED information display 3 4 wire SPI and I2C interfaces of SH1106 OLED The 8080 Parallel Interface 6800 Parallel Interface Serial Interface SPI or 12C Interface can be selected by different selections of IMO 2 as shown in Table 3 Table 3 Different selections of IMO 2 SH1106 V2 3 pdf Chap Functional Description Note1 When Serial Interface SPI or 12C Interface is selected D7 D2 is Hz D7 D2 is recommended to connect the Von or Vss It is also allowed to leave D7 D2 unconnected SH1106 provides 5 kinds of driver interfaces however the OLED board just provides 3 kinds of driver interfaces settling 3 wire SPI 4 wire SPI and I2C the IM2 pin is set to 1 by hardware BSO BS1 correspond to IMO IM1 respectively We introduce 4 wire SPI and 12C interfaces here Please read SH1106_V2 3 pdf for more details V1 4 1 Feb 26 2015 1 3inch OLED User Manual Waveshare 3 1 4 Wire Serial Interface 4 wire SPI The serial interface consists of serial clock SCL serial data SI AO and CS SI is shifted into an 8 bit shift register on every rising edge of SCL in the order of D7 D6 and DO AO is sampled on every eighth clock and the data b
4. e device that should respond is addressed first Two 7 bit slave addresses 0111100 and 0111101 are reserved for the SH1106 The least significant bit of the slave address is set by connecting the input SAO to either logic O VSS or 1 VDD1 The I2C bus protocol is illustrated in Figure 6 12C Protocol The sequence is initiated with a START condition S from the I2C bus master that is followed by the slave address All slaves with the corresponding address acknowledge in parallel all the others will ignore the 12C bus transfer After acknowledgement one or more command words follow which define the status of the addressed slaves A command word consists of a control byte which defines Co and D C note1 plus a data byte see Figure 6 12C Protocol The last control byte is tagged with a cleared most significant bit the continuation bit Co After a control byte with a cleared Co bit only data bytes will follow The state of the D C bit defines whether the data byte is interpreted as a command or as RAM data The control and data bytes are also acknowledged by all addressed slaves on the bus After the last control byte depending on the D C bit setting either a series of display data bytes or command data bytes may follow If the D C bit was set to 1 these display bytes are stored in the display RAM at the address specified by the data pointer The data pointer is automatically updated and the data is directed to the intended SH1106 device I
5. f the D C bit of the last control byte was set to 0 these command bytes will be decoded and the setting of the device will be changed according to the received commands The acknowledgement after each byte is made only by the addressed slave At the end of the transmission the 12C bus master issues a stop condition P If the R W bit is set to one in the slave address the chip will output data immediately after the slave address according to the D C bit which was sent during the last write access If no acknowledge is generated by the master after a byte the driver stops transferring data to the master V1 4 1 Feb 26 2015 1 3inch OLED User Manual Waveshare WRITE from S from S from S from S from S control byte data byte 0 DC control byte data byte 2n gt 0 bytes RE AD from S from M from M from M from M S start condition P stop condition Rihi ham A Acknowledge A Not Acknowledge C DCO 0 O O 0 OJA M I2C master S C slave Control Byte slave address Figure 6 I2C Protocol V1 4 1 Feb 26 2015
6. rt and Stop conditions Acknowledge Each byte of eight bits is followed by an acknowledge bit The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra 4 V1 4 1 Feb 26 2015 1 3inch OLED User Manual Waveshare acknowledge related clock pulse A slave receiver which is addressed must generate an acknowledge after the reception of each byte Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be taken into consideration A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition Rimmel DATA OUTPUT BY a TRANSMITTER INZ X X A 7 not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER TRAN TA A TN _ ft PNOO a START condition clock pulse for acknowledgement Figure 5 Acknowledge Protocol The SH1106 supports both read and write access The R W bit is part of the slave address Before any data is transmitted on the 2C bus th
7. yte in the shift register is written to the display data RAM AO 1 or command register AO 0 in the same clock See Figure 2 Two Tor m type pcs ro w OO Ot ojele emes fo fa fsa s Table 4 SPI interface setting SH1106_V2 3 pdf Chap 4 Wire Serial Interface Note pin must always be HIGH or LOW D7 D2 is recommended to connect the Vpop or Vss It is also allowed to leave D7 D2 unconnected The serial interface is initialized when CS is high In this state SCL clock pulse or SDI data have no effect A falling edge on CS enables the serial interface and indicates the start of data transmission The SPI is also able to work properly when the CS always keep low but it is not recommended a 75 gt Figure 2 4 wire SPI data transfer SH1106_V2 3 pdf Chap 4 Wire Serial Interface When the chip is not active the shift registers and the counter are reset to their initial statuses Read is not possible while in serial interface mode Caution is required on the SCL signal when it comes to line end reflections and external noise We recommend the operation be rechecked on the actual equipment 3 2 12C bus Interface The SH1106 can transfer data via a standard I2C bus and has slave mode only in communication The command or RAM data can be written into the chip and the status and RAM data can be read out of the chip imo m1 m2 type cs m o w o o o o emee femm so e
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