AD5744 Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar
Contents
1. 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 13 Differential Nonlinearity Error vs Temperature 0 04 0 03 0 02 0 01 0 0 01 0 02 0 03 0 04 0 05 0 06 Vod Vss 15 V 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 14 Differential Nonlinearity Error vs Temperature 0 12 0 10 0 08 0 06 0 04 0 02 0 02 0 04 Vod Vss 12 V 11 4 12 4 13 4 14 4 15 4 16 4 SUPPLY VOLTAGE V Figure 15 Integral Nonlinearity Error vs Supply Voltage DNL ERROR LSB 06064 019 INL ERROR LSB 06064 020 DNL ERROR LSB 06064 023 Rev PrE Page 16 of 32 0 03 0 02 0 01 0 0 01 0 02 0 02 0 04 0 05 0 06 11 4 12 4 13 4 14 4 15 4 16 4 SUPPLY VOLTAGE V Figure 16 Differential Nonlinearity Error vs Supply Voltage 0 20 0 15 0 10 0 05 0 05 0 10 0 15 0 20 0 25 1 2 3 4 5 6 7 REFERENCE VOLTAGE V Figure 17 Integral Nonlinearity Error vs Reference Voltage 0 10 0 08 0 06 0 04 0 02 0 02 0 04 0 06 0 08 0 10 1 2 3 4 5 6 7 REFERENCE VOLTAGE V Figure 18 Differential Nonlinearity Error vs Reference Voltage 06064 025 06064 027 06064 0312. The output voltage expression for the AD5744 is given by D Vour 2x VngrIN 4x VREFIN P where D is the decimal equivalent of the code loaded to the DAC Vrern is the reference voltage applied at the REFAB REFCD pins ASYNCHRONOUS CLEAR CLR CLR is a negative edge triggered clear that allows the outputs to be cleared to either 0 V twos complement coding or negative full scale offset binary coding It is necessary to maintain CLR low for a minimum amount of time see Figure 3 for the operation to complete When the CLR signal is returned high the output remains at the cleared value until a new value is programmed If at power on CLR is at 0 V then all DAC outputs are updated with the clear value A clear can also be initiated through software by writing the command 0x04XXXX to the AD5744 Rev PrE Page 22 of 32 Table 8 AD5744 MSB AD5744 Input Register Format LSB DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO RW o REG2 DATA REG1 REGO A2 Al AO Table 9 Input Register Bit Functions Register Function R W Indicates a read from or a write to the addressed register REG2 REG1 REGO Used in association with the address bits to determine if a read or write operation is to the data register offset register gain register o
3. 15V 8 _ 5000 40 Vpp Vss 12V w 4000 12 lt S 5 14 3000 ra gt 2 16 5 gt a 2000 _48 3 20 1000 Vpp Vss 12V 22 REFIN 5V 0 TA 25 C 24 0x8000 TO 0x7FFF 500ns DIV 1000 26 10 2 0 1 5 1 0 0 5 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 SOURCE SINK CURRENT mA 2 TIME us Figure 25 Source and Sink Capability of Output Amplifier with Positive Figure 28 Major Code Transition Glitch Energy Vop Vss 12 V Full Scale Loaded 10000 Vpp Vss 15V 9000 REFIN 5V MIDSCALE LOADED REFIN 0V 8000 SUPPLIES lt 7000 3 w 6000 9 12V SUPPLIES F 5000 d 4 gt 4000 5 amp 3000 2 O 2000 1000 0 50pV DIV 1000 x 12 7 2 3 8 50 0uV M1 00s CH4 26V SOURCE SINK CURRENT mA 8 Figure 26 Source and Sink Capability of Output Amplifier with Negative Figure 29 Peak to Peak Noise 100 kHz Bandwidth Full Scale Loaded E Vpp Vss 412V Vop Vss 15V t REFIN 5V TA 25 C mE SV RAMP TIME 100ys LOAD 200pF 10kO t ED B 1 B ED I ius DIV E I 3 00V M1 00us CH1 120mV 10 0V By 10 0V Mi00us ACH1 7 80mV 10 0mV By 29 60 3 Figure 27 Full Scale Settling Time Figure 30 VOUT vs Vop Vss on Power Up Rev PrE Page 18 of 32 06063 047 SHORT CIRCUIT CURRENT mA Vpp Vss 15V Ta 25 C REFIN 5V 0 20 40 60 80 100 120 Riscc kO Figure 31 Short Circuit Current vs Rlscc 06063 050
4. tr 5 ns 10 to 90 of DVcc and timed from a voltage level of 1 2 V 3 See Figure 2 Figure 3 and Figure 4 Standalone mode only 5 Measured with the load circuit of Figure 5 Daisy chain mode only Rev PrE Page 7 of 32 AD5144 VOUT LDAC 0 VOUT tia VOUT 06063 002 Figure 2 Serial Interface Timing Diagram l iO i i gt ts lt t lt I gt t lt e I I io I pem ti lt I nu I l I l SYNC WE I E INPUT WORD FOR DAC N INPUT WORD FOR DAC N 1 pt t 45 S C CC CCC UNDEFINED I INPUT WORD FOR DAC N Figure 3 Daisy Chain Timing Diagram Rev PrE Page 8 of 32 06063 003 AD5744 c NN FA p L A G E INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ UNDEFINED SELECTED REGISTER DATA CLOCKED OUT 06063 004 Figure 4 Readback Timing Diagram Von MIN OR VoL MAX TO OUTPUT PIN 06063 005 Figure 5 Load Circuit for SDO Timing Diagram Rev PrE Page 9 of 32 AD5744 ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Transient currents of up to 100 mA do not cause SCR latch up Table 5 Parameter Rating AVop to AGND DGND 0 3 V to 17 V AVss to AGND DGND 0 3 V to 17V DVcc to DGND 0 3 V to 7 V Digital Inputs to DGND 0 3V to DVcc 0 3 V or 7 V whichever is less Digital Outputs to DGND 0 3 V to DVcc 0 3 V REFIN to AGND PGND 0 3 V to AVoo 0 3V REFOUT to
5. Rev PrE Page 19 of 32 AD5744 AD5744 THEORY OF OPERATION The AD5744 is a quad 14 bit serial input bipolar voltage output DAC and operates from supply voltages of 11 4 V to 16 5 V and has a buffered output voltage of up to 10 5263 V Data is written to the AD5744 in a 24 bit word format via a 3 wire serial interface The device also offers an SDO pin which is available for daisy chaining or readback The AD5744 incorporates a power on reset circuit which ensures that the DAC registers power up loaded with 0x0000 The AD5744 features a digital I O port that can be programmed via the serial interface on chip reference buffers and per channel digital gain registers DAC ARCHITECTURE The DAC architecture of the AD5744 consists of a 14 bit current mode segmented R 2R DAC The simplified circuit diagram for the DAC section is shown in Figure 32 The four MSBs of the 14 bit data word are decoded to drive 15 switches E1 to E15 Each of these switches connects one of the 15 matched resistors to either AGND or IOUT The remaining 10 bits of the data word drive switches S0 to S9 of the 10 bit R 2R ladder network VREF 2R 4 MSBs DECODED INTO 10 BIT R 2R LADDER 15 EQUAL SEGMENTS Figure 32 DAC Ladder Structure REFERENCE BUFFERS The AD5744 operates with an external reference The reference inputs REFAB and REFCD have an input range up to 7 V This input voltage is then used to provide a buffered positive an
6. TUE mV CURRENT mA ZERO SCALE ERROR mV REFERENCE VOLTAGE V Figure 19 Total Unadjusted Error vs Reference Voltage 14 13 12 11 10 Vpb Vss 16 5 V Ta 25 C REFIN 5V llppl Ilssl 11 4 12 4 13 4 14 4 15 4 16 4 0 25 0 20 0 15 0 10 0 05 0 05 0 10 0 15 0 20 0 25 Vpp Vss V Figure 20 Ipp lss vs Vpp Vss REFIN 5V 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 21 Zero Scale Error vs Temperature BIPOLAR ZERO ERROR mV 06063 037 06063 035 GAIN ERROR mV Dicc mA 06063 038 Rev PrE Page 17 of 32 AD5744 REFIN 5V 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 22 Bipolar Zero Error vs Temperature REFIN 5V 4 PAP TEMPERATURE C Figure 23 Gain Error vs Temperature 0 0014 0 0013 0 0012 0 0011 0 0010 0 0009 0 0008 0 0007 0 0006 Figure 24 Dlcc vs Logic Input Voltage 06063 039 06063 040 06063 041 AD5144 7000 4 TA 25 C REFIN 5V 6 6000 Vpp Vss
7. AD5744 requires a clock synchronized to the serial data For this reason the 8XC51 must be operated in Mode 0 In this mode serial data enters and exits through RXD and a shift clock is output on TXD 06063 066 P3 3 and P3 4 are bit programmable pins on the serial port and are used to drive SYNC and LDAC respectively The 8CX51 provides the LSB of its SBUF register as the first bit in the data stream The user must ensure that the data in the SBUF register is arranged correctly because the DAC expects MSB first When data is to be transmitted to the DAC P3 3 is taken low Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge As a result no glue logic is required between this DAC and the microcontroller interface 8XC51 AD5744 06063 067 ADDITIONAL PINS OMITTED FOR CLARITY Figure 39 AD5744 to 8XC51 Interface The 8XC51 transmits data in 8 bit bytes with only eight falling clock edges occurring in the transmit cycle Because the DAC expects a 24 bit word SYNC P3 3 must be left low after the first eight bits are transferred After the third byte has been transferred the P3 3 line is taken high The DAC can be updated using LDAC via P3 4 of the 8XC51 AD5744 to ADSP2101 ADSP2103 Interface An interface between the AD5744 and the ADSP2101 ADSP2103 is shown in Figure 40 The ADSP2101 ADSP2103 should be set up to operate in the SPORT transmit alternate framin
8. AGND AVss to AVop TEMP AVss to AVpp VOUTA VOUTB VOUTC VOUTD to AVss to AVop AGND AGND to DGND 0 3 V to 40 3 V Operating Temperature Range Industrial Storage Temperature Range Junction Temperature T max 32 Lead TOFP Osa Thermal Impedance Osc Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 40 C to 85 C 65 C to 150 C 150 C 65 C W 12 C W 220 C 10 sec to 40 sec ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD SENSITIVE DEVICE Rev PrE Page 10 of 32 AD5744 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6 Pin Function Descriptions 8 BIN 2sCOMP X REFA
9. ANALOG OUTPUT CONTROL In many industrial process control applications it is vital that the output voltage be controlled during power up and during brownout conditions When the supply voltages are changing the VOUT pins are clamped to 0 V via a low impedance path To prevent the output amp being shorted to 0 V during this time transmission gate Gl is also opened see Figure 35 These conditions are maintained until the power supplies stabilize and a valid word is written to the DAC register At this time G2 opens and G1 closes Both transmission gates are also externally controllable via the Reset In RSTIN control input For instance if RSTIN is driven from a battery supervisor chip the RSTIN input is driven low to open G1 and close G2 on power off or during a brownout Conversely the on chip voltage detector output RSTOUT is also available to the user to control other parts of the system The basic transmission gate functionality is shown in Figure 35 RSTOUT RSTIN VOLTAGE MONITOR AND CONTROL 06063 063 Figure 35 Analog Output Control Circuitry PROGRAMMABLE SHORT CIRCUIT PROTECTION The short circuit current of the output amplifiers can be pro grammed by inserting an external resistor between the ISCC pin and PGND The programmable range for the current is 500 uA to 10 mA corresponding to a resistor range of 120 kQ to 6 kO The resistor value is calculated as follows _ 60 R Isc If the ISCC pin
10. VOUTD on GAIN REG D CLR O O AGNDD OFFSET REG D REFERENCE BUFFERS O LDAC REFCD 06063 001 Figure 1 Functional Block Diagram Rev PrE Page 3 of 32 AD5744 SPECIFICATIONS AVpp 11 4 V to 16 5 V AVss 11 4 V to 716 5 V AGND DGND REFGND PGND 0 V REFAB REFCD 5 V DVcc 2 7 V to 5 25 V Rioap 10 kO Cr 200 pF All specifications Tmn to Tmax unless otherwise noted Table 2 Parameter B Grade C Grade Unit Test Conditions Comments ACCURACY Outputs unloaded Resolution 14 14 Bits Relative Accuracy INL 2 1 LSB max Differential Nonlinearity 1 1 LSB max Guaranteed monotonic Bipolar Zero Error 2 2 mV max At 25 C error at other temperatures obtained using bipolar zero TC Bipolar Zero TC 2 2 ppm FSR C max Zero Scale Error 2 2 mV max At 25 C error at other temperatures obtained using zero scale TC Zero Scale TC 2 2 ppm FSR C max Gain Error 0 02 0 02 FSR max At 25 C error at other temperatures obtained using gain TC Gain TC ppm FSR C max DC Crosstalk 0 125 0 125 LSB max REFERENCE INPUT Reference Input Voltage 5 5 V nominal 1 for specified performance DC Input Impedance 1 1 MO min Typically 100 MQ Input Current 10 10 HA max Typically 30 nA Reference Range 1 7 1 7 V min V max OUTPUT CHARACTERISTICS Output Voltage Range 10 5263 10 5263 V min V max AVop AVss 11 4 V REFIN 5V 14 14 V min V max AVpp AVss 16 5 V REFI
11. further details DO D1 Value I O Port Status Bits Logic values written to these locations determine the logic outputs on the DO and D1 pins when configured as outputs These bits indicate the status of the DO and D1 pins when the I O port is active as an input When enabled as inputs these bits are don t cares during a write operation SDO Disable Set by the user to disable the SDO output Cleared by the user to enable the SDO output default CLR Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode LOAD Addressing this function updates the DAC registers and consequently the analog outputs Rev PrE Page 23 of 32 AD5744 DATA REGISTER The data register is addressed by setting the three REG bits to 010 The DAC address bits select with which DAC channel the data transfer is to take place see Table 9 The data bits are in positions DB15 to DB2 as shown in Table 12 Table 12 Programming the AD5744 Data Register REG2 REG1 REGO A2 Al AO DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 1 0 DAC Address 14 Bit DAC Data X X COARSE GAIN REGISTER The coarse gain register is addressed by setting the three REG bits to 011 The DAC address bits select with which DAC channel the data transfer is to take place see Table 9 The coarse gain register is a 2 bit register and allows the user
12. is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners Dual Low Power CMOS Analog Front End with DSP Microcomputer AD5744 GENERAL DESCRIPTION The AD5744 is a quad 14 bit serial input bipolar voltage output digital to analog converter that operates from supply voltages of 11 4 V up to 16 5 V Nominal full scale output range is 10 V The AD5744 provides integrated output amplifiers reference buffers and proprietary power up power down control circuitry The part also features a digital I O port which is programmed via the serial interface The AD5744 incorporates digital gain adjust registers per channel The AD5744 is a high performance converter that offers guaranteed monotonicity integral nonlinearity INL of 1 LSB low noise and 10 us settling time During power up when the supply voltages are changing VOUT is clamped to 0 V viaa low impedance path The AD5744 uses a serial interface that operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards Double buffering allows the simultaneous updating of all DACs The input coding is programmable to either twos complement or offset binary formats The asynchronous clear function clears all DAC registers to either bipolar zero or zero scale depending on the coding used The AD5744 is ideal for both closed loop s
13. is left unconnected the short circuit current limit defaults to 5 mA It should be noted that limiting the short circuit current to a small value can affect the slew rate of the output when driving into a capacitive load therefore the value of short circuit current programmed should take into account the size of the capacitive load being driven DIGITAL I O PORT The AD5744 contains a 2 bit digital I O port D1 and D0 these bits can be configured as inputs or outputs independently and can be driven or have their values read back via the serial interface The I O port signals are referenced to DVcc and DGND When configured as outputs they can be used as control signals to multiplexers or can be used to control calibration circuitry elsewhere in the system When configured as inputs the logic signals from limit switches for example can be applied to DO and D1 and can be read back via the digital interface LOCAL GROUND OFFSET ADJUST The AD5744 incorporates a local ground offset adjust feature which when enabled in the function register adjusts the DAC outputs for voltage differences between the individual DAC ground pins and the REFGND pin ensuring that the DAC output voltages are always with respect to the local DAC ground pin For instance if pin AGNDA is at 5 mV with respect to the REFGND pin and VOUTA is measured with respect to AGNDA then a 5mV error results enabling the local ground offset adjust feature adjusts VOUTA by
14. is reflected in the outputs of the device There are four possible sources of error to consider when choosing a voltage reference for high accuracy applications initial accuracy temperature coefficient of the output voltage long term drift and output voltage noise Initial accuracy error on the output voltage of an external refer ence could lead to a full scale error in the DAC Therefore to minimize these errors a reference with low initial accuracy error specification is preferred Choosing a reference with an output trim adjustment such as the ADR425 allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal The trim ad justment can also be used at temperature to trim out any error Long term drift is a measure of how much the reference output voltage drifts over time A reference with a tight long term drift specification ensures that the overall solution remains relatively stable over its entire lifetime The temperature coefficient of a references output voltage affects INL DNL and TUE A reference with a tight temperature coefficient specification should be chosen to reduce the dependence of the DAC output voltage on ambient conditions In high accuracy applications which have a relatively low noise budget reference output voltage noise needs to be considered Choosing a reference with as low an output noise voltage as practical for the system resolution requ
15. kO 200 pF load 20 AGNDC Ground Reference Pin for DAC C Output Amplifier Rev PrE Page 11 of 32 AD5744 Pin No Mnemonic Description 21 AGNDB Ground Reference Pin for DAC B Output Amplifier 22 VOUTB Analog Output Voltage of DAC B Buffered output with a nominal full scale output range of 10 V The output amplifier is capable of directly driving a 10 kO 200 pF load 23 VOUTA Analog Output Voltage of DAC A Buffered output with a nominal full scale output range of 10 V The output amplifier is capable of directly driving a 10 kO 200 pF load 24 AGNDA Ground Reference Pin for DAC A Output Amplifier 25 REFAB External Reference Voltage Input for Channel A and Channel B Reference input range is 1 V to 7 V programs the full scale output voltage REFIN 5 V for specified performance 26 REFCD External Reference Voltage Input for Channel C and Channel D Reference input range is 1 V to 7 V programs the full scale output voltage REFIN 5 V for specified performance 27 NC No Connect 28 REFGND Reference Ground Return for the Reference Generator and Buffers 29 NC No Connect 32 BIN 2sCOMP Determines the DAC Coding This pin should be hardwired to either DVcc or DGND When hardwired to DVcc input coding is offset binary When hardwired to DGND input coding is twos complement see Table 7 Internal pull up device on this logic input Therefore it can be left floating and defaults to a logic high condit
16. read using the readback function AD5744 to MC68HC11 Interface Figure 38 shows an example of a serial interface between the AD5744 and the MC68HC11 microcontroller The serial peripheral interface SPI on the MC68HC11 is configured for master mode MSTR 1 clock polarity bit CPOL 0 and the clock phase bit CPHA 1 The SPI is configured by writing to the SPI control register SPCR see the 68HC11User Manual SCK of the MC68HC11 drives the SCLK of theAD5744 the MOSI output drives the serial data line DIN of the AD5744 AD5744 and the MISO input is driven from SDO The SYNC is driven from one of the port lines in this case PC7 Rev PrE Page 27 of 32 AD5744 When data is being transmitted to the AD5744 the SYNC line PC7 is taken low and data is transmitted MSB first Data appearing on the MOSI output is valid on the falling edge of SCK Eight falling clock edges occur in the transmit cycle so in order to load the required 24 bit word PC7 is not brought high until the third 8 bit word has been transferred to the DACs input shift register MC68HC111 AD57441 TADDITIONAL PINS OMITTED FOR CLARITY Figure 38 AD5744 to MC68HC11 Interface LDAC is controlled by the PC6 port output The DAC can be updated after each 3 byte transfer by bringing LDAC low This example does not show other serial lines for the DAC For example if CLR were used it could be controlled by port output PC5 AD5744 to 8XC51 Interface The
17. to select the output range of each DAC as shown in Table 13 and Table 14 Table 13 Programming the AD5744 Coarse Gain Register REG2 REG1 REGO A2 Al AO DB15 DB2 DB1 DBO 0 1 1 DAC Address Don t Care CG1 CGO Table 14 Output Range Selection Output Range CG1 CGO 10V default 0 0 10 2564V 0 1 10 5263 V 1 0 FINE GAIN REGISTER The fine gain register is addressed by setting the three REG bits to 100 The DAC address bits select with which DAC channel the data transfer is to take place see Table 9 The fine gain register is a 6 bit register and allows the user to adjust the gain of each DAC channel by 8 LSBs to 7 75 LSBs in 0 25 LSB steps as shown in Table 15 and Table 16 The adjustment is made to both the positive full scale points and the negative full scale points simultaneously each point being adjusted by of one step The fine gain register coding is twos complement Table 15 Programming AD5744 Fine Gain Register REG2 REG1 REGO A2 Al AO DB15 DB6 DB5 DB4 DB3 DB2 DB1 DBO 1 0 0 DAC Address Don t Care FG5 FG4 FG3 FG2 FG1 FGO Table 16 AD5744 Fine Gain Register Options Gain Adjustment FG5 FG4 FG3 FG2 FG1 FGO 7 75 LSBs 0 1 1 1 1 1 7 5 LSBs 0 1 1 1 1 0 No Adjustment default 0 0 0 0 0 0 7 75 LSBs 1 0 0 0 0 1 8 LSBs 1 0 0 0 0 0 Rev PrE Page 24 of 32 AD5744 AD5744 FEATURES
18. updated Individual DAC Updating In this mode LDAC is held low while data is being clocked into the input shift register The addressed DAC output is updated on the rising edge of SYNC Simultaneous Updating of All DACs In this mode LDAC is held high while data is being clocked into the input shift register All DAC outputs are updated by taking LDAC low any time after SYNC has been taken high The update now occurs on the falling edge of LDAC Rev PrE Page 21 of 32 AD5144 OUTPUT VV AMPLIFIER VREFIN O O Vour LDAC SCLK SYNC SDIN INTERFACE LOGIC spo 06063 062 Figure 34 Simplified Serial Interface of Input Loading Circuitry for One DAC Channel TRANSFER FUNCTION Table 7 shows the ideal input code to output voltage relationship for the AD5744 for both offset binary and twos complement data coding Table 7 Ideal Output Voltage to Input Code Relationship for the AD5744 Digital Input Analog Output Offset Binary Data Coding MSB LSB Vour 11 1111 1111 1111 2 Veer X 8191 8192 10 0000 0000 0001 2 Veer x 1 8192 10 0000 0000 0000 0v 01 1111 1111 1111 2 Veer x 1 8192 00 0000 0000 0000 2 Veer x 8191 8192 Twos Complement Data Coding MSB LSB Vout 01 1111 1111 1111 2 Veer x 8191 8192 00 0000 0000 0001 2 Veer x 1 8192 00 0000 0000 0000 0v 11 1111 1111 1111 2 Veer x 1 8192 10 0000 0000 0000 2 Vier x 8191 8192
19. 00 4000 6000 8000 CODE 1000 12000 14000 16000 Figure 8 Integral Nonlinearity Error vs Code Vpp Vss 12 V Ta 25 C Vpp Vss 7 15V REFIN 5V 0 2000 4000 6000 8000 CODE 1000 12000 14000 16000 Figure 9 Differential Nonlinearity Error vs Code Vpp Vss 15 V 06063 009 06063 010 06063 013 DNL ERROR LSB INL ERROR LSB INL ERROR LSB Rev PrE Page 15 of 32 0 25 0 20 0 15 0 10 0 05 0 05 0 10 0 15 0 20 0 25 0 0 12 0 10 0 08 0 06 0 04 0 02 0 02 0 04 AD5744 Ta 25 C Vpp Vss 12V sla lal i 2000 6000 8000 CODE 1000 12000 14000 16000 Figure 10 Differential Nonlinearity Error vs Code Vod Vss 12 V 40 20 0 20 40 60 80 100 0 12 0 10 0 08 0 06 0 04 0 02 0 02 0 04 TEMPERATURE C Figure 11 Integral Nonlinearity Error vs Temperature Vop Vss 15 V 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 12 Integral Nonlinearity Error vs Temperature Vod Vss 12 V 06063 014 06064 015 06064 016 AD5744 DNL ERROR LSB DNL ERROR LSB INL ERROR LSB 0 01 0 02 0 03 0 04 0 05 0 06
20. 1 AD5744 to PIC16C6x 7x Interface Rev PrE Page 29 of 32 AD5144 OUTLINE DIMENSIONS MAX le 9 00 BSC SQ 607 45 F 00 TOP VIEW sa PINS DOWN 1 05 MIN 2g 1 00 0 09 0 95 Es Lae EN 0 15 SEATING 0 0 05 PLANE 0 08 MAX COPLANARITY BSC 037 VIEW A LEAD PITCH 3n ROTATED 90 CCW i COMPLIANT TO JEDEC STANDARDS MS 026ABA Figure 42 32 Lead Thin Plastic Quad Flat Package TQFP SU 32 2 Dimensions shown in millimeters ORDERING GUIDE Package Option Model Function INL Temperature Package Description AD5744BSUZ2 Quad 14 bit DAC 2 LSB max 40 C to 85 C 32 lead TQFP SU 32 2 AD5744BSUZ REEL72 Quad 14 bit DAC 2 LSB max 40 C to 85 C 32 lead TQFP SU 32 2 AD5744CSUZ Quad 14 bit DAC 1 LSB max 40 C to 85 C 32 lead TOFP SU 32 2 AD5744CSUZ REEL7 Quad 14 bit DAC 1 LSB max 40 C to 85 C 32 lead TOFP SU 32 2 1 Analog Devices reserves the right to ship higher grade devices in place of lower grade 2 Z Pb free part Rev PrE Page 30 of 32 AD5744 NOTES Rev PrE Page 31 of 32 AD5744 NOTES 2006 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners PR06063 0 3 06 PrE DEVICES www analog com Rev PrE Page 32 of 32
21. 5 mV eliminating the error Rev PrE Page 25 of 32 AD5744 APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 36 shows the typical operating circuit for the AD5744 The only external components needed for this precision 14 bit DAC are a reference voltage source decoupling capacitors on the supply pins and reference inputs and an optional short circuit current setting resistor Because the device incorporates reference buffers it eliminates the need for an external bipolar reference and associated buffers This leads to an overall savings in both cost and board space In Figure 36 Von and Vss are both connected to 15 V but Vpp and Vss can operate with supplies from 11 4 V to 16 5 V In Figure 36 AGNDA is connected to REFGND BIN 2sCOMP SYNC SCLK SDIN spo AD5744 AGNDA VOUTA VOUTB AGNDB AGNDC LDAC VOUTC D0 VOUTD D1 AGNDD RSTOUT RSTIN gt NC NO CONNECT 15V 15V 06063 064 Figure 36 Typical Operating Circuit Precision Voltage Reference Selection To achieve the optimum performance from the AD5744 over its full operating temperature range a precision voltage reference must be used Thought should be given to the selection of a precision voltage reference The AD5744 has two reference inputs REFAB and REFCD The voltages applied to the reference inputs are used to provide a buffered positive and negative reference for the DAC cores Therefore any error in the voltage reference
22. ANALOG DEVICES FEATURES Complete quad 14 bit digital to analog converters DACs Programmable output range 10 V 10 2564 V or 10 5263 V 1 LSB max INL error 1 LSB max DNL error Low noise 60 nV VHz Settling time 10 ps max Integrated reference buffers Output control during power up brownout Programmable short circuit protection Simultaneous updating via LDAC Asynchronous CLR to zero code Digital gain adjust Logic output control pins DSP microcontroller compatible serial interface Temperature range 40 C to 85 C iCMOS process technology APPLICATIONS Industrial automation Open closed loop servo control Process control Data acquisition systems Automatic test equipment Automotive test and measurement High accuracy instrumentation For analog systems designers within industrial instrumentation equipment OEMs who need high performance ICs at higher voltage levels iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and package size and increased AC and DC performance Rev PrE Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license
23. B 24 AGNDA VOUTA VOUTB AD5744 2l TOP VIEW AGNDE Not to Scale 20 AGNDC 19 vourc 18 VOUTD AGNDD s o o a NC NO CONNECT 06063 006 Figure 6 Pin Configuration Pin No Mnemonic Description 1 SYNC Active Low Input This is the frame synchronization signal for the serial interface While SYNC is low data is transferred in on the falling edge of SCLK 2 SCLK Serial Clock Input Data is clocked into the shift register on the falling edge of SCLK This operates at clock speeds up to 30 MHz 3 SDIN Serial Data Input Data must be valid on the falling edge of SCLK 4 SDO Serial Data Output Used to clock data from the serial register in daisy chain or readback mode 51 CLR Negative Edge Triggered Input Asserting this pin sets the DAC registers to 0x0000 6 LDAC Load DAC Logic input This is used to update the DAC registers and consequently the analog outputs When tied permanently low the addressed DAC register is updated on the rising edge of SYNC If LDAC is held high during the write cycle the DAC input register is updated but the output update is held off until the falling edge of LDAC In this mode all analog outputs can be updated simultaneously on the falling edge of LDAC The LDAC pin must not be left unconnected 7 8 DO D1 DO and D1 form a digital I O port The user can set up these pins as inputs or outputs that are configurable and readable over the serial inte
24. C e 21 REVISION HISTORY 3 06 Revision PrE Removed AD5744R AD5764 and AD5764R Universal Changes to Ordering Guide sse 30 Transfer PUDCOOD ete RA V RR E 22 Asynchronous Clear CLR 22 Function Register rere teret teretes 23 Data Register needs 24 Coarse Gain R gist r norrena E 24 Fine Gain Register parr aE EE 24 A D5744 Beat res icit a E 25 Analog Output Control seen 25 Programmable Short Circuit Protection 25 Digital VO Portia naa ua 25 Local Ground Offset Adjust sse 25 Applications Information eene 26 Typical Operating Circuit as 26 Layout Guidelines iR entum 27 Galvanically Isolated Interface sss 27 Microprocessor Interfacing senten 27 Outline Dimensions sse 30 Ordering Guide scsi u a RES 30 Rev PrE Page 2 of 32 AD5744 FUNCTIONAL BLOCK DIAGRAM PGND AVpp AVss AVpp AVss REFGND REFAB RSTOUT RSTIN O O O VOLTAGE eee REFERENCE AND AD5744 AND DGND BUFFERS CONTROL Iscc d SDIN O NEUT a Q VOUTA SHIFT SCLK Q REGISTER Xp SYNC AND SAN REGA px F SYNC C CONTROL OFFSET REG A Q AGNDA LOGIC spo O REG B e b es VOUTB OFFSET REG B AGNDB po INPUT D1 O REG C QO GAIN REG C OFFSET REG C E ias O gt Q z o BIN 2sCOMP O INPUT REG D QO
25. C This includes both digital and analog crosstalk It is measured by loading one of the DACs with a full scale code change all 0s to all 1s and vice versa with LDAC low and monitoring the output of another DAC The energy of the glitch is expressed in nV s Rev PrE Page 13 of 32 AD5744 Channel to Channel Isolation Channel to channel isolation is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC It is measured in dB Digital Crosstalk Digital crosstalk is a measure of the impulse injected into the analog output of one DAC from the digital inputs of another DAC but is measured when the DAC output is not updated It is specified in nV secs and measured with a full scale code change on the data bus that is from all Os to all 1s and vice versa Rev PrE Page 14 of 32 TYPICAL PERFORMANCE CHARACTERISTICS INL ERROR LSB INL ERROR LSB DNL ERROR LSB 0 25 0 20 0 15 0 10 0 05 0 10 0 15 0 20 0 25 0 25 0 20 0 15 0 10 0 05 0 05 0 10 0 15 0 20 0 25 TA 25 C Vpp Vss 15V REFIN 5V 0 2000 4000 6000 8000 CODE 1000 12000 14000 16000 Figure 7 Integral Nonlinearity Error vs Code Vpp Vss 15 V Ta 25 C Vpp Vss 12V REFIN 5V m fl I i Po wi M LL m m NT 20
26. N 7V Output Voltage Drift vs Time 13 13 ppm FSR 500 hours typ 15 15 ppm FSR 1000 hours typ Short Circuit Current 10 10 mA typ Riscc 6 kO see Figure 31 Load Current 1 1 mA max For specified performance Capacitive Load Stability RL 200 200 pF max R 2 10 kO 1000 1000 pF max DC Output Impedance 0 3 0 3 O max Rev PrE Page 4 of 32 AD5744 Parameter B Grade C Grade Unit Test Conditions Comments DIGITAL INPUTS DVcc 2 7 V to 5 25 V JEDEC compliant Vin Input High Voltage 2 2 V min Vi Input Low Voltage 0 8 0 8 V max Input Current 1 1 HA max Per pin Pin Capacitance 10 10 pF max Per pin DIGITAL OUTPUTS DO D1 SDO Output Low Voltage 0 4 0 4 V max DVc 5 V 5 sinking 200 HA Output High Voltage DVcc 1 DVcc 1 V min DVcc 5 V 596 sourcing 200 uA Output Low Voltage 0 4 0 4 V max DVcc 2 7 V to 3 6 V sinking 200 uA Output High Voltage DVcc 0 5 DVcc 0 5 V min DVcc 2 7 V to 3 6 V sourcing 200 HA High Impedance Leakage 1 1 uA max SDO only Current High Impedance Output 5 5 pF typ SDO only Capacitance POWER REQUIREMENTS AVop AVss 11 4 16 5 11 4 16 5 V min V max DVcc 2 7 5 25 2 7 5 25 V min V max Power Supply Sensitivity AVour AAVpp _85 _85 dB typ Alop 3 5 3 5 mA channel max Outputs unloaded Alss 2 75 2 75 mA channel max Outputs unloaded Dicc 1 2 1 2 mA max Vin DVcc Vi DGND 750 pA typ Power Dissipation 275 275 mW typ 12 V operation output unloaded Temperatu
27. Vrer 1 LSB Full scale error is expressed in percentage of full scale range Negative Full Scale Error Zero Scale Error Negative full scale error is the error in the DAC output voltage when 0x0000 offset binary coding or 0x8000 twos complement coding is loaded to the DAC register Ideally the output voltage should be 2 x Vzzr A plot of zero scale error vs temperature can be seen in Figure 21 Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full scale input change Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage The output slewing speed of a voltage output D A converter is usually limited by the slew rate of the amplifier used at its output Slew rate is measured from 1096 to 9096 of the output signal and is given in V us AD5744 Gain Error Gain error is a measure of the span error of the DAC It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as a percentage of the full scale range A plot of gain error vs temperature can be seen in Figure 23 Total Unadjusted Error Total unadjusted error TUE is a measure of the output error considering all the various errors A plot of total unadjusted error vs reference can be seen in Figure 19 Zero Scale Error TC Zero scale error TC is a measure of the change in zero scale error with a change i
28. d negative reference for the DAC cores The positive reference is given by 06063 060 Vrer 2 X Vrer While the negative reference to the DAC cores is given by Vrer 2 X Vrer These positive and negative reference voltages along with the gain register values define the output ranges of the DACs SERIAL INTERFACE The AD5744 is controlled over a versatile 3 wire serial interface that operates at clock rates of up to 30 MHz and is compatible with SPI QSPI MICROWIRE and DSP standards Input Shift Register The input shift register is 24 bits wide Data is loaded into the device MSB first as a 24 bit word under the control of a serial clock input SCLK The input register consists of a read write bit three register select bits three DAC address bits and 16 data bits as shown in Table 8 The timing diagram for this operation is shown in Figure 2 Upon power up the DAC registers are loaded with zero code 0x0000 and the outputs are clamped to 0 V via a low impedance path The outputs can be updated with the zero code value at this time by asserting either LDAC or CLR The corresponding output voltage depends on the state of the BIN 2sCOMP pin If the BIN 2sCOMP pin is tied to DGND then the data coding is twos complement and the outputs update to 0 V If the BIN 2sCOMP pin is tied to DVcc then the data coding is offset binary and the outputs update to negative full scale To have the outputs power up with zero code
29. d isolate the controlling circuitry from any hazardous common mode voltages that might occur Isocouplers provide voltage isolation in excess of 2 5 kV The serial loading structure of the AD5744 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum Figure 37 shows a 4 channel isolated interface to the AD5744 using an ADuM1400 For more information go to www analog com AD5744 HCONTROLLER ADuM14001 Va T N Voa SERIAL CLOCK OUT bz ENCODE 3 DECODE H le TO SCLK Ve P ECODE mN Vos SERIAL DATA OUT J ENCODE DECODE 4l TO SDIN Vic m gt Voc SYNC OUT ENCODE DECODE H TO SYNC Vp P mN Vop CONTROL OUT ENCODE DECODE H gt TO LDAC TADDITIONAL PINS OMITTED FOR CLARITY 06063 065 Figure 37 Isolated Interface MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5744 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors The communications channel is a 3 wire minimum interface consisting of a clock signal a data signal and a synchronization signal The AD5744 requires a 24 bit data word with data valid on the falling edge of SCLK For all the interfaces the DAC output update can be done automatically when all the data is clocked in or it can be done under the control of LDAC The contents of the DAC register can be
30. enabled by writing to the function register and clearing the SDO DISABLE bit this bit is cleared by default Readback mode is invoked by setting the R W bit 1 in the serial input register write With R W 1 Bit A2 to Bit AO in association with Bit REG2 Bit REG1 and Bit REGO select the register to be read The remaining data bits in the write sequence are dont care During the next SPI write the data appearing on the SDO output contain the data from the previously addressed register For a read of a single register the NOP command can be used in clocking out the data from the selected register on SDO The readback diagram in Figure 4 shows the readback sequence For example to read back the fine gain register of Channel A on the AD5744 the following sequence should be implemented 1 Write OXAOXXXX to the AD5744 input register This configures the AD5744 for read mode with the fine gain register of Channel A selected Note that all the data bits DB15 to DBO are dont care 2 Follow this with a second write a NOP condition 0x00XXXX During this write the data from the fine gain register is clocked out on the SDO line that is data clocked out contains the data from the fine gain register in Bit DB5 to Bit DBO SIMULTANEOUS UPDATING VIA LDAC Depending on the status of both SYNC and LDAC and after data has been transferred into the input register of the DACs there are two ways in which the DAC registers and DAC outputs can be
31. ervo control and open loop control applications The AD5744 is available in a 32 lead TQEP and offers guaranteed specifications over the 40 C to 85 C industrial temperature range See Figure 1 the functional block diagram Table 1 Related Devices Part No Description AD5744R AD5744 with Internal voltage reference AD5764 Complete Quad 16 Bit High Accuracy Serial Input Bipolar Voltage Output DACs AD5764R AD5764 with internal voltage reference One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2006 Analog Devices Inc All rights reserved AD5744 TABLE OF CONTENTS Features RP SPEED SS CSS CSE ESS 1 AP PLICATIONS ere EROR bao aasma 1 General Description oe DE ER 1 Revision History sse 2 Functional Block Diagram eerte 3 Specifications cce ESSET ERES EP fS 4 AC Performance Characteristic seen 6 Timing Characteristics a retient 7 Absolute Maximum Ratings essent 10 ESD Caution nete rennen ir tes 10 Pin Configuration and Function Descriptions 11 Terminology q qA q Sau huu a 13 Typical Performance Characteristics aaa 15 THe ory of Operation aceite ette tenens 20 DAG Architecture one teet t 20 Reference Buffers ede diete nene uen edente 20 Serial Interface a aq aq reae te Reb uuu 20 Simultaneous Updating via LDA
32. g mode The ADSP2101 ADSP2103 are programmed through the SPORT control register and should be configured as follows internal clock operation active low framing and 24 bit word length Transmission is initiated by writing a word to the TX register after the SPORT has been enabled As the data is clocked out of the DSP on the rising edge of SCLK no glue logic is required to interface the DSP to the DAC In the interface shown the DAC output is updated using the LDAC pin via the DSP Alterna tively the LDAC input could be tied permanently low and then the update takes place automatically when TFS is taken high ADSP2101 AD5744 ADSP21031 TADDITIONAL PINS OMITTED FOR CLARITY Figure 40 AD5744 to ADSP2101 ADSP2103 Interface 06063 068 AD5744 to PIC16C6x 7x Interface The PIC16C6x 7x synchronous serial port SSP is configured as an SPI master with the clock polarity bit set to 0 This is done by writing to the synchronous serial port control register SSPCON See the PIC16 17 Microcontroller User Manual In this example I O port RA1 is being used to pulse SYNC and enable the serial port of the AD5744 This microcontroller transfers only eight bits of data during each serial transfer operation therefore three consecutive write operations are needed Figure 41 shows the connection diagram Rev PrE Page 28 of 32 AD5744 PIC16C6x 7x AD5744 SDI RC4 D 06063 069 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 4
33. hat contain several devices the SDO pin can be used to daisy chain several devices together This daisy chain mode can be useful in system diagnostics and in reducing the number of serial interface lines The first falling edge of SYNC starts the write cycle The SCLK is continuously applied to the input shift register when SYNC is low If more than 24 clock pulses are applied the data ripples out of the shift register and appears on the SDO line This data is clocked out on the rising edge of SCLK and is valid on the falling edge By connecting the SDO of the first device to the SDIN input of the next device in the chain a multidevice interface is constructed Each device in the system requires 24 clock pulses Therefore the total number of clock cycles must equal 24N where N is the total number of AD5744 devices in the chain When the serial transfer to all devices is complete SYNC is taken high This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register The serial clock can be a continuous or a gated clock AD5744 A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles In gated clock mode a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data Readback Operation Before a readback operation is initiated the SDO pin must be
34. ion Rev PrE Page 12 of 32 TERMINOLOGY Relative Accuracy or Integral nonlinearity INL For the DAC relative accuracy or integral nonlinearity INL is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function A typical INL vs code plot can be seen in Figure 7 Differential Nonlinearity DNL Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity This DAC is guaranteed monotonic A typical DNL vs code plot can be seen in Figure 9 Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code The AD5744 is monotonic over its full operating temperature range Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ideal half scale output of 0 V when the DAC register is loaded with 0x8000 offset binary coding or 0x0000 twos complement coding A plot of bipolar zero error vs temperature can be seen in Figure 22 Bipolar Zero TC Bipolar zero TC is the measure of the change in the bipolar zero error with a change in temperature It is expressed in ppm FSR C Full Scale Error Full scale error is a measure of the output error when full scale code is loaded to the DAC register Ideally the output voltage should be 2 x
35. ired is important Precision voltage references such as the ADR435 XFET design produce low output noise in the 0 1 Hz to 10 Hz region However as the circuit bandwidth increases filtering the output of the reference may be required to minimize the output noise Table 17 Some Precision References Recommended for Use with the AD5744 Part No Initial Accuracy mV Max Long Term Drift ppm Typ Temp Drift ppm C Max 0 1 Hz to 10 Hz Noise uV p p Typ ADR435 6 30 3 3 4 ADR425 6 50 3 3 4 ADRO2 5 50 3 15 ADR395 6 50 25 5 AD586 2 5 15 10 4 Rev PrE Page 26 of 32 LAYOUT GUIDELINES In any circuit where accuracy is important careful consider ation of the power supply and ground return layout helps to ensure the rated performance The printed circuit board on which the AD5744 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board If the AD5744 is in a system where multiple devices require an AGND to DGND connection the connection should be made at one point only The star ground point should be established as close as possible to the device The AD5744 should have ample supply bypassing of 10 uF in parallel with 0 1 uF on each supply located as close to the package as possible ideally right up against the device The 10 uF capacitors are the tantalum bead type The 0 1 uF capacitor should have low effective series resista
36. loaded to the outputs the CLR pin should be held low during power up Standalone Operation The serial interface works with both a continuous and noncon tinuous serial clock A continuous SCLK source can only be used if SYNC is held low for the correct number of clock cycles In gated clock mode a burst clock containing the exact number of clock cycles must be used and SYNC must be taken high after the final clock to latch the data The first falling edge of SYNC starts the write cycle Exactly 24 falling clock edges must be applied to SCLK before SYNC is brought back high again If SYNC is brought high before the 24 falling SCLK edge then the data written is invalid If more than 24 falling SCLK edges are applied before SYNC is brought high then the input data is also invalid The register addressed is updated on the rising edge of SYNC In order for another serial transfer to take place SYNC must be brought low again After the end of the serial data transfer data is automatically transferred from the input shift register to the addressed register When the data has been transferred into the chosen register of the addressed DAC all DAC registers and outputs can be updated by taking LDAC low Rev PrE Page 20 of 32 68HC111 AD5744 SDIN AD5744 SDIN AD5744 SCLK SYNC LDAC 06063 061 ADDITIONAL PINS OMITTED FOR CLARITY Figure 33 Daisy Chaining the AD5744 Daisy Chain Operation For systems t
37. n temperature Zero scale error TC is expressed in ppm FSR C Gain Error TC Gain error TC is a measure of the change in gain error with changes in temperature Gain Error TC is expressed in ppm of FSR C Digital to Analog Glitch Energy Digital to analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state It is normally specified as the area of the glitch in nV secs and is measured when the digital input code is changed by 1 LSB at the major carry transition 0x7FFF to 0x8000 see Figure 28 Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated It is specified in nV secs and measured with a full scale code change on the data bus that is from all 0s to all 1s and vice versa Power Supply Sensitivity Power supply sensitivity indicates how the output of the DAC is affected by changes in the power supply voltage DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC It is measured with a full scale output change on one DAC while monitoring another DAC and is expressed in LSBs DAC to DAC Crosstalk DAC to DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DA
38. nce ESR and low effective series inductance ESI such as the common ceramic types which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching The power supply lines of the AD5744 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs A ground line routed between the SDIN and SCLK lines helps reduce cross talk between them not required on a multilayer board which has a separate ground plane however it is helpful to separate the lines It is essential to minimize noise on the reference inputs because it couples through to the DAC output Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles to each other This reduces the effects of feed through on the board A microstrip technique is recommended but not always possible with a double sided board In this technique the component side of the board is dedicated to ground plane while signal traces are placed on the solder side GALVANICALLY ISOLATED INTERFACE In many process control applications it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect an
39. r function register REG2 REG1 REGO Function 0 0 0 Function Register 0 1 0 Data Register 0 1 1 Coarse Gain Register 1 0 0 Fine Gain Register A2 A1 AO These bits are used to decode the DAC channels A2 Al AO Channel Address 0 0 0 DACA 0 0 1 DAC B 0 1 0 DAC C 0 1 1 DAC D 1 0 0 ALL DACs D15 DO Data Bits FUNCTION REGISTER The function register is addressed by setting the three REG bits to 000 The values written to the address bits and the data bits determine the function addressed The functions available via the function register are outlined in Table 10 and Table 11 Table 10 Function Register Options REG2 REG1 REGO A2 A1 AO DB15 DB6 DB5 DB4 DB3 DB2 DB1 DBO 0 0 0 0 0 0 NOP Data Don t Care 0 0 0 0 0 1 Don t Care Local D1 Direction D1 DO DO SDO Ground Value Direction Value Disable Offset Adjust 0 0 0 1 0 0 CLR Data Don t Care 0 0 0 1 0 1 LOAD Data Don t Care Table 11 Explanation of Function Register Options Option Description NOP No operation instruction used in readback operations Local Ground Set by the user to enable local ground offset adjust function Cleared by the user to disable local ground offset adjust Offset Adjust function default Refer to Features section for further details DO D1 Set by the user to enable DO D1 as outputs Cleared by the user to enable DO D1 as inputs default Refer to the Features Direction section for
40. re range 40 C to 85 C typical at 25 C Device functionality is guaranteed to 105 C with degraded performance 3 Guaranteed by design and characterization not production tested Output amplifier headroom requirement is 1 4 V minimum Rev PrE Page 5 of 32 AD5744 AC PERFORMANCE CHARACTERISTIC AVpp 11 4 V to 16 5 V AVss 11 4 V to 716 5 V AGND DGND REFGND PGND 0 V REFAB REFCD 5 V DVcc 2 7 V to 5 25 V Rroap 10 kO Cr 200 pF All specifications Tm to Tmax unless otherwise noted Guaranteed by design and characterization not production tested Table 3 Parameter BGrade CGrade Unit Test Conditions Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 8 8 us typ Full scale step to 1 LSB 10 10 us max 2 2 us typ 512 LSB step settling Slew Rate 5 5 V us typ Digital to Analog Glitch Energy 8 8 nV s typ Glitch Impulse Peak Amplitude 25 25 mV max Channel to Channel Isolation 80 80 dB typ DAC to DAC Crosstalk 8 8 nV s typ Digital Crosstalk 2 2 nV s typ Digital Feedthrough 2 2 nV s typ Effect of input bus activity on DAC outputs Output Noise 0 1 Hz to 10 Hz 0 025 0 025 LSB p p typ Output Noise 0 1 Hz to 100 kHz 45 45 uV rms max 1 f Corner Frequency 1 1 kHz typ Output Noise Spectral Density 60 60 nV VHz typ Measured at 10 kHz Complete System Output Noise Spectral 80 80 nV VHz typ Measured at 10 kHz Density Guaranteed by design and characterization not p
41. rface When configured as inputs these pins have weak internal pull ups to DVcc When programmed as outputs DO and D1 are referenced by DVcc and DGND 9 RSTOUT Reset Logic Output This is the output from the on chip voltage monitor used in the reset circuit If desired it can be used to control other system components 10 RSTIN Reset Logic Input This input allows external access to the internal reset logic Applying a Logic 0 to this input clamps the DAC outputs to 0 V In normal operation RSTIN should be tied to Logic 1 Register values remain unchanged 11 DGND Digital Ground Pin 12 DVcc Digital Supply Pin Voltage ranges from 2 7 V to 5 25 V 13 31 AVop Positive Analog Supply Pins Voltage ranges from 11 4 V to 16 5 V 14 PGND Ground Reference Point for Analog Circuitry 15 30 AVss Negative Analog Supply Pins Voltage ranges from 11 4 V to 16 5 V 16 ISCC This pin is used in association with an optional external resistor to AGND to program the short circuit current of the output amplifiers Refer to the Features section for further details 17 AGNDD Ground Reference Pin for DAC D Output Amplifier 18 VOUTD Analog Output Voltage of DAC D Buffered output with a nominal full scale output range of 10 V The output amplifier is capable of directly driving a 10 kO 200 pF load 19 VOUTC Analog Output Voltage of DAC C Buffered output with a nominal full scale output range of 10 V The output amplifier is capable of directly driving a 10
42. roduction tested Includes noise contributions from integrated reference buffers 14 bit DAC and output amplifier Rev PrE Page 6 of 32 TIMING CHARACTERISTICS AVpp 11 4 V to 16 5 V AVss 11 4 V to 716 5 V AGND DGND REFGND PGND 0 V REFAB REFCD 5 V DVcc 2 7 V to 5 25 V Rioap 10 kO Cr 200 pF All specifications Tmn to Tmax unless otherwise noted AD5744 Table 4 Parameter 2 3 Limit at Tmn Tmax Unit Description t 33 ns min SCLK cycle time t 13 ns min SCLK high time ts 13 ns min SCLK low time ta 13 ns min SYNC falling edge to SCLK falling edge setup time ts4 13 ns min 24 SCLK falling edge to SYNC rising edge ts 40 ns min Minimum SYNC high time t 2 ns min Data setup time ts 5 ns min Data hold time to 1 4 us min SYNC rising edge to LDAC falling edge all DACs updated 400 ns min SYNC rising edge to LDAC falling edge single DAC updated tio 10 ns min LDAC pulse width low tn 500 ns max LDAC falling edge to DAC output response time tie 10 us max DAC output settling time tis 10 ns min CLR pulse width low ta 2 us max CLR pulse activation time tis 6 25 ns max SCLK rising edge to SDO valid tie 20 ns min SYNC rising edge to SCLK rising edge ty 2 us min SYNC rising edge to DAC output response time LDAC 0 tis 170 ns min LDAC falling edge to SYNC rising edge Guaranteed by design and characterization not production tested 2 All input signals are specified with t
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