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MCS® 51 Microcontroller Family User`s Manual

1. As A 2 25 intel 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 11 Instruction Opcodes in Hexadecimal Order Continued Hex Number Hex Number Mnemonic Operands Mnemonic Operands Code ofBytes Code of Bytes 1 A RO 1 SUBB 1 1 A R1 1 5088 A R2 1 A RO 1 SUBB A R3 1 A R1 1 SUBB 1 A R2 1 SUBB AR5 1 A R3 1 SUBB A R6 1 1 SUBB 7 1 5 2 ORL C bit addr 1 A R6 2 AJMP code addr 1 7 2 C bit addr 2 code addr 1 INC DPTR 2 code addr 1 MUL AB 2 C bit addr 1 A DPTR 2 Ro data addr 2 A data 2 MOV GR1 data addr 3 data addr data 2 MOV RO data addr 2 GRO data 2 MOV R1 data addr 2 R1 data 2 MOV Re data addr 2 RO data 2 MOV R3 data addr 2 R1 data 2 MOV R4 data addr 2 R2 data 2 MOV R5 data addr 2 83 4 data 2 MOV R6 data addr 2 4 data 2 MOV R7 data addr 2 R5 data 2 ANL C bit addr 2 R6 data 2 ACALL code addr 2 R7 data 2 CPL bit addr 2 code addr 1 CPL 2 code addr 3 CJNE A data code addr 2 C bit addr 3 A data addr code addr 1 A GA PC 3 CJNE RO data code addr 1 AB 3 CJNE R1 data code addr 3 data addr data addr 3 CJNE RO data code addr 2 data addr R0 3 CJNE 1 data code addr 2 data addr R1 3 Re data code addr 2 data addr RO 3 CJNE data code addr 2 data addr R1 3 CJNE R4 data code addr 2 data addr R2 3 CJNE R5 data
2. Po p Figure 5 Bit Addressable 8 Bytes 2 10 FF EF E7 DF D7 CF C7 BF B7 AF A7 9F 97 8F 87 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Those SFRs that have their bits assigned for various functions are listed in this section A brief description of each bit is provided for quick reference For more detailed information refer to the Architecture Chapter of this book PSW PROGRAM STATUS WORD BIT ADDRESSABLE Lo sc ov gt PSW 7 Carry Flag 25 PSW 6 Auxiliary Carry Flag FO PSW 5 Flag 0 available to the user for general purpose 51 PSW 4 Register Bank selector bit 1 SEE NOTE 1 RSO PSW 3 Register Bank selector bit 0 SEE NOTE 1 PSW 2 Overflow Flag PSW 1 User definable flag P PSW 0 Parity Set cleared by hardware each instruction cycle to indicate odd even number of P bits in the accumulator NOTE 1 The value presented by RS0 and RS1 selects the corresponding register bank __ RS Register Bank 00H 07H 08H 0FH 10H 17H 18H 1FH PCON POWER CONTROL REGISTER NOT BIT ADDRESSABLE smop Po SMOD Double baud rate bit If Timer 1 is used to generate baud rate and SMOD 1 the baud rate is doubled when the Serial Port is used in modes 1 2 or 3 Not implemented reserved for future use Not implem
3. must be an integer value Rounding off to the nearest integer may not produce the desired baud rate In this case the user may have to choose another crystal frequency Since the PCON register is not bit addressable one way to set the bit is logical ORing the PCON register ie ORL PCON 80H The address of PCON is 87H USING TIMER COUNTER 2 TO GENERATE BAUD RATES For this purpose Timer 2 must be used in the baud rate generating mode Refer to Timer 2 Setup Table in this chapter If Timer 2 is being clocked through pin T2 P1 0 the baud rate is Bai Fia 2 Fists 16 And if it is being clocked internally the baud rate is Osc Freq o Baud Rate 57 65536 RCAP2H RCAP2D To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as Osc Freq RCAP2H RCAP2L 65536 32 x Baud Rate SERIAL PORT IN MODE 2 The baud rate is fixed in this mode and is 15 of the oscillator frequency depending on the value of the SMOD bit in the PCON register In this mode none of the Timers are used and the clock comes from the internal phase 2 clock SMOD 1 Baud Rate 7 4 Osc Freq SMOD 0 Baud Rate Osc Freq To set the SMOD bit ORL 80 The address of PCON is 87H SERIAL PORT IN MODE 3 The baud rate in mode 3 is variable and sets up exactly the same as in mode 1 2 20 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MCS 51
4. 8051 8052 AND 80C51 HARDWARE DESCRIPTION INTRODUCTION This chapter presents a comprehensive description of the on chip hardware features of the 51 micro controllers Included in this description are The port drivers and how they function both as ports and for Ports 0 and 2 in bus operations The Timer Counters The Serial Interface The Interrupt System Reset The Reduced Power Modes in the CHMOS devices The EPROM versions of the 8051 8052AH and 80C51BH The devices under consideration are listed in Table 1 it becomes unwieldy to be constantly referring to each of these devices by their individual names we will adopt a convention of referring to them generically as 8051s and 8052s unless a specific member of the group is being referred to in which case it will be specifically named The 8051s include the 8051 80C51BH and their ROMIess and versions The 80525 the 8052 8032AH and 8752BH Figure 1 shows a functional block diagram of the 8051s and 8052s Table 1 The MCS 51 Family of Microcontrollers 8051AH 8052AH 80C51BH 8031AH 8032AH 80C31BH 8751H 8751BH 8752BH 87C51 Special Function Registers Device ROMless EPROM ROM 6 bit Name Version Version ix a HMOS A map of the on chip memory area called SFR Special Function Register space is shown in Figure 2 SFRs marked by paren
5. CHMOS Power Reduction Modes CHMOS versions have two power reducing modes Idle and Power Down The input through which back up power is supplied during these operations is VCC Figure 27 shows the internal circuitry which imple ments these features In the Idle mode IDL 1 the oscillator continues to run and the Interrupt Serial Port and Timer blocks continue to be clocked but the intel clock signal is gated off to the CPU In Power Down PD 1 the oscillator is frozen The Idle and Power Down modes are activated by setting bits in Special Function Register PCON The address of this register is 87H Figure 26 details its contents In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices User software should never write 1 to unimplemented bits since they may be used in future MCS 51 products IDLE MODE An instruction that sets causes that to be the last instruction executed before going into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the Interrupt Timer and Serial Port functions The CPU status is preserved in its entirety the Stack Pointer Program Counter Program Status Word Accumulator and all other reg isters maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high levels There two way
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7. 1 21 pleted in less time than it takes other architectures to commence them SIMULATING A THIRD PRIORITY LEVEL IN SOFTWARE Some applications require more than the two priority levels that are provided by on chip hardware in MCS 51 devices In these cases relatively simple soft ware can be written to produce the same effect as a third priority level First interrupts that are to have higher priority than 1 are assigned to priority 1 in the IP Interrupt Priority register The service routines for priority 1 interrupts that are supposed to be interruptible by priority 2 interrupts are written to include the following code PUSH IE MOV MASK CALL LABEL execute service routine 12224443 LABEL RETI IE intel MCS 51 ARCHITECTURAL OVERVIEW As soon as any priority 1 interrupt is acknowledged the IE Interrupt Enable register is re defined so as to disable all but priority 2 interrupts Then a CALL to LABEL executes the RETI instruction which clears the priority 1 interrupt in progress flip flop At this point any priority 1 interrupt that is enabled can be serviced but only priority 2 interrupts are enabled POPping IE restores the original enable byte Then a normal RET rather than another RETT is used to terminate the service routine The additional software adds 10 ps at 12 MHz to priority 1 interrupts 1 22 ADDITIONAL REFERENCES The following appli
8. Encoding Operation Load Data Pointer with a 16 bit constant The Data Pointer is loaded with the 16 bit constant indicated The 16 bit constant is loaded into the second and third bytes of the instruction The second byte DPH is the high order byte while the third byte DPL holds the low order byte No flags are affected This is the only instruction which moves 16 bits of data at once The instruction MOV DPTR 1234H will load the value 1234H into the Data Pointer DPH will hold 12H and DPL will hold 34H 3 2 0000 immed data15 8 immed data7 0 MOV PTR lt datajs 0 DPH DPL ddatas s O data7 9 2 56 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET A A lt base reg gt Function Move Code byte Description The instructions load the Accumulator with a code byte or constant from program memory The address of the byte fetched is the sum of the original unsigned eight bit Accumu lator contents and the contents of a sixteen bit base register which may be either the Data Pointer or the PC In the latter case the PC is incremented to the address of the following instruction before being added with the Accumulator otherwise the base register is not al tered Sixteen bit addition is performed so a carry out from the low order eight bits may propagate through higher order bits No flags are affected Example value between 0 and 3 is in the Accumulator The following instr
9. Function Description Example Bytes Cycles Encoding Operation CLR bit Function Description Example CLR C Bytes Cycles Encoding Operation CLR bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Clear Accumulator The Accumulator is cleared all bits set on zero No flags are affected The Accumulator contains 5CH 01011100B The instruction CLR A will leave the Accumulator set to 000000008 1 1 CLR 0 Clear bit The indicated bit is cleared reset to zero No other flags are affected CLR can operate on the carry flag or any directly addressable bit Port 1 has previously been written with SDH 01011101B The instruction CLR 12 will leave the port set to 59H 01011001B 1100 0011 CLR 0 2 1 CLR bit 0 2 37 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CPL A Function Complement Accumulator Description Each bit of the Accumulator is logically complemented one s complement Bits which previ ously contained a one are changed to a zero and vice versa No flags are affected Example Accumulator contains 5 01011100B The instruction CPL A will leave the Accumulator set to 10100011B Bytes 1 Cycles 1 Encoding 1111 0100 Operation CPL lt 71 CPL bit Function Complement bit Description bit varia
10. tion time as the sum of the 16 bit DPTR register and the Accumulator Typically DPTR is set up with the address of a jump table and the Accumulator is given an index to the table In a 5 way branch for example an integer O through 4 is loaded into the Accumulator The code to be executed might be as follows MOV DPTR JUMP TABLE MOV A JINDEX NUMBER RL A JMP DPTR The RL instruction converts the index number 0 through 4 to an even number on the range 0 through 8 because each entry in the jump table is 2 bytes long JUMP TABLE AJMP CASE 0 AJMP CASE 1 AJMP CASE 2 AJMP CASE 3 AJMP CASE 4 Table 8 shows a single CALL addr instruction but there two of them LCALL and ACALL which differ in the format in which the subroutine address is given to the CPU CALL is a generic mnemonic which can be used if the programmer does not care which way the address is encoded The LCALL instruction uses the 16 bit address format and the subroutine can be anywhere in the 64K Pro gram Memory space The ACALL instruction uses the 11 bit format and the subroutine must be in the same 2K block as the instruction following the ACALL In any case the programmer specifies the subroutine address to the assembler in the same way as a label or as a 16 bit constant The assembler will put the address into the correct format for the given instructions Subroutines should end with a RET instruction which returns
11. Operation MOV direct Ri MOV direct data Bytes 3 Cycles 2 Encoding 0111 direct address immediate data Operation MOV direct lt data 2 54 intel Ri A Bytes Cycles Encoding Operation MOV Ri direct Bytes Cycles Encoding Operation Ri data Bytes Cycles Encoding Operation MCS 51 PROGRAMMER 5 GUIDE AND INSTRUCTION SET 1 1 MOV Ri 2 2 MOV direct 2 1 o111 o01tij MOV RD lt data MOV lt dest bit gt lt src bit gt Function Description Example Move bit data The Boolean variable indicated by the second operand is copied into the location specified by the first operand One of the operands must be the carry flag the other may be any directly addressable bit No other register or flag is affected The carry flag is originally set The data present at input Port 3 is 11000101B The data previously written to output Port 1 is 35H 00110101B MOV P1 3 C MOV 3 3 MOV P1 2 C will leave the carry cleared and change Port 1 to 39H 00111001B 2 55 intel C bit Bytes Cycles Encoding Operation MOV bit C Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 MOV lt tit 2 2 1001 bit address MOV bit C MOV OPTR data16 Function Description Example Bytes Cycles
12. Timer 0 TLO is an 8 bit Timer Counter controlled by the standard Timer 0 contro bits THO is an 8 bit timer only controlled by Timer 1 control bits Timer 1 Timer Counter 1 stopped Figure 6 TMOD Timer Counter Mode Control Register 3 10 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 INTERRUPT CONTROL 270252 9 Figure 7 Timer Counter 1 Mode 0 13 Bit Counter MSB LSB rer Tm m Name and Significance Timer 1 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 1 Run control bit Set cleared by software to tum Timer Counter on otf Timer 0 overflow Flag Set by hardware on Timer Counter overflow Cleared by hardware when processor vectors to interrupt routine Timer 0 Run control bit Set cleared by software to turn Timer Counter on off Symbol Position Name and Significance Interrupt 1 Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed Interrupt 1 Type contro bit Set Cleared by software to specify falling level triggered external interrupts Interrupt O Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed Interrupt O Type control bit Set cleared by software to specify falling level triggered external interrupts Figure 8 TCON Timer C
13. addition the transition at 2 causes bit EXF2 in T2CON to be set and EXF2 like TF2 can generate an interrupt The Capture Mode is illustrated in Figure 12 In the auto reload mode there are again two options which are selected by bit EXEN2 in T2CON If 2 0 then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2L and RCAP2H which are preset by software If EXEN2 then Timer 2 still does the above but with the 3 13 added feature that 1 10 0 transition at external input T2EX will also trigger the 16 bit reload and set EXF2 The auto reload mode is illustrated in Figure 13 The baud rate generator mode is selected by RCLK 1 and or TCLK 1 It will be described in conjunc tion with the serial port SERIAL INTERFACE The serial port is full duplex meaning it can transmit and receive simultaneously It is also receive buffered meaning it can commence reception of a second byte before a previously received byte has been read from the receive register However if the first byte still hasn t been read by the time reception of the second byte is complete one of the bytes will be lost The Serial port receive and transmit registers are both ac cessed at Special Function Register SBUF Writing to SBUF loads the transmit register and reading SBUF accesses a physically separate receive register HARDWARE DES
14. ditions 1 An interrupt of equal or higher priority level is al ready in progress The current polling cycle is not the final cycle in the execution of the instruction in progress The instruction in progress is RETI or any write to the IE or IP registers 2 3 Any of these three conditions will block the generation of the LCALL to the interrupt service routine Condi tion 2 ensures that the instruction in progress will be INTERRUPT ROUTINE 270252 20 This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP Figure 24 Interrupt Response Timing Diagram 3 24 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 completed before vectoring to any service routine Con dition 3 ensures that if the instruction in progress is RETI or any access to IE or IP then at least one more instruction will be executed before any interrupt is vec tored to The polling cycle is repeated with each machine cycle and the values polled are the values that were present at SSP2 of the previous machine cycle Note then that if an interrupt flag is active but not being responded to for one of the above conditions and is not still active when the blocking condition is removed the denied interrupt will not be serviced In other words the fact that the interrupt flag was once active but not serviced is not remembered Every polling cycle is new The polling cycle
15. location in Program Memory The interrupt causes the CPU to jump to that location where it commences exe cution of the service routine External Interrupt 0 for example is assigned to location 0003H If External In terrupt 0 is going to be used its service routine must begin at location 0003H If the interrupt is not going to be used its service location is available as general pur pose Program Memory 0033H 0028H 0023H INTERRUPT LOCATIONS 001BH 8 BYTES 0013H 0008H 0003H 0000H 270251 3 Figure 3 MCS 51 Program Memory The interrupt service locations are spaced at 8 byte in tervals 0003H for External Interrupt 0 000BH for Timer 0 0013H for External Interrupt 1 001BH for Timer 1 etc If an interrupt service routine is short enough as is often the case in control applications it can reside entirely within that 8 byte interval Longer service routines can use a jump instruction to skip over subsequent interrupt locations if other interrupts are in use The lowest 4K or 8K or 16K bytes of Program Mem ory can be either in the on chip ROM or in an external ROM This selection is made by strapping the EA Ex ternal Access pin to either Vcc or Vss In the 4K byte ROM devices if the E pin is strapped to then program fetches to addresses 0000H through 0FFFH are directed to the internal ROM Pro gram fetches to addresses 1000H through FFFFH are directed to external ROM In the
16. lt 40H RLA Rl lt 40H B lt 10H R1 P1 40H lt P2 P1 P2 leaves the value 30H in register 0 40H in both the Accumulator and register 1 10H in register B and OCAH 11001010B both in RAM location 40H and output on port 2 2 1 0101 direct address MOV direct MOV A ACC is not a valid instruction 2 52 intel MOV A Ri Bytes Cycles Encoding Operation MOV A data Bytes Cycles Encoding Operation MOV Rn A Bytes Cycles Encoding Operation MOV Rn direct Bytes Cycles Encoding Operation Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 MOV A Ri 2 1 0111 0100 immediate data MOV data 1 1 MOV Rn A 2 2 MOV Rn direct 2 1 MOV Rn lt data immediate data 2 53 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOV direct A Bytes 2 Cycles 1 Encoding 111110101 direct address Operation direct lt direct Rn Bytes 2 Cycles 2 Encoding direct address Operation MOV direct Rn MOV direct direct Bytes 3 Cycles 2 Encoding 1000 0101 dir addr src dir addr dest Operation MOV direct direct MOV direct GRi Bytes 2 Cycles 2 KEPE TM
17. write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse oc curs one bit time after that intel As data bits shift out to the right zeroes are clocked in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initially loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 10 divide by 16 rollover after write to SBUF Reception is initiated by a detected 1 10 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is imme diately reset and 1FFH is written into the input shift register Resetting the divide by 16 counter aligns its rollovers with the boundaries of the incoming bit times The 16 states of the counter divide each bit time into 16155 At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is
18. 1 amp 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1 amp 3 TCLK O causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port 2 0 causes Timer 2 to ignore events at T2EX Software START STOP control for Timer 2 A logic 1 starts the Timer Timer or Counter select 0 Internal Timer 1 External Event Counter falling edge triggered Capture Reload flag When set captures will occur on negative transitions at 2 if EXEN2 1 When cleared Auto Reloads will occur either with Timer 2 overflows or negative transitions at 2 when 2 1 When either RCLK 1 or TCLK 1 this bit is ignored and the Timer is forced to Auto Reload on Timer 2 overflow intel MCS9 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TIMER COUNTER 2 SET UP Except for the baud rate generator mode the values given for T2CON do not include the setting of the TR2 bit Therefore bit TR2 must be set separately to turn the Timer on As a Timer Tabie 7 INTERNAL EXTERNAL CONTROL CONTROL NOTE 1 NOTE 2 16 bit Auto Reload 16 bit Capture BAUD rate generator receive amp transmit same baud rate receive only transmit
19. 155 tors for Microcontrollers which is included in the Embedded Applications Handbook To drive the HMOS parts with an external clock source apply the external clock signal to XTAL2 and ground XTALI as shown in Figure 32 A pullup resis tor may be used to increase noise margin but is op tional if VOH of the driving gate exceeds the VIH MIN specification of XTAL2 270252 25 Figure 32 Driving the HMOS MCS 51 Parts with an External Clock Source CHMOS Versions The on chip oscillator circuitry for the 80C51BH Shown in Figure 33 consists of a single stage linear inverter intended for use as a crystal controlled posi tive reactance oscillator in the same manner as the HMOS parts However there are some important dif ferences One difference is that the 80C51BH is able to turn off its oscillator under software control by writing a 1 to the PD bit in PCON Another difference is that in the 80C51BH the internal clocking circuitry is driven by the signal at XTAL1 whereas in the HMOS versions it is by the signal at XTAL2 The feedback resistor Ry in Figure 33 consists of paral leled n and p channel FETs controlled by the PD bit such that Rr is opened when PD 1 The diodes D1 and D2 which act as clamps to VCC and VSS are parasitic to the FETs The oscillator can be used with the same external com ponents as the HMOS versions as shown in Figure 34 Typically C2 30 pF when
20. 17 Figure 19 Serial Port Mode 2 3 21 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 8051 INTERNAL BUS TIMER 1 TIMER 2 OVERFLOW OVERFLOW 8051 INTERNAL BUS TX LOC WRITE TO SBUF roc ___ 11 01 41 A A _ _ R k _ 1 __ pong pee S1P1 4 fl 1 TRANSMIT SHIFT Txo STOP BIT 1I STOP BIT GEN RX 16 RESET CLOCK gir DETECTOR STOP RECEIVE SAMPLE TIMES AM BIT SH RI J 525 f 270252 18 Figure 20 Serial Port Mode 3 TCLK RCLK and Timer 2 are Present in the 8052 8032 Only 3 22 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in Modes 2 and 3 is a 9 bit register it flags the RX Control block to do one last shift load SBUF and RB8 and set RI The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 RI 0 and 2 Either SM2 0 or the received Sth data bit 1 If either of these conditions is not met the received frame is irretrievably lost and RI is not set If both conditions are met the received 9th data bit goes into and the first 8 data bits go into SBUF One bit time later whether the above conditions were me
21. 2 external interrupts 2 timer interrupts and the serial port inter rupt What follows is an overview of the interrupt structure for the 8051 Other MCS 51 devices have ad ditional interrupt sources and vectors as shown in Ta ble 1 Refer to the appropriate chapters on other devic es for further information on their interrupts INTERRUPT ENABLES Each of the interrupt sources can be individually en abled or disabled by setting or clearing a bit in the SFR MSB LSB eA es er eo exo Enable bit 1 enables the interrupt Enable bit 0 disables it Symbol Position EA IE 7 Function disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit reserved reserved Serial Port Interrupt enabie bit Timer 1 Overflow Interrupt enable bit External Interrupt 1 enable bit ETO Timer 0 Overflow Interrupt enable bit EX0 External interrupt 0 enable bit These reserved bits are used in other MCS 51 devices ES ET1 EX1 Figure 17 IE Interrupt Enable Register in the 8051 1 20 named IE Interrupt Enable This register also con tains a global disable bit which can be cleared to dis able all interrupts at once Figure 17 shows the IE reg ister for the 8051 INTERRUPT PRIORITIES Each interrupt source can also be individually pro grammed to one of two priority levels b
22. 8K byte ROM devices Vcc selects ad dresses 0000H through to be internal and ad dresses 2000H through FFFFH to be external In the 16K byte ROM devices EA Vcc selects ad dresses OOOOH through 3FFFH to be internal and ad dresses 4000H through FFFFH to be external If the EA pin is strapped to Vss then all program fetches are directed to external ROM The ROMless parts must have this pin externally strapped to Vss to enable them to execute properly The read strobe to external ROM PSEN is used for all external program fetches PSEN is not activated for in ternal program fetches 270251 4 Figure 4 Executing from External Program Memory The hardware configuration for external program exe cution is shown in Figure 4 Note that 16 lines Ports 0 and 2 are dedicated to bus functions during external Program Memory fetches Port 0 PO in Figure 4 serves as a multiplexed address data bus It emits the low byte of the Program Counter PCL as an ad dress and then goes into a float state awaiting the arriv a of the code byte from the Program Memory During the time that the low byte of the Program Counter is valid on P0 the signal ALE Address Latch Enabie clocks this byte into an address latch Meanwhile Port 2 P2 in Figure 4 emits the high byte of the Program Counter PCH Then PSEN strobes the EPROM and the code byte is read into the microcontroller intel Program Memory addresses
23. C bit MOV J8 bit rel JNB bit rel JBC bit rel ACALL addrii LCALL 16 RET RETI AJMP 1 LJMP addr16 SJMP rel 2 23 Oscillator Description Byte BOOLEAN VARIABLE MANIPULATION Clear Carry Clear direct bit Set Carry Set direct bit Carry Complement direct bit AND direct bit to CARRY AND complement of direct bit to Carry OR direct bit to Carry OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry not set Jump if direct Bit is set Jump if direct Bit is Not set Jump if direct Bit is set amp clear bit PROGRAM BRANCHING Absolute Subroutine Call Long Subroutine Call Return from Subroutine Return from interrupt Absolute Jump Long Jump Short Jump relative addr All mnemonics copyrighted Intel Corporation 1980 intel PROGRAM BRANCHING Continued JMP JZ Mnemonic A DPTR A direct rel A data rel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 10 8051 Instruction Set Summary Continued Oscillator Period Description Jump indirect relative to the DPTR Jump if Accumulator is Zero Jump if Accumulator is Not Zero Compare direct byte to Acc and Jump if Not Equal Compare immediate to Acc and Jump if Not Equal Byte Mnemonic CJNE Ri data rel
24. DJNZ DJNZ direct rel Description PROGRAM BRANCHING Continued CJNE Rn data rel Compare immediate to register and Jump if Not Equal Compare immediate to indirect and Jump if Not Equal Decrement register and Jump if Not Zero Decrement direct byte and Jump if Not Zero No Operation Byte 1 Oscillator Period mnemonics copyrighted Intel Corporation 1980 2 24 I MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 11 Instruction Opcodes in Hexadecimal Order Hex Number Hex Number Code Bytes Mnemonic Operands Code of Bytes Mnemonic Operands code addr code addr A A data addr data addr A data addr data data A data addr A RO A R1 A RO A R2 A R3 A R4 A R5 6 A R7 code addr code addr data addr A data addr data A A data addr A RO A R1 A RO A R1 A R2 A R5 A R6 code addr code addr data data addr data data A data addr bit addr code addr code addr code addr A A data addr bit addr code addr code addr A A data A data addr A RO A GR1 AR1 AR2 A R3 5 AR6 AR bit addr code addr code addr 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1
25. Data Memory 270249 4 Figure 3b The 8052 Data Memory 2 5 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET INDIRECT ADDRESS AREA Note that in Figure 3b the SFRs and the indirect address RAM have the same addresses 8 Neverthe less they are two separate areas and are accessed in two different ways For example the instruction MOV 80H OAAH writes OAAH to Port 0 which is one of the SFRs and the instruction MOV 80 R0 0BBH writes OBBH in location 80H of the data Thus after execution of both of the above instructions Port 0 will contain OAAH and location 80 of the RAM will contain OBBH Note that the stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack space in those devices which implement 256 bytes of internal RAM DIRECT AND INDIRECT ADDRESS AREA The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments as listed below and shown in Figure 4 1 Register Banks 0 3 Locations O through 1FH 32 bytes ASM 51 and the device after reset default to register bank 0 To use the other register banks the user must select them in the software refer to the MCS 51 Micro Assembler User s Guide Each register bank contains 8 one byte registers O through 7 Reset initializes the Stack Pointer to location 07H and it is incremented once to start from location 08H which is th
26. Example Bytes Cycles Encoding Operation 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 INC lt Rn 1 2 1 INC direct lt direct 1 direct address 1 1 INC Ri Ri 1 Increment Data Pointer Increment the 16 bit data pointer by 1 16 bit increment modulo 216 is performed an overflow of the low order byte of the data pointer DPL from OFFH to 00H will increment the high order byte DPH No flags are affected This is the only 16 bit register which can be incremented Registers DPH and DPL contain 12H and OFEH respectively The instruction sequence INC DPIR INC DPTR INC DPTR will change DPH and DPL to 13H and 01H 1 2 INC DPTR DPTR 1 2 45 intel MCSe 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JB bit rel Function Jump if Bit set Description the indicated bit is one jump to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction bit tested is not modified No flags are affected Example The data present at input port 1 is 110010108 The Accumulator holds 56 01010110B The instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 will cause program execution to branch to the instruction at label
27. GUIDE AND INSTRUCTION SET Table 10 8051 Instruction Set Summary Continued Increment Data Pointer Multiply A amp B Divide B Decimal Adjust Accumulator AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive OR register to Accumulator Exclusive OR direct byte to Accumulator Exclusive OR indirect RAM to Accumulator Exclusive OR immediate data to Accumulator Exclusive OR Accumulator to direct byte Exclusive OR immediate data to direct byte Clear Accumulator Complement Accumulator MOV MOV MOV MOV 2 22 Mnemonic SWAP A DATA TRANSFER A direct A Ri A data Rn A Rn direct Rn data direct direct Rin direct direct direct Ri direct data Oscillator Description Period Byte LOGICAL OPERATIONS Continued Rotate Accumulator Left Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumuiator Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumula
28. LCALL sequence is illustrated in Figure 24 Note that if an interrupt of higher priority level goes active prior to S5P2 of the machine cycle labeled C3 in Figure 24 then in accordance with the above rules it will be vectored to during C5 and C6 without any in struction of the lower priority routine having been exe cuted Thus the processor acknowledges an interrupt request by executing a hardware generated LCALL to the ap propriate servicing routine In some cases it also clears the flag that generated the interrupt and in other cases it doesn t It never clears the Serial Port or Timer 2 flags This has to be done in the user s software It clears an external interrupt flag IEO or IE1 only if it was transition activated hardware generated LCALL pushes the contents of the Program Counter onto the stack but it does not save the PSW and re loads the PC with an address that depends on the source of the interrupt being vectored to as shown be low Vector Source Address IEO 0003H TF0 000BH IE1 0013 TF1 001BH RI TI 0023H TF2 EXF2 0028 Execution proceeds from that location until the instruction is encountered The RETI instruction in forms the processor that this interrupt routine is no longer in progress then pops the top two bytes from the stack and reloads the Program Counter Execution of the interrupted program continues from where it left off Note that a simple RET instruction would a
29. SFRs are outlined below ACCUMULATOR ACC is the Accumulator register The mnemonics for Accumulator Specific instructions however refer to the Accumulator simply as A B REGISTER The B register is used during multiply and divide oper ations For other instructions it can be treated as anoth er scratch pad register PROGRAM STATUS WORD The PSW register contains program status information as detailed in Figure 3 STACK POINTER The Stack Pointer Register is 8 bits wide It is incre mented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07H after a reset This causes the stack to begin at location 08H DATA POINTER The Data Pointer DPTR consists of a high byte DPH and a low byte DPL Its intended function is 3 5 to hold a 16 bit address It may be manipulated as a 16 bit register or as two independent 8 bit registers PORTS 0 TO 3 P1 P2 and P3 are the SFR latches of Ports 0 1 2 and 3 respectively SERIAL DATA BUFFER The Serial Data Buffer is actually two separate regis ters a transmit buffer and a receive buffer register When data is moved to SBUF it goes to the transmit buffer where it is held for serial transmission Moving a byte to SBUF is what initiates the transmission When data is moved from SBUF it comes from the receive buffer TIMER REGISTERS Register pairs THO TLO TH1
30. This may be done assuming no interrupts are enabled with the instruction sequence CLR 2 7 SETB 27 1 Cycles 1 Encoding 000010000 Operation 1 intel 1 MCS9 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ORL lt dest byte gt lt src byte gt Function Logical OR for byte variables Description ORL performs the bitwise logical OR operation between the indicated variables storing the results in the destination byte No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example If the Accumulator holds 11000011B and RO holds 55H 01010101B then the in struction ORL will leave the Accumulator holding the value 0D7H 11010111B When the destination is a directly addressed byte the instruction can set combinations of bits in any RAM location or hardware register The pattern of bits to be set is determined by a mask byte which may be either a constant data value in the instruction or a variable computed in the Accumulator at run t
31. a constant contained in the instruction or a value computed in the Accumulator at run time The instruction ANL 1 01110011 will clear bits 7 3 and 2 of output port 1 2 32 intel ANL A Rn Bytes Cycles Encoding Operation ANL A direct Bytes Cycles Encoding Operation ANL A Ri Bytes Cycles Encoding Operation ANL A data Bytes Cycles Encoding Operation ANL direct A Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 ANL 2 1 ANL A A direct 1 1 o101 0110 ANL A 2 1 ANL lt A f data 2 1 ANL direct direct A 2 33 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ANL direct data Bytes 3 Cycles 2 Encoding immediate data Operation ANL direct direct data ANL C lt src bit gt Function Logical AND for bit variables Description If the Boolean value of the source bit is a logical 0 then clear the carry flag otherwise leave the carry flag in its current state slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Only direct addressing is allowed for the source operand Example Set the car
32. array to encrypt the code bytes during EPROM verification The verifica Detailed procedures for programming and verifying tion procedure sequentially XNORs each code byte each device are given in the data sheets with one of the key bytes When the last key byte in the array is reached the verify routine starts over with the first byte of the array for the next code byte If the key Exposure to Light bytes are unprogrammed the XNOR process leaves the code byte unchanged With the key bytes programmed It is good practice to cover the EPROM window with the code bytes are encrypted and can be read correctly an opaque label when the device is in operation This is only if the key bytes are known in their proper order not so much to protect the EPROM array from inad Table 6 lists the number of encryption bytes available vertent erasure but to protect the and other on on the various products chip logic Allowing light to impinge on the silicon die while the device is operating can cause logical malfunc When using the encryption array one important factor tion should be considered If a code byte has the value 3 29 intel verifying the byte will produce the encryption byte value If a large block of code is left unpro grammed a verification routine will display the encryp tion array contents For this reason all unused code bytes should be programmed with some value other than OFFH and not all of them the same
33. as an inductive reactance in parallel resonance with capacitance exter nal to the crystal intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 23 Figure 29 On Chip Oscillator Circuitry in the HMOS Versions of the MCS 51 Family In general crystals used with these devices typically have the following specifications ESR Equivalent Series Resistance see Figure 31 Co Shunt Capacitance 7 0 pF max Load Capacitance 30 pF 3 pF Drive Level 1mWw 270252 24 Figure 30 Using the 5 On Chip Oscillator ESR OHMS The crystal specifications and capacitance values C1 and C2 in Figure 30 are not critical 30 pF can be used in these positions at any frequency with good quality crystals ceramic resonator can be used in place of 4 8 12 16 the crystal in cost sensitive applications When a ce CRYSTAL FREQUENCY in MHz ramic resonator is used C1 and C2 are normally select 270252 34 ed to be of somewhat higher values typically 47 The manufacturer of the ceramic resonator should be Figure 31 ESR vs Frequency consulted for recommendations on the values of these capacitors 3 31 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Frequency tolerance and temperature range are deter mined by the system requirements A more in depth discussion of crystal specifications ce ramic resonators and the selection of values for C1 and C2 can be found in Application Note
34. code addr 2 data addr R3 3 CJNE R6 data code addr 2 data addr R4 3 CJNE R7 data code addr 2 data addr R5 2 PUSH data addr 2 data R6 2 AJMP code addr 2 data addr R7 2 CLR bit addr 3 DPTR data 1 CLR 2 code addr 1 SWAP A 2 bit addr C 2 XCH A data addr 1 A A DPTR 1 XCH 2 A s data 1 XCH A GR1 2 A data addr 1 XCH A RO 1 A RO 1 XCH 1 1 1 A R2 1 A RO 1 2 26 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 11 Instruction Opcodes in Hexadecimal Order Continued Number of Bytes Hex Number Code Bytes Mnemonic Mnemonic Operands data addr code addr A GRO A R1 RO code addr R1 code addr R2 code addr R3 code addr R4 code addr R5 code addr R6 code addr R7 code addr A DPTR code addr A RO A R1 A A data addr data addr A eRO A GR1 A R2 A R3 A R4 A R5 A R6 A R7 A 1 1 1 1 1 1 1 1 2 1 2 1 2 1 1 1 1 1 3 1 1 1 1 2 2 1 2 1 2 1 2 2 2 1 2 1 2 1 2 1 1 1 2 1 1 1 1 1 1 1 2 1 2 27 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET INSTRUCTION DEFINITIONS ACALL addr11 Function Absolute Call Description ACALL unconditionally calls a subroutine located at the indicated address The instruction increments the PC twice to obtain the address of the following instruction then pushes the 16 bit result onto the stack low order byte first and increments the Stack Pointer twice The
35. execution to the instruction following the CALL RETI is used to return from an interrupt service rou tine The only difference between RET and RETI is that tells the interrupt control system that the interrupt in progress is done there is no interrupt in progress at the time RETI is executed then the RETI is functionally identical to RET Table 9 shows the list of conditional jumps available to the MCS 51 user All of these jumps specify the desti nation address by the relative offset method and so are limited to a jump distance of 128 to 127 bytes from the instruction following the conditional jump instruc tion Important to note however the user specifies to the assembler the actual destination address the same way as the other jumps as a label or a 16 bit constant intel MCS 51 ARCHITECTURAL OVERVIEW Table 9 Conditional Jumps in MCS 51 Devices Addressing Modes Execution Se JZ rel Jump if A 0 Accumulator only sss JNZ rel Accumulator only 2 DJNZ byte rel Decrement andjumpitnotzero x x 2 CINE A bye e JumpifA bye x x 2 CINE lt byte gt datarel bye daa x x 2 There is no Zero bit in the PSW JZ and JNZ instructions test the Accumulator data for that condi tion e MCS 51 HMOS OR CHMOS The DJNZ instruction Decrement and Jump if Not QUARTZ CRYSTAL Zero is for loop
36. instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The other way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still run ning the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset The signal at the RST pin clears the IDL bit directly and asynchronously At this time the CPU resumes program execution from where it left off that is at the instruction following the one that invoked the Idle Mode As shown in Figure 25 two or three machine cycles of program execution may take place before the internal reset algorithm takes control On chip hard ware inhibits access to the internal RAM during this time but access to the port pins is not inhibited To eliminate the possibility of unexpected outputs at the port pins the instruction following the one that invokes Idle should not be one that writes to a port pin or to externa Data RAM POWER DOWN MODE An instruction that sets PCON 1 causes that to be the last instruction executed before going into the Power Down mode In the Power Down mode the on chip oscillator is stopped With the clock frozen all func intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Tabie 4 EPROM Versions of the 8051 and 8052 Device EPROM EPROM Time Required to Name Version Bytes Pr
37. interrupt and the bit will have to be cleared in software In the 8052 the Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2 Neither of these flags is cleared by hardware when the service routine is vec tored to In fact the service routine may have to deter mine whether it was TF2 or EXF2 that generated the interrupt and the bit will have to be cleared in soft ware All of the bits that generate interrupts can be set or cleared by software with the same result as though it had been set or cleared by hardware That is interrupts can be generated or pending interrupts can be canceled in software MSB LSB es ers exi exo Enable Bit 1 enables the interrupt Enable Bit 0 disables it Symbol Position EA 1E 7 Function disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 reserved IE 5 Timer 2 interrupt enable bit IE 4 Serial Port interrupt enable bit IE 3 Timer 1 interrupt enable bit IE 2 External interrupt 1 enable bit Timer 0 interrupt enable bit 0 External interrupt 0 enable bit User software should never write 1s to unimplemented bits since they may be used in future MCS 51 products Figure 22 IE Interrupt Enable Register intel Each of these interrupt sources can be individually en abled or dis
38. not O the receive circuits are reset and the unit goes back to look ing for another 1 to 0 transition This is to provide re jection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed As data bits come in from the right 1s shift out to the left When the start bit arrives at the leftmost position in the shift register which in mode 1 is a 9 bit regis ter it flags the RX Control block to do one last shift load SBUF and and set RI The signal to load SBUF and RBS and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated 1 0 and 2 Either SM2 0 or the received stop bit 1 either of these two conditions is not met the received frame is irretrievably lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated At this time whether the above conditions are met or not the unit goes back to looking for 1 10 0 transition in RXD More About Modes 2 and 3 Eleven bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On trans 3 20 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 mit the 9th data bit TB8 can be assigned the value of 0 or 1 On receive the 9th data bit goes into RB8
39. output higher order address bits These pins would be controlled by an output instruction preceding the MOVX In the second type of MOVX instruction the Data Pointer generates a sixteen bit address P2 outputs the high order eight address bits the contents of DPH while P0 multiplexes the low order eight bits DPL with data The P2 Special Function Register retains its previous con tents while the P2 output buffers are emitting the contents of DPH This form is faster and more efficient when accessing very large data arrays up to 64K bytes since no additional instructions are needed to set up the output ports It is possible in some situations to mix the two MOVX types large RAM array with its high order address lines driven by P2 can be addressed via the Data Pointer or with code to output high order address bits to P2 followed by a instruction using or An external 256 byte RAM using multiplexed address data lines e g an Intel 8155 RAM I O Timer is connected to the 8051 Port 0 Port 3 provides control lines for the external RAM Ports 1 and 2 are used for normal I O Registers O and 1 contain 12H and 34H Location 34H of the external RAM holds the value 56H The instruction sequence MOVX A GRI MOVX copies the value 56H into both the Accumulator and external RAM location 12H 2 58 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOVX A GRi Bytes 1 2 Encoding 1110 00
40. so being able to increment it in one 16 bit operation is a useful feature The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16 bit product into the concatenated B and Accumulator registers 1 10 MCS 51 ARCHITECTURAL OVERVIEW Table 2 List of the MCS 51 Arithmetic Instructions operation Execution ma mm Tei 40 ases X X ak ss wes lt ve gt X x x L Nc DPR Data Poimerony 2 DEG A oec eves me we i xlxlxl DV AB A Int A B 4 Decimal Adis The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8 bit quotient in the Accumulator and the 8 bit remainder in the B register Oddly enough DIV AB finds less use in arithmetic divide routines than in radix conversions and grammable shift operations An example of the use of DIV AB in a radix conversion will be given later In shift operations dividing a number by 2 shifts its n completes the shift in 4 us and leaves the B register holding the bits that were shifted out The DA A instruction is for BCD arithmetic opera tions In BCD arithmetic ADD and ADDC instruc tions should always be followed by a DA A operation to ensure that the result is also in BCD Note that DA A will not convert a binary number to BCD
41. the feedback ele ment is a quartz crystal and C1 C2 47 pF whena ceramic resonator is used To drive the CHMOS parts with an external clock source apply the external clock signal to XTAL1 and leave XTAL2 float as shown in Figure 35 270252 26 Figure 33 On Chip Oscillator Circuitry in the CHMOS Versions of the MCS 51 Family intel 270252 28 Figure 35 Driving the CHMOS MCS 51 Parts with an External Clock Source The reason for this change from the way the HMOS part is driven can be seen by comparing Figures 29 and 33 In the HMOS devices the internal timing circuits are driven by the signal at XTAL2 In the CHMOS devices the internal timing circuits are driven by the signal at XTAL 1 3 33 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 27 INTERNAL TIMING Figures 36 through 39 show when the various strobe and port signals are clocked internally The figures do not show rise and fall times of the signals nor do they show propagation delays between the XTAL signal and events at other pins Rise and fall times are dependent on the external load ing that each pin must drive They are often taken to be something in the neighborhood of 10 nsec measured between 0 8V and 2 0V Propagation delays are different for different pins For a given pin they vary with pin loading temperature VCC and manufacturing lot If the XTAL waveform is taken as the timing reference prop delays may vary fr
42. to 7EH and internal RAM locations and set to OFFH and 3FH DEC A Bytes 1 Cycles 1 Operation DEC 1 DEC Rn Bytes 1 Cycles 1 Operation DEC Rn lt Rn 1 2 41 intel DEC direct Bytes Cycles Encoding Operation DEC Bytes Cycles Encoding Operation DIV AB Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET to DEC direct direct 1 1 1 DEC RD 1 Divide DIV AB divides the unsigned eight bit integer in the Accumulator by the unsigned eight bit integer in register B The Accumulator receives the integer part of the quotient register B receives the integer remainder The carry and OV flags will be cleared Exception if B had originally contained OOH the values returned in the Accumulator and B register will be undefined and the overflow flag will be set The carry flag is cleared in any case The Accumulator contains 251 OFBH or 11111011B and B contains 18 12H or 00010010B The instruction DIV AB will leave 13 in the Accumulator or 00001101B and the value 17 11H 00010001B in B since 251 13 X 18 17 Carry and OV will both be cleared 1 4 reso 199 DIV 15 Bro A 2 42 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DJNZ lt byte gt lt rel addr gt Function De
43. until INTO is pulsed from low to high to low Then it will execute RETI go back to the task program execute one instruction and immediately re enter the External Interrupt O rou tine to await the next pulsing of P3 2 One step of the task program is executed each time P3 2 is pulsed 12 OSC PERIODS 55 56 51 52 3 54 55 56 51 52 53 54 55 56 51 52 3 4 _ Cy INTERNAL RESET SIGNAL SAMPLE RST SAMPLE RST RESET The reset input is the RST pin which is the input to a Schmitt Trigger reset is accomplished by holding the RST pin high for at least two machine cycles 24 oscillator periods while the oscillator is running The CPU responds by generating an internal reset with the timing shown in Figure 25 The external reset signal is asynchronous to the internal clock The RST pin is sampled during State 5 Phase 2 of every machine cycle The port pins will maintain their current activities for 19 oscillator periods after a logic 1 has been sampled at the RST pin that is for 19 to 31 oscillator periods after the external reset signal has been applied to the RST pin While the RST pin is high ALE and PSEN are weakly pulled high After RST is pulled low it will take 1 to 2 machine cycles for ALE and PSEN to start clocking For this reason other devices can not be synchronized to the internal timings of the 8051 Driving the ALE and PSEN pins to O while reset
44. ware as processor vectors to the service routine TRO 4 Timer 0 run control bit Set cleared by software to turn Timer Counter 0 ON OFF IEI TCON 3 External Interrupt 1 edge flag Set by hardware when External Interrupt edge is detected Cleared by hardware when interrupt is processed IT1 TCON 2 Interrupt 1 type control bit Set cleared by software to specify falling edge low level triggered External Interrupt IEO TCON 1 External Interrupt 0 edge flag Set by hardware when External Interrupt edge detected Cleared by hardware when interrupt is processed ITO TCON 0 Interrupt 0 type control bit Set cleared by software to specify failing edge low level triggered External Interrupt TMOD TIMER COUNTER MODE CONTROL REGISTER NOT BIT ADDRESSABLE m Mo m Wo CIS FD NEC A l te is TIMER 1 TIMER 0 When TRx in TCON is set and GATE 1 TIMER COUNTERx will run only while INTx pin is high hardware control When GATE 0 TIMER COUNTERx will run only while TRx 1 software control C T Timer or Counter selector Cleared for Timer operation input from internal system clock Set for Coun ter operation input from Tx input pin M1 Mode selector bit NOTE 1 MO Mode selector bit NOTE 1 NOTE 1 Operating Mode 0 13 bit Timer MCS 48 compatibie 16 bit Timer Counter 1 2 8 bit Auto Reload Timer Counter 3 Timer O TLO is an 8 bit Timer Counter controlled by t
45. 0 enable the working register banks as follows 0 0 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 00H 07H 08H OFH 10H 17H 18H 1FH Figure 3 PSW Program Status Word Register ADDR DATA CONTROL ce READ LATCH INT BUS 270252 2 A Port 0 Bit READ LATCH 270252 4 C Port 2 Bit INTERNAL 270252 3 Port 1 Bit ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL PULL UP ALTERNATE INPUT FUNCTION 270252 5 D Port 3 Bit Figure 4 8051 Port Bit Latches and 1 0 Buffers See Figure 5 for details of the internal pullup PORT STRUCTURES AND OPERATION All four ports in the 8051 are bidirectional Each con sists of a latch Special Function Registers PO through P3 an output driver and an input buffer The output drivers of Ports 0 and 2 and the input buff ers of Port 0 are used in accesses to external memory In this application Port O outputs the low byte of the 3 6 external memory address time multiplexed with the byte being written or read Port 2 outputs the high byte of the externa memory address when the address is 16 bits wide Otherwise the Port 2 pins continue to emit the P2 SFR content All the Port 3 pins and in the 8052 two Port 1 pins are multifunctional They are not only port pins but also serve the functions of various special features as listed on the following page intel HARDWARE DESCRIPTION OF THE 8051
46. 0 the CPL C instruction is jumped over JBC executes the jump if the addressed bit is set and also clears the bit Thus a flag can be tested and cleared in one operation the PSW bits are directly addressable so the Parity bit or the general purpose flags for example are also available to the bit test instructions RELATIVE OFFSET The destination address for these jumps is specified to the assembler by a label or by an actual address in Program Memory However the destination address assembles to a relative offset byte This is a signed two s complement offset byte which is added to the PC in two s complement arithmetic if the jump is exe cuted The range of the jump is therefore 128 to 127 Pro gram Memory bytes relative to the first byte following the instruction MCS 51 ARCHITECTURAL OVERVIEW Jump Instructions Table 8 shows the list of unconditional jumps Table 8 Unconditional Jumps in MCS 51 Devices add JMP A DPTR Jump to A DPTR CALL addr Call subroutine ataddr 2 RET Rewntomssrwwne 2 Noe Nooperation 1 The Table lists a single JMP addr instruction but in fact there are three SJMP LJMP and AJMP which differ in the format of the destination address JMP is generic mnemonic which can be used if the program mer does not care which way the jump is encoded The SJMP instruction encodes the destination address as a relative of
47. 051 have additional SFRs that are not present in the 8051 nor perhaps in other proliferations of the family REGISTER MAPPED PORTS ADDRESSES THAT END IN OH OR 8H ARE ALSO BIT ADDRESSABLE PORT PINS ACCUMULATOR 5 270251 9 Figure 9 SFR Space Sixteen addresses in SFR space are both byte and bit addressable The bit addressable SFRs are those whose address ends in 0008 The bit addresses in this area 80H through FFH THE MCS 51 INSTRUCTION SET All members of the MCS 51 family execute the same instruction set The MCS 51 instruction set is opti mized for 8 bit control applications It provides a vari ety of fast addressing modes for accessing the internal RAM to facilitate byte operations on small data struc tures The instruction set provides extensive support for one bit variables as a separate data type allowing direct bit manipulation in control and logic systems that re quire Boolean processing An overview of the MCS 51 instruction set is presented below with a brief description of how certain instruc tions might be used References to the assembler in this discussion are to Intel s MCS 51 Macro Assembler ASMS1 More detailed information on the instruction set can be found in the MCS 5 Macro Assembler Us er s Guide Order No 9800937 for ISIS Systems Order No 122752 for DOS Systems Program Status Word The Program Status Word PSW contains several Status bits that r
48. 052 AND 80C51 ADDITIONAL REFERENCES The following application notes and articles found in the Embedded Applications handbook Order Number 270648 1 AP 125 Designing Microcontroller Systems for Electrically Noisy Environments 2 AP 155 Oscillators for Microcontrollers 3 AP 252 Designing with the 80C51BH 4 AR 517 Using the 8051 Microcontroller with Resonant Transducers
49. 1 Memory Structure CHMOS Devices Functionally the CHMOS devices designated with in the middle of the device name are all fully compatible with the 8051 but being CMOS draw less current than an HMOS counterpart To further exploit the power savings available in CMOS circuitry two re duced power modes are added Software invoked Idle Mode during which the CPU is turned off while the RAM and other on chip peripherals continue operating In this mode cur rent draw is reduced to about 15 of the current drawn when the device is fully active Software invoked Power Down Mode during which all on chip activities are suspended The on chip RAM continues to hold its data In this mode the device typically draws less than 10 pA Although the 80C51BH is functionally compatible with its HMOS counterpart specific differences between the two types of devices must be considered in the design of an application circuit if one wishes to ensure complete interchangeability between the HMOS and CHMOS devices These considerations are discussed in the Ap plication Note 252 Designing with the 80C51BH For more information on the individual devices and features listed in Table 1 refer to the Hardware De scriptions and Data Sheets of the specific device MEMORY ORGANIZATION IN MCS 51 DEVICES Logical Separation of Program and Data Memory All MCS 51 devices have separate address spaces for Program and Data Me
50. 1i Operation gt 1 8 A DPTR Bytes Cycles Encoding 1110 0000 Operation MOVX 3 gt 1 8 MOVX Bytes Encoding 1111 Operation B RD lt A MOVX DPTR A Bytes 1 Cycles 2 Encoding Operation DPTR lt 2 59 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MUL Function Multiply Description MUL AB multiplies the unsigned eight bit integers in the Accumulator and register B The low order byte of the sixteen bit product is left in the Accumulator and the high order byte in If the product is greater than 255 the overflow flag is set otherwise it is cleared The carry flag is always cleared Example Originally the Accumulator holds the value 80 50H Register B holds the value 160 OAOH The instruction MUL AB will give the product 12 800 3200H so B is changed to 32H 00110010B and the Accumula tor is cleared The overflow flag is set carry is cleared Bytes 1 Cycles 4 Operation MUL A 7 o lt A X 8 15 8 Function Operation Description Execution continues at the following instruction Other than the PC no registers or flags are affected Example It is desired to produce a low going output pulse on bit 7 of Port 2 lasting exactly 5 cycles simple SETB CLR sequence would generate a one cycle pulse so four additional cycles must be inserted
51. 2 is set 1 0 0 transition T2EX will set EXF2 but will not cause a reload from RCAP2H RCAP2L to TH2 TL2 Thus when Timer 2 is in use as a baud rate generator T2EX can be used as an extra external interrupt if desired It should be noted that when Timer 2 is running TR2 1 timer function in the baud rate generator mode one should not try to read or write TH2 or TL2 Under these conditions the Timer is being incremented every state time and the results of a read or write may not be accurate The RCAP registers may be read but shouldn t be written to because a write might overlap a reload and cause write and or reload errors Turn the Timer off clear TR2 before accessing the Timer 2 or RCAP registers in this case More About Mode 0 Serial data enters and exits through RXD TXD out puts the shift clock 8 bits are transmitted received 8 data bits LSB first The baud rate is fixed at the oscillator frequency Figure 17 shows a simplified functional diagram of the serial port in Mode 0 and associated timing 3 17 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal at S6P2 also loads 1 into the 9th position of the transmit shift register and tells the TX Control block to commence a transmission The internal timing is such that one full machine cycle will elapse between write to SB
52. 3 Two 8 Bit Counters Timer 2 Table 2 Timer 2 Operating Modes s Made 16 bit Auto Reload 16 bit Capture Baud Rate Generator off Timer 2 is a 16 bit Timer Counter which is present only in the 8052 Like Timers 0 and 1 it can operate either as a timer or as an event counter This is selected by bit C T2 in the Special Function Register 2 Figure 11 It has three operating modes capture auto load and baud rate generator which se lected by bits in 2 as shown in Table 2 3 12 intel MSB HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 LSB Tre amp x2 exene me Symbol TF2 Position T2CON 7 Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software TF2 will not be set when either RCLK 1 or TCLK 1 EXF2 T2CON 6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on 2 and 2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Receive clock flag When set causes the serial port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3 RCLK 0 causes Timer 1 overflow to be used for the receive clock Transmit clock flag When set causes the serial port to use Timer 2 overflow pulses for its transm
53. 4 oscillator periods to recognize a 1 to O transition the maximum count rate is 1 2 of the oscillator fre quency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle In addition to the Timer or Counter selection Timer 0 and Timer 1 have four operating modes from which to select Timer 2 in the 8052 has three modes of operation Capture Auto Reload and baud rate generator Timer 0 and Timer 1 These Timer Counters are present in both the 8051 and the 8052 The Timer or Counter function is select ed by control bits C T in the Special Function Register TMOD Figure 6 These two Timer Counters have MSB cate w four operating modes which are selected by bit pairs M1 MO in TMOD Modes 0 1 and 2 are the same for both Timer Counters Mode 3 is different The four operating modes are described in the following text MODE 0 Either Timer in Mode 0 is an 8 bit Counter with a divide by 32 prescaler This 13 bit timer is MCS 48 compatible Figure 7 shows the Mode 0 operation as it applies to Timer 1 In this mode the Timer register is configured as a 13 Bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TF1 The counted input is enabled to the Timer whe
54. 8 PC lt addris o LJMP addr16 Function Long Jump Description LJMP causes an unconditional branch to the indicated address by loading the high order and low order bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the full 64K program memory address space No flags are affected Example label is assigned to the instruction at program memory location 1234H The instruction LJMP JMPADR at location 0123H will load the program counter with 1234H Bytes 3 Cycles 2 Encoding 0000 0010 addri5 addre addr7 addro Operation LIMP PC lt 5 2 51 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET MOV lt dest byte gt lt src byte gt Function Description Example MOV Bytes Cycles Encoding Operation MOV A direct Bytes Cycles Encoding Operation Move byte variable The byte variable indicated by the second operand is copied into the location specified by the first operand The source byte is not affected No other register or flag is affected This is by far the most flexible operation Fifteen combinations of source and destination addressing modes are allowed Internal RAM location 30H holds 40H The value of RAM location 40H is 10H The data present at input port 1 is 11001010B MOV MOV MOV MOV MOV MOV R0 430H 0 lt A GRO A
55. 8052 80C51 Port Pin Alternate Function 1 0 2 Timer Counter 2 external input P1 1 T2EX Timer Counter 2 Capture Reload trigger P3 0 RXD serial input port P3 1 TXD serial output port P3 2 INTO external interrupt P3 3 INT1 external interrupt P3 4 TO Timer Counter 0 external input P3 5 T1 Timer Counter 1 external input P3 6 WR external Data Memory write strobe P3 7 RD externa Data Memory read strobe P1 0 and P1 1 serve these alternate functions only on the 8052 The alternate functions can only be activated if the cor responding bit latch in the port SFR contains a 1 Oth erwise the port pin is stuck at 0 I O Configurations Figure 4 shows a functional diagram of a typical bit latch and 1 O buffer in each of the four ports The bit latch one bit in the port s SFR is represented as a Type D flip flop which will clock in a value from the internal bus in response to a write to latch signal from the CPU The Q output of the flip flop is placed on the internal bus in response to a read latch signal from the CPU The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU Some instructions that read a port acti vate the read latch signal and others activate the read pin signal More about that later As shown in Figure 4 the output drivers of Ports 0 and 2 are switchable to an interna ADDR and ADDR DATA bus by an internal CONT
56. ACC 7 1 OV 0 MOV 1 0 LOAD CARRY WITH INPUT PIN 10 ORL 7 CARRY WITH THE ACC 7 ORL CARRY WITH THE INVERSE OF 2 2 0111 0010 ORL C C V bit 2 2 ORL v bit 2 63 intel 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET POP direct Function Pop from stack Description contents of the internal RAM location addressed by the Stack Pointer is read and the Stack Pointer is decremented by one The value read is then transferred to the directly ad dressed byte indicated No flags are affected Example Stack Pointer originally contains the value 32H and internal RAM locations through 32H contain the values 20H 23H and 01H respectively The instruction sequence POP DPH POP DPL will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H At this point the instruction POP SP will leave the Stack Pointer set to 20H Note that in this special case the Stack Pointer was decremented to 2FH before being loaded with the value popped 20H Bytes 2 Cycles 2 Encoding 0000 Operation POP direct lt 5 SP SP 1 PUSH direct Function Push onto stack Description Stack Pointer is incremented by one The contents of the indicated variable is then copied into the internal RAM location addressed by the Stack Pointer Otherwise no flags are af
57. ALU OPERANDS PSW 6 AUXILIARY CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERANDS 5 GENERAL PURPOSE STATUS FLAG PSW 4 REGISTER BANK SELECT BIT 1 MCS 51 ARCHITECTURAL OVERVIEW PSW 0 PARITY OF ACCUMULATOR SET BY HARDWARE TO 1 IF IT CONTAINS ODO NUMBER OF 15 OTHERWISE IT tS RESET TO 0 PSW 1 USER DEFINABLE FLAG PSW 2 OVERFLOW FLAG SET BY ARITHMETIC OPERATIONS PSW 5 REGISTER BANK SELECT BIT O 270251 10 Figure 10 PSW Program Status Word Register MCS 51 Devices The next 16 bytes above the register banks form a block of bit addressable memory space The MCS 51 instruc tion set includes a wide selection of single bit instruc tions and the 128 bits in this area can be directly ad dressed by these instructions The bit addresses in this area are 00H through 7FH All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing The Upper 128 Figure 8 can only be accessed by indirect addressing The Upper 128 bytes of RAM are not implemented in the 8051 but are in the devices with 256 bytes of RAM See Table 1 Figure 9 gives a brief look at the Special Function Reg ister SFR space SFRs include the Port latches tim ers peripheral controls etc These registers can only be accessed by direct addressing In general all MCS 51 microcontrollers have the same SFRs as the 8051 and at the same addresses in SFR space However enhance ments to the 8
58. Accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the internal RAM location indirectly addressed by the specified register The high order nibbles bits 7 4 of each register are not affected No flags are affi Example contains the address 20H The Accumulator holds the value 36H 00110110B Internal RAM location 20H holds the value 75H 01110101B The instruction XCHD A RO will leave RAM location 20H holding the value 76H 01110110B and 35H 00110101B in the Accumulator Bytes 1 Cycles 1 Operation XCHD Ris o XRL lt dest byte gt lt src byte gt Function Logical Exclusive OR for byte variables Description XRL performs the bitwise logical Exclusive OR operation between the indicated variables storing the results in the destination No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Example If the Accumulator holds 11000011B and register 0 holds OAAH 10101010B then the instruction XRL A RO will leave the Accumulator holding the valu
59. C152 Hardware Description 5 51 Family of 1 Microcontrollers Architectural Overview MCS 51 FAMILY OF CONTENTS PAGE MICROCONTROLLERS ARCHITECTURAL OVERVIEW 1 1 intel MCS 51 ARCHITECTURAL OVERVIEW INTRODUCTION The 8051 is the original member of the MCS 51 family and is the core for all MCS 51 devices The features of the 8051 core are e 8 bit CPU optimized for control applications Extensive Boolean processing single bit logic capabilities 64K Program Memory address space 64K Data Memory address space 4K bytes of on chip Program Memory 128 bytes of on chip Data RAM 32 bidirectional and individually addressable I O lines Two 16 bit timer counters Full duplex UART 6 source 5 vector interrupt structure with two priority levels On chip clock oscillator The basic architectural structure of this 8051 core is shown in Figure 1 EXTERNAL INTERRUPTS INTERRUPT 128 BYTES ae CONTROL RAM y PORT BUS I SERIAL CONTROL E 41 0 PORTS P2 ADDRESS P1 P3 270251 1 Figure 1 Block Diagram of the 8051 Core MCS 51 ARCHITECTURAL OVERVIEW 9 952 410 85728 02921 25 85108 029121 410 9 ____ 7918 WOH 72108 e 0 952 WOHdlO 8 29128 L 2 ee 029121 92 408 e mouse o
60. CRIPTION OF THE 8051 8052 80 51 270252 12 Figure 12 Timer 2 in Capture Mode The serial port can operate in 4 modes Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted re ceived 8 data bits LSB first The baud rate is fixed at 1 12 the oscillator frequency Mode 1 10 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB8 in Special Function Register SCON The baud rate is variable Mode 2 11 bits are transmitted through TXD or re ceived through RXD a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 On Transmit the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 On re ceive the 9th data bit goes into RB8 in Special Functon Register SCON while the stop bit is ignored The baud rate is programmable to either or the oscillator frequency Mode 3 11 bits are transmitted through TXD or re ceived through a start bit 0 8 data bits LSB first a programmable 9th data bit and a stop bit 1 In fact Mode 3 is the same as Mode 2 all respects except the baud rate The baud rate in Mode 3 is vari able In all four modes transmission is initiated by any in struction that uses SBUF as a destina
61. D DATA TXD SHIFT CLOCK 3 1 S6P1 WRITE SCON CLEAR RI Bohn te i C J pacai e SHIFT n n n f n RECEIVE RXD DATA nnn 020 001 002 93 poe gt _ TXD SHIFT CLOCK Figure 17 Serial Port Mode 0 270252 15 3 18 intel TIMER 1 OVERFLOW TIMER 2 OVERFLOW START TXCLOCK RXCLOCK RI RX CONTROL START DETECTOR TX WRITE TO SBUF HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8051 INTERNAL BUS EE I ZERO DETECTOR SHIFT pata TX CONTROL SEND LOAD SBUF SHIFT 1FFH I 8051 INTERNAL BUS SEND DATA 1 1 TRANSMIT SHIFT 1 1 1 wwo X X I 02 X 01 D X Ds pa sroPBT _ 2 0 et NE STARTBIT 316 RESET STOP BIT RECEIVE SHIFT 270252 16 Figure 18 Serial Port Mode 1 TCLK RCLK and Timer 2 are Present in the 8052 8032 Only Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit 3 19 times are synchronized to the divide by 16 counter not to the
62. Data Memory is mapped in Figure 6 The memory space is shown divided into three blocks which are generally referred to as the Lower 128 the Upper 128 and SFR space Internal Data Memory addresses are always one byte wide which implies an address space of only 256 bytes However the addressing modes for internal RAM can in fact accommodate 384 bytes using a simple trick Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space Thus Figure 6 shows the Up per 128 and SFR space occupying the same block of addresses through FFH although they are physi cally separate entities BIT ADDRESSABLE SPACE BIT ADDRESSES 0 7F RO R RESET VALUE OF STACK POINTER 270251 7 Figure 7 The Lower 128 Bytes of Internal RAM The Lower 128 bytes of RAM are present in all MCS 51 devices as mapped in Figure 7 The lowest 32 bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as RO through R7 Two bits in the Program Status Word PSW select which register bank is in use This allows more efficient use of code space since register instructions are shorter than instructions that use direct addressing NO BIT ADDRESSABLE SPACES AVAILABLE AS STACK SPACE IN DEVICES WITH 256 BYTES RAM NOT IMPLEMENTED IN 8051 270251 8 Figure 8 The Upper 128 Bytes of Internal RAM PSW 7 CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF
63. EGISTER INTERRUPT INTERRUPT POLLING SEQUENCE LOW PRIORITY INTERRUPT 270251 17 Figure 19 8051 Interrupt Control System In operation all the interrupt flags are latched into the interrupt control system during State 5 of every ma chine cycle The samples are polled during the follow ing machine cycle If the flag for an enabled interrupt is found to be set 1 the interrupt system generates an LCALL to the appropriate location in Program Memo ry unless some other condition blocks the interrupt Several conditions can block an interrupt among them that an interrupt of equal or higher priority level is already in progress The hardware generated LCALL causes the contents of the Program Counter to be pushed onto the stack and reloads the PC with the beginning address of the service routine As previously noted Figure 3 the service rou tine for each interrupt begins at a fixed location Only the Program Counter is automatically pushed onto the stack not the PSW or any other register Hav ing only the PC be automatically saved allows the pro grammer to decide how much time to spend saving which other registers This enhances the interrupt re sponse time albeit at the expense of increasing the pro grammer s burden of responsibility As a result many interrupt functions that are typical in control applica tions toggling a port pin for example or reloading a timer or unloading a serial buffer can often be com
64. INSTRUCTION SET Table 10 8051 Instruction Set Summary Oscillator Int t R Time Refer to Hard De nterrupt Response Time er to Period scription Chapter Instructions that Affect Flag Settings 1 Instruction Instruction Flag Mnemonic Description Byte ARITHMETIC OPERATIONS ADD A Rn Add register to Accumulator ADD A direct Add direct byte to Accumulator ADD A Ri Add indirect RAM to Accumulator ADD A data Addimmediate data to Accumulator ADDC A Rn Add register to Accumulator with Carry ADDC A direct Add direct byte to Accumulator with Carry ADDC A Ri Add indirect RAM to Accumulator with Carry A data Add immediate data to Acc with Carry A Rn Subtract Register from Acc with borrow A direct Subtract direct byte from Acc with borrow A GRi Subtract indirect RAM from ACC with borrow A data Subtract immediate data from Acc with borrow Increment Accumulator increment register increment direct byte increment direct RAM Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM All mnemonics copyrighted Intel Corporation 1980 2 gt X ANL C bit ANL C bit ORL ORL C bit MOV C bit x x x O O x x x O x x x x x x gt x O SETBC D Note that operations on SFR byte address 208 or bit addresses 209 215 the PSW or bits in the PSW will also affect flag settings Note on instruction set and addressing modes Rn Re
65. JC REQ LOW R7 sets the carry flag and branches to the instruction at label NOT By testing the carry flag this instruction determines whether R7 is greater or less than 60H If the data being presented to Port 1 is also 34H then the instruction WAIT A P1 WAIT clears the carry flag and continues with the next instruction in sequence since the Accumula tor does equal the data read from P1 If some other value was being input on P1 the program will loop at this point until the P1 data changes to 34H 3 2 10110101 PC PO 3 IF A lt gt direct THEN PC PC relative offset IF A lt direct 2 35 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CJNE A data rei Bytes 3 Cycles 2 Encoding 1011 immediate data Operation PO PO 3 IF A lt gt data THEN relative offset IF A lt data THEN lt 1 ELSE C 0 CJNE Rn data rel Bytes 3 Cycles 2 Encoding 1011 1 immediate data Operation PC 3 IF Rn lt gt data THEN PC PC relative offset IF Rn data THEN 1 C 0 ELSE CJNE Ri data rel Bytes 3 Cycles 2 Encoding 10110111 immediate data Operation 3 IF Ri lt gt data THEN relative offset IF Ri lt data THEN 1 C 0 ELSE 2 36 intel CLR A
66. JNZ and one to alter the pin DJNZ Rn rel Bytes 2 Cycles 2 Encoding 1105 Operation DJNZ PC PO 2 Rn 1 IF Rn gt Oor Rn lt 0 THEN lt rel intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DJNZ direct re Bytes 3 Cycles 2 Encoding direct address Operation DJNZ PC PC 2 direct lt direct 1 IF direct gt 0 or direct lt 0 THEN PC PO rel INC lt byte gt Function Increment Description INC increments the indicated variable by 1 An original value of 0FFH will overflow to 00H No flags are affected Three addressing modes are allowed register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch the input pins Example Register 0 contains 7EH 011111110B Internal RAM locations and 7FH contain OFFH and 40H respectively The instruction sequence INC GRO INC RO INC GRO will leave register O set to 7FH and internal RAM locations 7EH and 7FH holding respective ly and 41H INC A Bytes 1 Cycles Encoding Operation INC A A 1 2 44 intel INC INC INC Rn Bytes Cycles Encoding Operation direct Bytes Cycles Encoding Operation Ri Bytes Cycles Encoding Operation INC DPTR Function Description
67. LABEL2 Bytes 3 Cycles 2 Encoding 0010 0000 Operation JB 3 IF bit 1 THEN PO PO rel JBC bit rel Function Jump if Bit is set and Clear bit Description If the indicated bit is one branch to the address indicated otherwise proceed with the next instruction The bit will not be cleared if it is already a zero The branch destination is comput ed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction No flags are affected Note When this instruction is used to test an output pin the value used as the original data will be read from the output data latch not the input pin Example The Accumulator holds 56H 01010110B The instruction sequence JBC ACC 3 LABEL1 JBC ACC 2 LABEL2 will cause program execution to continue at the instruction identified by the label LABEL2 with the Accumulator modified to 52H 010100108 intel Bytes Encoding Operation JC rel Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 3 2 0000 JBC PO PO 3 IF bit 1 THEN bit 0 PO rel Jump if Carry is set If the carry flag is set branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by addin
68. ROL signal for use in external memory accesses During external memory ac cesses the P2 SFR remains unchanged but the PO SFR gets 1s written to it Also shown in Figure 4 is that if a P3 bit latch contains a 1 then the output level is controlled by the signal labeled alternate output function The actual P3 X pin level is always available to the pin s alternate input function if any Ports 1 2 and 3 have internal pullups Port 0 has open drain outputs Each I O line can be independently used as an input or an output Ports 0 and 2 may not be used as general purpose I O when being used as the ADDR DATA BUS To be used as an input the port bit latch must contain a 1 which turns off the output driver FET Then for Ports 1 2 and 3 the pin is pulled high by the internal pullup but can be pulled low by an external source Port 0 differs in not having internal pullups The pullup FET in the PO output driver see Figure 4 is used only when the Port is emitting 1s during external memory accesses Otherwise the pullup FET is off Consequent ly PO lines that are being used as output port lines are open drain Writing a 1 to the bit latch leaves both output FETs off so the pin floats In that condition it can be used a high impedance input Because Ports 1 2 and 3 have fixed internal pullups they are sometimes called quasi bidirectional ports When configured as inputs they pull high and will source current IIL in the dat
69. TABLES Table 6 shows the two instructions that are available for reading lookup tables in Program Memory Since these instructions access only Program Memory the lookup tables can only be read not updated The mne monic is MOVC for move constant If the table access is to external Program Memory then the read strobe is PSEN Tabie 6 The 5 51 Lookup Table Read Instructions MOVC A A DPTR Read Memory at A DPTR A A PC Read Pgm Memory at A PC The first MOVC instruction in Table 6 can accommo date a table of up to 256 entries numbered 0 through 255 The number of the desired entry is loaded into the Accumulator and the Data Pointer is set up to point to beginning of the table Then MOVC A DPTR copies the desired table entry into the Accumulator The other MOVC instruction works the same way ex cept the Program Counter PC is used as the table base and the table is accessed through a subroutine First the number of the desired entry is loaded into the Accumulator and the subroutine is called MOV CALL __ NUMBER TABLE The subroutine TABLE would look like this TABLE MOVC A A PC RET The table itself immediately follows the RET return instruction in Program Memory This type of table can have up to 255 entries numbered 1 through 255 Num ber 0 can not be used because at the time the MOVC instruction is exec
70. TL1 and TH2 TL2 are the 16 bit Counting registers for Timer Coun ters 0 1 and 2 respectively CAPTURE REGISTERS The register pair RCAP2H RCAP2L the Cap ture registers for the Timer 2 Capture Mode In this mode in response to a transition at the 80525 T2EX 2 and TL2 are copied into RCAP2H and RCAP2L Timer 2 also has 16 bit auto reload mode and RCAP2H and RCAP2L hold the reload value for this mode More about Timer 2 s features in a later section CONTROL REGISTERS Special Function Registers IP IE TMOD TCON T2CON SCON and PCON contain control and status bits for the interrupt system the Timer Counters and the serial port They are described in later sections MSB HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 LSB L cv ac ns ov e Name and Significance Carry flag Auxiliary Carry flag For BCD operations Position PSW 7 PSW 6 Symbol FO PSW 5 Flag 0 Available to the user for general purposes Register bank select control bits 1 amp 0 Set cleared by software to determine working register bank see Note Symbol P Position PSW 2 PSW 1 PSW 0 Name and Significance Overflow User definable flag Parity flag Set cleared by hardware each instruction cycle to indicate an odd even number of bits in the Accumulator i e even parity NOTE The contents of RS1 RS
71. The DA A operation produces a meaningful result only as the second step in the addition of two BCD bytes bits to the right Using DIV AB to perform the division Table 3 List of the MCS 51 Logical Instructions iL Dir ind Reg mm Time as ANL lt byte gt A bte ye ANDA X T ANL bye daa lt byte gt bye AND X 2 be A lt byie gt ORA x T lt byie gt wdata_ lt byte gt bye lt byte gt XAL bye da lt byte gt bye XOR X A Accumulator only CPL A Accumulator only Rotate ACC Left 1 bit Accumulator only RR A Rotate ACC Right 1 bit Accumulator only RRC A Rotate Right through Carry Accumulator only RLC A Rotate Left through Carry Accumulator only Swap Nbolesin A Accumulator only intel Logical Instructions Table 3 shows the list of MCS 51 logical instructions The instructions that perform Boolean operations AND OR Exclusive OR NOT on bytes perform the operation on a bit by bit basis That is if the Accumu lator contains 001101018 and lt byte gt contains 01010011B then ANL lt byte gt will leave the Accumulator holding 00010001B The addressing modes that can be used to access the lt byte gt operand are listed in Table 3 Thus the ANL lt byte gt instructio
72. UF and activation of SEND SEND enables the output of the shift register to the alternate output function line of P3 0 and also enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK is low during S3 54 and S5 of every machine cycle and high during S6 SI and S2 At S6P2 of every machine cycle in which SEND is active the contents of the transmit shift register are shifted to the right one position As data bits shift out to the right zeroes come in from the left When the MSB of the data byte is at the output position of the shift register then the 1 that was initial ly loaded into the 9th position is just to the left of the MSB and all positions to the left of that contain zeroes This condition flags the TX Control block to do one last shift and tben deactivate SEND and set TI Both of these actions occur at S1P1 of the 10th machine cycle after write to SBUF Reception is initiated by the condition REN 1 and R1 0 At S6P2 of the next machine cycle the RX Control unit writes the bits 11111110 to the receive shift register and in the next clock phase activates RE CEIVE RECEIVE enables SHIFT CLOCK to the alternate output function line of P3 1 SHIFT CLOCK makes transitions at S3P1 and S6P1 of every machine cycle At S6P2 of every machine cycle in which RECEIVE is active the contents of the receive shift register are shift ed to the left one position The value that comes in from the righ
73. Z 104 19 3201 1 ah SUG 4907 Auo 19 AALALAY ZHAO 02 ZHN tZ te zu paedg SOI8 1 WOH 89144 WOHd3 WOH d LO WOH 13 1V19819248 91 95 WOW 1971518968 o z 96 92 ISISON8 z 9 92 41 171518008 ol 01 2 WOH39L HV ISISOES o0 e v2 oF 92 WOH HVISISOIB e v 9 9s SS3iWOH HVISISOO8 2 9 Wouws 997519068 9S2 WOH X8 98 7515018 99 1819908 Vf eS gSrestoo8 Vf esro08 t _87 952 MWOUd3 e 8518578 WOH 9915958 SS31WOH 9015008 18 SS31NOH 02912 Z 0 9121 952 ze 9 992 SS31IWOH VAS 108 eur 3onpoud 23 8 4151 8 nouss nee _osisoce Ze 9219968 9319028 8416268 2029 21 WOud3 791 38 Y8 UMOG 19M0d 3201 JO LS SOW UL 1 AALL PROGRAM MEMORY READ ONLY 5 51 ARCHITECTURAL OVERVIEW DATA MEMORY READ WRITE INTERNAL 4 a 4 270251 2 Figure 2 MCS 5
74. a sheets when externally pulled low Port 0 on the other hand is considered true bidirectional because when configured as an in put it floats All the port latches in the 8051 have 1s written to them by the reset function If a 0 is subsequently written to a port latch it can be reconfigured as an input by writing a to it Writing to a Port In the execution of an instruction that changes the val ue in a port latch the new value arrives at the latch during S6P2 of the final cycle of the instruction How ever port latches are in fact sampled by their output buffers only during Phase 1 of any clock period Dur ing Phase 2 the output buffer holds the value it saw during the previous Phase 1 Consequently the new value in the port latch won t actually appear at the output pin until the next Phase 1 which will be at 51 1 of the next machine cycle See Figure 39 in the Internal Timing section If the change requires a 0 to 1 transition in Port 1 2 or 3 an additional pullup is turned on during S1P1 and S1P2 of the cycle in which the transition occurs This is done to increase the transition speed The extra pullup can source about 100 times tbe current that the normal pullup can It should be noted that the internal pullups are field effect transistors not linear resistors The pull up arrangements are shown in Figure 5 In HMOS versions of the 8051 the fixed part of the pullup is a depletion mode transistor with th
75. abled by setting or clearing a bit in Special Function Register Figure 22 IE contains also global disable bit EA which disables all interrupts at once Note in Figure 22 that bit position IE 6 is unimple mented In the 8051s bit position IE 5 is also unimple mented User software should not write 1s to these bit positions since they may be used in future MCS 51 products Priority Level Structure Each interrupt source can also be individually pro grammed to one of two priority levels by setting or clearing a bit in Special Function Register IP Figure 23 A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low pri ority interrupt high priority interrupt can t be inter rupted by any other interrupt source MSB LSB es er Pro exo Priority bit 1 assigns high priority Priority bit 0 assigns low priority Position IP 7 Function reserved reserved IP 6 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 ceived simultaneously an internal polling sequence de termines which request is serviced Thus within each priority level there is a second priority structure deter mined by the polling sequence as follows Source Priority Within Level IEO highest TFO IE1 TF1 RI TF2 EXF2 gt lowest Note that the priority within level structure is only used to resolve simultaneous reque
76. are always 16 bits wide even though the actual amount of Program Memory used may be less than 64K bytes External program execution sacrifices two of the 8 bit ports and P2 to the function of addressing the Program Memory Data Memory The right half of Figure 2 shows the internal and exter nal Data Memory spaces available to the MCS 51 user Figure 5 shows a hardware configuration for accessing up to 2K bytes of external RAM The CPU in this case is executing from internal ROM Port O serves as a multiplexed address data bus to the RAM and 3 lines of Port 2 are being used to page the RAM The CPU generates RD and WR signals as needed during exter nal RAM accesses 270251 5 Figure 5 Accessing External Data Memory If the Program Memory is Internal the Other Bits of P2 are Available as I O There can be up to 64K bytes of externa Data Memo ry External Data Memory addresses can be either 1 or 2 bytes wide One byte addresses are often used in con junction with one or more other I O lines to page the RAM as shown in Figure 5 Two byte addresses can also be used in which case the high address byte is emitted at Port 2 ACCESSIBLE BY DIRECT ADDRESSING ACCESSIBLE UPPER BY INDIRECT ADORESSING N ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING REGISTERS STACK POINTER ACCUMULATOR ETC 270251 6 Figure 6 Internal Data Memory MCS 51 ARCHITECTURAL OVERVIEW Internal
77. as been executed the Accumulator contains the two digits that were shifted out on the right Doing the routine with direct MOVs uses 14 code bytes and 9 ps of execution time assuming a 12 MHz clock The same operation with XCHs uses less code and executes almost twice as fast To right shift by an odd number of digits a one digit shift must be executed Figure 12 shows a sample of code that will right shift a BCD number one digit us ing the XCHD instruction Again the contents of the registers holding the number and of the Accumulator are shown alongside each instruction MOV R1 2EH MOV 2DH loop for R1 2EH LOOP MOV A R1 XCHD A eRO SWAP A MOV R1 A DEC DEC CJNE R1 2AH LOOP loop for R1 2DH loop for R1 2CH loop for R1 2BH 00 00 23 08101123145167 01 CLR o 01 23 5 7 00 A 2AH 00101123145167 08 Figure 12 Shifting a BCD Number One Digit to the Right First pointers R1 and 0 set up to point to the two bytes containing the last four BCD digits Then a loop 15 executed which leaves the last byte location holding the last two digits of the shifted number The pointers are decremented and the loop is repeated for location 2DH The CJNE instruction Compare and Jump if Not Equal is a loop control that will be de scribed later The loop is executed from LOOP to CJNE for R1 2EH 2DH 2CH and 2BH At that point the digit that was or
78. because the address and data bus are being used for the Data Mem Ory access Note that a Data Memory bus cycle takes twice as much time as a Program Memory bus cycle Figure 16 shows the relative timing of the addresses being emitted at Ports 0 and 2 and of ALE and PSEN ALE is used to latch the low address byte from PO into the address latch ONE MACHINE CYCLE ONE MACHINE CYCLE Doc To S ALE PSEN RD 1 j WITHOUT MOVX 1 1 I I 1 P2PCHOUTX PCHOUT PCHOUT PCHOUT X PCHOUT X PCHOUT I I I A 4 pci our VALID VALID pct our VALID VALIO 0 08 gt G5 our CYCLE CYCLE2 552221222 I PSEN l RO I P2PCHOUTX PCHOUT X DPHOUTORP20UT PCHOUT X PCHOUT LLL B WITH A MOVX EET UN UE Lec L ADDR OUT VALID VALID t PCL OUT VALID 270251 16 Figure 16 Bus Cycles in 5 51 Devices Executing from External Program Memory ntel MCS 51 ARCHITECTURAL OVERVIEW When the CPU is executing from internal Program Memory PSEN is not activated and program address es are not emitted However ALE continues to be acti vated twice per machine cycle and so is available as a clock output signal Note however that one ALE is skipped during the execution of the MOVX instruction Interrupt Structure The 8051 core provides 5 interrupt sources
79. because they have an internal pulldown on the RST pin The capacitor value could then be re duced to 1 pF When power is turned on the circuit holds the RST pin high for an amount of time that depends on the capaci tor value and the rate at which it charges To ensure a valid reset the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles On power up Vcc should rise within approximately ten milliseconds The oscillator start up time will de pend on the oscillator frequency For a 10 MHz crystal the start up time is typically 1 ms For a 1 MHz crystal the start up time is typically 10 ms With the given circuit reducing quickly to 0 caus es the RST pin voltage to momentarily fall below OV However this voltage is internally limited and will not harm the device NOTE The port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 15 to them Powering up the device without a valid reset could cause the CPU to start executing instructions from an indeterminate location This is because the SFRs spe cifically the Program Counter may not get properly initialized POWER SAVING MODES OF OPERATION For applications where power consumption is critical the CHMOS version provides power reduced modes of operation as a standard feature The power down mode in HMOS devices is no longer a standard feature and is being phased out
80. ble specified is complemented A bit which had been a one is changed to zero and vice versa No other flags are affected CLR can operate on the carry or any directly address able bit Note When this instruction is used to modify an output pin the value used as the original data will be read from the output data latch not the input pin Example 1 has previously been written with 5BH 01011101B The instruction sequence CPL Pl CPL 1 2 will leave the port set to 5 01011011B CPL C Bytes 1 Cycles 1 Encoding 1011 0011 Operation CPL intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CPL bit Bytes 2 Cycles 1 Encoding bit address Operation CPL bit lt 1 bit DA A Function Decimal adjust Accumulator for Addition Description DA A adjusts the eight bit value in the Accumulator resulting from the earlier addition of two variables each in packed BCD format producing two four bit digits Any ADD or ADDC instruction may have been used to perform the addition If Accumulator bits 3 0 are greater than nine xxxx1010 xxxx1111 or if the AC flag is one six is added to the Accumulator producing the proper BCD digit in the low order nibble This internal addition would set the carry flag if a carry out of the low order four bit field propagat ed through all high order bits but it would not clear the carry flag otherwise If the carry flag is now set or if the four high order bits
81. can only be read This addressing mode is intended for reading look up tables in Program Memory A 16 bit base register either DPTR or the Program Counter points to the base of the table and the Accumulator is set up with the table entry number The address of the table entry in Program Memory is formed by adding the Accumulator data to the base pointer Another type of indexed addressing is used in the case jump instruction In this case the destination address of a jump instruction is computed as the sum of the base pointer and the Accumulator data Arithmetic Instructions The menu of arithmetic instructions is listed in Table 2 The table indicates the addressing modes that can be used with each instruction to access the byte oper and For example the ADD A lt byte gt instruction can be written as ADD A 7FH direct addressing ADD A GRO indirect addressing ADD A R7 register addressing ADD A 127 immediate constant The execution times listed in Table 2 assume a 12 MHz clock frequency All of the arithmetic instructions exe cute 1 us except the INC DPTR instruction which takes 2 js and the Multiply and Divide instructions which take 4 ps Note that any byte in the internal Data Memory space can be incremented or decremented without going through the Accumulator One of the INC instructions operates on the 16 bit Data Pointer The Data Pointer is used to generate 16 bit addresses for external memory
82. cation notes are found in the Em bedded Control Applications handbook Order Num ber 270648 1 69 An Introduction to the Intel 5 51 Sin gle Chip Microcomputer Family 2 AP 70 Using the Intel MCS 51 Boolean Process ing Capabilities 5 51 Programmer s Guide Instruction Set MCS 51 PROGRAMMER S CONTENTS PAGE GUIDE AND INSTRUCTION SET WHAT DO THE SFRs CONTAIN JUST AFTER POWER ON OR RESET PSW PROGRAM STATUS WORD BIT ADDRESSABLE PCON POWER CONTROL REGISTER NOT BIT ADDRESSABLE INTERRUPTS IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS PRIORITY WITHIN LEVEL IP INTERRUPT PRIORITY REGISTER BIT ADDRESSABLE TCON TIMER COUNTER CONTROL REGISTER BIT ADDRESSABLE TMOD TIMER COUNTER MODE CONTROL REGISTER NOT BIT ADDRESSABLE TIMER SET UP TIMER COUNTER 0 TIMER COUNTER 1 T2CON TIMER COUNTER 2 CONTROL REGISTER BIT ADDRESSABLE TIMER COUNTER 2 SET UP SCON SERIAL PORT CONTROL REGISTER BIT ADDRESSABLE 2 1 CONTENTS PAGE CONTENTS PAGE SERIAL PORT SET UP USING TIMER COUNTER 2 TO GENERATE BAUD RATES GENERATING BAUD RATES Serial Portin Mode 6 SERIAL PORT IN MODE 2 Serial Port in Mode 1 SERIAL PORT IN MODE 3 USING TIMER COUNTER 1 TO 59 51 INSTRUCTION SET GENERATE BAUD RATES INSTRUCTION DEFINITIONS 2 2 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET The information pre
83. ccess by any external and must be held active long enough to allow the oscil means to the on chip Program Memory The effect of lator to restart and stabilize normally less than 10 this lock bit is that while it is programmed the internal msec Program Memory can not be read out the device can not further programmed and it not execute ternal Program Memory Erasing the EPROM array deactivates the lock bit and restores the device s full EPROM VERSIONS functionality It can then be re programmed The EPROM versions of these devices are listed in Ta ble 4 The 8751H programs at VPP 21V using one The procedure for programming the lock bit is detailed 50 msec PROG pulse per byte programmed This the 8751H data sheet sults in a total programming time 4K bytes of approx imately 4 minutes Two Program Memory Lock Schemes The 8751BH 8752BH and 87C51 use the faster 8751BH 8752BH and 87C51 contain two Program Quick Pulse programming algorithm These de Memory locking schemes Encrypted Verify and Lock vices program at VPP 12 75V using a series of Bits twenty five 100 us PROG pulses per byte programmed This results in total programming time of approxi Encryption Array Within the EPROM is an array of mately 26 seconds for the 8752BH 8 Kbytes and encryption bytes that are initially unprogrammed all 13 seconds for the 87C51 4 Kbytes 1 5 The user can program the
84. cle If an 8 bit address is being used MOVX GRi the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory cycle This will facili tate paging In any case the low byte of the address is time multi plexed with the data byte on Port 0 The ADDR DATA signal drives both FETs in the Port 0 output buffers Thus in this application the Port O pins are not open drain outputs and do not require externa pull ups Signal ALE Address Latch Enable should be used to capture the address byte into an external latch The address byte is valid at the negative transition of ALE Then in a write cycle the data byte to be written appears on Port 0 just before WR is activated and re mains there until after WR is deactivated a read cycle the incoming byte is accepted at Port 0 just be fore the read strobe is deactivated During any access to external memory the CPU writes OFFH to the Port 0 latch the Special Function Regis ter thus obliterating whatever information the Port 0 SFR may have been holding If the user writes to Port O during an externa memory fetch the incoming code byte is corrupted Therefore do not write to Port 0 if external program memory is used External Program Memory is accessed under two con ditions 1 Whenever signal is active or 2 Whenever the program counter PC contains a number that is larger than OFFFH 1FFFH for the 8052 This requires that the ROMle
85. control To execute a loop N times load counter byte with N and terminate loop with a DJNZ to the beginning of the loop as shown below for N 10 MOV COUNTER 10 LOOP begin loop end loop DJNZ COUNTER LOOP continue The CJNE instruction Compare and Jump if Not Equal can also be used for loop control as in Figure 12 Two bytes are specified in the operand field of the in struction The jump is executed only if the two bytes are not equal In the example of Figure 12 the two 270251 12 bytes were the data in R1 and the constant 2AH The A CHMOS initial data in R1 was 2EH Every time the loop was executed R1 was decremented and the looping was to continue until the R1 data reached 2 Another application of this instruction is in greater than less than comparisons The two bytes in the op erand field are taken as unsigned integers If the first is less than the second then the Carry bit is set 1 If the first is greater than or equal to the second then the Carry bit is cleared 270251 13 5 TIMING All 5 51 microcontrollers have an on chip oscillator which can be used if desired as the clock source for the CPU To use the on chip oscillator connect a crystal or ceramic resonator between the XTALI and XTAL2 pins of the microcontroller and capacitors to ground as shown in Figure 13 270251 14 CHMOS Figure 14 Usi
86. crement and Jump if Not Zero Description DJNZ decrements the location indicated by 1 and branches to the address indicated by the second operand if the resulting value is not zero An original value of 00H will underflow to OFFH No flags are affected The branch destination would be computed by adding the signed relative displacement value in the last instruction byte to the PC after incrementing the PC to the first byte of the following instruction The location decremented may be a register or directly addressed byte Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Internal RAM locations 40H 50H and 60H contain the values O1H 70H and 15H respec tively The instruction sequence DJNZ 40H LABEL__1 DJNZ SOH LABEL 2 DJNZ 60H LABEL 3 will cause a jump to the instruction at label LABEL 2 with the values and 15H in the three RAM locations The first jump was not taken because the result was zero This instruction provides a simple way of executing a program loop a given number of times or for adding a moderate time delay from 2 to 512 machine cycles with a single instruction The instruction sequence MOV R2 8 TOGGLE CPL P1 7 DJNZ R2 TOGGLE will toggle P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse will last three machine cycles two for D
87. cting signed integers OV indicates a negative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number The source operand allows four addressing modes register direct register indirect or imme diate The Accumulator holds OC9H 11001001B register 2 holds 54H 01010100B and the carry flag is set The instruction SUBB A R2 will leave the value 74H 01110100B in the accumulator with the carry flag and AC cleared but OV set Notice that OC9H minus 54H is 75H The difference between this and the above result is due to the carry borrow flag being set before the operation If the state of the carry is not known before starting a single or multiple precision subtraction it should be explicitly cleared by a CLR C instruction SUBB Rn 2 70 intel SUBB A direct Bytes Cycles Encoding Operation SUBB A Ri Bytes Cycles Encoding Operation SUBB A data Bytes Cycles Encoding Operation SWAP A Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 SUBB C direct 1 1 SUBB O 2 1 SUBB A data Swap nibbles within the Accumulator SWAP A interchanges the low and high order nibbles fou
88. d phases for various kinds of instructions Nor mally two program fetches are generated during each machine cycle even if the instruction being executed doesn t require it If the instruction being executed doesn t need more code bytes the CPU simply ignores the extra fetch and the Program Counter is not incre mented Execution of a one cycle instruction Figure 15 and B begins during State 1 of the machine cycle when the opcode is latched into the Instruction Register A sec ond fetch occurs during S4 of the same machine cycle Execution is complete at the end of State 6 of this ma chine cycle The MOVX instructions take two machine cycles to execute No program fetch is generated during the sec ond cycle of a instruction This is the only time program fetches are skipped The fetch execute se quence for MOVX instructions is shown in Figure 15 D 5 51 ARCHITECTURAL OVERVIEW The fetch execute sequences are the same whether the Program Memory is internal or external to the chip Execution times do not depend on whether the Pro gram Memory is internal or external Figure 16 shows the signals and timing involved in pro gram fetches when the Program Memory is external If Program Memory is external then the Program Memo ry read strobe PSEN is normally activated twice per machine cycle as shown in Figure 16 A If an access to external Data Memory occurs as shown in Figure 16 B two PSENs are skipped
89. destination address is obtained by successively concatenating the five high order bits of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2K block of the program memory as the first byte of the instruction following ACALL No flags are affected Initially SP equals 07H The label SUBRTN is at program memory location 0345 H After executing the instruction ACALL SUBRTN at location 0123H SP will contain 09H internal RAM locations 08H and 09H will contain 25H and 01H respectively and the PC will contain 0345H Bytes 2 Cycles 2 Encoding 10 a9 81 0001 a7 a6 a5 a4 a2 a1 Operation ACALL PC PO 2 SP SP 1 SP PC7 9 SP SP 1 SP 15 8 10 0 page address 2 28 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ADD A lt src byte gt Function Description Example ADD A Rn Bytes Cycles Encoding Operation ADD A direct Bytes Cycles Encoding Operation Add ADD adds the byte variable indicated to the Accumulator leaving the result in the Accumula tor The carry and auxiliary carry flags are set respectively if there is a carry out from bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occured OV 15 set if there is a carry out of bit 6 but not
90. e first register RO of the second register bank Thus in order to use more than one register bank the SP should be intialized to a different location of the RAM where it is not used for data storage ie higher part of the RAM 2 Bit Addressable Area 16 bytes have been assigned for this segment 20H 2FH Each one of the 128 bits of this segment can be directly addressed 0 7FH The bits can be referred to in two ways both of which are acceptable by the ASM 51 One way is to refer to their addresses 0 7FH The other way is with reference to bytes 20H to Thus bits 0 7 can also be referred to as bits 20 0 20 7 and bits 8 FH are the same as 21 0 21 7 and so on Each of the 16 bytes in this segment can also be addressed as a byte 3 Scratch Pad Area Bytes 30H through 7FH are available to the user as data RAM However if the stack pointer has been initialized to this area enough number of bytes should be left aside to prevent SP data destruction 2 6 intel 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Figure 4 shows the different segments of the on chip RAM 270249 5 Figure 4 128 Bytes of RAM Direct and Indirect Addressable intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SPECIAL FUNCTION REGISTERS Table 1 contains a list of all the SFRs and their addresses Comparing Table 1 and Figure 5 shows that all of the SFRs that are byte and bit addressable are located on the first column of the diag
91. e 69H 01101001B When the destination is a directly addressed byte this instruction can complement combina tions of bits in any RAM location or hardware register The pattern of bits to be complement ed is then determined by a mask byte either a constant contained in the instruction or a variable computed in the Accumulator at run time The instruction XRL 1 00110001 will complement bits 5 4 and O of output Port 1 2 78 intel XRL A Rn Bytes Cycles Encoding Operation A direct Bytes Cycles Encoding Operation XRL 8 Bytes Cycles Encoding Operation XRL A data Bytes Cycles Encoding Operation direct A Bytes Cycles Encoding Operation 59 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 XRL Rn 2 1 0110 0101 direct address XRL A direct 1 1 XRL Ri 2 1 0100 XRL lt A data 2 1 XRL direct lt direct A 2 74 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XRL direct data Bytes 3 Cycles 2 Encoding 0011 immediate data Operation XRL direct lt direct data 2 75 8051 8052 and 80C51 Hardware Description 8051 8052 and 80C51 Hardware Description CONTENTS PAGE CONTENTS PAGE PORT STRUCTURES AND OPERATION POWER SAVING MODES OF OPERATION 3 1 intel
92. e gate wired to the source This transistor will allow the pin to source about 0 25 mA when shorted to ground In parallel with the fixed pullup is an enhancement mode transistor which is activated during 1 whenever the port bit does 0 to 1 transition During this interval if the port pin is shorted to ground this extra transistor will allow the pin to source an additional 30 mA 2 OSC PERIODS HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 270252 6 A HMOS Configuration The enhancement mode transistor is turned on for 2 osc periods after Q makes a 0 to 1 transition 2 OSC PERIODS INPUT PORT PIN 270252 7 B CHMOS Configuration pFET 1 is turned on for 2 osc periods after Q makes a 0 to 1 transition During this time pFET 1 also turns on pFET 3 through the inverter to form a latch which holds the 1 pFET 2 is also on Figure 5 Ports 1 And 3 HMOS And CHMOS Internal Pullup Contigurations Port 2 is Similar Except That It Holds The Strong Pullup On While Emitting 1s That Are Address Bits See Text Accessing External Memory In the CHMOS versions the pullup consists of three pFETs It should be noted that an n channel FET nFET is turned on when a logical 1 is applied to its gate and is turned off when a logical 0 is applied to its gate A p channel FET pFET is the opposite it is on when its gate sees a O and off when its gate sees a 1 PFETI in Figure 5 i
93. eared by software RI SCON 0 Receive interrupt flag Set by hardware at the end of the 8th bit time in mode 0 or halfway through the stop bit time in the other modes except see SM2 Must be cleared by software Description Baud Rate SHIFT REGISTER Fosc 12 8 Bit UART Variable 9 Bit UART Fosc 64 OR Fosc 32 9 Bit UART Variable SERIAL PORT SET UP Table 9 SM2 VARIATION Single Processor Environment SM2 0 Multiprocessor Environment SM2 1 GENERATING BAUD RATES Serial Port in Mode 0 Mode 0 has a fixed baud rate which is 1 12 of the oscillator frequency To run the serial port in this mode none of the Timer Counters need to be set up Only the SCON register needs to be defined Osc Freq Baud Rate au e T Serial Port in Mode 1 Mode 1 has a variable baud rate The baud rate can be generated by either Timer 1 or Timer 2 8052 only 2 19 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET USING TIMER COUNTER 1 TO GENERATE BAUD RATES For this purpose Timer 1 is used in mode 2 Auto Reload Refer to Timer Setup section of this chapter K x Oscillator Freq Baud Rate 222 12x 256 THI If SMOD 0 then K If SMOD 1 then K 1 2 SMOD is the PCON register Most of the time the user knows the baud rate and needs to know the reload value for TH1 Therefore the equation to calculate TH1 can be written as K x Osc Freq 256 Ties 384 x baud rate
94. ed BCD digits of the decimal number 24 the low order two digits of the decimal sum of 56 67 and the carry in The carry flag will be set by the Decimal Adjust instruction indicating that a decimal overflow occurred The true sum 56 67 and 1 is 124 BCD variables can be incremented or decremented by adding 01H or 99H If the Accumulator initially holds 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DA A will leave the carry set and 29H in the Accumulator since 30 99 129 The low order byte of the sum can be interpreted to mean 30 1 29 1 DA contents of Accumulator are BCD IF Aso gt 9 v 1 3 0 lt A3 9 6 AND IF A gt 9 v KO 11 THEN 7 4 lt 6 2 40 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET DEC byte Function Decrement Description variable indicated is decremented by 1 An original value of 00H will underflow to OFFH No flags are affected Four operand addressing modes are allowed accumulator register direct or register indirect Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Register 0 contains 7FH 01111111B Internal RAM locations and 7FH contain 00H and 40H respectively The instruction sequence DEC GRO DEC RO DEC GRO will leave register 0 set
95. eflect the current state of the CPU The PSW shown in Figure 10 resides in SFR space It con tains the Carry bit the Auxiliary Carry for BCD oper ations the two register bank select bits the Overflow flag a Parity bit and two user definable status flags The Carry bit other than serving the functions of a Carry bit in arithmetic operations also serves as the Accumulator for a number of Boolean operations intel MCS 51 ARCHITECTURAL OVERVIEW The bits RSO and RS1 are used to select one of the four register banks shown in Figure 7 A number of instruc tions refer to these RAM locations as RO through R7 The selection of which of the four banks is being re ferred to is made on the basis of the bits RSO and RS1 at execution time The Parity bit reflects the number of 1s in the Accumu lator P 1 if the Accumulator contains an odd num ber of 1s and P 0 if the Accumulator contains an even number of 1s Thus the number of 1s in the Accu mulator plus P is always even Two bits in the PSW are uncommitted and may be used as general purpose status flags Addressing Modes The addressing modes in the MCS 51 instruction set are as follows DIRECT ADDRESSING In direct addressing the operand is specified by an 8 bit address field in the instruction Only internal Data RAM and SFRs can be directly addressed INDIRECT ADDRESSING In indirect addressing the instruction specifies a register which contains t
96. ented reserved for future use Not implemented reserved for future use General purpose flag bit GFO General purpose flag bit PD Power Down bit Setting this bit activates Power Down operation in the 80C51BH Available only in CHMOS IDL Idle Mode bit Setting this bit activates Idle Mode operation in the 80C51BH Available only in CHMOS If 1s are written to PD and IDL at the same time PD takes precedence User software should not write 1s to reserved bits These bits may be used in future MCS 51 products to invoke new features in that case the reset or inactive value of the new bit will be O and its active value will be 1 2 11 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET INTERRUPTS In order to use any of the interrupts in the MCS 51 the following three steps must be taken 1 Set the EA enable all bit in the IE register to 1 2 Set the corresponding individual interrupt enable bit in the IE register to 1 3 Begin the interrupt service routine at the corresponding Vector Address of that interrupt See Table below Interrupt Vector Source Address IE0 TF1 RI amp TI TF2 amp EXF2 In addition for external interrupts pins INTO and INT1 P3 2 and P3 3 must be set to 1 and depending on whether the interrupt is to be level or transition activated bits ITO or IT1 in the TCON register may need to be set to 1 ITx 0 level activated ITx 1 transition act
97. erwise OV is cleared When adding signed integers OV indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or imme diate Example The Accumulator holds 0C3H 11000011B and register 0 holds 10101010B with the carry flag set The instruction ADDC A RO will leave 6EH 01101110B in the Accumulator with AC cleared and both the Carry flag and OV set to 1 2 30 intel ADDC A Rn Bytes Cycles Encoding Operation ADDC A direct Bytes Cycles Encoding Operation ADDC A GRi Bytes Cycles Encoding Operation ADDC A data Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 1 1 0011 1 ADDC 2 1 ADDC O direct 1 1 ADDC lt R 2 1 0011 immediate data ADDC A A C data 2 31 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET AJMP 11 Function Absolute Jump Description AJMP transfers program execution to the indicated address which is formed at run time by concatenating the high order five bits of the PC after incrementing the PC twice opcode bits 7 5 and the second byte of the instruction The destination must therefore be within the same 2K block of program mem
98. f TB8 and all positions to the left of that contain zeroes This condition flags the TX Control unit to do one last shift and then deactivate SEND and set TI This occurs at the 11th divide by 16 rollover after write to SBUF Reception is initiated by a detected 1 10 0 transition at RXD For this purpose RXD is sampled at a rate of 16 times whatever baud rate has been established When a transition is detected the divide by 16 counter is imme diately reset and 1FFH is written to the input shift register At the 7th 8th and 9th counter states of each bit time the bit detector samples the value of RXD The value accepted is the value that was seen in at least 2 of the 3 samples If the value accepted during the first bit time is not O the receive circuits are reset and the unit goes back to looking for another 1 to O transition If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will pro intel n HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 8051 INTERNAL BUS KEEKE PHASE 2 CLOCK tosc MODE 2 SMOD 1 SERIAL INTERRUPT SMOD 0 SMOD IS AX CLOCK RX CONTROL INPUT SHIFT REG 9 BITS LOAD N SBUF y Y ix 8051 INTERNAL BUS LOCK 1 f 1 1 1 WRITE TO SBUF 86 DATA Esim aS SHIFT R fil 1 A 1 TRANSMIT TXD SIT J STOP RX 16 RESET RECEIVE 270252
99. fect ed Example entering an interrupt routine the Stack Pointer contains 09H The Data Pointer holds the value 0123H The instruction sequence PUSH DPL PUSH DPH will leave the Stack Pointer set to OBH and store 23H and O1H in internal RAM locations OAH and OBH respectively Bytes 2 Cycles 2 Encoding 0000 Operation PUSH SP SP 1 SP lt direct intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET RET Function Return from subroutine Description RET pops the high and low order bytes of the PC successively from the stack decrementing the Stack Pointer by two Program execution continues at the resulting address generally the instruction immediately following an ACALL or LCALL No flags are affected Example The Stack Pointer originally contains the value OBH Internal RAM locations OAH and OBH contain the values 23H and O1H respectively The instruction RET will leave the Stack Pointer equal to the value 09H Program execution will continue at location 0123H Bytes 1 Cycles 2 Encoding 0010 0010 Operation RET 15 8 SP SP lt SP 1 PC7 9 lt SP SP SP 1 RETI Function Return from interrupt Description RETI pops the high and low order bytes of the PC successively from the stack and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed The Stack Poi
100. from 128 bytes preceding this instruction to 127 bytes following it The label RELADR is assigned to an instruction at program memory location 0123H The instruction 5 RELADR will assemble into location 0100H After the instruction is executed the PC wil contain the value 0123H Note Under the above conditions the instruction following SJMP will be at 102H Therefore the displacement byte of the instruction will be the relative offset 0123H 0102H 21H Put another way an SJMP with a displacement of OFEH would be a one instruction infinite loop 2 2 SJMP PC PO 2 PC PO rel 2 69 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SUBB A lt src byte gt Function Description Example SUBB Bytes Cycles Encoding Operation Subtract with borrow SUBB subtracts the indicated variable and the carry flag together from the Accumulator leaving the result in the Accumulator SUBB sets the carry borrow flag if a borrow is needed for bit 7 and clears C otherwise If C was set before executing a SUBB instruction this indicates that a borrow was needed for the previous step in a multiple precision subtraction so the carry is subtracted from the Accumulator along with the source operand AC is set if a borrow is needed for bit 3 and cleared otherwise OV is set if a borrow is needed into bit 6 but not into bit 7 or into bit 7 but not bit 6 When subtra
101. fset as described above The instruction is 2 bytes long consisting of the opcode and the relative offset byte The jump distance is limited to a range of 128 to 4 127 bytes relative to the instruction follow ing the SJMP The LJMP instruction encodes the destination address as a 16 bit constant The instruction is 3 bytes long consisting of the opcode and two address bytes The destination address can be anywhere in the 64K Pro gram Memory space The AJMP instruction encodes the destination address as an 11 bit constant The instruction is 2 bytes long consisting of the opcode which itself contains 3 of the 11 address bits followed by another byte containing the low 8 bits of the destination address When the instruc tion is executed these 11 bits are simply substituted for the low 11 bits in the PC The high 5 bits stay the same Hence the destination has to be within the same 2K block as the instruction following the AJMP In all cases the programmer specifies the destination address to the assembler in the same way as a label or as a 16 bit constant The assembler will put the destina tion address into the correct format for the given in struction If the format required by the instruction will not support the distance to the specified destination ad dress a Destination out of range message is written into the List file The JMP A DPTR instruction supports case jumps The destination address is computed at execu
102. fy Write Feature Some instructions that read a port read the latch and others read the pin Which ones do which The instruc tions that read the latch rather than the pin are the ones that read a value possibly change it and then rewrite it to the latch These are called read modify write in structions The instructions listed below are read mod ify write instructions When the destination operand is a port or a port bit these instructions read the latch rather than the pin ANL logical AND e g ANL P1 ORL logical OR e g ORL P2 XRL logical EX OR e g XRL P3 A JBC jump if bit 1 and clear bit e g JBC 1 1 LABEL CPL complement bit e g CPL P3 0 INC increment e g INC P2 DEC decrement e g DEC P2 DJNZ decrement and jump if not zero e g DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of Port X CLR PX Y clear bit Y of Port X SETBPX Y set bit Y of Port X It is not obvious that the last three instructions in this list are read modify write instructions but they are They read the port byte all 8 bits modify the addressed bit then write the new byte back to the latch The reason that read modify write instructions are di rected to the latch rather than the pin is to avoid a possible misinterpretation of the voltage level at the pin For example a port bit might be used to drive the base of a transistor When a 1 is written to the bit the transistor is turned o
103. g the signed relative displacement in the second instruction byte to the PC after incrementing the twice No flags are affected The carry flag is cleared The instruction sequence JC LABELI CPL C JC LABEL2 will set the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 JC PO PO 2 IF O 1 THEN PO 2 47 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JMP A DPTR Function Description Example Bytes Encoding Operation Jump indirect Add the eight bit unsigned contents of the Accumulator with the sixteen bit data pointer and load the resulting sum to the program counter This will be the address for subsequent instruc tion fetches Sixteen bit addition is performed modulo 216 a carry out from the low order eight bits propagates through the higher order bits Neither the Accumulator nor the Data Pointer is altered No flags are affected An even number from to 6 is in the Accumulator The following sequence of instructions will branch to one of four AJMP instructions in a jump table starting at JMP__TBL MOV JMP JMP__TBL AJMP AJMP AJMP AJMP DPTR JMP__TBL A DPTR LABELO LABEL LABEL2 LABEL3 If the Accumulator equals 04H when starting this sequence execution will jump to label LABEL2 Remember that AJMP is a two byte instruction so the jump
104. gh to low interrupt sources are listed below IEO TF0 1 TF1 RI or TI TF2 or EXF2 IP INTERRUPT PRIORITY REGISTER BIT ADDRESSABLE If the bit is 0 the corresponding interrupt has a lower priority and if the bit is 1 the corresponding interrupt has a higher priority IP 7 Not implemented reserved for future use IP 6 Not implemented reserved for future use PT2 IP 5 Defines the Timer 2 interrupt priority level 8052 only PS IP 4 Defines the Serial Port interrupt priority level 3 Defines the Timer 1 interrupt priority level 2 Defines External Interrupt 1 priority level 1 Defines the Timer 0 interrupt priority level PXO 0 Defines the External Interrupt 0 priority level User software should not write 1s to reserved bits These bits may be used in future MCS 51 products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 2 13 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TCON TIMER COUNTER CONTROL REGISTER BIT ADDRESSABLE TCON 7 Timer 1 overflow flag Set by hardware when the Timer Counter 1 overflows Cleared by hard ware as processor vectors to the interrupt service routine TRI TCON 6 Timer 1 run control bit Set cleared by software to turn Timer Counter 1 ON OFF TCON 5 Timer 0 overflow Set by hardware when the Timer Counter 0 overflows Cleared by hard
105. gister R7 RO of the currently se lected Register Bank direct 8 bit internal data location s address This could be an Internal Data RAM location 0 127 a SFR i e I O port control register status register etc 128 255 Ri 8 bit internal data RAM location 0 255 addressed indirectly through reg ister R1 or RO data 8 bit constant included in instruction data 16 16 bit constant included in instruction addr 16 16 bit destination address Used by LCALL amp LJMP A branch be anywhere within the 64K byte Pro gram Memory address space 11 bit destination address Used by ACALL amp AJMP The branch will be within the same 2K byte page of pro gram memory as the first byte of the following instruction Signed two s complement 8 bit offset byte Used by SJMP and all condition al jumps Range 128 to 127 bytes relative to first byte of the fol lowing instruction Direct Addressed bit in Internal Data RAM or Special Function Register 2 21 intel ARITHMETIC OPERATIONS Continued INC MUL DIV DA LOGICAL OPERATIONS ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL DPTR AB AB A A Rn A Ri A data direct A direct data A direct A Ri A data direct A direct data A Rn A direct A Ri A data direct A direct data MCS 51 PROGRAMMER S
106. hardware at the end of the 8th bit time in Mode 0 or at the beginning of the stop bit in the other modes in any serial transmission Must be cleared by software is receive interrupt flag Set by hardware at the end of the Bth bit time in Mode 0 or halfway through the stop bit time in the other modes in any serial reception except see 5 2 Must be cleared by software Figure 14 SCON Serial Port Control Register Baud Rates The baud rate in Mode 0 is fixed Mode 0 Baud Rate Oscillator Frequency The baud rate in Mode 2 depends on the value of bit SMOD in Special Function Register PCON If SMOD 0 which is the value on reset the baud rate 1 4 the oscillator frequency If SMOD 1 the baud rate is the oscillator frequency 3 15 2SMOD Mode 2 Baud Rate X Oscillator Frequency In tbe 8051 the baud rates in Modes 1 and 3 are deter mined by the Timer 1 overflow rate In the 8052 these baud rates can be determined by Timer 1 or by Timer 2 or by both one for transmit and the other for re ceive intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 Using Timer 1 to Generate Baud Rates mode high nibble of TMOD 0010B In that case the baud rate is given by the formula When Timer 1 is used as the baud rate generator the baud rates in Modes 1 and 3 are determined by the Modes1 3 25 Oscillator Frequency 1 overflow rate and the value of SMOD as fol Baud Rate 7 12
107. he address of the operand Both inter nal and external RAM can be indirectly addressed The address register for 8 bit addresses can be RO or of the selected register bank or the Stack Pointer The address register for 16 bit addresses can only be the 16 bit data pointer register DPTR REGISTER INSTRUCTIONS The register banks containing registers RO through R7 can be accessed by certain instructions which carry a 3 bit register specification within the opcode of the in struction Instructions that access the registers this way are code efficient since this mode eliminates an address byte When the instruction is executed one of the eight registers in the selected bank is accessed One of four banks is selected at execution time by the two bank select bits in the PSW REGISTER SPECIFIC INSTRUCTIONS Some instructions are specific to a certain register For example some instructions always operate on the Ac cumulator or Data Pointer etc so no address byte is needed to point to it The opcode itself does that In structions that refer to the Accumlator as A assemble as accumulator specific opcodes IMMEDIATE CONSTANTS The value of a constant can follow the opcode in Pro gram Memory For example A 100 loads the Accumulator with the decimal number 100 The same number could be specified in hex digits as 64H INDEXED ADDRESSING Only Program Memory can be accessed with indexed addressing and it
108. he standard Timer O control bits THO is an 8 bit Timer and is controlled by Timer 1 control bits 3 Timer 1 Timer Counter 1 stopped intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TIMER SET UP Tables 3 through 6 give some values for TMOD which can be used to set up Timer 0 in different modes It is assumed that only one timer is being used at a time If it is desired to run Timers 0 and 1 simultaneously in any mode the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 Tables 5 and 6 For example if it is desired to run Timer 0 in mode 1 GATE external control and Timer 1 in mode 2 COUNTER then the value that must be loaded into TMOD is 69H 09H from Table 3 ORed with 60H from Table 6 Moreover it is assumed that the user at this point is not ready to turn the timers on and will do that at a different point in the program by setting bit TRx Gn TCON to 1 TIMER COUNTER 0 As a Timer Table 3 TIMER 0 FUNCTION INTERNAL CONTROL NOTE 1 EXTERNAL CONTROL NOTE 2 13 bit Timer 16 bit Timer 8 bit Auto Reload two 8 bit Timers As a Counter Table 4 COUNTER 0 FUNCTION INTERNAL CONTROL NOTE 1 EXTERNAL CONTROL NOTE 2 13 bit Timer 16 bit Timer 8 bit Auto Reload one 8 bit Counter NOTES 1 The Timer is turned ON OFF by setting clearing bit TRO in the software 2 The Timer is turned ON OFF by the 1 to 0 t
109. he value 8BH 10001011B with the carry unaffected 1 RL 1 lt 0 6 0 7 Rotate Accumulator Left through the Carry flag The eight bits in the Accumulator and the carry flag are together rotated one bit to the left Bit 7 moves into the carry flag the original state of the carry flag moves into the bit 0 position No other flags are affected The Accumulator holds the value 0C5H 11000101B and the carry is zero The instruction RLC A leaves the Accumulator holding the value 8BH 10001010B with the carry set 1 1 0011 0011 RLC An 1 lt 0 6 A0 C C A7 2 66 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET RR A Function Rotate Accumulator Right Description eight bits in the Accumulator are rotated one bit to the right Bit O is rotated into the bit 7 position No flags are affected Example Accumulator holds the value 0C5H 11000101 The instruction RR A leaves the Accumulator holding the value OE2H 11100010B with the carry unaffected Bytes 1 Cycles 1 Encoding 0000 0011 Operation RR 1 n 0 6 AO Function Rotate Accumulator Right through Carry flag Description eight bits the Accumulator and the carry flag are together rotated one bit to the right Bit O moves into the carry flag the original value of the carry flag moves into the bit 7 position No ot
110. her flags are affected Example Accumulator holds the value OC5H 11000101B the carry is zero The instruction RRC A leaves the Accumulator holding the value 62 01100010B with the carry set Bytes 1 Cycles 1 Encoding 0001 0011 Operation RRC lt 1 n 0 6 7 2 67 intel SETB lt bit gt Function Description Example SETB C Bytes Cycles Encoding Operation SETB bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Set Bit SETB sets the indicated bit to one SETB can operate on the carry flag or any directly addressable bit No other flags are affected The carry flag is cleared Output Port 1 has been written with the value 34H 00110100B The instructions SETB C SETB P1 0 will leave the carry set to 1 and change the data output on Port 1 to 35H 00110101B 1101 0011 SETB 1 2 1 mams SETB bit 1 2 68 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SJMP rel Function Description Example Bytes Cycles Encoding Operation Short Jump Program control branches unconditionally to the address indicated The branch destination is computed by adding the signed displacement in the second instruction byte to the PC after incrementing the PC twice Therefore the range of destinations allowed is
111. iginally shifted out on the right has propagated to location 2AH Since that location should be left with Os the lost digit is moved to the Accumulator intel MCS 51 ARCHITECTURAL OVERVIEW EXTERNAL RAM Table 5 shows a list of the Data Transfer instructions that access external Data Memory Only indirect ad dressing can be used The choice is whether to use a one byte address Ri where Ri can be either RO or R1 of the selected register bank or a two byte address DPTR The disadvantage to using 16 bit addresses if only a few K bytes of external RAM are involved is that 16 bit addresses use all 8 bits of Port 2 as address bus On the other hand 8 bit addresses allow one to address a few K bytes of RAM as shown in Figure 5 without having to sacrifice all of Port 2 All of these instructions execute in 2 ps with a 12 MHz clock Table 5 A List of the MCS 51 Data Transfer Instructions that Access External Data Memory Space s SES ECILTCNE NEN nomena prima EN Note that in all external Data RAM accesses the Ac cumulator is always either the destination or source of the data The read and write strobes to external RAM are acti vated only during the execution of a MOVX instruc tion Normally these signals are inactive and in fact if they re not going to be used at all their pins are avail able as extra I O lines More about that later LOOKUP
112. ime The instruction ORL 1 00110010 will set bits 5 4 and 1 of output Port 1 ORL Bytes 1 Cycles 1 encoding Operation ORL A A V Rn 2 61 intel ORL Bytes Cycles Encoding Operation ORL A Ri Bytes Cycles Encoding Operation ORL A data Bytes Cycles Encoding Operation ORL direct A Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 2 1 15919121 ORL V direct 1 1 ORL 2 1 ORL A A V data 2 1 ORL direct direct V A ORL direct data Bytes Cycles Encoding Operation 3 2 ORL direct direct V data 2 62 immediate data intel ORL C lt src bit gt Function Description Example ORL C bit Bytes Cycles Encoding Operation ORL C bit Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Logical OR for bit variables Set the carry flag if the Boolean value is a logical 1 leave the carry in its current state otherwise A slash preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value but the source bit itself is not affected No other flags are affected Set the carry flag if and only if P1 0 1
113. in SCON The baud rate is programmable to either or the oscillator frequency in Mode 2 Mode 3 may have a variable baud rate generated from either Timer 1 or 2 depending on the state of TCLK and RCLK Figures 19 and 20 show a functional diagram of the serial port in Modes 2 and 3 The receive portion is exactly the same as in Mode 1 The transmit portion differs from Mode 1 only in the 9th bit of the transmit shift register Transmission is initiated by any instruction that uses SBUF as a destination register The write to SBUF signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX Control unit that a transmission is requested Transmission com mences at 1 1 of the machine cycle following the next rollover in the divide by 16 counter Thus the bit times are synchronized to the divide by 16 counter not to the write to SBUF signal The transmission begins with activation of SEND which puts the start bit at TXD One bit time later DATA is activated which enables the output bit of the transmit shift register to TXD The first shift pulse oc curs one bit time after that The first shift clocks a 1 the stop bit into the 9th bit position of the shift regis ter Thereafter only zeroes are clocked in Thus as data bits shift out to the right zeroes are clocked in from the left When TB8 is at the output position of the shift register then the stop bit is just to the left o
114. instructions start at every other address 1 2 JMP DPTR 2 48 intel JNB bit el Function Description Example Bytes Cycles Encoding Operation JNC rel Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Jump if Bit Not set If the indicated bit is a zero branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC after incrementing the PC to the first byte of the next instruction The bit tested is not modified No flags are affected The data present at input port 1 is 11001010B The Accumulator holds 56H 01010110B The instruction sequence JNB Pi 3LABELI JNB ACC 3 LABEL2 will cause program execution to continue at the instruction at label LABEL2 3 2 0000 JNB PC PO 3 IF bi 0 THEN PC PC rel Jump if Carry not set If the carry flag is a zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice to point to the next instruction The carry flag is not modified The carry flag is set The instruction sequence JNC LABEL CPL C JNC LABEL2 will clea
115. intel MCS 51 MICROCONTROLLER FAMILY USER S MANUAL ORDER NO 272383 002 FEBRUARY 1994 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein intel retains the right to make changes to these specifications at any time without notice Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation Intel Corporation and intel s FASTPATH are not affiliated with Kinetics a division of Excelan Inc or its FASTPATH trademark or products Other brands and names are the property of their respective owners Additional copies of this document or other Intel literature may be obtained from Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 7641 or call 1 800 879 4683 c INTEL CORPORATION 1993 MCS 51 MICROCONTROLLER FAMILY USER S MANUAL CONTENTS PAGE CHAPTER 1 MCS 51 Family of Microcontrollers Architectural Overview CHAPTER 2 MCS 51 Programmer s Guide and Instruction Set CHAPTER 3 8051 8052 and 80C51 Hardware Description CHAPTER 4 8XC52 54 58 Hardware Description CHAPTER 5 8XC51FX Hardware Description CHAPTER 6 87C51GB Hardware Description CHAPTER 7 83
116. internal flag be moved to a port pin MOV MOV C FLAG P1 0 C In this example FLAG is the name of any addressable bit in the Lower 128 or SFR space An I O line the LSB of Port 1 in this case is set or cleared depending on whether the flag bit is 1 or O The Carry bit in the PSW is used as the single bit Accu mulator of the Boolean processor Bit instructions that refer to the Carry bit as C assemble as Carry specific instructions CLR C etc The Carry bit also has a direct address since it resides in the PSW register which is bit addressable Note that the Boolean instruction set includes ANL and ORL operations but not the XRL Exclusive OR operation An XRL operation is simple to implement in software Suppose for example it is required to form the Exclusive OR of two bits C bit XRL bit2 The software to do that could be as follows MOV C bit1 JNB bit2 OVER CPL OVER continue First bit is moved to the Carry If bit2 0 then C now contains the correct result That is bit XRL bit2 bit if bit2 0 On the other hand if bit2 1C now contains the complement of the correct result It need only be inverted CPL C to complete the opera tion This code uses the JNB instruction one of a series of bit test instructions which execute a jump if the ad dressed bit is set JC JB JBC or if the addressed bit is not set JNC JNB In the above case bit2 is being tested and if bit2
117. is active could cause the device to go into an indetermi nate state The internal reset algorithm writes Os to all the SFRs except the port latches the Stack Pointer and SBUF The port latches are initialized to FFH the Stack Pointer to 07H and SBUF is indeterminate Table 3 lists the SFRs and their reset values The internal RAM is not affected by reset On power up the RAM content is indeterminate y Y Y Y Y Y Y Y Y Jaoor jocos j LI 5 11 OSC PERIODS 19 OSC PERIODS q SSMsS SsO_ 270252 33 Figure 25 Reset Timing 3 26 intel Table 3 Reset Values of the SFRs BEI Fe See 2 ______ mM _ PO P3 _____ FFH TOD ___ 0H THO OOH TH TL1 2 8052 __7 2 8052 _ 00H 2 8052 _ RCAP2L 8052 SCON PCON HMOS PCON CHMOS 270252 21 Figure 26 Power on Reset Circuit 3 27 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 POWER ON RESET For HMOS devices when Vcc is turned on an automat ic reset can be obtained by connecting the RST pin to through 10 uF capacitor and to Vss through an 8 2 resistor Figure 26 The CHMOS devices do not require this resistor although its presence does no harm In fact for CHMOS devices the external resistor can be removed
118. it clock in modes 1 and 3 0 causes Timer 1 overflows to be used for the transmit clock Timer 2 external enable flag When set allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port EXEN2 0 causes Timer 2 to ignore events at T2EX Start stop control for Timer 2 A logic 1 starts the timer Timer or counter select Timer 2 0 internal timer OSC 12 1 External event counter falling edge triggered Capture Reload flag When set captures will occur on negative transitions at 2 if 2 1 When cleared auto reloads will occur either with Timer 2 overflows or negative transitions at 2 when EXEN2 1 When either RCLK 10r TCLK 1 this bit is ignored and the timer is forced to auto reload on Timer 2 overflow Figure 11 T2CON Timer Counter 2 Control Register In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON If EXEN2 0 then Timer 2 is a 16 bit timer or counter which upon overflowing sets bit TF2 the Timer 2 overflow bit which can be used to generate an interrupt If EXEN2 1 then Timer 2 still does the above but with the added feature that a 1 to 0 transition at external input T2EX causes the current value in the Timer 2 registers TL2 and 2 to be captured into registers RCAP2L and RCAP2H respectively RCAP2L and RCAP2H are new Special Function Registers in the 8052 In
119. ivated IE INTERRUPT ENABLE REGISTER BIT ADDRESSABLE If the bit is 0 the corresponding interrupt is disabled If the bit is 1 the corresponding interrupt is enabled IE 7 Disables all interrupts If EA 0 no interrupt will be acknowledged If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its enable bit IE 6 implemented reserved for future use ET2 IE 5 Enable or disable the Timer 2 overflow or capture interrupt 8052 only ES 4 Enable or disable the serial port interrupt ETI JE 3 X Enable or disable the Timer 1 overflow interrupt EX1 IE 2 Enable or disable External Interrupt 1 ETO IE Enable or disable the Timer 0 overflow interrupt EX0 IE 0 Enable or disable External Interrupt 0 User software should not write 15 to reserved bits These bits may be used in future MCS 51 products to invoke new features In that case the reset or inactive value of the new bit will be 0 and its active value will be 1 2 12 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1 Remember that while an interrupt service is in progress it cannot be interrupted by a lower or same level interrupt PRIORITY WITHIN LEVEL Priority within level is only to resolve simultaneous requests of the same priority level From hi
120. lso have returned execution to the interrupted program but it would have left the interrupt control system thinking an interrupt was still in progress 3 25 External Interrupts The external sources can be programmed to be level ac tivated or transition activated by setting or clearing bit or ITO in Register TCON If ITx 0 external interrupt x is triggered by a detected low at the INTx pin If ITx 1 external interrupt x is edge triggered In this mode if successive samples of the INTx pin Show a high in one cycle and a low in the next cycle interrupt request flag IEx in TCON is set Flag bit IEx then requests the interrupt Since the external interrupt pins are sampled once each machine cycle an input high or low should hold for at least 12 oscillator periods to ensure sampling If the external interrupt is transition activated the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag IEx will be set IEx will be automatically cleared by the CPU when the service routine is called If the external interrupt is level activated the external source has to hold the request active until the requested interrupt is actually generated Then it has to deacti vate the request before the interrupt service routine is completed or else another interrupt will be generated Response Ti
121. me The INTO and INTI levels are inverted and latched into the interrupt flags IEO and IE1 at S5P2 of every machine cycle Similarly the Timer 2 flag EXF2 and the Serial Port flags RI and TI are set at S5P2 The values are not actually polled by the circuitry until the next machine cycle The Timer 0 and Timer 1 flags and TF1 are set at 5 2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in the same cycle in which the timer overflows If a request is active and conditions are right for it to be acknowledged a hardware subroutine call to the re quested service routine will be the next instruction to be executed The call itself takes two cycles Thus a mini mum of three complete machine cycles elapse between activation of an external interrupt request and the be ginning of execution of the first instruction of the serv ice routine Figure 24 shows interrupt response timings A longer response time would result if the request is blocked by one of the 3 previously listed conditions If an interrupt of equal or higher priority level is already in progress the additional wait time obviously depends on the nature of the other interrupt s service routine If the instruction in progress is not in its final cycle the additional wait time cannot be more than 3 cycles since the longest instructions MUL and DIV are o
122. mory as shown in Figure 2 The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8 bit addresses which can be more quickly stored and manipulated by an 8 bit CPU Nevertheless 16 bit Data Memory ad dresses can also be generated through the DPTR regis ter Program Memory can only be read not written to There can be up to 64K bytes of Program Memory In the ROM and EPROM versions of these devices the lowest 4K 8K or 16K bytes of Program Memory are provided on chip Refer to Table 1 for the amount of on chip ROM or EPROM on each device In the ROMliess versions all Program Memory is external The read strobe for external Program Memory is the signal PSEN Program Store Enable intel MCS 51 ARCHITECTURAL OVERVIEW Data Memory occupies a separate address space from Program Memory Up to 64K bytes of external RAM can be addressed in the external Data Memory space The CPU generates read and write signals RD and WR as needed during external Data Memory accesses External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program Data memory Program Memory Figure 3 shows a map of the lower part of the Program Memory After reset the CPU begins execution from location 0000H As shown in Figure 3 each interrupt is assigned a fixed
123. n 1 and either GATE Oor INTI 1 Setting GATE 1 allows the Timer to be controlled by external input INT1 to facilitate pulse width measurements TR1 is a control bit in the Special Function Register TCON Figure 8 GATE is in TMOD The 13 Bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are inde terminate and should be ignored Setting the run flag 1 does not clear the registers Mode 0 operation is the same for Timer 0 as for Timer 1 Substitute TRO TFO and INTO for the correspond ing Timer 1 signals in Figure 7 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 MODE 1 Mode 1 is the same as Mode 0 except that the Timer register is being run with all 16 bits LSB Timer 0 Timer 1 Gating control when set Timer Counter x is enabled only while INTx pin is high and control pin is set When cleared Timer x is enabled whenever control bit is set Timer or Counter Selector cleared for Timer operation input from internal system clock Set for Counter operation input from Tx input Operating Mode Timer Counter THx with as 5 bit prescaler 16 bit Timer Counter THx and TLx cascaded there is 8 bit auto reload Timer Counter holds value which is to be reloaded into each time it overflows
124. n If the CPU then reads the same port bit at the pin rather than the latch it will read the base voltage of the transistor and interpret it as a O Reading the latch rather than the pin will return the correct value of 1 ACCESSING EXTERNAL MEMORY Accesses to external memory are of two types accesses to external Program Memory and accesses to external Data Memory Accesses to external Program Memory use signal PSEN program store enable as the read strobe Accesses to external Data Memory use RD or WR alternate functions of P3 7 and P3 6 to strobe the memory Refer to Figures 36 through 38 in the Internal Timing section Fetches from external Program Memory always use a 16 bit address Accesses to external Data Memory can use either a 16 bit address MOVX GDPTR or an 8 bit address MOVX 3 9 Whenever a 16 bit address is used the high byte of the address comes out on Port 2 where it is held for the duration of the read or write cycle Note that the Port 2 drivers use the strong pullups during the entire time that they are emitting address bits that are 1s This is during the execution of a MOVX DPTR instruction During this time the Port 2 latch the Special Function Register does not have to contain 1s and the contents of the Port 2 SFR not modified If the external memory cycle is not immediately followed by another external memory cycle the undisturbed contents of the Port 2 SFR will reappear in the next cy
125. n may take any of the forms ANL A 7FH direct addressing ANL A R1 indirect addressing ANL A R6 register addressing ANL A 53H immediate constant All of the logical instructions that are Accumulator specific execute in lus using 12 MHz clock The others take 2 ps Note that Boolean operations can be performed on any byte in the lower 128 internal Data Memory space or the SFR space using direct addressing without having to use the Accumulator The XRL lt byte gt data in struction for example offers a quick and easy way to invert port bits as in XRL If the operation is in response to an interrupt not using the Accumulator saves the time and effort to stack it in the service routine The Rotate instructions RL A RLC A etc shift the Accumulator 1 bit to the left or right For a left rota tion the MSB rolls into the LSB position For a right rotation the LSB rolis into the MSB position 5 51 ARCHITECTURAL OVERVIEW The SWAP A instruction interchanges the high and low nibbles within the Accumulator This is a useful operation in BCD manipulations For example if the Accumulator contains a binary number which is known to be less than 100 it can be quickly converted to BCD by the following code MOV 10 DIV AB SWAP A ADD Dividing the number by 10 leaves the tens digit in the low nibble of the Accumulator and the ones digit in the B register The SWAP and ADD instructions m
126. ng an External 1 17 intel MCS 51 ARCHITECTURAL OVERVIEW Examples of how to drive the clock with an external oscillator are shown in Figure 14 Note that in the HMOS devices 8051 etc the signal at the XTAL2 pin actually drives the internal clock generator In the CHMOS devices 80C51BH etc the signal at the pin drives the internal clock generator If only one pin is going to be driven with the external oscillator signal make sure it is the right pin The internal clock generator defines the sequence of states that make up the MCS 51 machine cycle 1 P1 P2 S2 P2 53 m 54 1 P2 P P2 OSC XTAL2 P2 READ NEXT OPCODE DISCARD READ NEXT OPCODE DISCARD READ NEXT OPCODE DISCARD 0 MOVX 1 byte 2 Machine Cycles A machine cycle consists of a sequence of 6 states numbered S1 through S6 Each state time lasts for two oscillator periods Thus a machine cycle takes 12 oscil lator periods or 1 ps if the oscillator frequency is 12 MHz Each state is divided into a Phase 1 half and a Phase 2 half Figure 15 shows the fetch execute sequences in 1 P1 P2 54 55 P1 P2 P1 P2 56 2 1 READ NEXT OPCODE AGAIN READ NEXT OPCODE AGAIN READ NEXT OPCODE AGAIN NO FETCH ACCESS EXTERNAL MEMORY 270251 15 Figure 15 State Sequences in 59 51 Devices 1 18 intel states an
127. nly 4 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 intel cycles long and if the instruction in progress is RETI or an access to IE or IP the additional wait time can not be more than 5 cycles a maximum of one more to complete the instruction in progress plus 4 cycles to complete the next instruction if the instruction is DIV Thus in a single interrupt system the response time is always more than 3 cycles and less than 9 cycles SINGLE STEP OPERATION The 8051 interrupt structure allows single step execu tion with very little software overhead As previously noted an interrupt request will not be responded to while an interrupt of equal priority level is still in prog ress nor will it be responded to after RETI until at least one other instruction has been executed Thus once an interrupt routine has been entered it cannot be re entered until at least one instruction of the interrupt ed program is executed One way to use this feature for single stop operation is to program one of the external interrupts say INTO to be level activated The service routine for the interrupt will terminate with the follow ing code JNB P3 2 Here Till INTO Goes High JB P3 Wait Here Till it Goes Low RETI Go Back and Execute One Instruction Now if the INTO pin which is also the P3 2 pin is held normally low the CPU will go right into the External Interrupt 0 routine and stay there
128. now exceed nine 1010xxxx 111xxxx these high order bits are incremented by six producing the proper BCD digit in the high order nibble Again this would set the carry flag if there was a carry out of the high order bits but wouldn t clear the carry The carry flag thus indicates if the sum of the original two BCD variables is greater than 100 allowing multiple precision decimal addition OV is not affected of this occurs during the one instruction cycle Essentially this instruction performs the decimal conversion by adding 06H 60H or 66H to the Accumulator depending on initial Accumulator and PSW conditions Note DA A cannot simply convert a hexadecimal number in the Accumulator to BCD nota tion nor does DA A apply to decimal subtraction 2 39 intel Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET The Accumulator holds the value 56H 01010110B representing the packed BCD digits of the decimal number 56 Register 3 contains the value 67H 01100111B representing the packed BCD digits of the decimal number 67 The carry flag is set The instruction sequence ADDC A R3 DA A will first perform a standard twos complement binary addition resulting in the value OBEH 10111110 in the Accumulator The carry and auxiliary carry flags will be cleared The Decimal Adjust instruction will then alter the Accumulator to the value 24H 00100100 indicating the pack
129. nter is left decremented by two No other registers are affected the PSW is not automatically restored to its pre interrupt status Program execution continues at the resulting address which is generally the instruction immediately after the point at which the interrupt request was detected If a lower or same level interrupt had been pending when the RETI instruction is executed that one instruction will be executed before the pending interrupt is processed Example Stack Pointer originally contains the value OBH An interrupt was detected during the instruction ending at location 0122H Internal RAM locations OAH and OBH contain the values 23H and 01H respectively The instruction RETI will leave the Stack Pointer equal to and return program execution to location 0123H Bytes 1 Cycles 2 Encoding 0011 0010 Operation RETI 15 8 SP SP SP 1 PC7 9 lt SP SP SP 1 2 65 intel Function Description Example Bytes Cycles Encoding Operation RLC A Function Description Example Bytes Cycles Encoding Operation MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Rotate Accumulator Left The eight bits in the Accumulator are rotated one bit to the left Bit 7 is rotated into tbe bit O position No flags are affected The Accumulator holds the value OCSH 11000101B The instruction RL A leaves the Accumulator holding t
130. ogram Entire E um 8051AH 8751H 8751BH 210V 1275V 4minutes eros i275v tions are stopped but the on chip RAM and Special Function Registers are held The port pins output the Program Memory LOCKS values held by their respective SFRs ALE and PSEN some microcontroller applications it is desirable that output lows the Program Memory be secure from software piracy Intel has responded to this need by implementing a The only exit from Power Down for the 80C51 is a Program Memory locking scheme in some of the MCS hardware reset Reset redefines all the SFRs but does 51 devices While it is impossible for anyone to guaran not change the on chip RAM tee absolute security against all levels of technological sophistication the Program Memory locks in the MCS In the Power Down mode of operation VCC can be 51 devices will present a substantial barrier against ille reduced to as low as 2V Care must be taken however gal readout of protected software to ensure that VCC is not reduced before the Power Down mode is invoked and that VCC is restored to its normal operating level before Power Down mode is One Lock Bit Scheme on 8751H terminated The reset that terminates Power Down also frees the oscillator The reset should not be activated The 8751H contams s lock bit which once pro before VCC is restored to its normal operating level grammed denies electrical a
131. om 25 to 125 nsec The AC Timings section of the data sheets do not refer ence any timing to the XTAL waveform Rather they relate the critical edges of control and input signals to each other The timings published in the data sheets include the effects of propagation delays under the specified test conditions intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 aya STATE 2 STATE 3 STATE 4 STATE 1 STATE 2 1 p2 P1 2 2 1 2 2 p 2 2 p 2 270252 29 Figure 36 External Program Memory Fetches STATE 6 DUE STATE 4 STATE 5 P1 P2 p1 2 1 22 1 2 1 2 2 pi 2 P2 OR OR B Figure 37 External Data Memory Read Cycle 270252 30 3 34 intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 STATE 5 6 STATE 3 Wapsi 1 P2 P1 2 p1 P2 1 p2 p1 P2 2 1 2 2 270252 31 Figure 38 External Data Memory Write Cycle STATE 5 STATE 6 STATE 1 STATE 2 STATE 3 STATE 4 STATE 5 2 2 2 2 1 2 1 2 1 2 1 2 P1 P2 P3 P1 P2 INPUTS SAMPLED RST RST MOV PORT SRC OLD DATA NEW DATA MODE 0 Figure 39 Port Operation 270252 32 3 35 intel HARDWARE DESCRIPTION OF THE 8051 8
132. only As a Counter Table 8 INTERNAL EXTERNAL CONTROL CONTROL NOTE 1 NOTE 2 16 bit Auto Reload 02H OAH 16 bit Capture 03H 5 1 Capture Reload occurs only on Timer Counter overflow 2 Capture Reload occurs on Timer Counter overflow and a 1 to 0 transition on T2EX P1 1 pin except when Timer 2 is used in the baud rate generating mode 2 18 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SCON SERIAL PORT CONTROL REGISTER BIT ADDRESSABLE sm sm2 ren mae m m SMO SCON 7 Serial Port mode specifier NOTE 1 SM1 SCON 6 Serial Port mode specifier NOTE 1 SM2 SCON 5 Enables the multiprocessor communication feature in modes 2 amp 3 In mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In mode 1 if SM2 1 then RI will not be activated if a valid stop bit was not received In mode 0 SM2 should be 0 See Table 9 REN 5 4 Set Cleared by software to Enable Disable reception 8 SCON 3 9th bit that will transmitted modes 2 amp 3 Set Cleared software RB8 SCON 2 In modes 2 amp 3 is the 9th data bit that was received In mode 1 if SM2 0 RB8 is the stop bit that was received In mode 0 RB8 is not used TI SCON 1 Transmit interrupt flag Set by hardware at the end of the 8th bit time in mode O or at the beginning of the stop bit in the other modes Must be cl
133. ory as the first byte of the instruction following AJMP Example label is at program memory location 0123H The instruction JMPADR is at location 0345H and will load the PC with 0123H Bytes 2 Cycles 2 Encoding 10 0001 a7 a5 a4 a2 a1 Operation AJMP PC PC 2 page address ANL lt dest byte gt lt src byte gt Function Logical AND for byte variables Description ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable No flags are affected The two operands allow six addressing mode combinations When the destination is the Accu mulator the source can use register direct register indirect or immediate addressing when the destination is a direct address the source can be the Accumulator or immediate data Note When this instruction is used to modify an output port the value used as the original port data will be read from the output data latch not the input pins Example Ifthe Accumulator holds 11000011B and register 0 holds 55H 01010101B then the instruction ANL A RO will leave 41H 01000001B in the Accumulator When the destination is a directly addressed byte this instruction will clear combinations of bits in any RAM location or hardware register The mask byte determining the pattern of bits to be cleared would either be
134. ounter Control Register MODE 2 Mode 2 configures the Timer register as an 8 bit Coun ter TL1 with automatic reload as shown in Figure 9 Overflow from TL1 not only sets TF1 but also reloads with the contents of which is preset by soft ware The reload leaves TH1 unchanged Mode 2 operation is the same for Timer Counter 0 MODE 3 Timer 1 in Mode 3 simply holds its count The effect is the same as setting TR1 0 3 11 Timer 0 in Mode 3 establishes TLO and THO as two separate counters The logic for Mode 3 on Timer 0 is shown in Figure 10 TLO uses the Timer 0 control bits C T GATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications requiring an extra 8 bit timer or counter With Timer O in Mode 3 an 8051 can look like it has three Timer Counters and an 8052 like it has four When Timer O is in Mode 3 Timer 1 can be turned on and off by switching it out of and into its own Mode 3 or can still be used by the serial port as a baud rate generator or in fact in any application not requiring an interrupt intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 INTERRUPT 270252 10 Figure 9 Timer Counter 1 Mode 2 8 Bit Auto Reload 1 121osc INTERRUPT CONTROL INTERRUPT 270252 11 Figure 10 Timer Counter 0 Mode
135. out of bit 7 or a carry out of bit 7 but not bit 6 otherwise OV is cleared When adding signed integers OV indicates a negative number pro duced as the sum of two positive operands or a positive sum from two negative operands Four source operand addressing modes are allowed register direct register indirect or imme diate The Accumulator holds 0C3H 11000011B and register 0 holds 10101010B The instruction ADD A R0 will leave 6DH 01101101B in the Accumulator with the AC flag cleared and both the carry flag and OV set to 1 1 1 52191111 ADD lt Rn 2 1 0010 lt direct direct address 2 29 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET ADD A Ri Bytes 1 Cycles 1 Operation ADD A RD ADD A data Bytes 2 Cycles 1 Encoding 0010 0100 Operation ADD A A data ADDC A lt sre byte gt Function Add with Carry Description ADDC simultaneously adds the byte variable indicated the carry flag and the Accumulator contents leaving the result in the Accumulator The carry and auxiliary carry flags are set respectively if there is a carry out from bit 7 or bit 3 and cleared otherwise When adding unsigned integers the carry flag indicates an overflow occured OV is set if there is a carry out of bit 6 but not out of bit 7 or a carry out of bit 7 but not out of bit 6 oth
136. ove the tens digit to the high nibble of the Accumulator and the ones digit to the low nibble Data Transfers INTERNAL RAM Table 4 shows the menu of instructions that are avail able for moving data around within the internal memo ry spaces and the addressing modes that can be used with each one With a 12 MHz clock all of these in structions execute in either 1 or 2 ps The MOV lt dest gt src instruction allows data to be transferred between any two internal RAM or SFR locations without going through the Accumulator Re member the Upper 128 byes of data RAM can be ac cessed only by indirect addressing and SFR space only by direct addressing Note that in all MCS 51 devices the stack resides in on chip RAM and grows upwards The PUSH instruc tion first increments the Stack Pointer SP then copies the byte into the stack PUSH and POP use only direct addressing to identify the byte being saved or restored Table 4 A List of the 51 Data Transfer Instructions that Access Internal Data Memory Space MOV det A lt de gt a x 16 bit immediateconstant x 2 gt x PP umb ese neo x 12 ACCand Riexchangelownibbles x 1 1 12 Addressing Modes Execution X X gt j ntel MCS 51 ARCHITECTURAL OVERVIEW but the stack itself is accessed by indirect addressing using
137. r bit fields of the Accumulator bits 3 0 and bits 7 4 The operation can also be thought of as a four bit rotate instruction No flags are affected The Accumulator holds the value 5 11000101B The instruction SWAP A leaves the Accumulator holding the value 5 01011100B 1 1 1 SWAP 3 0 A74 2 71 intel 5 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XCH A lt byte gt Function Description Example Bytes Cycles Encoding Operation XCH A direct Bytes Cycles Encoding Operation XCH A Ri Bytes Cycles Encoding Operation Exchange Accumulator with byte variable XCH loads the Accumulator with the contents of the indicated variable at the same time writing the original Accumulator contents to the indicated variable The source destination operand can use register direct or register indirect addressing RO contains the address 20H The Accumulator holds the value 3FH 00111111B Internal RAM location 20H holds the value 75H 01110101B The instruction XCH A GRO will leave RAM location 20H holding the values 3FH 00111111B and 75H 01110101B in the accumulator 1 1 XCH Rn 2 1 XCH A direct 1 1 XCH A Ri 2 72 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET XCHD A Ri Function Exchange Digit Description XCHD exchanges the low order nibble of the
138. r the carry and cause program execution to continue at the instruction identified by the label LABEL2 2 2 JNC lt 2 IF 0 THEN PC lt PC rel 2 49 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET JNZ rel Function Description Example Bytes Cycles Encoding Operation JZ Jump if Accumulator Not Zero If any bit of the Accumulator is a one branch to the indicated address otherwise proceed with the next instruction The branch destination is computed by adding the signed relative dis placement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally holds 00H The instruction sequence JNZ LABELI INC A JNZ LABEL2 will set the Accumulator to 01H and continue at label LABEL2 2 2 0111 0000 JNZ PC lt PC 2 IF 0 address rel Function Description Example Bytes Cycles Encoding Operation Jump if Accumulator Zero If all bits of the Accumulator are zero branch to the address indicated otherwise proceed with the next instruction The branch destination is computed by adding the signed relative dis placement in the second instruction byte to the PC after incrementing the PC twice The Accumulator is not modified No flags are affected The Accumulator originally contain
139. ram in Figure 5 Table 1 Accumulator B Register Program Status Word Stack Pointer Data Pointer 2 Bytes Low Byte High Byte Port 0 Port 1 Port 2 Port3 Interrupt Priority Control Interrupt Enable Control Timer Counter Mode Control Timer Counter Control Timer Counter 2 Control Timer Counter 0 High Byte Timer Counter 0 Low Byte Timer Counter 1 High Byte Timer Counter 1 Low Byte Timer Counter 2 High Byte Timer Counter 2 Low Byte T C 2 Capture Reg High Byte T C 2 Capture Reg Low Byte Serial Control Serial Data Buffer Power Control Bit addressable 8052 only intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET WHAT DO THE SFRs CONTAIN JUST AFTER POWER ON OR A RESET Table 2 lists the contents of each SFR after power on or a hardware reset Table 2 Contents of the SFRs after reset Register Value in Binary 00000000 00000000 00000000 000001 11 00000000 00000000 11111111 11111111 11111111 11111111 8051 XXX00000 8052 XX000000 8051 0 00000 8052 0X000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 indeterminate HMOS OXXXXXXX CHMOS 0XXX0000 X Undefined Bit Addressable 8052 only intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET SFR MEMORY MAP ScoN j EINE NEN NEDAE C _ 7 TCON TH
140. ransition on INTO P3 2 when TRO 1 hardware control 2 15 intel 51 PROGRAMMER S GUIDE AND INSTRUCTION SET TIMER COUNTER 1 Asa Counter NOTES Table 5 TIMER 1 FUNCTION INTERNAL CONTROL NOTE 1 13 bit Timer 16 bit Timer 8 bit Auto Reload does not run Table 6 COUNTER 1 FUNCTION INTERNAL CONTROL 13 bit Timer 16 bit Timer 8 bit Auto Reload not available EXTERNAL CONTROL NOTE 2 EXTERNAL CONTROL NOTE 2 1 The Timer is turned ON OFF by setting clearing bit TR1 in the software 2 The Timer is turned ON OFF by the 1 to 0 transition 1 P3 3 when TR1 1 hardware control 2 16 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET T2CON TIMER COUNTER 2 CONTROL REGISTER BIT ADDRESSABLE 8052 Only TF2 EXF2 RCLK TLCK EXEN2 C T2 CP RL2 T2CON 7 T2CON 6 T2CON 5 T2CON 4 T2CON 3 T2CON 2 T2CON 1 T2CON 0 Timer 2 overflow flag set by hardware and cleared by software TF2 cannot be set when either 1 CLK 1 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 1 When Timer 2 interrupt is enabled EXF2 1 will cause the CPU to vector to the Timer 2 interrupt routine EXF2 must be cleared by software Receive clock flag When set causes the Serial Port to use Timer 2 overflow pulses for its receive clock in modes
141. ry flag if and only if P1 0 1 ACC 7 1 and 0 MOV 1 0 LOAD CARRY WITH INPUT PIN STATE ANL 7 AND CARRY WITH ACCUM 7 ANL C OV AND WITH INVERSE OF OVERFLOW FLAG ANL Bytes 2 Cycles 2 Encoding bit address Operation ANL C A bit ANL C bit Bytes Cycles 2 Encoding Operation ANL lt Q A 1 bit intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET CJNE lt dest byte gt lt src byte gt rel Function Description Example CJNE A direct rel Bytes Cycles Encoding Operation Compare and Jump if Not Equal CJNE compares the magnitudes of the first two operands and branches if their values are not equal The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC after incrementing the PC to the start of the next instruction The carry flag is set if the unsigned integer value of lt dest byte gt is less than the unsigned integer value of lt src byte gt otherwise the carry is cleared Neither operand is affected The first two operands allow four addressing mode combinations the Accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared with an immediate constant The Accumulator contains 34H Register 7 contains 56H The first instruction in the se quence rev ee des R7 60H NOT EQ
142. s activated It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly ROM PROTECTION The 8051AHP and 80C51BHP are ROM Protected versions of the 8051AH and 80C51BH respectively To incorporate this Protection Feature program verifica tion has been disabled and external memory accesses have been limited to 4K Refer to the data sheets on these parts for more information ONCETM Mode The ONCE on circuit emulation mode facilitates testing and debugging of systems using the device with out the device having to be removed from the circuit The ONCE mode is invoked by 1 Pull ALE low while the device is in reset and PSEN is high 2 Hold ALE low as RST is deactivated While the device is in ONCE mode the Port 0 pins go into a float state and the other port pins and ALE and PSEN are weakly pulled high The oscillator circuit remains active While the device is in this mode an emulator or test CPU can be used to drive the circuit Normal operation is restored after a normal reset is applied THE ON CHIP OSCILLATORS HMOS Versions The on chip oscillator circuitry for the HMOS HMOS I and HMOS II members of the MCS 51 fam ily is a single stage linear inverter Figure 29 intended for use as a crystal controlled positive reactance oscil lator Figure 30 In this application the crystal is oper ated in its fundamental response mode
143. s 01H The instruction sequence JZ LABELI DEC A JZ LABEL2 will change the Accumulator to and cause program execution to continue at the instruc tion identified by the label LABEL2 2 2 2110 5000 JZ PC lt PO 2 IF A 0 THEN PO PO rel 2 50 intel LCALL addr16 MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Function Long call Description LCALL calls a subroutine located at the indicated address The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16 bit result onto the stack low byte first incrementing the Stack Pointer by two The high order and low order bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 64K byte program memory address space No flags are affected Example Initially the Stack Pointer equals 07H The label SUBRTN is assigned to program memory location 1234H After executing the instruction LCALL SUBRTN at location 0123H the Stack Pointer will contain 09H internal RAM locations 08H and 09H will contain 26H and 01H and the PC will contain 1234H Bytes 3 Cycles 2 Encoding 0001 0010 addr15 addr8 addr7 addr0 Operation LCALL PO 3 SP SP 1 SP lt PC7 9 SP SP 1 SP 5
144. s the transistor that is turned on for 2 oscillator periods after O to 1 transition in the port latch While it s on it turns on pFET3 a weak pull up through the inverter This inverter and pFET form a latch which hold the 1 Note that if the pin is emitting a 1 a negative glitch on the pin from some external source can turn off pFET3 causing the pin to go into a float state pFET2 is a very weak pullup which is on whenever the nFET is off in traditional CMOS style It s only about the strength of pFET3 Its function is to restore a to the pin in the event the pin had a 1 and lost it to a glitch Port Loading and Interfacing The output buffers of Ports 1 2 and 3 can each drive 4 LS TTL inputs These ports on HMOS versions can be driven in a normal manner by any TTL or NMOS cir cuit Both HMOS and CHMOS pins can be driven by open collector and open drain outputs but note that 0 to 1 transitions will not be fast In the HMOS device if the pin is driven by an open collector output 0 to 1 transition will have to be driven by the relatively weak depletion mode FET in Figure 5 A In the CHMOS device an input O turns off pullup pFET3 leaving only the very weak pullup to drive the transition In external bus mode Port 0 output buffers can each drive 8 LS TTL inputs As port pins they require exter nal pullups to drive any inputs intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 Read Modi
145. s to terminate the Idle Activation of any enabled interrupt will cause PCON O to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruc tion to be executed will be the one following the in struction that put the device into Idle 270252 22 Figure 27 Idle and Power Down Hardware 3 28 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 MSB LSB Gro PD o Position PCON 7 Symbol Name and Function Double Baud rate bit When set to a 1 and Timer 1 is used to generate baud rate and the Serial Port is used in modes 1 2 or 3 Reserved Reserved Reserved Generai purpose flag bit General purpose flag bit Power Down bit Setting this bit activates power down operation Idle mode bit Setting this bit activates idle mode operation 1s are written to PD and IDL at the same time PD takes precedence The reset value of PCON is 0XXX0000 In the HMOS devices the PCON register only contains SMOD The other four bits are implemented only in the CHMOS devices User software should never write 13 to unimplemented bits since they may be used in future MCS 51 products PCON 6 PCON 5 PCON 4 PCON 3 PCON 2 PCON 0 Figure 28 PCON Power Control Register The flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal oper ation or during 14 For example an
146. sented in this chapter is collected from the MCS 51 Architectural Overview and the Hardware Description of the 8051 8052 and 80C51 chapters of this book The material has been selected and rearranged to form a quick and convenient reference for the programmers of the MCS 51 This guide pertains specifically to the 8051 8052 and 80C51 MEMORY ORGANIZATION PROGRAM MEMORY The 8051 has separate address spaces for Program Memory and Data Memory The Program Memory can be up to 64K bytes long The lower 4K 8K for the 8052 may reside on chip Figure 1 shows a map of the 8051 program memory and Figure 2 shows a map of the 8052 program memory 270249 1 Figure 1 The 8051 Program Memory intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 270249 2 Figure 2 The 8052 Program Memory Data Memory The 8051 can address up to 64K bytes of Data Memory external to the chip The MOVX instruction is used to access the external data memory Refer to the MCS 51 Instruction Set in this chapter for detailed description of instructions The 8051 has 128 bytes of on chip RAM 256 bytes in the 8052 plus a number of Special Function Registers SFRs The lower 128 bytes of RAM can be accessed either by direct addressing MOV data addr or by indirect addressing MOV Ri Figure 3 shows the 8051 and the 8052 Data Memory organization 2 4 intel MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET 270249 3 Figure 3a The 8051
147. ss versions have EA wired low to enable the lower 4K 8K for the 8032 program bytes to be fetched from external memory When the CPU is executing out of external Program Memory all 8 bits of Port 2 are dedicated to an output function and may not be used for general purpose I O During external program fetches they output the high byte of the PC During this time the Port 2 drivers use the strong pullups to emit PC bits that are 1s TIMER COUNTERS The 8051 has two 16 bit Timer Counter registers Tim er 0 and Timer 1 The 8052 has these two plus one intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 more Timer 2 All three be configured to operate either as timers or event counters In the Timer function the register is incremented every machine cycle Thus one can think of it as count ing machine cycles Since a machine cycle consists of 12 oscillator periods the count rate is 1 of the oscillator frequency In the Counter function the register is incremented in response to a 1 10 0 transition at its corresponding external input pin TO T1 or in the 8052 T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incre mented The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected Since it takes 2 machine cycles 2
148. sts of the same priori ty level The IP register contains a number of unimplemented bits IP 7 and IP 6 are vacant in the 8052s and in the 8051s these and IP 5 are vacant User software should not write 1s to these bit positions since they may be used in future MCS 51 products How Interrupts Are The interrupt flags are sampled at S5P2 of every ma chine cycle The samples are polled during the follow ing machine cycle The 8052 s Timer 2 interrupt cycle is different as described in the Response Time Section If one of the flags was in a set condition at S5P2 of the preceding cycle the polling cycle will find it and the interrupt system will generate an LCALL to the appro priate service routine provided this hardware generat ed LCALL is not blocked by any of the following con IP 5 Timer 2 interrupt priority bit Serial Port interrupt priority bit Timer 1 interrupt priority bit IP 4 IP 3 IP 2 External interrupt 1 priority bit IP 1 Timer 0 interrupt priority bit IP 0 External interrupt O priority bit User software should never write 1s to unimplemented bits since they may be used in future MCS 51 products Figure 23 IP Interrupt Priority Register If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are re INTERRUPTS ARE POLLED INTERRUPT INTERRUPT GOES LATCHED ACTIVE
149. t is the value that was sampled at the P3 0 pin at S5P2 of the same machine cycle As data bits come in from the right 1s shift out to the left When the 0 that was initially loaded into the right most position arrives at the leftmost position in the shift register it flags the RX Control block to do one last Shift and load SBUF At SIP1 of the 10th machine cycle after the write to SCON that cleared RI RE CEIVE is cleared and RI is set More About Mode 1 Ten bits are transmitted through TXD or received through RXD a start bit 0 8 data bits LSB first and a stop bit 1 On receive the stop bit goes into RB SCON In the 8051 the baud rate is determined by the Timer 1 overflow rate In the 8052 it is deter mined either by the Timer 1 overflow rate or the Timer 2 overflow rate or both one for transmit and the other for receive Figure 18 shows a simplified functional diagram of the seria port in Mode 1 and associated timings for trans mit receive intel HARDWARE DESCRIPTION OF THE 8051 8052 80 51 RXD P3 0 ALT OUTPUT FUNCTION TXD P3 1 ALT OUTPUT FUNCTION RXCLOCK RI RECEIVE START 441111110 RXD P3 0 ALT INPUT FUNCTION 8051 INTERNAL BUS 333253 54 2002 523304 9690 6 323334 96 00 e s musa 3182833433 96 828254 96 96 ALE WRITE senn 3672 SHIFT Our 2 6 TRANSMIT RX
150. t or not the unit goes back to looking for a 1 to O transition at the RXD input Note that the value of the received stop bit is irrelevant to SBUF RB8 or RI INTERRUPTS The 8051 provides 5 interrupt sources The 8052 pro vides 6 These are shown in Figure 21 The External Interrupts INTO and INTI can each be either level activated or transition activated depending on bits ITO and IT1 in Register TCON The flags that actually generate these interrupts are bits and in TCON When an external interrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt 270252 19 Figure 21 MCS 51 Interrupt Sources was transition activated If the interrupt was level acti vated then the external requesting source is what con trols the request flag rather than the on chip hardware The Timer 0 and Timer 1 Interrupts are generated by and TF1 which are set by a rollover in their re spective Timer Counter registers except see Timer O in Mode 3 When a timer interrupt is generated the flag that generated it is cleared by the on chip hardware when the service routine is vectored to The Serial Port Interrupt is generated by the logical OR of RI and TI Neither of these flags is cleared by hard ware when the service routine is vectored to In fact the service routine will normally have to determine whether it was RI or TI that generated the
151. the SP register This means the stack can go into the Upper 128 if they are implemented but not into SFR space In devices that do not implement the Upper 128 if the SP points to the Upper 128 PUSHed bytes are lost and POPped bytes are indeterminate The Data Transfer instructions include 16 bit MOV that can be used to initialize the Data Pointer DPTR for look up tables in Program Memory or for 16 bit external Data Memory accesses The A byte instruction causes the Accumu lator and addressed byte to exchange data The XCHD A GRi instruction is similar but only the low nibbles are involved in the exchange To see how XCH and XCHD can be used to facilitate data manipulations consider first the problem of shift ing an 8 digit BCD number two digits to the right Fig ure 11 shows how this can be done using direct MOVs and for comparison how it can be done using XCH instructions To aid in understanding how the code works the contents of the registers that are holding the BCD number and the content of the Accumulator are shown alongside each instruction to indicate their status after the instruction has been executed MOV MOV MOV MOV MOV A 2EH 2EH 2DH 2DH 2CH 2CH 2BH 2BH 0 12 a Using direct MOVs 14 bytes 9 us CLR XCH XCH A A 2BH A 2CH 20 b Using XCHs 9 bytes 5 us Figure 11 Shifting a BCD Number Two Digits to the Right After the routine h
152. theses are resident in the 8052s but not in the 8051s intel HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 EGISTER lt lt 1 i PCON tz acara saur ik INTERRUPT SERIAL PORT AND TIMER BLOCKS INSTRUCTION REGISTER 10 17 270252 1 Figure 1 5 51 Architectural Diagram HARDWARE DESCRIPTION OF THE 8051 8052 AND 80C51 F8 FF FO F7 E8 EF EO E7 08 Do 07 CF co B8 BF 87 AQ A7 98 9F s jJ _ lj T s TMOD 4 THO TH Po SP pH I X PON 8 Figure 2 Indicates Resident 80525 not 80515 Note that not all of the addresses are occupied cupied addresses are not impiemented on the chip Read accesses to these addresses will in general return random data and write accesses will have no effect User software should not write Is to these unimple mented locations since they may be used in future MCS 51 products to invoke new features In that case the reset or inactive values of the new bits will always be 0 and their active values will be 1 The functions of the
153. tion register Re ception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 3 14 Multiprocessor Communications Modes 2 and 3 have a special provision for multipro cessor communications In these modes 9 data bits are received The 9th one goes into RB8 Then comes a stop bit The port can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON A way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an ad dress byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be com ing The slaves that weren t being addressed leave their 25 set and go on about their business ignoring the coming data bytes SM2 has no effect in Mode 0 and in Mode 1 can be used to check the validity of the stop bit In a Mode 1 reception if SM2 1 the receive interrupt
154. tor Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM All mnemonics copyrighted Intel Corporation 1980 intel Mnemonic MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET Table 10 8051 Instruction Set Summary Continued Description Byte Period DATA TRANSFER Continued MOM Ri direct Ri data DPTR data16 A A DPTR A A PC A Ri A DPTR DPTR A direct direct A Rn Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with a 16 bit constant Move Code byte relative to DPTR to Acc Move Code byte relative to PC to Acc Move External RAM 8 bit to Acc Move External RAM 16 bit addr to Acc Move Acc to External RAM 8 bit addr Move Acc to External RAM 16 bit addr Push direct byte onto stack Pop direct byte from Stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low order Digit indirect RAM with Acc Oscillator Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C bit ANL C bit ORL C bit ORL
155. uctions will translate the value in the Accumulator to one of four values defined by the DB define byte directive REL PC MOVC A A PC RET DB 66H DB 7TTH DB 88H DB 99H If the subroutine is called with the Accumulator equal to O1H it will return with 77H in the Accumulator The INC A before the MOVC instruction is needed to get around the RET instruction above the table If several bytes of code separated the MOVC from the table the corresponding number would be added to the Accumulator instead MOVC DPTR Bytes 1 Cycles Encoding Operation MOVC lt A DPTR MOVC A A PC Bytes Cycles 2 Operation MOVC lt 1 PC 2 57 MCS 51 PROGRAMMER S GUIDE AND INSTRUCTION SET intel MOVX lt dest byte gt lt src byte gt Function Description Example Move External The MOVX instructions transfer data between the Accumulator and a byte of external data memory hence the X appended to MOV There are two types of instructions differing in whether they provide an eight bit or sixteen bit indirect address to the external data RAM In the first type the contents of or 1 in the current register bank provide eight bit address multiplexed with data on Eight bits are sufficient for external 1 0 expansion decoding or for a relatively small RAM array For somewhat larger arrays any output port pins can be used to
156. ure 16 Timer 2 in Baud Rate Generator Mode 3 16 intel The baud rate generator mode is similar to the auto re load mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16 bit value in registers RCAP2H and RCAP2L which are preset by software Now the baud rates in Modes 1 and 3 are determined by Timer 2 s overflow rate as follows Timer 2 Overflow Rate 16 The Timer can be configured for either timer or counter operation In the most typical applications it is configured for timer operation C T2 0 Tim er operation is a little different for Timer 2 when it s being used as a baud rate generator Normally as a timer it would increment every machine cycle thus at the oscillator frequency As baud rate generator however it increments every state time thus at 7 the oscillator frequency In that case the baud rate is given by the formula Modes 1 3 Baud Rate Modes 1 3 Baud Rate Oscillator Frequency 32x 65536 RCAP2H RCAP2L where RCAP2H RCAP2L is the content of RCAP2H and RCAP2L taken as a 16 bit unsigned in teger Timer 2 as a baud rate generator is shown in Figure 16 This Figure is valid only if RCLK TCLK 1in T2CON Note that a rollover in TH2 does not set TF2 and will not generate an interrupt Therefore the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode Note too that if EXEN
157. uted the PC contains the address of the RET instruction An entry numbered 0 would be the RET opcode itself Boolean Instructions MCS 51 devices contain a complete Boolean single bit processor The internal RAM contains 128 addressable bits and the SFR space can support up to 128 other addressable bits All of the port lines are bit address able and each one can be treated as a separate single bit port The instructions that access these bits are not just conditional branches but a complete menu of move set clear complement OR and AND instruc tions These kinds of bit operations are not easily ob tained in other architectures with any amount of byte oriented software 5 51 ARCHITECTURAL OVERVIEW Table 7 A List of the MCS 51 Boolean Instructions Mnemonic Operation Tino ue AN C CAND DR 2 ANL C AND NOT bt 2 _ C C ORbt 2 cst C 2 om Joz 1 Mov wc c _____ w o 31 SETB bit C 2 Jump if bit 1 The instruction set for the Boolean processor is shown in Table 7 All bit accesses are by direct addressing Bit addresses 00H through 7FH are in the Lower 128 and bit addresses 80H through FFH are in SFR space CPL C CPL bit JC rel JNC rel JB bit rel J bit rel bit rel p ul IE S 2 __2 EMI 9 NB BC Note how easily an
158. value This will ensure maximum program protection Program Lock Bits Also included in the Program Lock scheme are Lock Bits which can be enabled to provide varying degrees of protection Table 5 lists the Lock Bits and their corresponding effect on the micro controller Refer to Table 6 for the Lock Bits available on the various products Erasing the EPROM also erases the Encryption Array and the Lock Bits returning the part to full functionali ty Table 5 Program Lock Bits and their Features Program Lock Bits Protection Type No program lock features enabled Code verify will still be encrypted by the encryption array if programmed MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory EA is sampled and latched on reset and further programming of the EPROM is disabled Same as 2 also verify is disabled Same as 3 also external execution is disabled P Programmed U Unprogrammed Any other combination of the Lock Bits is not defined Table 6 Program Protection Lock Bits Encrypt Array 87518 LB1 LB2 LB1 LB2 LB1 LB2 LB3 8752BH 87 51 3 30 HARDWARE DESCRIPTION OF THE 8051 8052 AND 80 51 When Lock Bit 1 is programmed the logic level at the EA pin is sampled and latched during reset If the de vice is powered up without a reset the latch initializes to a random value and holds that value until reset i
159. will not be activated unless a valid stop bit is received Serial Port Control Register The serial port control and status register is the Special Function Register SCON shown in Figure 14 This register contains not only the mode selection bits but also the 9th data bit for transmit and receive TB8 and 8 and the serial port interrupt bits TI and RI intel HARDWARE DESCRIPTION OF THE 8051 8052 80 51 270252 13 Figure 13 Timer 2 in Auto Reload Mode MSB LS8 smo Sw sm2 REN n Where 5 SM1 specify the serial port mode as follows SMO SM1 Mode Description Baud Rate O shifttregister 105 12 1 BbtUART variable 2 9 0 UART fosc 64 or 32 3 9 bit UART variable enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then will not be activated if the received 9th data bit RB8 is O In Mode 1 if SM2 1 then Rt will not be activated if a valid stop bit was not received In Mode 0 SM2 should be 0 enables serial reception Set by software to enable reception Clear by software to disable reception TB8 istheSth data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired in Modes 2 and 3 is the 9th data bit that was received In Mode 1 if SM2 0 RB8 is the stop bit that was received In Mode 0 RB8 is not used is transmit interrupt fiag Set by
160. x 256 Modes 1 3 5 One can achieve very low baud rates with Timer 1 by Baud Rate X Timer 1 Overflow Rate leaving the Timer 1 interrupt enabled and configuring the Timer to run as a 16 bit timer high nibble of TMOD 0001B and using the Timer 1 interrupt to The Timer 1 interrupt should be disabled in this appli do a 16 bit software reload cation The Timer itself can be configured for either timer or counter operation and in any of its 3 Figure 15 lists various commonly used baud rates and running modes In the most typical applications it is how they can be obtained from Timer 1 configured for timer operation in the auto reload Baud Rate Reloa ENGEL Mode 0 Max 1 MHZ 12 MHZ X Mode 2 Max 375K 12 MHZ 1 x X Modes 1 3 62 5K 12 MHZ 1 0 2 19 2K 11 059 MHZ 1 0 2 9 6K 11 059 MHZ 0 0 2 4 8K 11 059 MHZ 0 0 2 2 4K 11 059 MHZ 0 0 2 1 2K 11 059 MHZ 0 0 2 137 5 11 986 MHZ 0 0 2 110 6 MHZ 0 0 2 110 12 MHZ 0 0 1 Figure 15 Timer 1 Generated Used Baud Rates Using Timer 2 to Generate Baud Rates 11 Note then the baud rates for transmit and receive can be simultaneously different Setting RCLK and or In the 8052 Timer 2 is selected as the baud rate genera TCLK puts Timer 2 into its baud rate generator mode tor by setting TCLK and or RCLK in Y2CON Figure as shown in Figure 16 NOTE OSC FREQ IS DIVIDED BY 2 NOT 12 270252 14 Fig
161. y setting or clearing a bit in the SFR named IP Interrupt Priority Figure 18 shows the IP register in the 8051 low priority interrupt can be interrupted by a high priority interrupt but not by another low priority inter rupt A high priority interrupt can t be interrupted by any other interrupt source If two interrupt requests of different priority levels are received simultaneously the request of higher priority level is serviced If interrupt requests of the same priori ty level are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence Figure 19 shows for the 8051 how the IE and IP regis ters and the polling sequence work to determine which if any interrupt will be serviced MSB LSB es eri exi Pro exo Priority 1 assigns high priority Priority bit 0 assigns low priority iti Function reserved reserved reserved Seriat Port interrupt priority bit Timer 1 interrupt priority bit External Interrupt 1 priority bit Timer 0 interrupt priority bit External Interrupt 0 priority bit IP 2 IP 1 IP 0 These reserved bits are used in other MCS 51 devices Figure 18 IP Interrupt Priority Register in the 8051 IE REGISTER 1 46 INDIVIDUAL ENABLES DISABLE MCS 51 ARCHITECTURAL OVERVIEW HIGH PRIORITY IP R

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MCS® 51 Microcontroller Family User`s Manual